1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32wbxx_ll_tim.h"
23 #include "stm32wbxx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
36
37 /** @addtogroup TIM_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46 * @{
47 */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
67 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
69 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
71 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
72
73 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
74 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
75
76 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
77 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
78
79 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
80 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
81
82 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
85
86 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
90
91 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
107
108 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
111
112 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
115
116 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
117 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
118
119 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
120 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
121
122 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
123 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
124
125 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
128 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
129
130 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
131 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
132
133 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
134 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
135
136 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
152
153 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
154 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
155
156 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
157 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
158
159 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
160 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
161
162 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
178
179 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
180 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
181
182 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
183 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
184 /**
185 * @}
186 */
187
188
189 /* Private function prototypes -----------------------------------------------*/
190 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
191 * @{
192 */
193 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
199 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
203 /**
204 * @}
205 */
206
207 /* Exported functions --------------------------------------------------------*/
208 /** @addtogroup TIM_LL_Exported_Functions
209 * @{
210 */
211
212 /** @addtogroup TIM_LL_EF_Init
213 * @{
214 */
215
216 /**
217 * @brief Set TIMx registers to their reset values.
218 * @param TIMx Timer instance
219 * @retval An ErrorStatus enumeration value:
220 * - SUCCESS: TIMx registers are de-initialized
221 * - ERROR: invalid TIMx instance
222 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)223 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
224 {
225 ErrorStatus result = SUCCESS;
226
227 /* Check the parameters */
228 assert_param(IS_TIM_INSTANCE(TIMx));
229
230 if (TIMx == TIM1)
231 {
232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
234 }
235 else if (TIMx == TIM2)
236 {
237 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
238 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
239 }
240 #if defined(TIM16)
241 else if (TIMx == TIM16)
242 {
243 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
244 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
245 }
246 #endif
247 #if defined(TIM17)
248 else if (TIMx == TIM17)
249 {
250 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
251 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
252 }
253 #endif
254 else
255 {
256 result = ERROR;
257 }
258
259 return result;
260 }
261
262 /**
263 * @brief Set the fields of the time base unit configuration data structure
264 * to their default values.
265 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
266 * @retval None
267 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)268 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
269 {
270 /* Set the default configuration */
271 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
272 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
273 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
274 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
275 TIM_InitStruct->RepetitionCounter = 0x00000000U;
276 }
277
278 /**
279 * @brief Configure the TIMx time base unit.
280 * @param TIMx Timer Instance
281 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
282 * @retval An ErrorStatus enumeration value:
283 * - SUCCESS: TIMx registers are de-initialized
284 * - ERROR: not applicable
285 */
LL_TIM_Init(TIM_TypeDef * TIMx,LL_TIM_InitTypeDef * TIM_InitStruct)286 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
287 {
288 uint32_t tmpcr1;
289
290 /* Check the parameters */
291 assert_param(IS_TIM_INSTANCE(TIMx));
292 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
293 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
294
295 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
296
297 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
298 {
299 /* Select the Counter Mode */
300 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
301 }
302
303 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
304 {
305 /* Set the clock division */
306 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
307 }
308
309 /* Write to TIMx CR1 */
310 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
311
312 /* Set the Autoreload value */
313 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
314
315 /* Set the Prescaler value */
316 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
317
318 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
319 {
320 /* Set the Repetition Counter value */
321 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
322 }
323
324 /* Generate an update event to reload the Prescaler
325 and the repetition counter value (if applicable) immediately */
326 LL_TIM_GenerateEvent_UPDATE(TIMx);
327
328 return SUCCESS;
329 }
330
331 /**
332 * @brief Set the fields of the TIMx output channel configuration data
333 * structure to their default values.
334 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
335 * @retval None
336 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)337 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
338 {
339 /* Set the default configuration */
340 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
341 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
342 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
343 TIM_OC_InitStruct->CompareValue = 0x00000000U;
344 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
345 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
346 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
347 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
348 }
349
350 /**
351 * @brief Configure the TIMx output channel.
352 * @param TIMx Timer Instance
353 * @param Channel This parameter can be one of the following values:
354 * @arg @ref LL_TIM_CHANNEL_CH1
355 * @arg @ref LL_TIM_CHANNEL_CH2
356 * @arg @ref LL_TIM_CHANNEL_CH3
357 * @arg @ref LL_TIM_CHANNEL_CH4
358 * @arg @ref LL_TIM_CHANNEL_CH5
359 * @arg @ref LL_TIM_CHANNEL_CH6
360 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
361 * @retval An ErrorStatus enumeration value:
362 * - SUCCESS: TIMx output channel is initialized
363 * - ERROR: TIMx output channel is not initialized
364 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)365 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
366 {
367 ErrorStatus result = ERROR;
368
369 switch (Channel)
370 {
371 case LL_TIM_CHANNEL_CH1:
372 result = OC1Config(TIMx, TIM_OC_InitStruct);
373 break;
374 case LL_TIM_CHANNEL_CH2:
375 result = OC2Config(TIMx, TIM_OC_InitStruct);
376 break;
377 case LL_TIM_CHANNEL_CH3:
378 result = OC3Config(TIMx, TIM_OC_InitStruct);
379 break;
380 case LL_TIM_CHANNEL_CH4:
381 result = OC4Config(TIMx, TIM_OC_InitStruct);
382 break;
383 case LL_TIM_CHANNEL_CH5:
384 result = OC5Config(TIMx, TIM_OC_InitStruct);
385 break;
386 case LL_TIM_CHANNEL_CH6:
387 result = OC6Config(TIMx, TIM_OC_InitStruct);
388 break;
389 default:
390 break;
391 }
392
393 return result;
394 }
395
396 /**
397 * @brief Set the fields of the TIMx input channel configuration data
398 * structure to their default values.
399 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
400 * @retval None
401 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)402 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
403 {
404 /* Set the default configuration */
405 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
406 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
407 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
408 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
409 }
410
411 /**
412 * @brief Configure the TIMx input channel.
413 * @param TIMx Timer Instance
414 * @param Channel This parameter can be one of the following values:
415 * @arg @ref LL_TIM_CHANNEL_CH1
416 * @arg @ref LL_TIM_CHANNEL_CH2
417 * @arg @ref LL_TIM_CHANNEL_CH3
418 * @arg @ref LL_TIM_CHANNEL_CH4
419 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
420 * @retval An ErrorStatus enumeration value:
421 * - SUCCESS: TIMx output channel is initialized
422 * - ERROR: TIMx output channel is not initialized
423 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)424 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
425 {
426 ErrorStatus result = ERROR;
427
428 switch (Channel)
429 {
430 case LL_TIM_CHANNEL_CH1:
431 result = IC1Config(TIMx, TIM_IC_InitStruct);
432 break;
433 case LL_TIM_CHANNEL_CH2:
434 result = IC2Config(TIMx, TIM_IC_InitStruct);
435 break;
436 case LL_TIM_CHANNEL_CH3:
437 result = IC3Config(TIMx, TIM_IC_InitStruct);
438 break;
439 case LL_TIM_CHANNEL_CH4:
440 result = IC4Config(TIMx, TIM_IC_InitStruct);
441 break;
442 default:
443 break;
444 }
445
446 return result;
447 }
448
449 /**
450 * @brief Fills each TIM_EncoderInitStruct field with its default value
451 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
452 * @retval None
453 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)454 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
455 {
456 /* Set the default configuration */
457 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
458 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
459 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
460 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
461 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
462 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
463 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
464 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
465 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
466 }
467
468 /**
469 * @brief Configure the encoder interface of the timer instance.
470 * @param TIMx Timer Instance
471 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
472 * @retval An ErrorStatus enumeration value:
473 * - SUCCESS: TIMx registers are de-initialized
474 * - ERROR: not applicable
475 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)476 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
477 {
478 uint32_t tmpccmr1;
479 uint32_t tmpccer;
480
481 /* Check the parameters */
482 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
483 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
484 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
485 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
486 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
487 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
488 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
489 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
490 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
491 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
492
493 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
494 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
495
496 /* Get the TIMx CCMR1 register value */
497 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
498
499 /* Get the TIMx CCER register value */
500 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
501
502 /* Configure TI1 */
503 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
504 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
505 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
506 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
507
508 /* Configure TI2 */
509 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
510 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
511 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
512 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
513
514 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
515 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
516 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
517 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
518 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
519
520 /* Set encoder mode */
521 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
522
523 /* Write to TIMx CCMR1 */
524 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
525
526 /* Write to TIMx CCER */
527 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
528
529 return SUCCESS;
530 }
531
532 /**
533 * @brief Set the fields of the TIMx Hall sensor interface configuration data
534 * structure to their default values.
535 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
536 * @retval None
537 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)538 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
539 {
540 /* Set the default configuration */
541 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
542 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
543 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
544 TIM_HallSensorInitStruct->CommutationDelay = 0U;
545 }
546
547 /**
548 * @brief Configure the Hall sensor interface of the timer instance.
549 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
550 * to the TI1 input channel
551 * @note TIMx slave mode controller is configured in reset mode.
552 Selected internal trigger is TI1F_ED.
553 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
554 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
555 * between 2 changes on the inputs. It gives information about motor speed.
556 * @note Channel 2 is configured in output PWM 2 mode.
557 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
558 * @note OC2REF is selected as trigger output on TRGO.
559 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
560 * when TIMx operates in Hall sensor interface mode.
561 * @param TIMx Timer Instance
562 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
563 * @retval An ErrorStatus enumeration value:
564 * - SUCCESS: TIMx registers are de-initialized
565 * - ERROR: not applicable
566 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)567 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
568 {
569 uint32_t tmpcr2;
570 uint32_t tmpccmr1;
571 uint32_t tmpccer;
572 uint32_t tmpsmcr;
573
574 /* Check the parameters */
575 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
576 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
577 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
578 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
579
580 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
581 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
582
583 /* Get the TIMx CR2 register value */
584 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
585
586 /* Get the TIMx CCMR1 register value */
587 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
588
589 /* Get the TIMx CCER register value */
590 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
591
592 /* Get the TIMx SMCR register value */
593 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
594
595 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
596 tmpcr2 |= TIM_CR2_TI1S;
597
598 /* OC2REF signal is used as trigger output (TRGO) */
599 tmpcr2 |= LL_TIM_TRGO_OC2REF;
600
601 /* Configure the slave mode controller */
602 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
603 tmpsmcr |= LL_TIM_TS_TI1F_ED;
604 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
605
606 /* Configure input channel 1 */
607 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
608 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
609 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
610 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
611
612 /* Configure input channel 2 */
613 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
614 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
615
616 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
617 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
618 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
619 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
620
621 /* Write to TIMx CR2 */
622 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
623
624 /* Write to TIMx SMCR */
625 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
626
627 /* Write to TIMx CCMR1 */
628 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
629
630 /* Write to TIMx CCER */
631 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
632
633 /* Write to TIMx CCR2 */
634 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
635
636 return SUCCESS;
637 }
638
639 /**
640 * @brief Set the fields of the Break and Dead Time configuration data structure
641 * to their default values.
642 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
643 * @retval None
644 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)645 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
646 {
647 /* Set the default configuration */
648 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
649 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
650 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
651 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
652 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
653 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
654 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
655 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
656 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
657 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
658 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
659 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
660 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
661 }
662
663 /**
664 * @brief Configure the Break and Dead Time feature of the timer instance.
665 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
666 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
667 * can be necessary to configure all of them during the first write access to
668 * the TIMx_BDTR register.
669 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
670 * a timer instance provides a break input.
671 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
672 * a timer instance provides a second break input.
673 * @param TIMx Timer Instance
674 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
675 * @retval An ErrorStatus enumeration value:
676 * - SUCCESS: Break and Dead Time is initialized
677 * - ERROR: not applicable
678 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)679 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
680 {
681 uint32_t tmpbdtr = 0;
682
683 /* Check the parameters */
684 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
685 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
686 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
687 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
688 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
689 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
690 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
691
692 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
693 the OSSI State, the dead time value and the Automatic Output Enable Bit */
694
695 /* Set the BDTR bits */
696 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
697 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
698 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
699 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
700 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
701 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
702 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
703 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
704 if (IS_TIM_ADVANCED_INSTANCE(TIMx))
705 {
706 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
707 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
708 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
710 }
711
712 if (IS_TIM_BKIN2_INSTANCE(TIMx))
713 {
714 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
715 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
716 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
717 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
718
719 /* Set the BREAK2 input related BDTR bit-fields */
720 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
721 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
722 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
723 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
724 }
725
726 /* Set TIMx_BDTR */
727 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
728
729 return SUCCESS;
730 }
731 /**
732 * @}
733 */
734
735 /**
736 * @}
737 */
738
739 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
740 * @brief Private functions
741 * @{
742 */
743 /**
744 * @brief Configure the TIMx output channel 1.
745 * @param TIMx Timer Instance
746 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
747 * @retval An ErrorStatus enumeration value:
748 * - SUCCESS: TIMx registers are de-initialized
749 * - ERROR: not applicable
750 */
OC1Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)751 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
752 {
753 uint32_t tmpccmr1;
754 uint32_t tmpccer;
755 uint32_t tmpcr2;
756
757 /* Check the parameters */
758 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
759 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
760 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
761 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
762 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
763 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
764
765 /* Disable the Channel 1: Reset the CC1E Bit */
766 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
767
768 /* Get the TIMx CCER register value */
769 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
770
771 /* Get the TIMx CR2 register value */
772 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
773
774 /* Get the TIMx CCMR1 register value */
775 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
776
777 /* Reset Capture/Compare selection Bits */
778 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
779
780 /* Set the Output Compare Mode */
781 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
782
783 /* Set the Output Compare Polarity */
784 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
785
786 /* Set the Output State */
787 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
788
789 if (IS_TIM_BREAK_INSTANCE(TIMx))
790 {
791 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
792 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
793
794 /* Set the complementary output Polarity */
795 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
796
797 /* Set the complementary output State */
798 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
799
800 /* Set the Output Idle state */
801 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
802
803 /* Set the complementary output Idle state */
804 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
805 }
806
807 /* Write to TIMx CR2 */
808 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
809
810 /* Write to TIMx CCMR1 */
811 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
812
813 /* Set the Capture Compare Register value */
814 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
815
816 /* Write to TIMx CCER */
817 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
818
819 return SUCCESS;
820 }
821
822 /**
823 * @brief Configure the TIMx output channel 2.
824 * @param TIMx Timer Instance
825 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
826 * @retval An ErrorStatus enumeration value:
827 * - SUCCESS: TIMx registers are de-initialized
828 * - ERROR: not applicable
829 */
OC2Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)830 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
831 {
832 uint32_t tmpccmr1;
833 uint32_t tmpccer;
834 uint32_t tmpcr2;
835
836 /* Check the parameters */
837 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
838 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
839 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
840 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
841 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
842 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
843
844 /* Disable the Channel 2: Reset the CC2E Bit */
845 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
846
847 /* Get the TIMx CCER register value */
848 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
849
850 /* Get the TIMx CR2 register value */
851 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
852
853 /* Get the TIMx CCMR1 register value */
854 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
855
856 /* Reset Capture/Compare selection Bits */
857 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
858
859 /* Select the Output Compare Mode */
860 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
861
862 /* Set the Output Compare Polarity */
863 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
864
865 /* Set the Output State */
866 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
867
868 if (IS_TIM_BREAK_INSTANCE(TIMx))
869 {
870 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
871 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
872
873 /* Set the complementary output Polarity */
874 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
875
876 /* Set the complementary output State */
877 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
878
879 /* Set the Output Idle state */
880 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
881
882 /* Set the complementary output Idle state */
883 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
884 }
885
886 /* Write to TIMx CR2 */
887 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
888
889 /* Write to TIMx CCMR1 */
890 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
891
892 /* Set the Capture Compare Register value */
893 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
894
895 /* Write to TIMx CCER */
896 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
897
898 return SUCCESS;
899 }
900
901 /**
902 * @brief Configure the TIMx output channel 3.
903 * @param TIMx Timer Instance
904 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
905 * @retval An ErrorStatus enumeration value:
906 * - SUCCESS: TIMx registers are de-initialized
907 * - ERROR: not applicable
908 */
OC3Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)909 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
910 {
911 uint32_t tmpccmr2;
912 uint32_t tmpccer;
913 uint32_t tmpcr2;
914
915 /* Check the parameters */
916 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
917 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
918 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
919 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
920 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
921 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
922
923 /* Disable the Channel 3: Reset the CC3E Bit */
924 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
925
926 /* Get the TIMx CCER register value */
927 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
928
929 /* Get the TIMx CR2 register value */
930 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
931
932 /* Get the TIMx CCMR2 register value */
933 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
934
935 /* Reset Capture/Compare selection Bits */
936 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
937
938 /* Select the Output Compare Mode */
939 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
940
941 /* Set the Output Compare Polarity */
942 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
943
944 /* Set the Output State */
945 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
946
947 if (IS_TIM_BREAK_INSTANCE(TIMx))
948 {
949 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
950 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
951
952 /* Set the complementary output Polarity */
953 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
954
955 /* Set the complementary output State */
956 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
957
958 /* Set the Output Idle state */
959 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
960
961 /* Set the complementary output Idle state */
962 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
963 }
964
965 /* Write to TIMx CR2 */
966 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
967
968 /* Write to TIMx CCMR2 */
969 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
970
971 /* Set the Capture Compare Register value */
972 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
973
974 /* Write to TIMx CCER */
975 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
976
977 return SUCCESS;
978 }
979
980 /**
981 * @brief Configure the TIMx output channel 4.
982 * @param TIMx Timer Instance
983 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
984 * @retval An ErrorStatus enumeration value:
985 * - SUCCESS: TIMx registers are de-initialized
986 * - ERROR: not applicable
987 */
OC4Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)988 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
989 {
990 uint32_t tmpccmr2;
991 uint32_t tmpccer;
992 uint32_t tmpcr2;
993
994 /* Check the parameters */
995 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
996 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
997 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
998 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
999 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1000 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1001
1002 /* Disable the Channel 4: Reset the CC4E Bit */
1003 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1004
1005 /* Get the TIMx CCER register value */
1006 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1007
1008 /* Get the TIMx CR2 register value */
1009 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1010
1011 /* Get the TIMx CCMR2 register value */
1012 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1013
1014 /* Reset Capture/Compare selection Bits */
1015 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1016
1017 /* Select the Output Compare Mode */
1018 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1019
1020 /* Set the Output Compare Polarity */
1021 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1022
1023 /* Set the Output State */
1024 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1025
1026 if (IS_TIM_BREAK_INSTANCE(TIMx))
1027 {
1028 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1029 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1030
1031 /* Set the Output Idle state */
1032 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1033 }
1034
1035 /* Write to TIMx CR2 */
1036 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1037
1038 /* Write to TIMx CCMR2 */
1039 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1040
1041 /* Set the Capture Compare Register value */
1042 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1043
1044 /* Write to TIMx CCER */
1045 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1046
1047 return SUCCESS;
1048 }
1049
1050 /**
1051 * @brief Configure the TIMx output channel 5.
1052 * @param TIMx Timer Instance
1053 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1054 * @retval An ErrorStatus enumeration value:
1055 * - SUCCESS: TIMx registers are de-initialized
1056 * - ERROR: not applicable
1057 */
OC5Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1058 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1059 {
1060 uint32_t tmpccmr3;
1061 uint32_t tmpccer;
1062
1063 /* Check the parameters */
1064 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1065 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1066 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1067 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1068 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1069 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1070
1071 /* Disable the Channel 5: Reset the CC5E Bit */
1072 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1073
1074 /* Get the TIMx CCER register value */
1075 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1076
1077 /* Get the TIMx CCMR3 register value */
1078 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1079
1080 /* Select the Output Compare Mode */
1081 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1082
1083 /* Set the Output Compare Polarity */
1084 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1085
1086 /* Set the Output State */
1087 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1088
1089 if (IS_TIM_BREAK_INSTANCE(TIMx))
1090 {
1091 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1092 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1093
1094 /* Set the Output Idle state */
1095 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1096
1097 }
1098
1099 /* Write to TIMx CCMR3 */
1100 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1101
1102 /* Set the Capture Compare Register value */
1103 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1104
1105 /* Write to TIMx CCER */
1106 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1107
1108 return SUCCESS;
1109 }
1110
1111 /**
1112 * @brief Configure the TIMx output channel 6.
1113 * @param TIMx Timer Instance
1114 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1115 * @retval An ErrorStatus enumeration value:
1116 * - SUCCESS: TIMx registers are de-initialized
1117 * - ERROR: not applicable
1118 */
OC6Config(TIM_TypeDef * TIMx,LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1119 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1120 {
1121 uint32_t tmpccmr3;
1122 uint32_t tmpccer;
1123
1124 /* Check the parameters */
1125 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1126 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1127 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1128 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1129 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1130 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1131
1132 /* Disable the Channel 5: Reset the CC6E Bit */
1133 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1134
1135 /* Get the TIMx CCER register value */
1136 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1137
1138 /* Get the TIMx CCMR3 register value */
1139 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1140
1141 /* Select the Output Compare Mode */
1142 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1143
1144 /* Set the Output Compare Polarity */
1145 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1146
1147 /* Set the Output State */
1148 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1149
1150 if (IS_TIM_BREAK_INSTANCE(TIMx))
1151 {
1152 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1153 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1154
1155 /* Set the Output Idle state */
1156 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1157 }
1158
1159 /* Write to TIMx CCMR3 */
1160 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1161
1162 /* Set the Capture Compare Register value */
1163 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1164
1165 /* Write to TIMx CCER */
1166 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1167
1168 return SUCCESS;
1169 }
1170
1171 /**
1172 * @brief Configure the TIMx input channel 1.
1173 * @param TIMx Timer Instance
1174 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1175 * @retval An ErrorStatus enumeration value:
1176 * - SUCCESS: TIMx registers are de-initialized
1177 * - ERROR: not applicable
1178 */
IC1Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1179 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1180 {
1181 /* Check the parameters */
1182 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1183 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1184 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1185 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1186 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1187
1188 /* Disable the Channel 1: Reset the CC1E Bit */
1189 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1190
1191 /* Select the Input and set the filter and the prescaler value */
1192 MODIFY_REG(TIMx->CCMR1,
1193 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1194 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1195
1196 /* Select the Polarity and set the CC1E Bit */
1197 MODIFY_REG(TIMx->CCER,
1198 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1199 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1200
1201 return SUCCESS;
1202 }
1203
1204 /**
1205 * @brief Configure the TIMx input channel 2.
1206 * @param TIMx Timer Instance
1207 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1208 * @retval An ErrorStatus enumeration value:
1209 * - SUCCESS: TIMx registers are de-initialized
1210 * - ERROR: not applicable
1211 */
IC2Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1212 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1213 {
1214 /* Check the parameters */
1215 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1216 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1217 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1218 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1219 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1220
1221 /* Disable the Channel 2: Reset the CC2E Bit */
1222 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1223
1224 /* Select the Input and set the filter and the prescaler value */
1225 MODIFY_REG(TIMx->CCMR1,
1226 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1227 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1228
1229 /* Select the Polarity and set the CC2E Bit */
1230 MODIFY_REG(TIMx->CCER,
1231 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1232 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1233
1234 return SUCCESS;
1235 }
1236
1237 /**
1238 * @brief Configure the TIMx input channel 3.
1239 * @param TIMx Timer Instance
1240 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1241 * @retval An ErrorStatus enumeration value:
1242 * - SUCCESS: TIMx registers are de-initialized
1243 * - ERROR: not applicable
1244 */
IC3Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1245 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1246 {
1247 /* Check the parameters */
1248 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1249 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1250 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1251 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1252 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1253
1254 /* Disable the Channel 3: Reset the CC3E Bit */
1255 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1256
1257 /* Select the Input and set the filter and the prescaler value */
1258 MODIFY_REG(TIMx->CCMR2,
1259 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1260 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1261
1262 /* Select the Polarity and set the CC3E Bit */
1263 MODIFY_REG(TIMx->CCER,
1264 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1265 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1266
1267 return SUCCESS;
1268 }
1269
1270 /**
1271 * @brief Configure the TIMx input channel 4.
1272 * @param TIMx Timer Instance
1273 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1274 * @retval An ErrorStatus enumeration value:
1275 * - SUCCESS: TIMx registers are de-initialized
1276 * - ERROR: not applicable
1277 */
IC4Config(TIM_TypeDef * TIMx,LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1278 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1279 {
1280 /* Check the parameters */
1281 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1282 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1283 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1284 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1285 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1286
1287 /* Disable the Channel 4: Reset the CC4E Bit */
1288 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1289
1290 /* Select the Input and set the filter and the prescaler value */
1291 MODIFY_REG(TIMx->CCMR2,
1292 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1293 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1294
1295 /* Select the Polarity and set the CC2E Bit */
1296 MODIFY_REG(TIMx->CCER,
1297 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1298 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1299
1300 return SUCCESS;
1301 }
1302
1303
1304 /**
1305 * @}
1306 */
1307
1308 /**
1309 * @}
1310 */
1311
1312 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
1313
1314 /**
1315 * @}
1316 */
1317
1318 #endif /* USE_FULL_LL_DRIVER */
1319
1320 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1321
