1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32WBxx_LL_CRS_H
22 #define STM32WBxx_LL_CRS_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32wbxx.h"
30
31 /** @addtogroup STM32WBxx_LL_Driver
32 * @{
33 */
34
35 #if defined(CRS)
36
37 /** @defgroup CRS_LL CRS
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
46 * @{
47 */
48
49 /* Defines used for the bit position in the register and perform offsets*/
50 #define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
51 #define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
52 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
53
54
55 /**
56 * @}
57 */
58
59 /* Private macros ------------------------------------------------------------*/
60
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
64 * @{
65 */
66
67 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
68 * @brief Flags defines which can be used with LL_CRS_ReadReg function
69 * @{
70 */
71 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
72 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
73 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
74 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
75 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
76 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
77 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
78 /**
79 * @}
80 */
81
82 /** @defgroup CRS_LL_EC_IT IT Defines
83 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
84 * @{
85 */
86 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
87 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
88 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
89 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
90 /**
91 * @}
92 */
93
94 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
95 * @{
96 */
97 #define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
98 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
99 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
100 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
101 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
102 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
103 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
104 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
105 /**
106 * @}
107 */
108
109 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
110 * @{
111 */
112 #define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal soucre GPIO */
113 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
114 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
115 /**
116 * @}
117 */
118
119 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
120 * @{
121 */
122 #define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
123 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
124 /**
125 * @}
126 */
127
128 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
129 * @{
130 */
131 #define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
132 #define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
133 /**
134 * @}
135 */
136
137 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
138 * @{
139 */
140 /**
141 * @brief Reset value of the RELOAD field
142 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
143 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
144 */
145 #define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
146
147 /**
148 * @brief Reset value of Frequency error limit.
149 */
150 #define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
151
152 /**
153 * @brief Reset value of the HSI48 Calibration field
154 * @note The default value is 32, which corresponds to the middle of the trimming interval.
155 * The trimming step is around 67 kHz between two consecutive TRIM steps.
156 * A higher TRIM value corresponds to a higher output frequency
157 */
158 #define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
159 /**
160 * @}
161 */
162
163 /**
164 * @}
165 */
166
167 /* Exported macro ------------------------------------------------------------*/
168 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
169 * @{
170 */
171
172 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
173 * @{
174 */
175
176 /**
177 * @brief Write a value in CRS register
178 * @param __INSTANCE__ CRS Instance
179 * @param __REG__ Register to be written
180 * @param __VALUE__ Value to be written in the register
181 * @retval None
182 */
183 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
184
185 /**
186 * @brief Read a value in CRS register
187 * @param __INSTANCE__ CRS Instance
188 * @param __REG__ Register to be read
189 * @retval Register value
190 */
191 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
192 /**
193 * @}
194 */
195
196 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
197 * @{
198 */
199
200 /**
201 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
202 * @note The RELOAD value should be selected according to the ratio between
203 * the target frequency and the frequency of the synchronization source after
204 * prescaling. It is then decreased by one in order to reach the expected
205 * synchronization on the zero value. The formula is the following:
206 * RELOAD = (fTARGET / fSYNC) -1
207 * @param __FTARGET__ Target frequency (value in Hz)
208 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
209 * @retval Reload value (in Hz)
210 */
211 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
212
213 /**
214 * @}
215 */
216
217 /**
218 * @}
219 */
220
221 /* Exported functions --------------------------------------------------------*/
222 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
223 * @{
224 */
225
226 /** @defgroup CRS_LL_EF_Configuration Configuration
227 * @{
228 */
229
230 /**
231 * @brief Enable Frequency error counter
232 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
233 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
234 * @retval None
235 */
LL_CRS_EnableFreqErrorCounter(void)236 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
237 {
238 SET_BIT(CRS->CR, CRS_CR_CEN);
239 }
240
241 /**
242 * @brief Disable Frequency error counter
243 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
244 * @retval None
245 */
LL_CRS_DisableFreqErrorCounter(void)246 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
247 {
248 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
249 }
250
251 /**
252 * @brief Check if Frequency error counter is enabled or not
253 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
254 * @retval State of bit (1 or 0).
255 */
LL_CRS_IsEnabledFreqErrorCounter(void)256 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
257 {
258 return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
259 }
260
261 /**
262 * @brief Enable Automatic trimming counter
263 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
264 * @retval None
265 */
LL_CRS_EnableAutoTrimming(void)266 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
267 {
268 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
269 }
270
271 /**
272 * @brief Disable Automatic trimming counter
273 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
274 * @retval None
275 */
LL_CRS_DisableAutoTrimming(void)276 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
277 {
278 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
279 }
280
281 /**
282 * @brief Check if Automatic trimming is enabled or not
283 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
284 * @retval State of bit (1 or 0).
285 */
LL_CRS_IsEnabledAutoTrimming(void)286 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
287 {
288 return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
289 }
290
291 /**
292 * @brief Set HSI48 oscillator smooth trimming
293 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
294 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
295 * @param Value a number between Min_Data = 0 and Max_Data = 63
296 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
297 * @retval None
298 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)299 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
300 {
301 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
302 }
303
304 /**
305 * @brief Get HSI48 oscillator smooth trimming
306 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
307 * @retval a number between Min_Data = 0 and Max_Data = 63
308 */
LL_CRS_GetHSI48SmoothTrimming(void)309 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
310 {
311 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
312 }
313
314 /**
315 * @brief Set counter reload value
316 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
317 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
318 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
319 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
320 * @retval None
321 */
LL_CRS_SetReloadCounter(uint32_t Value)322 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
323 {
324 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
325 }
326
327 /**
328 * @brief Get counter reload value
329 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
330 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
331 */
LL_CRS_GetReloadCounter(void)332 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
333 {
334 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
335 }
336
337 /**
338 * @brief Set frequency error limit
339 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
340 * @param Value a number between Min_Data = 0 and Max_Data = 255
341 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
342 * @retval None
343 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)344 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
345 {
346 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
347 }
348
349 /**
350 * @brief Get frequency error limit
351 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
352 * @retval A number between Min_Data = 0 and Max_Data = 255
353 */
LL_CRS_GetFreqErrorLimit(void)354 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
355 {
356 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
357 }
358
359 /**
360 * @brief Set division factor for SYNC signal
361 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
362 * @param Divider This parameter can be one of the following values:
363 * @arg @ref LL_CRS_SYNC_DIV_1
364 * @arg @ref LL_CRS_SYNC_DIV_2
365 * @arg @ref LL_CRS_SYNC_DIV_4
366 * @arg @ref LL_CRS_SYNC_DIV_8
367 * @arg @ref LL_CRS_SYNC_DIV_16
368 * @arg @ref LL_CRS_SYNC_DIV_32
369 * @arg @ref LL_CRS_SYNC_DIV_64
370 * @arg @ref LL_CRS_SYNC_DIV_128
371 * @retval None
372 */
LL_CRS_SetSyncDivider(uint32_t Divider)373 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
374 {
375 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
376 }
377
378 /**
379 * @brief Get division factor for SYNC signal
380 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
381 * @retval Returned value can be one of the following values:
382 * @arg @ref LL_CRS_SYNC_DIV_1
383 * @arg @ref LL_CRS_SYNC_DIV_2
384 * @arg @ref LL_CRS_SYNC_DIV_4
385 * @arg @ref LL_CRS_SYNC_DIV_8
386 * @arg @ref LL_CRS_SYNC_DIV_16
387 * @arg @ref LL_CRS_SYNC_DIV_32
388 * @arg @ref LL_CRS_SYNC_DIV_64
389 * @arg @ref LL_CRS_SYNC_DIV_128
390 */
LL_CRS_GetSyncDivider(void)391 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
392 {
393 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
394 }
395
396 /**
397 * @brief Set SYNC signal source
398 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
399 * @param Source This parameter can be one of the following values:
400 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
401 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
402 * @arg @ref LL_CRS_SYNC_SOURCE_USB
403 * @retval None
404 */
LL_CRS_SetSyncSignalSource(uint32_t Source)405 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
406 {
407 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
408 }
409
410 /**
411 * @brief Get SYNC signal source
412 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
413 * @retval Returned value can be one of the following values:
414 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
415 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
416 * @arg @ref LL_CRS_SYNC_SOURCE_USB
417 */
LL_CRS_GetSyncSignalSource(void)418 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
419 {
420 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
421 }
422
423 /**
424 * @brief Set input polarity for the SYNC signal source
425 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
426 * @param Polarity This parameter can be one of the following values:
427 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
428 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
429 * @retval None
430 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)431 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
432 {
433 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
434 }
435
436 /**
437 * @brief Get input polarity for the SYNC signal source
438 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
439 * @retval Returned value can be one of the following values:
440 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
441 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
442 */
LL_CRS_GetSyncPolarity(void)443 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
444 {
445 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
446 }
447
448 /**
449 * @brief Configure CRS for the synchronization
450 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
451 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
452 * CFGR FELIM LL_CRS_ConfigSynchronization\n
453 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
454 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
455 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
456 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
457 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
458 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
459 * @param Settings This parameter can be a combination of the following values:
460 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
461 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
462 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
463 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
464 * @retval None
465 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)466 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
467 {
468 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
469 MODIFY_REG(CRS->CFGR,
470 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
471 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
472 }
473
474 /**
475 * @}
476 */
477
478 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
479 * @{
480 */
481
482 /**
483 * @brief Generate software SYNC event
484 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
485 * @retval None
486 */
LL_CRS_GenerateEvent_SWSYNC(void)487 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
488 {
489 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
490 }
491
492 /**
493 * @brief Get the frequency error direction latched in the time of the last
494 * SYNC event
495 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
496 * @retval Returned value can be one of the following values:
497 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
498 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
499 */
LL_CRS_GetFreqErrorDirection(void)500 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
501 {
502 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
503 }
504
505 /**
506 * @brief Get the frequency error counter value latched in the time of the last SYNC event
507 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
508 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
509 */
LL_CRS_GetFreqErrorCapture(void)510 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
511 {
512 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
513 }
514
515 /**
516 * @}
517 */
518
519 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
520 * @{
521 */
522
523 /**
524 * @brief Check if SYNC event OK signal occurred or not
525 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
526 * @retval State of bit (1 or 0).
527 */
LL_CRS_IsActiveFlag_SYNCOK(void)528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
529 {
530 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
531 }
532
533 /**
534 * @brief Check if SYNC warning signal occurred or not
535 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
536 * @retval State of bit (1 or 0).
537 */
LL_CRS_IsActiveFlag_SYNCWARN(void)538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
539 {
540 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Check if Synchronization or trimming error signal occurred or not
545 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
546 * @retval State of bit (1 or 0).
547 */
LL_CRS_IsActiveFlag_ERR(void)548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
549 {
550 return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Check if Expected SYNC signal occurred or not
555 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
556 * @retval State of bit (1 or 0).
557 */
LL_CRS_IsActiveFlag_ESYNC(void)558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
559 {
560 return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if SYNC error signal occurred or not
565 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
566 * @retval State of bit (1 or 0).
567 */
LL_CRS_IsActiveFlag_SYNCERR(void)568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
569 {
570 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if SYNC missed error signal occurred or not
575 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
576 * @retval State of bit (1 or 0).
577 */
LL_CRS_IsActiveFlag_SYNCMISS(void)578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
579 {
580 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Check if Trimming overflow or underflow occurred or not
585 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
586 * @retval State of bit (1 or 0).
587 */
LL_CRS_IsActiveFlag_TRIMOVF(void)588 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
589 {
590 return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Clear the SYNC event OK flag
595 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
596 * @retval None
597 */
LL_CRS_ClearFlag_SYNCOK(void)598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
599 {
600 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
601 }
602
603 /**
604 * @brief Clear the SYNC warning flag
605 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
606 * @retval None
607 */
LL_CRS_ClearFlag_SYNCWARN(void)608 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
609 {
610 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
611 }
612
613 /**
614 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
615 * the ERR flag
616 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
617 * @retval None
618 */
LL_CRS_ClearFlag_ERR(void)619 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
620 {
621 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
622 }
623
624 /**
625 * @brief Clear Expected SYNC flag
626 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
627 * @retval None
628 */
LL_CRS_ClearFlag_ESYNC(void)629 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
630 {
631 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
632 }
633
634 /**
635 * @}
636 */
637
638 /** @defgroup CRS_LL_EF_IT_Management IT_Management
639 * @{
640 */
641
642 /**
643 * @brief Enable SYNC event OK interrupt
644 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
645 * @retval None
646 */
LL_CRS_EnableIT_SYNCOK(void)647 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
648 {
649 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
650 }
651
652 /**
653 * @brief Disable SYNC event OK interrupt
654 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
655 * @retval None
656 */
LL_CRS_DisableIT_SYNCOK(void)657 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
658 {
659 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
660 }
661
662 /**
663 * @brief Check if SYNC event OK interrupt is enabled or not
664 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
665 * @retval State of bit (1 or 0).
666 */
LL_CRS_IsEnabledIT_SYNCOK(void)667 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
668 {
669 return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Enable SYNC warning interrupt
674 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
675 * @retval None
676 */
LL_CRS_EnableIT_SYNCWARN(void)677 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
678 {
679 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
680 }
681
682 /**
683 * @brief Disable SYNC warning interrupt
684 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
685 * @retval None
686 */
LL_CRS_DisableIT_SYNCWARN(void)687 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
688 {
689 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
690 }
691
692 /**
693 * @brief Check if SYNC warning interrupt is enabled or not
694 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
695 * @retval State of bit (1 or 0).
696 */
LL_CRS_IsEnabledIT_SYNCWARN(void)697 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
698 {
699 return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
700 }
701
702 /**
703 * @brief Enable Synchronization or trimming error interrupt
704 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
705 * @retval None
706 */
LL_CRS_EnableIT_ERR(void)707 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
708 {
709 SET_BIT(CRS->CR, CRS_CR_ERRIE);
710 }
711
712 /**
713 * @brief Disable Synchronization or trimming error interrupt
714 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
715 * @retval None
716 */
LL_CRS_DisableIT_ERR(void)717 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
718 {
719 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
720 }
721
722 /**
723 * @brief Check if Synchronization or trimming error interrupt is enabled or not
724 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
725 * @retval State of bit (1 or 0).
726 */
LL_CRS_IsEnabledIT_ERR(void)727 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
728 {
729 return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
730 }
731
732 /**
733 * @brief Enable Expected SYNC interrupt
734 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
735 * @retval None
736 */
LL_CRS_EnableIT_ESYNC(void)737 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
738 {
739 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
740 }
741
742 /**
743 * @brief Disable Expected SYNC interrupt
744 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
745 * @retval None
746 */
LL_CRS_DisableIT_ESYNC(void)747 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
748 {
749 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
750 }
751
752 /**
753 * @brief Check if Expected SYNC interrupt is enabled or not
754 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
755 * @retval State of bit (1 or 0).
756 */
LL_CRS_IsEnabledIT_ESYNC(void)757 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
758 {
759 return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
760 }
761
762 /**
763 * @}
764 */
765
766 #if defined(USE_FULL_LL_DRIVER)
767 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
768 * @{
769 */
770
771 ErrorStatus LL_CRS_DeInit(void);
772
773 /**
774 * @}
775 */
776 #endif /* USE_FULL_LL_DRIVER */
777
778 /**
779 * @}
780 */
781
782 /**
783 * @}
784 */
785
786 #endif /* defined(CRS) */
787
788 /**
789 * @}
790 */
791
792 #ifdef __cplusplus
793 }
794 #endif
795
796 #endif /* STM32WBxx_LL_CRS_H */
797
798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
799
