1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32u5xx_ll_dma.h"
43 #include "stm32u5xx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32U5xx_LL_Driver
51 * @{
52 */
53
54 #if (defined (GPDMA1) || defined (LPDMA1))
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_8) || \
78 ((Channel) == LL_DMA_CHANNEL_9) || \
79 ((Channel) == LL_DMA_CHANNEL_10) || \
80 ((Channel) == LL_DMA_CHANNEL_11) || \
81 ((Channel) == LL_DMA_CHANNEL_12) || \
82 ((Channel) == LL_DMA_CHANNEL_13) || \
83 ((Channel) == LL_DMA_CHANNEL_14) || \
84 ((Channel) == LL_DMA_CHANNEL_15) || \
85 ((Channel) == LL_DMA_CHANNEL_ALL))) || \
86 (((INSTANCE) == LPDMA1) && \
87 (((Channel) == LL_DMA_CHANNEL_0) || \
88 ((Channel) == LL_DMA_CHANNEL_1) || \
89 ((Channel) == LL_DMA_CHANNEL_2) || \
90 ((Channel) == LL_DMA_CHANNEL_3) || \
91 ((Channel) == LL_DMA_CHANNEL_ALL))))
92
93
94 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
95 (((Channel) == LL_DMA_CHANNEL_0) || \
96 ((Channel) == LL_DMA_CHANNEL_1) || \
97 ((Channel) == LL_DMA_CHANNEL_2) || \
98 ((Channel) == LL_DMA_CHANNEL_3) || \
99 ((Channel) == LL_DMA_CHANNEL_4) || \
100 ((Channel) == LL_DMA_CHANNEL_5) || \
101 ((Channel) == LL_DMA_CHANNEL_6) || \
102 ((Channel) == LL_DMA_CHANNEL_7) || \
103 ((Channel) == LL_DMA_CHANNEL_8) || \
104 ((Channel) == LL_DMA_CHANNEL_9) || \
105 ((Channel) == LL_DMA_CHANNEL_10) || \
106 ((Channel) == LL_DMA_CHANNEL_11) || \
107 ((Channel) == LL_DMA_CHANNEL_12) || \
108 ((Channel) == LL_DMA_CHANNEL_13) || \
109 ((Channel) == LL_DMA_CHANNEL_14) || \
110 ((Channel) == LL_DMA_CHANNEL_15)))
111
112 #define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \
113 (((Channel) == LL_DMA_CHANNEL_12) || \
114 ((Channel) == LL_DMA_CHANNEL_13) || \
115 ((Channel) == LL_DMA_CHANNEL_14) || \
116 ((Channel) == LL_DMA_CHANNEL_15)))
117
118 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
119 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
120 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
121
122 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
123 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
124 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
125
126 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
127
128 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
129 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
130 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
131
132 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
133 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
134 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
135
136 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
137 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
138
139 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
140 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
141
142 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
143 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
144 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
145 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
146
147 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
148
149 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
150
151 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
152 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
153 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
154 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
155
156 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
157 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
158 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
159
160 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
161 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
162
163 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM15_TRGO)
164
165 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM3_UE)
166
167 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
168 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
169 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
170 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
171
172 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
173 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
174
175 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
176 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
177
178 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
179 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
180
181 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
182 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
183
184 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
185 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
186
187 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
188 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
189
190 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
191 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
192
193 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
194 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
195
196 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
197 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
198
199 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
200
201 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
202 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
203
204 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
205 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
206
207 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
208
209 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
210
211 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
212
213 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
214
215 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
216 ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) || \
217 ((__VALUE__) == LL_DMA_LPDMA_LINEAR_NODE))
218
219 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
220 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
221 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
222
223 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
224 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
225 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
226 /**
227 * @}
228 */
229
230 /* Private function prototypes -----------------------------------------------*/
231 /* Exported functions --------------------------------------------------------*/
232
233 /** @addtogroup DMA_LL_Exported_Functions
234 * @{
235 */
236
237 /** @addtogroup DMA_LL_EF_Init
238 * @{
239 */
240
241 /**
242 * @brief De-initialize the DMA registers to their default reset values.
243 * @note This API is used for all available DMA channels.
244 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
245 * helper macros :
246 * @arg @ref LL_DMA_GET_INSTANCE
247 * @arg @ref LL_DMA_GET_CHANNEL
248 * @param DMAx DMAx Instance
249 * @param Channel This parameter can be one of the following values:
250 * @arg @ref LL_DMA_CHANNEL_0
251 * @arg @ref LL_DMA_CHANNEL_1
252 * @arg @ref LL_DMA_CHANNEL_2
253 * @arg @ref LL_DMA_CHANNEL_3
254 * @arg @ref LL_DMA_CHANNEL_4
255 * @arg @ref LL_DMA_CHANNEL_5
256 * @arg @ref LL_DMA_CHANNEL_6
257 * @arg @ref LL_DMA_CHANNEL_7
258 * @arg @ref LL_DMA_CHANNEL_8
259 * @arg @ref LL_DMA_CHANNEL_9
260 * @arg @ref LL_DMA_CHANNEL_10
261 * @arg @ref LL_DMA_CHANNEL_11
262 * @arg @ref LL_DMA_CHANNEL_12
263 * @arg @ref LL_DMA_CHANNEL_13
264 * @arg @ref LL_DMA_CHANNEL_14
265 * @arg @ref LL_DMA_CHANNEL_15
266 * @retval An ErrorStatus enumeration value:
267 * - SUCCESS : DMA registers are de-initialized.
268 * - ERROR : DMA registers are not de-initialized.
269 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)270 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
271 {
272 DMA_Channel_TypeDef *tmp;
273 ErrorStatus status = SUCCESS;
274
275 /* Check the DMA Instance DMAx and Channel parameters */
276 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
277
278 if (Channel == LL_DMA_CHANNEL_ALL)
279 {
280 if (DMAx == GPDMA1)
281 {
282 /* Force reset of DMA clock */
283 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
284
285 /* Release reset of DMA clock */
286 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
287 }
288 else
289 {
290 /* Force reset of DMA clock */
291 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
292
293 /* Release reset of DMA clock */
294 LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPDMA1);
295 }
296 }
297 else
298 {
299 /* Get the DMA Channel Instance */
300 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
301
302 /* Suspend DMA channel */
303 LL_DMA_SuspendChannel(DMAx, Channel);
304
305 /* Disable the selected Channel */
306 LL_DMA_ResetChannel(DMAx, Channel);
307
308 /* Reset DMAx_Channely control register */
309 LL_DMA_WriteReg(tmp, CLBAR, 0U);
310
311 /* Reset DMAx_Channely control register */
312 LL_DMA_WriteReg(tmp, CCR, 0U);
313
314 /* Reset DMAx_Channely Configuration register */
315 LL_DMA_WriteReg(tmp, CTR1, 0U);
316
317 /* Reset DMAx_Channely transfer register 2 */
318 LL_DMA_WriteReg(tmp, CTR2, 0U);
319
320 /* Reset DMAx_Channely block number of data register */
321 LL_DMA_WriteReg(tmp, CBR1, 0U);
322
323 /* Reset DMAx_Channely source address register */
324 LL_DMA_WriteReg(tmp, CSAR, 0U);
325
326 /* Reset DMAx_Channely destination address register */
327 LL_DMA_WriteReg(tmp, CDAR, 0U);
328
329 /* Check DMA channel */
330 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
331 {
332 /* Reset DMAx_Channely transfer register 3 */
333 LL_DMA_WriteReg(tmp, CTR3, 0U);
334
335 /* Reset DMAx_Channely Block register 2 */
336 LL_DMA_WriteReg(tmp, CBR2, 0U);
337 }
338
339 /* Reset DMAx_Channely Linked list address register */
340 LL_DMA_WriteReg(tmp, CLLR, 0U);
341
342 /* Reset DMAx_Channely pending flags */
343 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
344
345 /* Reset DMAx_Channely attribute */
346 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
347 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
348 LL_DMA_DisableChannelSecure(DMAx, Channel);
349 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
350 }
351
352 return (uint32_t)status;
353 }
354
355 /**
356 * @brief Initialize the DMA registers according to the specified parameters
357 * in DMA_InitStruct.
358 * @note This API is used for all available DMA channels.
359 * @note A software request transfer can be done once programming the direction
360 * field in memory to memory value.
361 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
362 * helper macros :
363 * @arg @ref LL_DMA_GET_INSTANCE
364 * @arg @ref LL_DMA_GET_CHANNEL
365 * @param DMAx DMAx Instance
366 * @param Channel This parameter can be one of the following values:
367 * @arg @ref LL_DMA_CHANNEL_0
368 * @arg @ref LL_DMA_CHANNEL_1
369 * @arg @ref LL_DMA_CHANNEL_2
370 * @arg @ref LL_DMA_CHANNEL_3
371 * @arg @ref LL_DMA_CHANNEL_4
372 * @arg @ref LL_DMA_CHANNEL_5
373 * @arg @ref LL_DMA_CHANNEL_6
374 * @arg @ref LL_DMA_CHANNEL_7
375 * @arg @ref LL_DMA_CHANNEL_8
376 * @arg @ref LL_DMA_CHANNEL_9
377 * @arg @ref LL_DMA_CHANNEL_10
378 * @arg @ref LL_DMA_CHANNEL_11
379 * @arg @ref LL_DMA_CHANNEL_12
380 * @arg @ref LL_DMA_CHANNEL_13
381 * @arg @ref LL_DMA_CHANNEL_14
382 * @arg @ref LL_DMA_CHANNEL_15
383 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
384 * @retval An ErrorStatus enumeration value:
385 * - SUCCESS : DMA registers are initialized.
386 * - ERROR : Not applicable.
387 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)388 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
389 {
390 /* Check the DMA Instance DMAx and Channel parameters*/
391 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
392
393 /* Check the DMA parameters from DMA_InitStruct */
394 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
395
396 /* Check direction */
397 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
398 {
399 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
400 }
401
402 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
403 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
404 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
405 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
406 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
407 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
408 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
409 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
410 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
411 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
412 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
413 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
414 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
415
416 /* Check DMA instance */
417 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
418 {
419 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
420 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
421 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
422 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
423 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
424 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
425 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
426 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
427 }
428
429 /* Check trigger polarity */
430 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
431 {
432 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
433 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
434 }
435
436 /* Check DMA channel */
437 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
438 {
439 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
440 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
441 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
442 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
443 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
444 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
445 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
446 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
447 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
448 }
449
450 /*-------------------------- DMAx CLBAR Configuration ------------------------
451 * Configure the Transfer linked list address with parameter :
452 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
453 */
454 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
455
456 /*-------------------------- DMAx CCR Configuration --------------------------
457 * Configure the control parameter :
458 * - LinkAllocatedPort: DMA_CCR_LAP bit
459 * LinkAllocatedPort field is not supported by LPDMA channels.
460 * - LinkStepMode: DMA_CCR_LSM bit
461 * - Priority: DMA_CCR_PRIO [23:22] bits
462 */
463 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
464 DMA_InitStruct->LinkAllocatedPort | \
465 DMA_InitStruct->LinkStepMode);
466
467 /*-------------------------- DMAx CTR1 Configuration -------------------------
468 * Configure the Data transfer parameter :
469 * - DestAllocatedPort: DMA_CTR1_DAP bit
470 * DestAllocatedPort field is not supported by LPDMA channels.
471 * - DestHWordExchange: DMA_CTR1_DHX bit
472 * DestHWordExchange field is not supported by LPDMA channels.
473 * - DestByteExchange: DMA_CTR1_DBX bit
474 * DestByteExchange field is not supported by LPDMA channels.
475 * - DestIncMode: DMA_CTR1_DINC bit
476 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
477 * - SrcAllocatedPort: DMA_CTR1_SAP bit
478 * SrcAllocatedPort field is not supported by LPDMA channels.
479 * - SrcByteExchange: DMA_CTR1_SBX bit
480 * SrcByteExchange field is not supported by LPDMA channels.
481 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
482 * DataAlignment field is reduced to one bit by LPDMA channels.
483 * - SrcIncMode: DMA_CTR1_SINC bit
484 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
485 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
486 * SrcBurstLength field is not supported by LPDMA channels.
487 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
488 * DestBurstLength field is not supported by LPDMA channels.
489 */
490 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
491 DMA_InitStruct->DestHWordExchange | \
492 DMA_InitStruct->DestByteExchange | \
493 DMA_InitStruct->DestIncMode | \
494 DMA_InitStruct->DestDataWidth | \
495 DMA_InitStruct->SrcAllocatedPort | \
496 DMA_InitStruct->SrcByteExchange | \
497 DMA_InitStruct->DataAlignment | \
498 DMA_InitStruct->SrcIncMode | \
499 DMA_InitStruct->SrcDataWidth);
500 /* Check DMA instance */
501 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
502 {
503 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
504 DMA_InitStruct->DestBurstLength);
505 }
506
507 /*-------------------------- DMAx CTR2 Configuration -------------------------
508 * Configure the channel transfer parameter :
509 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
510 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
511 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
512 * - BlkHWRequest: DMA_CTR2_BREQ bit
513 * - Direction: DMA_CTR2_DREQ bit
514 * - Direction: DMA_CTR2_SWREQ bit
515 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
516 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
517 * TriggerSelection field is reduced to 5 bits for LPDMA channels.
518 * - Request: DMA_CTR2_REQSEL [6:0] bits
519 * Request field is reduced to 5 bits for LPDMA channels.
520 */
521 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
522 DMA_InitStruct->TriggerPolarity | \
523 DMA_InitStruct->BlkHWRequest | \
524 DMA_InitStruct->Direction);
525
526 /* Check direction */
527 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
528 {
529 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
530 }
531
532 /* Check trigger polarity */
533 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
534 {
535 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
536 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
537 }
538
539 /*-------------------------- DMAx CBR1 Configuration -------------------------
540 * Configure the Transfer Block counters and update mode with parameter :
541 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
542 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
543 * BlkRptCount field is supported only by 2D addressing channels.
544 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
545 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
546 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
547 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
548 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
549 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
550 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
551 * DestAddrUpdateMode field is supported only by 2D addressing channels.
552 */
553 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
554
555 /* Check DMA channel */
556 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
557 {
558 LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
559 LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
560 DMA_InitStruct->BlkRptDestAddrUpdateMode | \
561 DMA_InitStruct->SrcAddrUpdateMode | \
562 DMA_InitStruct->DestAddrUpdateMode);
563 }
564
565 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
566 * Configure the Transfer source address with parameter :
567 * - SrcAddress: DMA_CSAR_SA[31:0] bits
568 * - DestAddress: DMA_CDAR_DA[31:0] bits
569 */
570 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
571
572 /* Check DMA channel */
573 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
574 {
575 /*------------------------ DMAx CTR3 Configuration -------------------------
576 * Configure the Transfer Block counters and update mode with parameter :
577 * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
578 * SrcAddrOffset field is supported only by 2D addressing channels.
579 * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
580 * DestAddrOffset field is supported only by 2D addressing channels.
581 */
582 LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
583
584 /*------------------------ DMAx CBR2 Configuration -----------------------
585 * Configure the Transfer Block counters and update mode with parameter :
586 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
587 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
588 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
589 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
590 */
591 LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
592 DMA_InitStruct->BlkRptDestAddrOffset);
593 }
594
595 /*-------------------------- DMAx CLLR Configuration -------------------------
596 * Configure the Transfer linked list address with parameter :
597 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
598 */
599 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
600
601 return (uint32_t)SUCCESS;
602 }
603
604 /**
605 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
606 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
607 * @retval None.
608 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)609 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
610 {
611 /* Set DMA_InitStruct fields to default values */
612 DMA_InitStruct->SrcAddress = 0x00000000U;
613 DMA_InitStruct->DestAddress = 0x00000000U;
614 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
615 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
616 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
617 DMA_InitStruct->SrcBurstLength = 1U;
618 DMA_InitStruct->DestBurstLength = 1U;
619 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
620 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
621 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
622 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
623 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
624 DMA_InitStruct->BlkDataLength = 0x00000000U;
625 DMA_InitStruct->BlkRptCount = 0x00000000U;
626 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
627 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
628 DMA_InitStruct->TriggerSelection = 0x00000000U;
629 DMA_InitStruct->Request = 0x00000000U;
630 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
631 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
632 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
633 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
634 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
635 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
636 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
637 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
638 DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
639 DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
640 DMA_InitStruct->SrcAddrOffset = 0x00000000U;
641 DMA_InitStruct->DestAddrOffset = 0x00000000U;
642 DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
643 DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
644 DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
645 DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
646 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
647 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
648 };
649
650 /**
651 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
652 * @param DMA_InitLinkedListStruct Pointer to
653 * a @ref LL_DMA_InitLinkedListTypeDef structure.
654 * @retval None.
655 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)656 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
657 {
658 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
659 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
660 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
661 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
662 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
663 };
664
665 /**
666 * @brief De-initialize the DMA linked list.
667 * @note This API is used for all available DMA channels.
668 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
669 * helper macros :
670 * @arg @ref LL_DMA_GET_INSTANCE
671 * @arg @ref LL_DMA_GET_CHANNEL
672 * @param DMAx DMAx Instance
673 * @param Channel This parameter can be one of the following values:
674 * @arg @ref LL_DMA_CHANNEL_0
675 * @arg @ref LL_DMA_CHANNEL_1
676 * @arg @ref LL_DMA_CHANNEL_2
677 * @arg @ref LL_DMA_CHANNEL_3
678 * @arg @ref LL_DMA_CHANNEL_4
679 * @arg @ref LL_DMA_CHANNEL_5
680 * @arg @ref LL_DMA_CHANNEL_6
681 * @arg @ref LL_DMA_CHANNEL_7
682 * @arg @ref LL_DMA_CHANNEL_8
683 * @arg @ref LL_DMA_CHANNEL_9
684 * @arg @ref LL_DMA_CHANNEL_10
685 * @arg @ref LL_DMA_CHANNEL_11
686 * @arg @ref LL_DMA_CHANNEL_12
687 * @arg @ref LL_DMA_CHANNEL_13
688 * @arg @ref LL_DMA_CHANNEL_14
689 * @arg @ref LL_DMA_CHANNEL_15
690 * @retval An ErrorStatus enumeration value:
691 * - SUCCESS : DMA registers are de-initialized.
692 * - ERROR : DMA registers are not de-initialized.
693 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)694 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
695 {
696 return LL_DMA_DeInit(DMAx, Channel);
697 }
698
699 /**
700 * @brief Initialize the DMA linked list according to the specified parameters
701 * in LL_DMA_InitLinkedListTypeDef.
702 * @note This API is used for all available DMA channels.
703 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
704 * helper macros :
705 * @arg @ref LL_DMA_GET_INSTANCE
706 * @arg @ref LL_DMA_GET_CHANNEL
707 * @param DMAx DMAx Instance
708 * @param Channel This parameter can be one of the following values:
709 * @arg @ref LL_DMA_CHANNEL_0
710 * @arg @ref LL_DMA_CHANNEL_1
711 * @arg @ref LL_DMA_CHANNEL_2
712 * @arg @ref LL_DMA_CHANNEL_3
713 * @arg @ref LL_DMA_CHANNEL_4
714 * @arg @ref LL_DMA_CHANNEL_5
715 * @arg @ref LL_DMA_CHANNEL_6
716 * @arg @ref LL_DMA_CHANNEL_7
717 * @arg @ref LL_DMA_CHANNEL_8
718 * @arg @ref LL_DMA_CHANNEL_9
719 * @arg @ref LL_DMA_CHANNEL_10
720 * @arg @ref LL_DMA_CHANNEL_11
721 * @arg @ref LL_DMA_CHANNEL_12
722 * @arg @ref LL_DMA_CHANNEL_13
723 * @arg @ref LL_DMA_CHANNEL_14
724 * @arg @ref LL_DMA_CHANNEL_15
725 * @param DMA_InitLinkedListStruct pointer to
726 * a @ref LL_DMA_InitLinkedListTypeDef structure.
727 * @retval An ErrorStatus enumeration value:
728 * - SUCCESS : DMA registers are initialized.
729 * - ERROR : Not applicable.
730 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)731 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
732 {
733 /* Check the DMA Instance DMAx and Channel parameters*/
734 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
735
736 /* Check the DMA parameters from DMA_InitLinkedListStruct */
737 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
738 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
739 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
740 /* Check DMA instance */
741 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
742 {
743 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
744 }
745
746 /*-------------------------- DMAx CCR Configuration --------------------------
747 * Configure the control parameter :
748 * - LinkAllocatedPort: DMA_CCR_LAP bit
749 * LinkAllocatedPort field is supported only by GPDMA channels.
750 * - LinkStepMode: DMA_CCR_LSM bit
751 * - Priority: DMA_CCR_PRIO [23:22] bits
752 */
753 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
754 DMA_InitLinkedListStruct->LinkAllocatedPort | \
755 DMA_InitLinkedListStruct->LinkStepMode);
756
757 /*-------------------------- DMAx CTR2 Configuration -------------------------
758 * Configure the channel transfer parameter :
759 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
760 */
761 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
762
763 return (uint32_t)SUCCESS;
764 }
765
766 /**
767 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
768 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
769 * structure.
770 * @retval None.
771 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)772 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
773 {
774 /* Set DMA_InitNodeStruct fields to default values */
775 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
776 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
777 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
778 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
779 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
780 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
781 DMA_InitNodeStruct->DestBurstLength = 1U;
782 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
783 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
784 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
785 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
786 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
787 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
788 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
789 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
790 DMA_InitNodeStruct->SrcBurstLength = 1U;
791 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
792 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
793 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
794 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
795 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
796 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
797 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
798 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
799 DMA_InitNodeStruct->Request = 0x00000000U;
800 DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
801 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
802 DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
803 DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
804 DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
805 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
806 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
807 DMA_InitNodeStruct->DestAddress = 0x00000000U;
808 DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
809 DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
810 DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
811 DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
812 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
813 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
814 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
815 LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
816 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
817 };
818
819 /**
820 * @brief Initializes DMA linked list node according to the specified
821 * parameters in the DMA_InitNodeStruct.
822 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
823 * that contains linked list node
824 * registers configurations.
825 * @param pNode Pointer to linked list node to fill according to
826 * LL_DMA_LinkNodeTypeDef parameters.
827 * @retval None
828 */
LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)829 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
830 {
831 uint32_t reg_counter = 0U;
832
833 /* Check the DMA Node type */
834 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
835
836 /* Check the DMA parameters from DMA_InitNodeStruct */
837 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
838
839 /* Check direction */
840 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
841 {
842 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
843 }
844
845 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
846 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
847 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
848 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
849 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
850 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
851 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
852 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
853 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
854 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
855
856 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
857 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
858 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
859 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
860
861 /* Check trigger polarity */
862 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
863 {
864 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
865 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
866 }
867
868 /* Check node type */
869 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)
870 {
871 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
872 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
873 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
874 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
875 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
876 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
877 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
878 }
879
880 /* Check DMA channel */
881 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
882 {
883 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
884 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
885 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
886 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
887 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
888 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
889 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
890 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
891 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
892 }
893
894 /* Check if CTR1 register update is enabled */
895 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
896 {
897 /*-------------------------- DMAx CTR1 Configuration -----------------------
898 * Configure the Data transfer parameter :
899 * - DestAllocatedPort: DMA_CTR1_DAP bit
900 * DestAllocatedPort field is not supported by LPDMA channels.
901 * - DestHWordExchange: DMA_CTR1_DHX bit
902 * DestHWordExchange field is not supported by LPDMA channels.
903 * - DestByteExchange: DMA_CTR1_DBX bit
904 * DestByteExchange field is not supported by LPDMA channels.
905 * - DestIncMode: DMA_CTR1_DINC bit
906 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
907 * - SrcAllocatedPort: DMA_CTR1_SAP bit
908 * SrcAllocatedPort field is not supported by LPDMA channels.
909 * - SrcByteExchange: DMA_CTR1_SBX bit
910 * SrcByteExchange field is not supported by LPDMA channels.
911 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
912 * DataAlignment field is reduced to one bit for LPDMA channels.
913 * - SrcIncMode: DMA_CTR1_SINC bit
914 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
915 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
916 * SrcBurstLength field is not supported by LPDMA channels.
917 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
918 * DestBurstLength field is not supported by LPDMA channels.
919 */
920
921 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
922 DMA_InitNodeStruct->DestDataWidth | \
923 DMA_InitNodeStruct->DataAlignment | \
924 DMA_InitNodeStruct->SrcIncMode | \
925 DMA_InitNodeStruct->SrcDataWidth);
926
927 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
928 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
929 DMA_InitNodeStruct->SrcSecure);
930 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
931
932 /* Update CTR1 register fields for not LPDMA channels */
933 if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE)
934 {
935 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
936 DMA_InitNodeStruct->DestHWordExchange | \
937 DMA_InitNodeStruct->DestByteExchange | \
938 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
939 DMA_InitNodeStruct->SrcAllocatedPort | \
940 DMA_InitNodeStruct->SrcByteExchange | \
941 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
942 }
943
944 /* Increment counter for the next register */
945 reg_counter++;
946 }
947
948
949 /* Check if CTR2 register update is enabled */
950 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
951 {
952 /*-------------------------- DMAx CTR2 Configuration -----------------------
953 * Configure the channel transfer parameter :
954 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
955 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
956 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
957 * - BlkHWRequest: DMA_CTR2_BREQ bit
958 * - Direction: DMA_CTR2_DREQ bit
959 * - Direction: DMA_CTR2_SWREQ bit
960 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
961 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
962 * DataAlignment field is reduced to 5 bits for LPDMA channels.
963 * - Request: DMA_CTR2_REQSEL [6:0] bits
964 * DataAlignment field is reduced to 5 bits for LPDMA channels.
965 */
966 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
967 DMA_InitNodeStruct->TriggerPolarity | \
968 DMA_InitNodeStruct->BlkHWRequest | \
969 DMA_InitNodeStruct->Direction);
970
971 /* Check direction */
972 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
973 {
974 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
975 }
976
977 /* Check trigger polarity */
978 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
979 {
980 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
981 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
982 }
983
984 /* Update CTR2 register fields for LPDMA */
985 if (DMA_InitNodeStruct->NodeType == LL_DMA_LPDMA_LINEAR_NODE)
986 {
987 pNode->LinkRegisters[reg_counter] &= (~(1UL << 21U) & ~(3UL << 5U));
988 }
989
990 /* Increment counter for the next register */
991 reg_counter++;
992 }
993
994
995 /* Check if CBR1 register update is enabled */
996 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
997 {
998 /*-------------------------- DMAx CBR1 Configuration -----------------------
999 * Configure the Transfer Block counters and update mode with parameter :
1000 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
1001 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
1002 * BlkRptCount field is supported only by 2D addressing channels.
1003 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
1004 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
1005 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
1006 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
1007 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
1008 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
1009 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
1010 * DestAddrUpdateMode field is supported only by 2D addressing channels.
1011 */
1012 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
1013
1014 /* Update CBR1 register fields for 2D addressing channels */
1015 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1016 {
1017 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
1018 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
1019 DMA_InitNodeStruct->DestAddrUpdateMode | \
1020 DMA_InitNodeStruct->SrcAddrUpdateMode | \
1021 ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
1022 }
1023
1024 /* Increment counter for the next register */
1025 reg_counter++;
1026 }
1027
1028
1029 /* Check if CSAR register update is enabled */
1030 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
1031 {
1032 /*-------------------------- DMAx CSAR Configuration -----------------------
1033 * Configure the Transfer Block counters and update mode with parameter :
1034 * - SrcAddress: DMA_CSAR_SA[31:0] bits
1035 */
1036 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
1037
1038 /* Increment counter for the next register */
1039 reg_counter++;
1040 }
1041
1042
1043 /* Check if CDAR register update is enabled */
1044 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
1045 {
1046 /*-------------------------- DMAx CDAR Configuration -----------------------
1047 * Configure the Transfer Block counters and update mode with parameter :
1048 * - DestAddress: DMA_CDAR_DA[31:0] bits
1049 */
1050 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
1051
1052 /* Increment counter for the next register */
1053 reg_counter++;
1054 }
1055
1056
1057 /* Update CTR3 register fields for 2D addressing channels */
1058 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1059 {
1060 /* Check if CTR3 register update is enabled */
1061 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
1062 {
1063 /*-------------------------- DMAx CTR3 Configuration ---------------------
1064 * Configure the Block counters and update mode with parameter :
1065 * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
1066 * DestAddressOffset field is supported only by 2D addressing channels.
1067 * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
1068 * SrcAddressOffset field is supported only by 2D addressing channels.
1069 */
1070 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
1071 ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
1072
1073 /* Increment counter for the next register */
1074 reg_counter++;
1075 }
1076 }
1077
1078
1079 /* Update CBR2 register fields for 2D addressing channels */
1080 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1081 {
1082 /* Check if CBR2 register update is enabled */
1083 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
1084 {
1085 /*-------------------------- DMAx CBR2 Configuration ---------------------
1086 * Configure the Block counters and update mode with parameter :
1087 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
1088 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
1089 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
1090 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
1091 */
1092 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
1093 ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
1094 DMA_CBR2_BRDAO));
1095
1096 /* Increment counter for the next register */
1097 reg_counter++;
1098 }
1099 }
1100
1101 /* Check if CLLR register update is enabled */
1102 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
1103 {
1104 /*-------------------------- DMAx CLLR Configuration -----------------------
1105 * Configure the Transfer Block counters and update mode with parameter :
1106 * - UpdateRegisters DMA_CLLR_UT1 bit
1107 * - UpdateRegisters DMA_CLLR_UT2 bit
1108 * - UpdateRegisters DMA_CLLR_UB1 bit
1109 * - UpdateRegisters DMA_CLLR_USA bit
1110 * - UpdateRegisters DMA_CLLR_UDA bit
1111 * - UpdateRegisters DMA_CLLR_UT3 bit
1112 * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
1113 * - UpdateRegisters DMA_CLLR_UB2 bit
1114 * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
1115 * - UpdateRegisters DMA_CLLR_ULL bit
1116 */
1117 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
1118 DMA_CLLR_UB1 | DMA_CLLR_USA | \
1119 DMA_CLLR_UDA | DMA_CLLR_ULL)));
1120
1121 /* Update CLLR register fields for 2D addressing channels */
1122 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1123 {
1124 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
1125 }
1126 }
1127
1128 return (uint32_t)SUCCESS;
1129 }
1130
1131 /**
1132 * @brief Connect Linked list Nodes.
1133 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
1134 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
1135 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1136 * @param pNewLinkNode Pointer to new Linked list.
1137 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
1138 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1139 * @retval None
1140 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)1141 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
1142 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
1143 {
1144 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
1145 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
1146 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
1147 DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
1148 }
1149
1150 /**
1151 * @brief Disconnect the next linked list node.
1152 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
1153 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
1154 * @retval None.
1155 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)1156 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
1157 {
1158 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
1159 }
1160
1161 /**
1162 * @}
1163 */
1164
1165 /**
1166 * @}
1167 */
1168
1169 /**
1170 * @}
1171 */
1172
1173 #endif /* (defined (GPDMA1) || defined (LPDMA1)) */
1174
1175 /**
1176 * @}
1177 */
1178
1179 #endif /* defined (USE_FULL_LL_DRIVER) */
1180
1181
