1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32U5xx_LL_PWR_H
21 #define STM32U5xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46
47 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
48 * @{
49 */
50
51 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
52 * @brief Flags defines which can be used with LL_PWR_WriteReg function
53 * @{
54 */
55 #define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
56 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
57 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
58 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
59 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
60 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
61 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
62 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
63 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
64 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
74 #define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< EPOD booster ready flag */
75 #define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
76 #define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
77 #define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */
78 #define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */
79 #define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
80 #define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */
81 #define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
82 #define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */
83 #define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
84 #define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
85 #define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
86 #define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */
87
88 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
89 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
90 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
91 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
92 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
93 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
94 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
95 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
96 /**
97 * @}
98 */
99
100 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
101 * @{
102 */
103 #define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */
104 #define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */
105 #define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */
106 #define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */
107 #define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */
108 #define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */
109 /**
110 * @}
111 */
112
113 /** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode
114 * @note For some products of the U5 family (please see the Reference Manual),
115 * the SRAM2 content is preserved based on the same defines in Stop 3 mode.
116 * @{
117 */
118 #define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */
119 #define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */
120 #define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */
121 #define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */
122 /**
123 * @}
124 */
125
126 /** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode
127 * @{
128 */
129 #define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */
130 #define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
131 #define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
132 #define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
133 #define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \
134 PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */
135 /**
136 * @}
137 */
138
139 /** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode
140 * @{
141 */
142 #define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */
143 #define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */
144 #define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */
145 #define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */
146 /**
147 * @}
148 */
149
150 /** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode
151 * @{
152 */
153 #define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */
154 #define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
155 #define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
156 #define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
157 #define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
158 #define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
159 #define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
160 #define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
161 #define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
162 #define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \
163 PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \
164 PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */
165 /**
166 * @}
167 */
168
169 /** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode
170 * @{
171 */
172 #define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */
173 #define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */
174 /**
175 * @}
176 */
177
178 /** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode
179 * @{
180 */
181 #define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */
182 #define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */
183 /**
184 * @}
185 */
186
187 /** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode
188 * @{
189 */
190 #define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */
191 #define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */
192 /**
193 * @}
194 */
195
196 /** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode
197 * @{
198 */
199 #define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */
200 #define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */
201 /**
202 * @}
203 */
204
205 /** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode
206 * @{
207 */
208 #define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */
209 #define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */
210 /**
211 * @}
212 */
213
214 /** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode
215 * @{
216 */
217 #define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */
218 #define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */
219 /**
220 * @}
221 */
222
223 /** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode
224 * @{
225 */
226 #define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */
227 #define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */
228 /**
229 * @}
230 */
231
232 /** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode
233 * @{
234 */
235 #define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */
236 #define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */
237 /**
238 * @}
239 */
240
241 /** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode
242 * @{
243 */
244 #define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */
245 #define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */
246 /**
247 * @}
248 */
249
250 /** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode
251 * @{
252 */
253 #define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */
254 #define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */
255 /**
256 * @}
257 */
258
259 /** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode
260 * @{
261 */
262 #define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */
263 #define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */
264 /**
265 * @}
266 */
267
268 /** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
269 * @{
270 */
271 #define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
272 #define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
273 /**
274 * @}
275 */
276
277 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
278 * @{
279 */
280 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */
281 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */
282 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */
283 #define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */
284 /**
285 * @}
286 */
287
288 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
289 * @{
290 */
291 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
292 #define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
293 #define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
294 #define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
295 #define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
296 #define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
297 #define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
298 #define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
299 pin, compared to internal VREFINT level */
300 /**
301 * @}
302 */
303
304 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
305 * @{
306 */
307 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
308 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
309 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
310 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
311 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
312 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
313 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
314 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
315 /**
316 * @}
317 */
318
319 /** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
320 * @{
321 */
322 #define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
323 #define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
324 #define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
325 #define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
326 /**
327 * @}
328 */
329
330 /** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
331 * @{
332 */
333 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
334 #define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */
335 /**
336 * @}
337 */
338
339 /** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection
340 * @{
341 */
342 #define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */
343 #define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */
344 #define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */
345 #define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */
346 #define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */
347 #define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */
348 #define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */
349 #define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */
350 #define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */
351 /**
352 * @}
353 */
354
355 /** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
356 * @{
357 */
358 #define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
359 #define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
360 #define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
361 #define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
362 #define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
363 #define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
364 #define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
365 #define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
366 #define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
367 #define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
368 #define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
369 #define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
370 #define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
371 #define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
372 #define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
373 #define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
374 /**
375 * @}
376 */
377
378 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
379 * @{
380 */
381 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
382 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
383 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
384 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
385 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
386 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
387 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
388 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
389 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
390 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
391 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
392 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
393 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
394 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
395 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
396 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
397
398 #define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
399 #define LL_PWR_LPM_SEC PWR_SECCFGR_WUP8SEC /*!< Low-power modes secure mode */
400 #define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
401 #define LL_PWR_VDM_SEC PWR_SECCFGR_WUP8SEC /*!< Voltage detection and monitoring secure mode */
402 #define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
403 #define LL_PWR_VB_SEC PWR_SECCFGR_WUP8SEC /*!< Backup domain secure mode */
404 #define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */
405 #define LL_PWR_APC_SEC PWR_SECCFGR_WUP8SEC /*!< Pull-up/pull-down secure mode */
406 /**
407 * @}
408 */
409
410 /**
411 * @}
412 */
413
414 /* Exported macro ------------------------------------------------------------*/
415
416 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
417 * @{
418 */
419
420 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
421 * @{
422 */
423
424 /**
425 * @brief Write a value in PWR register.
426 * @param __REG__ Register to be written.
427 * @param __VALUE__ Value to be written in the register.
428 * @retval None.
429 */
430 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
431
432 /**
433 * @brief Read a value in PWR register.
434 * @param __REG__ Register to be read.
435 * @retval Register value.
436 */
437 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
438 /**
439 * @}
440 */
441
442 /**
443 * @}
444 */
445
446 /* Exported functions --------------------------------------------------------*/
447
448 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
449 * @{
450 */
451
452 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
453 * @{
454 */
455
456 /**
457 * @brief Set system power mode.
458 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
459 * @param Mode : This parameter can be one of the following values:
460 * @arg @ref LL_PWR_STOP0_MODE
461 * @arg @ref LL_PWR_STOP1_MODE
462 * @arg @ref LL_PWR_STOP2_MODE
463 * @arg @ref LL_PWR_STOP3_MODE
464 * @arg @ref LL_PWR_STANDBY_MODE
465 * @arg @ref LL_PWR_SHUTDOWN_MODE
466 * @retval None
467 */
LL_PWR_SetPowerMode(uint32_t Mode)468 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
469 {
470 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
471 }
472
473 /**
474 * @brief Get system power mode.
475 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
476 * @retval Returned value can be one of the following values:
477 * @arg @ref LL_PWR_STOP0_MODE
478 * @arg @ref LL_PWR_STOP1_MODE
479 * @arg @ref LL_PWR_STOP2_MODE
480 * @arg @ref LL_PWR_STOP3_MODE
481 * @arg @ref LL_PWR_STANDBY_MODE
482 * @arg @ref LL_PWR_SHUTDOWN_MODE
483 */
LL_PWR_GetPowerMode(void)484 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
485 {
486 return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
487 }
488
489 /**
490 * @brief Set the SRAM2 page(s) retention in Standby mode.
491 * @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n
492 * @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention
493 * @param SRAM2PageRetention : This parameter can be one of the following values:
494 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
495 * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
496 * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
497 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
498 * @retval None
499 */
LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)500 __STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
501 {
502 MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention);
503 }
504
505 /**
506 * @brief Get the SRAM2 page(s) retention in Standby mode.
507 * @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n
508 * @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention
509 * @retval Returned value can be one of the following values:
510 * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
511 * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
512 * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
513 * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
514 */
LL_PWR_GetSRAM2SBRetention(void)515 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
516 {
517 return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2)));
518 }
519
520 /**
521 * @brief Enable BOR ultra low power mode.
522 * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
523 * @retval None
524 */
LL_PWR_EnableUltraLowPowerMode(void)525 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
526 {
527 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
528 }
529
530 /**
531 * @brief Disable BOR ultra low-power mode.
532 * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
533 * @retval None
534 */
LL_PWR_DisableUltraLowPowerMode(void)535 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
536 {
537 CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
538 }
539
540 /**
541 * @brief Check if BOR ultra low power mode is enabled.
542 * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
543 * @retval State of bit (1 or 0).
544 */
LL_PWR_IsEnabledUltraLowPowerMode(void)545 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
546 {
547 return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
548 }
549
550 /**
551 * @brief Set the SRAM1 retention in Run mode.
552 * @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n
553 * @param SRAM1Retention : This parameter can be one of the following values:
554 * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
555 * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
556 * @retval None
557 */
LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)558 __STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)
559 {
560 MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION));
561 }
562
563 /**
564 * @brief Get the SRAM1 retention in Run mode.
565 * @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n
566 * @retval Returned value can be one of the following values:
567 * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
568 * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
569 */
LL_PWR_GetSRAM1RunRetention(void)570 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void)
571 {
572 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION);
573 }
574
575 /**
576 * @brief Set the SRAM2 retention in Run mode.
577 * @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n
578 * @param SRAM2Retention : This parameter can be one of the following values:
579 * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
580 * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
581 * @retval None
582 */
LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)583 __STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)
584 {
585 MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION));
586 }
587
588 /**
589 * @brief Get the SRAM2 retention in Run mode.
590 * @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n
591 * @retval Returned value can be one of the following values:
592 * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
593 * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
594 */
LL_PWR_GetSRAM2RunRetention(void)595 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void)
596 {
597 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION);
598 }
599
600 /**
601 * @brief Set the SRAM3 retention in Run mode.
602 * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n
603 * @param SRAM3Retention : This parameter can be one of the following values:
604 * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
605 * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
606 * @retval None
607 */
LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)608 __STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)
609 {
610 MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION));
611 }
612
613 /**
614 * @brief Get the SRAM3 retention in Run mode.
615 * @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n
616 * @retval Returned value can be one of the following values:
617 * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
618 * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
619 */
LL_PWR_GetSRAM3RunRetention(void)620 __STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void)
621 {
622 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION);
623 }
624
625 /**
626 * @brief Set the SRAM4 retention in Run mode.
627 * @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n
628 * @param SRAM4Retention : This parameter can be one of the following values:
629 * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
630 * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
631 * @retval None
632 */
LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)633 __STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)
634 {
635 MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION));
636 }
637
638 /**
639 * @brief Get the SRAM4 retention in Run mode.
640 * @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n
641 * @retval Returned value can be one of the following values:
642 * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
643 * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
644 */
LL_PWR_GetSRAM4RunRetention(void)645 __STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void)
646 {
647 return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION);
648 }
649
650 /**
651 * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
652 * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n
653 * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n
654 * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3
655 * @param SRAM1PageRetention : This parameter can be one of the following values:
656 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
657 * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
658 * Or can be a combination of the following values:
659 * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
660 * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
661 * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
662 * @retval None
663 */
LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)664 __STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)
665 {
666 MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION));
667 }
668
669 /**
670 * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
671 * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n
672 * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n
673 * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
676 * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
677 * Or a combination of the following values:
678 * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
679 * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
680 * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
681 */
LL_PWR_GetSRAM1StopRetention_1_3(void)682 __STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void)
683 {
684 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION);
685 }
686
687 /**
688 * @brief Set the SRAM2 page(s) retention in Stop mode.
689 * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n
690 * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention
691 * @param SRAM2PageRetention : This parameter can be one of the following values:
692 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
693 * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
694 * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
695 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
696 * @retval None
697 */
LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)698 __STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
699 {
700 MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION));
701 }
702
703 /**
704 * @brief Get the SRAM2 page(s) retention in Stop mode.
705 * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n
706 * @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention
707 * @retval Returned value can be one of the following values:
708 * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
709 * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
710 * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
711 * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
712 */
LL_PWR_GetSRAM2StopRetention(void)713 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
714 {
715 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION);
716 }
717
718 /**
719 * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
720 * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n
721 * @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n
722 * @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n
723 * @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n
724 * @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n
725 * @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n
726 * @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n
727 * @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8
728 * @param SRAM3PageRetention : This parameter can be one of the following values:
729 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
730 * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
731 * Or can be a combination of the following values:
732 * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
733 * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
734 * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
735 * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
736 * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
737 * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
738 * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
739 * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
740 * @retval None
741 */
LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)742 __STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)
743 {
744 MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION));
745 }
746
747 /**
748 * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
749 * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n
750 * @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n
751 * @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n
752 * @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n
753 * @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n
754 * @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n
755 * @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n
756 * @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
759 * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
760 * Or can be a combination of the following values:
761 * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
762 * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
763 * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
764 * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
765 * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
766 * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
767 * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
768 * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
769 */
LL_PWR_GetSRAM3StopRetention_1_8(void)770 __STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void)
771 {
772 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION);
773 }
774
775 /**
776 * @brief Set the SRAM4 page retention in Stop mode.
777 * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n
778 * @param SRAM4PageRetention : This parameter can be one of the following values:
779 * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
780 * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
781 * @retval None
782 */
LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)783 __STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)
784 {
785 MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION));
786 }
787
788 /**
789 * @brief Get the SRAM4 page retention in Stop mode.
790 * @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention
791 * @retval Returned value can be one of the following values:
792 * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
793 * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
794 */
LL_PWR_GetSRAM4StopRetention(void)795 __STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void)
796 {
797 return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION);
798 }
799
800 /**
801 * @brief Set the ICACHE SRAM page retention in Stop mode.
802 * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n
803 * @param ICachePageRetention : This parameter can be one of the following values:
804 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
805 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
806 * @retval None
807 */
LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)808 __STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)
809 {
810 MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION,
811 ((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION));
812 }
813
814 /**
815 * @brief Get the ICACHE SRAM page retention in Stop mode.
816 * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
817 * @retval Returned value can be one of the following values:
818 * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
819 * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
820 */
LL_PWR_GetICacheRAMStopRetention(void)821 __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
822 {
823 return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION);
824 }
825
826 /**
827 * @brief Set the DCACHE1 SRAM page retention in Stop mode.
828 * @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n
829 * @param DCache1PageRetention : This parameter can be one of the following values:
830 * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
831 * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
832 * @retval None
833 */
LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)834 __STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)
835 {
836 MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION,
837 ((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION));
838 }
839
840 /**
841 * @brief Get the DCACHE1 SRAM page retention in Stop mode.
842 * @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
845 * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
846 */
LL_PWR_GetDCache1RAMStopRetention(void)847 __STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void)
848 {
849 return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION);
850 }
851
852 /**
853 * @brief Set the DMA2D SRAM page retention in Stop mode.
854 * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n
855 * @param DMA2DRAMPageRetention : This parameter can be one of the following values:
856 * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
857 * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
858 * @retval None
859 */
LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)860 __STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)
861 {
862 MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION,
863 ((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION));
864 }
865
866 /**
867 * @brief Get the DMA2D SRAM page retention in Stop mode.
868 * @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention
869 * @retval Returned value can be one of the following values:
870 * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
871 * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
872 */
LL_PWR_GetDMA2DRAMStopRetention(void)873 __STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void)
874 {
875 return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION);
876 }
877
878 /**
879 * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
880 * @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n
881 * @param PriphRAMPageRetention : This parameter can be one of the following values:
882 * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
883 * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
884 * @retval None
885 */
LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)886 __STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)
887 {
888 MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION,
889 ((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION));
890 }
891
892 /**
893 * @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
894 * @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention
895 * @retval Returned value can be one of the following values:
896 * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
897 * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
898 */
LL_PWR_GetPeriphRAMStopRetention(void)899 __STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void)
900 {
901 return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION);
902 }
903
904 /**
905 * @brief Set the PKA32 SRAM page retention in Stop mode.
906 * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention
907 * @param PKARAMPageRetention : This parameter can be one of the following values:
908 * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
909 * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
910 * @retval None
911 */
LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)912 __STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)
913 {
914 MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION));
915 }
916
917 /**
918 * @brief Get the PKA32 SRAM page retention in Stop mode.
919 * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention
920 * @retval Returned value can be one of the following values:
921 * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
922 * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
923 */
LL_PWR_GetPKARAMStopRetention(void)924 __STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void)
925 {
926 return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION);
927 }
928
929 /**
930 * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
931 * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
932 * @retval None
933 */
LL_PWR_EnableFlashFastWakeUp(void)934 __STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
935 {
936 SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
937 }
938
939 /**
940 * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
941 * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
942 * @retval None
943 */
LL_PWR_DisableFlashFastWakeUp(void)944 __STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
945 {
946 CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
947 }
948
949 /**
950 * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1)
951 * is enabled.
952 * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashSRAM_StopModes
953 * @retval State of bit (1 or 0).
954 */
LL_PWR_IsEnabledFlashFastWakeUp(void)955 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
956 {
957 return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
958 }
959
960 /**
961 * @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
962 * @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp
963 * @retval None
964 */
LL_PWR_EnableSRAM4FastWakeUp(void)965 __STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void)
966 {
967 SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
968 }
969
970 /**
971 * @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
972 * @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp
973 * @retval None
974 */
LL_PWR_DisableSRAM4FastWakeUp(void)975 __STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void)
976 {
977 CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
978 }
979
980 /**
981 * @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
982 * is enabled.
983 * @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp
984 * @retval State of bit (1 or 0).
985 */
LL_PWR_IsEnabledSRAM4FastWakeUp(void)986 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void)
987 {
988 return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL);
989 }
990
991 /**
992 * @brief Set the smart run domain mode.
993 * @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode
994 * @param SRDMode : This parameter can be one of the following values:
995 * @arg @ref LL_PWR_SRD_RUN_MODE
996 * @arg @ref LL_PWR_SRD_STOP_MODE
997 * @retval None
998 */
LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)999 __STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)
1000 {
1001 MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode);
1002 }
1003
1004 /**
1005 * @brief Get the smart run domain mode.
1006 * @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode
1007 * @retval Returned value can be one of the following values:
1008 * @arg @ref LL_PWR_SRD_RUN_MODE
1009 * @arg @ref LL_PWR_SRD_STOP_MODE
1010 */
LL_PWR_GetSmartRunDomainMode(void)1011 __STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void)
1012 {
1013 return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN));
1014 }
1015
1016 /**
1017 * @brief Set the VCore regulator supply.
1018 * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
1019 * @param RegulatorSupply : This parameter can be one of the following values:
1020 * @arg @ref LL_PWR_LDO_SUPPLY
1021 * @arg @ref LL_PWR_SMPS_SUPPLY
1022 * @retval None
1023 */
LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)1024 __STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
1025 {
1026 MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
1027 }
1028
1029 /**
1030 * @brief Get the VCore regulator supply.
1031 * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
1032 * @retval Returned value can be one of the following values:
1033 * @arg @ref LL_PWR_LDO_SUPPLY
1034 * @arg @ref LL_PWR_SMPS_SUPPLY
1035 */
LL_PWR_GetRegulatorSupply(void)1036 __STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
1037 {
1038 return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
1039 }
1040
1041 /**
1042 * @brief Enable the fast soft start for selected regulator.
1043 * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
1044 * @retval None
1045 */
LL_PWR_EnableFastSoftStart(void)1046 __STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
1047 {
1048 SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
1049 }
1050
1051 /**
1052 * @brief Disable the fast soft start for selected regulator.
1053 * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
1054 * @retval None
1055 */
LL_PWR_DisableFastSoftStart(void)1056 __STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
1057 {
1058 CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
1059 }
1060
1061 /**
1062 * @brief Check if the fast soft start for selected regulator is enabled.
1063 * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
1064 * @retval State of bit (1 or 0).
1065 */
LL_PWR_IsEnabledFastSoftStart(void)1066 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
1067 {
1068 return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
1069 }
1070
1071 /**
1072 * @brief Set the regulator supply output voltage.
1073 * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
1074 * @param VoltageScaling This parameter can be one of the following values:
1075 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1076 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1077 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1078 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
1079 * @retval None
1080 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)1081 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
1082 {
1083 MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
1084 }
1085
1086 /**
1087 * @brief Get the regulator supply output voltage.
1088 * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
1089 * @retval Returned value can be one of the following values:
1090 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1091 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1092 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1093 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
1094 */
LL_PWR_GetRegulVoltageScaling(void)1095 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1096 {
1097 return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
1098 }
1099
1100 /**
1101 * @brief Enable the EPOD (Embedded Power Distribution) booster.
1102 * @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster
1103 * @retval None
1104 */
LL_PWR_EnableEPODBooster(void)1105 __STATIC_INLINE void LL_PWR_EnableEPODBooster(void)
1106 {
1107 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1108 }
1109
1110 /**
1111 * @brief Disable the EPOD (Embedded Power Distribution) booster.
1112 * @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster
1113 * @retval None
1114 */
LL_PWR_DisableEPODBooster(void)1115 __STATIC_INLINE void LL_PWR_DisableEPODBooster(void)
1116 {
1117 CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
1118 }
1119
1120 /**
1121 * @brief Check if the EPOD (Embedded Power Distribution) booster is enabled.
1122 * @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster
1123 * @retval State of bit (1 or 0).
1124 */
LL_PWR_IsEnabledEPODBooster(void)1125 __STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void)
1126 {
1127 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL);
1128 }
1129
1130 /**
1131 * @brief Set the Power voltage detector level.
1132 * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
1133 * @param PVDLevel This parameter can be one of the following values:
1134 * @arg @ref LL_PWR_PVDLEVEL_0
1135 * @arg @ref LL_PWR_PVDLEVEL_1
1136 * @arg @ref LL_PWR_PVDLEVEL_2
1137 * @arg @ref LL_PWR_PVDLEVEL_3
1138 * @arg @ref LL_PWR_PVDLEVEL_4
1139 * @arg @ref LL_PWR_PVDLEVEL_5
1140 * @arg @ref LL_PWR_PVDLEVEL_6
1141 * @arg @ref LL_PWR_PVDLEVEL_7
1142 * @retval None
1143 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)1144 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
1145 {
1146 MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
1147 }
1148
1149 /**
1150 * @brief Get the Power voltage detector level.
1151 * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
1152 * @retval Returned value can be one of the following values:
1153 * @arg @ref LL_PWR_PVDLEVEL_0
1154 * @arg @ref LL_PWR_PVDLEVEL_1
1155 * @arg @ref LL_PWR_PVDLEVEL_2
1156 * @arg @ref LL_PWR_PVDLEVEL_3
1157 * @arg @ref LL_PWR_PVDLEVEL_4
1158 * @arg @ref LL_PWR_PVDLEVEL_5
1159 * @arg @ref LL_PWR_PVDLEVEL_6
1160 * @arg @ref LL_PWR_PVDLEVEL_7
1161 */
LL_PWR_GetPVDLevel(void)1162 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
1163 {
1164 return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
1165 }
1166
1167 /**
1168 * @brief Enable the power voltage detector.
1169 * @rmtoll SVMCR PVDE LL_PWR_EnablePVD
1170 * @retval None
1171 */
LL_PWR_EnablePVD(void)1172 __STATIC_INLINE void LL_PWR_EnablePVD(void)
1173 {
1174 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
1175 }
1176
1177 /**
1178 * @brief Disable the power voltage detector.
1179 * @rmtoll SVMCR PVDE LL_PWR_DisablePVD
1180 * @retval None
1181 */
LL_PWR_DisablePVD(void)1182 __STATIC_INLINE void LL_PWR_DisablePVD(void)
1183 {
1184 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
1185 }
1186
1187 /**
1188 * @brief Check if the power voltage detector is enabled.
1189 * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
1190 * @retval State of bit (1 or 0).
1191 */
LL_PWR_IsEnabledPVD(void)1192 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
1193 {
1194 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
1195 }
1196
1197 /**
1198 * @brief Enable the independent USB supply.
1199 * @rmtoll SVMCR USV LL_PWR_EnableVDDUSB
1200 * @retval None
1201 */
LL_PWR_EnableVDDUSB(void)1202 __STATIC_INLINE void LL_PWR_EnableVDDUSB(void)
1203 {
1204 SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1205 }
1206
1207 /**
1208 * @brief Disable the independent USB supply.
1209 * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB
1210 * @retval None
1211 */
LL_PWR_DisableVDDUSB(void)1212 __STATIC_INLINE void LL_PWR_DisableVDDUSB(void)
1213 {
1214 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
1215 }
1216
1217 /**
1218 * @brief Check if the independent USB supply is enabled.
1219 * @rmtoll SVMCR USV LL_PWR_IsEnabledVDDUSB
1220 * @retval State of bit (1 or 0).
1221 */
LL_PWR_IsEnabledVDDUSB(void)1222 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSB(void)
1223 {
1224 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL);
1225 }
1226
1227 /**
1228 * @brief Enable the independent I/Os supply.
1229 * @rmtoll SVMCR IO2SV LL_PWR_EnableVDDIO2
1230 * @retval None
1231 */
LL_PWR_EnableVDDIO2(void)1232 __STATIC_INLINE void LL_PWR_EnableVDDIO2(void)
1233 {
1234 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1235 }
1236
1237 /**
1238 * @brief Disable the independent I/Os supply.
1239 * @rmtoll SVMCR IO2SV LL_PWR_DisableVDDIO2
1240 * @retval None
1241 */
LL_PWR_DisableVDDIO2(void)1242 __STATIC_INLINE void LL_PWR_DisableVDDIO2(void)
1243 {
1244 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
1245 }
1246
1247 /**
1248 * @brief Check if the independent I/Os supply is enabled.
1249 * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVDDIO2
1250 * @retval State of bit (1 or 0).
1251 */
LL_PWR_IsEnabledVDDIO2(void)1252 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2(void)
1253 {
1254 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL);
1255 }
1256
1257 /**
1258 * @brief Enable the independent analog supply.
1259 * @rmtoll SVMCR ASV LL_PWR_EnableVDDA
1260 * @retval None
1261 */
LL_PWR_EnableVDDA(void)1262 __STATIC_INLINE void LL_PWR_EnableVDDA(void)
1263 {
1264 SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1265 }
1266
1267 /**
1268 * @brief Disable the independent analog supply.
1269 * @rmtoll SVMCR ASV LL_PWR_DisableVDDA
1270 * @retval None
1271 */
LL_PWR_DisableVDDA(void)1272 __STATIC_INLINE void LL_PWR_DisableVDDA(void)
1273 {
1274 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
1275 }
1276
1277 /**
1278 * @brief Check if the independent analog supply is enabled.
1279 * @rmtoll SVMCR ASV LL_PWR_IsEnabledVDDA
1280 * @retval State of bit (1 or 0).
1281 */
LL_PWR_IsEnabledVDDA(void)1282 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDA(void)
1283 {
1284 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL);
1285 }
1286
1287 /**
1288 * @brief Enable the independent USB supply monitor.
1289 * @rmtoll SVMCR UVMEN LL_PWR_EnableVDDUSBMonitor
1290 * @retval None
1291 */
LL_PWR_EnableVDDUSBMonitor(void)1292 __STATIC_INLINE void LL_PWR_EnableVDDUSBMonitor(void)
1293 {
1294 SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1295 }
1296
1297 /**
1298 * @brief Disable the independent USB supply monitor.
1299 * @rmtoll SVMCR UVMEN LL_PWR_DisableVDDUSBMonitor
1300 * @retval None
1301 */
LL_PWR_DisableVDDUSBMonitor(void)1302 __STATIC_INLINE void LL_PWR_DisableVDDUSBMonitor(void)
1303 {
1304 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
1305 }
1306
1307 /**
1308 * @brief Check if the independent USB supply monitor is enabled.
1309 * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVDDUSBMonitor
1310 * @retval State of bit (1 or 0).
1311 */
LL_PWR_IsEnabledVDDUSBMonitor(void)1312 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSBMonitor(void)
1313 {
1314 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL);
1315 }
1316
1317 /**
1318 * @brief Enable the independent I/Os supply monitor.
1319 * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVDDIO2Monitor
1320 * @retval None
1321 */
LL_PWR_EnableVDDIO2Monitor(void)1322 __STATIC_INLINE void LL_PWR_EnableVDDIO2Monitor(void)
1323 {
1324 SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1325 }
1326
1327 /**
1328 * @brief Disable the independent I/Os supply monitor.
1329 * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVDDIO2Monitor
1330 * @retval None
1331 */
LL_PWR_DisableVDDIO2Monitor(void)1332 __STATIC_INLINE void LL_PWR_DisableVDDIO2Monitor(void)
1333 {
1334 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
1335 }
1336
1337 /**
1338 * @brief Check if the independent I/Os supply monitor is enabled.
1339 * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVDDIO2Monitor
1340 * @retval State of bit (1 or 0).
1341 */
LL_PWR_IsEnabledVDDIO2Monitor(void)1342 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2Monitor(void)
1343 {
1344 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL);
1345 }
1346
1347 /**
1348 * @brief Enable the independent analog supply monitor 1.
1349 * @rmtoll SVMCR AVM1EN LL_PWR_EnableVDDAMonitor1
1350 * @retval None
1351 */
LL_PWR_EnableVDDAMonitor1(void)1352 __STATIC_INLINE void LL_PWR_EnableVDDAMonitor1(void)
1353 {
1354 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1355 }
1356
1357 /**
1358 * @brief Disable the independent analog supply monitor 1.
1359 * @rmtoll SVMCR AVM1EN LL_PWR_DisableVDDAMonitor1
1360 * @retval None
1361 */
LL_PWR_DisableVDDAMonitor1(void)1362 __STATIC_INLINE void LL_PWR_DisableVDDAMonitor1(void)
1363 {
1364 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
1365 }
1366
1367 /**
1368 * @brief Check if the independent analog supply monitor 1 is enabled.
1369 * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVDDAMonitor1
1370 * @retval State of bit (1 or 0).
1371 */
LL_PWR_IsEnabledVDDAMonitor1(void)1372 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor1(void)
1373 {
1374 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL);
1375 }
1376
1377 /**
1378 * @brief Enable the independent analog supply monitor 2.
1379 * @rmtoll SVMCR AVM2EN LL_PWR_EnableVDDAMonitor2
1380 * @retval None
1381 */
LL_PWR_EnableVDDAMonitor2(void)1382 __STATIC_INLINE void LL_PWR_EnableVDDAMonitor2(void)
1383 {
1384 SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1385 }
1386
1387 /**
1388 * @brief Disable the independent analog supply monitor 2.
1389 * @rmtoll SVMCR AVM2EN LL_PWR_DisableVDDAMonitor2
1390 * @retval None
1391 */
LL_PWR_DisableVDDAMonitor2(void)1392 __STATIC_INLINE void LL_PWR_DisableVDDAMonitor2(void)
1393 {
1394 CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
1395 }
1396
1397 /**
1398 * @brief Check if the independent analog supply monitor 2 is enabled.
1399 * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVDDAMonitor2
1400 * @retval State of bit (1 or 0).
1401 */
LL_PWR_IsEnabledVDDAMonitor2(void)1402 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor2(void)
1403 {
1404 return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL);
1405 }
1406
1407 /**
1408 * @brief Enable the wake up pin_x.
1409 * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
1410 * @param WakeUpPin This parameter can be a combination of the following values:
1411 * @arg @ref LL_PWR_WAKEUP_PIN1
1412 * @arg @ref LL_PWR_WAKEUP_PIN2
1413 * @arg @ref LL_PWR_WAKEUP_PIN3
1414 * @arg @ref LL_PWR_WAKEUP_PIN4
1415 * @arg @ref LL_PWR_WAKEUP_PIN5
1416 * @arg @ref LL_PWR_WAKEUP_PIN6
1417 * @arg @ref LL_PWR_WAKEUP_PIN7
1418 * @arg @ref LL_PWR_WAKEUP_PIN8
1419 * @retval None
1420 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1421 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1422 {
1423 SET_BIT(PWR->WUCR1, WakeUpPin);
1424 }
1425
1426 /**
1427 * @brief Disable the wake up pin_x.
1428 * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
1429 * @param WakeUpPin This parameter can be a combination of the following values:
1430 * @arg @ref LL_PWR_WAKEUP_PIN1
1431 * @arg @ref LL_PWR_WAKEUP_PIN2
1432 * @arg @ref LL_PWR_WAKEUP_PIN3
1433 * @arg @ref LL_PWR_WAKEUP_PIN4
1434 * @arg @ref LL_PWR_WAKEUP_PIN5
1435 * @arg @ref LL_PWR_WAKEUP_PIN6
1436 * @arg @ref LL_PWR_WAKEUP_PIN7
1437 * @arg @ref LL_PWR_WAKEUP_PIN8
1438 * @retval None
1439 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1440 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1441 {
1442 CLEAR_BIT(PWR->WUCR1, WakeUpPin);
1443 }
1444
1445 /**
1446 * @brief Check if the wake up pin_x is enabled.
1447 * @rmtoll WUCR1 WUPENx LL_PWR_IsEnableWakeUpPin
1448 * @param WakeUpPin This parameter can be one of the following values:
1449 * @arg @ref LL_PWR_WAKEUP_PIN1
1450 * @arg @ref LL_PWR_WAKEUP_PIN2
1451 * @arg @ref LL_PWR_WAKEUP_PIN3
1452 * @arg @ref LL_PWR_WAKEUP_PIN4
1453 * @arg @ref LL_PWR_WAKEUP_PIN5
1454 * @arg @ref LL_PWR_WAKEUP_PIN6
1455 * @arg @ref LL_PWR_WAKEUP_PIN7
1456 * @arg @ref LL_PWR_WAKEUP_PIN8
1457 * @retval State of bit (1 or 0).
1458 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1459 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1460 {
1461 return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1462 }
1463
1464 /**
1465 * @brief Set the wake up pin polarity low for the event detection.
1466 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
1467 * @param WakeUpPin This parameter can be a combination of the following values:
1468 * @arg @ref LL_PWR_WAKEUP_PIN1
1469 * @arg @ref LL_PWR_WAKEUP_PIN2
1470 * @arg @ref LL_PWR_WAKEUP_PIN3
1471 * @arg @ref LL_PWR_WAKEUP_PIN4
1472 * @arg @ref LL_PWR_WAKEUP_PIN5
1473 * @arg @ref LL_PWR_WAKEUP_PIN6
1474 * @arg @ref LL_PWR_WAKEUP_PIN7
1475 * @arg @ref LL_PWR_WAKEUP_PIN8
1476 * @retval None
1477 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1478 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1479 {
1480 SET_BIT(PWR->WUCR2, WakeUpPin);
1481 }
1482
1483 /**
1484 * @brief Set the wake up pin polarity high for the event detection.
1485 * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
1486 * @param WakeUpPin This parameter can be a combination of the following values:
1487 * @arg @ref LL_PWR_WAKEUP_PIN1
1488 * @arg @ref LL_PWR_WAKEUP_PIN2
1489 * @arg @ref LL_PWR_WAKEUP_PIN3
1490 * @arg @ref LL_PWR_WAKEUP_PIN4
1491 * @arg @ref LL_PWR_WAKEUP_PIN5
1492 * @arg @ref LL_PWR_WAKEUP_PIN6
1493 * @arg @ref LL_PWR_WAKEUP_PIN7
1494 * @arg @ref LL_PWR_WAKEUP_PIN8
1495 * @retval None
1496 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1497 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1498 {
1499 CLEAR_BIT(PWR->WUCR2, WakeUpPin);
1500 }
1501
1502 /**
1503 * @brief Get the wake up pin polarity for the event detection.
1504 * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
1505 * @param WakeUpPin This parameter can be one of the following values:
1506 * @arg @ref LL_PWR_WAKEUP_PIN1
1507 * @arg @ref LL_PWR_WAKEUP_PIN2
1508 * @arg @ref LL_PWR_WAKEUP_PIN3
1509 * @arg @ref LL_PWR_WAKEUP_PIN4
1510 * @arg @ref LL_PWR_WAKEUP_PIN5
1511 * @arg @ref LL_PWR_WAKEUP_PIN6
1512 * @arg @ref LL_PWR_WAKEUP_PIN7
1513 * @arg @ref LL_PWR_WAKEUP_PIN8
1514 * @retval State of bit (1 : polarity or 0 : polarity high).
1515 */
LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)1516 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
1517 {
1518 return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
1519 }
1520
1521 /**
1522 * @brief Set the wakeup pin_x selection 0.
1523 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
1524 * @param WakeUpPin This parameter can be one of the following values:
1525 * @arg @ref LL_PWR_WAKEUP_PIN1
1526 * @arg @ref LL_PWR_WAKEUP_PIN2
1527 * @arg @ref LL_PWR_WAKEUP_PIN3
1528 * @arg @ref LL_PWR_WAKEUP_PIN4
1529 * @arg @ref LL_PWR_WAKEUP_PIN5
1530 * @arg @ref LL_PWR_WAKEUP_PIN6
1531 * @arg @ref LL_PWR_WAKEUP_PIN7
1532 * @arg @ref LL_PWR_WAKEUP_PIN8
1533 * @retval None
1534 */
LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)1535 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
1536 {
1537 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
1538 (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
1539 }
1540
1541 /**
1542 * @brief Set the wakeup pin_x selection 1.
1543 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
1544 * @param WakeUpPin This parameter can be one of the following values:
1545 * @arg @ref LL_PWR_WAKEUP_PIN1
1546 * @arg @ref LL_PWR_WAKEUP_PIN2
1547 * @arg @ref LL_PWR_WAKEUP_PIN3
1548 * @arg @ref LL_PWR_WAKEUP_PIN4
1549 * @arg @ref LL_PWR_WAKEUP_PIN5
1550 * @arg @ref LL_PWR_WAKEUP_PIN6
1551 * @arg @ref LL_PWR_WAKEUP_PIN7
1552 * @arg @ref LL_PWR_WAKEUP_PIN8
1553 * @retval None
1554 */
LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)1555 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
1556 {
1557 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
1558 (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
1559 }
1560
1561 /**
1562 * @brief Set the wakeup pin_x selection 2.
1563 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
1564 * @param WakeUpPin This parameter can be one of the following values:
1565 * @arg @ref LL_PWR_WAKEUP_PIN1
1566 * @arg @ref LL_PWR_WAKEUP_PIN2
1567 * @arg @ref LL_PWR_WAKEUP_PIN3
1568 * @arg @ref LL_PWR_WAKEUP_PIN4
1569 * @arg @ref LL_PWR_WAKEUP_PIN5
1570 * @arg @ref LL_PWR_WAKEUP_PIN6
1571 * @arg @ref LL_PWR_WAKEUP_PIN7
1572 * @arg @ref LL_PWR_WAKEUP_PIN8
1573 * @retval None
1574 */
LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)1575 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
1576 {
1577 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
1578 (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
1579 }
1580
1581 /**
1582 * @brief Set the wakeup pin_x selection 3.
1583 * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
1584 * @param WakeUpPin This parameter can be one of the following values:
1585 * @arg @ref LL_PWR_WAKEUP_PIN1
1586 * @arg @ref LL_PWR_WAKEUP_PIN2
1587 * @arg @ref LL_PWR_WAKEUP_PIN3
1588 * @arg @ref LL_PWR_WAKEUP_PIN4
1589 * @arg @ref LL_PWR_WAKEUP_PIN5
1590 * @arg @ref LL_PWR_WAKEUP_PIN6
1591 * @arg @ref LL_PWR_WAKEUP_PIN7
1592 * @arg @ref LL_PWR_WAKEUP_PIN8
1593 * @retval None
1594 */
LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)1595 __STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
1596 {
1597 MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
1598 (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
1599 }
1600
1601 /**
1602 * @brief Get the wakeup pin_x selection.
1603 * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
1604 * @param WakeUpPin This parameter can be one of the following values:
1605 * @arg @ref LL_PWR_WAKEUP_PIN1
1606 * @arg @ref LL_PWR_WAKEUP_PIN2
1607 * @arg @ref LL_PWR_WAKEUP_PIN3
1608 * @arg @ref LL_PWR_WAKEUP_PIN4
1609 * @arg @ref LL_PWR_WAKEUP_PIN5
1610 * @arg @ref LL_PWR_WAKEUP_PIN6
1611 * @arg @ref LL_PWR_WAKEUP_PIN7
1612 * @arg @ref LL_PWR_WAKEUP_PIN8
1613 */
LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)1614 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
1615 {
1616 return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
1617 }
1618
1619 /**
1620 * @brief Enable backup regulator.
1621 * @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator
1622 * @note When this bit is set, the backup RAM content is kept in Standby and
1623 * VBAT modes. If BREN is reset, the backup RAM can still be used in
1624 * Run, Sleep and Stop modes. However, its content is lost in Standby,
1625 * Shutdown and VBAT modes. This bit can be written only when the
1626 * regulator is LDO, which must be configured before switching to SMPS.
1627 * @retval None
1628 */
LL_PWR_EnableBkUpRegulator(void)1629 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
1630 {
1631 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
1632 }
1633
1634 /**
1635 * @brief Disable backup regulator
1636 * @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator
1637 * @retval None
1638 */
LL_PWR_DisableBkUpRegulator(void)1639 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
1640 {
1641 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
1642 }
1643
1644 /**
1645 * @brief Check if the backup regulator is enabled
1646 * @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator
1647 * @retval State of bit (1 or 0).
1648 */
LL_PWR_IsEnabledBkUpRegulator(void)1649 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
1650 {
1651 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL);
1652 }
1653
1654 /**
1655 * @brief Enable the backup domain voltage and temperature monitoring.
1656 * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring
1657 * @retval None
1658 */
LL_PWR_EnableMonitoring(void)1659 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
1660 {
1661 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1662 }
1663
1664 /**
1665 * @brief Disable the backup domain voltage and temperature monitoring.
1666 * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring
1667 * @retval None
1668 */
LL_PWR_DisableMonitoring(void)1669 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
1670 {
1671 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
1672 }
1673
1674 /**
1675 * @brief Check if the backup domain voltage and temperature monitoring is
1676 * enabled.
1677 * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring
1678 * @retval State of bit (1 or 0).
1679 */
LL_PWR_IsEnabledMonitoring(void)1680 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
1681 {
1682 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
1683 }
1684
1685 /**
1686 * @brief Enable battery charging.
1687 * @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging
1688 * @retval None
1689 */
LL_PWR_EnableBatteryCharging(void)1690 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1691 {
1692 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1693 }
1694
1695 /**
1696 * @brief Disable battery charging.
1697 * @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging
1698 * @retval None
1699 */
LL_PWR_DisableBatteryCharging(void)1700 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1701 {
1702 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
1703 }
1704
1705 /**
1706 * @brief Check if battery charging is enabled.
1707 * @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging
1708 * @retval State of bit (1 or 0).
1709 */
LL_PWR_IsEnabledBatteryCharging(void)1710 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1711 {
1712 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Set the Battery charge resistor impedance
1717 * @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor
1718 * @param Resistor This parameter can be one of the following values:
1719 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1720 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
1721 * @retval None
1722 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)1723 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1724 {
1725 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor);
1726 }
1727
1728 /**
1729 * @brief Get the Battery charge resistor impedance
1730 * @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor
1731 * @retval Returned value can be one of the following values:
1732 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1733 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
1734 */
LL_PWR_GetBattChargResistor(void)1735 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1736 {
1737 return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS));
1738 }
1739
1740 /**
1741 * @brief Enable access to the backup domain.
1742 * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
1743 * @retval None
1744 */
LL_PWR_EnableBkUpAccess(void)1745 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
1746 {
1747 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
1748 }
1749
1750 /**
1751 * @brief Disable access to the backup domain.
1752 * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
1753 * @retval None
1754 */
LL_PWR_DisableBkUpAccess(void)1755 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
1756 {
1757 CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
1758 }
1759
1760 /**
1761 * @brief Check if the access to backup domain is enabled.
1762 * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
1763 * @retval State of bit (1 or 0).
1764 */
LL_PWR_IsEnabledBkUpAccess(void)1765 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
1766 {
1767 return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
1768 }
1769
1770 /**
1771 * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
1772 * @note This function must be called just before entering Standby mode.
1773 * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
1774 * @retval None
1775 */
LL_PWR_EnableUCPDStandbyMode(void)1776 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
1777 {
1778 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1779 }
1780
1781 /**
1782 * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
1783 * @note This function must be called after exiting Standby mode and before any
1784 * UCPD configuration update.
1785 * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
1786 * @retval None
1787 */
LL_PWR_DisableUCPDStandbyMode(void)1788 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
1789 {
1790 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
1791 }
1792
1793 /**
1794 * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
1795 * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
1796 * @retval State of bit (1 or 0).
1797 */
LL_PWR_IsEnabledUCPDStandbyMode(void)1798 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
1799 {
1800 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
1805 * on UCPD CC1 and CC2 pins.
1806 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
1807 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
1808 * to disable it in all cases, either to stop this pull-down or to hand over
1809 * control to the UCPD (which should therefore be initialized before doing the disable).
1810 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
1811 * @retval None
1812 */
LL_PWR_EnableUCPDDeadBattery(void)1813 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
1814 {
1815 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1816 }
1817
1818 /**
1819 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
1820 * on UCPD CC1 and CC2 pins.
1821 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
1822 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
1823 * to disable it in all cases, either to stop this pull-down or to hand over
1824 * control to the UCPD (which should therefore be initialized before doing the disable).
1825 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
1826 * @retval None
1827 */
LL_PWR_DisableUCPDDeadBattery(void)1828 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
1829 {
1830 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
1831 }
1832
1833 /**
1834 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
1835 * on UCPD CC1 and CC2 pins.
1836 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
1837 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
1838 * to disable it in all cases, either to stop this pull-down or to hand over
1839 * control to the UCPD (which should therefore be initialized before doing the disable).
1840 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
1841 * @retval State of feature (1 : enabled; 0 : disabled).
1842 */
LL_PWR_IsEnabledUCPDDeadBattery(void)1843 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
1844 {
1845 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
1846 }
1847
1848 /**
1849 * @brief Enable the pull-up and pull-down configuration.
1850 * @rmtoll APCR APC LL_PWR_EnablePUPDConfig
1851 * @retval None
1852 */
LL_PWR_EnablePUPDConfig(void)1853 __STATIC_INLINE void LL_PWR_EnablePUPDConfig(void)
1854 {
1855 SET_BIT(PWR->APCR, PWR_APCR_APC);
1856 }
1857
1858 /**
1859 * @brief Disable the pull-up and pull-down configuration.
1860 * @rmtoll APCR APC LL_PWR_DisablePUPDConfig
1861 * @retval None
1862 */
LL_PWR_DisablePUPDConfig(void)1863 __STATIC_INLINE void LL_PWR_DisablePUPDConfig(void)
1864 {
1865 CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
1866 }
1867
1868 /**
1869 * @brief Check if the pull-up and pull-down configuration is enabled.
1870 * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig
1871 * @retval State of bit (1 or 0).
1872 */
LL_PWR_IsEnabledPUPDConfig(void)1873 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void)
1874 {
1875 return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL);
1876 }
1877
1878 /**
1879 * @brief Enable GPIO pull-up in Standby and Shutdown modes
1880 * @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp
1881 * @param GPIOPort This parameter can be one of the following values:
1882 * @arg @ref LL_PWR_GPIO_PORTA
1883 * @arg @ref LL_PWR_GPIO_PORTB
1884 * @arg @ref LL_PWR_GPIO_PORTC
1885 * @arg @ref LL_PWR_GPIO_PORTD
1886 * @arg @ref LL_PWR_GPIO_PORTE
1887 * @arg @ref LL_PWR_GPIO_PORTF
1888 * @arg @ref LL_PWR_GPIO_PORTG
1889 * @arg @ref LL_PWR_GPIO_PORTH
1890 * @arg @ref LL_PWR_GPIO_PORTI
1891 * @param GPIOPin This parameter can be a combination of the following values:
1892 * @arg @ref LL_PWR_GPIO_PIN_0
1893 * @arg @ref LL_PWR_GPIO_PIN_1
1894 * @arg @ref LL_PWR_GPIO_PIN_2
1895 * @arg @ref LL_PWR_GPIO_PIN_3
1896 * @arg @ref LL_PWR_GPIO_PIN_4
1897 * @arg @ref LL_PWR_GPIO_PIN_5
1898 * @arg @ref LL_PWR_GPIO_PIN_6
1899 * @arg @ref LL_PWR_GPIO_PIN_7
1900 * @arg @ref LL_PWR_GPIO_PIN_8
1901 * @arg @ref LL_PWR_GPIO_PIN_9
1902 * @arg @ref LL_PWR_GPIO_PIN_10
1903 * @arg @ref LL_PWR_GPIO_PIN_11
1904 * @arg @ref LL_PWR_GPIO_PIN_12
1905 * @arg @ref LL_PWR_GPIO_PIN_13
1906 * @arg @ref LL_PWR_GPIO_PIN_14
1907 * @arg @ref LL_PWR_GPIO_PIN_15
1908 * @retval None.
1909 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)1910 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
1911 {
1912 SET_BIT(*((uint32_t *)GPIOPort), GPIOPin);
1913 }
1914
1915 /**
1916 * @brief Disable GPIO pull-up in Standby and Shutdown modes
1917 * @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp
1918 * @param GPIOPort This parameter can be one of the following values:
1919 * @arg @ref LL_PWR_GPIO_PORTA
1920 * @arg @ref LL_PWR_GPIO_PORTB
1921 * @arg @ref LL_PWR_GPIO_PORTC
1922 * @arg @ref LL_PWR_GPIO_PORTD
1923 * @arg @ref LL_PWR_GPIO_PORTE
1924 * @arg @ref LL_PWR_GPIO_PORTF
1925 * @arg @ref LL_PWR_GPIO_PORTG
1926 * @arg @ref LL_PWR_GPIO_PORTH
1927 * @arg @ref LL_PWR_GPIO_PORTI
1928 * @param GPIOPin This parameter can be a combination of the following values:
1929 * @arg @ref LL_PWR_GPIO_PIN_0
1930 * @arg @ref LL_PWR_GPIO_PIN_1
1931 * @arg @ref LL_PWR_GPIO_PIN_2
1932 * @arg @ref LL_PWR_GPIO_PIN_3
1933 * @arg @ref LL_PWR_GPIO_PIN_4
1934 * @arg @ref LL_PWR_GPIO_PIN_5
1935 * @arg @ref LL_PWR_GPIO_PIN_6
1936 * @arg @ref LL_PWR_GPIO_PIN_7
1937 * @arg @ref LL_PWR_GPIO_PIN_8
1938 * @arg @ref LL_PWR_GPIO_PIN_9
1939 * @arg @ref LL_PWR_GPIO_PIN_10
1940 * @arg @ref LL_PWR_GPIO_PIN_11
1941 * @arg @ref LL_PWR_GPIO_PIN_12
1942 * @arg @ref LL_PWR_GPIO_PIN_13
1943 * @arg @ref LL_PWR_GPIO_PIN_14
1944 * @arg @ref LL_PWR_GPIO_PIN_15
1945 * @retval None.
1946 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)1947 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
1948 {
1949 CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin);
1950 }
1951
1952 /**
1953 * @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled
1954 * @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp
1955 * @param GPIOPort This parameter can be one of the following values:
1956 * @arg @ref LL_PWR_GPIO_PORTA
1957 * @arg @ref LL_PWR_GPIO_PORTB
1958 * @arg @ref LL_PWR_GPIO_PORTC
1959 * @arg @ref LL_PWR_GPIO_PORTD
1960 * @arg @ref LL_PWR_GPIO_PORTE
1961 * @arg @ref LL_PWR_GPIO_PORTF
1962 * @arg @ref LL_PWR_GPIO_PORTG
1963 * @arg @ref LL_PWR_GPIO_PORTH
1964 * @arg @ref LL_PWR_GPIO_PORTI
1965 * @param GPIOPin This parameter can be one of the following values:
1966 * @arg @ref LL_PWR_GPIO_PIN_0
1967 * @arg @ref LL_PWR_GPIO_PIN_1
1968 * @arg @ref LL_PWR_GPIO_PIN_2
1969 * @arg @ref LL_PWR_GPIO_PIN_3
1970 * @arg @ref LL_PWR_GPIO_PIN_4
1971 * @arg @ref LL_PWR_GPIO_PIN_5
1972 * @arg @ref LL_PWR_GPIO_PIN_6
1973 * @arg @ref LL_PWR_GPIO_PIN_7
1974 * @arg @ref LL_PWR_GPIO_PIN_8
1975 * @arg @ref LL_PWR_GPIO_PIN_9
1976 * @arg @ref LL_PWR_GPIO_PIN_10
1977 * @arg @ref LL_PWR_GPIO_PIN_11
1978 * @arg @ref LL_PWR_GPIO_PIN_12
1979 * @arg @ref LL_PWR_GPIO_PIN_13
1980 * @arg @ref LL_PWR_GPIO_PIN_14
1981 * @arg @ref LL_PWR_GPIO_PIN_15
1982 * @retval State of bit (1 or 0).
1983 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort,uint32_t GPIOPin)1984 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
1985 {
1986 return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
1987 }
1988
1989 /**
1990 * @brief Enable GPIO pull-down in Standby and Shutdown modes.
1991 * @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown
1992 * @param GPIOPort This parameter can be one of the following values:
1993 * @arg @ref LL_PWR_GPIO_PORTA
1994 * @arg @ref LL_PWR_GPIO_PORTB
1995 * @arg @ref LL_PWR_GPIO_PORTC
1996 * @arg @ref LL_PWR_GPIO_PORTD
1997 * @arg @ref LL_PWR_GPIO_PORTE
1998 * @arg @ref LL_PWR_GPIO_PORTF
1999 * @arg @ref LL_PWR_GPIO_PORTG
2000 * @arg @ref LL_PWR_GPIO_PORTH
2001 * @arg @ref LL_PWR_GPIO_PORTI
2002 * @param GPIOPin This parameter can be a combination of the following values:
2003 * @arg @ref LL_PWR_GPIO_PIN_0
2004 * @arg @ref LL_PWR_GPIO_PIN_1
2005 * @arg @ref LL_PWR_GPIO_PIN_2
2006 * @arg @ref LL_PWR_GPIO_PIN_3
2007 * @arg @ref LL_PWR_GPIO_PIN_4
2008 * @arg @ref LL_PWR_GPIO_PIN_5
2009 * @arg @ref LL_PWR_GPIO_PIN_6
2010 * @arg @ref LL_PWR_GPIO_PIN_7
2011 * @arg @ref LL_PWR_GPIO_PIN_8
2012 * @arg @ref LL_PWR_GPIO_PIN_9
2013 * @arg @ref LL_PWR_GPIO_PIN_10
2014 * @arg @ref LL_PWR_GPIO_PIN_11
2015 * @arg @ref LL_PWR_GPIO_PIN_12
2016 * @arg @ref LL_PWR_GPIO_PIN_13
2017 * @arg @ref LL_PWR_GPIO_PIN_14
2018 * @arg @ref LL_PWR_GPIO_PIN_15
2019 * @retval None.
2020 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2021 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2022 {
2023 SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
2024 }
2025
2026 /**
2027 * @brief Disable GPIO pull-down in Standby and Shutdown modes.
2028 * @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown
2029 * @param GPIOPort This parameter can be one of the following values:
2030 * @arg @ref LL_PWR_GPIO_PORTA
2031 * @arg @ref LL_PWR_GPIO_PORTB
2032 * @arg @ref LL_PWR_GPIO_PORTC
2033 * @arg @ref LL_PWR_GPIO_PORTD
2034 * @arg @ref LL_PWR_GPIO_PORTE
2035 * @arg @ref LL_PWR_GPIO_PORTF
2036 * @arg @ref LL_PWR_GPIO_PORTG
2037 * @arg @ref LL_PWR_GPIO_PORTH
2038 * @arg @ref LL_PWR_GPIO_PORTI
2039 * @param GPIOPin This parameter can be a combination of the following values:
2040 * @arg @ref LL_PWR_GPIO_PIN_0
2041 * @arg @ref LL_PWR_GPIO_PIN_1
2042 * @arg @ref LL_PWR_GPIO_PIN_2
2043 * @arg @ref LL_PWR_GPIO_PIN_3
2044 * @arg @ref LL_PWR_GPIO_PIN_4
2045 * @arg @ref LL_PWR_GPIO_PIN_5
2046 * @arg @ref LL_PWR_GPIO_PIN_6
2047 * @arg @ref LL_PWR_GPIO_PIN_7
2048 * @arg @ref LL_PWR_GPIO_PIN_8
2049 * @arg @ref LL_PWR_GPIO_PIN_9
2050 * @arg @ref LL_PWR_GPIO_PIN_10
2051 * @arg @ref LL_PWR_GPIO_PIN_11
2052 * @arg @ref LL_PWR_GPIO_PIN_12
2053 * @arg @ref LL_PWR_GPIO_PIN_13
2054 * @arg @ref LL_PWR_GPIO_PIN_14
2055 * @arg @ref LL_PWR_GPIO_PIN_15
2056 * @retval None.
2057 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2058 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2059 {
2060 CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
2061 }
2062
2063 /**
2064 * @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled
2065 * @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp
2066 * @param GPIOPort This parameter can be one of the following values:
2067 * @arg @ref LL_PWR_GPIO_PORTA
2068 * @arg @ref LL_PWR_GPIO_PORTB
2069 * @arg @ref LL_PWR_GPIO_PORTC
2070 * @arg @ref LL_PWR_GPIO_PORTD
2071 * @arg @ref LL_PWR_GPIO_PORTE
2072 * @arg @ref LL_PWR_GPIO_PORTF
2073 * @arg @ref LL_PWR_GPIO_PORTG
2074 * @arg @ref LL_PWR_GPIO_PORTH
2075 * @arg @ref LL_PWR_GPIO_PORTI
2076 * @param GPIOPin This parameter can be one of the following values:
2077 * @arg @ref LL_PWR_GPIO_PIN_0
2078 * @arg @ref LL_PWR_GPIO_PIN_1
2079 * @arg @ref LL_PWR_GPIO_PIN_2
2080 * @arg @ref LL_PWR_GPIO_PIN_3
2081 * @arg @ref LL_PWR_GPIO_PIN_4
2082 * @arg @ref LL_PWR_GPIO_PIN_5
2083 * @arg @ref LL_PWR_GPIO_PIN_6
2084 * @arg @ref LL_PWR_GPIO_PIN_7
2085 * @arg @ref LL_PWR_GPIO_PIN_8
2086 * @arg @ref LL_PWR_GPIO_PIN_9
2087 * @arg @ref LL_PWR_GPIO_PIN_10
2088 * @arg @ref LL_PWR_GPIO_PIN_11
2089 * @arg @ref LL_PWR_GPIO_PIN_12
2090 * @arg @ref LL_PWR_GPIO_PIN_13
2091 * @arg @ref LL_PWR_GPIO_PIN_14
2092 * @arg @ref LL_PWR_GPIO_PIN_15
2093 * @retval State of bit (1 or 0).
2094 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort,uint32_t GPIOPin)2095 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
2096 {
2097 return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
2098 }
2099
2100 /**
2101 * @brief Get currently voltage scaling applied to VCORE.
2102 * @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS
2103 * @retval Returned value can be one of the following values:
2104 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
2105 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
2106 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
2107 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
2108 */
LL_PWR_GetRegulCurrentVOS(void)2109 __STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
2110 {
2111 return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
2112 }
2113 /**
2114 * @}
2115 */
2116
2117 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
2118 * @{
2119 */
2120
2121 /**
2122 * @brief Indicate whether the EPOD (Embedded Power Distribution) booster is
2123 * ready OR not.
2124 * @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST
2125 * @retval State of bit (1 or 0).
2126 */
LL_PWR_IsActiveFlag_BOOST(void)2127 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void)
2128 {
2129 return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL);
2130 }
2131
2132 /**
2133 * @brief Indicate whether the regulator voltage output is above voltage
2134 * scaling range or not.
2135 * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
2136 * @retval State of bit (1 or 0).
2137 */
LL_PWR_IsActiveFlag_VOS(void)2138 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2139 {
2140 return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
2141 }
2142
2143 /**
2144 * @brief Indicate whether the system was in standby mode or not.
2145 * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
2146 * @retval State of bit (1 or 0).
2147 */
LL_PWR_IsActiveFlag_SB(void)2148 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
2149 {
2150 return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
2151 }
2152
2153 /**
2154 * @brief Indicate whether the system was in stop mode or not.
2155 * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
2156 * @retval State of bit (1 or 0).
2157 */
LL_PWR_IsActiveFlag_STOP(void)2158 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
2159 {
2160 return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
2161 }
2162
2163 /**
2164 * @brief Indicate whether the regulator supply is LDO or SMPS.
2165 * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
2166 * @retval State of bit (1 or 0).
2167 */
LL_PWR_IsActiveFlag_REGULATOR(void)2168 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
2169 {
2170 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
2171 }
2172
2173 /**
2174 * @brief Indicate whether the VDD voltage is below the threshold or not.
2175 * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
2176 * @retval State of bit (1 or 0).
2177 */
LL_PWR_IsActiveFlag_PVDO(void)2178 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
2179 {
2180 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
2181 }
2182
2183 /**
2184 * @brief Indicate whether the regulator voltage output is equal to current
2185 * used voltage scaling range or not.
2186 * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
2187 * @retval State of bit (1 or 0).
2188 */
LL_PWR_IsActiveFlag_ACTVOS(void)2189 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
2190 {
2191 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
2192 }
2193
2194 /**
2195 * @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
2196 * @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB
2197 * @retval State of bit (1 or 0).
2198 */
LL_PWR_IsActiveFlag_VDDUSB(void)2199 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
2200 {
2201 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL);
2202 }
2203
2204 /**
2205 * @brief Indicate whether the VDDIO2 is below the threshold of monitor or not.
2206 * @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
2207 * @retval State of bit (1 or 0).
2208 */
LL_PWR_IsActiveFlag_VDDIO2(void)2209 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
2210 {
2211 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL);
2212 }
2213
2214 /**
2215 * @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or
2216 * not.
2217 * @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1
2218 * @retval State of bit (1 or 0).
2219 */
LL_PWR_IsActiveFlag_VDDA1(void)2220 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void)
2221 {
2222 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL);
2223 }
2224
2225 /**
2226 * @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or
2227 * not.
2228 * @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2
2229 * @retval State of bit (1 or 0).
2230 */
LL_PWR_IsActiveFlag_VDDA2(void)2231 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void)
2232 {
2233 return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL);
2234 }
2235
2236 /**
2237 * @brief Indicate whether the VBAT level is below high threshold or not.
2238 * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
2239 * @retval State of bit (1 or 0).
2240 */
LL_PWR_IsActiveFlag_VBATH(void)2241 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
2242 {
2243 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
2244 }
2245
2246 /**
2247 * @brief Indicate whether the CPU temperature level is above low threshold or
2248 * not.
2249 * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
2250 * @retval State of bit (1 or 0).
2251 */
LL_PWR_IsActiveFlag_TEMPL(void)2252 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
2253 {
2254 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
2255 }
2256
2257 /**
2258 * @brief Indicate whether the CPU temperature level is below high threshold
2259 * or not.
2260 * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
2261 * @retval State of bit (1 or 0).
2262 */
LL_PWR_IsActiveFlag_TEMPH(void)2263 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
2264 {
2265 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
2266 }
2267
2268 /**
2269 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
2270 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
2271 * @retval State of bit (1 or 0).
2272 */
LL_PWR_IsActiveFlag_WU1(void)2273 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
2274 {
2275 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
2276 }
2277
2278 /**
2279 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
2280 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
2281 * @retval State of bit (1 or 0).
2282 */
LL_PWR_IsActiveFlag_WU2(void)2283 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
2284 {
2285 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
2286 }
2287
2288 /**
2289 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
2290 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
2291 * @retval State of bit (1 or 0).
2292 */
LL_PWR_IsActiveFlag_WU3(void)2293 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
2294 {
2295 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
2300 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
2301 * @retval State of bit (1 or 0).
2302 */
LL_PWR_IsActiveFlag_WU4(void)2303 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
2304 {
2305 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
2306 }
2307
2308 /**
2309 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
2310 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
2311 * @retval State of bit (1 or 0).
2312 */
LL_PWR_IsActiveFlag_WU5(void)2313 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
2314 {
2315 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
2316 }
2317
2318 /**
2319 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
2320 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
2321 * @retval State of bit (1 or 0).
2322 */
LL_PWR_IsActiveFlag_WU6(void)2323 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
2324 {
2325 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
2326 }
2327
2328 /**
2329 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
2330 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
2331 * @retval State of bit (1 or 0).
2332 */
LL_PWR_IsActiveFlag_WU7(void)2333 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
2334 {
2335 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
2336 }
2337
2338 /**
2339 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
2340 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
2341 * @retval State of bit (1 or 0).
2342 */
LL_PWR_IsActiveFlag_WU8(void)2343 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
2344 {
2345 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
2346 }
2347
2348 /**
2349 * @brief Clear stop flag.
2350 * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
2351 * @retval None
2352 */
LL_PWR_ClearFlag_STOP(void)2353 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
2354 {
2355 WRITE_REG(PWR->SR, PWR_SR_CSSF);
2356 }
2357
2358 /**
2359 * @brief Clear standby flag.
2360 * @rmtoll SR CSSF LL_PWR_ClearFlag_SB
2361 * @retval None
2362 */
LL_PWR_ClearFlag_SB(void)2363 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
2364 {
2365 WRITE_REG(PWR->SR, PWR_SR_CSSF);
2366 }
2367
2368 /**
2369 * @brief Clear wake up flag 1.
2370 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
2371 * @retval None
2372 */
LL_PWR_ClearFlag_WU1(void)2373 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2374 {
2375 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
2376 }
2377
2378 /**
2379 * @brief Clear wake up flag 2.
2380 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
2381 * @retval None
2382 */
LL_PWR_ClearFlag_WU2(void)2383 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2384 {
2385 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
2386 }
2387
2388 /**
2389 * @brief Clear wake up flag 3.
2390 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
2391 * @retval None
2392 */
LL_PWR_ClearFlag_WU3(void)2393 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2394 {
2395 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
2396 }
2397
2398 /**
2399 * @brief Clear wake up flag 4.
2400 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
2401 * @retval None
2402 */
LL_PWR_ClearFlag_WU4(void)2403 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2404 {
2405 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
2406 }
2407
2408 /**
2409 * @brief Clear wake up flag 5.
2410 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
2411 * @retval None
2412 */
LL_PWR_ClearFlag_WU5(void)2413 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
2414 {
2415 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
2416 }
2417
2418 /**
2419 * @brief Clear wake up flag 6.
2420 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
2421 * @retval None
2422 */
LL_PWR_ClearFlag_WU6(void)2423 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
2424 {
2425 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
2426 }
2427
2428 /**
2429 * @brief Clear wake up flag 7.
2430 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
2431 * @retval None
2432 */
LL_PWR_ClearFlag_WU7(void)2433 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
2434 {
2435 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
2436 }
2437
2438 /**
2439 * @brief Clear wake up flag 8.
2440 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
2441 * @retval None
2442 */
LL_PWR_ClearFlag_WU8(void)2443 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
2444 {
2445 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
2446 }
2447
2448 /**
2449 * @brief Clear all wake up flags.
2450 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
2451 * @retval None
2452 */
LL_PWR_ClearFlag_WU(void)2453 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
2454 {
2455 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
2456 }
2457 /**
2458 * @}
2459 */
2460
2461 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
2462 * @{
2463 */
2464
2465 /**
2466 * @brief Enable privileged mode for nsecure items.
2467 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
2468 * @retval None
2469 */
LL_PWR_EnableNSecurePrivilege(void)2470 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
2471 {
2472 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
2473 }
2474
2475 /**
2476 * @brief Disable privileged mode for nsecure items.
2477 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
2478 * @retval None
2479 */
LL_PWR_DisableNSecurePrivilege(void)2480 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
2481 {
2482 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
2483 }
2484
2485 /**
2486 * @brief Check if privileged mode for nsecure items is enabled.
2487 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
2488 * @retval State of bit (1 or 0).
2489 */
LL_PWR_IsEnabledNSecurePrivilege(void)2490 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
2491 {
2492 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
2493 }
2494
2495 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2496 /**
2497 * @brief Enable privileged mode for secure items.
2498 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
2499 * @retval None
2500 */
LL_PWR_EnableSecurePrivilege(void)2501 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
2502 {
2503 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
2504 }
2505
2506 /**
2507 * @brief Disable privileged mode for secure items.
2508 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
2509 * @retval None
2510 */
LL_PWR_DisableSecurePrivilege(void)2511 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
2512 {
2513 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
2514 }
2515 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2516
2517 /**
2518 * @brief Check if privileged mode for secure items is enabled.
2519 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
2520 * @retval State of bit (1 or 0).
2521 */
LL_PWR_IsEnabledSecurePrivilege(void)2522 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
2523 {
2524 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
2525 }
2526
2527 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2528 /**
2529 * @brief Configure secure attribute mode.
2530 * @note This API can be executed only by CPU in secure mode.
2531 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
2532 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
2533 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
2534 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
2535 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
2536 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
2537 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
2538 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
2539 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
2540 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
2541 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
2542 * SECCFGR APCSEC LL_PWR_ConfigSecure
2543 * @param SecureConfig This parameter can be the full combination
2544 * of the following values:
2545 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
2546 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
2547 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
2548 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
2549 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
2550 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
2551 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
2552 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
2553 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
2554 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
2555 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
2556 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
2557 * @retval None.
2558 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)2559 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
2560 {
2561 WRITE_REG(PWR->SECCFGR, SecureConfig);
2562 }
2563
2564 /**
2565 * @brief Get secure attribute configuration.
2566 * @note This API can be executed only by CPU in secure mode.
2567 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
2568 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
2569 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
2570 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
2571 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
2572 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
2573 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
2574 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
2575 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
2576 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
2577 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
2578 * SECCFGR APCSEC LL_PWR_GetConfigSecure
2579 * @retval Returned value is the combination of the following values:
2580 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
2581 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
2582 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
2583 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
2584 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
2585 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
2586 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
2587 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
2588 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
2589 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
2590 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
2591 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
2592 */
LL_PWR_GetConfigSecure(void)2593 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
2594 {
2595 return (READ_REG(PWR->SECCFGR));
2596 }
2597 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2598 /**
2599 * @}
2600 */
2601
2602 #if defined (USE_FULL_LL_DRIVER)
2603 /** @defgroup PWR_LL_EF_Init De-initialization function
2604 * @{
2605 */
2606 ErrorStatus LL_PWR_DeInit(void);
2607 /**
2608 * @}
2609 */
2610 #endif /* defined (USE_FULL_LL_DRIVER) */
2611
2612
2613 /**
2614 * @}
2615 */
2616
2617 /**
2618 * @}
2619 */
2620
2621 #endif /* defined (PWR) */
2622
2623 /**
2624 * @}
2625 */
2626
2627 #ifdef __cplusplus
2628 }
2629 #endif /* __cplusplus */
2630
2631 #endif /* STM32U5xx_LL_PWR_H */
2632
