1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_dma2d.h 4 * @author MCD Application Team 5 * @brief Header file of DMA2D HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_DMA2D_H 21 #define STM32U5xx_HAL_DMA2D_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA2D) 35 36 /** @addtogroup DMA2D DMA2D 37 * @brief DMA2D HAL module driver 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 43 * @{ 44 */ 45 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 46 47 /** 48 * @brief DMA2D CLUT Structure definition 49 */ 50 typedef struct 51 { 52 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 53 54 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 55 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 56 57 uint32_t Size; /*!< Configures the DMA2D CLUT size. 58 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 59 } DMA2D_CLUTCfgTypeDef; 60 61 /** 62 * @brief DMA2D Init structure definition 63 */ 64 typedef struct 65 { 66 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 67 This parameter can be one value of @ref DMA2D_Mode. */ 68 69 uint32_t ColorMode; /*!< Configures the color format of the output image. 70 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 71 72 uint32_t OutputOffset; /*!< Specifies the Offset value. 73 This parameter must be a number between 74 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 75 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 76 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 77 78 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 79 for the output pixel format converter. 80 This parameter can be one value of @ref DMA2D_RB_Swap. */ 81 82 83 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 84 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 85 86 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 87 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 88 89 } DMA2D_InitTypeDef; 90 91 92 /** 93 * @brief DMA2D Layer structure definition 94 */ 95 typedef struct 96 { 97 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 98 This parameter must be a number between 99 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 100 101 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 102 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 103 104 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 105 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 106 107 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 108 in case of A8 or A4 color mode. 109 This parameter must be a number between Min_Data = 0x00 110 and Max_Data = 0xFF except for the color modes detailed below. 111 @note In case of A8 or A4 color mode (ARGB), 112 this parameter must be a number between 113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 115 - InputAlpha[16:23] is the red value RED[0:7] 116 - InputAlpha[8:15] is the green value GREEN[0:7] 117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 118 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 119 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 120 121 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 122 This parameter can be one value of @ref DMA2D_RB_Swap. */ 123 124 125 } DMA2D_LayerCfgTypeDef; 126 127 /** 128 * @brief HAL DMA2D State structures definition 129 */ 130 typedef enum 131 { 132 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 133 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 134 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 135 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 136 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 137 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 138 } HAL_DMA2D_StateTypeDef; 139 140 /** 141 * @brief DMA2D handle Structure definition 142 */ 143 typedef struct __DMA2D_HandleTypeDef 144 { 145 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 146 147 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 148 149 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 150 151 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 152 153 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 154 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 155 156 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 157 158 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 159 160 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 161 162 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 163 164 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 167 168 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 169 170 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 171 } DMA2D_HandleTypeDef; 172 173 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 174 /** 175 * @brief HAL DMA2D Callback pointer definition 176 */ 177 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 178 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 179 /** 180 * @} 181 */ 182 183 /* Exported constants --------------------------------------------------------*/ 184 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 185 * @{ 186 */ 187 188 /** @defgroup DMA2D_Error_Code DMA2D Error Code 189 * @{ 190 */ 191 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 192 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 193 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 194 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 195 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 196 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 197 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 198 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 199 200 /** 201 * @} 202 */ 203 204 /** @defgroup DMA2D_Mode DMA2D Mode 205 * @{ 206 */ 207 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 208 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 209 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 210 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 211 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 212 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 218 * @{ 219 */ 220 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 221 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 222 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 223 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 224 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 230 * @{ 231 */ 232 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 233 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 234 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 235 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 236 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 237 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 238 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 239 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 240 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 241 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 242 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 243 /** 244 * @} 245 */ 246 247 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 248 * @{ 249 */ 250 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 251 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 252 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 253 with original alpha channel value */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 259 * @{ 260 */ 261 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 262 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 263 /** 264 * @} 265 */ 266 267 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 268 * @{ 269 */ 270 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 271 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 272 /** 273 * @} 274 */ 275 276 277 278 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 279 * @{ 280 */ 281 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 282 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 288 * @{ 289 */ 290 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 291 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 292 /** 293 * @} 294 */ 295 296 297 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 298 * @{ 299 */ 300 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 301 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 302 /** 303 * @} 304 */ 305 306 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 307 * @{ 308 */ 309 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 310 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 311 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 312 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 313 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 314 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup DMA2D_Flags DMA2D Flags 320 * @{ 321 */ 322 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 323 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 324 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 325 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 326 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 327 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 328 /** 329 * @} 330 */ 331 332 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 333 /** 334 * @brief HAL DMA2D common Callback ID enumeration definition 335 */ 336 typedef enum 337 { 338 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 339 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 340 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 341 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 342 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 343 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 344 } HAL_DMA2D_CallbackIDTypeDef; 345 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 346 347 348 /** 349 * @} 350 */ 351 /* Exported macros ------------------------------------------------------------*/ 352 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 353 * @{ 354 */ 355 356 /** @brief Reset DMA2D handle state 357 * @param __HANDLE__ specifies the DMA2D handle. 358 * @retval None 359 */ 360 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 361 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 362 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 363 (__HANDLE__)->MspInitCallback = NULL; \ 364 (__HANDLE__)->MspDeInitCallback = NULL; \ 365 }while(0) 366 #else 367 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 368 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 369 370 371 /** 372 * @brief Enable the DMA2D. 373 * @param __HANDLE__ DMA2D handle 374 * @retval None. 375 */ 376 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 377 378 379 /* Interrupt & Flag management */ 380 /** 381 * @brief Get the DMA2D pending flags. 382 * @param __HANDLE__ DMA2D handle 383 * @param __FLAG__ flag to check. 384 * This parameter can be any combination of the following values: 385 * @arg DMA2D_FLAG_CE: Configuration error flag 386 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 387 * @arg DMA2D_FLAG_CAE: CLUT access error flag 388 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 389 * @arg DMA2D_FLAG_TC: Transfer complete flag 390 * @arg DMA2D_FLAG_TE: Transfer error flag 391 * @retval The state of FLAG. 392 */ 393 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 394 395 /** 396 * @brief Clear the DMA2D pending flags. 397 * @param __HANDLE__ DMA2D handle 398 * @param __FLAG__ specifies the flag to clear. 399 * This parameter can be any combination of the following values: 400 * @arg DMA2D_FLAG_CE: Configuration error flag 401 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 402 * @arg DMA2D_FLAG_CAE: CLUT access error flag 403 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 404 * @arg DMA2D_FLAG_TC: Transfer complete flag 405 * @arg DMA2D_FLAG_TE: Transfer error flag 406 * @retval None 407 */ 408 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 409 410 /** 411 * @brief Enable the specified DMA2D interrupts. 412 * @param __HANDLE__ DMA2D handle 413 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 414 * This parameter can be any combination of the following values: 415 * @arg DMA2D_IT_CE: Configuration error interrupt mask 416 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 417 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 418 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 419 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 420 * @arg DMA2D_IT_TE: Transfer error interrupt mask 421 * @retval None 422 */ 423 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 424 425 /** 426 * @brief Disable the specified DMA2D interrupts. 427 * @param __HANDLE__ DMA2D handle 428 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 429 * This parameter can be any combination of the following values: 430 * @arg DMA2D_IT_CE: Configuration error interrupt mask 431 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 432 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 433 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 434 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 435 * @arg DMA2D_IT_TE: Transfer error interrupt mask 436 * @retval None 437 */ 438 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 439 440 /** 441 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 442 * @param __HANDLE__ DMA2D handle 443 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 444 * This parameter can be one of the following values: 445 * @arg DMA2D_IT_CE: Configuration error interrupt mask 446 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 447 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 448 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 449 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 450 * @arg DMA2D_IT_TE: Transfer error interrupt mask 451 * @retval The state of INTERRUPT source. 452 */ 453 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 454 455 /** 456 * @} 457 */ 458 459 /* Exported functions --------------------------------------------------------*/ 460 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 461 * @{ 462 */ 463 464 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 465 * @{ 466 */ 467 468 /* Initialization and de-initialization functions *******************************/ 469 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 470 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 471 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 472 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 473 /* Callbacks Register/UnRegister functions ***********************************/ 474 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 475 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 476 pDMA2D_CallbackTypeDef pCallback); 477 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 478 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 479 480 /** 481 * @} 482 */ 483 484 485 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 486 * @{ 487 */ 488 489 /* IO operation functions *******************************************************/ 490 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 491 uint32_t Height); 492 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 493 uint32_t DstAddress, uint32_t Width, uint32_t Height); 494 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 495 uint32_t Height); 496 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 497 uint32_t DstAddress, uint32_t Width, uint32_t Height); 498 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 499 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 500 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 501 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 502 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 503 uint32_t LayerIdx); 504 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 505 uint32_t LayerIdx); 506 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 507 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 508 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 509 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 510 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 511 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 512 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 513 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 514 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 515 516 /** 517 * @} 518 */ 519 520 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 521 * @{ 522 */ 523 524 /* Peripheral Control functions *************************************************/ 525 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 526 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 527 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 528 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 529 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 530 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 531 532 /** 533 * @} 534 */ 535 536 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 537 * @{ 538 */ 539 540 /* Peripheral State functions ***************************************************/ 541 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 542 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 543 544 /** 545 * @} 546 */ 547 548 /** 549 * @} 550 */ 551 552 /* Private constants ---------------------------------------------------------*/ 553 554 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 555 * @{ 556 */ 557 558 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 559 * @{ 560 */ 561 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup DMA2D_Color_Value DMA2D Color Value 567 * @{ 568 */ 569 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 575 * @{ 576 */ 577 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 578 /** 579 * @} 580 */ 581 582 /** @defgroup DMA2D_Layers DMA2D Layers 583 * @{ 584 */ 585 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 586 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup DMA2D_Offset DMA2D Offset 592 * @{ 593 */ 594 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup DMA2D_Size DMA2D Size 600 * @{ 601 */ 602 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 603 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 609 * @{ 610 */ 611 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 612 /** 613 * @} 614 */ 615 616 /** 617 * @} 618 */ 619 620 621 /* Private macros ------------------------------------------------------------*/ 622 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 623 * @{ 624 */ 625 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 626 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 627 628 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 629 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 630 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 631 632 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 633 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 634 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 635 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 636 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 637 638 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 639 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 640 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 641 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 642 643 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 644 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 645 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 646 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 647 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 648 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 649 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 650 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 651 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 652 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 653 ((INPUT_CM) == DMA2D_INPUT_A4)) 654 655 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 656 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 657 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 658 659 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 660 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 661 662 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 663 ((RB_Swap) == DMA2D_RB_SWAP)) 664 665 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 666 ((LOM) == DMA2D_LOM_BYTES)) 667 668 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 669 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 670 671 672 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 673 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 674 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 675 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 676 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 677 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 678 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 679 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 680 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 681 /** 682 * @} 683 */ 684 685 /** 686 * @} 687 */ 688 689 #endif /* defined (DMA2D) */ 690 691 /** 692 * @} 693 */ 694 695 #ifdef __cplusplus 696 } 697 #endif 698 699 #endif /* STM32U5xx_HAL_DMA2D_H */ 700 701 702
