1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32MP1xx_HAL_RCC_EX_H 22 #define __STM32MP1xx_HAL_RCC_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 41 * @{ 42 */ 43 /** 44 * @brief RCC extended clocks structure definition 45 */ 46 typedef struct 47 { 48 uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. 49 This parameter can be a value of @ref 50 RCCEx_Periph_Clock_Selection */ 51 52 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters. 53 This parameter will be used only when 54 PLL2 is selected as Clock Source */ 55 56 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters. 57 This parameter will be used only when 58 PLL3 is selected as Clock Source */ 59 60 RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters. 61 This parameter will be used only when 62 PLL3 is selected as Clock Source */ 63 64 uint32_t I2c12ClockSelection; /*!< Specifies I2C12 clock source 65 This parameter can be a value of 66 @ref RCCEx_I2C12_Clock_Source */ 67 68 uint32_t I2c35ClockSelection; /*!< Specifies I2C35 clock source 69 This parameter can be a value of 70 @ref RCCEx_I2C35_Clock_Source */ 71 72 uint32_t I2c46ClockSelection; /*!< Specifies I2C46 clock source 73 This parameter can be a value of 74 @ref RCCEx_I2C46_Clock_Source */ 75 76 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source 77 This parameter can be a value of @ref 78 RCCEx_SAI1_Clock_Source */ 79 80 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source 81 This parameter can be a value of @ref 82 RCCEx_SAI2_Clock_Source */ 83 84 uint32_t Sai3ClockSelection; /*!< Specifies SAI3 clock source 85 This parameter can be a value of @ref 86 RCCEx_SAI3_Clock_Source */ 87 88 uint32_t Sai4ClockSelection; /*!< Specifies SAI4 clock source 89 This parameter can be a value of @ref 90 RCCEx_SAI4_Clock_Source */ 91 92 uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source 93 This parameter can be a value of @ref 94 RCCEx_SPI1_Clock_Source */ 95 96 uint32_t Spi23ClockSelection; /*!< Specifies SPI23 clock source 97 This parameter can be a value of @ref 98 RCCEx_SPI23_Clock_Source */ 99 100 uint32_t Spi45ClockSelection; /*!< Specifies SPI45 clock source 101 This parameter can be a value of @ref 102 RCCEx_SPI45_Clock_Source */ 103 104 uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source 105 This parameter can be a value of @ref 106 RCCEx_SPI6_Clock_Source */ 107 108 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source 109 This parameter can be a value of @ref 110 RCCEx_USART1_Clock_Source */ 111 112 uint32_t Uart24ClockSelection; /*!< Specifies UART24 clock source 113 This parameter can be a value of @ref 114 RCCEx_UART24_Clock_Source */ 115 116 uint32_t Uart35ClockSelection; /*!< Specifies UART35 clock source 117 This parameter can be a value of @ref 118 RCCEx_UART35_Clock_Source */ 119 120 uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source 121 This parameter can be a value of @ref 122 RCCEx_USART6_Clock_Source */ 123 124 uint32_t Uart78ClockSelection; /*!< Specifies UART78 clock source 125 This parameter can be a value of @ref 126 RCCEx_UART78_Clock_Source */ 127 128 uint32_t Sdmmc12ClockSelection; /*!< Specifies SDMMC12 clock source 129 This parameter can be a value of @ref 130 RCCEx_SDMMC12_Clock_Source */ 131 132 uint32_t Sdmmc3ClockSelection; /*!< Specifies SDMMC3 clock source 133 This parameter can be a value of @ref 134 RCCEx_SDMMC3_Clock_Source */ 135 136 uint32_t EthClockSelection; /*!< Specifies ETH clock source 137 This parameter can be a value of @ref 138 RCCEx_ETH_Clock_Source */ 139 140 uint32_t FmcClockSelection; /*!< Specifies FMC clock source 141 This parameter can be a value of @ref 142 RCCEx_FMC_Clock_Source */ 143 144 uint32_t QspiClockSelection; /*!< Specifies QSPI clock source 145 This parameter can be a value of @ref 146 RCCEx_QSPI_Clock_Source */ 147 148 uint32_t DsiClockSelection; /*!< Specifies DSI clock source 149 This parameter can be a value of @ref 150 RCCEx_DSI_Clock_Source */ 151 152 uint32_t CkperClockSelection; /*!< Specifies CKPER clock source 153 This parameter can be a value of @ref 154 RCCEx_CKPER_Clock_Source */ 155 156 uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source 157 This parameter can be a value of @ref 158 RCCEx_SPDIFRX_Clock_Source */ 159 160 uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source 161 This parameter can be a value of @ref 162 RCCEx_FDCAN_Clock_Source */ 163 164 uint32_t Rng1ClockSelection; /*!< Specifies RNG1 clock source 165 This parameter can be a value of @ref 166 RCCEx_RNG1_Clock_Source */ 167 168 uint32_t Rng2ClockSelection; /*!< Specifies RNG2 clock source 169 This parameter can be a value of @ref 170 RCCEx_RNG2_Clock_Source */ 171 172 uint32_t StgenClockSelection; /*!< Specifies STGEN clock source 173 This parameter can be a value of @ref 174 RCCEx_STGEN_Clock_Source */ 175 176 uint32_t UsbphyClockSelection; /*!< Specifies USB PHY clock source 177 This parameter can be a value of @ref 178 RCCEx_USBPHY_Clock_Source */ 179 180 uint32_t UsboClockSelection; /*!< Specifies USB OTG clock source 181 This parameter can be a value of @ref 182 RCCEx_USBO_Clock_Source */ 183 184 uint32_t CecClockSelection; /*!< Specifies CEC clock source 185 This parameter can be a value of @ref 186 RCCEx_CEC_Clock_Source */ 187 188 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source 189 This parameter can be a value of @ref 190 RCCEx_LPTIM1_Clock_Source */ 191 192 uint32_t Lptim23ClockSelection; /*!< Specifies LPTIM23 clock source 193 This parameter can be a value of @ref 194 RCCEx_LPTIM23_Clock_Source */ 195 196 uint32_t Lptim45ClockSelection; /*!< Specifies LPTIM45 clock source 197 This parameter can be a value of @ref 198 RCCEx_LPTIM45_Clock_Source */ 199 200 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source 201 This parameter can be a value of @ref 202 RCCEx_ADC_Clock_Source */ 203 204 uint32_t RTCClockSelection; /*!< Specifies RTC clock source 205 This parameter can be a value of @ref 206 RCC_RTC_Clock_Source */ 207 208 uint32_t TIMG1PresSelection; /*!< Specifies TIM Group 1 Clock Prescalers 209 Selection. 210 This parameter can be a value of @ref 211 RCCEx_TIMG1_Prescaler_Selection */ 212 213 uint32_t TIMG2PresSelection; /*!< Specifies TIM Group 2 Clock Prescalers 214 Selection. 215 This parameter can be a value of @ref 216 RCCEx_TIMG2_Prescaler_Selection */ 217 } RCC_PeriphCLKInitTypeDef; 218 /** 219 * @} 220 */ 221 222 /* Exported constants --------------------------------------------------------*/ 223 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 224 * @{ 225 */ 226 227 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx_Periph_Clock_Selection 228 * @{ 229 */ 230 #define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001) 231 #define RCC_PERIPHCLK_UART24 ((uint64_t)0x00000002) 232 #define RCC_PERIPHCLK_UART35 ((uint64_t)0x00000004) 233 #define RCC_PERIPHCLK_ADC ((uint64_t)0x00000008) 234 #define RCC_PERIPHCLK_I2C12 ((uint64_t)0x00000010) 235 #define RCC_PERIPHCLK_I2C35 ((uint64_t)0x00000020) 236 #define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000040) 237 #define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00000080) 238 #define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00000100) 239 #define RCC_PERIPHCLK_USBPHY ((uint64_t)0x00000200) 240 #define RCC_PERIPHCLK_TIMG1 ((uint64_t)0x00000400) 241 #define RCC_PERIPHCLK_TIMG2 ((uint64_t)0x00000800) 242 #define RCC_PERIPHCLK_RTC ((uint64_t)0x00001000) 243 #define RCC_PERIPHCLK_CEC ((uint64_t)0x00002000) 244 #define RCC_PERIPHCLK_USART6 ((uint64_t)0x00004000) 245 #define RCC_PERIPHCLK_UART78 ((uint64_t)0x00008000) 246 #define RCC_PERIPHCLK_LPTIM23 ((uint64_t)0x00010000) 247 #define RCC_PERIPHCLK_LPTIM45 ((uint64_t)0x00020000) 248 #define RCC_PERIPHCLK_SAI3 ((uint64_t)0x00040000) 249 #define RCC_PERIPHCLK_USBO ((uint64_t)0x00080000) 250 #define RCC_PERIPHCLK_FMC ((uint64_t)0x00100000) 251 #define RCC_PERIPHCLK_QSPI ((uint64_t)0x00200000) 252 #define RCC_PERIPHCLK_DSI ((uint64_t)0x00400000) 253 #define RCC_PERIPHCLK_CKPER ((uint64_t)0x00800000) 254 #define RCC_PERIPHCLK_SPDIFRX ((uint64_t)0x01000000) 255 #define RCC_PERIPHCLK_FDCAN ((uint64_t)0x02000000) 256 #define RCC_PERIPHCLK_SPI1 ((uint64_t)0x04000000) 257 #define RCC_PERIPHCLK_SPI23 ((uint64_t)0x08000000) 258 #define RCC_PERIPHCLK_SPI45 ((uint64_t)0x10000000) 259 #define RCC_PERIPHCLK_SPI6 ((uint64_t)0x20000000) 260 #define RCC_PERIPHCLK_SAI4 ((uint64_t)0x40000000) 261 #define RCC_PERIPHCLK_SDMMC12 ((uint64_t)0x80000000) 262 #define RCC_PERIPHCLK_SDMMC3 ((uint64_t)0x100000000) 263 #define RCC_PERIPHCLK_ETH ((uint64_t)0x200000000) 264 #define RCC_PERIPHCLK_RNG1 ((uint64_t)0x400000000) 265 #define RCC_PERIPHCLK_RNG2 ((uint64_t)0x800000000) 266 #define RCC_PERIPHCLK_STGEN ((uint64_t)0x1000000000) 267 #define RCC_PERIPHCLK_I2C46 ((uint64_t)0x2000000000) 268 269 #define IS_RCC_PERIPHCLOCK(SELECTION) \ 270 ((((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 271 (((SELECTION) & RCC_PERIPHCLK_UART24) == RCC_PERIPHCLK_UART24) || \ 272 (((SELECTION) & RCC_PERIPHCLK_UART35) == RCC_PERIPHCLK_UART35) || \ 273 (((SELECTION) & RCC_PERIPHCLK_I2C12) == RCC_PERIPHCLK_I2C12) || \ 274 (((SELECTION) & RCC_PERIPHCLK_I2C35) == RCC_PERIPHCLK_I2C35) || \ 275 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 276 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 277 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ 278 (((SELECTION) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) || \ 279 (((SELECTION) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 280 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 281 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ 282 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ 283 (((SELECTION) & RCC_PERIPHCLK_UART78) == RCC_PERIPHCLK_UART78) || \ 284 (((SELECTION) & RCC_PERIPHCLK_I2C46) == RCC_PERIPHCLK_I2C46) || \ 285 (((SELECTION) & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) || \ 286 (((SELECTION) & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) || \ 287 (((SELECTION) & RCC_PERIPHCLK_SAI3) == RCC_PERIPHCLK_SAI3) || \ 288 (((SELECTION) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \ 289 (((SELECTION) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 290 (((SELECTION) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) || \ 291 (((SELECTION) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \ 292 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ 293 (((SELECTION) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 294 (((SELECTION) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \ 295 (((SELECTION) & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) || \ 296 (((SELECTION) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) || \ 297 (((SELECTION) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \ 298 (((SELECTION) & RCC_PERIPHCLK_SAI4) == RCC_PERIPHCLK_SAI4) || \ 299 (((SELECTION) & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) || \ 300 (((SELECTION) & RCC_PERIPHCLK_SDMMC3) == RCC_PERIPHCLK_SDMMC3) || \ 301 (((SELECTION) & RCC_PERIPHCLK_ETH) == RCC_PERIPHCLK_ETH) || \ 302 (((SELECTION) & RCC_PERIPHCLK_RNG1) == RCC_PERIPHCLK_RNG1) || \ 303 (((SELECTION) & RCC_PERIPHCLK_RNG2) == RCC_PERIPHCLK_RNG2) || \ 304 (((SELECTION) & RCC_PERIPHCLK_USBO) == RCC_PERIPHCLK_USBO) || \ 305 (((SELECTION) & RCC_PERIPHCLK_STGEN) == RCC_PERIPHCLK_STGEN) || \ 306 (((SELECTION) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ 307 (((SELECTION) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2)) 308 /** 309 * @} 310 */ 311 312 /** @defgroup RCCEx_Periph_One_Clock RCCEx_Periph_One_Clock 313 * @{ 314 */ 315 #define RCC_PERIPHCLK_DAC ((uint64_t)0x4000000000) 316 #define RCC_PERIPHCLK_LTDC ((uint64_t)0x8000000000) 317 #define RCC_PERIPHCLK_DFSDM1 ((uint64_t)0x10000000000) 318 #define RCC_PERIPHCLK_TEMP ((uint64_t)0x20000000000) 319 #define RCC_PERIPHCLK_IWDG1 ((uint64_t)0x40000000000) 320 #define RCC_PERIPHCLK_DDRPHYC ((uint64_t)0x80000000000) 321 #define RCC_PERIPHCLK_IWDG2 ((uint64_t)0x100000000000) 322 #define RCC_PERIPHCLK_GPU ((uint64_t)0x200000000000) 323 #define RCC_PERIPHCLK_WWDG ((uint64_t)0x400000000000) 324 #define RCC_PERIPHCLK_TIM2 RCC_PERIPHCLK_TIMG1 325 #define RCC_PERIPHCLK_TIM3 RCC_PERIPHCLK_TIMG1 326 #define RCC_PERIPHCLK_TIM4 RCC_PERIPHCLK_TIMG1 327 #define RCC_PERIPHCLK_TIM5 RCC_PERIPHCLK_TIMG1 328 #define RCC_PERIPHCLK_TIM6 RCC_PERIPHCLK_TIMG1 329 #define RCC_PERIPHCLK_TIM7 RCC_PERIPHCLK_TIMG1 330 #define RCC_PERIPHCLK_TIM12 RCC_PERIPHCLK_TIMG1 331 #define RCC_PERIPHCLK_TIM13 RCC_PERIPHCLK_TIMG1 332 #define RCC_PERIPHCLK_TIM14 RCC_PERIPHCLK_TIMG1 333 #define RCC_PERIPHCLK_TIM1 RCC_PERIPHCLK_TIMG2 334 #define RCC_PERIPHCLK_TIM8 RCC_PERIPHCLK_TIMG2 335 #define RCC_PERIPHCLK_TIM15 RCC_PERIPHCLK_TIMG2 336 #define RCC_PERIPHCLK_TIM16 RCC_PERIPHCLK_TIMG2 337 #define RCC_PERIPHCLK_TIM17 RCC_PERIPHCLK_TIMG2 338 339 #define IS_RCC_PERIPHONECLOCK(PERIPH) \ 340 ((((PERIPH) & RCC_PERIPHCLK_DAC) == RCC_PERIPHCLK_DAC) || \ 341 (((PERIPH) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ 342 (((PERIPH) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ 343 (((PERIPH) & RCC_PERIPHCLK_TEMP) == RCC_PERIPHCLK_TEMP) || \ 344 (((PERIPH) & RCC_PERIPHCLK_IWDG1) == RCC_PERIPHCLK_IWDG1) || \ 345 (((PERIPH) & RCC_PERIPHCLK_IWDG2) == RCC_PERIPHCLK_IWDG2) || \ 346 (((PERIPH) & RCC_PERIPHCLK_WWDG) == RCC_PERIPHCLK_WWDG) || \ 347 (((PERIPH) & RCC_PERIPHCLK_DDRPHYC) == RCC_PERIPHCLK_DDRPHYC) || \ 348 (((PERIPH) & RCC_PERIPHCLK_GPU) == RCC_PERIPHCLK_GPU) || \ 349 (((PERIPH) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \ 350 (((PERIPH) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2)) 351 /** 352 * @} 353 */ 354 355 /** @defgroup RCCEx_I2C12_Clock_Source I2C12 Clock Source 356 * @{ 357 */ 358 #define RCC_I2C12CLKSOURCE_PCLK1 0U 359 #define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_0 360 #define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_1 361 #define RCC_I2C12CLKSOURCE_CSI (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0) 362 363 #define IS_RCC_I2C12CLKSOURCE(SOURCE) \ 364 (((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1) || \ 365 ((SOURCE) == RCC_I2C12CLKSOURCE_PLL4) || \ 366 ((SOURCE) == RCC_I2C12CLKSOURCE_HSI) || \ 367 ((SOURCE) == RCC_I2C12CLKSOURCE_CSI)) 368 /** 369 * @} 370 */ 371 372 /** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source 373 * @{ 374 */ 375 #define RCC_I2C35CLKSOURCE_PCLK1 0U 376 #define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_0 377 #define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_1 378 #define RCC_I2C35CLKSOURCE_CSI (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0) 379 380 #define IS_RCC_I2C35CLKSOURCE(SOURCE) \ 381 (((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \ 382 ((SOURCE) == RCC_I2C35CLKSOURCE_PLL4) || \ 383 ((SOURCE) == RCC_I2C35CLKSOURCE_HSI) || \ 384 ((SOURCE) == RCC_I2C35CLKSOURCE_CSI)) 385 /** 386 * @} 387 */ 388 389 390 /** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source 391 * @{ 392 */ 393 #define RCC_I2C46CLKSOURCE_PCLK5 0U 394 #define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_0 395 #define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_1 396 #define RCC_I2C46CLKSOURCE_CSI (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0) 397 398 #define IS_RCC_I2C46CLKSOURCE(SOURCE) \ 399 (((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5) || \ 400 ((SOURCE) == RCC_I2C46CLKSOURCE_PLL3) || \ 401 ((SOURCE) == RCC_I2C46CLKSOURCE_HSI) || \ 402 ((SOURCE) == RCC_I2C46CLKSOURCE_CSI)) 403 /** 404 * @} 405 */ 406 407 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 408 * @{ 409 */ 410 #define RCC_SAI1CLKSOURCE_PLL4 0U 411 #define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_0 412 #define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_1 413 #define RCC_SAI1CLKSOURCE_PER (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0) 414 #define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_2 415 416 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 417 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4) || \ 418 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_Q) || \ 419 ((__SOURCE__) == RCC_SAI1CLKSOURCE_I2SCKIN) || \ 420 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PER) || \ 421 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_R)) 422 /** 423 * @} 424 */ 425 426 427 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source 428 * @{ 429 */ 430 #define RCC_SAI2CLKSOURCE_PLL4 0U 431 #define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_0 432 #define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_1 433 #define RCC_SAI2CLKSOURCE_PER (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0) 434 #define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_2 435 #define RCC_SAI2CLKSOURCE_PLL3_R (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0) 436 437 438 #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \ 439 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL4) || \ 440 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_Q) || \ 441 ((__SOURCE__) == RCC_SAI2CLKSOURCE_I2SCKIN) || \ 442 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PER) || \ 443 ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIF) || \ 444 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_R)) 445 /** 446 * @} 447 */ 448 449 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source 450 * @{ 451 */ 452 #define RCC_SAI3CLKSOURCE_PLL4 0U 453 #define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_0 454 #define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_1 455 #define RCC_SAI3CLKSOURCE_PER (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0) 456 #define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_2 457 458 #define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \ 459 (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4) || \ 460 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_Q) || \ 461 ((__SOURCE__) == RCC_SAI3CLKSOURCE_I2SCKIN) || \ 462 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PER) || \ 463 ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_R)) 464 /** 465 * @} 466 */ 467 468 469 /** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source 470 * @{ 471 */ 472 #define RCC_SAI4CLKSOURCE_PLL4 0U 473 #define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_0 474 #define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_1 475 #define RCC_SAI4CLKSOURCE_PER (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0) 476 #define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_2 477 478 #define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \ 479 (((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4) || \ 480 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_Q) || \ 481 ((__SOURCE__) == RCC_SAI4CLKSOURCE_I2SCKIN) || \ 482 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PER) || \ 483 ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_R)) 484 /** 485 * @} 486 */ 487 488 489 /** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source 490 * @{ 491 */ 492 #define RCC_SPI1CLKSOURCE_PLL4 0U 493 #define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_0 494 #define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_1 495 #define RCC_SPI1CLKSOURCE_PER (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0) 496 #define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_2 497 498 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ 499 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4) || \ 500 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_Q) || \ 501 ((__SOURCE__) == RCC_SPI1CLKSOURCE_I2SCKIN) || \ 502 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PER) || \ 503 ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_R)) 504 /** 505 * @} 506 */ 507 508 /** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source 509 * @{ 510 */ 511 #define RCC_SPI23CLKSOURCE_PLL4 0U 512 #define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_0 513 #define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_1 514 #define RCC_SPI23CLKSOURCE_PER (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0) 515 #define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_2 516 517 #define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \ 518 (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4) || \ 519 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_Q) || \ 520 ((__SOURCE__) == RCC_SPI23CLKSOURCE_I2SCKIN) || \ 521 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PER) || \ 522 ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_R)) 523 /** 524 * @} 525 */ 526 527 /** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source 528 * @{ 529 */ 530 #define RCC_SPI45CLKSOURCE_PCLK2 0U 531 #define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_0 532 #define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_1 533 #define RCC_SPI45CLKSOURCE_CSI (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0) 534 #define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_2 535 536 #define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \ 537 (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \ 538 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL4) || \ 539 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ 540 ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ 541 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) 542 /** 543 * @} 544 */ 545 546 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source 547 * @{ 548 */ 549 #define RCC_SPI6CLKSOURCE_PCLK5 0U 550 #define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_0 551 #define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_1 552 #define RCC_SPI6CLKSOURCE_CSI (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0) 553 #define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_2 554 #define RCC_SPI6CLKSOURCE_PLL3 (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0) 555 556 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \ 557 (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \ 558 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL4) || \ 559 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ 560 ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ 561 ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ 562 ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)) 563 /** 564 * @} 565 */ 566 567 568 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 569 * @{ 570 */ 571 #define RCC_USART1CLKSOURCE_PCLK5 0U 572 #define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_0 573 #define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_1 574 #define RCC_USART1CLKSOURCE_CSI (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0) 575 #define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_2 576 #define RCC_USART1CLKSOURCE_HSE (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0) 577 578 #define IS_RCC_USART1CLKSOURCE(SOURCE) \ 579 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \ 580 ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ 581 ((SOURCE) == RCC_USART1CLKSOURCE_HSI) || \ 582 ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ 583 ((SOURCE) == RCC_USART1CLKSOURCE_PLL4) || \ 584 ((SOURCE) == RCC_USART1CLKSOURCE_HSE)) 585 /** 586 * @} 587 */ 588 589 /** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source 590 * @{ 591 */ 592 #define RCC_UART24CLKSOURCE_PCLK1 0U 593 #define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_0 594 #define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_1 595 #define RCC_UART24CLKSOURCE_CSI (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0) 596 #define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_2 597 598 #define IS_RCC_UART24CLKSOURCE(SOURCE) \ 599 (((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \ 600 ((SOURCE) == RCC_UART24CLKSOURCE_PLL4) || \ 601 ((SOURCE) == RCC_UART24CLKSOURCE_HSI) || \ 602 ((SOURCE) == RCC_UART24CLKSOURCE_CSI) || \ 603 ((SOURCE) == RCC_UART24CLKSOURCE_HSE)) 604 /** 605 * @} 606 */ 607 608 /** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source 609 * @{ 610 */ 611 #define RCC_UART35CLKSOURCE_PCLK1 0U 612 #define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_0 613 #define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_1 614 #define RCC_UART35CLKSOURCE_CSI (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0) 615 #define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_2 616 617 #define IS_RCC_UART35CLKSOURCE(SOURCE) \ 618 (((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \ 619 ((SOURCE) == RCC_UART35CLKSOURCE_PLL4) || \ 620 ((SOURCE) == RCC_UART35CLKSOURCE_HSI) || \ 621 ((SOURCE) == RCC_UART35CLKSOURCE_CSI) || \ 622 ((SOURCE) == RCC_UART35CLKSOURCE_HSE)) 623 /** 624 * @} 625 */ 626 627 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source 628 * @{ 629 */ 630 #define RCC_USART6CLKSOURCE_PCLK2 0U 631 #define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_0 632 #define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_1 633 #define RCC_USART6CLKSOURCE_CSI (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0) 634 #define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_2 635 636 #define IS_RCC_USART6CLKSOURCE(SOURCE) \ 637 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ 638 ((SOURCE) == RCC_USART6CLKSOURCE_PLL4) || \ 639 ((SOURCE) == RCC_USART6CLKSOURCE_HSI) || \ 640 ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ 641 ((SOURCE) == RCC_USART6CLKSOURCE_HSE)) 642 /** 643 * @} 644 */ 645 646 /** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source 647 * @{ 648 */ 649 #define RCC_UART78CLKSOURCE_PCLK1 0U 650 #define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_0 651 #define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_1 652 #define RCC_UART78CLKSOURCE_CSI (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0) 653 #define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_2 654 655 #define IS_RCC_UART78CLKSOURCE(SOURCE) \ 656 (((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \ 657 ((SOURCE) == RCC_UART78CLKSOURCE_PLL4) || \ 658 ((SOURCE) == RCC_UART78CLKSOURCE_HSI) || \ 659 ((SOURCE) == RCC_UART78CLKSOURCE_CSI) || \ 660 ((SOURCE) == RCC_UART78CLKSOURCE_HSE)) 661 /** 662 * @} 663 */ 664 665 /** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source 666 * @{ 667 */ 668 #define RCC_SDMMC12CLKSOURCE_HCLK6 0U 669 #define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_0 670 #define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_1 671 #define RCC_SDMMC12CLKSOURCE_HSI (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0) 672 673 #define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \ 674 (((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \ 675 ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL3) || \ 676 ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL4) || \ 677 ((SOURCE) == RCC_SDMMC12CLKSOURCE_HSI)) 678 /** 679 * @} 680 */ 681 682 /** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source 683 * @{ 684 */ 685 #define RCC_SDMMC3CLKSOURCE_HCLK2 0U 686 #define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_0 687 #define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_1 688 #define RCC_SDMMC3CLKSOURCE_HSI (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0) 689 690 #define IS_RCC_SDMMC3CLKSOURCE(SOURCE) \ 691 (((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \ 692 ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL3) || \ 693 ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL4) || \ 694 ((SOURCE) == RCC_SDMMC3CLKSOURCE_HSI)) 695 /** 696 * @} 697 */ 698 699 /** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source 700 * @{ 701 */ 702 #define RCC_ETHCLKSOURCE_PLL4 0U 703 #define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_0 704 #define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_1 705 706 707 #define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4) || \ 708 ((SOURCE) == RCC_ETHCLKSOURCE_PLL3) || \ 709 ((SOURCE) == RCC_ETHCLKSOURCE_OFF)) 710 /** 711 * @} 712 */ 713 714 715 /** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider 716 * @{ 717 */ 718 #define RCC_ETHPTPDIV_1 0U /*Bypass (default after reset*/ 719 #define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_0 /*Division by 2*/ 720 #define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 3*/ 721 #define RCC_ETHPTPDIV_4 (RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 4*/ 722 #define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 5*/ 723 #define RCC_ETHPTPDIV_6 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 6*/ 724 #define RCC_ETHPTPDIV_7 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 7*/ 725 #define RCC_ETHPTPDIV_8 (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 8*/ 726 #define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 9*/ 727 #define RCC_ETHPTPDIV_10 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 10*/ 728 #define RCC_ETHPTPDIV_11 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 11*/ 729 #define RCC_ETHPTPDIV_12 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 12*/ 730 #define RCC_ETHPTPDIV_13 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2) /*Division by 13*/ 731 #define RCC_ETHPTPDIV_14 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 14*/ 732 #define RCC_ETHPTPDIV_15 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1) /*Division by 15*/ 733 #define RCC_ETHPTPDIV_16 (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0) /*Division by 16*/ 734 735 736 #define IS_RCC_ETHPTPDIV(SOURCE) (((SOURCE) == RCC_ETHPTPDIV_1) || \ 737 ((SOURCE) == RCC_ETHPTPDIV_2) || \ 738 ((SOURCE) == RCC_ETHPTPDIV_3) || \ 739 ((SOURCE) == RCC_ETHPTPDIV_4) || \ 740 ((SOURCE) == RCC_ETHPTPDIV_5) || \ 741 ((SOURCE) == RCC_ETHPTPDIV_6) || \ 742 ((SOURCE) == RCC_ETHPTPDIV_7) || \ 743 ((SOURCE) == RCC_ETHPTPDIV_8) || \ 744 ((SOURCE) == RCC_ETHPTPDIV_9) || \ 745 ((SOURCE) == RCC_ETHPTPDIV_10) || \ 746 ((SOURCE) == RCC_ETHPTPDIV_11) || \ 747 ((SOURCE) == RCC_ETHPTPDIV_12) || \ 748 ((SOURCE) == RCC_ETHPTPDIV_13) || \ 749 ((SOURCE) == RCC_ETHPTPDIV_14) || \ 750 ((SOURCE) == RCC_ETHPTPDIV_15) || \ 751 ((SOURCE) == RCC_ETHPTPDIV_16)) 752 /** 753 * @} 754 */ 755 756 757 /** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source 758 * @{ 759 */ 760 #define RCC_QSPICLKSOURCE_ACLK 0U 761 #define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_0 762 #define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_1 763 #define RCC_QSPICLKSOURCE_PER (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0) 764 765 #define IS_RCC_QSPICLKSOURCE(SOURCE) \ 766 (((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \ 767 ((SOURCE) == RCC_QSPICLKSOURCE_PLL3) || \ 768 ((SOURCE) == RCC_QSPICLKSOURCE_PLL4) || \ 769 ((SOURCE) == RCC_QSPICLKSOURCE_PER)) 770 /** 771 * @} 772 */ 773 774 /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source 775 * @{ 776 */ 777 #define RCC_FMCCLKSOURCE_ACLK 0U 778 #define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_0 779 #define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_1 780 #define RCC_FMCCLKSOURCE_PER (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0) 781 782 #define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK) || \ 783 ((SOURCE) == RCC_FMCCLKSOURCE_PLL3) || \ 784 ((SOURCE) == RCC_FMCCLKSOURCE_PLL4) || \ 785 ((SOURCE) == RCC_FMCCLKSOURCE_PER)) 786 /** 787 * @} 788 */ 789 790 #if defined(FDCAN1) 791 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source 792 * @{ 793 */ 794 #define RCC_FDCANCLKSOURCE_HSE 0U 795 #define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_0 796 #define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_1 797 #define RCC_FDCANCLKSOURCE_PLL4_R (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0) 798 799 800 801 #define IS_RCC_FDCANCLKSOURCE(SOURCE) \ 802 (((SOURCE) == RCC_FDCANCLKSOURCE_HSE) || \ 803 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL3) || \ 804 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_Q) || \ 805 ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_R)) 806 /** 807 * @} 808 */ 809 #endif /*FDCAN1*/ 810 811 /** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source 812 * @{ 813 */ 814 #define RCC_SPDIFRXCLKSOURCE_PLL4 0U 815 #define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_0 816 #define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_1 817 818 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \ 819 (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4) || \ 820 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ 821 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) 822 /** 823 * @} 824 */ 825 826 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source 827 * @{ 828 */ 829 #define RCC_CECCLKSOURCE_LSE 0U 830 #define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_0 831 #define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_1 832 833 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ 834 ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ 835 ((SOURCE) == RCC_CECCLKSOURCE_CSI122)) 836 /** 837 * @} 838 */ 839 840 /** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source 841 * @{ 842 */ 843 #define RCC_USBPHYCLKSOURCE_HSE 0U 844 #define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_0 845 #define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_1 846 847 #define IS_RCC_USBPHYCLKSOURCE(SOURCE) \ 848 (((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \ 849 ((SOURCE) ==RCC_USBPHYCLKSOURCE_PLL4) || \ 850 ((SOURCE) ==RCC_USBPHYCLKSOURCE_HSE2)) 851 /** 852 * @} 853 */ 854 855 /** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source 856 * @{ 857 */ 858 #define RCC_USBOCLKSOURCE_PLL4 0U 859 #define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC 860 861 #define IS_RCC_USBOCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \ 862 ((SOURCE) == RCC_USBOCLKSOURCE_PHY)) 863 /** 864 * @} 865 */ 866 867 868 /** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source 869 * @{ 870 */ 871 #define RCC_RNG1CLKSOURCE_CSI 0U 872 #define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_0 873 #define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_1 874 #define RCC_RNG1CLKSOURCE_LSI (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0) 875 876 #define IS_RCC_RNG1CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG1CLKSOURCE_CSI) || \ 877 ((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \ 878 ((SOURCE) == RCC_RNG1CLKSOURCE_LSE) || \ 879 ((SOURCE) == RCC_RNG1CLKSOURCE_LSI)) 880 881 /** 882 * @} 883 */ 884 885 886 /** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source 887 * @{ 888 */ 889 #define RCC_RNG2CLKSOURCE_CSI 0U 890 #define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_0 891 #define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_1 892 #define RCC_RNG2CLKSOURCE_LSI (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0) 893 894 #define IS_RCC_RNG2CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG2CLKSOURCE_CSI) || \ 895 ((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \ 896 ((SOURCE) == RCC_RNG2CLKSOURCE_LSE) || \ 897 ((SOURCE) == RCC_RNG2CLKSOURCE_LSI)) 898 899 /** 900 * @} 901 */ 902 903 904 /** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source 905 * @{ 906 */ 907 #define RCC_CKPERCLKSOURCE_HSI 0U 908 #define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_0 909 #define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_1 910 #define RCC_CKPERCLKSOURCE_OFF (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/ 911 912 #define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \ 913 ((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \ 914 ((SOURCE) == RCC_CKPERCLKSOURCE_HSE) || \ 915 ((SOURCE) == RCC_CKPERCLKSOURCE_OFF)) 916 /** 917 * @} 918 */ 919 920 921 /** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source 922 * @{ 923 */ 924 #define RCC_STGENCLKSOURCE_HSI 0U 925 #define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_0 926 #define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_1 927 928 #define IS_RCC_STGENCLKSOURCE(SOURCE) \ 929 (((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \ 930 ((SOURCE) == RCC_STGENCLKSOURCE_HSE) || \ 931 ((SOURCE) == RCC_STGENCLKSOURCE_OFF)) 932 /** 933 * @} 934 */ 935 936 #if defined(DSI) 937 /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source 938 * @{ 939 */ 940 #define RCC_DSICLKSOURCE_PHY 0U 941 #define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC 942 943 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ 944 (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ 945 ((__SOURCE__) == RCC_DSICLKSOURCE_PLL4)) 946 /** 947 * @} 948 */ 949 #endif /*DSI*/ 950 951 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source 952 * @{ 953 */ 954 #define RCC_ADCCLKSOURCE_PLL4 0U 955 #define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_0 956 #define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_1 957 958 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4) || \ 959 ((SOURCE) == RCC_ADCCLKSOURCE_PER) || \ 960 ((SOURCE) == RCC_ADCCLKSOURCE_PLL3)) 961 /** 962 * @} 963 */ 964 965 966 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 967 * @{ 968 */ 969 #define RCC_LPTIM1CLKSOURCE_PCLK1 0U 970 #define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_0 971 #define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_1 972 #define RCC_LPTIM1CLKSOURCE_LSE (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) 973 #define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_2 974 #define RCC_LPTIM1CLKSOURCE_PER (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0) 975 #define RCC_LPTIM1CLKSOURCE_OFF (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1) 976 977 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \ 978 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 979 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL4) || \ 980 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ 981 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ 982 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ 983 ((SOURCE) == RCC_LPTIM1CLKSOURCE_PER) || \ 984 ((SOURCE) == RCC_LPTIM1CLKSOURCE_OFF)) 985 /** 986 * @} 987 */ 988 989 /** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source 990 * @{ 991 */ 992 #define RCC_LPTIM23CLKSOURCE_PCLK3 0U 993 #define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_0 994 #define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_1 995 #define RCC_LPTIM23CLKSOURCE_LSE (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) 996 #define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_2 997 #define RCC_LPTIM23CLKSOURCE_OFF (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0) 998 999 1000 #define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \ 1001 (((SOURCE) == RCC_LPTIM23CLKSOURCE_PCLK3) || \ 1002 ((SOURCE) == RCC_LPTIM23CLKSOURCE_PLL4) || \ 1003 ((SOURCE) == RCC_LPTIM23CLKSOURCE_PER) || \ 1004 ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSE) || \ 1005 ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSI) || \ 1006 ((SOURCE) == RCC_LPTIM23CLKSOURCE_OFF)) 1007 /** 1008 * @} 1009 */ 1010 1011 /** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source 1012 * @{ 1013 */ 1014 #define RCC_LPTIM45CLKSOURCE_PCLK3 0U 1015 #define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_0 1016 #define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_1 1017 #define RCC_LPTIM45CLKSOURCE_LSE (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) 1018 #define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_2 1019 #define RCC_LPTIM45CLKSOURCE_PER (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0) 1020 #define RCC_LPTIM45CLKSOURCE_OFF (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1) 1021 1022 1023 1024 #define IS_RCC_LPTIM45CLKSOURCE(SOURCE) \ 1025 (((SOURCE) == RCC_LPTIM45CLKSOURCE_PCLK3) || \ 1026 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL4) || \ 1027 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL3) || \ 1028 ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSE) || \ 1029 ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSI) || \ 1030 ((SOURCE) == RCC_LPTIM45CLKSOURCE_PER) || \ 1031 ((SOURCE) == RCC_LPTIM45CLKSOURCE_OFF)) 1032 /** 1033 * @} 1034 */ 1035 1036 1037 /** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection 1038 * @{ 1039 */ 1040 #define RCC_TIMG1PRES_DEACTIVATED 0U 1041 #define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE 1042 1043 #define IS_RCC_TIMG1PRES(PRES) (((PRES) == RCC_TIMG1PRES_DEACTIVATED) || \ 1044 ((PRES) == RCC_TIMG1PRES_ACTIVATED)) 1045 /** 1046 * @} 1047 */ 1048 1049 1050 /** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection 1051 * @{ 1052 */ 1053 #define RCC_TIMG2PRES_DEACTIVATED 0U 1054 #define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE 1055 1056 #define IS_RCC_TIMG2PRES(PRES) (((PRES) == RCC_TIMG2PRES_DEACTIVATED) || \ 1057 ((PRES) == RCC_TIMG2PRES_ACTIVATED)) 1058 /** 1059 * @} 1060 */ 1061 1062 1063 /** @defgroup RCCEx_RCC_BootCx RCC BootCx 1064 * @{ 1065 */ 1066 #define RCC_BOOT_C1 RCC_MP_BOOTCR_MPU_BEN 1067 #define RCC_BOOT_C2 RCC_MP_BOOTCR_MCU_BEN 1068 1069 #define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ 1070 ((CORE) == RCC_BOOT_C2) || \ 1071 ((CORE) == (RCC_BOOT_C1 ||RCC_BOOT_C2) )) 1072 /** 1073 * @} 1074 */ 1075 /** 1076 * @} 1077 */ 1078 1079 /* Exported macros -----------------------------------------------------------*/ 1080 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 1081 * @{ 1082 */ 1083 /** @brief macro to configure the I2C12 clock (I2C12CLK). 1084 * 1085 * @param __I2C12CLKSource__: specifies the I2C12 clock source. 1086 * This parameter can be one of the following values: 1087 * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock (default after reset) 1088 * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock 1089 * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock 1090 * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock 1091 * @retval None 1092 */ 1093 #define __HAL_RCC_I2C12_CONFIG(__I2C12CLKSource__) \ 1094 MODIFY_REG(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (uint32_t)(__I2C12CLKSource__)) 1095 1096 /** @brief macro to get the I2C12 clock source. 1097 * @retval The clock source can be one of the following values: 1098 * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock 1099 * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock 1100 * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock 1101 * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock 1102 */ 1103 #define __HAL_RCC_GET_I2C12_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC))) 1104 1105 /** @brief macro to configure the I2C35 clock (I2C35CLK). 1106 * 1107 * @param __I2C35CLKSource__: specifies the I2C35 clock source. 1108 * This parameter can be one of the following values: 1109 * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock (default after reset) 1110 * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock 1111 * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock 1112 * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock 1113 * @retval None 1114 */ 1115 #define __HAL_RCC_I2C35_CONFIG(__I2C35CLKSource__) \ 1116 MODIFY_REG(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (uint32_t)(__I2C35CLKSource__)) 1117 1118 /** @brief macro to get the I2C35 clock source. 1119 * @retval The clock source can be one of the following values: 1120 * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock 1121 * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock 1122 * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock 1123 * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock 1124 */ 1125 #define __HAL_RCC_GET_I2C35_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC))) 1126 1127 /** @brief macro to configure the I2C46 clock (I2C46CLK). 1128 * 1129 * @param __I2C46CLKSource__: specifies the I2C46 clock source. 1130 * This parameter can be one of the following values: 1131 * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock (default after reset) 1132 * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock 1133 * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock 1134 * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock 1135 * @retval None 1136 */ 1137 #define __HAL_RCC_I2C46_CONFIG(__I2C46CLKSource__) \ 1138 MODIFY_REG(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (uint32_t)(__I2C46CLKSource__)) 1139 1140 /** @brief macro to get the I2C46 clock source. 1141 * @retval The clock source can be one of the following values: 1142 * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock 1143 * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock 1144 * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock 1145 * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock 1146 */ 1147 #define __HAL_RCC_GET_I2C46_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC))) 1148 1149 /** 1150 * @brief Macro to Configure the SAI1 clock source. 1151 * @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. 1152 * This parameter can be one of the following values: 1153 * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q 1154 * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q 1155 * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN 1156 * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER 1157 * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R 1158 * @retval None 1159 */ 1160 #define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ ) \ 1161 MODIFY_REG(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (uint32_t)(__RCC_SAI1CLKSource__)) 1162 1163 /** @brief Macro to get the SAI1 clock source. 1164 * @retval The clock source can be one of the following values: 1165 * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q 1166 * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q 1167 * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN 1168 * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER 1169 * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R 1170 */ 1171 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC))) 1172 1173 1174 /** 1175 * @brief Macro to Configure the SAI2 clock source. 1176 * @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. 1177 * This parameter can be one of the following values: 1178 * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q 1179 * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q 1180 * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN 1181 * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER 1182 * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB 1183 * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R 1184 * @retval None 1185 */ 1186 #define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ ) \ 1187 MODIFY_REG(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (uint32_t)(__RCC_SAI2CLKSource__)) 1188 1189 /** @brief Macro to get the SAI2 clock source. 1190 * @retval The clock source can be one of the following values: 1191 * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q 1192 * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q 1193 * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN 1194 * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER 1195 * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB 1196 * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R 1197 */ 1198 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC))) 1199 1200 1201 /** 1202 * @brief Macro to Configure the SAI3 clock source. 1203 * @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. 1204 * This parameter can be one of the following values: 1205 * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q 1206 * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q 1207 * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN 1208 * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER 1209 * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R 1210 * @retval None 1211 */ 1212 #define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ ) \ 1213 MODIFY_REG(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (uint32_t)(__RCC_SAI3CLKSource__)) 1214 1215 /** @brief Macro to get the SAI3 clock source. 1216 * @retval The clock source can be one of the following values: 1217 * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q 1218 * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q 1219 * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN 1220 * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER 1221 * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R 1222 */ 1223 #define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC))) 1224 1225 1226 /** 1227 * @brief Macro to Configure the SAI4 clock source. 1228 * @param __RCC_SAI4CLKSource__: defines the SAI4 clock source. 1229 * This parameter can be one of the following values: 1230 * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q 1231 * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q 1232 * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN 1233 * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER 1234 * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R 1235 * @retval None 1236 */ 1237 #define __HAL_RCC_SAI4_CONFIG(__RCC_SAI4CLKSource__ ) \ 1238 MODIFY_REG(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (uint32_t)(__RCC_SAI4CLKSource__)) 1239 1240 /** @brief Macro to get the SAI4 clock source. 1241 * @retval The clock source can be one of the following values: 1242 * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q 1243 * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q 1244 * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN 1245 * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER 1246 * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R 1247 */ 1248 #define __HAL_RCC_GET_SAI4_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC))) 1249 1250 1251 /** 1252 * @brief Macro to Configure the SPI/I2S1 clock source. 1253 * @param __RCC_SPI1CLKSource__: defines the SPI/I2S1 clock source. 1254 * This parameter can be one of the following values: 1255 * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P 1256 * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q 1257 * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN 1258 * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER 1259 * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R 1260 * @retval None 1261 */ 1262 #define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__) \ 1263 MODIFY_REG(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (uint32_t)(__RCC_SPI1CLKSource__)) 1264 1265 /** @brief Macro to get the SPI/I2S1 clock source. 1266 * @retval The clock source can be one of the following values: 1267 * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P 1268 * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q 1269 * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN 1270 * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER 1271 * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R 1272 */ 1273 #define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC))) 1274 1275 1276 /** 1277 * @brief Macro to Configure the SPI/I2S2,3 clock source. 1278 * @param __RCC_SPI23CLKSource__: defines the SPI/I2S2,3 clock source. 1279 * This parameter can be one of the following values: 1280 * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P 1281 * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q 1282 * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN 1283 * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER 1284 * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R 1285 * @retval None 1286 */ 1287 #define __HAL_RCC_SPI23_CONFIG(__RCC_SPI23CLKSource__ ) \ 1288 MODIFY_REG(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (uint32_t)(__RCC_SPI23CLKSource__)) 1289 1290 /** @brief Macro to get the SPI/I2S2,3 clock source. 1291 * @retval The clock source can be one of the following values: 1292 * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P 1293 * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q 1294 * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN 1295 * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER 1296 * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R 1297 */ 1298 #define __HAL_RCC_GET_SPI23_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC))) 1299 1300 /** 1301 * @brief Macro to Configure the SPI45 clock source. 1302 * @param __RCC_SPI45CLKSource__: defines the SPI45 clock source. 1303 * This parameter can be one of the following values: 1304 * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2 1305 * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q 1306 * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI 1307 * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI 1308 * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE 1309 * @retval None 1310 */ 1311 #define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ ) \ 1312 MODIFY_REG(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (uint32_t)(__RCC_SPI45CLKSource__)) 1313 1314 /** @brief Macro to get the SPI45 clock source. 1315 * @retval The clock source can be one of the following values: 1316 * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2 1317 * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q 1318 * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI 1319 * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI 1320 * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE 1321 */ 1322 #define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC))) 1323 1324 /** 1325 * @brief Macro to Configure the SPI6 clock source. 1326 * @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. 1327 * This parameter can be one of the following values: 1328 * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5 1329 * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q 1330 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 1331 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 1332 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 1333 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q 1334 * @retval None 1335 */ 1336 #define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ ) \ 1337 MODIFY_REG(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (uint32_t)(__RCC_SPI6CLKSource__)) 1338 1339 /** @brief Macro to get the SPI6 clock source. 1340 * @retval The clock source can be one of the following values: 1341 * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5 1342 * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q 1343 * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI 1344 * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI 1345 * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE 1346 * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q 1347 */ 1348 #define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC))) 1349 1350 1351 /** @brief macro to configure the USART1 clock (USART1CLK). 1352 * 1353 * @param __USART1CLKSource__: specifies the USART1 clock source. 1354 * This parameter can be one of the following values: 1355 * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset) 1356 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock USART1 1357 * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock USART1 1358 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock USART1 1359 * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock USART1 1360 * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock USART1 1361 * @retval None 1362 */ 1363 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \ 1364 MODIFY_REG(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (uint32_t)(__USART1CLKSource__)) 1365 1366 /** @brief macro to get the USART1 clock source. 1367 * @retval The clock source can be one of the following values: 1368 * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset) 1369 * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock 1370 * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock 1371 * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock 1372 * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock 1373 * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock 1374 */ 1375 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC))) 1376 1377 /** @brief macro to configure the UART24 clock (UART24CLK). 1378 * 1379 * @param __UART24CLKSource__: specifies the UART24 clock source. 1380 * This parameter can be one of the following values: 1381 * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24 1382 * clock (default after reset) 1383 * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock 1384 * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock 1385 * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock 1386 * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock 1387 * @retval None 1388 */ 1389 #define __HAL_RCC_UART24_CONFIG(__UART24CLKSource__) \ 1390 MODIFY_REG(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (uint32_t)(__UART24CLKSource__)) 1391 1392 /** @brief macro to get the UART24 clock source. 1393 * @retval The clock source can be one of the following values: 1394 * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24 clock 1395 * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock 1396 * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock 1397 * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock 1398 * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock 1399 */ 1400 #define __HAL_RCC_GET_UART24_SOURCE() ((uint32_t)(READ_BIT(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC))) 1401 1402 1403 /** @brief macro to configure the UART35 clock (UART35CLK). 1404 * 1405 * @param __UART35CLKSource__: specifies the UART35 clock source. 1406 * This parameter can be one of the following values: 1407 * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35 1408 * clock (default after reset) 1409 * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock 1410 * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock 1411 * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock 1412 * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock 1413 * @retval None 1414 */ 1415 #define __HAL_RCC_UART35_CONFIG(__UART35CLKSource__) \ 1416 MODIFY_REG(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (uint32_t)(__UART35CLKSource__)) 1417 1418 /** @brief macro to get the UART35 clock source. 1419 * @retval The clock source can be one of the following values: 1420 * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35 clock 1421 * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock 1422 * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock 1423 * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock 1424 * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock 1425 */ 1426 #define __HAL_RCC_GET_UART35_SOURCE() ((uint32_t)(READ_BIT(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC))) 1427 1428 1429 /** @brief macro to configure the USART6 clock (USART6CLK). 1430 * 1431 * @param __USART6CLKSource__: specifies the USART6 clock source. 1432 * This parameter can be one of the following values: 1433 * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock (default after reset) 1434 * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock 1435 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1436 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1437 * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock 1438 * @retval None 1439 */ 1440 #define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \ 1441 MODIFY_REG(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (uint32_t)(__USART6CLKSource__)) 1442 1443 /** @brief macro to get the USART6 clock source. 1444 * @retval The clock source can be one of the following values: 1445 * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock 1446 * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock 1447 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock 1448 * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock 1449 * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock 1450 */ 1451 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC))) 1452 1453 /** @brief macro to configure the UART78clock (UART78CLK). 1454 * 1455 * @param __UART78CLKSource__: specifies the UART78 clock source. 1456 * This parameter can be one of the following values: 1457 * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock (default after reset) 1458 * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock 1459 * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock 1460 * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock 1461 * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock 1462 * @retval None 1463 */ 1464 #define __HAL_RCC_UART78_CONFIG(__UART78CLKSource__) \ 1465 MODIFY_REG(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (uint32_t)(__UART78CLKSource__)) 1466 1467 /** @brief macro to get the UART78 clock source. 1468 * @retval The clock source can be one of the following values: 1469 * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock 1470 * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock 1471 * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock 1472 * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock 1473 * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock 1474 */ 1475 #define __HAL_RCC_GET_UART78_SOURCE() ((uint32_t)(READ_BIT(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC))) 1476 1477 /** @brief macro to configure the SDMMC12 clock (SDMMC12CLK). 1478 * 1479 * @param __SDMMC12CLKSource__: specifies the SDMMC12 clock source. 1480 * This parameter can be one of the following values: 1481 * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset) 1482 * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock 1483 * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock 1484 * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock 1485 * @retval None 1486 */ 1487 #define __HAL_RCC_SDMMC12_CONFIG(__SDMMC12CLKSource__) \ 1488 MODIFY_REG(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (uint32_t)(__SDMMC12CLKSource__)) 1489 1490 /** @brief macro to get the SDMMC12 clock source. 1491 * @retval The clock source can be one of the following values: 1492 * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset) 1493 * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock 1494 * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock 1495 * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock 1496 */ 1497 #define __HAL_RCC_GET_SDMMC12_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC))) 1498 1499 1500 /** @brief macro to configure the SDMMC3 clock (SDMMC3CLK). 1501 * 1502 * @param __SDMMC3CLKSource__: specifies the SDMMC3 clock source. 1503 * This parameter can be one of the following values: 1504 * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset) 1505 * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock 1506 * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock 1507 * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock 1508 * 1509 * @retval None 1510 */ 1511 #define __HAL_RCC_SDMMC3_CONFIG(__SDMMC3CLKSource__) \ 1512 MODIFY_REG(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (uint32_t)(__SDMMC3CLKSource__)) 1513 1514 /** @brief macro to get the SDMMC3 clock source. 1515 * @retval The clock source can be one of the following values: 1516 * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset) 1517 * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock 1518 * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock 1519 * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock 1520 */ 1521 #define __HAL_RCC_GET_SDMMC3_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC))) 1522 1523 1524 /** @brief macro to configure the ETH clock (ETHCLK). 1525 * 1526 * @param __ETHCLKSource__: specifies the ETH clock source. 1527 * This parameter can be one of the following values: 1528 * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset) 1529 * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock 1530 * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled 1531 * @retval None 1532 */ 1533 #define __HAL_RCC_ETH_CONFIG(__ETHCLKSource__) \ 1534 MODIFY_REG(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC, (uint32_t)(__ETHCLKSource__)) 1535 1536 /** @brief macro to get the ETH clock source. 1537 * @retval The clock source can be one of the following values: 1538 * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset) 1539 * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock 1540 * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled 1541 */ 1542 #define __HAL_RCC_GET_ETH_SOURCE() ((uint32_t)(READ_BIT(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC))) 1543 1544 1545 /** @brief macro to configure the QSPI clock (QSPICLK). 1546 * 1547 * @param __QSPICLKSource__: specifies the QSPI clock source. 1548 * This parameter can be one of the following values: 1549 * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset) 1550 * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock 1551 * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock 1552 * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock 1553 * @retval None 1554 */ 1555 #define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ 1556 MODIFY_REG(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC, (uint32_t)(__QSPICLKSource__)) 1557 1558 /** @brief macro to get the QSPI clock source. 1559 * @retval The clock source can be one of the following values: 1560 * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset) 1561 * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock 1562 * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock 1563 * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock 1564 */ 1565 #define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC))) 1566 1567 1568 /** @brief macro to configure the FMC clock (FMCCLK). 1569 * 1570 * @param __FMCCLKSource__: specifies the FMC clock source. 1571 * This parameter can be one of the following values: 1572 * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset) 1573 * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock 1574 * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock 1575 * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock 1576 * @retval None 1577 */ 1578 #define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ 1579 MODIFY_REG(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC, (uint32_t)(__FMCCLKSource__)) 1580 1581 /** @brief macro to get the FMC clock source. 1582 * @retval The clock source can be one of the following values: 1583 * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset) 1584 * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock 1585 * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock 1586 * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock 1587 */ 1588 #define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC))) 1589 1590 #if defined(FDCAN1) 1591 /** @brief macro to configure the FDCAN clock (FDCANCLK). 1592 * 1593 * @param __FDCANCLKSource__: specifies the FDCAN clock source. 1594 * This parameter can be one of the following values: 1595 * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset) 1596 * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock 1597 * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock 1598 * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock 1599 * @retval None 1600 */ 1601 #define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ 1602 MODIFY_REG(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC, (uint32_t)(__FDCANCLKSource__)) 1603 1604 /** @brief macro to get the FDCAN clock source. 1605 * @retval The clock source can be one of the following values: 1606 * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset) 1607 * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock 1608 * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock 1609 * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock 1610 */ 1611 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC))) 1612 #endif /*FDCAN1*/ 1613 1614 /** @brief macro to configure the SPDIFRX clock (SPDIFCLK). 1615 * 1616 * @param __SPDIFCLKSource__: specifies the SPDIF clock source. 1617 * This parameter can be one of the following values: 1618 * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset) 1619 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock 1620 * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock 1621 * @retval None 1622 */ 1623 #define __HAL_RCC_SPDIFRX_CONFIG(__SPDIFCLKSource__) \ 1624 MODIFY_REG(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC, (uint32_t)(__SPDIFCLKSource__)) 1625 1626 /** @brief macro to get the SPDIFRX clock source. 1627 * @retval The clock source can be one of the following values: 1628 * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset) 1629 * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock 1630 * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock 1631 */ 1632 #define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC))) 1633 1634 1635 /** @brief macro to configure the CEC clock (CECCLK). 1636 * 1637 * @param __CECCLKSource__: specifies the CEC clock source. 1638 * This parameter can be one of the following values: 1639 * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset) 1640 * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock 1641 * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock 1642 * @retval None 1643 */ 1644 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ 1645 MODIFY_REG(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC, (uint32_t)(__CECCLKSource__)) 1646 1647 /** @brief macro to get the CEC clock source. 1648 * @retval The clock source can be one of the following values: 1649 * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset) 1650 * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock 1651 * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock 1652 */ 1653 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC))) 1654 1655 1656 /** @brief macro to configure the USB PHY clock (USBPHYCLK). 1657 * 1658 * @param __USBPHYCLKSource__: specifies the USB PHY clock source. 1659 * This parameter can be one of the following values: 1660 * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset) 1661 * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock 1662 * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock 1663 * @retval None 1664 */ 1665 #define __HAL_RCC_USBPHY_CONFIG(__USBPHYCLKSource__) \ 1666 MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC, (uint32_t)(__USBPHYCLKSource__)) 1667 1668 /** @brief macro to get the USB PHY PLL clock source. 1669 * @retval The clock source can be one of the following values: 1670 * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset) 1671 * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock 1672 * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock 1673 */ 1674 #define __HAL_RCC_GET_USBPHY_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC))) 1675 1676 1677 /** @brief macro to configure the USB OTG clock (USBOCLK). 1678 * 1679 * @param __USBOCLKSource__: specifies the USB OTG clock source. 1680 * This parameter can be one of the following values: 1681 * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset) 1682 * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock 1683 * @retval None 1684 */ 1685 #define __HAL_RCC_USBO_CONFIG(__USBOCLKSource__) \ 1686 MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC, (uint32_t)(__USBOCLKSource__)) 1687 1688 /** @brief macro to get the USB OTG PLL clock source. 1689 * @retval The clock source can be one of the following values: 1690 * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset) 1691 * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock 1692 */ 1693 #define __HAL_RCC_GET_USBO_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC))) 1694 1695 1696 /** @brief macro to configure the RNG1 clock (RNG1CLK). 1697 * 1698 * @param __RNG1CLKSource__: specifies the RNG1 clock source. 1699 * This parameter can be one of the following values: 1700 * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset) 1701 * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock 1702 * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock 1703 * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock 1704 * @retval None 1705 */ 1706 #define __HAL_RCC_RNG1_CONFIG(__RNG1CLKSource__) \ 1707 MODIFY_REG(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (uint32_t)(__RNG1CLKSource__)) 1708 1709 /** @brief macro to get the RNG1 clock source. 1710 * @retval The clock source can be one of the following values: 1711 * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset) 1712 * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock 1713 * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock 1714 * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock 1715 */ 1716 #define __HAL_RCC_GET_RNG1_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC))) 1717 1718 1719 /** @brief macro to configure the RNG2 clock (RNG2CLK). 1720 * 1721 * @param __RNG2CLKSource__: specifies the RNG2 clock source. 1722 * This parameter can be one of the following values: 1723 * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset) 1724 * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock 1725 * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock 1726 * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock 1727 * @retval None 1728 */ 1729 #define __HAL_RCC_RNG2_CONFIG(__RNG2CLKSource__) \ 1730 MODIFY_REG(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (uint32_t)(__RNG2CLKSource__)) 1731 1732 /** @brief macro to get the RNG2 clock source. 1733 * @retval The clock source can be one of the following values: 1734 * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset) 1735 * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock 1736 * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock 1737 * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock 1738 */ 1739 #define __HAL_RCC_GET_RNG2_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC))) 1740 1741 1742 /** @brief macro to configure the CK_PER clock (CK_PERCLK). 1743 * 1744 * @param __CKPERCLKSource__: specifies the CPER clock source. 1745 * This parameter can be one of the following values: 1746 * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset) 1747 * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock 1748 * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock 1749 * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER 1750 * @retval None 1751 */ 1752 #define __HAL_RCC_CKPER_CONFIG(__CKPERCLKSource__) \ 1753 MODIFY_REG(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC, (uint32_t)(__CKPERCLKSource__)) 1754 1755 /** @brief macro to get the CPER clock source. 1756 * @retval The clock source can be one of the following values: 1757 * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset) 1758 * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock 1759 * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock 1760 * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER 1761 */ 1762 #define __HAL_RCC_GET_CKPER_SOURCE() ((uint32_t)(READ_BIT(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC))) 1763 1764 1765 /** @brief macro to configure the STGEN clock (STGENCLK). 1766 * 1767 * @param __STGENCLKSource__: specifies the STGEN clock source. 1768 * This parameter can be one of the following values: 1769 * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset) 1770 * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock 1771 * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled 1772 * 1773 * @retval None 1774 */ 1775 #define __HAL_RCC_STGEN_CONFIG(__STGENCLKSource__) \ 1776 MODIFY_REG(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC, (uint32_t)(__STGENCLKSource__)) 1777 1778 /** @brief macro to get the STGEN clock source. 1779 * @retval The clock source can be one of the following values: 1780 * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset) 1781 * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock 1782 * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled 1783 */ 1784 #define __HAL_RCC_GET_STGEN_SOURCE() ((uint32_t)(READ_BIT(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC))) 1785 1786 #if defined(DSI) 1787 /** @brief macro to configure the DSI clock (DSICLK). 1788 * 1789 * @param __DSICLKSource__: specifies the DSI clock source. 1790 * This parameter can be one of the following values: 1791 * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset) 1792 * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock 1793 * @retval None 1794 */ 1795 #define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ 1796 MODIFY_REG(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC, (uint32_t)(__DSICLKSource__)) 1797 1798 /** @brief macro to get the DSI clock source. 1799 * @retval The clock source can be one of the following values: 1800 * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset) 1801 * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock 1802 */ 1803 #define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC))) 1804 #endif /*DSI*/ 1805 1806 /** @brief macro to configure the ADC clock (ADCCLK). 1807 * 1808 * @param __ADCCLKSource__: specifies the ADC clock source. 1809 * This parameter can be one of the following values: 1810 * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset) 1811 * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock 1812 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock 1813 * @retval None 1814 */ 1815 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ 1816 MODIFY_REG(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC, (uint32_t)(__ADCCLKSource__)) 1817 1818 /** @brief macro to get the ADC clock source. 1819 * @retval The clock source can be one of the following values: 1820 * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset) 1821 * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock 1822 * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock 1823 */ 1824 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC))) 1825 1826 1827 /** @brief macro to configure the LPTIM1 clock (LPTIM1CLK). 1828 * 1829 * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source. 1830 * This parameter can be one of the following values: 1831 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset) 1832 * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock 1833 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock 1834 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock 1835 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 1836 * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock 1837 * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled 1838 * 1839 * @retval None 1840 */ 1841 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ 1842 MODIFY_REG(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (uint32_t)(__LPTIM1CLKSource__)) 1843 1844 /** @brief macro to get the LPTIM1 clock source. 1845 * @retval The clock source can be one of the following values: 1846 * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset) 1847 * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock 1848 * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock 1849 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock 1850 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock 1851 * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock 1852 * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled 1853 */ 1854 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC))) 1855 1856 /** @brief macro to configure the LPTIM23 clock (LPTIM23CLK). 1857 * 1858 * @param __LPTIM23CLKSource__: specifies the LPTIM23 clock source. 1859 * This parameter can be one of the following values: 1860 * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset) 1861 * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock 1862 * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock 1863 * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock 1864 * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock 1865 * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled 1866 * @retval None 1867 */ 1868 #define __HAL_RCC_LPTIM23_CONFIG(__LPTIM23CLKSource__) \ 1869 MODIFY_REG(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (uint32_t)(__LPTIM23CLKSource__)) 1870 1871 /** @brief macro to get the LPTIM23 clock source. 1872 * @retval The clock source can be one of the following values: 1873 * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset) 1874 * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock 1875 * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock 1876 * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock 1877 * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock 1878 * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled 1879 */ 1880 #define __HAL_RCC_GET_LPTIM23_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC))) 1881 1882 /** @brief macro to configure the LPTIM45 clock (LPTIM45CLK). 1883 * 1884 * @param __LPTIM45CLKSource__: specifies the LPTIM45 clock source. 1885 * This parameter can be one of the following values: 1886 * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset) 1887 * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock 1888 * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock 1889 * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock 1890 * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock 1891 * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock 1892 * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled 1893 * @retval None 1894 */ 1895 #define __HAL_RCC_LPTIM45_CONFIG(__LPTIM45CLKSource__) \ 1896 MODIFY_REG(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (uint32_t)(__LPTIM45CLKSource__)) 1897 1898 /** @brief macro to get the LPTIM45 clock source. 1899 * @retval The clock source can be one of the following values: 1900 * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset) 1901 * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock 1902 * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock 1903 * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock 1904 * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock 1905 * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock 1906 * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled 1907 */ 1908 #define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC))) 1909 1910 1911 1912 /** 1913 * @brief Macro to set the APB1 timer clock prescaler 1914 * @note Set and reset by software to control the clock frequency of all the timers connected to APB1 domain. 1915 * It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. 1916 * @param __RCC_TIMG1PRES__: specifies the Timers clocks prescaler selection 1917 * This parameter can be one of the following values: 1918 * @arg RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1919 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1920 * @arg RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1921 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1922 */ 1923 #define __HAL_RCC_TIMG1PRES(__RCC_TIMG1PRES__) \ 1924 do{ MODIFY_REG( RCC->TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE , __RCC_TIMG1PRES__ );\ 1925 } while(0) 1926 1927 /** @brief Macro to get the APB1 timer clock prescaler. 1928 * @retval The APB1 timer clock prescaler. The returned value can be one 1929 * of the following: 1930 * - RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1931 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1932 * - RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding 1933 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1934 */ 1935 #define __HAL_RCC_GET_TIMG1PRES() ((uint32_t)(RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRE)) 1936 1937 /** 1938 * @brief Macro to set the APB2 timers clocks prescaler 1939 * @note Set and reset by software to control the clock frequency of all the timers connected to APB2 domain. 1940 * It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. 1941 * @param __RCC_TIMG2PRES__: specifies the timers clocks prescaler selection 1942 * This parameter can be one of the following values: 1943 * @arg RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1944 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk2 (default after reset) 1945 * @arg RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1946 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1947 */ 1948 #define __HAL_RCC_TIMG2PRES(__RCC_TIMG2PRES__) \ 1949 do{ MODIFY_REG( RCC->TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE , __RCC_TIMG2PRES__ );\ 1950 } while(0) 1951 1952 /** @brief Macro to get the APB2 timer clock prescaler. 1953 * @retval The APB2 timer clock prescaler. The returned value can be one 1954 * of the following: 1955 * - RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1956 * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset) 1957 * - RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding 1958 * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1 1959 */ 1960 #define __HAL_RCC_GET_TIMG2PRES() ((uint32_t)(RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRE)) 1961 1962 1963 1964 #define USB_PHY_VALUE ((uint32_t)48000000) /*!< Value of the USB_PHY_VALUE signal in Hz 1965 It is equal to rcc_hsphy_CLK_48M which is 1966 a constant value */ 1967 /** 1968 * @} 1969 */ 1970 1971 1972 /* Exported functions --------------------------------------------------------*/ 1973 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions 1974 * @{ 1975 */ 1976 1977 /** @addtogroup RCCEx_Exported_Functions_Group1 1978 * @{ 1979 */ 1980 1981 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); 1982 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1983 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1984 HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2); 1985 HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3); 1986 HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4); 1987 1988 /** 1989 * @} 1990 */ 1991 1992 /** @addtogroup RCCEx_Exported_Functions_Group2 1993 * @{ 1994 */ 1995 1996 void HAL_RCCEx_EnableLSECSS(void); 1997 void HAL_RCCEx_DisableLSECSS(void); 1998 1999 #ifdef CORE_CA7 2000 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); 2001 void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx); 2002 void HAL_RCCEx_HoldBootMCU(void); 2003 void HAL_RCCEx_BootMCU(void); 2004 #endif /* CORE_CA7 */ 2005 2006 /** 2007 * @} 2008 */ 2009 2010 /** 2011 * @} 2012 */ 2013 2014 /** 2015 * @} 2016 */ 2017 2018 /** 2019 * @} 2020 */ 2021 2022 #ifdef __cplusplus 2023 } 2024 #endif 2025 2026 #endif /* __STM32MP1xx_HAL_RCC_EX_H */ 2027 2028 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2029
