1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_FDCAN_H 22 #define STM32MP1xx_HAL_FDCAN_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 #if defined(FDCAN1) 32 33 /** @addtogroup STM32MP1xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup FDCAN 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 52 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 53 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 54 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 55 } HAL_FDCAN_StateTypeDef; 56 57 /** 58 * @brief FDCAN Init structure definition 59 */ 60 typedef struct 61 { 62 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 63 This parameter can be a value of @ref FDCAN_frame_format */ 64 65 uint32_t Mode; /*!< Specifies the FDCAN mode. 66 This parameter can be a value of @ref FDCAN_operating_mode */ 67 68 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 69 This parameter can be set to ENABLE or DISABLE */ 70 71 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 72 This parameter can be set to ENABLE or DISABLE */ 73 74 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 75 This parameter can be set to ENABLE or DISABLE */ 76 77 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 78 divided for generating the nominal bit time quanta. 79 This parameter must be a number between 1 and 512 */ 80 81 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 82 hardware is allowed to lengthen or shorten a bit to perform 83 resynchronization. 84 This parameter must be a number between 1 and 128 */ 85 86 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 87 This parameter must be a number between 2 and 256 */ 88 89 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 90 This parameter must be a number between 2 and 128 */ 91 92 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 93 divided for generating the data bit time quanta. 94 This parameter must be a number between 1 and 32 */ 95 96 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 97 hardware is allowed to lengthen or shorten a data bit to 98 perform resynchronization. 99 This parameter must be a number between 1 and 16 */ 100 101 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 102 This parameter must be a number between 1 and 32 */ 103 104 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 105 This parameter must be a number between 1 and 16 */ 106 107 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. 108 This parameter must be a number between 0 and 2560 */ 109 110 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 111 This parameter must be a number between 0 and 128 */ 112 113 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 114 This parameter must be a number between 0 and 64 */ 115 116 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. 117 This parameter must be a number between 0 and 64 */ 118 119 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. 120 This parameter can be a value of @ref FDCAN_data_field_size */ 121 122 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. 123 This parameter must be a number between 0 and 64 */ 124 125 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. 126 This parameter can be a value of @ref FDCAN_data_field_size */ 127 128 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. 129 This parameter must be a number between 0 and 64 */ 130 131 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. 132 This parameter can be a value of @ref FDCAN_data_field_size */ 133 134 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. 135 This parameter must be a number between 0 and 32 */ 136 137 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. 138 This parameter must be a number between 0 and 32 */ 139 140 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. 141 This parameter must be a number between 0 and 32 */ 142 143 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 144 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 145 146 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. 147 This parameter can be a value of @ref FDCAN_data_field_size */ 148 149 } FDCAN_InitTypeDef; 150 151 /** 152 * @brief FDCAN clock calibration unit structure definition 153 */ 154 typedef struct 155 { 156 uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. 157 This parameter can be a value of @ref FDCAN_clock_calibration. */ 158 159 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration 160 is bypassed. 161 This parameter can be a value of @ref FDCAN_clock_divider */ 162 163 uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The 164 actual configured number of periods is MinOscClkPeriods x 32. 165 This parameter must be a number between 0x00 and 0xFF */ 166 167 uint32_t CalFieldLength; /*!< Specifies the calibration field length. 168 This parameter can be a value of @ref FDCAN_calibration_field_length */ 169 170 uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. 171 This parameter must be a number between 4 and 25 */ 172 173 uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. 174 If set to zero the counter is disabled. 175 This parameter must be a number between 0x0000 and 0xFFFF */ 176 177 } FDCAN_ClkCalUnitTypeDef; 178 179 /** 180 * @brief FDCAN filter structure definition 181 */ 182 typedef struct 183 { 184 uint32_t IdType; /*!< Specifies the identifier type. 185 This parameter can be a value of @ref FDCAN_id_type */ 186 187 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 188 This parameter must be a number between: 189 - 0 and 127, if IdType is FDCAN_STANDARD_ID 190 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 191 192 uint32_t FilterType; /*!< Specifies the filter type. 193 This parameter can be a value of @ref FDCAN_filter_type. 194 The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted 195 only when IdType is FDCAN_EXTENDED_ID. 196 This parameter is ignored if FilterConfig is set to 197 FDCAN_FILTER_TO_RXBUFFER */ 198 199 uint32_t FilterConfig; /*!< Specifies the filter configuration. 200 This parameter can be a value of @ref FDCAN_filter_config */ 201 202 uint32_t FilterID1; /*!< Specifies the filter identification 1. 203 This parameter must be a number between: 204 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 205 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 206 207 uint32_t FilterID2; /*!< Specifies the filter identification 2. 208 This parameter is ignored if FilterConfig is set to 209 FDCAN_FILTER_TO_RXBUFFER. 210 This parameter must be a number between: 211 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 212 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 213 214 uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the 215 matching message will be stored. 216 This parameter must be a number between 0 and 63. 217 This parameter is ignored if FilterConfig is different 218 from FDCAN_FILTER_TO_RXBUFFER */ 219 220 uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for 221 calibration messages. 222 This parameter is ignored if FilterConfig is different 223 from FDCAN_FILTER_TO_RXBUFFER. 224 This parameter can be: 225 - 0 : ordinary message 226 - 1 : calibration message */ 227 228 } FDCAN_FilterTypeDef; 229 230 /** 231 * @brief FDCAN Tx header structure definition 232 */ 233 typedef struct 234 { 235 uint32_t Identifier; /*!< Specifies the identifier. 236 This parameter must be a number between: 237 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 238 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 239 240 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 241 transmitted. 242 This parameter can be a value of @ref FDCAN_id_type */ 243 244 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 245 This parameter can be a value of @ref FDCAN_frame_type */ 246 247 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 248 This parameter can be a value of @ref FDCAN_data_length_code */ 249 250 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 251 This parameter can be a value of @ref FDCAN_error_state_indicator */ 252 253 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 254 bit rate switching. 255 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 256 257 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 258 FD format. 259 This parameter can be a value of @ref FDCAN_format */ 260 261 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 262 This parameter can be a value of @ref FDCAN_EFC */ 263 264 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 265 element for identification of Tx message status. 266 This parameter must be a number between 0 and 0xFF */ 267 268 } FDCAN_TxHeaderTypeDef; 269 270 /** 271 * @brief FDCAN Rx header structure definition 272 */ 273 typedef struct 274 { 275 uint32_t Identifier; /*!< Specifies the identifier. 276 This parameter must be a number between: 277 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 278 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 279 280 uint32_t IdType; /*!< Specifies the identifier type of the received message. 281 This parameter can be a value of @ref FDCAN_id_type */ 282 283 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 284 This parameter can be a value of @ref FDCAN_frame_type */ 285 286 uint32_t DataLength; /*!< Specifies the received frame length. 287 This parameter can be a value of @ref FDCAN_data_length_code */ 288 289 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 290 This parameter can be a value of @ref FDCAN_error_state_indicator */ 291 292 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 293 rate switching. 294 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 295 296 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 297 format. 298 This parameter can be a value of @ref FDCAN_format */ 299 300 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 301 reception. 302 This parameter must be a number between 0 and 0xFFFF */ 303 304 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 305 This parameter must be a number between: 306 - 0 and 127, if IdType is FDCAN_STANDARD_ID 307 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 308 309 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 310 Acceptance of non-matching frames may be enabled via 311 HAL_FDCAN_ConfigGlobalFilter(). 312 This parameter can be 0 or 1 */ 313 314 } FDCAN_RxHeaderTypeDef; 315 316 /** 317 * @brief FDCAN Tx event FIFO structure definition 318 */ 319 typedef struct 320 { 321 uint32_t Identifier; /*!< Specifies the identifier. 322 This parameter must be a number between: 323 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 324 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 325 326 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 327 This parameter can be a value of @ref FDCAN_id_type */ 328 329 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 330 This parameter can be a value of @ref FDCAN_frame_type */ 331 332 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 333 This parameter can be a value of @ref FDCAN_data_length_code */ 334 335 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 336 This parameter can be a value of @ref FDCAN_error_state_indicator */ 337 338 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 339 rate switching. 340 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 341 342 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 343 format. 344 This parameter can be a value of @ref FDCAN_format */ 345 346 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 347 transmission. 348 This parameter must be a number between 0 and 0xFFFF */ 349 350 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 351 for identification of Tx message status. 352 This parameter must be a number between 0 and 0xFF */ 353 354 uint32_t EventType; /*!< Specifies the event type. 355 This parameter can be a value of @ref FDCAN_event_type */ 356 357 } FDCAN_TxEventFifoTypeDef; 358 359 /** 360 * @brief FDCAN High Priority Message Status structure definition 361 */ 362 typedef struct 363 { 364 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 365 This parameter can be: 366 - 0 : Standard Filter List 367 - 1 : Extended Filter List */ 368 369 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 370 This parameter can be a number between: 371 - 0 and 127, if FilterList is 0 (Standard) 372 - 0 and 63, if FilterList is 1 (Extended) */ 373 374 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 375 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 376 377 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 378 message was stored. 379 This parameter is valid only when MessageStorage is: 380 FDCAN_HP_STORAGE_RXFIFO0 381 or 382 FDCAN_HP_STORAGE_RXFIFO1 */ 383 384 } FDCAN_HpMsgStatusTypeDef; 385 386 /** 387 * @brief FDCAN Protocol Status structure definition 388 */ 389 typedef struct 390 { 391 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 392 This parameter can be a value of @ref FDCAN_protocol_error_code */ 393 394 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format 395 frame with its BRS flag set. 396 This parameter can be a value of @ref FDCAN_protocol_error_code */ 397 398 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 399 This parameter can be a value of @ref FDCAN_communication_state */ 400 401 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 402 This parameter can be: 403 - 0 : The FDCAN is in Error_Active state 404 - 1 : The FDCAN is in Error_Passive state */ 405 406 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 407 This parameter can be: 408 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 409 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 410 411 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 412 This parameter can be: 413 - 0 : The FDCAN is not in Bus_Off state 414 - 1 : The FDCAN is in Bus_Off state */ 415 416 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 417 This parameter can be: 418 - 0 : Last received CAN FD message did not have its ESI flag set 419 - 1 : Last received CAN FD message had its ESI flag set */ 420 421 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 422 This parameter can be: 423 - 0 : Last received CAN FD message did not have its BRS flag set 424 - 1 : Last received CAN FD message had its BRS flag set */ 425 426 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. 427 This parameter can be: 428 - 0 : no CAN FD message received 429 - 1 : CAN FD message received */ 430 431 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 432 This parameter can be: 433 - 0 : No protocol exception event occurred since last read access 434 - 1 : Protocol exception event occurred */ 435 436 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 437 This parameter can be a number between 0 and 127 */ 438 439 } FDCAN_ProtocolStatusTypeDef; 440 441 /** 442 * @brief FDCAN Error Counters structure definition 443 */ 444 typedef struct 445 { 446 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 447 This parameter can be a number between 0 and 255 */ 448 449 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 450 This parameter can be a number between 0 and 127 */ 451 452 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 453 This parameter can be: 454 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 455 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ 456 457 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 458 This parameter can be a number between 0 and 255. 459 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 460 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 461 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 462 463 } FDCAN_ErrorCountersTypeDef; 464 465 /** 466 * @brief FDCAN TT Init structure definition 467 */ 468 typedef struct 469 { 470 uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. 471 This parameter can be a value of @ref FDCAN_operation_mode */ 472 473 uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. 474 This parameter can be a value of @ref FDCAN_TT_operation. 475 This parameter is ignored if OperationMode is set to 476 FDCAN_TT_COMMUNICATION_LEVEL0 */ 477 478 uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. 479 This parameter can be a value of @ref FDCAN_TT_time_master */ 480 481 uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR 482 numerator : TUR = (Numerator � SDL) / Denominator. 483 With : SDL = 2^(SyncDevLimit+5). 484 This parameter must be a number between 0 and 7 */ 485 486 uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. 487 This parameter must be a number between 0 and 127 */ 488 489 uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. 490 This parameter can be a value of @ref FDCAN_TT_external_clk_sync. 491 This parameter is ignored if OperationMode is set to 492 FDCAN_TT_COMMUNICATION_LEVEL1 */ 493 494 uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after 495 which the application has to serve the application watchdog. 496 The application watchdog is incremented once each 256 NTUs. 497 The application watchdog can be disabled by setting AppWdgLimit to 0. 498 This parameter must be a number between 0 and 255. 499 This parameter is ignored if OperationMode is set to 500 FDCAN_TT_COMMUNICATION_LEVEL0 */ 501 502 uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. 503 This parameter can be a value of @ref FDCAN_TT_global_time_filtering. 504 This parameter is ignored if OperationMode is set to 505 FDCAN_TT_COMMUNICATION_LEVEL1 */ 506 507 uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. 508 This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. 509 This parameter is ignored if OperationMode is set to 510 FDCAN_TT_COMMUNICATION_LEVEL1 */ 511 512 uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. 513 This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. 514 This parameter is ignored if OperationMode is set to 515 FDCAN_TT_COMMUNICATION_LEVEL0 */ 516 517 uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix. 518 This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ 519 520 uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. 521 This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ 522 523 uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. 524 This parameter must be a number between 1 and 16 */ 525 526 uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. 527 This is the sum of Tx_Triggers for exclusive, single arbitrating and 528 merged arbitrating windows. 529 This parameter must be a number between 0 and 4095 */ 530 531 uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. 532 It is adviced to set this parameter to the largest applicable value. 533 This parameter must be a number between 0x10000 and 0x1FFFF */ 534 535 uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. 536 This parameter must be a number between 0x0001 and 0x3FFF */ 537 538 uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. 539 This parameter must be a number between 0 and 64 */ 540 541 uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. 542 This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ 543 544 uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. 545 This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ 546 547 } FDCAN_TT_ConfigTypeDef; 548 549 /** 550 * @brief FDCAN Trigger structure definition 551 */ 552 typedef struct 553 { 554 uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. 555 This parameter must be a number between 0 and 63 */ 556 557 uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. 558 This parameter must be a number between 0 and 0xFFFF */ 559 560 uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. 561 This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ 562 563 uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. 564 This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. 565 This parameter must be a number between 0 and RepeatFactor */ 566 567 uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. 568 If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element 569 becomes active. 570 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ 571 572 uint32_t TmEventExt; /*!< Enable or disable the external time mark event. 573 If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when 574 trigger memory element becomes active. 575 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ 576 577 uint32_t TriggerType; /*!< Specifies the trigger type. 578 This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ 579 580 uint32_t FilterType; /*!< Specifies the filter identifier type. 581 This parameter can be a value of @ref FDCAN_id_type */ 582 583 uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. 584 This parameter can be a value of @ref FDCAN_Tx_location. 585 This parameter is taken in consideration only if the trigger is configured for 586 transmission. */ 587 588 uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. 589 This parameter is taken in consideration only if the trigger is configured for 590 reception. 591 This parameter must be a number between: 592 - 0 and 127, if FilterType is FDCAN_STANDARD_ID 593 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ 594 595 } FDCAN_TriggerTypeDef; 596 597 /** 598 * @brief FDCAN TT Operation Status structure definition 599 */ 600 typedef struct 601 { 602 uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. 603 This parameter can be a value of @ref FDCAN_TT_error_level */ 604 605 uint32_t MasterState; /*!< Specifies the type of the TT master state. 606 This parameter can be a value of @ref FDCAN_TT_master_state */ 607 608 uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. 609 This parameter can be a value of @ref FDCAN_TT_sync_state */ 610 611 uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. 612 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. 613 This parameter can be: 614 - 0 : Global time not valid 615 - 1 : Global time in phase with Time Master */ 616 617 uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. 618 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. 619 This parameter can be: 620 - 0 : Local clock speed not synchronized to Time Master clock speed 621 - 1 : Synchronization Deviation = SDL */ 622 623 uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. 624 This parameter can be a number between 0 and 0xFF */ 625 626 uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. 627 This parameter can be: 628 - 0 : No global time preset pending 629 - 1 : Node waits for the global time preset to take effect */ 630 631 uint32_t GapFinished; /*!< Specifies whether a Gap is finished. 632 This parameter can be: 633 - 0 : Reset at the end of each reference message 634 - 1 : Gap finished */ 635 636 uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. 637 This parameter can be a number between 0 and 0x7 */ 638 639 uint32_t GapStarted; /*!< Specifies whether a Gap is started. 640 This parameter can be: 641 - 0 : No Gap in schedule 642 - 1 : Gap time after Basic Cycle has started */ 643 644 uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced. 645 This parameter can be: 646 - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 647 - 1 : Reference message with Next_is_Gap = 1 received */ 648 649 uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. 650 This parameter can be: 651 - 0 : Application Watchdog served in time 652 - 1 : Failed to serve Application Watchdog in time */ 653 654 uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. 655 This parameter can be: 656 - 0 : No external clock synchronization pending 657 - 1 : Node waits for external clock synchronization to take effect */ 658 659 uint32_t PhaseLock; /*!< Specifies the Phase Lock State. 660 This parameter can be: 661 - 0 : Phase outside range 662 - 1 : Phase inside range */ 663 664 } FDCAN_TTOperationStatusTypeDef; 665 666 /** 667 * @brief FDCAN Message RAM blocks 668 */ 669 typedef struct 670 { 671 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 672 This parameter must be a 32-bit word address */ 673 674 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 675 This parameter must be a 32-bit word address */ 676 677 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 678 This parameter must be a 32-bit word address */ 679 680 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 681 This parameter must be a 32-bit word address */ 682 683 uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. 684 This parameter must be a 32-bit word address */ 685 686 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 687 This parameter must be a 32-bit word address */ 688 689 uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. 690 This parameter must be a 32-bit word address */ 691 692 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 693 This parameter must be a 32-bit word address */ 694 695 uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. 696 This parameter must be a 32-bit word address */ 697 698 uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. 699 This parameter must be a 32-bit word address */ 700 701 } FDCAN_MsgRamAddressTypeDef; 702 703 /** 704 * @brief FDCAN handle structure definition 705 */ 706 typedef struct 707 { 708 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 709 710 TTCAN_TypeDef *ttcan; /*!< TT register base address */ 711 712 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 713 714 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 715 716 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 717 of latest Tx FIFO/Queue request */ 718 719 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 720 721 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 722 723 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 724 725 726 } FDCAN_HandleTypeDef; 727 728 729 /** 730 * @} 731 */ 732 733 /* Exported constants --------------------------------------------------------*/ 734 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 735 * @{ 736 */ 737 738 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 739 * @{ 740 */ 741 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 742 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 743 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 744 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 745 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 746 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 747 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 748 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 749 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 750 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 751 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 752 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 753 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 754 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 755 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 756 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 757 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ 758 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ 759 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ 760 #define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ 761 #define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ 762 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ 763 #define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ 764 #define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ 765 #define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ 766 767 /** 768 * @} 769 */ 770 771 /** @defgroup FDCAN_frame_format FDCAN Frame Format 772 * @{ 773 */ 774 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 775 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 776 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 782 * @{ 783 */ 784 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 785 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 786 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 787 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 788 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 789 /** 790 * @} 791 */ 792 793 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration 794 * @{ 795 */ 796 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ 797 #define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ 798 /** 799 * @} 800 */ 801 802 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 803 * @{ 804 */ 805 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 806 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */ 807 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */ 808 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */ 809 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */ 810 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */ 811 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */ 812 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */ 813 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */ 814 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */ 815 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */ 816 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */ 817 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */ 818 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */ 819 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */ 820 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length 826 * @{ 827 */ 828 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ 829 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ 830 /** 831 * @} 832 */ 833 834 /** @defgroup FDCAN_calibration_state FDCAN Calibration State 835 * @{ 836 */ 837 #define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ 838 #define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ 839 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ 840 /** 841 * @} 842 */ 843 844 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter 845 * @{ 846 */ 847 #define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ 848 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ 849 #define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size 855 * @{ 856 */ 857 #define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ 858 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ 859 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ 860 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ 861 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ 862 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ 863 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ 864 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 870 * @{ 871 */ 872 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 873 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 874 /** 875 * @} 876 */ 877 878 /** @defgroup FDCAN_id_type FDCAN ID Type 879 * @{ 880 */ 881 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 882 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 883 /** 884 * @} 885 */ 886 887 /** @defgroup FDCAN_frame_type FDCAN Frame Type 888 * @{ 889 */ 890 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 891 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 892 /** 893 * @} 894 */ 895 896 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 897 * @{ 898 */ 899 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 900 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 901 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 902 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 903 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 904 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 905 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 906 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 907 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 908 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 909 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 910 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 911 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 912 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 913 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 914 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 915 /** 916 * @} 917 */ 918 919 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 920 * @{ 921 */ 922 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 923 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 924 /** 925 * @} 926 */ 927 928 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 929 * @{ 930 */ 931 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 932 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 933 /** 934 * @} 935 */ 936 937 /** @defgroup FDCAN_format FDCAN format 938 * @{ 939 */ 940 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 941 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 942 /** 943 * @} 944 */ 945 946 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 947 * @{ 948 */ 949 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 950 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 951 /** 952 * @} 953 */ 954 955 /** @defgroup FDCAN_filter_type FDCAN Filter Type 956 * @{ 957 */ 958 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 959 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 960 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 961 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 962 /** 963 * @} 964 */ 965 966 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 967 * @{ 968 */ 969 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 970 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 971 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 972 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 973 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 974 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 975 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 976 #define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ 977 /** 978 * @} 979 */ 980 981 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 982 * @{ 983 */ 984 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 985 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 986 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 987 #define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ 988 #define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ 989 #define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ 990 #define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ 991 #define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ 992 #define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ 993 #define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ 994 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ 995 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ 996 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ 997 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ 998 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ 999 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ 1000 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ 1001 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ 1002 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ 1003 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ 1004 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ 1005 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ 1006 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ 1007 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ 1008 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ 1009 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ 1010 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ 1011 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ 1012 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ 1013 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ 1014 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ 1015 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ 1016 /** 1017 * @} 1018 */ 1019 1020 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 1021 * @{ 1022 */ 1023 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 1024 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 1025 #define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ 1026 #define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ 1027 #define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ 1028 #define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ 1029 #define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ 1030 #define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ 1031 #define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ 1032 #define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ 1033 #define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ 1034 #define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ 1035 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ 1036 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ 1037 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ 1038 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ 1039 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ 1040 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ 1041 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ 1042 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ 1043 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ 1044 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ 1045 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ 1046 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ 1047 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ 1048 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ 1049 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ 1050 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ 1051 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ 1052 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ 1053 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ 1054 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ 1055 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ 1056 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ 1057 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ 1058 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ 1059 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ 1060 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ 1061 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ 1062 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ 1063 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ 1064 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ 1065 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ 1066 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ 1067 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ 1068 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ 1069 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ 1070 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ 1071 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ 1072 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ 1073 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ 1074 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ 1075 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ 1076 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ 1077 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ 1078 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ 1079 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ 1080 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ 1081 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ 1082 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ 1083 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ 1084 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ 1085 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ 1086 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ 1087 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ 1088 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ 1089 /** 1090 * @} 1091 */ 1092 1093 /** @defgroup FDCAN_event_type FDCAN Event Type 1094 * @{ 1095 */ 1096 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 1097 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 1098 /** 1099 * @} 1100 */ 1101 1102 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 1103 * @{ 1104 */ 1105 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 1106 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 1107 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 1108 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 1109 /** 1110 * @} 1111 */ 1112 1113 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 1114 * @{ 1115 */ 1116 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 1117 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 1118 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 1119 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 1120 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 1121 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 1122 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 1123 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 1124 /** 1125 * @} 1126 */ 1127 1128 /** @defgroup FDCAN_communication_state FDCAN communication state 1129 * @{ 1130 */ 1131 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 1132 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 1133 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 1134 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 1135 /** 1136 * @} 1137 */ 1138 1139 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark 1140 * @{ 1141 */ 1142 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ 1143 #define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ 1144 #define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ 1145 /** 1146 * @} 1147 */ 1148 1149 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 1150 * @{ 1151 */ 1152 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 1153 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ 1154 /** 1155 * @} 1156 */ 1157 1158 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 1159 * @{ 1160 */ 1161 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 1162 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 1163 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 1164 /** 1165 * @} 1166 */ 1167 1168 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 1169 * @{ 1170 */ 1171 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 1172 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 1178 * @{ 1179 */ 1180 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 1181 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 1182 /** 1183 * @} 1184 */ 1185 1186 /** @defgroup FDCAN_Timestamp FDCAN timestamp 1187 * @{ 1188 */ 1189 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 1190 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 1191 /** 1192 * @} 1193 */ 1194 1195 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 1196 * @{ 1197 */ 1198 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 1199 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */ 1200 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */ 1201 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */ 1202 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */ 1203 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */ 1204 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */ 1205 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */ 1206 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */ 1207 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */ 1208 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */ 1209 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */ 1210 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */ 1211 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */ 1212 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */ 1213 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */ 1214 /** 1215 * @} 1216 */ 1217 1218 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 1219 * @{ 1220 */ 1221 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 1222 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 1223 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 1224 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 1225 /** 1226 * @} 1227 */ 1228 1229 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload 1230 * @{ 1231 */ 1232 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ 1233 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ 1234 /** 1235 * @} 1236 */ 1237 1238 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor 1239 * @{ 1240 */ 1241 #define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ 1242 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ 1243 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ 1244 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ 1245 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ 1246 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ 1247 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ 1248 /** 1249 * @} 1250 */ 1251 1252 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type 1253 * @{ 1254 */ 1255 #define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ 1256 #define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ 1257 #define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ 1258 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ 1259 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ 1260 #define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ 1261 #define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ 1262 #define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ 1263 #define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ 1264 #define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ 1265 #define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ 1266 /** 1267 * @} 1268 */ 1269 1270 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal 1271 * @{ 1272 */ 1273 #define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1274 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ 1275 /** 1276 * @} 1277 */ 1278 1279 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external 1280 * @{ 1281 */ 1282 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1283 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ 1284 /** 1285 * @} 1286 */ 1287 1288 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode 1289 * @{ 1290 */ 1291 #define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ 1292 #define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ 1293 #define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup FDCAN_TT_operation FDCAN TT Operation 1299 * @{ 1300 */ 1301 #define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ 1302 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ 1303 /** 1304 * @} 1305 */ 1306 1307 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master 1308 * @{ 1309 */ 1310 #define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ 1311 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ 1312 /** 1313 * @} 1314 */ 1315 1316 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization 1317 * @{ 1318 */ 1319 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ 1320 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ 1321 /** 1322 * @} 1323 */ 1324 1325 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering 1326 * @{ 1327 */ 1328 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ 1329 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ 1330 /** 1331 * @} 1332 */ 1333 1334 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration 1335 * @{ 1336 */ 1337 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ 1338 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ 1339 /** 1340 * @} 1341 */ 1342 1343 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity 1344 * @{ 1345 */ 1346 #define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ 1347 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ 1348 /** 1349 * @} 1350 */ 1351 1352 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number 1353 * @{ 1354 */ 1355 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ 1356 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ 1357 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ 1358 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ 1359 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ 1360 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ 1361 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ 1362 /** 1363 * @} 1364 */ 1365 1366 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync 1367 * @{ 1368 */ 1369 #define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ 1370 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ 1371 #define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ 1372 /** 1373 * @} 1374 */ 1375 1376 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection 1377 * @{ 1378 */ 1379 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ 1380 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ 1381 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ 1382 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ 1383 /** 1384 * @} 1385 */ 1386 1387 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection 1388 * @{ 1389 */ 1390 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ 1391 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ 1392 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ 1393 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ 1394 /** 1395 * @} 1396 */ 1397 1398 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source 1399 * @{ 1400 */ 1401 #define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ 1402 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ 1403 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ 1404 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ 1405 /** 1406 * @} 1407 */ 1408 1409 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity 1410 * @{ 1411 */ 1412 #define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ 1413 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ 1414 /** 1415 * @} 1416 */ 1417 1418 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source 1419 * @{ 1420 */ 1421 #define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ 1422 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ 1423 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ 1424 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ 1425 /** 1426 * @} 1427 */ 1428 1429 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level 1430 * @{ 1431 */ 1432 #define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ 1433 #define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ 1434 #define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ 1435 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ 1436 /** 1437 * @} 1438 */ 1439 1440 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State 1441 * @{ 1442 */ 1443 #define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ 1444 #define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ 1445 #define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ 1446 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ 1447 /** 1448 * @} 1449 */ 1450 1451 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State 1452 * @{ 1453 */ 1454 #define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ 1455 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ 1456 #define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ 1457 #define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ 1458 /** 1459 * @} 1460 */ 1461 1462 /** @defgroup Interrupt_Masks Interrupt masks 1463 * @{ 1464 */ 1465 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ 1466 #define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup FDCAN_flags FDCAN Flags 1472 * @{ 1473 */ 1474 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 1475 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 1476 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 1477 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 1478 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ 1479 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 1480 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 1481 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ 1482 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 1483 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 1484 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 1485 #define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ 1486 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 1487 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 1488 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 1489 #define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ 1490 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 1491 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 1492 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 1493 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 1494 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 1495 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 1496 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 1497 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 1498 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 1499 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 1500 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 1501 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 1502 #define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ 1503 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ 1504 /** 1505 * @} 1506 */ 1507 1508 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 1509 * @{ 1510 */ 1511 1512 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 1513 * @{ 1514 */ 1515 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 1516 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 1517 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 1518 /** 1519 * @} 1520 */ 1521 1522 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 1523 * @{ 1524 */ 1525 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 1526 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ 1527 /** 1528 * @} 1529 */ 1530 1531 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 1532 * @{ 1533 */ 1534 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 1535 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 1536 /** 1537 * @} 1538 */ 1539 1540 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts 1541 * @{ 1542 */ 1543 #define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ 1544 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ 1545 /** 1546 * @} 1547 */ 1548 1549 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 1550 * @{ 1551 */ 1552 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 1553 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 1554 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ 1555 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 1556 /** 1557 * @} 1558 */ 1559 1560 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 1561 * @{ 1562 */ 1563 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 1564 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 1565 #define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ 1566 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 1567 /** 1568 * @} 1569 */ 1570 1571 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 1572 * @{ 1573 */ 1574 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 1575 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 1576 #define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ 1577 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 1578 /** 1579 * @} 1580 */ 1581 1582 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 1583 * @{ 1584 */ 1585 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 1586 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 1587 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 1588 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 1589 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 1590 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 1591 /** 1592 * @} 1593 */ 1594 1595 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 1596 * @{ 1597 */ 1598 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 1599 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 1600 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 1601 /** 1602 * @} 1603 */ 1604 1605 /** 1606 * @} 1607 */ 1608 1609 /** @defgroup FDCAN_TTflags FDCAN TT Flags 1610 * @{ 1611 */ 1612 #define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ 1613 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ 1614 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ 1615 #define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ 1616 #define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ 1617 #define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ 1618 #define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ 1619 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ 1620 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ 1621 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ 1622 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ 1623 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ 1624 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ 1625 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ 1626 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ 1627 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ 1628 #define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ 1629 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ 1630 #define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ 1631 /** 1632 * @} 1633 */ 1634 1635 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts 1636 * @{ 1637 */ 1638 1639 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts 1640 * @{ 1641 */ 1642 #define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ 1643 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ 1644 #define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ 1645 #define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ 1646 /** 1647 * @} 1648 */ 1649 1650 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts 1651 * @{ 1652 */ 1653 #define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ 1654 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ 1655 /** 1656 * @} 1657 */ 1658 1659 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt 1660 * @{ 1661 */ 1662 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ 1663 /** 1664 * @} 1665 */ 1666 1667 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts 1668 * @{ 1669 */ 1670 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ 1671 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ 1672 /** 1673 * @} 1674 */ 1675 1676 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts 1677 * @{ 1678 */ 1679 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ 1680 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ 1681 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ 1682 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ 1683 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ 1684 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ 1685 /** 1686 * @} 1687 */ 1688 1689 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts 1690 * @{ 1691 */ 1692 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ 1693 #define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ 1694 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ 1695 #define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ 1696 /** 1697 * @} 1698 */ 1699 1700 /** 1701 * @} 1702 */ 1703 1704 /** 1705 * @} 1706 */ 1707 1708 /* Exported macro ------------------------------------------------------------*/ 1709 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1710 * @{ 1711 */ 1712 1713 /** @brief Reset FDCAN handle state. 1714 * @param __HANDLE__ FDCAN handle. 1715 * @retval None 1716 */ 1717 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1718 1719 /** 1720 * @brief Enable the specified FDCAN interrupts. 1721 * @param __HANDLE__ FDCAN handle. 1722 * @param __INTERRUPT__ FDCAN interrupt. 1723 * This parameter can be any combination of @arg FDCAN_Interrupts 1724 * @retval None 1725 */ 1726 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1727 do{ \ 1728 (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1729 FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1730 }while(0) 1731 1732 1733 /** 1734 * @brief Disable the specified FDCAN interrupts. 1735 * @param __HANDLE__ FDCAN handle. 1736 * @param __INTERRUPT__ FDCAN interrupt. 1737 * This parameter can be any combination of @arg FDCAN_Interrupts 1738 * @retval None 1739 */ 1740 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1741 do{ \ 1742 ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ 1743 FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1744 }while(0) 1745 1746 /** 1747 * @brief Check whether the specified FDCAN interrupt is set or not. 1748 * @param __HANDLE__ FDCAN handle. 1749 * @param __INTERRUPT__ FDCAN interrupt. 1750 * This parameter can be one of @arg FDCAN_Interrupts 1751 * @retval ITStatus 1752 */ 1753 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) 1754 1755 /** 1756 * @brief Clear the specified FDCAN interrupts. 1757 * @param __HANDLE__ FDCAN handle. 1758 * @param __INTERRUPT__ specifies the interrupts to clear. 1759 * This parameter can be any combination of @arg FDCAN_Interrupts 1760 * @retval None 1761 */ 1762 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1763 do{ \ 1764 ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1765 FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1766 }while(0) 1767 1768 /** 1769 * @brief Check whether the specified FDCAN flag is set or not. 1770 * @param __HANDLE__ FDCAN handle. 1771 * @param __FLAG__ FDCAN flag. 1772 * This parameter can be one of @arg FDCAN_flags 1773 * @retval FlagStatus 1774 */ 1775 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) 1776 1777 /** 1778 * @brief Clear the specified FDCAN flags. 1779 * @param __HANDLE__ FDCAN handle. 1780 * @param __FLAG__ specifies the flags to clear. 1781 * This parameter can be any combination of @arg FDCAN_flags 1782 * @retval None 1783 */ 1784 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1785 do{ \ 1786 ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ 1787 FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ 1788 }while(0) 1789 1790 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1791 * @param __HANDLE__ FDCAN handle. 1792 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1793 * This parameter can be a value of @arg FDCAN_Interrupts 1794 * @retval ITStatus 1795 */ 1796 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__))) 1797 1798 /** 1799 * @brief Enable the specified FDCAN TT interrupts. 1800 * @param __HANDLE__ FDCAN handle. 1801 * @param __INTERRUPT__ FDCAN TT interrupt. 1802 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1803 * @retval None 1804 */ 1805 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) 1806 1807 /** 1808 * @brief Disable the specified FDCAN TT interrupts. 1809 * @param __HANDLE__ FDCAN handle. 1810 * @param __INTERRUPT__ FDCAN TT interrupt. 1811 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1812 * @retval None 1813 */ 1814 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) 1815 1816 /** 1817 * @brief Check whether the specified FDCAN TT interrupt is set or not. 1818 * @param __HANDLE__ FDCAN handle. 1819 * @param __INTERRUPT__ FDCAN TT interrupt. 1820 * This parameter can be one of @arg FDCAN_TTInterrupts 1821 * @retval ITStatus 1822 */ 1823 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) 1824 1825 /** 1826 * @brief Clear the specified FDCAN TT interrupts. 1827 * @param __HANDLE__ FDCAN handle. 1828 * @param __INTERRUPT__ specifies the TT interrupts to clear. 1829 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1830 * @retval None 1831 */ 1832 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) 1833 1834 /** 1835 * @brief Check whether the specified FDCAN TT flag is set or not. 1836 * @param __HANDLE__ FDCAN handle. 1837 * @param __FLAG__ FDCAN TT flag. 1838 * This parameter can be one of @arg FDCAN_TTflags 1839 * @retval FlagStatus 1840 */ 1841 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) 1842 1843 /** 1844 * @brief Clear the specified FDCAN TT flags. 1845 * @param __HANDLE__ FDCAN handle. 1846 * @param __FLAG__ specifies the TT flags to clear. 1847 * This parameter can be any combination of @arg FDCAN_TTflags 1848 * @retval None 1849 */ 1850 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) 1851 1852 /** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. 1853 * @param __HANDLE__ FDCAN handle. 1854 * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. 1855 * This parameter can be a value of @arg FDCAN_TTInterrupts 1856 * @retval ITStatus 1857 */ 1858 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) 1859 1860 /** 1861 * @} 1862 */ 1863 1864 /* Exported functions --------------------------------------------------------*/ 1865 /** @addtogroup FDCAN_Exported_Functions 1866 * @{ 1867 */ 1868 1869 /** @addtogroup FDCAN_Exported_Functions_Group1 1870 * @{ 1871 */ 1872 /* Initialization and de-initialization functions *****************************/ 1873 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1874 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1875 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1876 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1877 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1878 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1879 1880 /** 1881 * @} 1882 */ 1883 1884 /** @addtogroup FDCAN_Exported_Functions_Group2 1885 * @{ 1886 */ 1887 /* Configuration functions ****************************************************/ 1888 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig); 1889 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1890 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1891 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); 1892 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 1893 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); 1894 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1895 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1896 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); 1897 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1898 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1899 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 1900 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1901 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1902 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1903 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); 1904 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1905 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1906 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1907 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1908 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); 1909 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1910 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1911 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 1912 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 1913 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1914 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1915 /** 1916 * @} 1917 */ 1918 1919 /** @addtogroup FDCAN_Exported_Functions_Group3 1920 * @{ 1921 */ 1922 /* Control functions **********************************************************/ 1923 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 1924 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 1925 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); 1926 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); 1927 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1928 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 1929 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1930 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 1931 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 1932 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 1933 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 1934 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 1935 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); 1936 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 1937 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 1938 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 1939 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1940 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1941 /** 1942 * @} 1943 */ 1944 1945 /** @addtogroup FDCAN_Exported_Functions_Group4 1946 * @{ 1947 */ 1948 /* TT Configuration and control functions**************************************/ 1949 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams); 1950 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); 1951 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); 1952 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); 1953 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); 1954 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); 1955 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle); 1956 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1957 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1958 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1959 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1960 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 1961 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 1962 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 1963 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 1964 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); 1965 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); 1966 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); 1967 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 1968 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 1969 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus); 1970 /** 1971 * @} 1972 */ 1973 1974 /** @addtogroup FDCAN_Exported_Functions_Group5 1975 * @{ 1976 */ 1977 /* Interrupts management ******************************************************/ 1978 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 1979 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine); 1980 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); 1981 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 1982 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); 1983 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); 1984 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 1985 /** 1986 * @} 1987 */ 1988 1989 /** @addtogroup FDCAN_Exported_Functions_Group6 1990 * @{ 1991 */ 1992 /* Callback functions *********************************************************/ 1993 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); 1994 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 1995 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 1996 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 1997 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 1998 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1999 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 2000 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2001 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2002 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 2003 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 2004 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 2005 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 2006 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); 2007 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); 2008 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); 2009 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); 2010 /** 2011 * @} 2012 */ 2013 2014 /** @addtogroup FDCAN_Exported_Functions_Group7 2015 * @{ 2016 */ 2017 /* Peripheral State functions *************************************************/ 2018 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 2019 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 2020 /** 2021 * @} 2022 */ 2023 2024 /** 2025 * @} 2026 */ 2027 2028 /* Private types -------------------------------------------------------------*/ 2029 /** @defgroup FDCAN_Private_Types FDCAN Private Types 2030 * @{ 2031 */ 2032 2033 /** 2034 * @} 2035 */ 2036 2037 /* Private variables ---------------------------------------------------------*/ 2038 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 2039 * @{ 2040 */ 2041 2042 /** 2043 * @} 2044 */ 2045 2046 /* Private constants ---------------------------------------------------------*/ 2047 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 2048 * @{ 2049 */ 2050 2051 /** 2052 * @} 2053 */ 2054 2055 /* Private macros ------------------------------------------------------------*/ 2056 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 2057 * @{ 2058 */ 2059 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 2060 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 2061 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 2062 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 2063 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 2064 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 2065 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 2066 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 2067 2068 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ 2069 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) 2070 2071 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 2072 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 2073 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 2074 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 2075 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 2076 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 2077 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 2078 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 2079 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 2080 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 2081 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 2082 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 2083 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 2084 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 2085 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 2086 ((CKDIV) == FDCAN_CLOCK_DIV30)) 2087 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 2088 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 2089 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 2090 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 2091 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 2092 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 2093 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 2094 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 2095 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) 2096 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) 2097 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ 2098 ((SIZE) == FDCAN_DATA_BYTES_12) || \ 2099 ((SIZE) == FDCAN_DATA_BYTES_16) || \ 2100 ((SIZE) == FDCAN_DATA_BYTES_20) || \ 2101 ((SIZE) == FDCAN_DATA_BYTES_24) || \ 2102 ((SIZE) == FDCAN_DATA_BYTES_32) || \ 2103 ((SIZE) == FDCAN_DATA_BYTES_48) || \ 2104 ((SIZE) == FDCAN_DATA_BYTES_64)) 2105 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 2106 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 2107 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 2108 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 2109 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 2110 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 2111 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 2112 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 2113 ((CONFIG) == FDCAN_FILTER_HP ) || \ 2114 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 2115 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ 2116 ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) 2117 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 2118 ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ 2119 ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ 2120 ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ 2121 ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ 2122 ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ 2123 ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ 2124 ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ 2125 ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ 2126 ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ 2127 ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ 2128 ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ 2129 ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ 2130 ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ 2131 ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ 2132 ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) 2133 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 2134 ((FIFO) == FDCAN_RX_FIFO1)) 2135 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 2136 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 2137 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 2138 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2139 ((TYPE) == FDCAN_FILTER_MASK )) 2140 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 2141 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2142 ((TYPE) == FDCAN_FILTER_MASK ) || \ 2143 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 2144 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 2145 ((TYPE) == FDCAN_REMOTE_FRAME)) 2146 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 2147 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 2148 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 2149 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 2150 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 2151 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 2152 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 2153 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 2154 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 2155 ((DLC) == FDCAN_DLC_BYTES_12) || \ 2156 ((DLC) == FDCAN_DLC_BYTES_16) || \ 2157 ((DLC) == FDCAN_DLC_BYTES_20) || \ 2158 ((DLC) == FDCAN_DLC_BYTES_24) || \ 2159 ((DLC) == FDCAN_DLC_BYTES_32) || \ 2160 ((DLC) == FDCAN_DLC_BYTES_48) || \ 2161 ((DLC) == FDCAN_DLC_BYTES_64)) 2162 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 2163 ((ESI) == FDCAN_ESI_PASSIVE)) 2164 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 2165 ((BRS) == FDCAN_BRS_ON )) 2166 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 2167 ((FDF) == FDCAN_FD_CAN )) 2168 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 2169 ((EFC) == FDCAN_STORE_TX_EVENTS)) 2170 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) 2171 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) 2172 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ 2173 ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ 2174 ((FIFO) == FDCAN_CFG_RX_FIFO1 )) 2175 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 2176 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 2177 ((DESTINATION) == FDCAN_REJECT )) 2178 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 2179 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 2180 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 2181 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 2182 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 2183 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 2184 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 2185 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 2186 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 2187 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 2188 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 2189 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 2190 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 2191 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 2192 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 2193 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 2194 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 2195 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 2196 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 2197 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 2198 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 2199 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 2200 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 2201 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 2202 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 2203 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 2204 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ 2205 ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) 2206 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ 2207 ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ 2208 ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) 2209 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ 2210 ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) 2211 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ 2212 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ 2213 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ 2214 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ 2215 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ 2216 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ 2217 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) 2218 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ 2219 ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ 2220 ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ 2221 ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ 2222 ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ 2223 ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ 2224 ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ 2225 ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ 2226 ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ 2227 ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ 2228 ((TYPE) == FDCAN_TT_END_OF_LIST )) 2229 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ 2230 ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) 2231 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ 2232 ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) 2233 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ 2234 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ 2235 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) 2236 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ 2237 ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) 2238 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ 2239 ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) 2240 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ 2241 ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) 2242 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ 2243 ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) 2244 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ 2245 ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) 2246 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ 2247 ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) 2248 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ 2249 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ 2250 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ 2251 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ 2252 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ 2253 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ 2254 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) 2255 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ 2256 ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ 2257 ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) 2258 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) 2259 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) 2260 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) 2261 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) 2262 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) 2263 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ 2264 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ 2265 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ 2266 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) 2267 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ 2268 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ 2269 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ 2270 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) 2271 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) 2272 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ 2273 ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ 2274 ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ 2275 ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) 2276 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ 2277 ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) 2278 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ 2279 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ 2280 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ 2281 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) 2282 /** 2283 * @} 2284 */ 2285 2286 /* Private functions prototypes ----------------------------------------------*/ 2287 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes 2288 * @{ 2289 */ 2290 2291 /** 2292 * @} 2293 */ 2294 2295 /* Private functions ---------------------------------------------------------*/ 2296 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions 2297 * @{ 2298 */ 2299 2300 /** 2301 * @} 2302 */ 2303 /** 2304 * @} 2305 */ 2306 2307 /** 2308 * @} 2309 */ 2310 #endif /* FDCAN1 */ 2311 2312 #ifdef __cplusplus 2313 } 2314 #endif 2315 2316 #endif /* STM32MP1xx_HAL_FDCAN_H */ 2317 2318 2319 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2320
