1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) API to access to MCU info (CPUID register)
17 (+) API to enable fault handler (SHCSR accesses)
18
19 @endverbatim
20 ******************************************************************************
21 * @attention
22 *
23 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
24 * All rights reserved.</center></h2>
25 *
26 * This software component is licensed by ST under BSD 3-Clause license,
27 * the "License"; You may not use this file except in compliance with the
28 * License. You may obtain a copy of the License at:
29 * opensource.org/licenses/BSD-3-Clause
30 *
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32L5xx_LL_CORTEX_H
36 #define STM32L5xx_LL_CORTEX_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l5xx.h"
44
45 /** @addtogroup STM32L5xx_LL_Driver
46 * @{
47 */
48
49 /** @defgroup CORTEX_LL CORTEX
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57
58 /* Private macros ------------------------------------------------------------*/
59
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
63 * @{
64 */
65
66 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
67 * @{
68 */
69 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
71 /**
72 * @}
73 */
74
75 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
76 * @{
77 */
78 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
79 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
80 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
81 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
82 /**
83 * @}
84 */
85
86 #if (__MPU_PRESENT == 1)
87 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
88 * @{
89 */
90 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
91 #define LL_MPU_CTRL_HARDFAULT_NMI 2U
92 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
93 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
94 /**
95 * @}
96 */
97
98 /** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes
99 * @{
100 */
101 #define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
102 #define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
103 #define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
104 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
105
106 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
107 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
108 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
109
110 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
111 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
112
113 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
114 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
115 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
116 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
117 /**
118 * @}
119 */
120
121 /** @defgroup CORTEX_LL_MPU_Region_Enable MPU Region Enable
122 * @{
123 */
124 #define LL_MPU_REGION_ENABLE 1U
125 #define LL_MPU_REGION_DISABLE 0U
126 /**
127 * @}
128 */
129
130 /** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access
131 * @{
132 */
133 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
134 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
135 /**
136 * @}
137 */
138
139 /** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable
140 * @{
141 */
142 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
143 #define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
144 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
145 /**
146 * @}
147 */
148
149 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes
150 * @{
151 */
152 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
153 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
154 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
155 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
156 /**
157 * @}
158 */
159
160 /** @defgroup CORTEX_LL_MPU_Region_Number MPU Region Number
161 * @{
162 */
163 #define LL_MPU_REGION_NUMBER0 0U
164 #define LL_MPU_REGION_NUMBER1 1U
165 #define LL_MPU_REGION_NUMBER2 2U
166 #define LL_MPU_REGION_NUMBER3 3U
167 #define LL_MPU_REGION_NUMBER4 4U
168 #define LL_MPU_REGION_NUMBER5 5U
169 #define LL_MPU_REGION_NUMBER6 6U
170 #define LL_MPU_REGION_NUMBER7 7U
171 /**
172 * @}
173 */
174
175 /** @defgroup CORTEX_LL_MPU_Attributes_Number MPU Memory Attributes Number
176 * @{
177 */
178 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
179 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
180 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
181 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
182 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
183 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
184 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
185 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
186 /**
187 * @}
188 */
189
190 #endif /* __MPU_PRESENT */
191
192 /**
193 * @}
194 */
195
196 /* Exported macro ------------------------------------------------------------*/
197
198 /* Exported functions --------------------------------------------------------*/
199 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
200 * @{
201 */
202
203 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
204 * @{
205 */
206
207 /**
208 * @brief This function checks if the Systick counter flag is active or not.
209 * @note It can be used in timeout function on application side.
210 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
211 * @retval State of bit (1 or 0).
212 */
LL_SYSTICK_IsActiveCounterFlag(void)213 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
214 {
215 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
216 }
217
218 /**
219 * @brief Configures the SysTick clock source
220 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
221 * @param Source This parameter can be one of the following values:
222 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
223 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
224 * @retval None
225 */
LL_SYSTICK_SetClkSource(uint32_t Source)226 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
227 {
228 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
229 {
230 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
231 }
232 else
233 {
234 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
235 }
236 }
237
238 /**
239 * @brief Get the SysTick clock source
240 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
241 * @retval Returned value can be one of the following values:
242 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
243 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
244 */
LL_SYSTICK_GetClkSource(void)245 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
246 {
247 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
248 }
249
250 /**
251 * @brief Enable SysTick exception request
252 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
253 * @retval None
254 */
LL_SYSTICK_EnableIT(void)255 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
256 {
257 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
258 }
259
260 /**
261 * @brief Disable SysTick exception request
262 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
263 * @retval None
264 */
LL_SYSTICK_DisableIT(void)265 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
266 {
267 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
268 }
269
270 /**
271 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
272 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
273 * @retval State of bit (1 or 0).
274 */
LL_SYSTICK_IsEnabledIT(void)275 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
276 {
277 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
278 }
279
280 /**
281 * @}
282 */
283
284 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
285 * @{
286 */
287
288 /**
289 * @brief Processor uses sleep as its low power mode
290 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
291 * @retval None
292 */
LL_LPM_EnableSleep(void)293 __STATIC_INLINE void LL_LPM_EnableSleep(void)
294 {
295 /* Clear SLEEPDEEP bit of Cortex System Control Register */
296 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
297 }
298
299 /**
300 * @brief Processor uses deep sleep as its low power mode
301 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
302 * @retval None
303 */
LL_LPM_EnableDeepSleep(void)304 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
305 {
306 /* Set SLEEPDEEP bit of Cortex System Control Register */
307 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
308 }
309
310 /**
311 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
312 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
313 * empty main application.
314 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
315 * @retval None
316 */
LL_LPM_EnableSleepOnExit(void)317 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
318 {
319 /* Set SLEEPONEXIT bit of Cortex System Control Register */
320 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
321 }
322
323 /**
324 * @brief Do not sleep when returning to Thread mode.
325 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
326 * @retval None
327 */
LL_LPM_DisableSleepOnExit(void)328 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
329 {
330 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
331 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
332 }
333
334 /**
335 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
336 * processor.
337 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
338 * @retval None
339 */
LL_LPM_EnableEventOnPend(void)340 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
341 {
342 /* Set SEVEONPEND bit of Cortex System Control Register */
343 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
344 }
345
346 /**
347 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
348 * excluded
349 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
350 * @retval None
351 */
LL_LPM_DisableEventOnPend(void)352 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
353 {
354 /* Clear SEVEONPEND bit of Cortex System Control Register */
355 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
356 }
357
358 /**
359 * @}
360 */
361
362 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
363 * @{
364 */
365
366 /**
367 * @brief Enable a fault in System handler control register (SHCSR)
368 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
369 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
370 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
371 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
372 * @param Fault This parameter can be a combination of the following values:
373 * @arg @ref LL_HANDLER_FAULT_USG
374 * @arg @ref LL_HANDLER_FAULT_BUS
375 * @arg @ref LL_HANDLER_FAULT_MEM
376 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
377 *
378 * (*) value applicable in secure when the system implements the security.
379 * @retval None
380 */
LL_HANDLER_EnableFault(uint32_t Fault)381 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
382 {
383 /* Enable the system handler fault */
384 SET_BIT(SCB->SHCSR, Fault);
385 }
386
387 /**
388 * @brief Disable a fault in System handler control register (SHCSR)
389 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
390 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
391 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
392 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
393 * @param Fault This parameter can be a combination of the following values:
394 * @arg @ref LL_HANDLER_FAULT_USG
395 * @arg @ref LL_HANDLER_FAULT_BUS
396 * @arg @ref LL_HANDLER_FAULT_MEM
397 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
398 *
399 * (*) value applicable in secure when the system implements the security.
400 * @retval None
401 */
LL_HANDLER_DisableFault(uint32_t Fault)402 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
403 {
404 /* Disable the system handler fault */
405 CLEAR_BIT(SCB->SHCSR, Fault);
406 }
407
408 /**
409 * @}
410 */
411
412 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
413 * @{
414 */
415
416 /**
417 * @brief Get Implementer code
418 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
419 * @retval Value should be equal to 0x41 for ARM
420 */
LL_CPUID_GetImplementer(void)421 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
422 {
423 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
424 }
425
426 /**
427 * @brief Get Variant number (The r value in the rnpn product revision identifier)
428 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
429 * @retval Value between 0 and 255 (0x0: revision 0)
430 */
LL_CPUID_GetVariant(void)431 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
432 {
433 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
434 }
435
436 /**
437 * @brief Get Constant number
438 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
439 * @retval Value should be equal to 0xF for Cortex-M33 devices
440 */
LL_CPUID_GetConstant(void)441 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
442 {
443 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
444 }
445
446 /**
447 * @brief Get Part number
448 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
449 * @retval Value should be equal to 0xD21 for Cortex-M33
450 */
LL_CPUID_GetParNo(void)451 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
452 {
453 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
454 }
455
456 /**
457 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
458 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
459 * @retval Value between 0 and 255 (0x1: patch 1)
460 */
LL_CPUID_GetRevision(void)461 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
462 {
463 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
464 }
465
466 /**
467 * @}
468 */
469
470 #if __MPU_PRESENT
471 /** @defgroup CORTEX_LL_EF_MPU MPU
472 * @{
473 */
474
475 /**
476 * @brief Enable MPU with input options
477 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable\n
478 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable\n
479 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable
480 * @param MPU_Control This parameter can be one of the following values:
481 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
482 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
483 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
484 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
485 * @retval None
486 */
LL_MPU_Enable(uint32_t MPU_Control)487 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
488 {
489 /* Enable the MPU*/
490 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
491
492 /* Ensure MPU settings take effects */
493 __DSB();
494
495 /* Sequence instruction fetches using update settings */
496 __ISB();
497 }
498
499 /**
500 * @brief Disable MPU
501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable\n
502 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable\n
503 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable
504 * @retval None
505 */
LL_MPU_Disable(void)506 __STATIC_INLINE void LL_MPU_Disable(void)
507 {
508 /* Make sure outstanding transfers are done */
509 __DMB();
510 /* Disable MPU*/
511 WRITE_REG(MPU->CTRL, 0U);
512 }
513
514 /**
515 * @brief Check if MPU is enabled or not
516 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
517 * @retval State of bit (1 or 0).
518 */
LL_MPU_IsEnabled(void)519 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
520 {
521 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
522 }
523
524 /**
525 * @brief Enable a MPU region
526 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion\n
527 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion
528 * @param Region This parameter can be one of the following values:
529 * @arg @ref LL_MPU_REGION_NUMBER0
530 * @arg @ref LL_MPU_REGION_NUMBER1
531 * @arg @ref LL_MPU_REGION_NUMBER2
532 * @arg @ref LL_MPU_REGION_NUMBER3
533 * @arg @ref LL_MPU_REGION_NUMBER4
534 * @arg @ref LL_MPU_REGION_NUMBER5
535 * @arg @ref LL_MPU_REGION_NUMBER6
536 * @arg @ref LL_MPU_REGION_NUMBER7
537 * @note cortex-M33 support 8 secure and 8 non secure regions.
538 * @retval None
539 */
LL_MPU_EnableRegion(uint32_t Region)540 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
541 {
542 /* Set Region number */
543 WRITE_REG(MPU->RNR, Region);
544
545 /* Enable the MPU region */
546 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
547 }
548
549 /**
550 * @brief Check if MPU region is enabled or not
551 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion\n
552 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion
553 * @param Region This parameter can be one of the following values:
554 * @arg @ref LL_MPU_REGION_NUMBER0
555 * @arg @ref LL_MPU_REGION_NUMBER1
556 * @arg @ref LL_MPU_REGION_NUMBER2
557 * @arg @ref LL_MPU_REGION_NUMBER3
558 * @arg @ref LL_MPU_REGION_NUMBER4
559 * @arg @ref LL_MPU_REGION_NUMBER5
560 * @arg @ref LL_MPU_REGION_NUMBER6
561 * @arg @ref LL_MPU_REGION_NUMBER7
562 * @note cortex-M33 support 8 secure and 8 non secure regions.
563 * @retval State of bit (1 or 0).
564 */
LL_MPU_IsEnabledRegion(uint32_t Region)565 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
566 {
567 return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
568 }
569
570 /**
571 * @brief Disable a MPU region
572 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
573 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion
574 * @param Region This parameter can be one of the following values:
575 * @arg @ref LL_MPU_REGION_NUMBER0
576 * @arg @ref LL_MPU_REGION_NUMBER1
577 * @arg @ref LL_MPU_REGION_NUMBER2
578 * @arg @ref LL_MPU_REGION_NUMBER3
579 * @arg @ref LL_MPU_REGION_NUMBER4
580 * @arg @ref LL_MPU_REGION_NUMBER5
581 * @arg @ref LL_MPU_REGION_NUMBER6
582 * @arg @ref LL_MPU_REGION_NUMBER7
583 * @note cortex-M33 support 8 secure and 8 non secure regions.
584 * @retval None
585 */
LL_MPU_DisableRegion(uint32_t Region)586 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
587 {
588 /* Set Region number */
589 WRITE_REG(MPU->RNR, Region);
590
591 /* Disable the MPU region */
592 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
593 }
594
595 /**
596 * @brief Configure and enable a MPU region
597 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
598 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
599 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
600 * MPU_RBAR XN LL_MPU_ConfigRegion\n
601 * MPU_RBAR AP LL_MPU_ConfigRegion\n
602 * MPU_RBAR SH LL_MPU_ConfigRegion\n
603 * MPU_RLAR EN LL_MPU_ConfigRegion\n
604 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion
605 * @param Region This parameter can be one of the following values:
606 * @arg @ref LL_MPU_REGION_NUMBER0
607 * @arg @ref LL_MPU_REGION_NUMBER1
608 * @arg @ref LL_MPU_REGION_NUMBER2
609 * @arg @ref LL_MPU_REGION_NUMBER3
610 * @arg @ref LL_MPU_REGION_NUMBER4
611 * @arg @ref LL_MPU_REGION_NUMBER5
612 * @arg @ref LL_MPU_REGION_NUMBER6
613 * @arg @ref LL_MPU_REGION_NUMBER7
614 * @param AttrIndx This parameter can be one of the following values:
615 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
616 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
617 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
618 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
619 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
620 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
621 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
622 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
623 * @param BaseAddress Value of region base address
624 * @param LimitAddress Value of region limit address
625 * @param Attributes This parameter can be a combination of the following values:
626 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
627 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
628 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
629 * @note cortex-M33 support 8 secure and 8 non secure regions.
630 * @retval None
631 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)632 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress)
633 {
634 /* Set Region number */
635 WRITE_REG(MPU->RNR, Region);
636
637 /* Set base address */
638 MPU->RBAR |= Attributes;
639 /* Set base address */
640 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
641
642 /* Set limit address */
643 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
644 /* Configure MPU */
645 MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
646 }
647
648 /**
649 * @brief Configure a MPU region address range
650 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
651 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
652 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
653 * @param Region This parameter can be one of the following values:
654 * @arg @ref LL_MPU_REGION_NUMBER0
655 * @arg @ref LL_MPU_REGION_NUMBER1
656 * @arg @ref LL_MPU_REGION_NUMBER2
657 * @arg @ref LL_MPU_REGION_NUMBER3
658 * @arg @ref LL_MPU_REGION_NUMBER4
659 * @arg @ref LL_MPU_REGION_NUMBER5
660 * @arg @ref LL_MPU_REGION_NUMBER6
661 * @arg @ref LL_MPU_REGION_NUMBER7
662 * @param BaseAddress Value of region base address
663 * @param LimitAddress Value of region limit address
664 * @note cortex-M33 support 8 secure and 8 non secure regions.
665 * @retval None
666 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)667 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
668 {
669 /* Set Region number */
670 WRITE_REG(MPU->RNR, Region);
671
672 /* Set base address */
673 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ;
674
675 /* Set limit address */
676 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
677 }
678
679 /**
680 * @brief Configure a MPU attributes index
681 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes\n
682 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes\n
683 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes\n
684 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes\n
685 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes\n
686 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes\n
687 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes\n
688 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes
689 * @param AttIndex This parameter can be one of the following values:
690 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
691 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
692 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
693 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
694 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
695 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
696 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
697 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
698 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
699 * @retval None
700 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)701 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
702 {
703 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
704 {
705 /* Program MPU_MAIR0 */
706 WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U)));
707 }
708 else
709 {
710 /* Program MPU_MAIR1 */
711 WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
712 }
713 }
714
715 /**
716 * @brief Configure a MPU region base address
717 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
718 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress
719 * @param Region This parameter can be one of the following values:
720 * @arg @ref LL_MPU_REGION_NUMBER0
721 * @arg @ref LL_MPU_REGION_NUMBER1
722 * @arg @ref LL_MPU_REGION_NUMBER2
723 * @arg @ref LL_MPU_REGION_NUMBER3
724 * @arg @ref LL_MPU_REGION_NUMBER4
725 * @arg @ref LL_MPU_REGION_NUMBER5
726 * @arg @ref LL_MPU_REGION_NUMBER6
727 * @arg @ref LL_MPU_REGION_NUMBER7
728 * @param BaseAddress Value of region base address
729 * @note cortex-M33 support 8 secure and 8 non secure regions.
730 * @retval None
731 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)732 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
733 {
734 /* Set Region number */
735 WRITE_REG(MPU->RNR, Region);
736 /* Set base address */
737 MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U);
738 }
739
740 /**
741 * @brief Get a MPU region base address
742 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
743 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress
744 * @param Region This parameter can be one of the following values:
745 * @arg @ref LL_MPU_REGION_NUMBER0
746 * @arg @ref LL_MPU_REGION_NUMBER1
747 * @arg @ref LL_MPU_REGION_NUMBER2
748 * @arg @ref LL_MPU_REGION_NUMBER3
749 * @arg @ref LL_MPU_REGION_NUMBER4
750 * @arg @ref LL_MPU_REGION_NUMBER5
751 * @arg @ref LL_MPU_REGION_NUMBER6
752 * @arg @ref LL_MPU_REGION_NUMBER7
753 * @retval None
754 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)755 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
756 {
757 /* Set Region number */
758 WRITE_REG(MPU->RNR, Region);
759 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
760 }
761
762 /**
763 * @brief Configure a MPU region limit address
764 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
765 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress
766 * @param Region This parameter can be one of the following values:
767 * @arg @ref LL_MPU_REGION_NUMBER0
768 * @arg @ref LL_MPU_REGION_NUMBER1
769 * @arg @ref LL_MPU_REGION_NUMBER2
770 * @arg @ref LL_MPU_REGION_NUMBER3
771 * @arg @ref LL_MPU_REGION_NUMBER4
772 * @arg @ref LL_MPU_REGION_NUMBER5
773 * @arg @ref LL_MPU_REGION_NUMBER6
774 * @arg @ref LL_MPU_REGION_NUMBER7
775 * @param LimitAddress Value of region limit address
776 * @note cortex-M33 support 8 secure and 8 non secure regions.
777 * @retval None
778 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)779 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
780 {
781 /* Set Region number */
782 WRITE_REG(MPU->RNR, Region);
783 /* Set limit address */
784 MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U);
785 }
786
787 /**
788 * @brief Get a MPU region limit address
789 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
790 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress
791 * @param Region This parameter can be one of the following values:
792 * @arg @ref LL_MPU_REGION_NUMBER0
793 * @arg @ref LL_MPU_REGION_NUMBER1
794 * @arg @ref LL_MPU_REGION_NUMBER2
795 * @arg @ref LL_MPU_REGION_NUMBER3
796 * @arg @ref LL_MPU_REGION_NUMBER4
797 * @arg @ref LL_MPU_REGION_NUMBER5
798 * @arg @ref LL_MPU_REGION_NUMBER6
799 * @arg @ref LL_MPU_REGION_NUMBER7
800 * @retval None
801 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)802 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
803 {
804 /* Set Region number */
805 WRITE_REG(MPU->RNR, Region);
806 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
807 }
808
809 /**
810 * @brief Configure a MPU region access attributes and enable a region
811 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
812 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
813 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
814 * MPU_RBAR SH LL_MPU_SetRegionAccess
815 * @param Region This parameter can be one of the following values:
816 * @arg @ref LL_MPU_REGION_NUMBER0
817 * @arg @ref LL_MPU_REGION_NUMBER1
818 * @arg @ref LL_MPU_REGION_NUMBER2
819 * @arg @ref LL_MPU_REGION_NUMBER3
820 * @arg @ref LL_MPU_REGION_NUMBER4
821 * @arg @ref LL_MPU_REGION_NUMBER5
822 * @arg @ref LL_MPU_REGION_NUMBER6
823 * @arg @ref LL_MPU_REGION_NUMBER7
824 * @param Attributes This parameter can be a combination of the following values:
825 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
826 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
827 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
828 * @note cortex-M33 support 8 secure and 8 non secure regions.
829 * @retval None
830 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)831 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
832 {
833 /* Set Region number */
834 WRITE_REG(MPU->RNR, Region);
835 /* Set base address */
836 MPU->RBAR |= Attributes;
837 }
838
839 /**
840 * @brief Get a MPU region access attributes
841 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
842 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
843 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
844 * MPU_RBAR SH LL_MPU_GetRegionAccess
845 * @param Region This parameter can be one of the following values:
846 * @arg @ref LL_MPU_REGION_NUMBER0
847 * @arg @ref LL_MPU_REGION_NUMBER1
848 * @arg @ref LL_MPU_REGION_NUMBER2
849 * @arg @ref LL_MPU_REGION_NUMBER3
850 * @arg @ref LL_MPU_REGION_NUMBER4
851 * @arg @ref LL_MPU_REGION_NUMBER5
852 * @arg @ref LL_MPU_REGION_NUMBER6
853 * @arg @ref LL_MPU_REGION_NUMBER7
854 * @retval None
855 */
LL_MPU_GetRegionAccess(uint32_t Region)856 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
857 {
858 /* Set Region number */
859 WRITE_REG(MPU->RNR, Region);
860 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
861 }
862
863 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
864 /**
865 * @brief Enable non-secure MPU with input options
866 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable_NS\n
867 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable_NS\n
868 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable_NS
869 * @param MPU_Control This parameter can be one of the following values:
870 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
871 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
872 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
873 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
874 * @retval None
875 */
LL_MPU_Enable_NS(uint32_t MPU_Control)876 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
877 {
878 /* Enable the MPU*/
879 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
880
881 /* Ensure MPU settings take effects */
882 __DSB();
883
884 /* Sequence instruction fetches using update settings */
885 __ISB();
886 }
887
888 /**
889 * @brief Disable non-secure MPU
890 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS\n
891 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable_NS\n
892 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable_NS
893 * @retval None
894 */
LL_MPU_Disable_NS(void)895 __STATIC_INLINE void LL_MPU_Disable_NS(void)
896 {
897 /* Make sure outstanding transfers are done */
898 __DMB();
899 /* Disable MPU*/
900 WRITE_REG(MPU_NS->CTRL, 0U);
901 }
902
903 /**
904 * @brief Check if non-secure MPU is enabled or not
905 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
906 * @retval State of bit (1 or 0).
907 */
LL_MPU_IsEnabled_NS(void)908 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
909 {
910 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
911 }
912
913 /**
914 * @brief Enable a non-secure MPU region
915 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion_NS\n
916 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS
917 * @param Region This parameter can be one of the following values:
918 * @arg @ref LL_MPU_REGION_NUMBER0
919 * @arg @ref LL_MPU_REGION_NUMBER1
920 * @arg @ref LL_MPU_REGION_NUMBER2
921 * @arg @ref LL_MPU_REGION_NUMBER3
922 * @arg @ref LL_MPU_REGION_NUMBER4
923 * @arg @ref LL_MPU_REGION_NUMBER5
924 * @arg @ref LL_MPU_REGION_NUMBER6
925 * @arg @ref LL_MPU_REGION_NUMBER7
926 * @note cortex-M33 support 8 secure and 8 non secure regions.
927 * @retval None
928 */
LL_MPU_EnableRegion_NS(uint32_t Region)929 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
930 {
931 /* Set Region number */
932 WRITE_REG(MPU_NS->RNR, Region);
933
934 /* Enable the MPU region */
935 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
936 }
937
938 /**
939 * @brief Disable a non-secure MPU region
940 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
941 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion_NS
942 * @param Region This parameter can be one of the following values:
943 * @arg @ref LL_MPU_REGION_NUMBER0
944 * @arg @ref LL_MPU_REGION_NUMBER1
945 * @arg @ref LL_MPU_REGION_NUMBER2
946 * @arg @ref LL_MPU_REGION_NUMBER3
947 * @arg @ref LL_MPU_REGION_NUMBER4
948 * @arg @ref LL_MPU_REGION_NUMBER5
949 * @arg @ref LL_MPU_REGION_NUMBER6
950 * @arg @ref LL_MPU_REGION_NUMBER7
951 * @note cortex-M33 support 8 secure and 8 non secure regions.
952 * @retval None
953 */
LL_MPU_DisableRegion_NS(uint32_t Region)954 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
955 {
956 /* Set Region number */
957 WRITE_REG(MPU_NS->RNR, Region);
958
959 /* Disable the MPU region */
960 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
961 }
962
963 /**
964 * @brief Check if non-secure MPU region is enabled or not
965 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion_NS\n
966 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion_NS
967 * @param Region This parameter can be one of the following values:
968 * @arg @ref LL_MPU_REGION_NUMBER0
969 * @arg @ref LL_MPU_REGION_NUMBER1
970 * @arg @ref LL_MPU_REGION_NUMBER2
971 * @arg @ref LL_MPU_REGION_NUMBER3
972 * @arg @ref LL_MPU_REGION_NUMBER4
973 * @arg @ref LL_MPU_REGION_NUMBER5
974 * @arg @ref LL_MPU_REGION_NUMBER6
975 * @arg @ref LL_MPU_REGION_NUMBER7
976 * @note cortex-M33 support 8 secure and 8 non secure regions.
977 * @retval State of bit (1 or 0).
978 */
LL_MPU_IsEnabledRegion_NS(uint32_t Region)979 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
980 {
981 return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
982 }
983
984 /**
985 * @brief Configure and enable a non-secure MPU region
986 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
987 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
988 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
989 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
990 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
991 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
992 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
993 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS
994 * @param Region This parameter can be one of the following values:
995 * @arg @ref LL_MPU_REGION_NUMBER0
996 * @arg @ref LL_MPU_REGION_NUMBER1
997 * @arg @ref LL_MPU_REGION_NUMBER2
998 * @arg @ref LL_MPU_REGION_NUMBER3
999 * @arg @ref LL_MPU_REGION_NUMBER4
1000 * @arg @ref LL_MPU_REGION_NUMBER5
1001 * @arg @ref LL_MPU_REGION_NUMBER6
1002 * @arg @ref LL_MPU_REGION_NUMBER7
1003 * @param AttrIndx This parameter can be one of the following values:
1004 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1005 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1006 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1007 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1008 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1009 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1010 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1011 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1012 * @param BaseAddress Value of region base address
1013 * @param LimitAddress Value of region limit address
1014 * @param Attributes This parameter can be a combination of the following values:
1015 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1016 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1017 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
1018 * @note cortex-M33 support 8 secure and 8 non secure regions.
1019 * @retval None
1020 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)1021 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress)
1022 {
1023 /* Set Region number */
1024 WRITE_REG(MPU_NS->RNR, Region);
1025
1026 /* Set base address */
1027 MPU_NS->RBAR |= Attributes;
1028
1029 /* Set base address */
1030 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
1031
1032 /* Set limit address */
1033 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
1034 /* Configure MPU */
1035 MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx);
1036 }
1037
1038 /**
1039 * @brief Configure a non-secure MPU region address range
1040 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
1041 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1042 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1043 * @param Region This parameter can be one of the following values:
1044 * @arg @ref LL_MPU_REGION_NUMBER0
1045 * @arg @ref LL_MPU_REGION_NUMBER1
1046 * @arg @ref LL_MPU_REGION_NUMBER2
1047 * @arg @ref LL_MPU_REGION_NUMBER3
1048 * @arg @ref LL_MPU_REGION_NUMBER4
1049 * @arg @ref LL_MPU_REGION_NUMBER5
1050 * @arg @ref LL_MPU_REGION_NUMBER6
1051 * @arg @ref LL_MPU_REGION_NUMBER7
1052 * @param BaseAddress Value of region base address
1053 * @param LimitAddress Value of region limit address
1054 * @note cortex-M33 support 8 secure and 8 non secure regions.
1055 * @retval None
1056 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)1057 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
1058 {
1059 /* Set Region number */
1060 WRITE_REG(MPU_NS->RNR, Region);
1061
1062 /* Set base address */
1063 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
1064
1065 /* Set limit address */
1066 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
1067 }
1068
1069 /**
1070 * @brief Configure a non-secure MPU attributes index
1071 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes_NS\n
1072 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes_NS\n
1073 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes_NS\n
1074 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes_NS\n
1075 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes_NS\n
1076 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes_NS\n
1077 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes_NS\n
1078 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes_NS
1079 * @param AttIndex This parameter can be one of the following values:
1080 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1081 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1082 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1083 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1084 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1085 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1086 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1087 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1088 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
1089 * @retval None
1090 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)1091 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1092 {
1093 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1094 {
1095 /* Program MPU_MAIR0 */
1096 WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U)));
1097 }
1098 else
1099 {
1100 /* Program MPU_MAIR1 */
1101 WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U)));
1102 }
1103 }
1104
1105 /**
1106 * @brief Configure a non-secure MPU region base address
1107 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1108 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS
1109 * @param Region This parameter can be one of the following values:
1110 * @arg @ref LL_MPU_REGION_NUMBER0
1111 * @arg @ref LL_MPU_REGION_NUMBER1
1112 * @arg @ref LL_MPU_REGION_NUMBER2
1113 * @arg @ref LL_MPU_REGION_NUMBER3
1114 * @arg @ref LL_MPU_REGION_NUMBER4
1115 * @arg @ref LL_MPU_REGION_NUMBER5
1116 * @arg @ref LL_MPU_REGION_NUMBER6
1117 * @arg @ref LL_MPU_REGION_NUMBER7
1118 * @param BaseAddress Value of region base address
1119 * @note cortex-M33 support 8 secure and 8 non secure regions.
1120 * @retval None
1121 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1122 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1123 {
1124 /* Set Region number */
1125 WRITE_REG(MPU_NS->RNR, Region);
1126 /* Set base address */
1127 MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U);
1128 }
1129
1130 /**
1131 * @brief Get a non-secure MPU region base address
1132 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1133 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS
1134 * @param Region This parameter can be one of the following values:
1135 * @arg @ref LL_MPU_REGION_NUMBER0
1136 * @arg @ref LL_MPU_REGION_NUMBER1
1137 * @arg @ref LL_MPU_REGION_NUMBER2
1138 * @arg @ref LL_MPU_REGION_NUMBER3
1139 * @arg @ref LL_MPU_REGION_NUMBER4
1140 * @arg @ref LL_MPU_REGION_NUMBER5
1141 * @arg @ref LL_MPU_REGION_NUMBER6
1142 * @arg @ref LL_MPU_REGION_NUMBER7
1143 * @retval None
1144 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1145 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1146 {
1147 /* Set Region number */
1148 WRITE_REG(MPU_NS->RNR, Region);
1149 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1150 }
1151
1152 /**
1153 * @brief Configure a non-secure MPU region limit address
1154 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1155 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS
1156 * @param Region This parameter can be one of the following values:
1157 * @arg @ref LL_MPU_REGION_NUMBER0
1158 * @arg @ref LL_MPU_REGION_NUMBER1
1159 * @arg @ref LL_MPU_REGION_NUMBER2
1160 * @arg @ref LL_MPU_REGION_NUMBER3
1161 * @arg @ref LL_MPU_REGION_NUMBER4
1162 * @arg @ref LL_MPU_REGION_NUMBER5
1163 * @arg @ref LL_MPU_REGION_NUMBER6
1164 * @arg @ref LL_MPU_REGION_NUMBER7
1165 * @param LimitAddress Value of region limit address
1166 * @note cortex-M33 support 8 secure and 8 non secure regions.
1167 * @retval None
1168 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1169 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1170 {
1171 /* Set Region number */
1172 WRITE_REG(MPU_NS->RNR, Region);
1173 /* Set limit address */
1174 MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U);
1175 }
1176
1177 /**
1178 * @brief Get a non-secure MPU region limit address
1179 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1180 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS
1181 * @param Region This parameter can be one of the following values:
1182 * @arg @ref LL_MPU_REGION_NUMBER0
1183 * @arg @ref LL_MPU_REGION_NUMBER1
1184 * @arg @ref LL_MPU_REGION_NUMBER2
1185 * @arg @ref LL_MPU_REGION_NUMBER3
1186 * @arg @ref LL_MPU_REGION_NUMBER4
1187 * @arg @ref LL_MPU_REGION_NUMBER5
1188 * @arg @ref LL_MPU_REGION_NUMBER6
1189 * @arg @ref LL_MPU_REGION_NUMBER7
1190 * @retval None
1191 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1192 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1193 {
1194 /* Set Region number */
1195 WRITE_REG(MPU_NS->RNR, Region);
1196 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1197 }
1198
1199 /**
1200 * @brief Configure a non-secure MPU region access attributes and enable a region
1201 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1202 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1203 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1204 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS
1205 * @param Region This parameter can be one of the following values:
1206 * @arg @ref LL_MPU_REGION_NUMBER0
1207 * @arg @ref LL_MPU_REGION_NUMBER1
1208 * @arg @ref LL_MPU_REGION_NUMBER2
1209 * @arg @ref LL_MPU_REGION_NUMBER3
1210 * @arg @ref LL_MPU_REGION_NUMBER4
1211 * @arg @ref LL_MPU_REGION_NUMBER5
1212 * @arg @ref LL_MPU_REGION_NUMBER6
1213 * @arg @ref LL_MPU_REGION_NUMBER7
1214 * @param Attributes This parameter can be a combination of the following values:
1215 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1216 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1217 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO
1218 * @note cortex-M33 support 8 secure and 8 non secure regions.
1219 * @retval None
1220 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1221 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1222 {
1223 /* Set Region number */
1224 WRITE_REG(MPU_NS->RNR, Region);
1225 /* Set base address Attributes */
1226 MPU_NS->RBAR |= Attributes;
1227 }
1228
1229 /**
1230 * @brief Get a non-secure MPU region access attributes
1231 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1232 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1233 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1234 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS
1235 * @param Region This parameter can be one of the following values:
1236 * @arg @ref LL_MPU_REGION_NUMBER0
1237 * @arg @ref LL_MPU_REGION_NUMBER1
1238 * @arg @ref LL_MPU_REGION_NUMBER2
1239 * @arg @ref LL_MPU_REGION_NUMBER3
1240 * @arg @ref LL_MPU_REGION_NUMBER4
1241 * @arg @ref LL_MPU_REGION_NUMBER5
1242 * @arg @ref LL_MPU_REGION_NUMBER6
1243 * @arg @ref LL_MPU_REGION_NUMBER7
1244 * @retval None
1245 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1246 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1247 {
1248 /* Set Region number */
1249 WRITE_REG(MPU_NS->RNR, Region);
1250 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1251 }
1252 #endif /* __ARM_FEATURE_CMSE */
1253
1254 /**
1255 * @}
1256 */
1257
1258 #endif /* __MPU_PRESENT */
1259 /**
1260 * @}
1261 */
1262
1263 /**
1264 * @}
1265 */
1266
1267 /**
1268 * @}
1269 */
1270
1271 #ifdef __cplusplus
1272 }
1273 #endif
1274
1275 #endif /* STM32L5xx_LL_CORTEX_H */
1276
1277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1278
