1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_FDCAN_H 22 #define STM32L5xx_HAL_FDCAN_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 #if defined(FDCAN1) 32 33 /** @addtogroup STM32L5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup FDCAN 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 52 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 53 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 54 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 55 } HAL_FDCAN_StateTypeDef; 56 57 /** 58 * @brief FDCAN Init structure definition 59 */ 60 typedef struct 61 { 62 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider. 63 The clock is common to all FDCAN instances. 64 This parameter is applied only at initialisation of 65 first FDCAN instance. 66 This parameter can be a value of @ref FDCAN_clock_divider. */ 67 68 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 69 This parameter can be a value of @ref FDCAN_frame_format */ 70 71 uint32_t Mode; /*!< Specifies the FDCAN mode. 72 This parameter can be a value of @ref FDCAN_operating_mode */ 73 74 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 75 This parameter can be set to ENABLE or DISABLE */ 76 77 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 78 This parameter can be set to ENABLE or DISABLE */ 79 80 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 81 This parameter can be set to ENABLE or DISABLE */ 82 83 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 84 divided for generating the nominal bit time quanta. 85 This parameter must be a number between 1 and 512 */ 86 87 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 88 hardware is allowed to lengthen or shorten a bit to perform 89 resynchronization. 90 This parameter must be a number between 1 and 128 */ 91 92 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 93 This parameter must be a number between 2 and 256 */ 94 95 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 96 This parameter must be a number between 2 and 128 */ 97 98 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 99 divided for generating the data bit time quanta. 100 This parameter must be a number between 1 and 32 */ 101 102 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 103 hardware is allowed to lengthen or shorten a data bit to 104 perform resynchronization. 105 This parameter must be a number between 1 and 16 */ 106 107 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 108 This parameter must be a number between 1 and 32 */ 109 110 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 111 This parameter must be a number between 1 and 16 */ 112 113 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 114 This parameter must be a number between 0 and 28 */ 115 116 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 117 This parameter must be a number between 0 and 8 */ 118 119 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 120 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 121 122 } FDCAN_InitTypeDef; 123 124 /** 125 * @brief FDCAN filter structure definition 126 */ 127 typedef struct 128 { 129 uint32_t IdType; /*!< Specifies the identifier type. 130 This parameter can be a value of @ref FDCAN_id_type */ 131 132 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 133 This parameter must be a number between: 134 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 135 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ 136 137 uint32_t FilterType; /*!< Specifies the filter type. 138 This parameter can be a value of @ref FDCAN_filter_type. 139 The value FDCAN_FILTER_RANGE_NO_EIDM is permitted 140 only when IdType is FDCAN_EXTENDED_ID. */ 141 142 uint32_t FilterConfig; /*!< Specifies the filter configuration. 143 This parameter can be a value of @ref FDCAN_filter_config */ 144 145 uint32_t FilterID1; /*!< Specifies the filter identification 1. 146 This parameter must be a number between: 147 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 148 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 149 150 uint32_t FilterID2; /*!< Specifies the filter identification 2. 151 This parameter must be a number between: 152 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 153 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 154 155 } FDCAN_FilterTypeDef; 156 157 /** 158 * @brief FDCAN Tx header structure definition 159 */ 160 typedef struct 161 { 162 uint32_t Identifier; /*!< Specifies the identifier. 163 This parameter must be a number between: 164 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 165 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 166 167 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 168 transmitted. 169 This parameter can be a value of @ref FDCAN_id_type */ 170 171 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 172 This parameter can be a value of @ref FDCAN_frame_type */ 173 174 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 175 This parameter can be a value of @ref FDCAN_data_length_code */ 176 177 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 178 This parameter can be a value of @ref FDCAN_error_state_indicator */ 179 180 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 181 bit rate switching. 182 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 183 184 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 185 FD format. 186 This parameter can be a value of @ref FDCAN_format */ 187 188 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 189 This parameter can be a value of @ref FDCAN_EFC */ 190 191 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 192 element for identification of Tx message status. 193 This parameter must be a number between 0 and 0xFF */ 194 195 } FDCAN_TxHeaderTypeDef; 196 197 /** 198 * @brief FDCAN Rx header structure definition 199 */ 200 typedef struct 201 { 202 uint32_t Identifier; /*!< Specifies the identifier. 203 This parameter must be a number between: 204 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 205 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 206 207 uint32_t IdType; /*!< Specifies the identifier type of the received message. 208 This parameter can be a value of @ref FDCAN_id_type */ 209 210 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 211 This parameter can be a value of @ref FDCAN_frame_type */ 212 213 uint32_t DataLength; /*!< Specifies the received frame length. 214 This parameter can be a value of @ref FDCAN_data_length_code */ 215 216 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 217 This parameter can be a value of @ref FDCAN_error_state_indicator */ 218 219 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 220 rate switching. 221 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 222 223 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 224 format. 225 This parameter can be a value of @ref FDCAN_format */ 226 227 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 228 reception. 229 This parameter must be a number between 0 and 0xFFFF */ 230 231 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 232 This parameter must be a number between: 233 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 234 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ 235 236 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 237 Acceptance of non-matching frames may be enabled via 238 HAL_FDCAN_ConfigGlobalFilter(). 239 This parameter can be 0 or 1 */ 240 241 } FDCAN_RxHeaderTypeDef; 242 243 /** 244 * @brief FDCAN Tx event FIFO structure definition 245 */ 246 typedef struct 247 { 248 uint32_t Identifier; /*!< Specifies the identifier. 249 This parameter must be a number between: 250 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 251 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 252 253 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 254 This parameter can be a value of @ref FDCAN_id_type */ 255 256 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 257 This parameter can be a value of @ref FDCAN_frame_type */ 258 259 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 260 This parameter can be a value of @ref FDCAN_data_length_code */ 261 262 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 263 This parameter can be a value of @ref FDCAN_error_state_indicator */ 264 265 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 266 rate switching. 267 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 268 269 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 270 format. 271 This parameter can be a value of @ref FDCAN_format */ 272 273 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 274 transmission. 275 This parameter must be a number between 0 and 0xFFFF */ 276 277 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 278 for identification of Tx message status. 279 This parameter must be a number between 0 and 0xFF */ 280 281 uint32_t EventType; /*!< Specifies the event type. 282 This parameter can be a value of @ref FDCAN_event_type */ 283 284 } FDCAN_TxEventFifoTypeDef; 285 286 /** 287 * @brief FDCAN High Priority Message Status structure definition 288 */ 289 typedef struct 290 { 291 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 292 This parameter can be: 293 - 0 : Standard Filter List 294 - 1 : Extended Filter List */ 295 296 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 297 This parameter can be a number between: 298 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard) 299 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */ 300 301 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 302 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 303 304 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 305 message was stored. 306 This parameter is valid only when MessageStorage is: 307 FDCAN_HP_STORAGE_RXFIFO0 308 or 309 FDCAN_HP_STORAGE_RXFIFO1 */ 310 311 } FDCAN_HpMsgStatusTypeDef; 312 313 /** 314 * @brief FDCAN Protocol Status structure definition 315 */ 316 typedef struct 317 { 318 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 319 This parameter can be a value of @ref FDCAN_protocol_error_code */ 320 321 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase 322 of a CAN FD format frame with its BRS flag set. 323 This parameter can be a value of @ref FDCAN_protocol_error_code */ 324 325 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 326 This parameter can be a value of @ref FDCAN_communication_state */ 327 328 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 329 This parameter can be: 330 - 0 : The FDCAN is in Error_Active state 331 - 1 : The FDCAN is in Error_Passive state */ 332 333 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 334 This parameter can be: 335 - 0 : error counters (RxErrorCnt and TxErrorCnt) 336 are below the Error_Warning limit of 96 337 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 338 339 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 340 This parameter can be: 341 - 0 : The FDCAN is not in Bus_Off state 342 - 1 : The FDCAN is in Bus_Off state */ 343 344 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 345 This parameter can be: 346 - 0 : Last received CAN FD message did not have its ESI flag set 347 - 1 : Last received CAN FD message had its ESI flag set */ 348 349 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 350 This parameter can be: 351 - 0 : Last received CAN FD message did not have its BRS flag set 352 - 1 : Last received CAN FD message had its BRS flag set */ 353 354 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received 355 since last protocol status.This parameter can be: 356 - 0 : No CAN FD message received 357 - 1 : CAN FD message received */ 358 359 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 360 This parameter can be: 361 - 0 : No protocol exception event occurred since last read access 362 - 1 : Protocol exception event occurred */ 363 364 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 365 This parameter can be a number between 0 and 127 */ 366 367 } FDCAN_ProtocolStatusTypeDef; 368 369 /** 370 * @brief FDCAN Error Counters structure definition 371 */ 372 typedef struct 373 { 374 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 375 This parameter can be a number between 0 and 255 */ 376 377 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 378 This parameter can be a number between 0 and 127 */ 379 380 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 381 This parameter can be: 382 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 383 - 1 : The Receive Error Counter (RxErrorCnt) 384 has reached the error passive level of 128 */ 385 386 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 387 This parameter can be a number between 0 and 255. 388 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 389 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 390 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 391 392 } FDCAN_ErrorCountersTypeDef; 393 394 /** 395 * @brief FDCAN Message RAM blocks 396 */ 397 typedef struct 398 { 399 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 400 This parameter must be a 32-bit word address */ 401 402 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 403 This parameter must be a 32-bit word address */ 404 405 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 406 This parameter must be a 32-bit word address */ 407 408 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 409 This parameter must be a 32-bit word address */ 410 411 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 412 This parameter must be a 32-bit word address */ 413 414 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 415 This parameter must be a 32-bit word address */ 416 417 } FDCAN_MsgRamAddressTypeDef; 418 419 /** 420 * @brief FDCAN handle structure definition 421 */ 422 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 423 typedef struct __FDCAN_HandleTypeDef 424 #else 425 typedef struct 426 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 427 { 428 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 429 430 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 431 432 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 433 434 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 435 of latest Tx FIFO/Queue request */ 436 437 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 438 439 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 440 441 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 442 443 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 444 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ 445 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ 446 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ 447 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ 448 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ 449 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ 450 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ 451 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ 452 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ 453 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ 454 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ 455 456 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ 457 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ 458 459 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 460 461 } FDCAN_HandleTypeDef; 462 463 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 464 /** 465 * @brief HAL FDCAN common Callback ID enumeration definition 466 */ 467 typedef enum 468 { 469 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ 470 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */ 471 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */ 472 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */ 473 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */ 474 475 HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */ 476 HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */ 477 478 } HAL_FDCAN_CallbackIDTypeDef; 479 480 /** 481 * @brief HAL FDCAN Callback pointer definition 482 */ 483 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ 484 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ 485 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ 486 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ 487 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ 488 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ 489 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ 490 491 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 492 493 /** 494 * @} 495 */ 496 497 /* Exported constants --------------------------------------------------------*/ 498 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 499 * @{ 500 */ 501 502 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 503 * @{ 504 */ 505 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 506 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 507 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 508 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 509 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 510 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 511 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 512 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 513 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 514 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 515 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 516 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 517 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 518 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 519 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 520 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 521 522 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 523 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ 524 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup FDCAN_frame_format FDCAN Frame Format 530 * @{ 531 */ 532 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 533 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 534 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 540 * @{ 541 */ 542 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 543 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 544 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 545 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 546 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 552 * @{ 553 */ 554 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 555 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ 556 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ 557 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ 558 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ 559 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ 560 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ 561 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ 562 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ 563 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ 564 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ 565 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ 566 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ 567 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ 568 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ 569 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 575 * @{ 576 */ 577 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 578 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup FDCAN_id_type FDCAN ID Type 584 * @{ 585 */ 586 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 587 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup FDCAN_frame_type FDCAN Frame Type 593 * @{ 594 */ 595 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 596 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 597 /** 598 * @} 599 */ 600 601 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 602 * @{ 603 */ 604 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 605 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 606 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 607 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 608 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 609 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 610 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 611 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 612 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 613 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 614 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 615 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 616 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 617 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 618 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 619 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 625 * @{ 626 */ 627 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 628 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 634 * @{ 635 */ 636 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 637 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup FDCAN_format FDCAN format 643 * @{ 644 */ 645 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 646 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 652 * @{ 653 */ 654 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 655 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup FDCAN_filter_type FDCAN Filter Type 661 * @{ 662 */ 663 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 664 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 665 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 666 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 667 /** 668 * @} 669 */ 670 671 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 672 * @{ 673 */ 674 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 675 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 676 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 677 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 678 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 679 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 680 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 686 * @{ 687 */ 688 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 689 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 690 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 691 /** 692 * @} 693 */ 694 695 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 696 * @{ 697 */ 698 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 699 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 700 /** 701 * @} 702 */ 703 704 /** @defgroup FDCAN_event_type FDCAN Event Type 705 * @{ 706 */ 707 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 708 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 709 /** 710 * @} 711 */ 712 713 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 714 * @{ 715 */ 716 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 717 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 718 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 719 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 720 /** 721 * @} 722 */ 723 724 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 725 * @{ 726 */ 727 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 728 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 729 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 730 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 731 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 732 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 733 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 734 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup FDCAN_communication_state FDCAN communication state 740 * @{ 741 */ 742 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 743 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 744 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 745 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 746 /** 747 * @} 748 */ 749 750 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 751 * @{ 752 */ 753 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 754 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ 755 /** 756 * @} 757 */ 758 759 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 760 * @{ 761 */ 762 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 763 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 764 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 765 /** 766 * @} 767 */ 768 769 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 770 * @{ 771 */ 772 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 773 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 779 * @{ 780 */ 781 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 782 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 783 /** 784 * @} 785 */ 786 787 /** @defgroup FDCAN_Timestamp FDCAN timestamp 788 * @{ 789 */ 790 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 791 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 792 /** 793 * @} 794 */ 795 796 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 797 * @{ 798 */ 799 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 800 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ 801 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ 802 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ 803 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ 804 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ 805 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ 806 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ 807 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ 808 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ 809 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ 810 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ 811 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ 812 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ 813 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ 814 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ 815 /** 816 * @} 817 */ 818 819 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 820 * @{ 821 */ 822 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 823 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 824 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 825 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 826 /** 827 * @} 828 */ 829 830 /** @defgroup Interrupt_Masks Interrupt masks 831 * @{ 832 */ 833 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */ 834 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */ 835 /** 836 * @} 837 */ 838 839 /** @defgroup FDCAN_flags FDCAN Flags 840 * @{ 841 */ 842 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 843 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 844 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 845 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 846 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 847 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 848 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 849 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 850 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 851 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 852 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 853 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 854 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 855 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 856 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 857 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 858 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 859 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 860 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 861 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 862 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 863 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 864 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 865 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 866 /** 867 * @} 868 */ 869 870 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 871 * @{ 872 */ 873 874 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 875 * @{ 876 */ 877 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 878 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 879 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 880 /** 881 * @} 882 */ 883 884 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 885 * @{ 886 */ 887 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 888 /** 889 * @} 890 */ 891 892 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 893 * @{ 894 */ 895 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 896 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 897 /** 898 * @} 899 */ 900 901 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 902 * @{ 903 */ 904 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 905 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 906 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 907 /** 908 * @} 909 */ 910 911 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 912 * @{ 913 */ 914 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 915 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 916 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 917 /** 918 * @} 919 */ 920 921 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 922 * @{ 923 */ 924 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 925 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 926 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 927 /** 928 * @} 929 */ 930 931 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 932 * @{ 933 */ 934 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 935 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 936 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 937 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 938 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 939 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 940 /** 941 * @} 942 */ 943 944 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 945 * @{ 946 */ 947 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 948 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 949 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 950 /** 951 * @} 952 */ 953 954 /** 955 * @} 956 */ 957 958 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List 959 * @{ 960 */ 961 #define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \ 962 FDCAN_IT_RX_FIFO0_FULL | \ 963 FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */ 964 #define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \ 965 FDCAN_IT_RX_FIFO1_FULL | \ 966 FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */ 967 #define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \ 968 FDCAN_IT_TX_COMPLETE | \ 969 FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */ 970 #define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \ 971 FDCAN_IT_TX_EVT_FIFO_FULL | \ 972 FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \ 973 FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */ 974 #define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \ 975 FDCAN_IT_RAM_ACCESS_FAILURE | \ 976 FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */ 977 #define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \ 978 FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */ 979 #define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \ 980 FDCAN_IT_DATA_PROTOCOL_ERROR | \ 981 FDCAN_IT_ARB_PROTOCOL_ERROR | \ 982 FDCAN_IT_RAM_WATCHDOG | \ 983 FDCAN_IT_BUS_OFF | \ 984 FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */ 985 /** 986 * @} 987 */ 988 989 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group 990 * @{ 991 */ 992 #define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: 993 RF0LL: Rx FIFO 0 Message Lost 994 RF0FL: Rx FIFO 0 is Full 995 RF0NL: Rx FIFO 0 Has New Message */ 996 #define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: 997 RF1LL: Rx FIFO 1 Message Lost 998 RF1FL: Rx FIFO 1 is Full 999 RF1NL: Rx FIFO 1 Has New Message */ 1000 #define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: 1001 TCFL: Transmission Cancellation Finished 1002 TCL: Transmission Completed 1003 HPML: High Priority Message */ 1004 #define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: 1005 TEFLL: Tx Event FIFO Element Lost 1006 TEFFL: Tx Event FIFO Full 1007 TEFNL: Tx Event FIFO New Entry 1008 TFEL: Tx FIFO Empty Interrupt Line */ 1009 #define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group: 1010 TOOL: Timeout Occurred 1011 MRAFL: Message RAM Access Failure 1012 TSWL: Timestamp Wraparound */ 1013 #define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: 1014 EPL: Error Passive 1015 ELOL: Error Logging Overflow */ 1016 #define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group: 1017 ARAL: Access to Reserved Address Line 1018 PEDL: Protocol Error in Data Phase Line 1019 PEAL: Protocol Error in Arbitration Phase Line 1020 WDIL: Watchdog Interrupt Line 1021 BOL: Bus_Off Status 1022 EWL: Warning Status */ 1023 /** 1024 * @} 1025 */ 1026 1027 /** 1028 * @} 1029 */ 1030 1031 /* Exported macro ------------------------------------------------------------*/ 1032 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1033 * @{ 1034 */ 1035 1036 /** @brief Reset FDCAN handle state. 1037 * @param __HANDLE__ FDCAN handle. 1038 * @retval None 1039 */ 1040 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1041 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1042 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ 1043 (__HANDLE__)->MspInitCallback = NULL; \ 1044 (__HANDLE__)->MspDeInitCallback = NULL; \ 1045 } while(0) 1046 #else 1047 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1048 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1049 1050 /** 1051 * @brief Enable the specified FDCAN interrupts. 1052 * @param __HANDLE__ FDCAN handle. 1053 * @param __INTERRUPT__ FDCAN interrupt. 1054 * This parameter can be any combination of @arg FDCAN_Interrupts 1055 * @retval None 1056 */ 1057 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1058 (__HANDLE__)->Instance->IE |= (__INTERRUPT__) 1059 1060 /** 1061 * @brief Disable the specified FDCAN interrupts. 1062 * @param __HANDLE__ FDCAN handle. 1063 * @param __INTERRUPT__ FDCAN interrupt. 1064 * This parameter can be any combination of @arg FDCAN_Interrupts 1065 * @retval None 1066 */ 1067 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1068 ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__) 1069 1070 /** 1071 * @brief Check whether the specified FDCAN interrupt is set or not. 1072 * @param __HANDLE__ FDCAN handle. 1073 * @param __INTERRUPT__ FDCAN interrupt. 1074 * This parameter can be one of @arg FDCAN_Interrupts 1075 * @retval ITStatus 1076 */ 1077 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) 1078 1079 /** 1080 * @brief Clear the specified FDCAN interrupts. 1081 * @param __HANDLE__ FDCAN handle. 1082 * @param __INTERRUPT__ specifies the interrupts to clear. 1083 * This parameter can be any combination of @arg FDCAN_Interrupts 1084 * @retval None 1085 */ 1086 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1087 ((__HANDLE__)->Instance->IR) = (__INTERRUPT__) 1088 1089 /** 1090 * @brief Check whether the specified FDCAN flag is set or not. 1091 * @param __HANDLE__ FDCAN handle. 1092 * @param __FLAG__ FDCAN flag. 1093 * This parameter can be one of @arg FDCAN_flags 1094 * @retval FlagStatus 1095 */ 1096 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) 1097 1098 /** 1099 * @brief Clear the specified FDCAN flags. 1100 * @param __HANDLE__ FDCAN handle. 1101 * @param __FLAG__ specifies the flags to clear. 1102 * This parameter can be any combination of @arg FDCAN_flags 1103 * @retval None 1104 */ 1105 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1106 ((__HANDLE__)->Instance->IR) = (__FLAG__) 1107 1108 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1109 * @param __HANDLE__ FDCAN handle. 1110 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1111 * This parameter can be a value of @arg FDCAN_Interrupts 1112 * @retval ITStatus 1113 */ 1114 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) 1115 1116 /** 1117 * @} 1118 */ 1119 1120 /* Exported functions --------------------------------------------------------*/ 1121 /** @addtogroup FDCAN_Exported_Functions 1122 * @{ 1123 */ 1124 1125 /** @addtogroup FDCAN_Exported_Functions_Group1 1126 * @{ 1127 */ 1128 /* Initialization and de-initialization functions *****************************/ 1129 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1130 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1131 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1132 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1133 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1134 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1135 1136 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1137 /* Callbacks Register/UnRegister functions ***********************************/ 1138 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, 1139 pFDCAN_CallbackTypeDef pCallback); 1140 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); 1141 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, 1142 pFDCAN_TxEventFifoCallbackTypeDef pCallback); 1143 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); 1144 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, 1145 pFDCAN_RxFifo0CallbackTypeDef pCallback); 1146 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); 1147 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, 1148 pFDCAN_RxFifo1CallbackTypeDef pCallback); 1149 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); 1150 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, 1151 pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); 1152 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); 1153 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, 1154 pFDCAN_TxBufferAbortCallbackTypeDef pCallback); 1155 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); 1156 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, 1157 pFDCAN_ErrorStatusCallbackTypeDef pCallback); 1158 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); 1159 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1160 /** 1161 * @} 1162 */ 1163 1164 /** @addtogroup FDCAN_Exported_Functions_Group2 1165 * @{ 1166 */ 1167 /* Configuration functions ****************************************************/ 1168 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 1169 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, 1170 uint32_t NonMatchingExt, uint32_t RejectRemoteStd, 1171 uint32_t RejectRemoteExt); 1172 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1173 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1174 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1175 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1176 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 1177 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1178 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1179 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1180 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, 1181 uint32_t TimeoutPeriod); 1182 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1183 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1184 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1185 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1186 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, 1187 uint32_t TdcFilter); 1188 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1189 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1190 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 1191 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 1192 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1193 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1194 /** 1195 * @} 1196 */ 1197 1198 /** @addtogroup FDCAN_Exported_Functions_Group3 1199 * @{ 1200 */ 1201 /* Control functions **********************************************************/ 1202 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 1203 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 1204 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, 1205 uint8_t *pTxData); 1206 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 1207 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1208 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, 1209 FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 1210 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 1211 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, 1212 FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 1213 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 1214 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 1215 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 1216 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 1217 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 1218 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1219 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1220 /** 1221 * @} 1222 */ 1223 1224 /** @addtogroup FDCAN_Exported_Functions_Group4 1225 * @{ 1226 */ 1227 /* Interrupts management ******************************************************/ 1228 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 1229 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, 1230 uint32_t BufferIndexes); 1231 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 1232 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 1233 /** 1234 * @} 1235 */ 1236 1237 /** @addtogroup FDCAN_Exported_Functions_Group5 1238 * @{ 1239 */ 1240 /* Callback functions *********************************************************/ 1241 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 1242 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 1243 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 1244 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 1245 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1246 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1247 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 1248 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 1249 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 1250 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 1251 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 1252 /** 1253 * @} 1254 */ 1255 1256 /** @addtogroup FDCAN_Exported_Functions_Group6 1257 * @{ 1258 */ 1259 /* Peripheral State functions *************************************************/ 1260 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 1261 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 1262 /** 1263 * @} 1264 */ 1265 1266 /** 1267 * @} 1268 */ 1269 1270 /* Private types -------------------------------------------------------------*/ 1271 /** @defgroup FDCAN_Private_Types FDCAN Private Types 1272 * @{ 1273 */ 1274 1275 /** 1276 * @} 1277 */ 1278 1279 /* Private variables ---------------------------------------------------------*/ 1280 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 1281 * @{ 1282 */ 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /* Private constants ---------------------------------------------------------*/ 1289 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 1290 * @{ 1291 */ 1292 1293 /** 1294 * @} 1295 */ 1296 1297 /* Private macros ------------------------------------------------------------*/ 1298 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 1299 * @{ 1300 */ 1301 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 1302 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 1303 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 1304 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 1305 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 1306 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 1307 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 1308 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 1309 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 1310 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 1311 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 1312 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 1313 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 1314 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 1315 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 1316 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 1317 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 1318 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 1319 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 1320 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 1321 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 1322 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 1323 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 1324 ((CKDIV) == FDCAN_CLOCK_DIV30)) 1325 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 1326 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 1327 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 1328 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 1329 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 1330 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 1331 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 1332 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 1333 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) 1334 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) 1335 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 1336 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 1337 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 1338 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 1339 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 1340 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 1341 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 1342 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 1343 ((CONFIG) == FDCAN_FILTER_HP ) || \ 1344 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 1345 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP)) 1346 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 1347 ((LOCATION) == FDCAN_TX_BUFFER2 )) 1348 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \ 1349 ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2))) 1350 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 1351 ((FIFO) == FDCAN_RX_FIFO1)) 1352 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 1353 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 1354 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 1355 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1356 ((TYPE) == FDCAN_FILTER_MASK )) 1357 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 1358 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1359 ((TYPE) == FDCAN_FILTER_MASK ) || \ 1360 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 1361 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 1362 ((TYPE) == FDCAN_REMOTE_FRAME)) 1363 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 1364 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 1365 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 1366 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 1367 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 1368 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 1369 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 1370 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 1371 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 1372 ((DLC) == FDCAN_DLC_BYTES_12) || \ 1373 ((DLC) == FDCAN_DLC_BYTES_16) || \ 1374 ((DLC) == FDCAN_DLC_BYTES_20) || \ 1375 ((DLC) == FDCAN_DLC_BYTES_24) || \ 1376 ((DLC) == FDCAN_DLC_BYTES_32) || \ 1377 ((DLC) == FDCAN_DLC_BYTES_48) || \ 1378 ((DLC) == FDCAN_DLC_BYTES_64)) 1379 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 1380 ((ESI) == FDCAN_ESI_PASSIVE)) 1381 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 1382 ((BRS) == FDCAN_BRS_ON )) 1383 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 1384 ((FDF) == FDCAN_FD_CAN )) 1385 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 1386 ((EFC) == FDCAN_STORE_TX_EVENTS)) 1387 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) 1388 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U) 1389 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 1390 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 1391 ((DESTINATION) == FDCAN_REJECT )) 1392 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 1393 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 1394 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 1395 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 1396 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 1397 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 1398 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 1399 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 1400 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 1401 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 1402 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 1403 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 1404 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 1405 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 1406 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 1407 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 1408 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 1409 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 1410 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 1411 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 1412 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 1413 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 1414 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 1415 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 1416 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 1417 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 1418 /** 1419 * @} 1420 */ 1421 1422 /* Private functions prototypes ----------------------------------------------*/ 1423 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes 1424 * @{ 1425 */ 1426 1427 /** 1428 * @} 1429 */ 1430 1431 /* Private functions ---------------------------------------------------------*/ 1432 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions 1433 * @{ 1434 */ 1435 1436 /** 1437 * @} 1438 */ 1439 /** 1440 * @} 1441 */ 1442 1443 /** 1444 * @} 1445 */ 1446 #endif /* FDCAN1 */ 1447 1448 #ifdef __cplusplus 1449 } 1450 #endif 1451 1452 #endif /* STM32L5xx_HAL_FDCAN_H */ 1453 1454 1455 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1456
