1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.</center></h2>
16 *
17 * This software component is licensed by ST under BSD 3-Clause license,
18 * the "License"; You may not use this file except in compliance with the
19 * License. You may obtain a copy of the License at:
20 * opensource.org/licenses/BSD-3-Clause
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32l4xx_hal.h"
27
28 /** @addtogroup STM32L4xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup PWR PWR
33 * @brief PWR HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_PWR_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private define ------------------------------------------------------------*/
41
42 /** @defgroup PWR_Private_Defines PWR Private Defines
43 * @{
44 */
45
46 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
47 * @{
48 */
49 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
50 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
51 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
52 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
53 /**
54 * @}
55 */
56
57 /**
58 * @}
59 */
60
61 /* Private macro -------------------------------------------------------------*/
62 /* Private variables ---------------------------------------------------------*/
63 /* Private function prototypes -----------------------------------------------*/
64 /* Exported functions --------------------------------------------------------*/
65
66 /** @defgroup PWR_Exported_Functions PWR Exported Functions
67 * @{
68 */
69
70 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
71 * @brief Initialization and de-initialization functions
72 *
73 @verbatim
74 ===============================================================================
75 ##### Initialization and de-initialization functions #####
76 ===============================================================================
77 [..]
78
79 @endverbatim
80 * @{
81 */
82
83 /**
84 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
85 * @retval None
86 */
HAL_PWR_DeInit(void)87 void HAL_PWR_DeInit(void)
88 {
89 __HAL_RCC_PWR_FORCE_RESET();
90 __HAL_RCC_PWR_RELEASE_RESET();
91 }
92
93 /**
94 * @brief Enable access to the backup domain
95 * (RTC registers, RTC backup data registers).
96 * @note After reset, the backup domain is protected against
97 * possible unwanted write accesses.
98 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
99 * In order to set or modify the RTC clock, the backup domain access must be
100 * disabled.
101 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
102 * back-up domain.
103 * @retval None
104 */
HAL_PWR_EnableBkUpAccess(void)105 void HAL_PWR_EnableBkUpAccess(void)
106 {
107 SET_BIT(PWR->CR1, PWR_CR1_DBP);
108 }
109
110 /**
111 * @brief Disable access to the backup domain
112 * (RTC registers, RTC backup data registers).
113 * @retval None
114 */
HAL_PWR_DisableBkUpAccess(void)115 void HAL_PWR_DisableBkUpAccess(void)
116 {
117 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
118 }
119
120
121
122
123 /**
124 * @}
125 */
126
127
128
129 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
130 * @brief Low Power modes configuration functions
131 *
132 @verbatim
133
134 ===============================================================================
135 ##### Peripheral Control functions #####
136 ===============================================================================
137
138 [..]
139 *** PVD configuration ***
140 =========================
141 [..]
142 (+) The PVD is used to monitor the VDD power supply by comparing it to a
143 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
144
145 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
146 than the PVD threshold. This event is internally connected to the EXTI
147 line16 and can generate an interrupt if enabled. This is done through
148 __HAL_PVD_EXTI_ENABLE_IT() macro.
149 (+) The PVD is stopped in Standby mode.
150
151
152 *** WakeUp pin configuration ***
153 ================================
154 [..]
155 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
156 The polarity of these pins can be set to configure event detection on high
157 level (rising edge) or low level (falling edge).
158
159
160
161 *** Low Power modes configuration ***
162 =====================================
163 [..]
164 The devices feature 8 low-power modes:
165 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
166 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
167 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
168 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
169 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
170 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
171 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
172 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
173 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
174
175
176 *** Low-power run mode ***
177 ==========================
178 [..]
179 (+) Entry: (from main run mode)
180 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
181
182 (+) Exit:
183 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
184 then can the system clock frequency be increased above 2 MHz.
185
186
187 *** Sleep mode / Low-power sleep mode ***
188 =========================================
189 [..]
190 (+) Entry:
191 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
192 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
193 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
194 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
195 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
196 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
197 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
198
199 (+) WFI Exit:
200 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
201 controller (NVIC) or any wake-up event.
202
203 (+) WFE Exit:
204 (++) Any wake-up event such as an EXTI line configured in event mode.
205
206 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
207 the MCU is in Low-power Run mode.
208
209 *** Stop 0, Stop 1 and Stop 2 modes ***
210 ===============================
211 [..]
212 (+) Entry:
213 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
214 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
215 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
216 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
217 (++) PWR_MAINREGULATOR_ON
218 (++) PWR_LOWPOWERREGULATOR_ON
219 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
220 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
221 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
222
223 (+) WFI Exit:
224 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
225 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
226 when programmed in wakeup mode.
227 (+) WFE Exit:
228 (++) Any EXTI Line (Internal or External) configured in Event mode.
229
230 [..]
231 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
232 depending on the LPR bit setting.
233 When exiting Stop 2 mode, the MCU is in Run mode.
234
235 *** Standby mode ***
236 ====================
237 [..]
238 The Standby mode offers two options:
239 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
240 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
241 and Standby circuitry.
242 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
243 SRAM and register contents are lost except for the RTC registers, RTC backup registers
244 and Standby circuitry.
245
246 (++) Entry:
247 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
248 SRAM1 and register contents are lost except for registers in the Backup domain and
249 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
250 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
251 to set RRS bit.
252
253 (++) Exit:
254 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
255 external reset in NRST pin, IWDG reset.
256
257 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
258
259
260 *** Shutdown mode ***
261 ======================
262 [..]
263 In Shutdown mode,
264 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
265 SRAM and registers contents are lost except for backup domain registers.
266
267 (+) Entry:
268 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
269
270 (+) Exit:
271 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
272 external reset in NRST pin.
273
274 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
275
276
277 *** Auto-wakeup (AWU) from low-power mode ***
278 =============================================
279 [..]
280 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
281 Wakeup event, a tamper event or a time-stamp event, without depending on
282 an external interrupt (Auto-wakeup mode).
283
284 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
285
286
287 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
288 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
289
290 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
291 is necessary to configure the RTC to detect the tamper or time stamp event using the
292 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
293
294 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
295 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
296
297 @endverbatim
298 * @{
299 */
300
301
302
303 /**
304 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
305 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
306 * configuration information.
307 * @note Refer to the electrical characteristics of your device datasheet for
308 * more details about the voltage thresholds corresponding to each
309 * detection level.
310 * @retval None
311 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)312 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
313 {
314 /* Check the parameters */
315 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
316 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
317
318 /* Set PLS bits according to PVDLevel value */
319 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
320
321 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
322 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
323 __HAL_PWR_PVD_EXTI_DISABLE_IT();
324 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
325 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
326
327 /* Configure interrupt mode */
328 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
329 {
330 __HAL_PWR_PVD_EXTI_ENABLE_IT();
331 }
332
333 /* Configure event mode */
334 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
335 {
336 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
337 }
338
339 /* Configure the edge */
340 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
341 {
342 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
343 }
344
345 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
346 {
347 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
348 }
349
350 return HAL_OK;
351 }
352
353
354 /**
355 * @brief Enable the Power Voltage Detector (PVD).
356 * @retval None
357 */
HAL_PWR_EnablePVD(void)358 void HAL_PWR_EnablePVD(void)
359 {
360 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
361 }
362
363 /**
364 * @brief Disable the Power Voltage Detector (PVD).
365 * @retval None
366 */
HAL_PWR_DisablePVD(void)367 void HAL_PWR_DisablePVD(void)
368 {
369 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
370 }
371
372
373
374
375 /**
376 * @brief Enable the WakeUp PINx functionality.
377 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
378 * This parameter can be one of the following legacy values which set the default polarity
379 * i.e. detection on high level (rising edge):
380 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
381 *
382 * or one of the following value where the user can explicitly specify the enabled pin and
383 * the chosen polarity:
384 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
385 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
386 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
387 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
388 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
389 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
390 * @retval None
391 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)392 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
393 {
394 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
395
396 /* Specifies the Wake-Up pin polarity for the event detection
397 (rising or falling edge) */
398 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
399
400 /* Enable wake-up pin */
401 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
402
403
404 }
405
406 /**
407 * @brief Disable the WakeUp PINx functionality.
408 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
409 * This parameter can be one of the following values:
410 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
411 * @retval None
412 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)413 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
414 {
415 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
416
417 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
418 }
419
420
421 /**
422 * @brief Enter Sleep or Low-power Sleep mode.
423 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
424 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
425 * This parameter can be one of the following values:
426 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
427 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
428 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
429 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
430 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
431 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
432 * Additionally, the clock frequency must be reduced below 2 MHz.
433 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
434 * be done before calling HAL_PWR_EnterSLEEPMode() API.
435 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
436 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
437 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
438 * This parameter can be one of the following values:
439 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
440 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
441 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
442 * the interrupt wake up source.
443 * @retval None
444 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)445 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
446 {
447 /* Check the parameters */
448 assert_param(IS_PWR_REGULATOR(Regulator));
449 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
450
451 /* Set Regulator parameter */
452 if (Regulator == PWR_MAINREGULATOR_ON)
453 {
454 /* If in low-power run mode at this point, exit it */
455 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
456 {
457 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
458 {
459 return ;
460 }
461 }
462 /* Regulator now in main mode. */
463 }
464 else
465 {
466 /* If in run mode, first move to low-power run mode.
467 The system clock frequency must be below 2 MHz at this point. */
468 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
469 {
470 HAL_PWREx_EnableLowPowerRunMode();
471 }
472 }
473
474 /* Clear SLEEPDEEP bit of Cortex System Control Register */
475 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
476
477 /* Select SLEEP mode entry -------------------------------------------------*/
478 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
479 {
480 /* Request Wait For Interrupt */
481 __WFI();
482 }
483 else
484 {
485 /* Request Wait For Event */
486 __SEV();
487 __WFE();
488 __WFE();
489 }
490
491 }
492
493
494 /**
495 * @brief Enter Stop mode
496 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
497 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
498 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
499 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
500 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
501 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
502 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
503 * only to the peripheral requesting it.
504 * SRAM1, SRAM2 and register contents are preserved.
505 * The BOR is available.
506 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
507 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
508 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
509 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
510 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
511 * startup delay is incurred when waking up.
512 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
513 * is higher although the startup time is reduced.
514 * @param Regulator: Specifies the regulator state in Stop mode.
515 * This parameter can be one of the following values:
516 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
517 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
518 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
519 * This parameter can be one of the following values:
520 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
521 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
522 * @retval None
523 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)524 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
525 {
526 /* Check the parameters */
527 assert_param(IS_PWR_REGULATOR(Regulator));
528
529 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
530 {
531 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
532 }
533 else
534 {
535 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
536 }
537 }
538
539 /**
540 * @brief Enter Standby mode.
541 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
542 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
543 * in which case the regulator is in low-power mode.
544 * SRAM1 and register contents are lost except for registers in the Backup domain and
545 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
546 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
547 * to set RRS bit.
548 * The BOR is available.
549 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
550 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
551 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
552 * same.
553 * These states are effective in Standby mode only if APC bit is set through
554 * HAL_PWREx_EnablePullUpPullDownConfig() API.
555 * @retval None
556 */
HAL_PWR_EnterSTANDBYMode(void)557 void HAL_PWR_EnterSTANDBYMode(void)
558 {
559 /* Set Stand-by mode */
560 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
561
562 /* Set SLEEPDEEP bit of Cortex System Control Register */
563 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
564
565 /* This option is used to ensure that store operations are completed */
566 #if defined ( __CC_ARM)
567 __force_stores();
568 #endif
569 /* Request Wait For Interrupt */
570 __WFI();
571 }
572
573
574
575 /**
576 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
577 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
578 * re-enters SLEEP mode when an interruption handling is over.
579 * Setting this bit is useful when the processor is expected to run only on
580 * interruptions handling.
581 * @retval None
582 */
HAL_PWR_EnableSleepOnExit(void)583 void HAL_PWR_EnableSleepOnExit(void)
584 {
585 /* Set SLEEPONEXIT bit of Cortex System Control Register */
586 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
587 }
588
589
590 /**
591 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
592 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
593 * re-enters SLEEP mode when an interruption handling is over.
594 * @retval None
595 */
HAL_PWR_DisableSleepOnExit(void)596 void HAL_PWR_DisableSleepOnExit(void)
597 {
598 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
599 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
600 }
601
602
603
604 /**
605 * @brief Enable CORTEX M4 SEVONPEND bit.
606 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
607 * WFE to wake up when an interrupt moves from inactive to pended.
608 * @retval None
609 */
HAL_PWR_EnableSEVOnPend(void)610 void HAL_PWR_EnableSEVOnPend(void)
611 {
612 /* Set SEVONPEND bit of Cortex System Control Register */
613 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
614 }
615
616
617 /**
618 * @brief Disable CORTEX M4 SEVONPEND bit.
619 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
620 * WFE to wake up when an interrupt moves from inactive to pended.
621 * @retval None
622 */
HAL_PWR_DisableSEVOnPend(void)623 void HAL_PWR_DisableSEVOnPend(void)
624 {
625 /* Clear SEVONPEND bit of Cortex System Control Register */
626 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
627 }
628
629
630
631
632
633 /**
634 * @brief PWR PVD interrupt callback
635 * @retval None
636 */
HAL_PWR_PVDCallback(void)637 __weak void HAL_PWR_PVDCallback(void)
638 {
639 /* NOTE : This function should not be modified; when the callback is needed,
640 the HAL_PWR_PVDCallback can be implemented in the user file
641 */
642 }
643
644 /**
645 * @}
646 */
647
648 /**
649 * @}
650 */
651
652 #endif /* HAL_PWR_MODULE_ENABLED */
653 /**
654 * @}
655 */
656
657 /**
658 * @}
659 */
660
661 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
662
