1 /** 2 ****************************************************************************** 3 * @file stm32l152xd.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32L1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral�s registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 /** @addtogroup CMSIS 29 * @{ 30 */ 31 32 /** @addtogroup stm32l152xd 33 * @{ 34 */ 35 36 #ifndef __STM32L152xD_H 37 #define __STM32L152xD_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /** @addtogroup Configuration_section_for_CMSIS 45 * @{ 46 */ 47 /** 48 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 49 */ 50 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ 51 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ 52 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief STM32L1xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 74 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 75 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 76 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 77 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 78 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 79 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 80 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 81 82 /****** STM32L specific Interrupt Numbers ***********************************************************/ 83 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 84 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 85 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 86 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ 87 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 88 RCC_IRQn = 5, /*!< RCC global Interrupt */ 89 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 90 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 91 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 92 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 93 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 94 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 95 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 96 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 97 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 98 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 99 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 100 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 101 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 102 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ 103 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ 104 DAC_IRQn = 21, /*!< DAC Interrupt */ 105 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ 106 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 107 LCD_IRQn = 24, /*!< LCD Interrupt */ 108 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ 109 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ 110 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ 111 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 112 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 113 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 114 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 115 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 116 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 117 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 118 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 119 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 120 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 121 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 122 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 123 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 124 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 125 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ 126 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ 127 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ 128 SDIO_IRQn = 45, /*!< SDIO global Interrupt */ 129 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ 130 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ 131 UART4_IRQn = 48, /*!< UART4 global Interrupt */ 132 UART5_IRQn = 49, /*!< UART5 global Interrupt */ 133 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ 134 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ 135 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ 136 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ 137 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ 138 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ 139 } IRQn_Type; 140 141 /** 142 * @} 143 */ 144 145 #include "core_cm3.h" 146 #include "system_stm32l1xx.h" 147 #include <stdint.h> 148 149 /** @addtogroup Peripheral_registers_structures 150 * @{ 151 */ 152 153 /** 154 * @brief Analog to Digital Converter 155 */ 156 157 typedef struct 158 { 159 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ 160 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ 161 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ 162 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 163 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 164 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ 165 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ 166 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ 167 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ 168 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ 169 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ 170 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ 171 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 172 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 173 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 174 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 175 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ 176 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ 177 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ 178 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ 179 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ 180 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ 181 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ 182 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ 183 } ADC_TypeDef; 184 185 typedef struct 186 { 187 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ 188 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 189 } ADC_Common_TypeDef; 190 191 /** 192 * @brief Comparator 193 */ 194 195 typedef struct 196 { 197 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 198 } COMP_TypeDef; 199 200 typedef struct 201 { 202 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 203 } COMP_Common_TypeDef; 204 205 /** 206 * @brief CRC calculation unit 207 */ 208 209 typedef struct 210 { 211 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 212 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 213 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 214 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 215 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 216 } CRC_TypeDef; 217 218 /** 219 * @brief Digital to Analog Converter 220 */ 221 222 typedef struct 223 { 224 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 225 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 226 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 227 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 228 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 229 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 230 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 231 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 232 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 233 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 234 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 235 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 236 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 237 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 238 } DAC_TypeDef; 239 240 /** 241 * @brief Debug MCU 242 */ 243 244 typedef struct 245 { 246 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 247 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 248 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 249 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 250 }DBGMCU_TypeDef; 251 252 /** 253 * @brief DMA Controller 254 */ 255 256 typedef struct 257 { 258 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 259 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 260 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 261 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 262 } DMA_Channel_TypeDef; 263 264 typedef struct 265 { 266 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 267 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 268 } DMA_TypeDef; 269 270 /** 271 * @brief External Interrupt/Event Controller 272 */ 273 274 typedef struct 275 { 276 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 277 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 278 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 279 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 280 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 281 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 282 } EXTI_TypeDef; 283 284 /** 285 * @brief FLASH Registers 286 */ 287 typedef struct 288 { 289 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 290 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 291 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 292 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 293 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 294 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 295 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 296 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ 297 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */ 298 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */ 299 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ 300 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */ 301 } FLASH_TypeDef; 302 303 /** 304 * @brief Option Bytes Registers 305 */ 306 typedef struct 307 { 308 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 309 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 310 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ 311 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ 312 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ 313 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ 314 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ 315 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ 316 } OB_TypeDef; 317 318 /** 319 * @brief Operational Amplifier (OPAMP) 320 */ 321 typedef struct 322 { 323 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 324 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ 325 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ 326 } OPAMP_TypeDef; 327 328 typedef struct 329 { 330 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ 331 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 332 } OPAMP_Common_TypeDef; 333 334 /** 335 * @brief Flexible Static Memory Controller 336 */ 337 338 typedef struct 339 { 340 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 341 } FSMC_Bank1_TypeDef; 342 343 /** 344 * @brief Flexible Static Memory Controller Bank1E 345 */ 346 347 typedef struct 348 { 349 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 350 } FSMC_Bank1E_TypeDef; 351 352 /** 353 * @brief General Purpose IO 354 */ 355 356 typedef struct 357 { 358 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 359 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 360 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 361 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 362 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 363 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 364 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 365 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 366 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 367 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 368 } GPIO_TypeDef; 369 370 /** 371 * @brief SysTem Configuration 372 */ 373 374 typedef struct 375 { 376 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 377 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 378 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 379 } SYSCFG_TypeDef; 380 381 /** 382 * @brief Inter-integrated Circuit Interface 383 */ 384 385 typedef struct 386 { 387 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 388 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 389 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 390 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 391 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ 392 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 393 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 394 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 395 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 396 } I2C_TypeDef; 397 398 /** 399 * @brief Independent WATCHDOG 400 */ 401 402 typedef struct 403 { 404 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 405 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 406 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 407 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 408 } IWDG_TypeDef; 409 410 /** 411 * @brief LCD 412 */ 413 414 typedef struct 415 { 416 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ 417 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ 418 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ 419 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ 420 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ 421 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ 422 } LCD_TypeDef; 423 424 /** 425 * @brief Power Control 426 */ 427 428 typedef struct 429 { 430 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 431 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 432 } PWR_TypeDef; 433 434 /** 435 * @brief Reset and Clock Control 436 */ 437 438 typedef struct 439 { 440 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 441 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 442 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ 443 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ 444 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ 445 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ 446 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ 447 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ 448 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ 449 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ 450 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ 451 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ 452 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ 453 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ 454 } RCC_TypeDef; 455 456 /** 457 * @brief Routing Interface 458 */ 459 460 typedef struct 461 { 462 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ 463 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ 464 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ 465 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ 466 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ 467 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ 468 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ 469 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ 470 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ 471 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ 472 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ 473 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ 474 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ 475 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ 476 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ 477 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ 478 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ 479 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ 480 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ 481 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ 482 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ 483 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ 484 } RI_TypeDef; 485 486 /** 487 * @brief Real-Time Clock 488 */ 489 typedef struct 490 { 491 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 492 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 493 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 494 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 495 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 496 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 497 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 498 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 499 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 500 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 501 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 502 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 503 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 504 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 505 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 506 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ 507 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 508 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 509 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 510 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 511 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 512 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 513 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 514 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 515 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 516 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 517 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 518 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 519 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 520 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 521 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 522 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 523 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 524 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 525 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 526 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 527 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 528 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 529 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 530 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 531 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ 532 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ 533 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ 534 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ 535 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ 536 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ 537 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ 538 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ 539 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ 540 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ 541 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ 542 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ 543 } RTC_TypeDef; 544 545 /** 546 * @brief SD host Interface 547 */ 548 549 typedef struct 550 { 551 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ 552 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ 553 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ 554 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ 555 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ 556 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ 557 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ 558 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ 559 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ 560 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ 561 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ 562 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ 563 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ 564 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ 565 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ 566 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ 567 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ 568 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ 569 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ 570 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ 571 } SDIO_TypeDef; 572 573 /** 574 * @brief Serial Peripheral Interface 575 */ 576 577 typedef struct 578 { 579 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 580 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 581 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 582 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 583 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 584 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 585 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 586 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 587 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 588 } SPI_TypeDef; 589 590 /** 591 * @brief TIM 592 */ 593 typedef struct 594 { 595 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 596 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 597 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 598 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 599 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 600 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 601 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 602 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 603 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 604 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 605 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 606 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 607 uint32_t RESERVED12; /*!< Reserved, 0x30 */ 608 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 609 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 610 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 611 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 612 uint32_t RESERVED17; /*!< Reserved, 0x44 */ 613 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 614 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 615 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 616 } TIM_TypeDef; 617 /** 618 * @brief Universal Synchronous Asynchronous Receiver Transmitter 619 */ 620 621 typedef struct 622 { 623 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 624 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 625 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 626 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 627 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 628 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 629 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 630 } USART_TypeDef; 631 632 /** 633 * @brief Universal Serial Bus Full Speed Device 634 */ 635 636 typedef struct 637 { 638 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 639 __IO uint16_t RESERVED0; /*!< Reserved */ 640 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 641 __IO uint16_t RESERVED1; /*!< Reserved */ 642 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 643 __IO uint16_t RESERVED2; /*!< Reserved */ 644 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 645 __IO uint16_t RESERVED3; /*!< Reserved */ 646 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 647 __IO uint16_t RESERVED4; /*!< Reserved */ 648 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 649 __IO uint16_t RESERVED5; /*!< Reserved */ 650 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 651 __IO uint16_t RESERVED6; /*!< Reserved */ 652 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 653 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 654 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 655 __IO uint16_t RESERVED8; /*!< Reserved */ 656 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 657 __IO uint16_t RESERVED9; /*!< Reserved */ 658 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 659 __IO uint16_t RESERVEDA; /*!< Reserved */ 660 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 661 __IO uint16_t RESERVEDB; /*!< Reserved */ 662 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 663 __IO uint16_t RESERVEDC; /*!< Reserved */ 664 } USB_TypeDef; 665 666 /** 667 * @brief Window WATCHDOG 668 */ 669 typedef struct 670 { 671 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 672 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 673 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 674 } WWDG_TypeDef; 675 676 /** 677 * @brief Universal Serial Bus Full Speed Device 678 */ 679 /** 680 * @} 681 */ 682 683 /** @addtogroup Peripheral_memory_map 684 * @{ 685 */ 686 687 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ 688 #define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */ 689 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ 690 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ 691 #define FSMC_BASE (0x60000000UL) /*!< FSMC base address */ 692 #define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */ 693 #define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ 694 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ 695 #define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */ 696 #define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */ 697 #define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */ 698 #define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */ 699 #define FLASH_EEPROM_END (0x08082FFFUL) /*!< FLASH EEPROM end address (12KB) */ 700 701 /*!< Peripheral memory map */ 702 #define APB1PERIPH_BASE PERIPH_BASE 703 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 704 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 705 706 /*!< APB1 peripherals */ 707 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 708 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 709 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 710 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) 711 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 712 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 713 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) 714 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 715 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 716 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 717 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 718 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) 719 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 720 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 721 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) 722 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) 723 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 724 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 725 726 /* USB device FS */ 727 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ 728 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ 729 730 /* USB device FS SRAM */ 731 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 732 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 733 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL) 734 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL) 735 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL) 736 737 /*!< APB2 peripherals */ 738 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) 739 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 740 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL) 741 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL) 742 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL) 743 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 744 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL) 745 #define SDIO_BASE (APB2PERIPH_BASE + 0x00002C00UL) 746 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 747 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 748 749 /*!< AHB peripherals */ 750 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL) 751 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL) 752 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL) 753 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL) 754 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL) 755 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL) 756 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL) 757 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL) 758 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 759 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL) 760 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */ 761 #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ 762 #define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 763 #define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 764 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) 765 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 766 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 767 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 768 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 769 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 770 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 771 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 772 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) 773 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) 774 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) 775 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) 776 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) 777 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) 778 #define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ 779 #define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ 780 #define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */ 781 #define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */ 782 #define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */ 783 #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000UL) /*!< FSMC Bank1 registers base address */ 784 #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104UL) /*!< FSMC Bank1E registers base address */ 785 #define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */ 786 787 /** 788 * @} 789 */ 790 791 /** @addtogroup Peripheral_declaration 792 * @{ 793 */ 794 795 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 796 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 797 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 798 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 799 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 800 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 801 #define LCD ((LCD_TypeDef *) LCD_BASE) 802 #define RTC ((RTC_TypeDef *) RTC_BASE) 803 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 804 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 805 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 806 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 807 #define USART2 ((USART_TypeDef *) USART2_BASE) 808 #define USART3 ((USART_TypeDef *) USART3_BASE) 809 #define UART4 ((USART_TypeDef *) UART4_BASE) 810 #define UART5 ((USART_TypeDef *) UART5_BASE) 811 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 812 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 813 /* USB device FS */ 814 #define USB ((USB_TypeDef *) USB_BASE) 815 /* USB device FS SRAM */ 816 #define PWR ((PWR_TypeDef *) PWR_BASE) 817 818 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 819 /* Legacy define */ 820 #define DAC DAC1 821 822 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ 823 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 824 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 825 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ 826 827 #define RI ((RI_TypeDef *) RI_BASE) 828 829 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 830 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) 831 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) 832 #define OPAMP3 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U)) 833 #define OPAMP123_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) 834 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 835 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 836 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 837 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 838 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 839 840 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 841 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 842 /* Legacy defines */ 843 #define ADC ADC1_COMMON 844 845 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 846 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 847 #define USART1 ((USART_TypeDef *) USART1_BASE) 848 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 849 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 850 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 851 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 852 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 853 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 854 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 855 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 856 #define CRC ((CRC_TypeDef *) CRC_BASE) 857 #define RCC ((RCC_TypeDef *) RCC_BASE) 858 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 859 #define OB ((OB_TypeDef *) OB_BASE) 860 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 861 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 862 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 863 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 864 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 865 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 866 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 867 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 868 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 869 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 870 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 871 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 872 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 873 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 874 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE) 875 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE) 876 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 877 878 /** 879 * @} 880 */ 881 882 /** @addtogroup Exported_constants 883 * @{ 884 */ 885 886 /** @addtogroup Hardware_Constant_Definition 887 * @{ 888 */ 889 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ 890 891 /** 892 * @} 893 */ 894 895 /** @addtogroup Peripheral_Registers_Bits_Definition 896 * @{ 897 */ 898 899 /******************************************************************************/ 900 /* Peripheral Registers Bits Definition */ 901 /******************************************************************************/ 902 /******************************************************************************/ 903 /* */ 904 /* Analog to Digital Converter (ADC) */ 905 /* */ 906 /******************************************************************************/ 907 #define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 908 #define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 909 #define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ 910 911 /******************** Bit definition for ADC_SR register ********************/ 912 #define ADC_SR_AWD_Pos (0U) 913 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 914 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 915 #define ADC_SR_EOCS_Pos (1U) 916 #define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ 917 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ 918 #define ADC_SR_JEOS_Pos (2U) 919 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 920 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 921 #define ADC_SR_JSTRT_Pos (3U) 922 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 923 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 924 #define ADC_SR_STRT_Pos (4U) 925 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 926 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 927 #define ADC_SR_OVR_Pos (5U) 928 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ 929 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ 930 #define ADC_SR_ADONS_Pos (6U) 931 #define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ 932 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ 933 #define ADC_SR_RCNR_Pos (8U) 934 #define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ 935 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ 936 #define ADC_SR_JCNR_Pos (9U) 937 #define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ 938 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ 939 940 /* Legacy defines */ 941 #define ADC_SR_EOC (ADC_SR_EOCS) 942 #define ADC_SR_JEOC (ADC_SR_JEOS) 943 944 /******************* Bit definition for ADC_CR1 register ********************/ 945 #define ADC_CR1_AWDCH_Pos (0U) 946 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 947 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 948 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 949 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 950 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 951 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 952 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 953 954 #define ADC_CR1_EOCSIE_Pos (5U) 955 #define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ 956 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ 957 #define ADC_CR1_AWDIE_Pos (6U) 958 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 959 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 960 #define ADC_CR1_JEOSIE_Pos (7U) 961 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 962 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 963 #define ADC_CR1_SCAN_Pos (8U) 964 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 965 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 966 #define ADC_CR1_AWDSGL_Pos (9U) 967 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 968 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 969 #define ADC_CR1_JAUTO_Pos (10U) 970 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 971 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 972 #define ADC_CR1_DISCEN_Pos (11U) 973 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 974 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 975 #define ADC_CR1_JDISCEN_Pos (12U) 976 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 977 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 978 979 #define ADC_CR1_DISCNUM_Pos (13U) 980 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 981 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 982 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 983 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 984 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 985 986 #define ADC_CR1_PDD_Pos (16U) 987 #define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ 988 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ 989 #define ADC_CR1_PDI_Pos (17U) 990 #define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ 991 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ 992 993 #define ADC_CR1_JAWDEN_Pos (22U) 994 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 995 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 996 #define ADC_CR1_AWDEN_Pos (23U) 997 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 998 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 999 1000 #define ADC_CR1_RES_Pos (24U) 1001 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ 1002 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ 1003 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ 1004 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ 1005 1006 #define ADC_CR1_OVRIE_Pos (26U) 1007 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ 1008 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 1009 1010 /* Legacy defines */ 1011 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) 1012 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 1013 1014 /******************* Bit definition for ADC_CR2 register ********************/ 1015 #define ADC_CR2_ADON_Pos (0U) 1016 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 1017 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 1018 #define ADC_CR2_CONT_Pos (1U) 1019 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 1020 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1021 #define ADC_CR2_CFG_Pos (2U) 1022 #define ADC_CR2_CFG_Msk (0x1UL << ADC_CR2_CFG_Pos) /*!< 0x00000004 */ 1023 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */ 1024 1025 #define ADC_CR2_DELS_Pos (4U) 1026 #define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ 1027 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ 1028 #define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ 1029 #define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ 1030 #define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ 1031 1032 #define ADC_CR2_DMA_Pos (8U) 1033 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 1034 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 1035 #define ADC_CR2_DDS_Pos (9U) 1036 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ 1037 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ 1038 #define ADC_CR2_EOCS_Pos (10U) 1039 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ 1040 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ 1041 #define ADC_CR2_ALIGN_Pos (11U) 1042 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 1043 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 1044 1045 #define ADC_CR2_JEXTSEL_Pos (16U) 1046 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ 1047 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1048 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ 1049 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ 1050 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ 1051 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ 1052 1053 #define ADC_CR2_JEXTEN_Pos (20U) 1054 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ 1055 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1056 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ 1057 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ 1058 1059 #define ADC_CR2_JSWSTART_Pos (22U) 1060 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ 1061 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 1062 1063 #define ADC_CR2_EXTSEL_Pos (24U) 1064 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ 1065 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1066 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ 1067 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ 1068 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ 1069 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ 1070 1071 #define ADC_CR2_EXTEN_Pos (28U) 1072 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ 1073 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1074 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ 1075 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ 1076 1077 #define ADC_CR2_SWSTART_Pos (30U) 1078 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ 1079 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 1080 1081 /****************** Bit definition for ADC_SMPR1 register *******************/ 1082 #define ADC_SMPR1_SMP20_Pos (0U) 1083 #define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ 1084 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ 1085 #define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ 1086 #define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ 1087 #define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ 1088 1089 #define ADC_SMPR1_SMP21_Pos (3U) 1090 #define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ 1091 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ 1092 #define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ 1093 #define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ 1094 #define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ 1095 1096 #define ADC_SMPR1_SMP22_Pos (6U) 1097 #define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ 1098 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ 1099 #define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ 1100 #define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ 1101 #define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ 1102 1103 #define ADC_SMPR1_SMP23_Pos (9U) 1104 #define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ 1105 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ 1106 #define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ 1107 #define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ 1108 #define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ 1109 1110 #define ADC_SMPR1_SMP24_Pos (12U) 1111 #define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ 1112 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ 1113 #define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ 1114 #define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ 1115 #define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ 1116 1117 #define ADC_SMPR1_SMP25_Pos (15U) 1118 #define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ 1119 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ 1120 #define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ 1121 #define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ 1122 #define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ 1123 1124 #define ADC_SMPR1_SMP26_Pos (18U) 1125 #define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ 1126 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ 1127 #define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ 1128 #define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ 1129 #define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ 1130 1131 #define ADC_SMPR1_SMP27_Pos (21U) 1132 #define ADC_SMPR1_SMP27_Msk (0x7UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */ 1133 #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */ 1134 #define ADC_SMPR1_SMP27_0 (0x1UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */ 1135 #define ADC_SMPR1_SMP27_1 (0x2UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */ 1136 #define ADC_SMPR1_SMP27_2 (0x4UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */ 1137 1138 #define ADC_SMPR1_SMP28_Pos (24U) 1139 #define ADC_SMPR1_SMP28_Msk (0x7UL << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */ 1140 #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */ 1141 #define ADC_SMPR1_SMP28_0 (0x1UL << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */ 1142 #define ADC_SMPR1_SMP28_1 (0x2UL << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */ 1143 #define ADC_SMPR1_SMP28_2 (0x4UL << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */ 1144 1145 #define ADC_SMPR1_SMP29_Pos (27U) 1146 #define ADC_SMPR1_SMP29_Msk (0x7UL << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */ 1147 #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */ 1148 #define ADC_SMPR1_SMP29_0 (0x1UL << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */ 1149 #define ADC_SMPR1_SMP29_1 (0x2UL << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */ 1150 #define ADC_SMPR1_SMP29_2 (0x4UL << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */ 1151 1152 /****************** Bit definition for ADC_SMPR2 register *******************/ 1153 #define ADC_SMPR2_SMP10_Pos (0U) 1154 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1155 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1156 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1157 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1158 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1159 1160 #define ADC_SMPR2_SMP11_Pos (3U) 1161 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1162 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1163 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1164 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1165 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1166 1167 #define ADC_SMPR2_SMP12_Pos (6U) 1168 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1169 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1170 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1171 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1172 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1173 1174 #define ADC_SMPR2_SMP13_Pos (9U) 1175 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1176 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1177 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1178 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1179 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1180 1181 #define ADC_SMPR2_SMP14_Pos (12U) 1182 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1183 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1184 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1185 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1186 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1187 1188 #define ADC_SMPR2_SMP15_Pos (15U) 1189 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1190 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ 1191 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1192 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1193 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1194 1195 #define ADC_SMPR2_SMP16_Pos (18U) 1196 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1197 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1198 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1199 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1200 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1201 1202 #define ADC_SMPR2_SMP17_Pos (21U) 1203 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1204 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1205 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1206 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1207 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1208 1209 #define ADC_SMPR2_SMP18_Pos (24U) 1210 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1211 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1212 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1213 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1214 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1215 1216 #define ADC_SMPR2_SMP19_Pos (27U) 1217 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ 1218 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ 1219 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ 1220 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ 1221 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ 1222 1223 /****************** Bit definition for ADC_SMPR3 register *******************/ 1224 #define ADC_SMPR3_SMP0_Pos (0U) 1225 #define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ 1226 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1227 #define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ 1228 #define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ 1229 #define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ 1230 1231 #define ADC_SMPR3_SMP1_Pos (3U) 1232 #define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ 1233 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1234 #define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ 1235 #define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ 1236 #define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ 1237 1238 #define ADC_SMPR3_SMP2_Pos (6U) 1239 #define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ 1240 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1241 #define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ 1242 #define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ 1243 #define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ 1244 1245 #define ADC_SMPR3_SMP3_Pos (9U) 1246 #define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ 1247 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1248 #define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ 1249 #define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ 1250 #define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ 1251 1252 #define ADC_SMPR3_SMP4_Pos (12U) 1253 #define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ 1254 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1255 #define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ 1256 #define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ 1257 #define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ 1258 1259 #define ADC_SMPR3_SMP5_Pos (15U) 1260 #define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ 1261 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1262 #define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ 1263 #define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ 1264 #define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ 1265 1266 #define ADC_SMPR3_SMP6_Pos (18U) 1267 #define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ 1268 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1269 #define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ 1270 #define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ 1271 #define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ 1272 1273 #define ADC_SMPR3_SMP7_Pos (21U) 1274 #define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ 1275 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1276 #define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ 1277 #define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ 1278 #define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ 1279 1280 #define ADC_SMPR3_SMP8_Pos (24U) 1281 #define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ 1282 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1283 #define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ 1284 #define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ 1285 #define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ 1286 1287 #define ADC_SMPR3_SMP9_Pos (27U) 1288 #define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ 1289 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1290 #define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ 1291 #define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ 1292 #define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ 1293 1294 /****************** Bit definition for ADC_JOFR1 register *******************/ 1295 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1296 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 1297 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 1298 1299 /****************** Bit definition for ADC_JOFR2 register *******************/ 1300 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1301 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 1302 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 1303 1304 /****************** Bit definition for ADC_JOFR3 register *******************/ 1305 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1306 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 1307 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 1308 1309 /****************** Bit definition for ADC_JOFR4 register *******************/ 1310 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1311 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 1312 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 1313 1314 /******************* Bit definition for ADC_HTR register ********************/ 1315 #define ADC_HTR_HT_Pos (0U) 1316 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 1317 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 1318 1319 /******************* Bit definition for ADC_LTR register ********************/ 1320 #define ADC_LTR_LT_Pos (0U) 1321 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 1322 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 1323 1324 /******************* Bit definition for ADC_SQR1 register *******************/ 1325 #define ADC_SQR1_L_Pos (20U) 1326 #define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ 1327 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1328 #define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 1329 #define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 1330 #define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 1331 #define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 1332 #define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /*!< 0x01000000 */ 1333 1334 #define ADC_SQR1_SQ28_Pos (15U) 1335 #define ADC_SQR1_SQ28_Msk (0x1FUL << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */ 1336 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */ 1337 #define ADC_SQR1_SQ28_0 (0x01UL << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */ 1338 #define ADC_SQR1_SQ28_1 (0x02UL << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */ 1339 #define ADC_SQR1_SQ28_2 (0x04UL << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */ 1340 #define ADC_SQR1_SQ28_3 (0x08UL << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */ 1341 #define ADC_SQR1_SQ28_4 (0x10UL << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */ 1342 1343 #define ADC_SQR1_SQ27_Pos (10U) 1344 #define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ 1345 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ 1346 #define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ 1347 #define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ 1348 #define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ 1349 #define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ 1350 #define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ 1351 1352 #define ADC_SQR1_SQ26_Pos (5U) 1353 #define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ 1354 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ 1355 #define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ 1356 #define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ 1357 #define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ 1358 #define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ 1359 #define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ 1360 1361 #define ADC_SQR1_SQ25_Pos (0U) 1362 #define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ 1363 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ 1364 #define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ 1365 #define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ 1366 #define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ 1367 #define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ 1368 #define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ 1369 1370 /******************* Bit definition for ADC_SQR2 register *******************/ 1371 #define ADC_SQR2_SQ19_Pos (0U) 1372 #define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ 1373 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ 1374 #define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ 1375 #define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ 1376 #define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ 1377 #define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ 1378 #define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ 1379 1380 #define ADC_SQR2_SQ20_Pos (5U) 1381 #define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ 1382 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ 1383 #define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ 1384 #define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ 1385 #define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ 1386 #define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ 1387 #define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ 1388 1389 #define ADC_SQR2_SQ21_Pos (10U) 1390 #define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ 1391 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ 1392 #define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ 1393 #define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ 1394 #define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ 1395 #define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ 1396 #define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ 1397 1398 #define ADC_SQR2_SQ22_Pos (15U) 1399 #define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ 1400 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ 1401 #define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ 1402 #define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ 1403 #define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ 1404 #define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ 1405 #define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ 1406 1407 #define ADC_SQR2_SQ23_Pos (20U) 1408 #define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ 1409 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ 1410 #define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ 1411 #define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ 1412 #define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ 1413 #define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ 1414 #define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ 1415 1416 #define ADC_SQR2_SQ24_Pos (25U) 1417 #define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ 1418 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ 1419 #define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ 1420 #define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ 1421 #define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ 1422 #define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ 1423 #define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ 1424 1425 /******************* Bit definition for ADC_SQR3 register *******************/ 1426 #define ADC_SQR3_SQ13_Pos (0U) 1427 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ 1428 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1429 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ 1430 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ 1431 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ 1432 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ 1433 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ 1434 1435 #define ADC_SQR3_SQ14_Pos (5U) 1436 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ 1437 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1438 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ 1439 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ 1440 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ 1441 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ 1442 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ 1443 1444 #define ADC_SQR3_SQ15_Pos (10U) 1445 #define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ 1446 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1447 #define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ 1448 #define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ 1449 #define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ 1450 #define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ 1451 #define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ 1452 1453 #define ADC_SQR3_SQ16_Pos (15U) 1454 #define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ 1455 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1456 #define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ 1457 #define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ 1458 #define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ 1459 #define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ 1460 #define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ 1461 1462 #define ADC_SQR3_SQ17_Pos (20U) 1463 #define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ 1464 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ 1465 #define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ 1466 #define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ 1467 #define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ 1468 #define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ 1469 #define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ 1470 1471 #define ADC_SQR3_SQ18_Pos (25U) 1472 #define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ 1473 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ 1474 #define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ 1475 #define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ 1476 #define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ 1477 #define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ 1478 #define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ 1479 1480 /******************* Bit definition for ADC_SQR4 register *******************/ 1481 #define ADC_SQR4_SQ7_Pos (0U) 1482 #define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ 1483 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1484 #define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ 1485 #define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ 1486 #define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ 1487 #define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ 1488 #define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ 1489 1490 #define ADC_SQR4_SQ8_Pos (5U) 1491 #define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ 1492 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1493 #define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ 1494 #define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ 1495 #define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ 1496 #define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ 1497 #define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ 1498 1499 #define ADC_SQR4_SQ9_Pos (10U) 1500 #define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ 1501 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1502 #define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ 1503 #define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ 1504 #define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ 1505 #define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ 1506 #define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ 1507 1508 #define ADC_SQR4_SQ10_Pos (15U) 1509 #define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ 1510 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1511 #define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ 1512 #define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ 1513 #define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ 1514 #define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ 1515 #define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ 1516 1517 #define ADC_SQR4_SQ11_Pos (20U) 1518 #define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ 1519 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1520 #define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ 1521 #define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ 1522 #define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ 1523 #define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ 1524 #define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ 1525 1526 #define ADC_SQR4_SQ12_Pos (25U) 1527 #define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ 1528 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1529 #define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ 1530 #define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ 1531 #define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ 1532 #define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ 1533 #define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ 1534 1535 /******************* Bit definition for ADC_SQR5 register *******************/ 1536 #define ADC_SQR5_SQ1_Pos (0U) 1537 #define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ 1538 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1539 #define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ 1540 #define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ 1541 #define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ 1542 #define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ 1543 #define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ 1544 1545 #define ADC_SQR5_SQ2_Pos (5U) 1546 #define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ 1547 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1548 #define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ 1549 #define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ 1550 #define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ 1551 #define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ 1552 #define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ 1553 1554 #define ADC_SQR5_SQ3_Pos (10U) 1555 #define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ 1556 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1557 #define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ 1558 #define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ 1559 #define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ 1560 #define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ 1561 #define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ 1562 1563 #define ADC_SQR5_SQ4_Pos (15U) 1564 #define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ 1565 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1566 #define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ 1567 #define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ 1568 #define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ 1569 #define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ 1570 #define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ 1571 1572 #define ADC_SQR5_SQ5_Pos (20U) 1573 #define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ 1574 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1575 #define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ 1576 #define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ 1577 #define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ 1578 #define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ 1579 #define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ 1580 1581 #define ADC_SQR5_SQ6_Pos (25U) 1582 #define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ 1583 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1584 #define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ 1585 #define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ 1586 #define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ 1587 #define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ 1588 #define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ 1589 1590 1591 /******************* Bit definition for ADC_JSQR register *******************/ 1592 #define ADC_JSQR_JSQ1_Pos (0U) 1593 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 1594 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1595 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 1596 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 1597 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 1598 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 1599 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 1600 1601 #define ADC_JSQR_JSQ2_Pos (5U) 1602 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 1603 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1604 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 1605 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 1606 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 1607 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 1608 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 1609 1610 #define ADC_JSQR_JSQ3_Pos (10U) 1611 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 1612 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1613 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 1614 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 1615 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 1616 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 1617 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 1618 1619 #define ADC_JSQR_JSQ4_Pos (15U) 1620 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 1621 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1622 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 1623 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 1624 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 1625 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 1626 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 1627 1628 #define ADC_JSQR_JL_Pos (20U) 1629 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 1630 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1631 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 1632 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 1633 1634 /******************* Bit definition for ADC_JDR1 register *******************/ 1635 #define ADC_JDR1_JDATA_Pos (0U) 1636 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1637 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1638 1639 /******************* Bit definition for ADC_JDR2 register *******************/ 1640 #define ADC_JDR2_JDATA_Pos (0U) 1641 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1642 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1643 1644 /******************* Bit definition for ADC_JDR3 register *******************/ 1645 #define ADC_JDR3_JDATA_Pos (0U) 1646 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1647 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1648 1649 /******************* Bit definition for ADC_JDR4 register *******************/ 1650 #define ADC_JDR4_JDATA_Pos (0U) 1651 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1652 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1653 1654 /******************** Bit definition for ADC_DR register ********************/ 1655 #define ADC_DR_DATA_Pos (0U) 1656 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1657 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1658 1659 /****************** Bit definition for ADC_SMPR0 register *******************/ 1660 #define ADC_SMPR0_SMP30_Pos (0U) 1661 #define ADC_SMPR0_SMP30_Msk (0x7UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */ 1662 #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */ 1663 #define ADC_SMPR0_SMP30_0 (0x1UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */ 1664 #define ADC_SMPR0_SMP30_1 (0x2UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */ 1665 #define ADC_SMPR0_SMP30_2 (0x4UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */ 1666 1667 #define ADC_SMPR0_SMP31_Pos (3U) 1668 #define ADC_SMPR0_SMP31_Msk (0x7UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */ 1669 #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */ 1670 #define ADC_SMPR0_SMP31_0 (0x1UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */ 1671 #define ADC_SMPR0_SMP31_1 (0x2UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */ 1672 #define ADC_SMPR0_SMP31_2 (0x4UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */ 1673 1674 /******************* Bit definition for ADC_CSR register ********************/ 1675 #define ADC_CSR_AWD1_Pos (0U) 1676 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ 1677 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1678 #define ADC_CSR_EOCS1_Pos (1U) 1679 #define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ 1680 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ 1681 #define ADC_CSR_JEOS1_Pos (2U) 1682 #define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ 1683 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1684 #define ADC_CSR_JSTRT1_Pos (3U) 1685 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ 1686 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ 1687 #define ADC_CSR_STRT1_Pos (4U) 1688 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ 1689 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ 1690 #define ADC_CSR_OVR1_Pos (5U) 1691 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ 1692 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ 1693 #define ADC_CSR_ADONS1_Pos (6U) 1694 #define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ 1695 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ 1696 1697 /* Legacy defines */ 1698 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) 1699 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) 1700 1701 /******************* Bit definition for ADC_CCR register ********************/ 1702 #define ADC_CCR_ADCPRE_Pos (16U) 1703 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ 1704 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ 1705 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ 1706 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ 1707 #define ADC_CCR_TSVREFE_Pos (23U) 1708 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ 1709 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 1710 1711 /******************************************************************************/ 1712 /* */ 1713 /* Analog Comparators (COMP) */ 1714 /* */ 1715 /******************************************************************************/ 1716 1717 /****************** Bit definition for COMP_CSR register ********************/ 1718 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ 1719 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ 1720 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ 1721 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ 1722 #define COMP_CSR_CMP1EN_Pos (4U) 1723 #define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ 1724 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ 1725 #define COMP_CSR_CMP1OUT_Pos (7U) 1726 #define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ 1727 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ 1728 #define COMP_CSR_SPEED_Pos (12U) 1729 #define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ 1730 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ 1731 #define COMP_CSR_CMP2OUT_Pos (13U) 1732 #define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ 1733 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ 1734 1735 #define COMP_CSR_WNDWE_Pos (17U) 1736 #define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ 1737 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1738 1739 #define COMP_CSR_INSEL_Pos (18U) 1740 #define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ 1741 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ 1742 #define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ 1743 #define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ 1744 #define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ 1745 #define COMP_CSR_OUTSEL_Pos (21U) 1746 #define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ 1747 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ 1748 #define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ 1749 #define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ 1750 #define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ 1751 1752 /* Bits present in COMP register but not related to comparator */ 1753 /* (or partially related to comparator, in addition to other peripherals) */ 1754 #define COMP_CSR_SW1_Pos (5U) 1755 #define COMP_CSR_SW1_Msk (0x1UL << COMP_CSR_SW1_Pos) /*!< 0x00000020 */ 1756 #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */ 1757 #define COMP_CSR_VREFOUTEN_Pos (16U) 1758 #define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ 1759 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ 1760 1761 #define COMP_CSR_FCH3_Pos (26U) 1762 #define COMP_CSR_FCH3_Msk (0x1UL << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */ 1763 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */ 1764 #define COMP_CSR_FCH8_Pos (27U) 1765 #define COMP_CSR_FCH8_Msk (0x1UL << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */ 1766 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */ 1767 #define COMP_CSR_RCH13_Pos (28U) 1768 #define COMP_CSR_RCH13_Msk (0x1UL << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */ 1769 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */ 1770 1771 #define COMP_CSR_CAIE_Pos (29U) 1772 #define COMP_CSR_CAIE_Msk (0x1UL << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */ 1773 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */ 1774 #define COMP_CSR_CAIF_Pos (30U) 1775 #define COMP_CSR_CAIF_Msk (0x1UL << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */ 1776 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */ 1777 #define COMP_CSR_TSUSP_Pos (31U) 1778 #define COMP_CSR_TSUSP_Msk (0x1UL << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */ 1779 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */ 1780 1781 /******************************************************************************/ 1782 /* */ 1783 /* Operational Amplifier (OPAMP) */ 1784 /* */ 1785 /******************************************************************************/ 1786 /******************* Bit definition for OPAMP_CSR register ******************/ 1787 #define OPAMP_CSR_OPA1PD_Pos (0U) 1788 #define OPAMP_CSR_OPA1PD_Msk (0x1UL << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */ 1789 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */ 1790 #define OPAMP_CSR_S3SEL1_Pos (1U) 1791 #define OPAMP_CSR_S3SEL1_Msk (0x1UL << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */ 1792 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */ 1793 #define OPAMP_CSR_S4SEL1_Pos (2U) 1794 #define OPAMP_CSR_S4SEL1_Msk (0x1UL << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */ 1795 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */ 1796 #define OPAMP_CSR_S5SEL1_Pos (3U) 1797 #define OPAMP_CSR_S5SEL1_Msk (0x1UL << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */ 1798 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */ 1799 #define OPAMP_CSR_S6SEL1_Pos (4U) 1800 #define OPAMP_CSR_S6SEL1_Msk (0x1UL << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */ 1801 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */ 1802 #define OPAMP_CSR_OPA1CAL_L_Pos (5U) 1803 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */ 1804 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */ 1805 #define OPAMP_CSR_OPA1CAL_H_Pos (6U) 1806 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */ 1807 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */ 1808 #define OPAMP_CSR_OPA1LPM_Pos (7U) 1809 #define OPAMP_CSR_OPA1LPM_Msk (0x1UL << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */ 1810 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */ 1811 #define OPAMP_CSR_OPA2PD_Pos (8U) 1812 #define OPAMP_CSR_OPA2PD_Msk (0x1UL << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */ 1813 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */ 1814 #define OPAMP_CSR_S3SEL2_Pos (9U) 1815 #define OPAMP_CSR_S3SEL2_Msk (0x1UL << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */ 1816 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */ 1817 #define OPAMP_CSR_S4SEL2_Pos (10U) 1818 #define OPAMP_CSR_S4SEL2_Msk (0x1UL << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */ 1819 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */ 1820 #define OPAMP_CSR_S5SEL2_Pos (11U) 1821 #define OPAMP_CSR_S5SEL2_Msk (0x1UL << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */ 1822 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */ 1823 #define OPAMP_CSR_S6SEL2_Pos (12U) 1824 #define OPAMP_CSR_S6SEL2_Msk (0x1UL << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */ 1825 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */ 1826 #define OPAMP_CSR_OPA2CAL_L_Pos (13U) 1827 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */ 1828 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */ 1829 #define OPAMP_CSR_OPA2CAL_H_Pos (14U) 1830 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */ 1831 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */ 1832 #define OPAMP_CSR_OPA2LPM_Pos (15U) 1833 #define OPAMP_CSR_OPA2LPM_Msk (0x1UL << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */ 1834 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */ 1835 #define OPAMP_CSR_OPA3PD_Pos (16U) 1836 #define OPAMP_CSR_OPA3PD_Msk (0x1UL << OPAMP_CSR_OPA3PD_Pos) /*!< 0x00010000 */ 1837 #define OPAMP_CSR_OPA3PD OPAMP_CSR_OPA3PD_Msk /*!< OPAMP3 disable */ 1838 #define OPAMP_CSR_S3SEL3_Pos (17U) 1839 #define OPAMP_CSR_S3SEL3_Msk (0x1UL << OPAMP_CSR_S3SEL3_Pos) /*!< 0x00020000 */ 1840 #define OPAMP_CSR_S3SEL3 OPAMP_CSR_S3SEL3_Msk /*!< Switch 3 for OPAMP3 Enable */ 1841 #define OPAMP_CSR_S4SEL3_Pos (18U) 1842 #define OPAMP_CSR_S4SEL3_Msk (0x1UL << OPAMP_CSR_S4SEL3_Pos) /*!< 0x00040000 */ 1843 #define OPAMP_CSR_S4SEL3 OPAMP_CSR_S4SEL3_Msk /*!< Switch 4 for OPAMP3 Enable */ 1844 #define OPAMP_CSR_S5SEL3_Pos (19U) 1845 #define OPAMP_CSR_S5SEL3_Msk (0x1UL << OPAMP_CSR_S5SEL3_Pos) /*!< 0x00080000 */ 1846 #define OPAMP_CSR_S5SEL3 OPAMP_CSR_S5SEL3_Msk /*!< Switch 5 for OPAMP3 Enable */ 1847 #define OPAMP_CSR_S6SEL3_Pos (20U) 1848 #define OPAMP_CSR_S6SEL3_Msk (0x1UL << OPAMP_CSR_S6SEL3_Pos) /*!< 0x00100000 */ 1849 #define OPAMP_CSR_S6SEL3 OPAMP_CSR_S6SEL3_Msk /*!< Switch 6 for OPAMP3 Enable */ 1850 #define OPAMP_CSR_OPA3CAL_L_Pos (21U) 1851 #define OPAMP_CSR_OPA3CAL_L_Msk (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */ 1852 #define OPAMP_CSR_OPA3CAL_L OPAMP_CSR_OPA3CAL_L_Msk /*!< OPAMP3 Offset calibration for P differential pair */ 1853 #define OPAMP_CSR_OPA3CAL_H_Pos (22U) 1854 #define OPAMP_CSR_OPA3CAL_H_Msk (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */ 1855 #define OPAMP_CSR_OPA3CAL_H OPAMP_CSR_OPA3CAL_H_Msk /*!< OPAMP3 Offset calibration for N differential pair */ 1856 #define OPAMP_CSR_OPA3LPM_Pos (23U) 1857 #define OPAMP_CSR_OPA3LPM_Msk (0x1UL << OPAMP_CSR_OPA3LPM_Pos) /*!< 0x00800000 */ 1858 #define OPAMP_CSR_OPA3LPM OPAMP_CSR_OPA3LPM_Msk /*!< OPAMP3 Low power enable */ 1859 #define OPAMP_CSR_ANAWSEL1_Pos (24U) 1860 #define OPAMP_CSR_ANAWSEL1_Msk (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */ 1861 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ 1862 #define OPAMP_CSR_ANAWSEL2_Pos (25U) 1863 #define OPAMP_CSR_ANAWSEL2_Msk (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */ 1864 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */ 1865 #define OPAMP_CSR_ANAWSEL3_Pos (26U) 1866 #define OPAMP_CSR_ANAWSEL3_Msk (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */ 1867 #define OPAMP_CSR_ANAWSEL3 OPAMP_CSR_ANAWSEL3_Msk /*!< Switch ANA Enable for OPAMP3 */ 1868 #define OPAMP_CSR_S7SEL2_Pos (27U) 1869 #define OPAMP_CSR_S7SEL2_Msk (0x1UL << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */ 1870 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */ 1871 #define OPAMP_CSR_AOP_RANGE_Pos (28U) 1872 #define OPAMP_CSR_AOP_RANGE_Msk (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */ 1873 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ 1874 #define OPAMP_CSR_OPA1CALOUT_Pos (29U) 1875 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */ 1876 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */ 1877 #define OPAMP_CSR_OPA2CALOUT_Pos (30U) 1878 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */ 1879 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */ 1880 #define OPAMP_CSR_OPA3CALOUT_Pos (31U) 1881 #define OPAMP_CSR_OPA3CALOUT_Msk (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */ 1882 #define OPAMP_CSR_OPA3CALOUT OPAMP_CSR_OPA3CALOUT_Msk /*!< OPAMP3 calibration output */ 1883 1884 /******************* Bit definition for OPAMP_OTR register ******************/ 1885 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) 1886 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */ 1887 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1888 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) 1889 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */ 1890 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1891 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) 1892 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */ 1893 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1894 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) 1895 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */ 1896 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1897 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U) 1898 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */ 1899 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ 1900 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U) 1901 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */ 1902 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ 1903 #define OPAMP_OTR_OT_USER_Pos (31U) 1904 #define OPAMP_OTR_OT_USER_Msk (0x1UL << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */ 1905 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */ 1906 1907 /******************* Bit definition for OPAMP_LPOTR register ****************/ 1908 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) 1909 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */ 1910 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1911 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) 1912 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */ 1913 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1914 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) 1915 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */ 1916 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1917 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) 1918 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */ 1919 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1920 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U) 1921 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */ 1922 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ 1923 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U) 1924 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */ 1925 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ 1926 1927 /******************************************************************************/ 1928 /* */ 1929 /* CRC calculation unit (CRC) */ 1930 /* */ 1931 /******************************************************************************/ 1932 1933 /******************* Bit definition for CRC_DR register *********************/ 1934 #define CRC_DR_DR_Pos (0U) 1935 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1936 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1937 1938 /******************* Bit definition for CRC_IDR register ********************/ 1939 #define CRC_IDR_IDR_Pos (0U) 1940 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 1941 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 1942 1943 /******************** Bit definition for CRC_CR register ********************/ 1944 #define CRC_CR_RESET_Pos (0U) 1945 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1946 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 1947 1948 /******************************************************************************/ 1949 /* */ 1950 /* Digital to Analog Converter (DAC) */ 1951 /* */ 1952 /******************************************************************************/ 1953 1954 /******************** Bit definition for DAC_CR register ********************/ 1955 #define DAC_CR_EN1_Pos (0U) 1956 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1957 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 1958 #define DAC_CR_BOFF1_Pos (1U) 1959 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 1960 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ 1961 #define DAC_CR_TEN1_Pos (2U) 1962 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 1963 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 1964 1965 #define DAC_CR_TSEL1_Pos (3U) 1966 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 1967 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 1968 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1969 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1970 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1971 1972 #define DAC_CR_WAVE1_Pos (6U) 1973 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 1974 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 1975 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 1976 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 1977 1978 #define DAC_CR_MAMP1_Pos (8U) 1979 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 1980 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 1981 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 1982 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 1983 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 1984 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 1985 1986 #define DAC_CR_DMAEN1_Pos (12U) 1987 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1988 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 1989 #define DAC_CR_DMAUDRIE1_Pos (13U) 1990 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1991 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */ 1992 #define DAC_CR_EN2_Pos (16U) 1993 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 1994 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 1995 #define DAC_CR_BOFF2_Pos (17U) 1996 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 1997 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ 1998 #define DAC_CR_TEN2_Pos (18U) 1999 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 2000 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 2001 2002 #define DAC_CR_TSEL2_Pos (19U) 2003 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 2004 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 2005 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 2006 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 2007 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 2008 2009 #define DAC_CR_WAVE2_Pos (22U) 2010 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 2011 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 2012 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 2013 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 2014 2015 #define DAC_CR_MAMP2_Pos (24U) 2016 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 2017 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 2018 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 2019 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 2020 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 2021 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 2022 2023 #define DAC_CR_DMAEN2_Pos (28U) 2024 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 2025 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 2026 #define DAC_CR_DMAUDRIE2_Pos (29U) 2027 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 2028 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */ 2029 /***************** Bit definition for DAC_SWTRIGR register ******************/ 2030 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 2031 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 2032 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 2033 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 2034 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 2035 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 2036 2037 /***************** Bit definition for DAC_DHR12R1 register ******************/ 2038 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 2039 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 2040 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2041 2042 /***************** Bit definition for DAC_DHR12L1 register ******************/ 2043 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 2044 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2045 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2046 2047 /****************** Bit definition for DAC_DHR8R1 register ******************/ 2048 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 2049 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 2050 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2051 2052 /***************** Bit definition for DAC_DHR12R2 register ******************/ 2053 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 2054 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 2055 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2056 2057 /***************** Bit definition for DAC_DHR12L2 register ******************/ 2058 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 2059 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 2060 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2061 2062 /****************** Bit definition for DAC_DHR8R2 register ******************/ 2063 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 2064 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 2065 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2066 2067 /***************** Bit definition for DAC_DHR12RD register ******************/ 2068 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 2069 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 2070 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2071 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 2072 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 2073 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2074 2075 /***************** Bit definition for DAC_DHR12LD register ******************/ 2076 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 2077 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2078 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2079 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 2080 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 2081 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2082 2083 /****************** Bit definition for DAC_DHR8RD register ******************/ 2084 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 2085 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 2086 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2087 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 2088 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 2089 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2090 2091 /******************* Bit definition for DAC_DOR1 register *******************/ 2092 #define DAC_DOR1_DACC1DOR_Pos (0U) 2093 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 2094 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 2095 2096 /******************* Bit definition for DAC_DOR2 register *******************/ 2097 #define DAC_DOR2_DACC2DOR_Pos (0U) 2098 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 2099 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 2100 2101 /******************** Bit definition for DAC_SR register ********************/ 2102 #define DAC_SR_DMAUDR1_Pos (13U) 2103 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 2104 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 2105 #define DAC_SR_DMAUDR2_Pos (29U) 2106 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 2107 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 2108 2109 /******************************************************************************/ 2110 /* */ 2111 /* Debug MCU (DBGMCU) */ 2112 /* */ 2113 /******************************************************************************/ 2114 2115 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 2116 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 2117 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 2118 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 2119 2120 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 2121 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 2122 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 2123 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 2124 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 2125 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 2126 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 2127 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 2128 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 2129 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 2130 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 2131 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 2132 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 2133 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 2134 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 2135 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 2136 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 2137 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 2138 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 2139 2140 /****************** Bit definition for DBGMCU_CR register *******************/ 2141 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 2142 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 2143 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 2144 #define DBGMCU_CR_DBG_STOP_Pos (1U) 2145 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 2146 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 2147 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 2148 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 2149 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 2150 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 2151 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 2152 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 2153 2154 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 2155 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 2156 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 2157 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 2158 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 2159 2160 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 2161 2162 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 2163 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 2164 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 2165 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 2166 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 2167 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 2168 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 2169 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ 2170 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 2171 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) 2172 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ 2173 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ 2174 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 2175 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 2176 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 2177 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 2178 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 2179 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 2180 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 2181 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 2182 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */ 2183 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 2184 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 2185 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 2186 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 2187 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 2188 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 2189 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 2190 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 2191 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2192 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 2193 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 2194 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2195 2196 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 2197 2198 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) 2199 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */ 2200 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */ 2201 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) 2202 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */ 2203 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */ 2204 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) 2205 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */ 2206 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */ 2207 2208 /******************************************************************************/ 2209 /* */ 2210 /* DMA Controller (DMA) */ 2211 /* */ 2212 /******************************************************************************/ 2213 2214 /******************* Bit definition for DMA_ISR register ********************/ 2215 #define DMA_ISR_GIF1_Pos (0U) 2216 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2217 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2218 #define DMA_ISR_TCIF1_Pos (1U) 2219 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2220 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2221 #define DMA_ISR_HTIF1_Pos (2U) 2222 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2223 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2224 #define DMA_ISR_TEIF1_Pos (3U) 2225 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2226 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2227 #define DMA_ISR_GIF2_Pos (4U) 2228 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2229 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2230 #define DMA_ISR_TCIF2_Pos (5U) 2231 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2232 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2233 #define DMA_ISR_HTIF2_Pos (6U) 2234 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2235 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2236 #define DMA_ISR_TEIF2_Pos (7U) 2237 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2238 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2239 #define DMA_ISR_GIF3_Pos (8U) 2240 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2241 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2242 #define DMA_ISR_TCIF3_Pos (9U) 2243 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2244 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2245 #define DMA_ISR_HTIF3_Pos (10U) 2246 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2247 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2248 #define DMA_ISR_TEIF3_Pos (11U) 2249 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2250 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2251 #define DMA_ISR_GIF4_Pos (12U) 2252 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2253 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2254 #define DMA_ISR_TCIF4_Pos (13U) 2255 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2256 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2257 #define DMA_ISR_HTIF4_Pos (14U) 2258 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2259 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2260 #define DMA_ISR_TEIF4_Pos (15U) 2261 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2262 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2263 #define DMA_ISR_GIF5_Pos (16U) 2264 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2265 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2266 #define DMA_ISR_TCIF5_Pos (17U) 2267 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2268 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2269 #define DMA_ISR_HTIF5_Pos (18U) 2270 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2271 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2272 #define DMA_ISR_TEIF5_Pos (19U) 2273 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2274 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2275 #define DMA_ISR_GIF6_Pos (20U) 2276 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2277 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2278 #define DMA_ISR_TCIF6_Pos (21U) 2279 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2280 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2281 #define DMA_ISR_HTIF6_Pos (22U) 2282 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2283 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2284 #define DMA_ISR_TEIF6_Pos (23U) 2285 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2286 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2287 #define DMA_ISR_GIF7_Pos (24U) 2288 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2289 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2290 #define DMA_ISR_TCIF7_Pos (25U) 2291 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2292 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2293 #define DMA_ISR_HTIF7_Pos (26U) 2294 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2295 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2296 #define DMA_ISR_TEIF7_Pos (27U) 2297 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2298 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2299 2300 /******************* Bit definition for DMA_IFCR register *******************/ 2301 #define DMA_IFCR_CGIF1_Pos (0U) 2302 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2303 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2304 #define DMA_IFCR_CTCIF1_Pos (1U) 2305 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2306 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2307 #define DMA_IFCR_CHTIF1_Pos (2U) 2308 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2309 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2310 #define DMA_IFCR_CTEIF1_Pos (3U) 2311 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2312 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2313 #define DMA_IFCR_CGIF2_Pos (4U) 2314 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2315 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2316 #define DMA_IFCR_CTCIF2_Pos (5U) 2317 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2318 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2319 #define DMA_IFCR_CHTIF2_Pos (6U) 2320 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2321 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2322 #define DMA_IFCR_CTEIF2_Pos (7U) 2323 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2324 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2325 #define DMA_IFCR_CGIF3_Pos (8U) 2326 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2327 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2328 #define DMA_IFCR_CTCIF3_Pos (9U) 2329 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2330 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2331 #define DMA_IFCR_CHTIF3_Pos (10U) 2332 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2333 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2334 #define DMA_IFCR_CTEIF3_Pos (11U) 2335 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2336 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2337 #define DMA_IFCR_CGIF4_Pos (12U) 2338 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2339 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2340 #define DMA_IFCR_CTCIF4_Pos (13U) 2341 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2342 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2343 #define DMA_IFCR_CHTIF4_Pos (14U) 2344 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2345 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2346 #define DMA_IFCR_CTEIF4_Pos (15U) 2347 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2348 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2349 #define DMA_IFCR_CGIF5_Pos (16U) 2350 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2351 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2352 #define DMA_IFCR_CTCIF5_Pos (17U) 2353 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2354 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2355 #define DMA_IFCR_CHTIF5_Pos (18U) 2356 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2357 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2358 #define DMA_IFCR_CTEIF5_Pos (19U) 2359 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2360 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2361 #define DMA_IFCR_CGIF6_Pos (20U) 2362 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2363 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2364 #define DMA_IFCR_CTCIF6_Pos (21U) 2365 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2366 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2367 #define DMA_IFCR_CHTIF6_Pos (22U) 2368 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2369 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2370 #define DMA_IFCR_CTEIF6_Pos (23U) 2371 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2372 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2373 #define DMA_IFCR_CGIF7_Pos (24U) 2374 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2375 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2376 #define DMA_IFCR_CTCIF7_Pos (25U) 2377 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2378 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2379 #define DMA_IFCR_CHTIF7_Pos (26U) 2380 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2381 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2382 #define DMA_IFCR_CTEIF7_Pos (27U) 2383 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2384 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2385 2386 /******************* Bit definition for DMA_CCR register *******************/ 2387 #define DMA_CCR_EN_Pos (0U) 2388 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2389 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/ 2390 #define DMA_CCR_TCIE_Pos (1U) 2391 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2392 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2393 #define DMA_CCR_HTIE_Pos (2U) 2394 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2395 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2396 #define DMA_CCR_TEIE_Pos (3U) 2397 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2398 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2399 #define DMA_CCR_DIR_Pos (4U) 2400 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2401 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2402 #define DMA_CCR_CIRC_Pos (5U) 2403 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2404 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2405 #define DMA_CCR_PINC_Pos (6U) 2406 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2407 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2408 #define DMA_CCR_MINC_Pos (7U) 2409 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2410 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2411 2412 #define DMA_CCR_PSIZE_Pos (8U) 2413 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2414 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2415 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2416 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2417 2418 #define DMA_CCR_MSIZE_Pos (10U) 2419 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2420 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2421 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2422 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2423 2424 #define DMA_CCR_PL_Pos (12U) 2425 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2426 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 2427 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2428 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2429 2430 #define DMA_CCR_MEM2MEM_Pos (14U) 2431 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2432 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2433 2434 /****************** Bit definition generic for DMA_CNDTR register *******************/ 2435 #define DMA_CNDTR_NDT_Pos (0U) 2436 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2437 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2438 2439 /****************** Bit definition for DMA_CNDTR1 register ******************/ 2440 #define DMA_CNDTR1_NDT_Pos (0U) 2441 #define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */ 2442 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */ 2443 2444 /****************** Bit definition for DMA_CNDTR2 register ******************/ 2445 #define DMA_CNDTR2_NDT_Pos (0U) 2446 #define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */ 2447 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */ 2448 2449 /****************** Bit definition for DMA_CNDTR3 register ******************/ 2450 #define DMA_CNDTR3_NDT_Pos (0U) 2451 #define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */ 2452 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */ 2453 2454 /****************** Bit definition for DMA_CNDTR4 register ******************/ 2455 #define DMA_CNDTR4_NDT_Pos (0U) 2456 #define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */ 2457 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */ 2458 2459 /****************** Bit definition for DMA_CNDTR5 register ******************/ 2460 #define DMA_CNDTR5_NDT_Pos (0U) 2461 #define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */ 2462 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */ 2463 2464 /****************** Bit definition for DMA_CNDTR6 register ******************/ 2465 #define DMA_CNDTR6_NDT_Pos (0U) 2466 #define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */ 2467 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */ 2468 2469 /****************** Bit definition for DMA_CNDTR7 register ******************/ 2470 #define DMA_CNDTR7_NDT_Pos (0U) 2471 #define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */ 2472 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */ 2473 2474 /****************** Bit definition generic for DMA_CPAR register ********************/ 2475 #define DMA_CPAR_PA_Pos (0U) 2476 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2477 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2478 2479 /****************** Bit definition for DMA_CPAR1 register *******************/ 2480 #define DMA_CPAR1_PA_Pos (0U) 2481 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */ 2482 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */ 2483 2484 /****************** Bit definition for DMA_CPAR2 register *******************/ 2485 #define DMA_CPAR2_PA_Pos (0U) 2486 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */ 2487 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */ 2488 2489 /****************** Bit definition for DMA_CPAR3 register *******************/ 2490 #define DMA_CPAR3_PA_Pos (0U) 2491 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */ 2492 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */ 2493 2494 2495 /****************** Bit definition for DMA_CPAR4 register *******************/ 2496 #define DMA_CPAR4_PA_Pos (0U) 2497 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */ 2498 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */ 2499 2500 /****************** Bit definition for DMA_CPAR5 register *******************/ 2501 #define DMA_CPAR5_PA_Pos (0U) 2502 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */ 2503 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */ 2504 2505 /****************** Bit definition for DMA_CPAR6 register *******************/ 2506 #define DMA_CPAR6_PA_Pos (0U) 2507 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */ 2508 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */ 2509 2510 2511 /****************** Bit definition for DMA_CPAR7 register *******************/ 2512 #define DMA_CPAR7_PA_Pos (0U) 2513 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */ 2514 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */ 2515 2516 /****************** Bit definition generic for DMA_CMAR register ********************/ 2517 #define DMA_CMAR_MA_Pos (0U) 2518 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2519 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2520 2521 /****************** Bit definition for DMA_CMAR1 register *******************/ 2522 #define DMA_CMAR1_MA_Pos (0U) 2523 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */ 2524 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */ 2525 2526 /****************** Bit definition for DMA_CMAR2 register *******************/ 2527 #define DMA_CMAR2_MA_Pos (0U) 2528 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */ 2529 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */ 2530 2531 /****************** Bit definition for DMA_CMAR3 register *******************/ 2532 #define DMA_CMAR3_MA_Pos (0U) 2533 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */ 2534 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */ 2535 2536 2537 /****************** Bit definition for DMA_CMAR4 register *******************/ 2538 #define DMA_CMAR4_MA_Pos (0U) 2539 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */ 2540 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */ 2541 2542 /****************** Bit definition for DMA_CMAR5 register *******************/ 2543 #define DMA_CMAR5_MA_Pos (0U) 2544 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */ 2545 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */ 2546 2547 /****************** Bit definition for DMA_CMAR6 register *******************/ 2548 #define DMA_CMAR6_MA_Pos (0U) 2549 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */ 2550 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */ 2551 2552 /****************** Bit definition for DMA_CMAR7 register *******************/ 2553 #define DMA_CMAR7_MA_Pos (0U) 2554 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */ 2555 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */ 2556 2557 /******************************************************************************/ 2558 /* */ 2559 /* External Interrupt/Event Controller (EXTI) */ 2560 /* */ 2561 /******************************************************************************/ 2562 2563 /******************* Bit definition for EXTI_IMR register *******************/ 2564 #define EXTI_IMR_MR0_Pos (0U) 2565 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2566 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2567 #define EXTI_IMR_MR1_Pos (1U) 2568 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2569 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2570 #define EXTI_IMR_MR2_Pos (2U) 2571 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2572 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2573 #define EXTI_IMR_MR3_Pos (3U) 2574 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2575 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2576 #define EXTI_IMR_MR4_Pos (4U) 2577 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2578 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2579 #define EXTI_IMR_MR5_Pos (5U) 2580 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2581 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2582 #define EXTI_IMR_MR6_Pos (6U) 2583 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2584 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2585 #define EXTI_IMR_MR7_Pos (7U) 2586 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2587 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2588 #define EXTI_IMR_MR8_Pos (8U) 2589 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2590 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2591 #define EXTI_IMR_MR9_Pos (9U) 2592 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2593 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2594 #define EXTI_IMR_MR10_Pos (10U) 2595 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2596 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2597 #define EXTI_IMR_MR11_Pos (11U) 2598 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2599 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2600 #define EXTI_IMR_MR12_Pos (12U) 2601 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2602 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2603 #define EXTI_IMR_MR13_Pos (13U) 2604 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2605 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2606 #define EXTI_IMR_MR14_Pos (14U) 2607 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2608 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2609 #define EXTI_IMR_MR15_Pos (15U) 2610 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2611 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2612 #define EXTI_IMR_MR16_Pos (16U) 2613 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2614 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2615 #define EXTI_IMR_MR17_Pos (17U) 2616 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2617 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2618 #define EXTI_IMR_MR18_Pos (18U) 2619 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 2620 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 2621 #define EXTI_IMR_MR19_Pos (19U) 2622 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 2623 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 2624 #define EXTI_IMR_MR20_Pos (20U) 2625 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 2626 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 2627 #define EXTI_IMR_MR21_Pos (21U) 2628 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 2629 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 2630 #define EXTI_IMR_MR22_Pos (22U) 2631 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 2632 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 2633 #define EXTI_IMR_MR23_Pos (23U) 2634 #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 2635 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 2636 2637 /* References Defines */ 2638 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2639 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2640 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2641 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2642 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2643 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2644 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2645 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2646 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2647 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2648 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2649 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2650 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2651 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2652 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2653 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2654 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2655 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2656 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2657 #define EXTI_IMR_IM19 EXTI_IMR_MR19 2658 #define EXTI_IMR_IM20 EXTI_IMR_MR20 2659 #define EXTI_IMR_IM21 EXTI_IMR_MR21 2660 #define EXTI_IMR_IM22 EXTI_IMR_MR22 2661 /* Category 3, 4 & 5 */ 2662 #define EXTI_IMR_IM23 EXTI_IMR_MR23 2663 #define EXTI_IMR_IM_Pos (0U) 2664 #define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */ 2665 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 2666 2667 /******************* Bit definition for EXTI_EMR register *******************/ 2668 #define EXTI_EMR_MR0_Pos (0U) 2669 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2670 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2671 #define EXTI_EMR_MR1_Pos (1U) 2672 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2673 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2674 #define EXTI_EMR_MR2_Pos (2U) 2675 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2676 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2677 #define EXTI_EMR_MR3_Pos (3U) 2678 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2679 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2680 #define EXTI_EMR_MR4_Pos (4U) 2681 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2682 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2683 #define EXTI_EMR_MR5_Pos (5U) 2684 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2685 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2686 #define EXTI_EMR_MR6_Pos (6U) 2687 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2688 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2689 #define EXTI_EMR_MR7_Pos (7U) 2690 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2691 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2692 #define EXTI_EMR_MR8_Pos (8U) 2693 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2694 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2695 #define EXTI_EMR_MR9_Pos (9U) 2696 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2697 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2698 #define EXTI_EMR_MR10_Pos (10U) 2699 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2700 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2701 #define EXTI_EMR_MR11_Pos (11U) 2702 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2703 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2704 #define EXTI_EMR_MR12_Pos (12U) 2705 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2706 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2707 #define EXTI_EMR_MR13_Pos (13U) 2708 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2709 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2710 #define EXTI_EMR_MR14_Pos (14U) 2711 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2712 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2713 #define EXTI_EMR_MR15_Pos (15U) 2714 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2715 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2716 #define EXTI_EMR_MR16_Pos (16U) 2717 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2718 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2719 #define EXTI_EMR_MR17_Pos (17U) 2720 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2721 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2722 #define EXTI_EMR_MR18_Pos (18U) 2723 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 2724 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 2725 #define EXTI_EMR_MR19_Pos (19U) 2726 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 2727 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 2728 #define EXTI_EMR_MR20_Pos (20U) 2729 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 2730 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 2731 #define EXTI_EMR_MR21_Pos (21U) 2732 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 2733 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 2734 #define EXTI_EMR_MR22_Pos (22U) 2735 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 2736 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 2737 #define EXTI_EMR_MR23_Pos (23U) 2738 #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 2739 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 2740 2741 /* References Defines */ 2742 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2743 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2744 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2745 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2746 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2747 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2748 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2749 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2750 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2751 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2752 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2753 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2754 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2755 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2756 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2757 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2758 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2759 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2760 #define EXTI_EMR_EM18 EXTI_EMR_MR18 2761 #define EXTI_EMR_EM19 EXTI_EMR_MR19 2762 #define EXTI_EMR_EM20 EXTI_EMR_MR20 2763 #define EXTI_EMR_EM21 EXTI_EMR_MR21 2764 #define EXTI_EMR_EM22 EXTI_EMR_MR22 2765 #define EXTI_EMR_EM23 EXTI_EMR_MR23 2766 2767 /****************** Bit definition for EXTI_RTSR register *******************/ 2768 #define EXTI_RTSR_TR0_Pos (0U) 2769 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2770 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2771 #define EXTI_RTSR_TR1_Pos (1U) 2772 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2773 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2774 #define EXTI_RTSR_TR2_Pos (2U) 2775 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2776 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2777 #define EXTI_RTSR_TR3_Pos (3U) 2778 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2779 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2780 #define EXTI_RTSR_TR4_Pos (4U) 2781 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2782 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2783 #define EXTI_RTSR_TR5_Pos (5U) 2784 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2785 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2786 #define EXTI_RTSR_TR6_Pos (6U) 2787 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2788 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2789 #define EXTI_RTSR_TR7_Pos (7U) 2790 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2791 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2792 #define EXTI_RTSR_TR8_Pos (8U) 2793 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2794 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2795 #define EXTI_RTSR_TR9_Pos (9U) 2796 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2797 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2798 #define EXTI_RTSR_TR10_Pos (10U) 2799 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2800 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2801 #define EXTI_RTSR_TR11_Pos (11U) 2802 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2803 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2804 #define EXTI_RTSR_TR12_Pos (12U) 2805 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2806 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2807 #define EXTI_RTSR_TR13_Pos (13U) 2808 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2809 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2810 #define EXTI_RTSR_TR14_Pos (14U) 2811 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2812 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2813 #define EXTI_RTSR_TR15_Pos (15U) 2814 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2815 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2816 #define EXTI_RTSR_TR16_Pos (16U) 2817 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2818 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2819 #define EXTI_RTSR_TR17_Pos (17U) 2820 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2821 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2822 #define EXTI_RTSR_TR18_Pos (18U) 2823 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 2824 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2825 #define EXTI_RTSR_TR19_Pos (19U) 2826 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 2827 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 2828 #define EXTI_RTSR_TR20_Pos (20U) 2829 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 2830 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 2831 #define EXTI_RTSR_TR21_Pos (21U) 2832 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 2833 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 2834 #define EXTI_RTSR_TR22_Pos (22U) 2835 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 2836 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 2837 #define EXTI_RTSR_TR23_Pos (23U) 2838 #define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */ 2839 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */ 2840 2841 /* References Defines */ 2842 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2843 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2844 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2845 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2846 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2847 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2848 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2849 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2850 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2851 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2852 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2853 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2854 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2855 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2856 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2857 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2858 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2859 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2860 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 2861 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 2862 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 2863 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 2864 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 2865 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 2866 2867 /****************** Bit definition for EXTI_FTSR register *******************/ 2868 #define EXTI_FTSR_TR0_Pos (0U) 2869 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2870 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2871 #define EXTI_FTSR_TR1_Pos (1U) 2872 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2873 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2874 #define EXTI_FTSR_TR2_Pos (2U) 2875 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2876 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2877 #define EXTI_FTSR_TR3_Pos (3U) 2878 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2879 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2880 #define EXTI_FTSR_TR4_Pos (4U) 2881 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2882 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2883 #define EXTI_FTSR_TR5_Pos (5U) 2884 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2885 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2886 #define EXTI_FTSR_TR6_Pos (6U) 2887 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2888 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2889 #define EXTI_FTSR_TR7_Pos (7U) 2890 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2891 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2892 #define EXTI_FTSR_TR8_Pos (8U) 2893 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2894 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2895 #define EXTI_FTSR_TR9_Pos (9U) 2896 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2897 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2898 #define EXTI_FTSR_TR10_Pos (10U) 2899 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2900 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2901 #define EXTI_FTSR_TR11_Pos (11U) 2902 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2903 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2904 #define EXTI_FTSR_TR12_Pos (12U) 2905 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2906 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2907 #define EXTI_FTSR_TR13_Pos (13U) 2908 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2909 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2910 #define EXTI_FTSR_TR14_Pos (14U) 2911 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2912 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2913 #define EXTI_FTSR_TR15_Pos (15U) 2914 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2915 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2916 #define EXTI_FTSR_TR16_Pos (16U) 2917 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2918 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2919 #define EXTI_FTSR_TR17_Pos (17U) 2920 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2921 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2922 #define EXTI_FTSR_TR18_Pos (18U) 2923 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 2924 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2925 #define EXTI_FTSR_TR19_Pos (19U) 2926 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 2927 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 2928 #define EXTI_FTSR_TR20_Pos (20U) 2929 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 2930 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 2931 #define EXTI_FTSR_TR21_Pos (21U) 2932 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 2933 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 2934 #define EXTI_FTSR_TR22_Pos (22U) 2935 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 2936 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 2937 #define EXTI_FTSR_TR23_Pos (23U) 2938 #define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */ 2939 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */ 2940 2941 /* References Defines */ 2942 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2943 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2944 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2945 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2946 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2947 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2948 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2949 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2950 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2951 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2952 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2953 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2954 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2955 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2956 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2957 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2958 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2959 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2960 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 2961 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 2962 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 2963 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 2964 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 2965 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 2966 2967 /****************** Bit definition for EXTI_SWIER register ******************/ 2968 #define EXTI_SWIER_SWIER0_Pos (0U) 2969 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2970 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2971 #define EXTI_SWIER_SWIER1_Pos (1U) 2972 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2973 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2974 #define EXTI_SWIER_SWIER2_Pos (2U) 2975 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2976 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2977 #define EXTI_SWIER_SWIER3_Pos (3U) 2978 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2979 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2980 #define EXTI_SWIER_SWIER4_Pos (4U) 2981 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2982 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2983 #define EXTI_SWIER_SWIER5_Pos (5U) 2984 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2985 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2986 #define EXTI_SWIER_SWIER6_Pos (6U) 2987 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2988 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2989 #define EXTI_SWIER_SWIER7_Pos (7U) 2990 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2991 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2992 #define EXTI_SWIER_SWIER8_Pos (8U) 2993 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2994 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2995 #define EXTI_SWIER_SWIER9_Pos (9U) 2996 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2997 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2998 #define EXTI_SWIER_SWIER10_Pos (10U) 2999 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 3000 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 3001 #define EXTI_SWIER_SWIER11_Pos (11U) 3002 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 3003 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 3004 #define EXTI_SWIER_SWIER12_Pos (12U) 3005 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 3006 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 3007 #define EXTI_SWIER_SWIER13_Pos (13U) 3008 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 3009 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 3010 #define EXTI_SWIER_SWIER14_Pos (14U) 3011 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 3012 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 3013 #define EXTI_SWIER_SWIER15_Pos (15U) 3014 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 3015 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 3016 #define EXTI_SWIER_SWIER16_Pos (16U) 3017 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 3018 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 3019 #define EXTI_SWIER_SWIER17_Pos (17U) 3020 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 3021 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 3022 #define EXTI_SWIER_SWIER18_Pos (18U) 3023 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 3024 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 3025 #define EXTI_SWIER_SWIER19_Pos (19U) 3026 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 3027 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 3028 #define EXTI_SWIER_SWIER20_Pos (20U) 3029 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 3030 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 3031 #define EXTI_SWIER_SWIER21_Pos (21U) 3032 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 3033 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 3034 #define EXTI_SWIER_SWIER22_Pos (22U) 3035 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 3036 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 3037 #define EXTI_SWIER_SWIER23_Pos (23U) 3038 #define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */ 3039 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */ 3040 3041 /* References Defines */ 3042 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 3043 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 3044 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 3045 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 3046 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 3047 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 3048 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 3049 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 3050 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 3051 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 3052 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 3053 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 3054 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 3055 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 3056 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 3057 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 3058 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 3059 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 3060 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 3061 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 3062 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 3063 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 3064 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 3065 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 3066 3067 /******************* Bit definition for EXTI_PR register ********************/ 3068 #define EXTI_PR_PR0_Pos (0U) 3069 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 3070 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 3071 #define EXTI_PR_PR1_Pos (1U) 3072 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 3073 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 3074 #define EXTI_PR_PR2_Pos (2U) 3075 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 3076 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 3077 #define EXTI_PR_PR3_Pos (3U) 3078 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 3079 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 3080 #define EXTI_PR_PR4_Pos (4U) 3081 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 3082 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 3083 #define EXTI_PR_PR5_Pos (5U) 3084 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 3085 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 3086 #define EXTI_PR_PR6_Pos (6U) 3087 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 3088 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 3089 #define EXTI_PR_PR7_Pos (7U) 3090 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 3091 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 3092 #define EXTI_PR_PR8_Pos (8U) 3093 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 3094 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 3095 #define EXTI_PR_PR9_Pos (9U) 3096 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 3097 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 3098 #define EXTI_PR_PR10_Pos (10U) 3099 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 3100 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 3101 #define EXTI_PR_PR11_Pos (11U) 3102 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 3103 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 3104 #define EXTI_PR_PR12_Pos (12U) 3105 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3106 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3107 #define EXTI_PR_PR13_Pos (13U) 3108 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3109 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3110 #define EXTI_PR_PR14_Pos (14U) 3111 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3112 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3113 #define EXTI_PR_PR15_Pos (15U) 3114 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3115 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3116 #define EXTI_PR_PR16_Pos (16U) 3117 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3118 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3119 #define EXTI_PR_PR17_Pos (17U) 3120 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3121 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3122 #define EXTI_PR_PR18_Pos (18U) 3123 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 3124 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 3125 #define EXTI_PR_PR19_Pos (19U) 3126 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 3127 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 3128 #define EXTI_PR_PR20_Pos (20U) 3129 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 3130 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 3131 #define EXTI_PR_PR21_Pos (21U) 3132 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 3133 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ 3134 #define EXTI_PR_PR22_Pos (22U) 3135 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 3136 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 3137 #define EXTI_PR_PR23_Pos (23U) 3138 #define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */ 3139 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */ 3140 3141 /* References Defines */ 3142 #define EXTI_PR_PIF0 EXTI_PR_PR0 3143 #define EXTI_PR_PIF1 EXTI_PR_PR1 3144 #define EXTI_PR_PIF2 EXTI_PR_PR2 3145 #define EXTI_PR_PIF3 EXTI_PR_PR3 3146 #define EXTI_PR_PIF4 EXTI_PR_PR4 3147 #define EXTI_PR_PIF5 EXTI_PR_PR5 3148 #define EXTI_PR_PIF6 EXTI_PR_PR6 3149 #define EXTI_PR_PIF7 EXTI_PR_PR7 3150 #define EXTI_PR_PIF8 EXTI_PR_PR8 3151 #define EXTI_PR_PIF9 EXTI_PR_PR9 3152 #define EXTI_PR_PIF10 EXTI_PR_PR10 3153 #define EXTI_PR_PIF11 EXTI_PR_PR11 3154 #define EXTI_PR_PIF12 EXTI_PR_PR12 3155 #define EXTI_PR_PIF13 EXTI_PR_PR13 3156 #define EXTI_PR_PIF14 EXTI_PR_PR14 3157 #define EXTI_PR_PIF15 EXTI_PR_PR15 3158 #define EXTI_PR_PIF16 EXTI_PR_PR16 3159 #define EXTI_PR_PIF17 EXTI_PR_PR17 3160 #define EXTI_PR_PIF18 EXTI_PR_PR18 3161 #define EXTI_PR_PIF19 EXTI_PR_PR19 3162 #define EXTI_PR_PIF20 EXTI_PR_PR20 3163 #define EXTI_PR_PIF21 EXTI_PR_PR21 3164 #define EXTI_PR_PIF22 EXTI_PR_PR22 3165 #define EXTI_PR_PIF23 EXTI_PR_PR23 3166 3167 /******************************************************************************/ 3168 /* */ 3169 /* FLASH, DATA EEPROM and Option Bytes Registers */ 3170 /* (FLASH, DATA_EEPROM, OB) */ 3171 /* */ 3172 /******************************************************************************/ 3173 /* 3174 * @brief Specific device feature definitions (not present on all devices in the STM32L1 serie) 3175 */ 3176 #define FLASH_CUT4 3177 3178 /******************* Bit definition for FLASH_ACR register ******************/ 3179 #define FLASH_ACR_LATENCY_Pos (0U) 3180 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3181 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 3182 #define FLASH_ACR_PRFTEN_Pos (1U) 3183 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 3184 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 3185 #define FLASH_ACR_ACC64_Pos (2U) 3186 #define FLASH_ACR_ACC64_Msk (0x1UL << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */ 3187 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */ 3188 #define FLASH_ACR_SLEEP_PD_Pos (3U) 3189 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 3190 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 3191 #define FLASH_ACR_RUN_PD_Pos (4U) 3192 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 3193 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 3194 3195 /******************* Bit definition for FLASH_PECR register ******************/ 3196 #define FLASH_PECR_PELOCK_Pos (0U) 3197 #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 3198 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 3199 #define FLASH_PECR_PRGLOCK_Pos (1U) 3200 #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 3201 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 3202 #define FLASH_PECR_OPTLOCK_Pos (2U) 3203 #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 3204 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 3205 #define FLASH_PECR_PROG_Pos (3U) 3206 #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 3207 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 3208 #define FLASH_PECR_DATA_Pos (4U) 3209 #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 3210 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 3211 #define FLASH_PECR_FTDW_Pos (8U) 3212 #define FLASH_PECR_FTDW_Msk (0x1UL << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */ 3213 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 3214 #define FLASH_PECR_ERASE_Pos (9U) 3215 #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 3216 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 3217 #define FLASH_PECR_FPRG_Pos (10U) 3218 #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 3219 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 3220 #define FLASH_PECR_PARALLBANK_Pos (15U) 3221 #define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ 3222 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ 3223 #define FLASH_PECR_EOPIE_Pos (16U) 3224 #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 3225 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 3226 #define FLASH_PECR_ERRIE_Pos (17U) 3227 #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 3228 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 3229 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 3230 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 3231 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 3232 3233 /****************** Bit definition for FLASH_PDKEYR register ******************/ 3234 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 3235 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 3236 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3237 3238 /****************** Bit definition for FLASH_PEKEYR register ******************/ 3239 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 3240 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 3241 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3242 3243 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 3244 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 3245 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 3246 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 3247 3248 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 3249 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 3250 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 3251 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 3252 3253 /****************** Bit definition for FLASH_SR register *******************/ 3254 #define FLASH_SR_BSY_Pos (0U) 3255 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 3256 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 3257 #define FLASH_SR_EOP_Pos (1U) 3258 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 3259 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 3260 #define FLASH_SR_ENDHV_Pos (2U) 3261 #define FLASH_SR_ENDHV_Msk (0x1UL << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */ 3262 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */ 3263 #define FLASH_SR_READY_Pos (3U) 3264 #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 3265 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 3266 3267 #define FLASH_SR_WRPERR_Pos (8U) 3268 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 3269 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */ 3270 #define FLASH_SR_PGAERR_Pos (9U) 3271 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 3272 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 3273 #define FLASH_SR_SIZERR_Pos (10U) 3274 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 3275 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 3276 #define FLASH_SR_OPTVERR_Pos (11U) 3277 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 3278 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 3279 #define FLASH_SR_OPTVERRUSR_Pos (12U) 3280 #define FLASH_SR_OPTVERRUSR_Msk (0x1UL << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */ 3281 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */ 3282 3283 /****************** Bit definition for FLASH_OBR register *******************/ 3284 #define FLASH_OBR_RDPRT_Pos (0U) 3285 #define FLASH_OBR_RDPRT_Msk (0xFFUL << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */ 3286 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */ 3287 #define FLASH_OBR_BOR_LEV_Pos (16U) 3288 #define FLASH_OBR_BOR_LEV_Msk (0xFUL << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */ 3289 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 3290 #define FLASH_OBR_USER_Pos (20U) 3291 #define FLASH_OBR_USER_Msk (0xFUL << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */ 3292 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 3293 #define FLASH_OBR_IWDG_SW_Pos (20U) 3294 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */ 3295 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */ 3296 #define FLASH_OBR_nRST_STOP_Pos (21U) 3297 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */ 3298 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 3299 #define FLASH_OBR_nRST_STDBY_Pos (22U) 3300 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */ 3301 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 3302 #define FLASH_OBR_nRST_BFB2_Pos (23U) 3303 #define FLASH_OBR_nRST_BFB2_Msk (0x1UL << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */ 3304 #define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */ 3305 3306 /****************** Bit definition for FLASH_WRPR register ******************/ 3307 #define FLASH_WRPR1_WRP_Pos (0U) 3308 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */ 3309 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */ 3310 #define FLASH_WRPR2_WRP_Pos (0U) 3311 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */ 3312 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */ 3313 #define FLASH_WRPR3_WRP_Pos (0U) 3314 #define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */ 3315 #define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */ 3316 3317 /******************************************************************************/ 3318 /* */ 3319 /* Flexible Static Memory Controller */ 3320 /* */ 3321 /******************************************************************************/ 3322 /****************** Bit definition for FSMC_BCRx register (x=1..4) *******************/ 3323 #define FSMC_BCRx_MBKEN_Pos (0U) 3324 #define FSMC_BCRx_MBKEN_Msk (0x1UL << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */ 3325 #define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */ 3326 #define FSMC_BCRx_MUXEN_Pos (1U) 3327 #define FSMC_BCRx_MUXEN_Msk (0x1UL << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */ 3328 #define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */ 3329 3330 #define FSMC_BCRx_MTYP_Pos (2U) 3331 #define FSMC_BCRx_MTYP_Msk (0x3UL << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */ 3332 #define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */ 3333 #define FSMC_BCRx_MTYP_0 (0x1UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */ 3334 #define FSMC_BCRx_MTYP_1 (0x2UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */ 3335 3336 #define FSMC_BCRx_MWID_Pos (4U) 3337 #define FSMC_BCRx_MWID_Msk (0x3UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */ 3338 #define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */ 3339 #define FSMC_BCRx_MWID_0 (0x1UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */ 3340 #define FSMC_BCRx_MWID_1 (0x2UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */ 3341 3342 #define FSMC_BCRx_FACCEN_Pos (6U) 3343 #define FSMC_BCRx_FACCEN_Msk (0x1UL << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */ 3344 #define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */ 3345 #define FSMC_BCRx_BURSTEN_Pos (8U) 3346 #define FSMC_BCRx_BURSTEN_Msk (0x1UL << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */ 3347 #define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */ 3348 #define FSMC_BCRx_WAITPOL_Pos (9U) 3349 #define FSMC_BCRx_WAITPOL_Msk (0x1UL << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */ 3350 #define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */ 3351 #define FSMC_BCRx_WRAPMOD_Pos (10U) 3352 #define FSMC_BCRx_WRAPMOD_Msk (0x1UL << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */ 3353 #define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */ 3354 #define FSMC_BCRx_WAITCFG_Pos (11U) 3355 #define FSMC_BCRx_WAITCFG_Msk (0x1UL << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */ 3356 #define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */ 3357 #define FSMC_BCRx_WREN_Pos (12U) 3358 #define FSMC_BCRx_WREN_Msk (0x1UL << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */ 3359 #define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */ 3360 #define FSMC_BCRx_WAITEN_Pos (13U) 3361 #define FSMC_BCRx_WAITEN_Msk (0x1UL << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */ 3362 #define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */ 3363 #define FSMC_BCRx_EXTMOD_Pos (14U) 3364 #define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ 3365 #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ 3366 #define FSMC_BCRx_ASYNCWAIT_Pos (15U) 3367 #define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ 3368 #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ 3369 #define FSMC_BCRx_CPSIZE_Pos (16U) 3370 #define FSMC_BCRx_CPSIZE_Msk (0x7UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */ 3371 #define FSMC_BCRx_CPSIZE FSMC_BCRx_CPSIZE_Msk /*!< Cellular RAM page size */ 3372 #define FSMC_BCRx_CPSIZE_0 (0x1UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */ 3373 #define FSMC_BCRx_CPSIZE_1 (0x2UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */ 3374 #define FSMC_BCRx_CPSIZE_2 (0x4UL << FSMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */ 3375 #define FSMC_BCRx_CBURSTRW_Pos (19U) 3376 #define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ 3377 #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ 3378 3379 /****************** Bit definition for FSMC_BTRx register (x=1..4) ******************/ 3380 #define FSMC_BTRx_ADDSET_Pos (0U) 3381 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */ 3382 #define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 3383 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */ 3384 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */ 3385 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */ 3386 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */ 3387 3388 #define FSMC_BTRx_ADDHLD_Pos (4U) 3389 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 3390 #define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 3391 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */ 3392 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */ 3393 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */ 3394 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */ 3395 3396 #define FSMC_BTRx_DATAST_Pos (8U) 3397 #define FSMC_BTRx_DATAST_Msk (0xFFUL << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */ 3398 #define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ 3399 #define FSMC_BTRx_DATAST_0 (0x01UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */ 3400 #define FSMC_BTRx_DATAST_1 (0x02UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */ 3401 #define FSMC_BTRx_DATAST_2 (0x04UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */ 3402 #define FSMC_BTRx_DATAST_3 (0x08UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */ 3403 #define FSMC_BTRx_DATAST_4 (0x10UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */ 3404 #define FSMC_BTRx_DATAST_5 (0x20UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */ 3405 #define FSMC_BTRx_DATAST_6 (0x40UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */ 3406 #define FSMC_BTRx_DATAST_7 (0x80UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */ 3407 3408 #define FSMC_BTRx_BUSTURN_Pos (16U) 3409 #define FSMC_BTRx_BUSTURN_Msk (0xFUL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */ 3410 #define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ 3411 #define FSMC_BTRx_BUSTURN_0 (0x1UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */ 3412 #define FSMC_BTRx_BUSTURN_1 (0x2UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */ 3413 #define FSMC_BTRx_BUSTURN_2 (0x4UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */ 3414 #define FSMC_BTRx_BUSTURN_3 (0x8UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */ 3415 3416 #define FSMC_BTRx_CLKDIV_Pos (20U) 3417 #define FSMC_BTRx_CLKDIV_Msk (0xFUL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */ 3418 #define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */ 3419 #define FSMC_BTRx_CLKDIV_0 (0x1UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */ 3420 #define FSMC_BTRx_CLKDIV_1 (0x2UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */ 3421 #define FSMC_BTRx_CLKDIV_2 (0x4UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */ 3422 #define FSMC_BTRx_CLKDIV_3 (0x8UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */ 3423 3424 #define FSMC_BTRx_DATLAT_Pos (24U) 3425 #define FSMC_BTRx_DATLAT_Msk (0xFUL << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */ 3426 #define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */ 3427 #define FSMC_BTRx_DATLAT_0 (0x1UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */ 3428 #define FSMC_BTRx_DATLAT_1 (0x2UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */ 3429 #define FSMC_BTRx_DATLAT_2 (0x4UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */ 3430 #define FSMC_BTRx_DATLAT_3 (0x8UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */ 3431 3432 #define FSMC_BTRx_ACCMOD_Pos (28U) 3433 #define FSMC_BTRx_ACCMOD_Msk (0x3UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */ 3434 #define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 3435 #define FSMC_BTRx_ACCMOD_0 (0x1UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */ 3436 #define FSMC_BTRx_ACCMOD_1 (0x2UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */ 3437 3438 /****************** Bit definition for FSMC_BWTRx register (x=1..4) ******************/ 3439 #define FSMC_BWTRx_ADDSET_Pos (0U) 3440 #define FSMC_BWTRx_ADDSET_Msk (0xFUL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */ 3441 #define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 3442 #define FSMC_BWTRx_ADDSET_0 (0x1UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */ 3443 #define FSMC_BWTRx_ADDSET_1 (0x2UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */ 3444 #define FSMC_BWTRx_ADDSET_2 (0x4UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */ 3445 #define FSMC_BWTRx_ADDSET_3 (0x8UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */ 3446 3447 #define FSMC_BWTRx_ADDHLD_Pos (4U) 3448 #define FSMC_BWTRx_ADDHLD_Msk (0xFUL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 3449 #define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 3450 #define FSMC_BWTRx_ADDHLD_0 (0x1UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */ 3451 #define FSMC_BWTRx_ADDHLD_1 (0x2UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */ 3452 #define FSMC_BWTRx_ADDHLD_2 (0x4UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */ 3453 #define FSMC_BWTRx_ADDHLD_3 (0x8UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */ 3454 3455 #define FSMC_BWTRx_DATAST_Pos (8U) 3456 #define FSMC_BWTRx_DATAST_Msk (0xFFUL << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */ 3457 #define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ 3458 #define FSMC_BWTRx_DATAST_0 (0x01UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */ 3459 #define FSMC_BWTRx_DATAST_1 (0x02UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */ 3460 #define FSMC_BWTRx_DATAST_2 (0x04UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */ 3461 #define FSMC_BWTRx_DATAST_3 (0x08UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */ 3462 #define FSMC_BWTRx_DATAST_4 (0x10UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */ 3463 #define FSMC_BWTRx_DATAST_5 (0x20UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */ 3464 #define FSMC_BWTRx_DATAST_6 (0x40UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */ 3465 #define FSMC_BWTRx_DATAST_7 (0x80UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */ 3466 3467 #define FSMC_BWTRx_BUSTURN_Pos (16U) 3468 #define FSMC_BWTRx_BUSTURN_Msk (0xFUL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */ 3469 #define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ 3470 #define FSMC_BWTRx_BUSTURN_0 (0x1UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */ 3471 #define FSMC_BWTRx_BUSTURN_1 (0x2UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */ 3472 #define FSMC_BWTRx_BUSTURN_2 (0x4UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */ 3473 #define FSMC_BWTRx_BUSTURN_3 (0x8UL << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */ 3474 3475 #define FSMC_BWTRx_ACCMOD_Pos (28U) 3476 #define FSMC_BWTRx_ACCMOD_Msk (0x3UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */ 3477 #define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 3478 #define FSMC_BWTRx_ACCMOD_0 (0x1UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */ 3479 #define FSMC_BWTRx_ACCMOD_1 (0x2UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */ 3480 3481 /******************************************************************************/ 3482 /* */ 3483 /* General Purpose I/O */ 3484 /* */ 3485 /******************************************************************************/ 3486 /****************** Bits definition for GPIO_MODER register *****************/ 3487 #define GPIO_MODER_MODER0_Pos (0U) 3488 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 3489 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 3490 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 3491 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 3492 3493 #define GPIO_MODER_MODER1_Pos (2U) 3494 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 3495 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 3496 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 3497 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 3498 3499 #define GPIO_MODER_MODER2_Pos (4U) 3500 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 3501 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 3502 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 3503 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 3504 3505 #define GPIO_MODER_MODER3_Pos (6U) 3506 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 3507 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 3508 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 3509 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 3510 3511 #define GPIO_MODER_MODER4_Pos (8U) 3512 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 3513 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 3514 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 3515 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 3516 3517 #define GPIO_MODER_MODER5_Pos (10U) 3518 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 3519 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 3520 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 3521 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 3522 3523 #define GPIO_MODER_MODER6_Pos (12U) 3524 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 3525 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 3526 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 3527 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 3528 3529 #define GPIO_MODER_MODER7_Pos (14U) 3530 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 3531 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 3532 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 3533 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 3534 3535 #define GPIO_MODER_MODER8_Pos (16U) 3536 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 3537 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 3538 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 3539 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 3540 3541 #define GPIO_MODER_MODER9_Pos (18U) 3542 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 3543 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 3544 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 3545 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 3546 3547 #define GPIO_MODER_MODER10_Pos (20U) 3548 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 3549 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 3550 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 3551 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 3552 3553 #define GPIO_MODER_MODER11_Pos (22U) 3554 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 3555 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 3556 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 3557 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 3558 3559 #define GPIO_MODER_MODER12_Pos (24U) 3560 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 3561 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 3562 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 3563 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 3564 3565 #define GPIO_MODER_MODER13_Pos (26U) 3566 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 3567 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 3568 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 3569 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 3570 3571 #define GPIO_MODER_MODER14_Pos (28U) 3572 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 3573 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 3574 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 3575 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 3576 3577 #define GPIO_MODER_MODER15_Pos (30U) 3578 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 3579 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 3580 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 3581 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 3582 3583 /****************** Bits definition for GPIO_OTYPER register ****************/ 3584 #define GPIO_OTYPER_OT_0 (0x00000001U) 3585 #define GPIO_OTYPER_OT_1 (0x00000002U) 3586 #define GPIO_OTYPER_OT_2 (0x00000004U) 3587 #define GPIO_OTYPER_OT_3 (0x00000008U) 3588 #define GPIO_OTYPER_OT_4 (0x00000010U) 3589 #define GPIO_OTYPER_OT_5 (0x00000020U) 3590 #define GPIO_OTYPER_OT_6 (0x00000040U) 3591 #define GPIO_OTYPER_OT_7 (0x00000080U) 3592 #define GPIO_OTYPER_OT_8 (0x00000100U) 3593 #define GPIO_OTYPER_OT_9 (0x00000200U) 3594 #define GPIO_OTYPER_OT_10 (0x00000400U) 3595 #define GPIO_OTYPER_OT_11 (0x00000800U) 3596 #define GPIO_OTYPER_OT_12 (0x00001000U) 3597 #define GPIO_OTYPER_OT_13 (0x00002000U) 3598 #define GPIO_OTYPER_OT_14 (0x00004000U) 3599 #define GPIO_OTYPER_OT_15 (0x00008000U) 3600 3601 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 3602 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 3603 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 3604 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 3605 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 3606 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 3607 3608 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 3609 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 3610 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 3611 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 3612 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 3613 3614 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 3615 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 3616 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 3617 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 3618 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 3619 3620 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 3621 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 3622 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 3623 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 3624 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 3625 3626 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 3627 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 3628 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 3629 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 3630 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 3631 3632 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 3633 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 3634 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 3635 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 3636 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 3637 3638 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 3639 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 3640 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 3641 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 3642 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 3643 3644 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 3645 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 3646 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 3647 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 3648 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 3649 3650 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 3651 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 3652 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 3653 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 3654 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 3655 3656 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 3657 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 3658 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 3659 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 3660 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 3661 3662 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 3663 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 3664 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 3665 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 3666 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 3667 3668 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 3669 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 3670 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 3671 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 3672 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 3673 3674 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 3675 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 3676 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 3677 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 3678 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 3679 3680 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 3681 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 3682 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 3683 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 3684 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 3685 3686 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 3687 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 3688 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 3689 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 3690 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 3691 3692 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 3693 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 3694 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 3695 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 3696 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 3697 3698 /****************** Bits definition for GPIO_PUPDR register *****************/ 3699 #define GPIO_PUPDR_PUPDR0_Pos (0U) 3700 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 3701 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 3702 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 3703 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 3704 3705 #define GPIO_PUPDR_PUPDR1_Pos (2U) 3706 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 3707 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 3708 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 3709 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 3710 3711 #define GPIO_PUPDR_PUPDR2_Pos (4U) 3712 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 3713 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 3714 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 3715 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 3716 3717 #define GPIO_PUPDR_PUPDR3_Pos (6U) 3718 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 3719 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 3720 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 3721 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 3722 3723 #define GPIO_PUPDR_PUPDR4_Pos (8U) 3724 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 3725 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 3726 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 3727 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 3728 3729 #define GPIO_PUPDR_PUPDR5_Pos (10U) 3730 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 3731 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 3732 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 3733 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 3734 3735 #define GPIO_PUPDR_PUPDR6_Pos (12U) 3736 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 3737 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 3738 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 3739 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 3740 3741 #define GPIO_PUPDR_PUPDR7_Pos (14U) 3742 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 3743 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 3744 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 3745 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 3746 3747 #define GPIO_PUPDR_PUPDR8_Pos (16U) 3748 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 3749 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 3750 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 3751 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 3752 3753 #define GPIO_PUPDR_PUPDR9_Pos (18U) 3754 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 3755 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 3756 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 3757 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 3758 3759 #define GPIO_PUPDR_PUPDR10_Pos (20U) 3760 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 3761 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 3762 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 3763 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 3764 3765 #define GPIO_PUPDR_PUPDR11_Pos (22U) 3766 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 3767 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 3768 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 3769 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 3770 3771 #define GPIO_PUPDR_PUPDR12_Pos (24U) 3772 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 3773 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 3774 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 3775 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 3776 3777 #define GPIO_PUPDR_PUPDR13_Pos (26U) 3778 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 3779 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 3780 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 3781 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 3782 3783 #define GPIO_PUPDR_PUPDR14_Pos (28U) 3784 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 3785 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 3786 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 3787 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 3788 #define GPIO_PUPDR_PUPDR15_Pos (30U) 3789 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 3790 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 3791 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 3792 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 3793 3794 /****************** Bits definition for GPIO_IDR register *******************/ 3795 #define GPIO_IDR_IDR_0 (0x00000001U) 3796 #define GPIO_IDR_IDR_1 (0x00000002U) 3797 #define GPIO_IDR_IDR_2 (0x00000004U) 3798 #define GPIO_IDR_IDR_3 (0x00000008U) 3799 #define GPIO_IDR_IDR_4 (0x00000010U) 3800 #define GPIO_IDR_IDR_5 (0x00000020U) 3801 #define GPIO_IDR_IDR_6 (0x00000040U) 3802 #define GPIO_IDR_IDR_7 (0x00000080U) 3803 #define GPIO_IDR_IDR_8 (0x00000100U) 3804 #define GPIO_IDR_IDR_9 (0x00000200U) 3805 #define GPIO_IDR_IDR_10 (0x00000400U) 3806 #define GPIO_IDR_IDR_11 (0x00000800U) 3807 #define GPIO_IDR_IDR_12 (0x00001000U) 3808 #define GPIO_IDR_IDR_13 (0x00002000U) 3809 #define GPIO_IDR_IDR_14 (0x00004000U) 3810 #define GPIO_IDR_IDR_15 (0x00008000U) 3811 3812 /****************** Bits definition for GPIO_ODR register *******************/ 3813 #define GPIO_ODR_ODR_0 (0x00000001U) 3814 #define GPIO_ODR_ODR_1 (0x00000002U) 3815 #define GPIO_ODR_ODR_2 (0x00000004U) 3816 #define GPIO_ODR_ODR_3 (0x00000008U) 3817 #define GPIO_ODR_ODR_4 (0x00000010U) 3818 #define GPIO_ODR_ODR_5 (0x00000020U) 3819 #define GPIO_ODR_ODR_6 (0x00000040U) 3820 #define GPIO_ODR_ODR_7 (0x00000080U) 3821 #define GPIO_ODR_ODR_8 (0x00000100U) 3822 #define GPIO_ODR_ODR_9 (0x00000200U) 3823 #define GPIO_ODR_ODR_10 (0x00000400U) 3824 #define GPIO_ODR_ODR_11 (0x00000800U) 3825 #define GPIO_ODR_ODR_12 (0x00001000U) 3826 #define GPIO_ODR_ODR_13 (0x00002000U) 3827 #define GPIO_ODR_ODR_14 (0x00004000U) 3828 #define GPIO_ODR_ODR_15 (0x00008000U) 3829 3830 /****************** Bits definition for GPIO_BSRR register ******************/ 3831 #define GPIO_BSRR_BS_0 (0x00000001U) 3832 #define GPIO_BSRR_BS_1 (0x00000002U) 3833 #define GPIO_BSRR_BS_2 (0x00000004U) 3834 #define GPIO_BSRR_BS_3 (0x00000008U) 3835 #define GPIO_BSRR_BS_4 (0x00000010U) 3836 #define GPIO_BSRR_BS_5 (0x00000020U) 3837 #define GPIO_BSRR_BS_6 (0x00000040U) 3838 #define GPIO_BSRR_BS_7 (0x00000080U) 3839 #define GPIO_BSRR_BS_8 (0x00000100U) 3840 #define GPIO_BSRR_BS_9 (0x00000200U) 3841 #define GPIO_BSRR_BS_10 (0x00000400U) 3842 #define GPIO_BSRR_BS_11 (0x00000800U) 3843 #define GPIO_BSRR_BS_12 (0x00001000U) 3844 #define GPIO_BSRR_BS_13 (0x00002000U) 3845 #define GPIO_BSRR_BS_14 (0x00004000U) 3846 #define GPIO_BSRR_BS_15 (0x00008000U) 3847 #define GPIO_BSRR_BR_0 (0x00010000U) 3848 #define GPIO_BSRR_BR_1 (0x00020000U) 3849 #define GPIO_BSRR_BR_2 (0x00040000U) 3850 #define GPIO_BSRR_BR_3 (0x00080000U) 3851 #define GPIO_BSRR_BR_4 (0x00100000U) 3852 #define GPIO_BSRR_BR_5 (0x00200000U) 3853 #define GPIO_BSRR_BR_6 (0x00400000U) 3854 #define GPIO_BSRR_BR_7 (0x00800000U) 3855 #define GPIO_BSRR_BR_8 (0x01000000U) 3856 #define GPIO_BSRR_BR_9 (0x02000000U) 3857 #define GPIO_BSRR_BR_10 (0x04000000U) 3858 #define GPIO_BSRR_BR_11 (0x08000000U) 3859 #define GPIO_BSRR_BR_12 (0x10000000U) 3860 #define GPIO_BSRR_BR_13 (0x20000000U) 3861 #define GPIO_BSRR_BR_14 (0x40000000U) 3862 #define GPIO_BSRR_BR_15 (0x80000000U) 3863 3864 /****************** Bit definition for GPIO_LCKR register ********************/ 3865 #define GPIO_LCKR_LCK0_Pos (0U) 3866 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 3867 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 3868 #define GPIO_LCKR_LCK1_Pos (1U) 3869 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 3870 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 3871 #define GPIO_LCKR_LCK2_Pos (2U) 3872 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 3873 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 3874 #define GPIO_LCKR_LCK3_Pos (3U) 3875 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 3876 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 3877 #define GPIO_LCKR_LCK4_Pos (4U) 3878 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3879 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3880 #define GPIO_LCKR_LCK5_Pos (5U) 3881 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3882 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3883 #define GPIO_LCKR_LCK6_Pos (6U) 3884 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3885 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3886 #define GPIO_LCKR_LCK7_Pos (7U) 3887 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3888 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3889 #define GPIO_LCKR_LCK8_Pos (8U) 3890 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3891 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3892 #define GPIO_LCKR_LCK9_Pos (9U) 3893 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3894 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3895 #define GPIO_LCKR_LCK10_Pos (10U) 3896 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3897 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3898 #define GPIO_LCKR_LCK11_Pos (11U) 3899 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3900 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3901 #define GPIO_LCKR_LCK12_Pos (12U) 3902 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3903 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3904 #define GPIO_LCKR_LCK13_Pos (13U) 3905 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3906 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3907 #define GPIO_LCKR_LCK14_Pos (14U) 3908 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3909 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3910 #define GPIO_LCKR_LCK15_Pos (15U) 3911 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3912 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3913 #define GPIO_LCKR_LCKK_Pos (16U) 3914 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3915 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3916 3917 /****************** Bit definition for GPIO_AFRL register ********************/ 3918 #define GPIO_AFRL_AFSEL0_Pos (0U) 3919 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3920 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3921 #define GPIO_AFRL_AFSEL1_Pos (4U) 3922 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3923 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3924 #define GPIO_AFRL_AFSEL2_Pos (8U) 3925 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3926 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3927 #define GPIO_AFRL_AFSEL3_Pos (12U) 3928 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3929 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3930 #define GPIO_AFRL_AFSEL4_Pos (16U) 3931 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3932 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3933 #define GPIO_AFRL_AFSEL5_Pos (20U) 3934 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3935 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3936 #define GPIO_AFRL_AFSEL6_Pos (24U) 3937 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3938 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3939 #define GPIO_AFRL_AFSEL7_Pos (28U) 3940 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3941 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3942 3943 /****************** Bit definition for GPIO_AFRH register ********************/ 3944 #define GPIO_AFRH_AFSEL8_Pos (0U) 3945 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3946 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3947 #define GPIO_AFRH_AFSEL9_Pos (4U) 3948 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3949 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3950 #define GPIO_AFRH_AFSEL10_Pos (8U) 3951 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3952 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3953 #define GPIO_AFRH_AFSEL11_Pos (12U) 3954 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3955 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3956 #define GPIO_AFRH_AFSEL12_Pos (16U) 3957 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3958 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3959 #define GPIO_AFRH_AFSEL13_Pos (20U) 3960 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3961 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3962 #define GPIO_AFRH_AFSEL14_Pos (24U) 3963 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3964 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3965 #define GPIO_AFRH_AFSEL15_Pos (28U) 3966 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3967 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3968 3969 /****************** Bit definition for GPIO_BRR register *********************/ 3970 #define GPIO_BRR_BR_0 (0x00000001U) 3971 #define GPIO_BRR_BR_1 (0x00000002U) 3972 #define GPIO_BRR_BR_2 (0x00000004U) 3973 #define GPIO_BRR_BR_3 (0x00000008U) 3974 #define GPIO_BRR_BR_4 (0x00000010U) 3975 #define GPIO_BRR_BR_5 (0x00000020U) 3976 #define GPIO_BRR_BR_6 (0x00000040U) 3977 #define GPIO_BRR_BR_7 (0x00000080U) 3978 #define GPIO_BRR_BR_8 (0x00000100U) 3979 #define GPIO_BRR_BR_9 (0x00000200U) 3980 #define GPIO_BRR_BR_10 (0x00000400U) 3981 #define GPIO_BRR_BR_11 (0x00000800U) 3982 #define GPIO_BRR_BR_12 (0x00001000U) 3983 #define GPIO_BRR_BR_13 (0x00002000U) 3984 #define GPIO_BRR_BR_14 (0x00004000U) 3985 #define GPIO_BRR_BR_15 (0x00008000U) 3986 3987 /******************************************************************************/ 3988 /* */ 3989 /* Inter-integrated Circuit Interface (I2C) */ 3990 /* */ 3991 /******************************************************************************/ 3992 3993 /******************* Bit definition for I2C_CR1 register ********************/ 3994 #define I2C_CR1_PE_Pos (0U) 3995 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3996 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 3997 #define I2C_CR1_SMBUS_Pos (1U) 3998 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 3999 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 4000 #define I2C_CR1_SMBTYPE_Pos (3U) 4001 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 4002 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 4003 #define I2C_CR1_ENARP_Pos (4U) 4004 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 4005 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 4006 #define I2C_CR1_ENPEC_Pos (5U) 4007 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 4008 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 4009 #define I2C_CR1_ENGC_Pos (6U) 4010 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 4011 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 4012 #define I2C_CR1_NOSTRETCH_Pos (7U) 4013 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 4014 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 4015 #define I2C_CR1_START_Pos (8U) 4016 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 4017 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 4018 #define I2C_CR1_STOP_Pos (9U) 4019 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 4020 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 4021 #define I2C_CR1_ACK_Pos (10U) 4022 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 4023 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 4024 #define I2C_CR1_POS_Pos (11U) 4025 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 4026 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 4027 #define I2C_CR1_PEC_Pos (12U) 4028 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 4029 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 4030 #define I2C_CR1_ALERT_Pos (13U) 4031 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 4032 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 4033 #define I2C_CR1_SWRST_Pos (15U) 4034 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 4035 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 4036 4037 /******************* Bit definition for I2C_CR2 register ********************/ 4038 #define I2C_CR2_FREQ_Pos (0U) 4039 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 4040 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 4041 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 4042 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 4043 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 4044 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 4045 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 4046 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 4047 4048 #define I2C_CR2_ITERREN_Pos (8U) 4049 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 4050 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 4051 #define I2C_CR2_ITEVTEN_Pos (9U) 4052 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 4053 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 4054 #define I2C_CR2_ITBUFEN_Pos (10U) 4055 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 4056 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 4057 #define I2C_CR2_DMAEN_Pos (11U) 4058 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 4059 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 4060 #define I2C_CR2_LAST_Pos (12U) 4061 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 4062 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 4063 4064 /******************* Bit definition for I2C_OAR1 register *******************/ 4065 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */ 4066 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */ 4067 4068 #define I2C_OAR1_ADD0_Pos (0U) 4069 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 4070 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 4071 #define I2C_OAR1_ADD1_Pos (1U) 4072 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 4073 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 4074 #define I2C_OAR1_ADD2_Pos (2U) 4075 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 4076 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 4077 #define I2C_OAR1_ADD3_Pos (3U) 4078 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 4079 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 4080 #define I2C_OAR1_ADD4_Pos (4U) 4081 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 4082 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 4083 #define I2C_OAR1_ADD5_Pos (5U) 4084 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 4085 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 4086 #define I2C_OAR1_ADD6_Pos (6U) 4087 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 4088 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 4089 #define I2C_OAR1_ADD7_Pos (7U) 4090 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 4091 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 4092 #define I2C_OAR1_ADD8_Pos (8U) 4093 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 4094 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 4095 #define I2C_OAR1_ADD9_Pos (9U) 4096 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 4097 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 4098 4099 #define I2C_OAR1_ADDMODE_Pos (15U) 4100 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 4101 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 4102 4103 /******************* Bit definition for I2C_OAR2 register *******************/ 4104 #define I2C_OAR2_ENDUAL_Pos (0U) 4105 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 4106 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 4107 #define I2C_OAR2_ADD2_Pos (1U) 4108 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 4109 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 4110 4111 /******************** Bit definition for I2C_DR register ********************/ 4112 #define I2C_DR_DR_Pos (0U) 4113 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 4114 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 4115 4116 /******************* Bit definition for I2C_SR1 register ********************/ 4117 #define I2C_SR1_SB_Pos (0U) 4118 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 4119 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 4120 #define I2C_SR1_ADDR_Pos (1U) 4121 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 4122 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 4123 #define I2C_SR1_BTF_Pos (2U) 4124 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 4125 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 4126 #define I2C_SR1_ADD10_Pos (3U) 4127 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 4128 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 4129 #define I2C_SR1_STOPF_Pos (4U) 4130 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 4131 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 4132 #define I2C_SR1_RXNE_Pos (6U) 4133 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 4134 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 4135 #define I2C_SR1_TXE_Pos (7U) 4136 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 4137 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 4138 #define I2C_SR1_BERR_Pos (8U) 4139 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 4140 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 4141 #define I2C_SR1_ARLO_Pos (9U) 4142 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 4143 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 4144 #define I2C_SR1_AF_Pos (10U) 4145 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 4146 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 4147 #define I2C_SR1_OVR_Pos (11U) 4148 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 4149 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 4150 #define I2C_SR1_PECERR_Pos (12U) 4151 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 4152 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 4153 #define I2C_SR1_TIMEOUT_Pos (14U) 4154 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 4155 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 4156 #define I2C_SR1_SMBALERT_Pos (15U) 4157 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 4158 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 4159 4160 /******************* Bit definition for I2C_SR2 register ********************/ 4161 #define I2C_SR2_MSL_Pos (0U) 4162 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 4163 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 4164 #define I2C_SR2_BUSY_Pos (1U) 4165 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 4166 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 4167 #define I2C_SR2_TRA_Pos (2U) 4168 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 4169 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 4170 #define I2C_SR2_GENCALL_Pos (4U) 4171 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 4172 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 4173 #define I2C_SR2_SMBDEFAULT_Pos (5U) 4174 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 4175 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 4176 #define I2C_SR2_SMBHOST_Pos (6U) 4177 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 4178 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 4179 #define I2C_SR2_DUALF_Pos (7U) 4180 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 4181 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 4182 #define I2C_SR2_PEC_Pos (8U) 4183 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 4184 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 4185 4186 /******************* Bit definition for I2C_CCR register ********************/ 4187 #define I2C_CCR_CCR_Pos (0U) 4188 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 4189 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 4190 #define I2C_CCR_DUTY_Pos (14U) 4191 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 4192 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 4193 #define I2C_CCR_FS_Pos (15U) 4194 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 4195 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 4196 4197 /****************** Bit definition for I2C_TRISE register *******************/ 4198 #define I2C_TRISE_TRISE_Pos (0U) 4199 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 4200 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 4201 4202 /******************************************************************************/ 4203 /* */ 4204 /* Independent WATCHDOG (IWDG) */ 4205 /* */ 4206 /******************************************************************************/ 4207 4208 /******************* Bit definition for IWDG_KR register ********************/ 4209 #define IWDG_KR_KEY_Pos (0U) 4210 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 4211 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 4212 4213 /******************* Bit definition for IWDG_PR register ********************/ 4214 #define IWDG_PR_PR_Pos (0U) 4215 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 4216 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 4217 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 4218 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 4219 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 4220 4221 /******************* Bit definition for IWDG_RLR register *******************/ 4222 #define IWDG_RLR_RL_Pos (0U) 4223 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 4224 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 4225 4226 /******************* Bit definition for IWDG_SR register ********************/ 4227 #define IWDG_SR_PVU_Pos (0U) 4228 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 4229 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 4230 #define IWDG_SR_RVU_Pos (1U) 4231 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 4232 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 4233 4234 /******************************************************************************/ 4235 /* */ 4236 /* LCD Controller (LCD) */ 4237 /* */ 4238 /******************************************************************************/ 4239 4240 /******************* Bit definition for LCD_CR register *********************/ 4241 #define LCD_CR_LCDEN_Pos (0U) 4242 #define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ 4243 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ 4244 #define LCD_CR_VSEL_Pos (1U) 4245 #define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ 4246 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ 4247 4248 #define LCD_CR_DUTY_Pos (2U) 4249 #define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ 4250 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ 4251 #define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ 4252 #define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ 4253 #define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ 4254 4255 #define LCD_CR_BIAS_Pos (5U) 4256 #define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ 4257 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ 4258 #define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ 4259 #define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ 4260 4261 #define LCD_CR_MUX_SEG_Pos (7U) 4262 #define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ 4263 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ 4264 4265 /******************* Bit definition for LCD_FCR register ********************/ 4266 #define LCD_FCR_HD_Pos (0U) 4267 #define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */ 4268 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ 4269 #define LCD_FCR_SOFIE_Pos (1U) 4270 #define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ 4271 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ 4272 #define LCD_FCR_UDDIE_Pos (3U) 4273 #define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ 4274 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ 4275 4276 #define LCD_FCR_PON_Pos (4U) 4277 #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ 4278 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ 4279 #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ 4280 #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ 4281 #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ 4282 4283 #define LCD_FCR_DEAD_Pos (7U) 4284 #define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ 4285 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ 4286 #define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ 4287 #define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ 4288 #define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ 4289 4290 #define LCD_FCR_CC_Pos (10U) 4291 #define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ 4292 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ 4293 #define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */ 4294 #define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */ 4295 #define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */ 4296 4297 #define LCD_FCR_BLINKF_Pos (13U) 4298 #define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ 4299 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ 4300 #define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ 4301 #define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ 4302 #define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ 4303 4304 #define LCD_FCR_BLINK_Pos (16U) 4305 #define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ 4306 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ 4307 #define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ 4308 #define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ 4309 4310 #define LCD_FCR_DIV_Pos (18U) 4311 #define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ 4312 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ 4313 #define LCD_FCR_PS_Pos (22U) 4314 #define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ 4315 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ 4316 4317 /******************* Bit definition for LCD_SR register *********************/ 4318 #define LCD_SR_ENS_Pos (0U) 4319 #define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */ 4320 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ 4321 #define LCD_SR_SOF_Pos (1U) 4322 #define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */ 4323 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ 4324 #define LCD_SR_UDR_Pos (2U) 4325 #define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */ 4326 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ 4327 #define LCD_SR_UDD_Pos (3U) 4328 #define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */ 4329 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ 4330 #define LCD_SR_RDY_Pos (4U) 4331 #define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */ 4332 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ 4333 #define LCD_SR_FCRSR_Pos (5U) 4334 #define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ 4335 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ 4336 4337 /******************* Bit definition for LCD_CLR register ********************/ 4338 #define LCD_CLR_SOFC_Pos (1U) 4339 #define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ 4340 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ 4341 #define LCD_CLR_UDDC_Pos (3U) 4342 #define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ 4343 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ 4344 4345 /******************* Bit definition for LCD_RAM register ********************/ 4346 #define LCD_RAM_SEGMENT_DATA_Pos (0U) 4347 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ 4348 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ 4349 4350 /******************************************************************************/ 4351 /* */ 4352 /* Power Control (PWR) */ 4353 /* */ 4354 /******************************************************************************/ 4355 4356 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 4357 4358 /******************** Bit definition for PWR_CR register ********************/ 4359 #define PWR_CR_LPSDSR_Pos (0U) 4360 #define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 4361 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 4362 #define PWR_CR_PDDS_Pos (1U) 4363 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 4364 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 4365 #define PWR_CR_CWUF_Pos (2U) 4366 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 4367 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 4368 #define PWR_CR_CSBF_Pos (3U) 4369 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 4370 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 4371 #define PWR_CR_PVDE_Pos (4U) 4372 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 4373 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 4374 4375 #define PWR_CR_PLS_Pos (5U) 4376 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 4377 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 4378 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 4379 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 4380 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 4381 4382 /*!< PVD level configuration */ 4383 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 4384 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 4385 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 4386 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 4387 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 4388 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 4389 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 4390 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 4391 4392 #define PWR_CR_DBP_Pos (8U) 4393 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 4394 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 4395 #define PWR_CR_ULP_Pos (9U) 4396 #define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 4397 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 4398 #define PWR_CR_FWU_Pos (10U) 4399 #define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 4400 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 4401 4402 #define PWR_CR_VOS_Pos (11U) 4403 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 4404 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 4405 #define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 4406 #define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 4407 #define PWR_CR_LPRUN_Pos (14U) 4408 #define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 4409 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 4410 4411 /******************* Bit definition for PWR_CSR register ********************/ 4412 #define PWR_CSR_WUF_Pos (0U) 4413 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 4414 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 4415 #define PWR_CSR_SBF_Pos (1U) 4416 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 4417 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 4418 #define PWR_CSR_PVDO_Pos (2U) 4419 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 4420 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 4421 #define PWR_CSR_VREFINTRDYF_Pos (3U) 4422 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 4423 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 4424 #define PWR_CSR_VOSF_Pos (4U) 4425 #define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 4426 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 4427 #define PWR_CSR_REGLPF_Pos (5U) 4428 #define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 4429 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 4430 4431 #define PWR_CSR_EWUP1_Pos (8U) 4432 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 4433 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 4434 #define PWR_CSR_EWUP2_Pos (9U) 4435 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 4436 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 4437 #define PWR_CSR_EWUP3_Pos (10U) 4438 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 4439 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 4440 4441 /******************************************************************************/ 4442 /* */ 4443 /* Reset and Clock Control (RCC) */ 4444 /* */ 4445 /******************************************************************************/ 4446 /* 4447 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) 4448 */ 4449 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */ 4450 4451 /******************** Bit definition for RCC_CR register ********************/ 4452 #define RCC_CR_HSION_Pos (0U) 4453 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 4454 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 4455 #define RCC_CR_HSIRDY_Pos (1U) 4456 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 4457 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 4458 4459 #define RCC_CR_MSION_Pos (8U) 4460 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 4461 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 4462 #define RCC_CR_MSIRDY_Pos (9U) 4463 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 4464 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 4465 4466 #define RCC_CR_HSEON_Pos (16U) 4467 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 4468 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 4469 #define RCC_CR_HSERDY_Pos (17U) 4470 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 4471 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 4472 #define RCC_CR_HSEBYP_Pos (18U) 4473 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 4474 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 4475 4476 #define RCC_CR_PLLON_Pos (24U) 4477 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 4478 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 4479 #define RCC_CR_PLLRDY_Pos (25U) 4480 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 4481 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 4482 #define RCC_CR_CSSON_Pos (28U) 4483 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x10000000 */ 4484 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 4485 4486 #define RCC_CR_RTCPRE_Pos (29U) 4487 #define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */ 4488 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */ 4489 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */ 4490 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */ 4491 4492 /******************** Bit definition for RCC_ICSCR register *****************/ 4493 #define RCC_ICSCR_HSICAL_Pos (0U) 4494 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 4495 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 4496 #define RCC_ICSCR_HSITRIM_Pos (8U) 4497 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 4498 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 4499 4500 #define RCC_ICSCR_MSIRANGE_Pos (13U) 4501 #define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 4502 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 4503 #define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 4504 #define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 4505 #define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 4506 #define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 4507 #define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 4508 #define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 4509 #define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 4510 #define RCC_ICSCR_MSICAL_Pos (16U) 4511 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 4512 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 4513 #define RCC_ICSCR_MSITRIM_Pos (24U) 4514 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 4515 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 4516 4517 /******************** Bit definition for RCC_CFGR register ******************/ 4518 #define RCC_CFGR_SW_Pos (0U) 4519 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 4520 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 4521 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4522 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4523 4524 /*!< SW configuration */ 4525 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 4526 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 4527 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 4528 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 4529 4530 #define RCC_CFGR_SWS_Pos (2U) 4531 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 4532 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 4533 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 4534 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4535 4536 /*!< SWS configuration */ 4537 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 4538 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 4539 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 4540 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 4541 4542 #define RCC_CFGR_HPRE_Pos (4U) 4543 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 4544 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4545 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 4546 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 4547 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 4548 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 4549 4550 /*!< HPRE configuration */ 4551 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 4552 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 4553 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 4554 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 4555 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 4556 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 4557 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 4558 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 4559 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 4560 4561 #define RCC_CFGR_PPRE1_Pos (8U) 4562 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 4563 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 4564 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 4565 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 4566 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 4567 4568 /*!< PPRE1 configuration */ 4569 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 4570 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 4571 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 4572 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 4573 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 4574 4575 #define RCC_CFGR_PPRE2_Pos (11U) 4576 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 4577 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 4578 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 4579 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 4580 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 4581 4582 /*!< PPRE2 configuration */ 4583 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 4584 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 4585 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 4586 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 4587 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 4588 4589 /*!< PLL entry clock source*/ 4590 #define RCC_CFGR_PLLSRC_Pos (16U) 4591 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 4592 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 4593 4594 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 4595 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 4596 4597 4598 /*!< PLLMUL configuration */ 4599 #define RCC_CFGR_PLLMUL_Pos (18U) 4600 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 4601 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4602 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 4603 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 4604 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 4605 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 4606 4607 /*!< PLLMUL configuration */ 4608 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 4609 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 4610 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 4611 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 4612 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 4613 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 4614 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 4615 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 4616 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 4617 4618 /*!< PLLDIV configuration */ 4619 #define RCC_CFGR_PLLDIV_Pos (22U) 4620 #define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 4621 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 4622 #define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 4623 #define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 4624 4625 4626 /*!< PLLDIV configuration */ 4627 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */ 4628 #define RCC_CFGR_PLLDIV2_Pos (22U) 4629 #define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 4630 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 4631 #define RCC_CFGR_PLLDIV3_Pos (23U) 4632 #define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 4633 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 4634 #define RCC_CFGR_PLLDIV4_Pos (22U) 4635 #define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 4636 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 4637 4638 4639 #define RCC_CFGR_MCOSEL_Pos (24U) 4640 #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4641 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4642 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4643 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4644 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4645 4646 /*!< MCO configuration */ 4647 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4648 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 4649 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 4650 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */ 4651 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 4652 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 4653 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 4654 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 4655 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 4656 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 4657 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 4658 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 4659 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 4660 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 4661 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 4662 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 4663 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 4664 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 4665 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 4666 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 4667 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 4668 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 4669 4670 #define RCC_CFGR_MCOPRE_Pos (28U) 4671 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4672 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */ 4673 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4674 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4675 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4676 4677 /*!< MCO Prescaler configuration */ 4678 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 4679 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 4680 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 4681 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 4682 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 4683 4684 /* Legacy aliases */ 4685 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1 4686 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2 4687 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4 4688 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8 4689 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16 4690 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 4691 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 4692 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 4693 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 4694 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 4695 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 4696 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 4697 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 4698 4699 /*!<****************** Bit definition for RCC_CIR register ********************/ 4700 #define RCC_CIR_LSIRDYF_Pos (0U) 4701 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 4702 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 4703 #define RCC_CIR_LSERDYF_Pos (1U) 4704 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 4705 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 4706 #define RCC_CIR_HSIRDYF_Pos (2U) 4707 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 4708 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 4709 #define RCC_CIR_HSERDYF_Pos (3U) 4710 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 4711 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 4712 #define RCC_CIR_PLLRDYF_Pos (4U) 4713 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 4714 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 4715 #define RCC_CIR_MSIRDYF_Pos (5U) 4716 #define RCC_CIR_MSIRDYF_Msk (0x1UL << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */ 4717 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 4718 #define RCC_CIR_LSECSSF_Pos (6U) 4719 #define RCC_CIR_LSECSSF_Msk (0x1UL << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */ 4720 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */ 4721 #define RCC_CIR_CSSF_Pos (7U) 4722 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 4723 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 4724 4725 #define RCC_CIR_LSIRDYIE_Pos (8U) 4726 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 4727 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 4728 #define RCC_CIR_LSERDYIE_Pos (9U) 4729 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 4730 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 4731 #define RCC_CIR_HSIRDYIE_Pos (10U) 4732 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 4733 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 4734 #define RCC_CIR_HSERDYIE_Pos (11U) 4735 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 4736 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 4737 #define RCC_CIR_PLLRDYIE_Pos (12U) 4738 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 4739 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 4740 #define RCC_CIR_MSIRDYIE_Pos (13U) 4741 #define RCC_CIR_MSIRDYIE_Msk (0x1UL << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */ 4742 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 4743 #define RCC_CIR_LSECSSIE_Pos (14U) 4744 #define RCC_CIR_LSECSSIE_Msk (0x1UL << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */ 4745 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */ 4746 4747 #define RCC_CIR_LSIRDYC_Pos (16U) 4748 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 4749 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 4750 #define RCC_CIR_LSERDYC_Pos (17U) 4751 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 4752 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 4753 #define RCC_CIR_HSIRDYC_Pos (18U) 4754 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 4755 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 4756 #define RCC_CIR_HSERDYC_Pos (19U) 4757 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 4758 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 4759 #define RCC_CIR_PLLRDYC_Pos (20U) 4760 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 4761 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 4762 #define RCC_CIR_MSIRDYC_Pos (21U) 4763 #define RCC_CIR_MSIRDYC_Msk (0x1UL << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */ 4764 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 4765 #define RCC_CIR_LSECSSC_Pos (22U) 4766 #define RCC_CIR_LSECSSC_Msk (0x1UL << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */ 4767 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */ 4768 #define RCC_CIR_CSSC_Pos (23U) 4769 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 4770 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 4771 4772 /***************** Bit definition for RCC_AHBRSTR register ******************/ 4773 #define RCC_AHBRSTR_GPIOARST_Pos (0U) 4774 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4775 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */ 4776 #define RCC_AHBRSTR_GPIOBRST_Pos (1U) 4777 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4778 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */ 4779 #define RCC_AHBRSTR_GPIOCRST_Pos (2U) 4780 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4781 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */ 4782 #define RCC_AHBRSTR_GPIODRST_Pos (3U) 4783 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4784 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */ 4785 #define RCC_AHBRSTR_GPIOERST_Pos (4U) 4786 #define RCC_AHBRSTR_GPIOERST_Msk (0x1UL << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */ 4787 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */ 4788 #define RCC_AHBRSTR_GPIOHRST_Pos (5U) 4789 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1UL << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */ 4790 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */ 4791 #define RCC_AHBRSTR_GPIOFRST_Pos (6U) 4792 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */ 4793 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */ 4794 #define RCC_AHBRSTR_GPIOGRST_Pos (7U) 4795 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1UL << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */ 4796 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */ 4797 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4798 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4799 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 4800 #define RCC_AHBRSTR_FLITFRST_Pos (15U) 4801 #define RCC_AHBRSTR_FLITFRST_Msk (0x1UL << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */ 4802 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */ 4803 #define RCC_AHBRSTR_DMA1RST_Pos (24U) 4804 #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */ 4805 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */ 4806 #define RCC_AHBRSTR_DMA2RST_Pos (25U) 4807 #define RCC_AHBRSTR_DMA2RST_Msk (0x1UL << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */ 4808 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */ 4809 #define RCC_AHBRSTR_FSMCRST_Pos (30U) 4810 #define RCC_AHBRSTR_FSMCRST_Msk (0x1UL << RCC_AHBRSTR_FSMCRST_Pos) /*!< 0x40000000 */ 4811 #define RCC_AHBRSTR_FSMCRST RCC_AHBRSTR_FSMCRST_Msk /*!< FSMC reset */ 4812 4813 /***************** Bit definition for RCC_APB2RSTR register *****************/ 4814 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 4815 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 4816 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */ 4817 #define RCC_APB2RSTR_TIM9RST_Pos (2U) 4818 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */ 4819 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ 4820 #define RCC_APB2RSTR_TIM10RST_Pos (3U) 4821 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */ 4822 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */ 4823 #define RCC_APB2RSTR_TIM11RST_Pos (4U) 4824 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */ 4825 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */ 4826 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 4827 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 4828 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */ 4829 #define RCC_APB2RSTR_SDIORST_Pos (11U) 4830 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ 4831 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk /*!< SDIO reset */ 4832 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 4833 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 4834 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 4835 #define RCC_APB2RSTR_USART1RST_Pos (14U) 4836 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 4837 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 4838 4839 /***************** Bit definition for RCC_APB1RSTR register *****************/ 4840 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 4841 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 4842 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 4843 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 4844 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 4845 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 4846 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 4847 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 4848 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 4849 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 4850 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ 4851 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ 4852 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 4853 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 4854 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 4855 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 4856 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 4857 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 4858 #define RCC_APB1RSTR_LCDRST_Pos (9U) 4859 #define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ 4860 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */ 4861 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 4862 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 4863 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 4864 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 4865 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 4866 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 4867 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 4868 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 4869 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ 4870 #define RCC_APB1RSTR_USART2RST_Pos (17U) 4871 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 4872 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 4873 #define RCC_APB1RSTR_USART3RST_Pos (18U) 4874 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 4875 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 4876 #define RCC_APB1RSTR_UART4RST_Pos (19U) 4877 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ 4878 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ 4879 #define RCC_APB1RSTR_UART5RST_Pos (20U) 4880 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ 4881 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ 4882 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 4883 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 4884 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 4885 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 4886 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 4887 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 4888 #define RCC_APB1RSTR_USBRST_Pos (23U) 4889 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 4890 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ 4891 #define RCC_APB1RSTR_PWRRST_Pos (28U) 4892 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 4893 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 4894 #define RCC_APB1RSTR_DACRST_Pos (29U) 4895 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 4896 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 4897 #define RCC_APB1RSTR_COMPRST_Pos (31U) 4898 #define RCC_APB1RSTR_COMPRST_Msk (0x1UL << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */ 4899 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */ 4900 4901 /****************** Bit definition for RCC_AHBENR register ******************/ 4902 #define RCC_AHBENR_GPIOAEN_Pos (0U) 4903 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4904 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */ 4905 #define RCC_AHBENR_GPIOBEN_Pos (1U) 4906 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4907 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */ 4908 #define RCC_AHBENR_GPIOCEN_Pos (2U) 4909 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4910 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */ 4911 #define RCC_AHBENR_GPIODEN_Pos (3U) 4912 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */ 4913 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */ 4914 #define RCC_AHBENR_GPIOEEN_Pos (4U) 4915 #define RCC_AHBENR_GPIOEEN_Msk (0x1UL << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */ 4916 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */ 4917 #define RCC_AHBENR_GPIOHEN_Pos (5U) 4918 #define RCC_AHBENR_GPIOHEN_Msk (0x1UL << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */ 4919 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */ 4920 #define RCC_AHBENR_GPIOFEN_Pos (6U) 4921 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */ 4922 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */ 4923 #define RCC_AHBENR_GPIOGEN_Pos (7U) 4924 #define RCC_AHBENR_GPIOGEN_Msk (0x1UL << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */ 4925 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */ 4926 #define RCC_AHBENR_CRCEN_Pos (12U) 4927 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4928 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 4929 #define RCC_AHBENR_FLITFEN_Pos (15U) 4930 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */ 4931 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when 4932 the Flash memory is in power down mode) */ 4933 #define RCC_AHBENR_DMA1EN_Pos (24U) 4934 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */ 4935 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 4936 #define RCC_AHBENR_DMA2EN_Pos (25U) 4937 #define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */ 4938 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ 4939 #define RCC_AHBENR_FSMCEN_Pos (30U) 4940 #define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /*!< 0x40000000 */ 4941 #define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */ 4942 4943 /****************** Bit definition for RCC_APB2ENR register *****************/ 4944 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 4945 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 4946 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */ 4947 #define RCC_APB2ENR_TIM9EN_Pos (2U) 4948 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */ 4949 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */ 4950 #define RCC_APB2ENR_TIM10EN_Pos (3U) 4951 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */ 4952 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */ 4953 #define RCC_APB2ENR_TIM11EN_Pos (4U) 4954 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */ 4955 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */ 4956 #define RCC_APB2ENR_ADC1EN_Pos (9U) 4957 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 4958 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */ 4959 #define RCC_APB2ENR_SDIOEN_Pos (11U) 4960 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ 4961 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk /*!< SDIO clock enable */ 4962 #define RCC_APB2ENR_SPI1EN_Pos (12U) 4963 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 4964 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 4965 #define RCC_APB2ENR_USART1EN_Pos (14U) 4966 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 4967 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 4968 4969 /***************** Bit definition for RCC_APB1ENR register ******************/ 4970 #define RCC_APB1ENR_TIM2EN_Pos (0U) 4971 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 4972 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 4973 #define RCC_APB1ENR_TIM3EN_Pos (1U) 4974 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 4975 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 4976 #define RCC_APB1ENR_TIM4EN_Pos (2U) 4977 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 4978 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 4979 #define RCC_APB1ENR_TIM5EN_Pos (3U) 4980 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ 4981 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ 4982 #define RCC_APB1ENR_TIM6EN_Pos (4U) 4983 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 4984 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 4985 #define RCC_APB1ENR_TIM7EN_Pos (5U) 4986 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 4987 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 4988 #define RCC_APB1ENR_LCDEN_Pos (9U) 4989 #define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ 4990 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ 4991 #define RCC_APB1ENR_WWDGEN_Pos (11U) 4992 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 4993 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 4994 #define RCC_APB1ENR_SPI2EN_Pos (14U) 4995 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 4996 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 4997 #define RCC_APB1ENR_SPI3EN_Pos (15U) 4998 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 4999 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ 5000 #define RCC_APB1ENR_USART2EN_Pos (17U) 5001 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 5002 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 5003 #define RCC_APB1ENR_USART3EN_Pos (18U) 5004 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 5005 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 5006 #define RCC_APB1ENR_UART4EN_Pos (19U) 5007 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ 5008 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ 5009 #define RCC_APB1ENR_UART5EN_Pos (20U) 5010 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ 5011 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ 5012 #define RCC_APB1ENR_I2C1EN_Pos (21U) 5013 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 5014 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 5015 #define RCC_APB1ENR_I2C2EN_Pos (22U) 5016 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 5017 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 5018 #define RCC_APB1ENR_USBEN_Pos (23U) 5019 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 5020 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ 5021 #define RCC_APB1ENR_PWREN_Pos (28U) 5022 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 5023 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 5024 #define RCC_APB1ENR_DACEN_Pos (29U) 5025 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 5026 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 5027 #define RCC_APB1ENR_COMPEN_Pos (31U) 5028 #define RCC_APB1ENR_COMPEN_Msk (0x1UL << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */ 5029 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */ 5030 5031 /****************** Bit definition for RCC_AHBLPENR register ****************/ 5032 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U) 5033 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ 5034 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 5035 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) 5036 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ 5037 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 5038 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) 5039 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ 5040 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 5041 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U) 5042 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ 5043 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 5044 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U) 5045 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ 5046 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 5047 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) 5048 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */ 5049 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 5050 #define RCC_AHBLPENR_GPIOFLPEN_Pos (6U) 5051 #define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */ 5052 #define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */ 5053 #define RCC_AHBLPENR_GPIOGLPEN_Pos (7U) 5054 #define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */ 5055 #define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */ 5056 #define RCC_AHBLPENR_CRCLPEN_Pos (12U) 5057 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1UL << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */ 5058 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */ 5059 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U) 5060 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1UL << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ 5061 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode 5062 (has effect only when the Flash memory is 5063 in power down mode) */ 5064 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U) 5065 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1UL << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */ 5066 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */ 5067 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U) 5068 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */ 5069 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */ 5070 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U) 5071 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1UL << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */ 5072 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */ 5073 #define RCC_AHBLPENR_FSMCLPEN_Pos (30U) 5074 #define RCC_AHBLPENR_FSMCLPEN_Msk (0x1UL << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */ 5075 #define RCC_AHBLPENR_FSMCLPEN RCC_AHBLPENR_FSMCLPEN_Msk /*!< FSMC clock enabled in sleep mode */ 5076 5077 /****************** Bit definition for RCC_APB2LPENR register ***************/ 5078 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) 5079 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */ 5080 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */ 5081 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U) 5082 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */ 5083 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */ 5084 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U) 5085 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */ 5086 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */ 5087 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U) 5088 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */ 5089 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */ 5090 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U) 5091 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */ 5092 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */ 5093 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) 5094 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ 5095 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk /*!< SDIO clock enabled in sleep mode */ 5096 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 5097 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ 5098 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */ 5099 #define RCC_APB2LPENR_USART1LPEN_Pos (14U) 5100 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ 5101 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */ 5102 5103 /***************** Bit definition for RCC_APB1LPENR register ****************/ 5104 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 5105 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ 5106 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 5107 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 5108 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ 5109 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 5110 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 5111 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ 5112 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */ 5113 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) 5114 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ 5115 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */ 5116 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 5117 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ 5118 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 5119 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 5120 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ 5121 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 5122 #define RCC_APB1LPENR_LCDLPEN_Pos (9U) 5123 #define RCC_APB1LPENR_LCDLPEN_Msk (0x1UL << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */ 5124 #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */ 5125 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 5126 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ 5127 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 5128 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 5129 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ 5130 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */ 5131 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) 5132 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ 5133 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */ 5134 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 5135 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ 5136 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */ 5137 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 5138 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ 5139 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */ 5140 #define RCC_APB1LPENR_UART4LPEN_Pos (19U) 5141 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ 5142 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */ 5143 #define RCC_APB1LPENR_UART5LPEN_Pos (20U) 5144 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ 5145 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */ 5146 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 5147 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ 5148 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */ 5149 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 5150 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ 5151 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */ 5152 #define RCC_APB1LPENR_USBLPEN_Pos (23U) 5153 #define RCC_APB1LPENR_USBLPEN_Msk (0x1UL << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */ 5154 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */ 5155 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 5156 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ 5157 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */ 5158 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 5159 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ 5160 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */ 5161 #define RCC_APB1LPENR_COMPLPEN_Pos (31U) 5162 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1UL << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */ 5163 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/ 5164 5165 /******************* Bit definition for RCC_CSR register ********************/ 5166 #define RCC_CSR_LSION_Pos (0U) 5167 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 5168 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 5169 #define RCC_CSR_LSIRDY_Pos (1U) 5170 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 5171 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 5172 5173 #define RCC_CSR_LSEON_Pos (8U) 5174 #define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 5175 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 5176 #define RCC_CSR_LSERDY_Pos (9U) 5177 #define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 5178 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 5179 #define RCC_CSR_LSEBYP_Pos (10U) 5180 #define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 5181 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 5182 5183 #define RCC_CSR_LSECSSON_Pos (11U) 5184 #define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */ 5185 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 5186 #define RCC_CSR_LSECSSD_Pos (12U) 5187 #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */ 5188 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 5189 5190 #define RCC_CSR_RTCSEL_Pos (16U) 5191 #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 5192 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 5193 #define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 5194 #define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 5195 5196 /*!< RTC congiguration */ 5197 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 5198 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 5199 #define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 5200 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 5201 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 5202 #define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 5203 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 5204 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 5205 #define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 5206 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */ 5207 5208 #define RCC_CSR_RTCEN_Pos (22U) 5209 #define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */ 5210 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 5211 #define RCC_CSR_RTCRST_Pos (23U) 5212 #define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */ 5213 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */ 5214 5215 #define RCC_CSR_RMVF_Pos (24U) 5216 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 5217 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 5218 #define RCC_CSR_OBLRSTF_Pos (25U) 5219 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 5220 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */ 5221 #define RCC_CSR_PINRSTF_Pos (26U) 5222 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 5223 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 5224 #define RCC_CSR_PORRSTF_Pos (27U) 5225 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 5226 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 5227 #define RCC_CSR_SFTRSTF_Pos (28U) 5228 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 5229 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 5230 #define RCC_CSR_IWDGRSTF_Pos (29U) 5231 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 5232 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 5233 #define RCC_CSR_WWDGRSTF_Pos (30U) 5234 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 5235 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 5236 #define RCC_CSR_LPWRRSTF_Pos (31U) 5237 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 5238 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 5239 5240 /******************************************************************************/ 5241 /* */ 5242 /* Real-Time Clock (RTC) */ 5243 /* */ 5244 /******************************************************************************/ 5245 /* 5246 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) 5247 */ 5248 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 5249 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 5250 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */ 5251 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 5252 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 5253 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */ 5254 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */ 5255 5256 /******************** Bits definition for RTC_TR register *******************/ 5257 #define RTC_TR_PM_Pos (22U) 5258 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 5259 #define RTC_TR_PM RTC_TR_PM_Msk 5260 #define RTC_TR_HT_Pos (20U) 5261 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 5262 #define RTC_TR_HT RTC_TR_HT_Msk 5263 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 5264 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 5265 #define RTC_TR_HU_Pos (16U) 5266 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 5267 #define RTC_TR_HU RTC_TR_HU_Msk 5268 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 5269 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 5270 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 5271 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 5272 #define RTC_TR_MNT_Pos (12U) 5273 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 5274 #define RTC_TR_MNT RTC_TR_MNT_Msk 5275 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 5276 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 5277 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 5278 #define RTC_TR_MNU_Pos (8U) 5279 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 5280 #define RTC_TR_MNU RTC_TR_MNU_Msk 5281 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 5282 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 5283 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 5284 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 5285 #define RTC_TR_ST_Pos (4U) 5286 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 5287 #define RTC_TR_ST RTC_TR_ST_Msk 5288 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 5289 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 5290 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 5291 #define RTC_TR_SU_Pos (0U) 5292 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 5293 #define RTC_TR_SU RTC_TR_SU_Msk 5294 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 5295 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 5296 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 5297 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 5298 5299 /******************** Bits definition for RTC_DR register *******************/ 5300 #define RTC_DR_YT_Pos (20U) 5301 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 5302 #define RTC_DR_YT RTC_DR_YT_Msk 5303 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 5304 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 5305 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 5306 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 5307 #define RTC_DR_YU_Pos (16U) 5308 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 5309 #define RTC_DR_YU RTC_DR_YU_Msk 5310 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 5311 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 5312 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 5313 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 5314 #define RTC_DR_WDU_Pos (13U) 5315 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 5316 #define RTC_DR_WDU RTC_DR_WDU_Msk 5317 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 5318 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 5319 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 5320 #define RTC_DR_MT_Pos (12U) 5321 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 5322 #define RTC_DR_MT RTC_DR_MT_Msk 5323 #define RTC_DR_MU_Pos (8U) 5324 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 5325 #define RTC_DR_MU RTC_DR_MU_Msk 5326 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 5327 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 5328 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 5329 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 5330 #define RTC_DR_DT_Pos (4U) 5331 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 5332 #define RTC_DR_DT RTC_DR_DT_Msk 5333 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 5334 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 5335 #define RTC_DR_DU_Pos (0U) 5336 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 5337 #define RTC_DR_DU RTC_DR_DU_Msk 5338 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 5339 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 5340 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 5341 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 5342 5343 /******************** Bits definition for RTC_CR register *******************/ 5344 #define RTC_CR_COE_Pos (23U) 5345 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 5346 #define RTC_CR_COE RTC_CR_COE_Msk 5347 #define RTC_CR_OSEL_Pos (21U) 5348 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 5349 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 5350 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 5351 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 5352 #define RTC_CR_POL_Pos (20U) 5353 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 5354 #define RTC_CR_POL RTC_CR_POL_Msk 5355 #define RTC_CR_COSEL_Pos (19U) 5356 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 5357 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 5358 #define RTC_CR_BKP_Pos (18U) 5359 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 5360 #define RTC_CR_BKP RTC_CR_BKP_Msk 5361 #define RTC_CR_SUB1H_Pos (17U) 5362 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 5363 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 5364 #define RTC_CR_ADD1H_Pos (16U) 5365 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 5366 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 5367 #define RTC_CR_TSIE_Pos (15U) 5368 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 5369 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 5370 #define RTC_CR_WUTIE_Pos (14U) 5371 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 5372 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 5373 #define RTC_CR_ALRBIE_Pos (13U) 5374 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 5375 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 5376 #define RTC_CR_ALRAIE_Pos (12U) 5377 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 5378 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 5379 #define RTC_CR_TSE_Pos (11U) 5380 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 5381 #define RTC_CR_TSE RTC_CR_TSE_Msk 5382 #define RTC_CR_WUTE_Pos (10U) 5383 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 5384 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 5385 #define RTC_CR_ALRBE_Pos (9U) 5386 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 5387 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 5388 #define RTC_CR_ALRAE_Pos (8U) 5389 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 5390 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 5391 #define RTC_CR_DCE_Pos (7U) 5392 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos) /*!< 0x00000080 */ 5393 #define RTC_CR_DCE RTC_CR_DCE_Msk 5394 #define RTC_CR_FMT_Pos (6U) 5395 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 5396 #define RTC_CR_FMT RTC_CR_FMT_Msk 5397 #define RTC_CR_BYPSHAD_Pos (5U) 5398 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 5399 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 5400 #define RTC_CR_REFCKON_Pos (4U) 5401 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 5402 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 5403 #define RTC_CR_TSEDGE_Pos (3U) 5404 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 5405 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 5406 #define RTC_CR_WUCKSEL_Pos (0U) 5407 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 5408 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 5409 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 5410 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 5411 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 5412 5413 /* Legacy defines */ 5414 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 5415 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 5416 #define RTC_CR_BCK RTC_CR_BKP 5417 5418 /******************** Bits definition for RTC_ISR register ******************/ 5419 #define RTC_ISR_RECALPF_Pos (16U) 5420 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 5421 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 5422 #define RTC_ISR_TAMP3F_Pos (15U) 5423 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 5424 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk 5425 #define RTC_ISR_TAMP2F_Pos (14U) 5426 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 5427 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 5428 #define RTC_ISR_TAMP1F_Pos (13U) 5429 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 5430 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 5431 #define RTC_ISR_TSOVF_Pos (12U) 5432 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 5433 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 5434 #define RTC_ISR_TSF_Pos (11U) 5435 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 5436 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 5437 #define RTC_ISR_WUTF_Pos (10U) 5438 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 5439 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 5440 #define RTC_ISR_ALRBF_Pos (9U) 5441 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 5442 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 5443 #define RTC_ISR_ALRAF_Pos (8U) 5444 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 5445 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 5446 #define RTC_ISR_INIT_Pos (7U) 5447 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 5448 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 5449 #define RTC_ISR_INITF_Pos (6U) 5450 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 5451 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 5452 #define RTC_ISR_RSF_Pos (5U) 5453 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 5454 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 5455 #define RTC_ISR_INITS_Pos (4U) 5456 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 5457 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 5458 #define RTC_ISR_SHPF_Pos (3U) 5459 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 5460 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 5461 #define RTC_ISR_WUTWF_Pos (2U) 5462 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 5463 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 5464 #define RTC_ISR_ALRBWF_Pos (1U) 5465 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 5466 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 5467 #define RTC_ISR_ALRAWF_Pos (0U) 5468 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 5469 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 5470 5471 /******************** Bits definition for RTC_PRER register *****************/ 5472 #define RTC_PRER_PREDIV_A_Pos (16U) 5473 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 5474 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 5475 #define RTC_PRER_PREDIV_S_Pos (0U) 5476 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 5477 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 5478 5479 /******************** Bits definition for RTC_WUTR register *****************/ 5480 #define RTC_WUTR_WUT_Pos (0U) 5481 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 5482 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 5483 5484 /******************** Bits definition for RTC_CALIBR register ***************/ 5485 #define RTC_CALIBR_DCS_Pos (7U) 5486 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ 5487 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk 5488 #define RTC_CALIBR_DC_Pos (0U) 5489 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ 5490 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk 5491 5492 /******************** Bits definition for RTC_ALRMAR register ***************/ 5493 #define RTC_ALRMAR_MSK4_Pos (31U) 5494 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 5495 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 5496 #define RTC_ALRMAR_WDSEL_Pos (30U) 5497 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 5498 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 5499 #define RTC_ALRMAR_DT_Pos (28U) 5500 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 5501 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 5502 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 5503 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 5504 #define RTC_ALRMAR_DU_Pos (24U) 5505 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 5506 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 5507 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 5508 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 5509 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 5510 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 5511 #define RTC_ALRMAR_MSK3_Pos (23U) 5512 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 5513 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 5514 #define RTC_ALRMAR_PM_Pos (22U) 5515 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 5516 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 5517 #define RTC_ALRMAR_HT_Pos (20U) 5518 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 5519 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 5520 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 5521 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 5522 #define RTC_ALRMAR_HU_Pos (16U) 5523 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 5524 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 5525 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 5526 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 5527 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 5528 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 5529 #define RTC_ALRMAR_MSK2_Pos (15U) 5530 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 5531 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 5532 #define RTC_ALRMAR_MNT_Pos (12U) 5533 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 5534 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 5535 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 5536 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 5537 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 5538 #define RTC_ALRMAR_MNU_Pos (8U) 5539 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 5540 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 5541 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 5542 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 5543 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 5544 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 5545 #define RTC_ALRMAR_MSK1_Pos (7U) 5546 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 5547 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 5548 #define RTC_ALRMAR_ST_Pos (4U) 5549 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 5550 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 5551 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 5552 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 5553 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 5554 #define RTC_ALRMAR_SU_Pos (0U) 5555 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 5556 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 5557 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 5558 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 5559 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 5560 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 5561 5562 /******************** Bits definition for RTC_ALRMBR register ***************/ 5563 #define RTC_ALRMBR_MSK4_Pos (31U) 5564 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 5565 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 5566 #define RTC_ALRMBR_WDSEL_Pos (30U) 5567 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 5568 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 5569 #define RTC_ALRMBR_DT_Pos (28U) 5570 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 5571 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 5572 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 5573 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 5574 #define RTC_ALRMBR_DU_Pos (24U) 5575 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 5576 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 5577 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 5578 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 5579 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 5580 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 5581 #define RTC_ALRMBR_MSK3_Pos (23U) 5582 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 5583 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 5584 #define RTC_ALRMBR_PM_Pos (22U) 5585 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 5586 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 5587 #define RTC_ALRMBR_HT_Pos (20U) 5588 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 5589 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 5590 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 5591 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 5592 #define RTC_ALRMBR_HU_Pos (16U) 5593 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 5594 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 5595 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 5596 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 5597 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 5598 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 5599 #define RTC_ALRMBR_MSK2_Pos (15U) 5600 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 5601 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 5602 #define RTC_ALRMBR_MNT_Pos (12U) 5603 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 5604 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 5605 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 5606 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 5607 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 5608 #define RTC_ALRMBR_MNU_Pos (8U) 5609 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 5610 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 5611 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 5612 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 5613 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 5614 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 5615 #define RTC_ALRMBR_MSK1_Pos (7U) 5616 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 5617 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 5618 #define RTC_ALRMBR_ST_Pos (4U) 5619 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 5620 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 5621 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 5622 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 5623 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 5624 #define RTC_ALRMBR_SU_Pos (0U) 5625 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 5626 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 5627 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 5628 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 5629 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 5630 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 5631 5632 /******************** Bits definition for RTC_WPR register ******************/ 5633 #define RTC_WPR_KEY_Pos (0U) 5634 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 5635 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 5636 5637 /******************** Bits definition for RTC_SSR register ******************/ 5638 #define RTC_SSR_SS_Pos (0U) 5639 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 5640 #define RTC_SSR_SS RTC_SSR_SS_Msk 5641 5642 /******************** Bits definition for RTC_SHIFTR register ***************/ 5643 #define RTC_SHIFTR_SUBFS_Pos (0U) 5644 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 5645 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 5646 #define RTC_SHIFTR_ADD1S_Pos (31U) 5647 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 5648 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 5649 5650 /******************** Bits definition for RTC_TSTR register *****************/ 5651 #define RTC_TSTR_PM_Pos (22U) 5652 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 5653 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 5654 #define RTC_TSTR_HT_Pos (20U) 5655 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 5656 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 5657 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 5658 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 5659 #define RTC_TSTR_HU_Pos (16U) 5660 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 5661 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 5662 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 5663 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 5664 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 5665 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 5666 #define RTC_TSTR_MNT_Pos (12U) 5667 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 5668 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 5669 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 5670 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 5671 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 5672 #define RTC_TSTR_MNU_Pos (8U) 5673 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 5674 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 5675 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 5676 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 5677 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 5678 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 5679 #define RTC_TSTR_ST_Pos (4U) 5680 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 5681 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 5682 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 5683 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 5684 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 5685 #define RTC_TSTR_SU_Pos (0U) 5686 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 5687 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 5688 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 5689 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 5690 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 5691 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 5692 5693 /******************** Bits definition for RTC_TSDR register *****************/ 5694 #define RTC_TSDR_WDU_Pos (13U) 5695 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 5696 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 5697 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 5698 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 5699 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 5700 #define RTC_TSDR_MT_Pos (12U) 5701 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 5702 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 5703 #define RTC_TSDR_MU_Pos (8U) 5704 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 5705 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 5706 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 5707 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 5708 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 5709 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 5710 #define RTC_TSDR_DT_Pos (4U) 5711 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 5712 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 5713 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 5714 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 5715 #define RTC_TSDR_DU_Pos (0U) 5716 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 5717 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 5718 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 5719 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 5720 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 5721 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 5722 5723 /******************** Bits definition for RTC_TSSSR register ****************/ 5724 #define RTC_TSSSR_SS_Pos (0U) 5725 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 5726 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 5727 5728 /******************** Bits definition for RTC_CAL register *****************/ 5729 #define RTC_CALR_CALP_Pos (15U) 5730 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 5731 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 5732 #define RTC_CALR_CALW8_Pos (14U) 5733 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 5734 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 5735 #define RTC_CALR_CALW16_Pos (13U) 5736 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 5737 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 5738 #define RTC_CALR_CALM_Pos (0U) 5739 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 5740 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 5741 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 5742 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 5743 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 5744 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 5745 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 5746 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 5747 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 5748 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 5749 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 5750 5751 /******************** Bits definition for RTC_TAFCR register ****************/ 5752 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) 5753 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ 5754 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk 5755 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 5756 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 5757 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 5758 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 5759 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 5760 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 5761 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 5762 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 5763 #define RTC_TAFCR_TAMPFLT_Pos (11U) 5764 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 5765 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 5766 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 5767 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 5768 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 5769 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 5770 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 5771 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 5772 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 5773 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 5774 #define RTC_TAFCR_TAMPTS_Pos (7U) 5775 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 5776 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 5777 #define RTC_TAFCR_TAMP3TRG_Pos (6U) 5778 #define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 5779 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk 5780 #define RTC_TAFCR_TAMP3E_Pos (5U) 5781 #define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ 5782 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk 5783 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 5784 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 5785 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 5786 #define RTC_TAFCR_TAMP2E_Pos (3U) 5787 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 5788 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 5789 #define RTC_TAFCR_TAMPIE_Pos (2U) 5790 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 5791 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 5792 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 5793 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 5794 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 5795 #define RTC_TAFCR_TAMP1E_Pos (0U) 5796 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 5797 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 5798 5799 /******************** Bits definition for RTC_ALRMASSR register *************/ 5800 #define RTC_ALRMASSR_MASKSS_Pos (24U) 5801 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 5802 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 5803 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 5804 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 5805 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 5806 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 5807 #define RTC_ALRMASSR_SS_Pos (0U) 5808 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 5809 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 5810 5811 /******************** Bits definition for RTC_ALRMBSSR register *************/ 5812 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 5813 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 5814 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 5815 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 5816 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 5817 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 5818 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 5819 #define RTC_ALRMBSSR_SS_Pos (0U) 5820 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 5821 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 5822 5823 /******************** Bits definition for RTC_BKP0R register ****************/ 5824 #define RTC_BKP0R_Pos (0U) 5825 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5826 #define RTC_BKP0R RTC_BKP0R_Msk 5827 5828 /******************** Bits definition for RTC_BKP1R register ****************/ 5829 #define RTC_BKP1R_Pos (0U) 5830 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5831 #define RTC_BKP1R RTC_BKP1R_Msk 5832 5833 /******************** Bits definition for RTC_BKP2R register ****************/ 5834 #define RTC_BKP2R_Pos (0U) 5835 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5836 #define RTC_BKP2R RTC_BKP2R_Msk 5837 5838 /******************** Bits definition for RTC_BKP3R register ****************/ 5839 #define RTC_BKP3R_Pos (0U) 5840 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5841 #define RTC_BKP3R RTC_BKP3R_Msk 5842 5843 /******************** Bits definition for RTC_BKP4R register ****************/ 5844 #define RTC_BKP4R_Pos (0U) 5845 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5846 #define RTC_BKP4R RTC_BKP4R_Msk 5847 5848 /******************** Bits definition for RTC_BKP5R register ****************/ 5849 #define RTC_BKP5R_Pos (0U) 5850 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 5851 #define RTC_BKP5R RTC_BKP5R_Msk 5852 5853 /******************** Bits definition for RTC_BKP6R register ****************/ 5854 #define RTC_BKP6R_Pos (0U) 5855 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 5856 #define RTC_BKP6R RTC_BKP6R_Msk 5857 5858 /******************** Bits definition for RTC_BKP7R register ****************/ 5859 #define RTC_BKP7R_Pos (0U) 5860 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 5861 #define RTC_BKP7R RTC_BKP7R_Msk 5862 5863 /******************** Bits definition for RTC_BKP8R register ****************/ 5864 #define RTC_BKP8R_Pos (0U) 5865 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 5866 #define RTC_BKP8R RTC_BKP8R_Msk 5867 5868 /******************** Bits definition for RTC_BKP9R register ****************/ 5869 #define RTC_BKP9R_Pos (0U) 5870 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 5871 #define RTC_BKP9R RTC_BKP9R_Msk 5872 5873 /******************** Bits definition for RTC_BKP10R register ***************/ 5874 #define RTC_BKP10R_Pos (0U) 5875 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 5876 #define RTC_BKP10R RTC_BKP10R_Msk 5877 5878 /******************** Bits definition for RTC_BKP11R register ***************/ 5879 #define RTC_BKP11R_Pos (0U) 5880 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 5881 #define RTC_BKP11R RTC_BKP11R_Msk 5882 5883 /******************** Bits definition for RTC_BKP12R register ***************/ 5884 #define RTC_BKP12R_Pos (0U) 5885 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 5886 #define RTC_BKP12R RTC_BKP12R_Msk 5887 5888 /******************** Bits definition for RTC_BKP13R register ***************/ 5889 #define RTC_BKP13R_Pos (0U) 5890 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 5891 #define RTC_BKP13R RTC_BKP13R_Msk 5892 5893 /******************** Bits definition for RTC_BKP14R register ***************/ 5894 #define RTC_BKP14R_Pos (0U) 5895 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 5896 #define RTC_BKP14R RTC_BKP14R_Msk 5897 5898 /******************** Bits definition for RTC_BKP15R register ***************/ 5899 #define RTC_BKP15R_Pos (0U) 5900 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 5901 #define RTC_BKP15R RTC_BKP15R_Msk 5902 5903 /******************** Bits definition for RTC_BKP16R register ***************/ 5904 #define RTC_BKP16R_Pos (0U) 5905 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 5906 #define RTC_BKP16R RTC_BKP16R_Msk 5907 5908 /******************** Bits definition for RTC_BKP17R register ***************/ 5909 #define RTC_BKP17R_Pos (0U) 5910 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 5911 #define RTC_BKP17R RTC_BKP17R_Msk 5912 5913 /******************** Bits definition for RTC_BKP18R register ***************/ 5914 #define RTC_BKP18R_Pos (0U) 5915 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 5916 #define RTC_BKP18R RTC_BKP18R_Msk 5917 5918 /******************** Bits definition for RTC_BKP19R register ***************/ 5919 #define RTC_BKP19R_Pos (0U) 5920 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 5921 #define RTC_BKP19R RTC_BKP19R_Msk 5922 5923 /******************** Bits definition for RTC_BKP20R register ***************/ 5924 #define RTC_BKP20R_Pos (0U) 5925 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ 5926 #define RTC_BKP20R RTC_BKP20R_Msk 5927 5928 /******************** Bits definition for RTC_BKP21R register ***************/ 5929 #define RTC_BKP21R_Pos (0U) 5930 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ 5931 #define RTC_BKP21R RTC_BKP21R_Msk 5932 5933 /******************** Bits definition for RTC_BKP22R register ***************/ 5934 #define RTC_BKP22R_Pos (0U) 5935 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ 5936 #define RTC_BKP22R RTC_BKP22R_Msk 5937 5938 /******************** Bits definition for RTC_BKP23R register ***************/ 5939 #define RTC_BKP23R_Pos (0U) 5940 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ 5941 #define RTC_BKP23R RTC_BKP23R_Msk 5942 5943 /******************** Bits definition for RTC_BKP24R register ***************/ 5944 #define RTC_BKP24R_Pos (0U) 5945 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ 5946 #define RTC_BKP24R RTC_BKP24R_Msk 5947 5948 /******************** Bits definition for RTC_BKP25R register ***************/ 5949 #define RTC_BKP25R_Pos (0U) 5950 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ 5951 #define RTC_BKP25R RTC_BKP25R_Msk 5952 5953 /******************** Bits definition for RTC_BKP26R register ***************/ 5954 #define RTC_BKP26R_Pos (0U) 5955 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ 5956 #define RTC_BKP26R RTC_BKP26R_Msk 5957 5958 /******************** Bits definition for RTC_BKP27R register ***************/ 5959 #define RTC_BKP27R_Pos (0U) 5960 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ 5961 #define RTC_BKP27R RTC_BKP27R_Msk 5962 5963 /******************** Bits definition for RTC_BKP28R register ***************/ 5964 #define RTC_BKP28R_Pos (0U) 5965 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ 5966 #define RTC_BKP28R RTC_BKP28R_Msk 5967 5968 /******************** Bits definition for RTC_BKP29R register ***************/ 5969 #define RTC_BKP29R_Pos (0U) 5970 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ 5971 #define RTC_BKP29R RTC_BKP29R_Msk 5972 5973 /******************** Bits definition for RTC_BKP30R register ***************/ 5974 #define RTC_BKP30R_Pos (0U) 5975 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ 5976 #define RTC_BKP30R RTC_BKP30R_Msk 5977 5978 /******************** Bits definition for RTC_BKP31R register ***************/ 5979 #define RTC_BKP31R_Pos (0U) 5980 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ 5981 #define RTC_BKP31R RTC_BKP31R_Msk 5982 5983 /******************** Number of backup registers ******************************/ 5984 #define RTC_BKP_NUMBER 32 5985 5986 /******************************************************************************/ 5987 /* */ 5988 /* SD host Interface */ 5989 /* */ 5990 /******************************************************************************/ 5991 5992 /****************** Bit definition for SDIO_POWER register ******************/ 5993 #define SDIO_POWER_PWRCTRL_Pos (0U) 5994 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ 5995 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ 5996 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000001 */ 5997 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000002 */ 5998 5999 /****************** Bit definition for SDIO_CLKCR register ******************/ 6000 #define SDIO_CLKCR_CLKDIV_Pos (0U) 6001 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ 6002 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ 6003 #define SDIO_CLKCR_CLKEN_Pos (8U) 6004 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ 6005 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ 6006 #define SDIO_CLKCR_PWRSAV_Pos (9U) 6007 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ 6008 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ 6009 #define SDIO_CLKCR_BYPASS_Pos (10U) 6010 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ 6011 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ 6012 6013 #define SDIO_CLKCR_WIDBUS_Pos (11U) 6014 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ 6015 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ 6016 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */ 6017 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */ 6018 6019 #define SDIO_CLKCR_NEGEDGE_Pos (13U) 6020 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ 6021 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ 6022 #define SDIO_CLKCR_HWFC_EN_Pos (14U) 6023 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ 6024 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ 6025 6026 /******************* Bit definition for SDIO_ARG register *******************/ 6027 #define SDIO_ARG_CMDARG_Pos (0U) 6028 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ 6029 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ 6030 6031 /******************* Bit definition for SDIO_CMD register *******************/ 6032 #define SDIO_CMD_CMDINDEX_Pos (0U) 6033 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ 6034 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ 6035 6036 #define SDIO_CMD_WAITRESP_Pos (6U) 6037 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ 6038 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ 6039 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000040 */ 6040 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000080 */ 6041 6042 #define SDIO_CMD_WAITINT_Pos (8U) 6043 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ 6044 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ 6045 #define SDIO_CMD_WAITPEND_Pos (9U) 6046 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ 6047 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ 6048 #define SDIO_CMD_CPSMEN_Pos (10U) 6049 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ 6050 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ 6051 #define SDIO_CMD_SDIOSUSPEND_Pos (11U) 6052 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ 6053 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ 6054 #define SDIO_CMD_ENCMDCOMPL_Pos (12U) 6055 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ 6056 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ 6057 #define SDIO_CMD_NIEN_Pos (13U) 6058 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ 6059 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ 6060 #define SDIO_CMD_CEATACMD_Pos (14U) 6061 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ 6062 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ 6063 6064 /***************** Bit definition for SDIO_RESPCMD register *****************/ 6065 #define SDIO_RESPCMD_RESPCMD_Pos (0U) 6066 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ 6067 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ 6068 6069 /****************** Bit definition for SDIO_RESP0 register ******************/ 6070 #define SDIO_RESP0_CARDSTATUS0_Pos (0U) 6071 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ 6072 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ 6073 6074 /****************** Bit definition for SDIO_RESP1 register ******************/ 6075 #define SDIO_RESP1_CARDSTATUS1_Pos (0U) 6076 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ 6077 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ 6078 6079 /****************** Bit definition for SDIO_RESP2 register ******************/ 6080 #define SDIO_RESP2_CARDSTATUS2_Pos (0U) 6081 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ 6082 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ 6083 6084 /****************** Bit definition for SDIO_RESP3 register ******************/ 6085 #define SDIO_RESP3_CARDSTATUS3_Pos (0U) 6086 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ 6087 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ 6088 6089 /****************** Bit definition for SDIO_RESP4 register ******************/ 6090 #define SDIO_RESP4_CARDSTATUS4_Pos (0U) 6091 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ 6092 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ 6093 6094 /****************** Bit definition for SDIO_DTIMER register *****************/ 6095 #define SDIO_DTIMER_DATATIME_Pos (0U) 6096 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ 6097 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ 6098 6099 /****************** Bit definition for SDIO_DLEN register *******************/ 6100 #define SDIO_DLEN_DATALENGTH_Pos (0U) 6101 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ 6102 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ 6103 6104 /****************** Bit definition for SDIO_DCTRL register ******************/ 6105 #define SDIO_DCTRL_DTEN_Pos (0U) 6106 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ 6107 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ 6108 #define SDIO_DCTRL_DTDIR_Pos (1U) 6109 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ 6110 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ 6111 #define SDIO_DCTRL_DTMODE_Pos (2U) 6112 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ 6113 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ 6114 #define SDIO_DCTRL_DMAEN_Pos (3U) 6115 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ 6116 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ 6117 6118 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) 6119 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ 6120 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ 6121 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */ 6122 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */ 6123 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */ 6124 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */ 6125 6126 #define SDIO_DCTRL_RWSTART_Pos (8U) 6127 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ 6128 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ 6129 #define SDIO_DCTRL_RWSTOP_Pos (9U) 6130 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ 6131 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ 6132 #define SDIO_DCTRL_RWMOD_Pos (10U) 6133 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ 6134 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ 6135 #define SDIO_DCTRL_SDIOEN_Pos (11U) 6136 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ 6137 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ 6138 6139 /****************** Bit definition for SDIO_DCOUNT register *****************/ 6140 #define SDIO_DCOUNT_DATACOUNT_Pos (0U) 6141 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ 6142 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ 6143 6144 /****************** Bit definition for SDIO_STA register ********************/ 6145 #define SDIO_STA_CCRCFAIL_Pos (0U) 6146 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ 6147 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ 6148 #define SDIO_STA_DCRCFAIL_Pos (1U) 6149 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ 6150 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ 6151 #define SDIO_STA_CTIMEOUT_Pos (2U) 6152 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ 6153 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ 6154 #define SDIO_STA_DTIMEOUT_Pos (3U) 6155 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ 6156 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ 6157 #define SDIO_STA_TXUNDERR_Pos (4U) 6158 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ 6159 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ 6160 #define SDIO_STA_RXOVERR_Pos (5U) 6161 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ 6162 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ 6163 #define SDIO_STA_CMDREND_Pos (6U) 6164 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ 6165 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ 6166 #define SDIO_STA_CMDSENT_Pos (7U) 6167 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ 6168 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ 6169 #define SDIO_STA_DATAEND_Pos (8U) 6170 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ 6171 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ 6172 #define SDIO_STA_STBITERR_Pos (9U) 6173 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ 6174 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ 6175 #define SDIO_STA_DBCKEND_Pos (10U) 6176 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ 6177 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ 6178 #define SDIO_STA_CMDACT_Pos (11U) 6179 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ 6180 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ 6181 #define SDIO_STA_TXACT_Pos (12U) 6182 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ 6183 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ 6184 #define SDIO_STA_RXACT_Pos (13U) 6185 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ 6186 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ 6187 #define SDIO_STA_TXFIFOHE_Pos (14U) 6188 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ 6189 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ 6190 #define SDIO_STA_RXFIFOHF_Pos (15U) 6191 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ 6192 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ 6193 #define SDIO_STA_TXFIFOF_Pos (16U) 6194 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ 6195 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ 6196 #define SDIO_STA_RXFIFOF_Pos (17U) 6197 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ 6198 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ 6199 #define SDIO_STA_TXFIFOE_Pos (18U) 6200 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ 6201 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ 6202 #define SDIO_STA_RXFIFOE_Pos (19U) 6203 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ 6204 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ 6205 #define SDIO_STA_TXDAVL_Pos (20U) 6206 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ 6207 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ 6208 #define SDIO_STA_RXDAVL_Pos (21U) 6209 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ 6210 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ 6211 #define SDIO_STA_SDIOIT_Pos (22U) 6212 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ 6213 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ 6214 #define SDIO_STA_CEATAEND_Pos (23U) 6215 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ 6216 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ 6217 6218 /******************* Bit definition for SDIO_ICR register *******************/ 6219 #define SDIO_ICR_CCRCFAILC_Pos (0U) 6220 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ 6221 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ 6222 #define SDIO_ICR_DCRCFAILC_Pos (1U) 6223 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ 6224 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ 6225 #define SDIO_ICR_CTIMEOUTC_Pos (2U) 6226 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ 6227 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ 6228 #define SDIO_ICR_DTIMEOUTC_Pos (3U) 6229 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ 6230 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ 6231 #define SDIO_ICR_TXUNDERRC_Pos (4U) 6232 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ 6233 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ 6234 #define SDIO_ICR_RXOVERRC_Pos (5U) 6235 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ 6236 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ 6237 #define SDIO_ICR_CMDRENDC_Pos (6U) 6238 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ 6239 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ 6240 #define SDIO_ICR_CMDSENTC_Pos (7U) 6241 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ 6242 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ 6243 #define SDIO_ICR_DATAENDC_Pos (8U) 6244 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ 6245 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ 6246 #define SDIO_ICR_STBITERRC_Pos (9U) 6247 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ 6248 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ 6249 #define SDIO_ICR_DBCKENDC_Pos (10U) 6250 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ 6251 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ 6252 #define SDIO_ICR_SDIOITC_Pos (22U) 6253 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ 6254 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ 6255 #define SDIO_ICR_CEATAENDC_Pos (23U) 6256 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ 6257 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ 6258 6259 /****************** Bit definition for SDIO_MASK register *******************/ 6260 #define SDIO_MASK_CCRCFAILIE_Pos (0U) 6261 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ 6262 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ 6263 #define SDIO_MASK_DCRCFAILIE_Pos (1U) 6264 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ 6265 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ 6266 #define SDIO_MASK_CTIMEOUTIE_Pos (2U) 6267 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ 6268 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ 6269 #define SDIO_MASK_DTIMEOUTIE_Pos (3U) 6270 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ 6271 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ 6272 #define SDIO_MASK_TXUNDERRIE_Pos (4U) 6273 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ 6274 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ 6275 #define SDIO_MASK_RXOVERRIE_Pos (5U) 6276 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ 6277 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ 6278 #define SDIO_MASK_CMDRENDIE_Pos (6U) 6279 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ 6280 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ 6281 #define SDIO_MASK_CMDSENTIE_Pos (7U) 6282 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ 6283 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ 6284 #define SDIO_MASK_DATAENDIE_Pos (8U) 6285 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ 6286 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ 6287 #define SDIO_MASK_STBITERRIE_Pos (9U) 6288 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ 6289 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ 6290 #define SDIO_MASK_DBCKENDIE_Pos (10U) 6291 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ 6292 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ 6293 #define SDIO_MASK_CMDACTIE_Pos (11U) 6294 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ 6295 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ 6296 #define SDIO_MASK_TXACTIE_Pos (12U) 6297 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ 6298 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ 6299 #define SDIO_MASK_RXACTIE_Pos (13U) 6300 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ 6301 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ 6302 #define SDIO_MASK_TXFIFOHEIE_Pos (14U) 6303 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ 6304 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ 6305 #define SDIO_MASK_RXFIFOHFIE_Pos (15U) 6306 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ 6307 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ 6308 #define SDIO_MASK_TXFIFOFIE_Pos (16U) 6309 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ 6310 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ 6311 #define SDIO_MASK_RXFIFOFIE_Pos (17U) 6312 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ 6313 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ 6314 #define SDIO_MASK_TXFIFOEIE_Pos (18U) 6315 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ 6316 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ 6317 #define SDIO_MASK_RXFIFOEIE_Pos (19U) 6318 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ 6319 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ 6320 #define SDIO_MASK_TXDAVLIE_Pos (20U) 6321 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ 6322 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ 6323 #define SDIO_MASK_RXDAVLIE_Pos (21U) 6324 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ 6325 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ 6326 #define SDIO_MASK_SDIOITIE_Pos (22U) 6327 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ 6328 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ 6329 #define SDIO_MASK_CEATAENDIE_Pos (23U) 6330 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ 6331 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ 6332 6333 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 6334 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) 6335 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ 6336 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ 6337 6338 /****************** Bit definition for SDIO_FIFO register *******************/ 6339 #define SDIO_FIFO_FIFODATA_Pos (0U) 6340 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ 6341 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ 6342 6343 /******************************************************************************/ 6344 /* */ 6345 /* Serial Peripheral Interface (SPI) */ 6346 /* */ 6347 /******************************************************************************/ 6348 6349 /* 6350 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) 6351 */ 6352 #define SPI_I2S_SUPPORT 6353 6354 /******************* Bit definition for SPI_CR1 register ********************/ 6355 #define SPI_CR1_CPHA_Pos (0U) 6356 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 6357 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 6358 #define SPI_CR1_CPOL_Pos (1U) 6359 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 6360 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 6361 #define SPI_CR1_MSTR_Pos (2U) 6362 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 6363 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 6364 6365 #define SPI_CR1_BR_Pos (3U) 6366 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 6367 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 6368 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 6369 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 6370 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 6371 6372 #define SPI_CR1_SPE_Pos (6U) 6373 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 6374 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 6375 #define SPI_CR1_LSBFIRST_Pos (7U) 6376 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 6377 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 6378 #define SPI_CR1_SSI_Pos (8U) 6379 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 6380 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 6381 #define SPI_CR1_SSM_Pos (9U) 6382 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 6383 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 6384 #define SPI_CR1_RXONLY_Pos (10U) 6385 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 6386 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 6387 #define SPI_CR1_DFF_Pos (11U) 6388 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 6389 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 6390 #define SPI_CR1_CRCNEXT_Pos (12U) 6391 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 6392 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 6393 #define SPI_CR1_CRCEN_Pos (13U) 6394 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 6395 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 6396 #define SPI_CR1_BIDIOE_Pos (14U) 6397 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 6398 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 6399 #define SPI_CR1_BIDIMODE_Pos (15U) 6400 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 6401 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 6402 6403 /******************* Bit definition for SPI_CR2 register ********************/ 6404 #define SPI_CR2_RXDMAEN_Pos (0U) 6405 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 6406 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 6407 #define SPI_CR2_TXDMAEN_Pos (1U) 6408 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 6409 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 6410 #define SPI_CR2_SSOE_Pos (2U) 6411 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 6412 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 6413 #define SPI_CR2_FRF_Pos (4U) 6414 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 6415 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */ 6416 #define SPI_CR2_ERRIE_Pos (5U) 6417 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 6418 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 6419 #define SPI_CR2_RXNEIE_Pos (6U) 6420 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 6421 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 6422 #define SPI_CR2_TXEIE_Pos (7U) 6423 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 6424 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 6425 6426 /******************** Bit definition for SPI_SR register ********************/ 6427 #define SPI_SR_RXNE_Pos (0U) 6428 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 6429 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 6430 #define SPI_SR_TXE_Pos (1U) 6431 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 6432 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 6433 #define SPI_SR_CHSIDE_Pos (2U) 6434 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 6435 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 6436 #define SPI_SR_UDR_Pos (3U) 6437 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 6438 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 6439 #define SPI_SR_CRCERR_Pos (4U) 6440 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 6441 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 6442 #define SPI_SR_MODF_Pos (5U) 6443 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 6444 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 6445 #define SPI_SR_OVR_Pos (6U) 6446 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 6447 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 6448 #define SPI_SR_BSY_Pos (7U) 6449 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 6450 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 6451 #define SPI_SR_FRE_Pos (8U) 6452 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 6453 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ 6454 6455 /******************** Bit definition for SPI_DR register ********************/ 6456 #define SPI_DR_DR_Pos (0U) 6457 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 6458 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 6459 6460 /******************* Bit definition for SPI_CRCPR register ******************/ 6461 #define SPI_CRCPR_CRCPOLY_Pos (0U) 6462 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 6463 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 6464 6465 /****************** Bit definition for SPI_RXCRCR register ******************/ 6466 #define SPI_RXCRCR_RXCRC_Pos (0U) 6467 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 6468 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 6469 6470 /****************** Bit definition for SPI_TXCRCR register ******************/ 6471 #define SPI_TXCRCR_TXCRC_Pos (0U) 6472 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 6473 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 6474 6475 /****************** Bit definition for SPI_I2SCFGR register *****************/ 6476 #define SPI_I2SCFGR_CHLEN_Pos (0U) 6477 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 6478 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 6479 6480 #define SPI_I2SCFGR_DATLEN_Pos (1U) 6481 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 6482 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 6483 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 6484 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 6485 6486 #define SPI_I2SCFGR_CKPOL_Pos (3U) 6487 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 6488 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 6489 6490 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 6491 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 6492 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 6493 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 6494 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 6495 6496 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 6497 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 6498 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 6499 6500 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 6501 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 6502 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 6503 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 6504 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 6505 6506 #define SPI_I2SCFGR_I2SE_Pos (10U) 6507 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 6508 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 6509 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 6510 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 6511 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 6512 6513 /****************** Bit definition for SPI_I2SPR register *******************/ 6514 #define SPI_I2SPR_I2SDIV_Pos (0U) 6515 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 6516 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 6517 #define SPI_I2SPR_ODD_Pos (8U) 6518 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 6519 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 6520 #define SPI_I2SPR_MCKOE_Pos (9U) 6521 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 6522 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 6523 6524 /******************************************************************************/ 6525 /* */ 6526 /* System Configuration (SYSCFG) */ 6527 /* */ 6528 /******************************************************************************/ 6529 /***************** Bit definition for SYSCFG_MEMRMP register ****************/ 6530 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 6531 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ 6532 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 6533 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 6534 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 6535 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) 6536 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */ 6537 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */ 6538 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */ 6539 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2UL << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */ 6540 6541 /***************** Bit definition for SYSCFG_PMC register *******************/ 6542 #define SYSCFG_PMC_USB_PU_Pos (0U) 6543 #define SYSCFG_PMC_USB_PU_Msk (0x1UL << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */ 6544 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */ 6545 #define SYSCFG_PMC_LCD_CAPA_Pos (1U) 6546 #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FUL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */ 6547 #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */ 6548 #define SYSCFG_PMC_LCD_CAPA_0 (0x01UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */ 6549 #define SYSCFG_PMC_LCD_CAPA_1 (0x02UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */ 6550 #define SYSCFG_PMC_LCD_CAPA_2 (0x04UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */ 6551 #define SYSCFG_PMC_LCD_CAPA_3 (0x08UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */ 6552 #define SYSCFG_PMC_LCD_CAPA_4 (0x10UL << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */ 6553 6554 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 6555 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 6556 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 6557 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 6558 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 6559 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 6560 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 6561 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 6562 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 6563 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 6564 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 6565 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 6566 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 6567 6568 /** 6569 * @brief EXTI0 configuration 6570 */ 6571 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 6572 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 6573 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 6574 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 6575 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 6576 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 6577 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */ 6578 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */ 6579 6580 /** 6581 * @brief EXTI1 configuration 6582 */ 6583 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 6584 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 6585 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 6586 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 6587 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 6588 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 6589 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */ 6590 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */ 6591 6592 /** 6593 * @brief EXTI2 configuration 6594 */ 6595 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 6596 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 6597 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 6598 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 6599 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 6600 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */ 6601 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */ 6602 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */ 6603 6604 /** 6605 * @brief EXTI3 configuration 6606 */ 6607 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 6608 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 6609 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 6610 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 6611 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 6612 #define SYSCFG_EXTICR1_EXTI3_PF (0x00006000U) /*!< PF[3] pin */ 6613 #define SYSCFG_EXTICR1_EXTI3_PG (0x00007000U) /*!< PG[3] pin */ 6614 6615 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 6616 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 6617 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 6618 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 6619 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 6620 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 6621 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 6622 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 6623 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 6624 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 6625 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 6626 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 6627 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 6628 6629 /** 6630 * @brief EXTI4 configuration 6631 */ 6632 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 6633 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 6634 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 6635 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 6636 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 6637 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */ 6638 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */ 6639 6640 /** 6641 * @brief EXTI5 configuration 6642 */ 6643 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 6644 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 6645 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 6646 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 6647 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 6648 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */ 6649 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */ 6650 6651 /** 6652 * @brief EXTI6 configuration 6653 */ 6654 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 6655 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 6656 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 6657 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 6658 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 6659 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */ 6660 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */ 6661 6662 /** 6663 * @brief EXTI7 configuration 6664 */ 6665 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 6666 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 6667 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 6668 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 6669 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 6670 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */ 6671 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */ 6672 6673 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 6674 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 6675 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 6676 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 6677 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 6678 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 6679 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 6680 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 6681 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 6682 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 6683 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 6684 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 6685 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 6686 6687 /** 6688 * @brief EXTI8 configuration 6689 */ 6690 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 6691 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 6692 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 6693 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 6694 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 6695 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */ 6696 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */ 6697 6698 /** 6699 * @brief EXTI9 configuration 6700 */ 6701 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 6702 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 6703 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 6704 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 6705 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 6706 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */ 6707 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */ 6708 6709 /** 6710 * @brief EXTI10 configuration 6711 */ 6712 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 6713 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 6714 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 6715 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 6716 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 6717 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */ 6718 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */ 6719 6720 /** 6721 * @brief EXTI11 configuration 6722 */ 6723 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 6724 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 6725 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 6726 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 6727 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 6728 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */ 6729 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */ 6730 6731 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 6732 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 6733 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 6734 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 6735 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 6736 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 6737 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 6738 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 6739 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 6740 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 6741 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 6742 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 6743 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 6744 6745 /** 6746 * @brief EXTI12 configuration 6747 */ 6748 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 6749 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 6750 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 6751 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 6752 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 6753 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */ 6754 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */ 6755 6756 /** 6757 * @brief EXTI13 configuration 6758 */ 6759 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 6760 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 6761 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 6762 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 6763 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 6764 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */ 6765 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */ 6766 6767 /** 6768 * @brief EXTI14 configuration 6769 */ 6770 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 6771 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 6772 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 6773 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 6774 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 6775 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */ 6776 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */ 6777 6778 /** 6779 * @brief EXTI15 configuration 6780 */ 6781 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 6782 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 6783 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 6784 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 6785 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 6786 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ 6787 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ 6788 6789 /******************************************************************************/ 6790 /* */ 6791 /* Routing Interface (RI) */ 6792 /* */ 6793 /******************************************************************************/ 6794 6795 /******************** Bit definition for RI_ICR register ********************/ 6796 #define RI_ICR_IC1OS_Pos (0U) 6797 #define RI_ICR_IC1OS_Msk (0xFUL << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */ 6798 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */ 6799 #define RI_ICR_IC1OS_0 (0x1UL << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */ 6800 #define RI_ICR_IC1OS_1 (0x2UL << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */ 6801 #define RI_ICR_IC1OS_2 (0x4UL << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */ 6802 #define RI_ICR_IC1OS_3 (0x8UL << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */ 6803 6804 #define RI_ICR_IC2OS_Pos (4U) 6805 #define RI_ICR_IC2OS_Msk (0xFUL << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */ 6806 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */ 6807 #define RI_ICR_IC2OS_0 (0x1UL << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */ 6808 #define RI_ICR_IC2OS_1 (0x2UL << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */ 6809 #define RI_ICR_IC2OS_2 (0x4UL << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */ 6810 #define RI_ICR_IC2OS_3 (0x8UL << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */ 6811 6812 #define RI_ICR_IC3OS_Pos (8U) 6813 #define RI_ICR_IC3OS_Msk (0xFUL << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */ 6814 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */ 6815 #define RI_ICR_IC3OS_0 (0x1UL << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */ 6816 #define RI_ICR_IC3OS_1 (0x2UL << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */ 6817 #define RI_ICR_IC3OS_2 (0x4UL << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */ 6818 #define RI_ICR_IC3OS_3 (0x8UL << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */ 6819 6820 #define RI_ICR_IC4OS_Pos (12U) 6821 #define RI_ICR_IC4OS_Msk (0xFUL << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */ 6822 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */ 6823 #define RI_ICR_IC4OS_0 (0x1UL << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */ 6824 #define RI_ICR_IC4OS_1 (0x2UL << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */ 6825 #define RI_ICR_IC4OS_2 (0x4UL << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */ 6826 #define RI_ICR_IC4OS_3 (0x8UL << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */ 6827 6828 #define RI_ICR_TIM_Pos (16U) 6829 #define RI_ICR_TIM_Msk (0x3UL << RI_ICR_TIM_Pos) /*!< 0x00030000 */ 6830 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */ 6831 #define RI_ICR_TIM_0 (0x1UL << RI_ICR_TIM_Pos) /*!< 0x00010000 */ 6832 #define RI_ICR_TIM_1 (0x2UL << RI_ICR_TIM_Pos) /*!< 0x00020000 */ 6833 6834 #define RI_ICR_IC1_Pos (18U) 6835 #define RI_ICR_IC1_Msk (0x1UL << RI_ICR_IC1_Pos) /*!< 0x00040000 */ 6836 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */ 6837 #define RI_ICR_IC2_Pos (19U) 6838 #define RI_ICR_IC2_Msk (0x1UL << RI_ICR_IC2_Pos) /*!< 0x00080000 */ 6839 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */ 6840 #define RI_ICR_IC3_Pos (20U) 6841 #define RI_ICR_IC3_Msk (0x1UL << RI_ICR_IC3_Pos) /*!< 0x00100000 */ 6842 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */ 6843 #define RI_ICR_IC4_Pos (21U) 6844 #define RI_ICR_IC4_Msk (0x1UL << RI_ICR_IC4_Pos) /*!< 0x00200000 */ 6845 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */ 6846 6847 /******************** Bit definition for RI_ASCR1 register ********************/ 6848 #define RI_ASCR1_CH_Pos (0U) 6849 #define RI_ASCR1_CH_Msk (0x7BFDFFFFUL << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */ 6850 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */ 6851 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */ 6852 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */ 6853 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */ 6854 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */ 6855 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */ 6856 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */ 6857 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */ 6858 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */ 6859 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */ 6860 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */ 6861 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */ 6862 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */ 6863 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */ 6864 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */ 6865 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */ 6866 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */ 6867 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */ 6868 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */ 6869 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */ 6870 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */ 6871 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */ 6872 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */ 6873 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */ 6874 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */ 6875 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */ 6876 #define RI_ASCR1_VCOMP_Pos (26U) 6877 #define RI_ASCR1_VCOMP_Msk (0x1UL << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */ 6878 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */ 6879 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */ 6880 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */ 6881 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */ 6882 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */ 6883 #define RI_ASCR1_SCM_Pos (31U) 6884 #define RI_ASCR1_SCM_Msk (0x1UL << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */ 6885 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */ 6886 6887 /******************** Bit definition for RI_ASCR2 register ********************/ 6888 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */ 6889 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */ 6890 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */ 6891 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */ 6892 #define RI_ASCR2_GR6_Pos (4U) 6893 #define RI_ASCR2_GR6_Msk (0x1800003UL << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */ 6894 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */ 6895 #define RI_ASCR2_GR6_1 (0x0000001UL << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */ 6896 #define RI_ASCR2_GR6_2 (0x0000002UL << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */ 6897 #define RI_ASCR2_GR6_3 (0x0800000UL << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */ 6898 #define RI_ASCR2_GR6_4 (0x1000000UL << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */ 6899 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */ 6900 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */ 6901 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */ 6902 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */ 6903 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */ 6904 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */ 6905 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */ 6906 #define RI_ASCR2_CH0b_Pos (16U) 6907 #define RI_ASCR2_CH0b_Msk (0x1UL << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */ 6908 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */ 6909 #define RI_ASCR2_CH1b_Pos (17U) 6910 #define RI_ASCR2_CH1b_Msk (0x1UL << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */ 6911 #define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */ 6912 #define RI_ASCR2_CH2b_Pos (18U) 6913 #define RI_ASCR2_CH2b_Msk (0x1UL << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */ 6914 #define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */ 6915 #define RI_ASCR2_CH3b_Pos (19U) 6916 #define RI_ASCR2_CH3b_Msk (0x1UL << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */ 6917 #define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */ 6918 #define RI_ASCR2_CH6b_Pos (20U) 6919 #define RI_ASCR2_CH6b_Msk (0x1UL << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */ 6920 #define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */ 6921 #define RI_ASCR2_CH7b_Pos (21U) 6922 #define RI_ASCR2_CH7b_Msk (0x1UL << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */ 6923 #define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */ 6924 #define RI_ASCR2_CH8b_Pos (22U) 6925 #define RI_ASCR2_CH8b_Msk (0x1UL << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */ 6926 #define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */ 6927 #define RI_ASCR2_CH9b_Pos (23U) 6928 #define RI_ASCR2_CH9b_Msk (0x1UL << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */ 6929 #define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */ 6930 #define RI_ASCR2_CH10b_Pos (24U) 6931 #define RI_ASCR2_CH10b_Msk (0x1UL << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */ 6932 #define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */ 6933 #define RI_ASCR2_CH11b_Pos (25U) 6934 #define RI_ASCR2_CH11b_Msk (0x1UL << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */ 6935 #define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */ 6936 #define RI_ASCR2_CH12b_Pos (26U) 6937 #define RI_ASCR2_CH12b_Msk (0x1UL << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */ 6938 #define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */ 6939 6940 /******************** Bit definition for RI_HYSCR1 register ********************/ 6941 #define RI_HYSCR1_PA_Pos (0U) 6942 #define RI_HYSCR1_PA_Msk (0xFFFFUL << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */ 6943 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */ 6944 #define RI_HYSCR1_PA_0 (0x0001UL << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */ 6945 #define RI_HYSCR1_PA_1 (0x0002UL << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */ 6946 #define RI_HYSCR1_PA_2 (0x0004UL << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */ 6947 #define RI_HYSCR1_PA_3 (0x0008UL << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */ 6948 #define RI_HYSCR1_PA_4 (0x0010UL << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */ 6949 #define RI_HYSCR1_PA_5 (0x0020UL << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */ 6950 #define RI_HYSCR1_PA_6 (0x0040UL << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */ 6951 #define RI_HYSCR1_PA_7 (0x0080UL << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */ 6952 #define RI_HYSCR1_PA_8 (0x0100UL << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */ 6953 #define RI_HYSCR1_PA_9 (0x0200UL << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */ 6954 #define RI_HYSCR1_PA_10 (0x0400UL << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */ 6955 #define RI_HYSCR1_PA_11 (0x0800UL << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */ 6956 #define RI_HYSCR1_PA_12 (0x1000UL << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */ 6957 #define RI_HYSCR1_PA_13 (0x2000UL << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */ 6958 #define RI_HYSCR1_PA_14 (0x4000UL << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */ 6959 #define RI_HYSCR1_PA_15 (0x8000UL << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */ 6960 6961 #define RI_HYSCR1_PB_Pos (16U) 6962 #define RI_HYSCR1_PB_Msk (0xFFFFUL << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */ 6963 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */ 6964 #define RI_HYSCR1_PB_0 (0x0001UL << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */ 6965 #define RI_HYSCR1_PB_1 (0x0002UL << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */ 6966 #define RI_HYSCR1_PB_2 (0x0004UL << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */ 6967 #define RI_HYSCR1_PB_3 (0x0008UL << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */ 6968 #define RI_HYSCR1_PB_4 (0x0010UL << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */ 6969 #define RI_HYSCR1_PB_5 (0x0020UL << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */ 6970 #define RI_HYSCR1_PB_6 (0x0040UL << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */ 6971 #define RI_HYSCR1_PB_7 (0x0080UL << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */ 6972 #define RI_HYSCR1_PB_8 (0x0100UL << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */ 6973 #define RI_HYSCR1_PB_9 (0x0200UL << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */ 6974 #define RI_HYSCR1_PB_10 (0x0400UL << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */ 6975 #define RI_HYSCR1_PB_11 (0x0800UL << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */ 6976 #define RI_HYSCR1_PB_12 (0x1000UL << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */ 6977 #define RI_HYSCR1_PB_13 (0x2000UL << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */ 6978 #define RI_HYSCR1_PB_14 (0x4000UL << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */ 6979 #define RI_HYSCR1_PB_15 (0x8000UL << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */ 6980 6981 /******************** Bit definition for RI_HYSCR2 register ********************/ 6982 #define RI_HYSCR2_PC_Pos (0U) 6983 #define RI_HYSCR2_PC_Msk (0xFFFFUL << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */ 6984 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */ 6985 #define RI_HYSCR2_PC_0 (0x0001UL << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */ 6986 #define RI_HYSCR2_PC_1 (0x0002UL << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */ 6987 #define RI_HYSCR2_PC_2 (0x0004UL << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */ 6988 #define RI_HYSCR2_PC_3 (0x0008UL << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */ 6989 #define RI_HYSCR2_PC_4 (0x0010UL << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */ 6990 #define RI_HYSCR2_PC_5 (0x0020UL << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */ 6991 #define RI_HYSCR2_PC_6 (0x0040UL << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */ 6992 #define RI_HYSCR2_PC_7 (0x0080UL << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */ 6993 #define RI_HYSCR2_PC_8 (0x0100UL << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */ 6994 #define RI_HYSCR2_PC_9 (0x0200UL << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */ 6995 #define RI_HYSCR2_PC_10 (0x0400UL << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */ 6996 #define RI_HYSCR2_PC_11 (0x0800UL << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */ 6997 #define RI_HYSCR2_PC_12 (0x1000UL << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */ 6998 #define RI_HYSCR2_PC_13 (0x2000UL << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */ 6999 #define RI_HYSCR2_PC_14 (0x4000UL << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */ 7000 #define RI_HYSCR2_PC_15 (0x8000UL << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */ 7001 7002 #define RI_HYSCR2_PD_Pos (16U) 7003 #define RI_HYSCR2_PD_Msk (0xFFFFUL << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */ 7004 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */ 7005 #define RI_HYSCR2_PD_0 (0x0001UL << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */ 7006 #define RI_HYSCR2_PD_1 (0x0002UL << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */ 7007 #define RI_HYSCR2_PD_2 (0x0004UL << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */ 7008 #define RI_HYSCR2_PD_3 (0x0008UL << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */ 7009 #define RI_HYSCR2_PD_4 (0x0010UL << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */ 7010 #define RI_HYSCR2_PD_5 (0x0020UL << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */ 7011 #define RI_HYSCR2_PD_6 (0x0040UL << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */ 7012 #define RI_HYSCR2_PD_7 (0x0080UL << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */ 7013 #define RI_HYSCR2_PD_8 (0x0100UL << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */ 7014 #define RI_HYSCR2_PD_9 (0x0200UL << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */ 7015 #define RI_HYSCR2_PD_10 (0x0400UL << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */ 7016 #define RI_HYSCR2_PD_11 (0x0800UL << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */ 7017 #define RI_HYSCR2_PD_12 (0x1000UL << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */ 7018 #define RI_HYSCR2_PD_13 (0x2000UL << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */ 7019 #define RI_HYSCR2_PD_14 (0x4000UL << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ 7020 #define RI_HYSCR2_PD_15 (0x8000UL << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ 7021 7022 /******************** Bit definition for RI_HYSCR3 register ********************/ 7023 #define RI_HYSCR3_PE_Pos (0U) 7024 #define RI_HYSCR3_PE_Msk (0xFFFFUL << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ 7025 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ 7026 #define RI_HYSCR3_PE_0 (0x0001UL << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ 7027 #define RI_HYSCR3_PE_1 (0x0002UL << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ 7028 #define RI_HYSCR3_PE_2 (0x0004UL << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ 7029 #define RI_HYSCR3_PE_3 (0x0008UL << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ 7030 #define RI_HYSCR3_PE_4 (0x0010UL << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ 7031 #define RI_HYSCR3_PE_5 (0x0020UL << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ 7032 #define RI_HYSCR3_PE_6 (0x0040UL << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ 7033 #define RI_HYSCR3_PE_7 (0x0080UL << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ 7034 #define RI_HYSCR3_PE_8 (0x0100UL << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ 7035 #define RI_HYSCR3_PE_9 (0x0200UL << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ 7036 #define RI_HYSCR3_PE_10 (0x0400UL << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ 7037 #define RI_HYSCR3_PE_11 (0x0800UL << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ 7038 #define RI_HYSCR3_PE_12 (0x1000UL << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ 7039 #define RI_HYSCR3_PE_13 (0x2000UL << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ 7040 #define RI_HYSCR3_PE_14 (0x4000UL << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ 7041 #define RI_HYSCR3_PE_15 (0x8000UL << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ 7042 #define RI_HYSCR3_PF_Pos (16U) 7043 #define RI_HYSCR3_PF_Msk (0xFFFFUL << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ 7044 #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ 7045 #define RI_HYSCR3_PF_0 (0x0001UL << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ 7046 #define RI_HYSCR3_PF_1 (0x0002UL << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ 7047 #define RI_HYSCR3_PF_2 (0x0004UL << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ 7048 #define RI_HYSCR3_PF_3 (0x0008UL << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ 7049 #define RI_HYSCR3_PF_4 (0x0010UL << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ 7050 #define RI_HYSCR3_PF_5 (0x0020UL << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ 7051 #define RI_HYSCR3_PF_6 (0x0040UL << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ 7052 #define RI_HYSCR3_PF_7 (0x0080UL << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ 7053 #define RI_HYSCR3_PF_8 (0x0100UL << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ 7054 #define RI_HYSCR3_PF_9 (0x0200UL << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ 7055 #define RI_HYSCR3_PF_10 (0x0400UL << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ 7056 #define RI_HYSCR3_PF_11 (0x0800UL << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ 7057 #define RI_HYSCR3_PF_12 (0x1000UL << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ 7058 #define RI_HYSCR3_PF_13 (0x2000UL << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ 7059 #define RI_HYSCR3_PF_14 (0x4000UL << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ 7060 #define RI_HYSCR3_PF_15 (0x8000UL << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ 7061 /******************** Bit definition for RI_HYSCR4 register ********************/ 7062 #define RI_HYSCR4_PG_Pos (0U) 7063 #define RI_HYSCR4_PG_Msk (0xFFFFUL << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ 7064 #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ 7065 #define RI_HYSCR4_PG_0 (0x0001UL << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ 7066 #define RI_HYSCR4_PG_1 (0x0002UL << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ 7067 #define RI_HYSCR4_PG_2 (0x0004UL << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ 7068 #define RI_HYSCR4_PG_3 (0x0008UL << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ 7069 #define RI_HYSCR4_PG_4 (0x0010UL << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ 7070 #define RI_HYSCR4_PG_5 (0x0020UL << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ 7071 #define RI_HYSCR4_PG_6 (0x0040UL << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ 7072 #define RI_HYSCR4_PG_7 (0x0080UL << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ 7073 #define RI_HYSCR4_PG_8 (0x0100UL << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ 7074 #define RI_HYSCR4_PG_9 (0x0200UL << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ 7075 #define RI_HYSCR4_PG_10 (0x0400UL << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ 7076 #define RI_HYSCR4_PG_11 (0x0800UL << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ 7077 #define RI_HYSCR4_PG_12 (0x1000UL << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ 7078 #define RI_HYSCR4_PG_13 (0x2000UL << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ 7079 #define RI_HYSCR4_PG_14 (0x4000UL << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ 7080 #define RI_HYSCR4_PG_15 (0x8000UL << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ 7081 7082 /******************** Bit definition for RI_ASMR1 register ********************/ 7083 #define RI_ASMR1_PA_Pos (0U) 7084 #define RI_ASMR1_PA_Msk (0xFFFFUL << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */ 7085 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 7086 #define RI_ASMR1_PA_0 (0x0001UL << RI_ASMR1_PA_Pos) /*!< 0x00000001 */ 7087 #define RI_ASMR1_PA_1 (0x0002UL << RI_ASMR1_PA_Pos) /*!< 0x00000002 */ 7088 #define RI_ASMR1_PA_2 (0x0004UL << RI_ASMR1_PA_Pos) /*!< 0x00000004 */ 7089 #define RI_ASMR1_PA_3 (0x0008UL << RI_ASMR1_PA_Pos) /*!< 0x00000008 */ 7090 #define RI_ASMR1_PA_4 (0x0010UL << RI_ASMR1_PA_Pos) /*!< 0x00000010 */ 7091 #define RI_ASMR1_PA_5 (0x0020UL << RI_ASMR1_PA_Pos) /*!< 0x00000020 */ 7092 #define RI_ASMR1_PA_6 (0x0040UL << RI_ASMR1_PA_Pos) /*!< 0x00000040 */ 7093 #define RI_ASMR1_PA_7 (0x0080UL << RI_ASMR1_PA_Pos) /*!< 0x00000080 */ 7094 #define RI_ASMR1_PA_8 (0x0100UL << RI_ASMR1_PA_Pos) /*!< 0x00000100 */ 7095 #define RI_ASMR1_PA_9 (0x0200UL << RI_ASMR1_PA_Pos) /*!< 0x00000200 */ 7096 #define RI_ASMR1_PA_10 (0x0400UL << RI_ASMR1_PA_Pos) /*!< 0x00000400 */ 7097 #define RI_ASMR1_PA_11 (0x0800UL << RI_ASMR1_PA_Pos) /*!< 0x00000800 */ 7098 #define RI_ASMR1_PA_12 (0x1000UL << RI_ASMR1_PA_Pos) /*!< 0x00001000 */ 7099 #define RI_ASMR1_PA_13 (0x2000UL << RI_ASMR1_PA_Pos) /*!< 0x00002000 */ 7100 #define RI_ASMR1_PA_14 (0x4000UL << RI_ASMR1_PA_Pos) /*!< 0x00004000 */ 7101 #define RI_ASMR1_PA_15 (0x8000UL << RI_ASMR1_PA_Pos) /*!< 0x00008000 */ 7102 7103 /******************** Bit definition for RI_CMR1 register ********************/ 7104 #define RI_CMR1_PA_Pos (0U) 7105 #define RI_CMR1_PA_Msk (0xFFFFUL << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */ 7106 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 7107 #define RI_CMR1_PA_0 (0x0001UL << RI_CMR1_PA_Pos) /*!< 0x00000001 */ 7108 #define RI_CMR1_PA_1 (0x0002UL << RI_CMR1_PA_Pos) /*!< 0x00000002 */ 7109 #define RI_CMR1_PA_2 (0x0004UL << RI_CMR1_PA_Pos) /*!< 0x00000004 */ 7110 #define RI_CMR1_PA_3 (0x0008UL << RI_CMR1_PA_Pos) /*!< 0x00000008 */ 7111 #define RI_CMR1_PA_4 (0x0010UL << RI_CMR1_PA_Pos) /*!< 0x00000010 */ 7112 #define RI_CMR1_PA_5 (0x0020UL << RI_CMR1_PA_Pos) /*!< 0x00000020 */ 7113 #define RI_CMR1_PA_6 (0x0040UL << RI_CMR1_PA_Pos) /*!< 0x00000040 */ 7114 #define RI_CMR1_PA_7 (0x0080UL << RI_CMR1_PA_Pos) /*!< 0x00000080 */ 7115 #define RI_CMR1_PA_8 (0x0100UL << RI_CMR1_PA_Pos) /*!< 0x00000100 */ 7116 #define RI_CMR1_PA_9 (0x0200UL << RI_CMR1_PA_Pos) /*!< 0x00000200 */ 7117 #define RI_CMR1_PA_10 (0x0400UL << RI_CMR1_PA_Pos) /*!< 0x00000400 */ 7118 #define RI_CMR1_PA_11 (0x0800UL << RI_CMR1_PA_Pos) /*!< 0x00000800 */ 7119 #define RI_CMR1_PA_12 (0x1000UL << RI_CMR1_PA_Pos) /*!< 0x00001000 */ 7120 #define RI_CMR1_PA_13 (0x2000UL << RI_CMR1_PA_Pos) /*!< 0x00002000 */ 7121 #define RI_CMR1_PA_14 (0x4000UL << RI_CMR1_PA_Pos) /*!< 0x00004000 */ 7122 #define RI_CMR1_PA_15 (0x8000UL << RI_CMR1_PA_Pos) /*!< 0x00008000 */ 7123 7124 /******************** Bit definition for RI_CICR1 register ********************/ 7125 #define RI_CICR1_PA_Pos (0U) 7126 #define RI_CICR1_PA_Msk (0xFFFFUL << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */ 7127 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/ 7128 #define RI_CICR1_PA_0 (0x0001UL << RI_CICR1_PA_Pos) /*!< 0x00000001 */ 7129 #define RI_CICR1_PA_1 (0x0002UL << RI_CICR1_PA_Pos) /*!< 0x00000002 */ 7130 #define RI_CICR1_PA_2 (0x0004UL << RI_CICR1_PA_Pos) /*!< 0x00000004 */ 7131 #define RI_CICR1_PA_3 (0x0008UL << RI_CICR1_PA_Pos) /*!< 0x00000008 */ 7132 #define RI_CICR1_PA_4 (0x0010UL << RI_CICR1_PA_Pos) /*!< 0x00000010 */ 7133 #define RI_CICR1_PA_5 (0x0020UL << RI_CICR1_PA_Pos) /*!< 0x00000020 */ 7134 #define RI_CICR1_PA_6 (0x0040UL << RI_CICR1_PA_Pos) /*!< 0x00000040 */ 7135 #define RI_CICR1_PA_7 (0x0080UL << RI_CICR1_PA_Pos) /*!< 0x00000080 */ 7136 #define RI_CICR1_PA_8 (0x0100UL << RI_CICR1_PA_Pos) /*!< 0x00000100 */ 7137 #define RI_CICR1_PA_9 (0x0200UL << RI_CICR1_PA_Pos) /*!< 0x00000200 */ 7138 #define RI_CICR1_PA_10 (0x0400UL << RI_CICR1_PA_Pos) /*!< 0x00000400 */ 7139 #define RI_CICR1_PA_11 (0x0800UL << RI_CICR1_PA_Pos) /*!< 0x00000800 */ 7140 #define RI_CICR1_PA_12 (0x1000UL << RI_CICR1_PA_Pos) /*!< 0x00001000 */ 7141 #define RI_CICR1_PA_13 (0x2000UL << RI_CICR1_PA_Pos) /*!< 0x00002000 */ 7142 #define RI_CICR1_PA_14 (0x4000UL << RI_CICR1_PA_Pos) /*!< 0x00004000 */ 7143 #define RI_CICR1_PA_15 (0x8000UL << RI_CICR1_PA_Pos) /*!< 0x00008000 */ 7144 7145 /******************** Bit definition for RI_ASMR2 register ********************/ 7146 #define RI_ASMR2_PB_Pos (0U) 7147 #define RI_ASMR2_PB_Msk (0xFFFFUL << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */ 7148 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */ 7149 #define RI_ASMR2_PB_0 (0x0001UL << RI_ASMR2_PB_Pos) /*!< 0x00000001 */ 7150 #define RI_ASMR2_PB_1 (0x0002UL << RI_ASMR2_PB_Pos) /*!< 0x00000002 */ 7151 #define RI_ASMR2_PB_2 (0x0004UL << RI_ASMR2_PB_Pos) /*!< 0x00000004 */ 7152 #define RI_ASMR2_PB_3 (0x0008UL << RI_ASMR2_PB_Pos) /*!< 0x00000008 */ 7153 #define RI_ASMR2_PB_4 (0x0010UL << RI_ASMR2_PB_Pos) /*!< 0x00000010 */ 7154 #define RI_ASMR2_PB_5 (0x0020UL << RI_ASMR2_PB_Pos) /*!< 0x00000020 */ 7155 #define RI_ASMR2_PB_6 (0x0040UL << RI_ASMR2_PB_Pos) /*!< 0x00000040 */ 7156 #define RI_ASMR2_PB_7 (0x0080UL << RI_ASMR2_PB_Pos) /*!< 0x00000080 */ 7157 #define RI_ASMR2_PB_8 (0x0100UL << RI_ASMR2_PB_Pos) /*!< 0x00000100 */ 7158 #define RI_ASMR2_PB_9 (0x0200UL << RI_ASMR2_PB_Pos) /*!< 0x00000200 */ 7159 #define RI_ASMR2_PB_10 (0x0400UL << RI_ASMR2_PB_Pos) /*!< 0x00000400 */ 7160 #define RI_ASMR2_PB_11 (0x0800UL << RI_ASMR2_PB_Pos) /*!< 0x00000800 */ 7161 #define RI_ASMR2_PB_12 (0x1000UL << RI_ASMR2_PB_Pos) /*!< 0x00001000 */ 7162 #define RI_ASMR2_PB_13 (0x2000UL << RI_ASMR2_PB_Pos) /*!< 0x00002000 */ 7163 #define RI_ASMR2_PB_14 (0x4000UL << RI_ASMR2_PB_Pos) /*!< 0x00004000 */ 7164 #define RI_ASMR2_PB_15 (0x8000UL << RI_ASMR2_PB_Pos) /*!< 0x00008000 */ 7165 7166 /******************** Bit definition for RI_CMR2 register ********************/ 7167 #define RI_CMR2_PB_Pos (0U) 7168 #define RI_CMR2_PB_Msk (0xFFFFUL << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */ 7169 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */ 7170 #define RI_CMR2_PB_0 (0x0001UL << RI_CMR2_PB_Pos) /*!< 0x00000001 */ 7171 #define RI_CMR2_PB_1 (0x0002UL << RI_CMR2_PB_Pos) /*!< 0x00000002 */ 7172 #define RI_CMR2_PB_2 (0x0004UL << RI_CMR2_PB_Pos) /*!< 0x00000004 */ 7173 #define RI_CMR2_PB_3 (0x0008UL << RI_CMR2_PB_Pos) /*!< 0x00000008 */ 7174 #define RI_CMR2_PB_4 (0x0010UL << RI_CMR2_PB_Pos) /*!< 0x00000010 */ 7175 #define RI_CMR2_PB_5 (0x0020UL << RI_CMR2_PB_Pos) /*!< 0x00000020 */ 7176 #define RI_CMR2_PB_6 (0x0040UL << RI_CMR2_PB_Pos) /*!< 0x00000040 */ 7177 #define RI_CMR2_PB_7 (0x0080UL << RI_CMR2_PB_Pos) /*!< 0x00000080 */ 7178 #define RI_CMR2_PB_8 (0x0100UL << RI_CMR2_PB_Pos) /*!< 0x00000100 */ 7179 #define RI_CMR2_PB_9 (0x0200UL << RI_CMR2_PB_Pos) /*!< 0x00000200 */ 7180 #define RI_CMR2_PB_10 (0x0400UL << RI_CMR2_PB_Pos) /*!< 0x00000400 */ 7181 #define RI_CMR2_PB_11 (0x0800UL << RI_CMR2_PB_Pos) /*!< 0x00000800 */ 7182 #define RI_CMR2_PB_12 (0x1000UL << RI_CMR2_PB_Pos) /*!< 0x00001000 */ 7183 #define RI_CMR2_PB_13 (0x2000UL << RI_CMR2_PB_Pos) /*!< 0x00002000 */ 7184 #define RI_CMR2_PB_14 (0x4000UL << RI_CMR2_PB_Pos) /*!< 0x00004000 */ 7185 #define RI_CMR2_PB_15 (0x8000UL << RI_CMR2_PB_Pos) /*!< 0x00008000 */ 7186 7187 /******************** Bit definition for RI_CICR2 register ********************/ 7188 #define RI_CICR2_PB_Pos (0U) 7189 #define RI_CICR2_PB_Msk (0xFFFFUL << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */ 7190 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */ 7191 #define RI_CICR2_PB_0 (0x0001UL << RI_CICR2_PB_Pos) /*!< 0x00000001 */ 7192 #define RI_CICR2_PB_1 (0x0002UL << RI_CICR2_PB_Pos) /*!< 0x00000002 */ 7193 #define RI_CICR2_PB_2 (0x0004UL << RI_CICR2_PB_Pos) /*!< 0x00000004 */ 7194 #define RI_CICR2_PB_3 (0x0008UL << RI_CICR2_PB_Pos) /*!< 0x00000008 */ 7195 #define RI_CICR2_PB_4 (0x0010UL << RI_CICR2_PB_Pos) /*!< 0x00000010 */ 7196 #define RI_CICR2_PB_5 (0x0020UL << RI_CICR2_PB_Pos) /*!< 0x00000020 */ 7197 #define RI_CICR2_PB_6 (0x0040UL << RI_CICR2_PB_Pos) /*!< 0x00000040 */ 7198 #define RI_CICR2_PB_7 (0x0080UL << RI_CICR2_PB_Pos) /*!< 0x00000080 */ 7199 #define RI_CICR2_PB_8 (0x0100UL << RI_CICR2_PB_Pos) /*!< 0x00000100 */ 7200 #define RI_CICR2_PB_9 (0x0200UL << RI_CICR2_PB_Pos) /*!< 0x00000200 */ 7201 #define RI_CICR2_PB_10 (0x0400UL << RI_CICR2_PB_Pos) /*!< 0x00000400 */ 7202 #define RI_CICR2_PB_11 (0x0800UL << RI_CICR2_PB_Pos) /*!< 0x00000800 */ 7203 #define RI_CICR2_PB_12 (0x1000UL << RI_CICR2_PB_Pos) /*!< 0x00001000 */ 7204 #define RI_CICR2_PB_13 (0x2000UL << RI_CICR2_PB_Pos) /*!< 0x00002000 */ 7205 #define RI_CICR2_PB_14 (0x4000UL << RI_CICR2_PB_Pos) /*!< 0x00004000 */ 7206 #define RI_CICR2_PB_15 (0x8000UL << RI_CICR2_PB_Pos) /*!< 0x00008000 */ 7207 7208 /******************** Bit definition for RI_ASMR3 register ********************/ 7209 #define RI_ASMR3_PC_Pos (0U) 7210 #define RI_ASMR3_PC_Msk (0xFFFFUL << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */ 7211 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */ 7212 #define RI_ASMR3_PC_0 (0x0001UL << RI_ASMR3_PC_Pos) /*!< 0x00000001 */ 7213 #define RI_ASMR3_PC_1 (0x0002UL << RI_ASMR3_PC_Pos) /*!< 0x00000002 */ 7214 #define RI_ASMR3_PC_2 (0x0004UL << RI_ASMR3_PC_Pos) /*!< 0x00000004 */ 7215 #define RI_ASMR3_PC_3 (0x0008UL << RI_ASMR3_PC_Pos) /*!< 0x00000008 */ 7216 #define RI_ASMR3_PC_4 (0x0010UL << RI_ASMR3_PC_Pos) /*!< 0x00000010 */ 7217 #define RI_ASMR3_PC_5 (0x0020UL << RI_ASMR3_PC_Pos) /*!< 0x00000020 */ 7218 #define RI_ASMR3_PC_6 (0x0040UL << RI_ASMR3_PC_Pos) /*!< 0x00000040 */ 7219 #define RI_ASMR3_PC_7 (0x0080UL << RI_ASMR3_PC_Pos) /*!< 0x00000080 */ 7220 #define RI_ASMR3_PC_8 (0x0100UL << RI_ASMR3_PC_Pos) /*!< 0x00000100 */ 7221 #define RI_ASMR3_PC_9 (0x0200UL << RI_ASMR3_PC_Pos) /*!< 0x00000200 */ 7222 #define RI_ASMR3_PC_10 (0x0400UL << RI_ASMR3_PC_Pos) /*!< 0x00000400 */ 7223 #define RI_ASMR3_PC_11 (0x0800UL << RI_ASMR3_PC_Pos) /*!< 0x00000800 */ 7224 #define RI_ASMR3_PC_12 (0x1000UL << RI_ASMR3_PC_Pos) /*!< 0x00001000 */ 7225 #define RI_ASMR3_PC_13 (0x2000UL << RI_ASMR3_PC_Pos) /*!< 0x00002000 */ 7226 #define RI_ASMR3_PC_14 (0x4000UL << RI_ASMR3_PC_Pos) /*!< 0x00004000 */ 7227 #define RI_ASMR3_PC_15 (0x8000UL << RI_ASMR3_PC_Pos) /*!< 0x00008000 */ 7228 7229 /******************** Bit definition for RI_CMR3 register ********************/ 7230 #define RI_CMR3_PC_Pos (0U) 7231 #define RI_CMR3_PC_Msk (0xFFFFUL << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */ 7232 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */ 7233 #define RI_CMR3_PC_0 (0x0001UL << RI_CMR3_PC_Pos) /*!< 0x00000001 */ 7234 #define RI_CMR3_PC_1 (0x0002UL << RI_CMR3_PC_Pos) /*!< 0x00000002 */ 7235 #define RI_CMR3_PC_2 (0x0004UL << RI_CMR3_PC_Pos) /*!< 0x00000004 */ 7236 #define RI_CMR3_PC_3 (0x0008UL << RI_CMR3_PC_Pos) /*!< 0x00000008 */ 7237 #define RI_CMR3_PC_4 (0x0010UL << RI_CMR3_PC_Pos) /*!< 0x00000010 */ 7238 #define RI_CMR3_PC_5 (0x0020UL << RI_CMR3_PC_Pos) /*!< 0x00000020 */ 7239 #define RI_CMR3_PC_6 (0x0040UL << RI_CMR3_PC_Pos) /*!< 0x00000040 */ 7240 #define RI_CMR3_PC_7 (0x0080UL << RI_CMR3_PC_Pos) /*!< 0x00000080 */ 7241 #define RI_CMR3_PC_8 (0x0100UL << RI_CMR3_PC_Pos) /*!< 0x00000100 */ 7242 #define RI_CMR3_PC_9 (0x0200UL << RI_CMR3_PC_Pos) /*!< 0x00000200 */ 7243 #define RI_CMR3_PC_10 (0x0400UL << RI_CMR3_PC_Pos) /*!< 0x00000400 */ 7244 #define RI_CMR3_PC_11 (0x0800UL << RI_CMR3_PC_Pos) /*!< 0x00000800 */ 7245 #define RI_CMR3_PC_12 (0x1000UL << RI_CMR3_PC_Pos) /*!< 0x00001000 */ 7246 #define RI_CMR3_PC_13 (0x2000UL << RI_CMR3_PC_Pos) /*!< 0x00002000 */ 7247 #define RI_CMR3_PC_14 (0x4000UL << RI_CMR3_PC_Pos) /*!< 0x00004000 */ 7248 #define RI_CMR3_PC_15 (0x8000UL << RI_CMR3_PC_Pos) /*!< 0x00008000 */ 7249 7250 /******************** Bit definition for RI_CICR3 register ********************/ 7251 #define RI_CICR3_PC_Pos (0U) 7252 #define RI_CICR3_PC_Msk (0xFFFFUL << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */ 7253 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */ 7254 #define RI_CICR3_PC_0 (0x0001UL << RI_CICR3_PC_Pos) /*!< 0x00000001 */ 7255 #define RI_CICR3_PC_1 (0x0002UL << RI_CICR3_PC_Pos) /*!< 0x00000002 */ 7256 #define RI_CICR3_PC_2 (0x0004UL << RI_CICR3_PC_Pos) /*!< 0x00000004 */ 7257 #define RI_CICR3_PC_3 (0x0008UL << RI_CICR3_PC_Pos) /*!< 0x00000008 */ 7258 #define RI_CICR3_PC_4 (0x0010UL << RI_CICR3_PC_Pos) /*!< 0x00000010 */ 7259 #define RI_CICR3_PC_5 (0x0020UL << RI_CICR3_PC_Pos) /*!< 0x00000020 */ 7260 #define RI_CICR3_PC_6 (0x0040UL << RI_CICR3_PC_Pos) /*!< 0x00000040 */ 7261 #define RI_CICR3_PC_7 (0x0080UL << RI_CICR3_PC_Pos) /*!< 0x00000080 */ 7262 #define RI_CICR3_PC_8 (0x0100UL << RI_CICR3_PC_Pos) /*!< 0x00000100 */ 7263 #define RI_CICR3_PC_9 (0x0200UL << RI_CICR3_PC_Pos) /*!< 0x00000200 */ 7264 #define RI_CICR3_PC_10 (0x0400UL << RI_CICR3_PC_Pos) /*!< 0x00000400 */ 7265 #define RI_CICR3_PC_11 (0x0800UL << RI_CICR3_PC_Pos) /*!< 0x00000800 */ 7266 #define RI_CICR3_PC_12 (0x1000UL << RI_CICR3_PC_Pos) /*!< 0x00001000 */ 7267 #define RI_CICR3_PC_13 (0x2000UL << RI_CICR3_PC_Pos) /*!< 0x00002000 */ 7268 #define RI_CICR3_PC_14 (0x4000UL << RI_CICR3_PC_Pos) /*!< 0x00004000 */ 7269 #define RI_CICR3_PC_15 (0x8000UL << RI_CICR3_PC_Pos) /*!< 0x00008000 */ 7270 7271 /******************** Bit definition for RI_ASMR4 register ********************/ 7272 #define RI_ASMR4_PF_Pos (0U) 7273 #define RI_ASMR4_PF_Msk (0xFFFFUL << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ 7274 #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ 7275 #define RI_ASMR4_PF_0 (0x0001UL << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ 7276 #define RI_ASMR4_PF_1 (0x0002UL << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ 7277 #define RI_ASMR4_PF_2 (0x0004UL << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ 7278 #define RI_ASMR4_PF_3 (0x0008UL << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ 7279 #define RI_ASMR4_PF_4 (0x0010UL << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ 7280 #define RI_ASMR4_PF_5 (0x0020UL << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ 7281 #define RI_ASMR4_PF_6 (0x0040UL << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ 7282 #define RI_ASMR4_PF_7 (0x0080UL << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ 7283 #define RI_ASMR4_PF_8 (0x0100UL << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ 7284 #define RI_ASMR4_PF_9 (0x0200UL << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ 7285 #define RI_ASMR4_PF_10 (0x0400UL << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ 7286 #define RI_ASMR4_PF_11 (0x0800UL << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ 7287 #define RI_ASMR4_PF_12 (0x1000UL << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ 7288 #define RI_ASMR4_PF_13 (0x2000UL << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ 7289 #define RI_ASMR4_PF_14 (0x4000UL << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ 7290 #define RI_ASMR4_PF_15 (0x8000UL << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ 7291 7292 /******************** Bit definition for RI_CMR4 register ********************/ 7293 #define RI_CMR4_PF_Pos (0U) 7294 #define RI_CMR4_PF_Msk (0xFFFFUL << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ 7295 #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ 7296 #define RI_CMR4_PF_0 (0x0001UL << RI_CMR4_PF_Pos) /*!< 0x00000001 */ 7297 #define RI_CMR4_PF_1 (0x0002UL << RI_CMR4_PF_Pos) /*!< 0x00000002 */ 7298 #define RI_CMR4_PF_2 (0x0004UL << RI_CMR4_PF_Pos) /*!< 0x00000004 */ 7299 #define RI_CMR4_PF_3 (0x0008UL << RI_CMR4_PF_Pos) /*!< 0x00000008 */ 7300 #define RI_CMR4_PF_4 (0x0010UL << RI_CMR4_PF_Pos) /*!< 0x00000010 */ 7301 #define RI_CMR4_PF_5 (0x0020UL << RI_CMR4_PF_Pos) /*!< 0x00000020 */ 7302 #define RI_CMR4_PF_6 (0x0040UL << RI_CMR4_PF_Pos) /*!< 0x00000040 */ 7303 #define RI_CMR4_PF_7 (0x0080UL << RI_CMR4_PF_Pos) /*!< 0x00000080 */ 7304 #define RI_CMR4_PF_8 (0x0100UL << RI_CMR4_PF_Pos) /*!< 0x00000100 */ 7305 #define RI_CMR4_PF_9 (0x0200UL << RI_CMR4_PF_Pos) /*!< 0x00000200 */ 7306 #define RI_CMR4_PF_10 (0x0400UL << RI_CMR4_PF_Pos) /*!< 0x00000400 */ 7307 #define RI_CMR4_PF_11 (0x0800UL << RI_CMR4_PF_Pos) /*!< 0x00000800 */ 7308 #define RI_CMR4_PF_12 (0x1000UL << RI_CMR4_PF_Pos) /*!< 0x00001000 */ 7309 #define RI_CMR4_PF_13 (0x2000UL << RI_CMR4_PF_Pos) /*!< 0x00002000 */ 7310 #define RI_CMR4_PF_14 (0x4000UL << RI_CMR4_PF_Pos) /*!< 0x00004000 */ 7311 #define RI_CMR4_PF_15 (0x8000UL << RI_CMR4_PF_Pos) /*!< 0x00008000 */ 7312 7313 /******************** Bit definition for RI_CICR4 register ********************/ 7314 #define RI_CICR4_PF_Pos (0U) 7315 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ 7316 #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ 7317 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */ 7318 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */ 7319 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */ 7320 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */ 7321 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */ 7322 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */ 7323 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */ 7324 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */ 7325 #define RI_CICR4_PF_8 (0x0100UL << RI_CICR4_PF_Pos) /*!< 0x00000100 */ 7326 #define RI_CICR4_PF_9 (0x0200UL << RI_CICR4_PF_Pos) /*!< 0x00000200 */ 7327 #define RI_CICR4_PF_10 (0x0400UL << RI_CICR4_PF_Pos) /*!< 0x00000400 */ 7328 #define RI_CICR4_PF_11 (0x0800UL << RI_CICR4_PF_Pos) /*!< 0x00000800 */ 7329 #define RI_CICR4_PF_12 (0x1000UL << RI_CICR4_PF_Pos) /*!< 0x00001000 */ 7330 #define RI_CICR4_PF_13 (0x2000UL << RI_CICR4_PF_Pos) /*!< 0x00002000 */ 7331 #define RI_CICR4_PF_14 (0x4000UL << RI_CICR4_PF_Pos) /*!< 0x00004000 */ 7332 #define RI_CICR4_PF_15 (0x8000UL << RI_CICR4_PF_Pos) /*!< 0x00008000 */ 7333 7334 /******************** Bit definition for RI_ASMR5 register ********************/ 7335 #define RI_ASMR5_PG_Pos (0U) 7336 #define RI_ASMR5_PG_Msk (0xFFFFUL << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ 7337 #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ 7338 #define RI_ASMR5_PG_0 (0x0001UL << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ 7339 #define RI_ASMR5_PG_1 (0x0002UL << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ 7340 #define RI_ASMR5_PG_2 (0x0004UL << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ 7341 #define RI_ASMR5_PG_3 (0x0008UL << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ 7342 #define RI_ASMR5_PG_4 (0x0010UL << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ 7343 #define RI_ASMR5_PG_5 (0x0020UL << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ 7344 #define RI_ASMR5_PG_6 (0x0040UL << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ 7345 #define RI_ASMR5_PG_7 (0x0080UL << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ 7346 #define RI_ASMR5_PG_8 (0x0100UL << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ 7347 #define RI_ASMR5_PG_9 (0x0200UL << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ 7348 #define RI_ASMR5_PG_10 (0x0400UL << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ 7349 #define RI_ASMR5_PG_11 (0x0800UL << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ 7350 #define RI_ASMR5_PG_12 (0x1000UL << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ 7351 #define RI_ASMR5_PG_13 (0x2000UL << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ 7352 #define RI_ASMR5_PG_14 (0x4000UL << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ 7353 #define RI_ASMR5_PG_15 (0x8000UL << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ 7354 7355 /******************** Bit definition for RI_CMR5 register ********************/ 7356 #define RI_CMR5_PG_Pos (0U) 7357 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ 7358 #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ 7359 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */ 7360 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */ 7361 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */ 7362 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */ 7363 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */ 7364 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */ 7365 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */ 7366 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */ 7367 #define RI_CMR5_PG_8 (0x0100UL << RI_CMR5_PG_Pos) /*!< 0x00000100 */ 7368 #define RI_CMR5_PG_9 (0x0200UL << RI_CMR5_PG_Pos) /*!< 0x00000200 */ 7369 #define RI_CMR5_PG_10 (0x0400UL << RI_CMR5_PG_Pos) /*!< 0x00000400 */ 7370 #define RI_CMR5_PG_11 (0x0800UL << RI_CMR5_PG_Pos) /*!< 0x00000800 */ 7371 #define RI_CMR5_PG_12 (0x1000UL << RI_CMR5_PG_Pos) /*!< 0x00001000 */ 7372 #define RI_CMR5_PG_13 (0x2000UL << RI_CMR5_PG_Pos) /*!< 0x00002000 */ 7373 #define RI_CMR5_PG_14 (0x4000UL << RI_CMR5_PG_Pos) /*!< 0x00004000 */ 7374 #define RI_CMR5_PG_15 (0x8000UL << RI_CMR5_PG_Pos) /*!< 0x00008000 */ 7375 7376 /******************** Bit definition for RI_CICR5 register ********************/ 7377 #define RI_CICR5_PG_Pos (0U) 7378 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ 7379 #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ 7380 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */ 7381 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */ 7382 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */ 7383 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */ 7384 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */ 7385 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */ 7386 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */ 7387 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */ 7388 #define RI_CICR5_PG_8 (0x0100UL << RI_CICR5_PG_Pos) /*!< 0x00000100 */ 7389 #define RI_CICR5_PG_9 (0x0200UL << RI_CICR5_PG_Pos) /*!< 0x00000200 */ 7390 #define RI_CICR5_PG_10 (0x0400UL << RI_CICR5_PG_Pos) /*!< 0x00000400 */ 7391 #define RI_CICR5_PG_11 (0x0800UL << RI_CICR5_PG_Pos) /*!< 0x00000800 */ 7392 #define RI_CICR5_PG_12 (0x1000UL << RI_CICR5_PG_Pos) /*!< 0x00001000 */ 7393 #define RI_CICR5_PG_13 (0x2000UL << RI_CICR5_PG_Pos) /*!< 0x00002000 */ 7394 #define RI_CICR5_PG_14 (0x4000UL << RI_CICR5_PG_Pos) /*!< 0x00004000 */ 7395 #define RI_CICR5_PG_15 (0x8000UL << RI_CICR5_PG_Pos) /*!< 0x00008000 */ 7396 7397 /******************************************************************************/ 7398 /* */ 7399 /* Timers (TIM) */ 7400 /* */ 7401 /******************************************************************************/ 7402 7403 /******************* Bit definition for TIM_CR1 register ********************/ 7404 #define TIM_CR1_CEN_Pos (0U) 7405 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 7406 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 7407 #define TIM_CR1_UDIS_Pos (1U) 7408 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 7409 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 7410 #define TIM_CR1_URS_Pos (2U) 7411 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 7412 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 7413 #define TIM_CR1_OPM_Pos (3U) 7414 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 7415 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 7416 #define TIM_CR1_DIR_Pos (4U) 7417 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 7418 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 7419 7420 #define TIM_CR1_CMS_Pos (5U) 7421 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 7422 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 7423 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 7424 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 7425 7426 #define TIM_CR1_ARPE_Pos (7U) 7427 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 7428 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 7429 7430 #define TIM_CR1_CKD_Pos (8U) 7431 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 7432 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 7433 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 7434 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 7435 7436 /******************* Bit definition for TIM_CR2 register ********************/ 7437 #define TIM_CR2_CCDS_Pos (3U) 7438 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 7439 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 7440 7441 #define TIM_CR2_MMS_Pos (4U) 7442 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 7443 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 7444 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 7445 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 7446 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 7447 7448 #define TIM_CR2_TI1S_Pos (7U) 7449 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 7450 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 7451 7452 /******************* Bit definition for TIM_SMCR register *******************/ 7453 #define TIM_SMCR_SMS_Pos (0U) 7454 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 7455 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 7456 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 7457 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 7458 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 7459 7460 #define TIM_SMCR_OCCS_Pos (3U) 7461 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 7462 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 7463 7464 #define TIM_SMCR_TS_Pos (4U) 7465 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 7466 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 7467 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 7468 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 7469 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 7470 7471 #define TIM_SMCR_MSM_Pos (7U) 7472 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 7473 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 7474 7475 #define TIM_SMCR_ETF_Pos (8U) 7476 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 7477 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 7478 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 7479 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 7480 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 7481 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 7482 7483 #define TIM_SMCR_ETPS_Pos (12U) 7484 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 7485 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 7486 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 7487 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 7488 7489 #define TIM_SMCR_ECE_Pos (14U) 7490 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 7491 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 7492 #define TIM_SMCR_ETP_Pos (15U) 7493 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 7494 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 7495 7496 /******************* Bit definition for TIM_DIER register *******************/ 7497 #define TIM_DIER_UIE_Pos (0U) 7498 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 7499 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 7500 #define TIM_DIER_CC1IE_Pos (1U) 7501 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 7502 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 7503 #define TIM_DIER_CC2IE_Pos (2U) 7504 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 7505 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 7506 #define TIM_DIER_CC3IE_Pos (3U) 7507 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 7508 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 7509 #define TIM_DIER_CC4IE_Pos (4U) 7510 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 7511 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 7512 #define TIM_DIER_TIE_Pos (6U) 7513 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 7514 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 7515 #define TIM_DIER_UDE_Pos (8U) 7516 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 7517 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 7518 #define TIM_DIER_CC1DE_Pos (9U) 7519 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 7520 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 7521 #define TIM_DIER_CC2DE_Pos (10U) 7522 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 7523 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 7524 #define TIM_DIER_CC3DE_Pos (11U) 7525 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 7526 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 7527 #define TIM_DIER_CC4DE_Pos (12U) 7528 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 7529 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 7530 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */ 7531 #define TIM_DIER_TDE_Pos (14U) 7532 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 7533 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 7534 7535 /******************** Bit definition for TIM_SR register ********************/ 7536 #define TIM_SR_UIF_Pos (0U) 7537 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 7538 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 7539 #define TIM_SR_CC1IF_Pos (1U) 7540 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 7541 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 7542 #define TIM_SR_CC2IF_Pos (2U) 7543 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 7544 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 7545 #define TIM_SR_CC3IF_Pos (3U) 7546 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 7547 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 7548 #define TIM_SR_CC4IF_Pos (4U) 7549 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 7550 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 7551 #define TIM_SR_TIF_Pos (6U) 7552 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 7553 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 7554 #define TIM_SR_CC1OF_Pos (9U) 7555 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 7556 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 7557 #define TIM_SR_CC2OF_Pos (10U) 7558 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 7559 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 7560 #define TIM_SR_CC3OF_Pos (11U) 7561 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 7562 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 7563 #define TIM_SR_CC4OF_Pos (12U) 7564 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 7565 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 7566 7567 /******************* Bit definition for TIM_EGR register ********************/ 7568 #define TIM_EGR_UG_Pos (0U) 7569 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 7570 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 7571 #define TIM_EGR_CC1G_Pos (1U) 7572 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 7573 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 7574 #define TIM_EGR_CC2G_Pos (2U) 7575 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 7576 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 7577 #define TIM_EGR_CC3G_Pos (3U) 7578 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 7579 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 7580 #define TIM_EGR_CC4G_Pos (4U) 7581 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 7582 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 7583 #define TIM_EGR_TG_Pos (6U) 7584 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 7585 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 7586 7587 /****************** Bit definition for TIM_CCMR1 register *******************/ 7588 #define TIM_CCMR1_CC1S_Pos (0U) 7589 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 7590 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 7591 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 7592 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 7593 7594 #define TIM_CCMR1_OC1FE_Pos (2U) 7595 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 7596 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 7597 #define TIM_CCMR1_OC1PE_Pos (3U) 7598 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 7599 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 7600 7601 #define TIM_CCMR1_OC1M_Pos (4U) 7602 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 7603 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 7604 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 7605 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 7606 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 7607 7608 #define TIM_CCMR1_OC1CE_Pos (7U) 7609 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 7610 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 7611 7612 #define TIM_CCMR1_CC2S_Pos (8U) 7613 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 7614 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 7615 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 7616 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 7617 7618 #define TIM_CCMR1_OC2FE_Pos (10U) 7619 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 7620 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 7621 #define TIM_CCMR1_OC2PE_Pos (11U) 7622 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 7623 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 7624 7625 #define TIM_CCMR1_OC2M_Pos (12U) 7626 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 7627 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 7628 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 7629 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 7630 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 7631 7632 #define TIM_CCMR1_OC2CE_Pos (15U) 7633 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 7634 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 7635 7636 /*----------------------------------------------------------------------------*/ 7637 7638 #define TIM_CCMR1_IC1PSC_Pos (2U) 7639 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 7640 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 7641 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 7642 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 7643 7644 #define TIM_CCMR1_IC1F_Pos (4U) 7645 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 7646 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 7647 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 7648 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 7649 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 7650 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 7651 7652 #define TIM_CCMR1_IC2PSC_Pos (10U) 7653 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 7654 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 7655 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 7656 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 7657 7658 #define TIM_CCMR1_IC2F_Pos (12U) 7659 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 7660 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 7661 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 7662 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 7663 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 7664 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 7665 7666 /****************** Bit definition for TIM_CCMR2 register *******************/ 7667 #define TIM_CCMR2_CC3S_Pos (0U) 7668 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 7669 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 7670 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 7671 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 7672 7673 #define TIM_CCMR2_OC3FE_Pos (2U) 7674 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 7675 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 7676 #define TIM_CCMR2_OC3PE_Pos (3U) 7677 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 7678 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 7679 7680 #define TIM_CCMR2_OC3M_Pos (4U) 7681 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 7682 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 7683 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 7684 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 7685 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 7686 7687 #define TIM_CCMR2_OC3CE_Pos (7U) 7688 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 7689 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 7690 7691 #define TIM_CCMR2_CC4S_Pos (8U) 7692 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 7693 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 7694 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 7695 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 7696 7697 #define TIM_CCMR2_OC4FE_Pos (10U) 7698 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 7699 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 7700 #define TIM_CCMR2_OC4PE_Pos (11U) 7701 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 7702 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 7703 7704 #define TIM_CCMR2_OC4M_Pos (12U) 7705 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 7706 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 7707 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 7708 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 7709 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 7710 7711 #define TIM_CCMR2_OC4CE_Pos (15U) 7712 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 7713 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 7714 7715 /*----------------------------------------------------------------------------*/ 7716 7717 #define TIM_CCMR2_IC3PSC_Pos (2U) 7718 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 7719 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 7720 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 7721 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 7722 7723 #define TIM_CCMR2_IC3F_Pos (4U) 7724 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 7725 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 7726 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 7727 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 7728 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 7729 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 7730 7731 #define TIM_CCMR2_IC4PSC_Pos (10U) 7732 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 7733 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 7734 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 7735 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 7736 7737 #define TIM_CCMR2_IC4F_Pos (12U) 7738 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 7739 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 7740 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 7741 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 7742 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 7743 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 7744 7745 /******************* Bit definition for TIM_CCER register *******************/ 7746 #define TIM_CCER_CC1E_Pos (0U) 7747 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 7748 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 7749 #define TIM_CCER_CC1P_Pos (1U) 7750 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 7751 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 7752 #define TIM_CCER_CC1NP_Pos (3U) 7753 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 7754 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 7755 #define TIM_CCER_CC2E_Pos (4U) 7756 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 7757 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 7758 #define TIM_CCER_CC2P_Pos (5U) 7759 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 7760 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 7761 #define TIM_CCER_CC2NP_Pos (7U) 7762 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 7763 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 7764 #define TIM_CCER_CC3E_Pos (8U) 7765 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 7766 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 7767 #define TIM_CCER_CC3P_Pos (9U) 7768 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 7769 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 7770 #define TIM_CCER_CC3NP_Pos (11U) 7771 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 7772 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 7773 #define TIM_CCER_CC4E_Pos (12U) 7774 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 7775 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 7776 #define TIM_CCER_CC4P_Pos (13U) 7777 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 7778 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 7779 #define TIM_CCER_CC4NP_Pos (15U) 7780 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 7781 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 7782 7783 /******************* Bit definition for TIM_CNT register ********************/ 7784 #define TIM_CNT_CNT_Pos (0U) 7785 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 7786 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 7787 7788 /******************* Bit definition for TIM_PSC register ********************/ 7789 #define TIM_PSC_PSC_Pos (0U) 7790 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 7791 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 7792 7793 /******************* Bit definition for TIM_ARR register ********************/ 7794 #define TIM_ARR_ARR_Pos (0U) 7795 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 7796 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 7797 7798 /******************* Bit definition for TIM_CCR1 register *******************/ 7799 #define TIM_CCR1_CCR1_Pos (0U) 7800 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 7801 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 7802 7803 /******************* Bit definition for TIM_CCR2 register *******************/ 7804 #define TIM_CCR2_CCR2_Pos (0U) 7805 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 7806 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 7807 7808 /******************* Bit definition for TIM_CCR3 register *******************/ 7809 #define TIM_CCR3_CCR3_Pos (0U) 7810 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 7811 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 7812 7813 /******************* Bit definition for TIM_CCR4 register *******************/ 7814 #define TIM_CCR4_CCR4_Pos (0U) 7815 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 7816 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 7817 7818 /******************* Bit definition for TIM_DCR register ********************/ 7819 #define TIM_DCR_DBA_Pos (0U) 7820 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 7821 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 7822 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 7823 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 7824 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 7825 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 7826 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 7827 7828 #define TIM_DCR_DBL_Pos (8U) 7829 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 7830 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 7831 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 7832 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 7833 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 7834 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 7835 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 7836 7837 /******************* Bit definition for TIM_DMAR register *******************/ 7838 #define TIM_DMAR_DMAB_Pos (0U) 7839 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 7840 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 7841 7842 /******************* Bit definition for TIM_OR register *********************/ 7843 #define TIM_OR_TI1RMP_Pos (0U) 7844 #define TIM_OR_TI1RMP_Msk (0x3UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */ 7845 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */ 7846 #define TIM_OR_TI1RMP_0 (0x1UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */ 7847 #define TIM_OR_TI1RMP_1 (0x2UL << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */ 7848 7849 #define TIM_OR_ETR_RMP_Pos (2U) 7850 #define TIM_OR_ETR_RMP_Msk (0x1UL << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 7851 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/ 7852 #define TIM_OR_TI1_RMP_RI_Pos (3U) 7853 #define TIM_OR_TI1_RMP_RI_Msk (0x1UL << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */ 7854 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */ 7855 7856 /*----------------------------------------------------------------------------*/ 7857 #define TIM9_OR_ITR1_RMP_Pos (2U) 7858 #define TIM9_OR_ITR1_RMP_Msk (0x1UL << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */ 7859 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */ 7860 7861 /*----------------------------------------------------------------------------*/ 7862 #define TIM2_OR_ITR1_RMP_Pos (0U) 7863 #define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ 7864 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */ 7865 7866 /*----------------------------------------------------------------------------*/ 7867 #define TIM3_OR_ITR2_RMP_Pos (0U) 7868 #define TIM3_OR_ITR2_RMP_Msk (0x1UL << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */ 7869 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */ 7870 7871 /*----------------------------------------------------------------------------*/ 7872 7873 /******************************************************************************/ 7874 /* */ 7875 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 7876 /* */ 7877 /******************************************************************************/ 7878 7879 /******************* Bit definition for USART_SR register *******************/ 7880 #define USART_SR_PE_Pos (0U) 7881 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 7882 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 7883 #define USART_SR_FE_Pos (1U) 7884 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 7885 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 7886 #define USART_SR_NE_Pos (2U) 7887 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 7888 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 7889 #define USART_SR_ORE_Pos (3U) 7890 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 7891 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 7892 #define USART_SR_IDLE_Pos (4U) 7893 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 7894 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 7895 #define USART_SR_RXNE_Pos (5U) 7896 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 7897 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 7898 #define USART_SR_TC_Pos (6U) 7899 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 7900 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 7901 #define USART_SR_TXE_Pos (7U) 7902 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 7903 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 7904 #define USART_SR_LBD_Pos (8U) 7905 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 7906 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 7907 #define USART_SR_CTS_Pos (9U) 7908 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 7909 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 7910 7911 /******************* Bit definition for USART_DR register *******************/ 7912 #define USART_DR_DR_Pos (0U) 7913 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 7914 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 7915 7916 /****************** Bit definition for USART_BRR register *******************/ 7917 #define USART_BRR_DIV_FRACTION_Pos (0U) 7918 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 7919 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 7920 #define USART_BRR_DIV_MANTISSA_Pos (4U) 7921 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 7922 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 7923 7924 /****************** Bit definition for USART_CR1 register *******************/ 7925 #define USART_CR1_SBK_Pos (0U) 7926 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 7927 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 7928 #define USART_CR1_RWU_Pos (1U) 7929 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 7930 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 7931 #define USART_CR1_RE_Pos (2U) 7932 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 7933 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 7934 #define USART_CR1_TE_Pos (3U) 7935 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 7936 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 7937 #define USART_CR1_IDLEIE_Pos (4U) 7938 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 7939 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 7940 #define USART_CR1_RXNEIE_Pos (5U) 7941 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 7942 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 7943 #define USART_CR1_TCIE_Pos (6U) 7944 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 7945 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 7946 #define USART_CR1_TXEIE_Pos (7U) 7947 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 7948 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 7949 #define USART_CR1_PEIE_Pos (8U) 7950 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 7951 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 7952 #define USART_CR1_PS_Pos (9U) 7953 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 7954 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 7955 #define USART_CR1_PCE_Pos (10U) 7956 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 7957 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 7958 #define USART_CR1_WAKE_Pos (11U) 7959 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 7960 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 7961 #define USART_CR1_M_Pos (12U) 7962 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 7963 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 7964 #define USART_CR1_UE_Pos (13U) 7965 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 7966 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 7967 #define USART_CR1_OVER8_Pos (15U) 7968 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 7969 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */ 7970 7971 /****************** Bit definition for USART_CR2 register *******************/ 7972 #define USART_CR2_ADD_Pos (0U) 7973 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 7974 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 7975 #define USART_CR2_LBDL_Pos (5U) 7976 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 7977 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 7978 #define USART_CR2_LBDIE_Pos (6U) 7979 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 7980 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 7981 #define USART_CR2_LBCL_Pos (8U) 7982 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 7983 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 7984 #define USART_CR2_CPHA_Pos (9U) 7985 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 7986 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 7987 #define USART_CR2_CPOL_Pos (10U) 7988 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 7989 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 7990 #define USART_CR2_CLKEN_Pos (11U) 7991 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 7992 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 7993 7994 #define USART_CR2_STOP_Pos (12U) 7995 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 7996 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 7997 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 7998 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 7999 8000 #define USART_CR2_LINEN_Pos (14U) 8001 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 8002 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 8003 8004 /****************** Bit definition for USART_CR3 register *******************/ 8005 #define USART_CR3_EIE_Pos (0U) 8006 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 8007 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 8008 #define USART_CR3_IREN_Pos (1U) 8009 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 8010 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 8011 #define USART_CR3_IRLP_Pos (2U) 8012 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 8013 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 8014 #define USART_CR3_HDSEL_Pos (3U) 8015 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 8016 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 8017 #define USART_CR3_NACK_Pos (4U) 8018 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 8019 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 8020 #define USART_CR3_SCEN_Pos (5U) 8021 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 8022 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 8023 #define USART_CR3_DMAR_Pos (6U) 8024 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 8025 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 8026 #define USART_CR3_DMAT_Pos (7U) 8027 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 8028 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 8029 #define USART_CR3_RTSE_Pos (8U) 8030 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 8031 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 8032 #define USART_CR3_CTSE_Pos (9U) 8033 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 8034 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 8035 #define USART_CR3_CTSIE_Pos (10U) 8036 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 8037 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 8038 #define USART_CR3_ONEBIT_Pos (11U) 8039 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 8040 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 8041 8042 /****************** Bit definition for USART_GTPR register ******************/ 8043 #define USART_GTPR_PSC_Pos (0U) 8044 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 8045 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 8046 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 8047 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 8048 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 8049 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 8050 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 8051 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 8052 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 8053 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 8054 8055 #define USART_GTPR_GT_Pos (8U) 8056 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 8057 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 8058 8059 /******************************************************************************/ 8060 /* */ 8061 /* Universal Serial Bus (USB) */ 8062 /* */ 8063 /******************************************************************************/ 8064 8065 /*!<Endpoint-specific registers */ 8066 8067 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 8068 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */ 8069 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */ 8070 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */ 8071 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */ 8072 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */ 8073 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */ 8074 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */ 8075 8076 /* bit positions */ 8077 #define USB_EP_CTR_RX_Pos (15U) 8078 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 8079 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 8080 #define USB_EP_DTOG_RX_Pos (14U) 8081 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 8082 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 8083 #define USB_EPRX_STAT_Pos (12U) 8084 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 8085 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 8086 #define USB_EP_SETUP_Pos (11U) 8087 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 8088 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 8089 #define USB_EP_T_FIELD_Pos (9U) 8090 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 8091 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 8092 #define USB_EP_KIND_Pos (8U) 8093 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ 8094 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 8095 #define USB_EP_CTR_TX_Pos (7U) 8096 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 8097 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 8098 #define USB_EP_DTOG_TX_Pos (6U) 8099 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 8100 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 8101 #define USB_EPTX_STAT_Pos (4U) 8102 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 8103 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 8104 #define USB_EPADDR_FIELD_Pos (0U) 8105 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 8106 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 8107 8108 /* EndPoint REGister MASK (no toggle fields) */ 8109 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 8110 /*!< EP_TYPE[1:0] EndPoint TYPE */ 8111 #define USB_EP_TYPE_MASK_Pos (9U) 8112 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 8113 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 8114 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */ 8115 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */ 8116 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */ 8117 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */ 8118 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 8119 8120 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 8121 /*!< STAT_TX[1:0] STATus for TX transfer */ 8122 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */ 8123 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */ 8124 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */ 8125 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */ 8126 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */ 8127 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */ 8128 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 8129 /*!< STAT_RX[1:0] STATus for RX transfer */ 8130 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */ 8131 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */ 8132 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */ 8133 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */ 8134 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */ 8135 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */ 8136 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 8137 8138 /******************* Bit definition for USB_EP0R register *******************/ 8139 #define USB_EP0R_EA_Pos (0U) 8140 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 8141 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */ 8142 8143 #define USB_EP0R_STAT_TX_Pos (4U) 8144 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 8145 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8146 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 8147 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 8148 8149 #define USB_EP0R_DTOG_TX_Pos (6U) 8150 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 8151 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8152 #define USB_EP0R_CTR_TX_Pos (7U) 8153 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 8154 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8155 #define USB_EP0R_EP_KIND_Pos (8U) 8156 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 8157 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */ 8158 8159 #define USB_EP0R_EP_TYPE_Pos (9U) 8160 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 8161 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8162 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 8163 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 8164 8165 #define USB_EP0R_SETUP_Pos (11U) 8166 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 8167 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */ 8168 8169 #define USB_EP0R_STAT_RX_Pos (12U) 8170 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 8171 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8172 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 8173 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 8174 8175 #define USB_EP0R_DTOG_RX_Pos (14U) 8176 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 8177 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8178 #define USB_EP0R_CTR_RX_Pos (15U) 8179 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 8180 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8181 8182 /******************* Bit definition for USB_EP1R register *******************/ 8183 #define USB_EP1R_EA_Pos (0U) 8184 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 8185 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */ 8186 8187 #define USB_EP1R_STAT_TX_Pos (4U) 8188 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 8189 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8190 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 8191 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 8192 8193 #define USB_EP1R_DTOG_TX_Pos (6U) 8194 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 8195 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8196 #define USB_EP1R_CTR_TX_Pos (7U) 8197 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 8198 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8199 #define USB_EP1R_EP_KIND_Pos (8U) 8200 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 8201 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */ 8202 8203 #define USB_EP1R_EP_TYPE_Pos (9U) 8204 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 8205 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8206 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 8207 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 8208 8209 #define USB_EP1R_SETUP_Pos (11U) 8210 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 8211 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */ 8212 8213 #define USB_EP1R_STAT_RX_Pos (12U) 8214 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 8215 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8216 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 8217 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 8218 8219 #define USB_EP1R_DTOG_RX_Pos (14U) 8220 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 8221 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8222 #define USB_EP1R_CTR_RX_Pos (15U) 8223 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 8224 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8225 8226 /******************* Bit definition for USB_EP2R register *******************/ 8227 #define USB_EP2R_EA_Pos (0U) 8228 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 8229 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */ 8230 8231 #define USB_EP2R_STAT_TX_Pos (4U) 8232 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 8233 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8234 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 8235 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 8236 8237 #define USB_EP2R_DTOG_TX_Pos (6U) 8238 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 8239 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8240 #define USB_EP2R_CTR_TX_Pos (7U) 8241 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 8242 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8243 #define USB_EP2R_EP_KIND_Pos (8U) 8244 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 8245 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */ 8246 8247 #define USB_EP2R_EP_TYPE_Pos (9U) 8248 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 8249 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8250 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 8251 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 8252 8253 #define USB_EP2R_SETUP_Pos (11U) 8254 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 8255 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */ 8256 8257 #define USB_EP2R_STAT_RX_Pos (12U) 8258 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 8259 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8260 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 8261 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 8262 8263 #define USB_EP2R_DTOG_RX_Pos (14U) 8264 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 8265 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8266 #define USB_EP2R_CTR_RX_Pos (15U) 8267 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 8268 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8269 8270 /******************* Bit definition for USB_EP3R register *******************/ 8271 #define USB_EP3R_EA_Pos (0U) 8272 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 8273 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */ 8274 8275 #define USB_EP3R_STAT_TX_Pos (4U) 8276 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 8277 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8278 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 8279 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 8280 8281 #define USB_EP3R_DTOG_TX_Pos (6U) 8282 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 8283 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8284 #define USB_EP3R_CTR_TX_Pos (7U) 8285 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 8286 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8287 #define USB_EP3R_EP_KIND_Pos (8U) 8288 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 8289 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */ 8290 8291 #define USB_EP3R_EP_TYPE_Pos (9U) 8292 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 8293 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8294 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 8295 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 8296 8297 #define USB_EP3R_SETUP_Pos (11U) 8298 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 8299 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */ 8300 8301 #define USB_EP3R_STAT_RX_Pos (12U) 8302 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 8303 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8304 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 8305 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 8306 8307 #define USB_EP3R_DTOG_RX_Pos (14U) 8308 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 8309 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8310 #define USB_EP3R_CTR_RX_Pos (15U) 8311 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 8312 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8313 8314 /******************* Bit definition for USB_EP4R register *******************/ 8315 #define USB_EP4R_EA_Pos (0U) 8316 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 8317 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */ 8318 8319 #define USB_EP4R_STAT_TX_Pos (4U) 8320 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 8321 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8322 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 8323 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 8324 8325 #define USB_EP4R_DTOG_TX_Pos (6U) 8326 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 8327 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8328 #define USB_EP4R_CTR_TX_Pos (7U) 8329 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 8330 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8331 #define USB_EP4R_EP_KIND_Pos (8U) 8332 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 8333 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */ 8334 8335 #define USB_EP4R_EP_TYPE_Pos (9U) 8336 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 8337 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8338 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 8339 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 8340 8341 #define USB_EP4R_SETUP_Pos (11U) 8342 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 8343 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */ 8344 8345 #define USB_EP4R_STAT_RX_Pos (12U) 8346 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 8347 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8348 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 8349 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 8350 8351 #define USB_EP4R_DTOG_RX_Pos (14U) 8352 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 8353 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8354 #define USB_EP4R_CTR_RX_Pos (15U) 8355 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 8356 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8357 8358 /******************* Bit definition for USB_EP5R register *******************/ 8359 #define USB_EP5R_EA_Pos (0U) 8360 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 8361 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */ 8362 8363 #define USB_EP5R_STAT_TX_Pos (4U) 8364 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 8365 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8366 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 8367 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 8368 8369 #define USB_EP5R_DTOG_TX_Pos (6U) 8370 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 8371 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8372 #define USB_EP5R_CTR_TX_Pos (7U) 8373 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 8374 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8375 #define USB_EP5R_EP_KIND_Pos (8U) 8376 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 8377 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */ 8378 8379 #define USB_EP5R_EP_TYPE_Pos (9U) 8380 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 8381 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8382 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 8383 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 8384 8385 #define USB_EP5R_SETUP_Pos (11U) 8386 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 8387 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */ 8388 8389 #define USB_EP5R_STAT_RX_Pos (12U) 8390 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 8391 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8392 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 8393 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 8394 8395 #define USB_EP5R_DTOG_RX_Pos (14U) 8396 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 8397 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8398 #define USB_EP5R_CTR_RX_Pos (15U) 8399 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 8400 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8401 8402 /******************* Bit definition for USB_EP6R register *******************/ 8403 #define USB_EP6R_EA_Pos (0U) 8404 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 8405 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */ 8406 8407 #define USB_EP6R_STAT_TX_Pos (4U) 8408 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 8409 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8410 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 8411 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 8412 8413 #define USB_EP6R_DTOG_TX_Pos (6U) 8414 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 8415 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8416 #define USB_EP6R_CTR_TX_Pos (7U) 8417 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 8418 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8419 #define USB_EP6R_EP_KIND_Pos (8U) 8420 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 8421 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */ 8422 8423 #define USB_EP6R_EP_TYPE_Pos (9U) 8424 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 8425 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8426 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 8427 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 8428 8429 #define USB_EP6R_SETUP_Pos (11U) 8430 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 8431 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */ 8432 8433 #define USB_EP6R_STAT_RX_Pos (12U) 8434 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 8435 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8436 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 8437 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 8438 8439 #define USB_EP6R_DTOG_RX_Pos (14U) 8440 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 8441 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8442 #define USB_EP6R_CTR_RX_Pos (15U) 8443 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 8444 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8445 8446 /******************* Bit definition for USB_EP7R register *******************/ 8447 #define USB_EP7R_EA_Pos (0U) 8448 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 8449 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */ 8450 8451 #define USB_EP7R_STAT_TX_Pos (4U) 8452 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 8453 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 8454 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 8455 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 8456 8457 #define USB_EP7R_DTOG_TX_Pos (6U) 8458 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 8459 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 8460 #define USB_EP7R_CTR_TX_Pos (7U) 8461 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 8462 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 8463 #define USB_EP7R_EP_KIND_Pos (8U) 8464 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 8465 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */ 8466 8467 #define USB_EP7R_EP_TYPE_Pos (9U) 8468 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 8469 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 8470 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 8471 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 8472 8473 #define USB_EP7R_SETUP_Pos (11U) 8474 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 8475 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */ 8476 8477 #define USB_EP7R_STAT_RX_Pos (12U) 8478 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 8479 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 8480 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 8481 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 8482 8483 #define USB_EP7R_DTOG_RX_Pos (14U) 8484 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 8485 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 8486 #define USB_EP7R_CTR_RX_Pos (15U) 8487 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 8488 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */ 8489 8490 /*!<Common registers */ 8491 8492 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ 8493 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ 8494 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ 8495 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ 8496 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ 8497 8498 8499 8500 /******************* Bit definition for USB_CNTR register *******************/ 8501 #define USB_CNTR_FRES_Pos (0U) 8502 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 8503 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */ 8504 #define USB_CNTR_PDWN_Pos (1U) 8505 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 8506 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */ 8507 #define USB_CNTR_LPMODE_Pos (2U) 8508 #define USB_CNTR_LPMODE_Msk (0x1UL << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */ 8509 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */ 8510 #define USB_CNTR_FSUSP_Pos (3U) 8511 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 8512 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */ 8513 #define USB_CNTR_RESUME_Pos (4U) 8514 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 8515 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */ 8516 #define USB_CNTR_ESOFM_Pos (8U) 8517 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 8518 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */ 8519 #define USB_CNTR_SOFM_Pos (9U) 8520 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 8521 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */ 8522 #define USB_CNTR_RESETM_Pos (10U) 8523 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 8524 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */ 8525 #define USB_CNTR_SUSPM_Pos (11U) 8526 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 8527 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */ 8528 #define USB_CNTR_WKUPM_Pos (12U) 8529 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 8530 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */ 8531 #define USB_CNTR_ERRM_Pos (13U) 8532 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 8533 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */ 8534 #define USB_CNTR_PMAOVRM_Pos (14U) 8535 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 8536 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */ 8537 #define USB_CNTR_CTRM_Pos (15U) 8538 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 8539 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */ 8540 8541 /******************* Bit definition for USB_ISTR register *******************/ 8542 #define USB_ISTR_EP_ID_Pos (0U) 8543 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 8544 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */ 8545 #define USB_ISTR_DIR_Pos (4U) 8546 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 8547 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */ 8548 #define USB_ISTR_ESOF_Pos (8U) 8549 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 8550 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */ 8551 #define USB_ISTR_SOF_Pos (9U) 8552 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 8553 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */ 8554 #define USB_ISTR_RESET_Pos (10U) 8555 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 8556 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */ 8557 #define USB_ISTR_SUSP_Pos (11U) 8558 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 8559 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */ 8560 #define USB_ISTR_WKUP_Pos (12U) 8561 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 8562 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */ 8563 #define USB_ISTR_ERR_Pos (13U) 8564 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 8565 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */ 8566 #define USB_ISTR_PMAOVR_Pos (14U) 8567 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 8568 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */ 8569 #define USB_ISTR_CTR_Pos (15U) 8570 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 8571 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */ 8572 8573 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 8574 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 8575 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 8576 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 8577 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 8578 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 8579 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 8580 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 8581 8582 8583 /******************* Bit definition for USB_FNR register ********************/ 8584 #define USB_FNR_FN_Pos (0U) 8585 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ 8586 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */ 8587 #define USB_FNR_LSOF_Pos (11U) 8588 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 8589 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */ 8590 #define USB_FNR_LCK_Pos (13U) 8591 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 8592 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */ 8593 #define USB_FNR_RXDM_Pos (14U) 8594 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 8595 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */ 8596 #define USB_FNR_RXDP_Pos (15U) 8597 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 8598 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */ 8599 8600 /****************** Bit definition for USB_DADDR register *******************/ 8601 #define USB_DADDR_ADD_Pos (0U) 8602 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 8603 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */ 8604 #define USB_DADDR_ADD0_Pos (0U) 8605 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 8606 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */ 8607 #define USB_DADDR_ADD1_Pos (1U) 8608 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 8609 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */ 8610 #define USB_DADDR_ADD2_Pos (2U) 8611 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 8612 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */ 8613 #define USB_DADDR_ADD3_Pos (3U) 8614 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 8615 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */ 8616 #define USB_DADDR_ADD4_Pos (4U) 8617 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 8618 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */ 8619 #define USB_DADDR_ADD5_Pos (5U) 8620 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 8621 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */ 8622 #define USB_DADDR_ADD6_Pos (6U) 8623 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 8624 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */ 8625 8626 #define USB_DADDR_EF_Pos (7U) 8627 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 8628 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */ 8629 8630 /****************** Bit definition for USB_BTABLE register ******************/ 8631 #define USB_BTABLE_BTABLE_Pos (3U) 8632 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 8633 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */ 8634 8635 /*!< Buffer descriptor table */ 8636 /***************** Bit definition for USB_ADDR0_TX register *****************/ 8637 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 8638 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 8639 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 8640 8641 /***************** Bit definition for USB_ADDR1_TX register *****************/ 8642 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 8643 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 8644 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 8645 8646 /***************** Bit definition for USB_ADDR2_TX register *****************/ 8647 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 8648 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 8649 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 8650 8651 /***************** Bit definition for USB_ADDR3_TX register *****************/ 8652 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 8653 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 8654 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 8655 8656 /***************** Bit definition for USB_ADDR4_TX register *****************/ 8657 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 8658 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 8659 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 8660 8661 /***************** Bit definition for USB_ADDR5_TX register *****************/ 8662 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 8663 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 8664 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 8665 8666 /***************** Bit definition for USB_ADDR6_TX register *****************/ 8667 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 8668 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 8669 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 8670 8671 /***************** Bit definition for USB_ADDR7_TX register *****************/ 8672 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 8673 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 8674 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 8675 8676 /*----------------------------------------------------------------------------*/ 8677 8678 /***************** Bit definition for USB_COUNT0_TX register ****************/ 8679 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 8680 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 8681 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 8682 8683 /***************** Bit definition for USB_COUNT1_TX register ****************/ 8684 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 8685 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 8686 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 8687 8688 /***************** Bit definition for USB_COUNT2_TX register ****************/ 8689 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 8690 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 8691 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 8692 8693 /***************** Bit definition for USB_COUNT3_TX register ****************/ 8694 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 8695 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 8696 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 8697 8698 /***************** Bit definition for USB_COUNT4_TX register ****************/ 8699 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 8700 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 8701 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 8702 8703 /***************** Bit definition for USB_COUNT5_TX register ****************/ 8704 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 8705 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 8706 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 8707 8708 /***************** Bit definition for USB_COUNT6_TX register ****************/ 8709 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 8710 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 8711 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 8712 8713 /***************** Bit definition for USB_COUNT7_TX register ****************/ 8714 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 8715 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 8716 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 8717 8718 /*----------------------------------------------------------------------------*/ 8719 8720 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 8721 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ 8722 8723 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 8724 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ 8725 8726 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 8727 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ 8728 8729 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 8730 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ 8731 8732 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 8733 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ 8734 8735 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 8736 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ 8737 8738 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 8739 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */ 8740 8741 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 8742 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */ 8743 8744 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 8745 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ 8746 8747 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 8748 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ 8749 8750 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 8751 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ 8752 8753 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 8754 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ 8755 8756 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 8757 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ 8758 8759 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 8760 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ 8761 8762 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 8763 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ 8764 8765 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 8766 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ 8767 8768 /*----------------------------------------------------------------------------*/ 8769 8770 /***************** Bit definition for USB_ADDR0_RX register *****************/ 8771 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 8772 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 8773 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 8774 8775 /***************** Bit definition for USB_ADDR1_RX register *****************/ 8776 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 8777 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 8778 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 8779 8780 /***************** Bit definition for USB_ADDR2_RX register *****************/ 8781 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 8782 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 8783 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 8784 8785 /***************** Bit definition for USB_ADDR3_RX register *****************/ 8786 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 8787 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 8788 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 8789 8790 /***************** Bit definition for USB_ADDR4_RX register *****************/ 8791 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 8792 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 8793 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 8794 8795 /***************** Bit definition for USB_ADDR5_RX register *****************/ 8796 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 8797 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 8798 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 8799 8800 /***************** Bit definition for USB_ADDR6_RX register *****************/ 8801 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 8802 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 8803 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 8804 8805 /***************** Bit definition for USB_ADDR7_RX register *****************/ 8806 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 8807 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 8808 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 8809 8810 /*----------------------------------------------------------------------------*/ 8811 8812 /***************** Bit definition for USB_COUNT0_RX register ****************/ 8813 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 8814 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 8815 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 8816 8817 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 8818 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8819 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8820 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8821 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8822 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8823 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8824 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8825 8826 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 8827 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8828 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 8829 8830 /***************** Bit definition for USB_COUNT1_RX register ****************/ 8831 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 8832 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 8833 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 8834 8835 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 8836 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8837 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8838 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8839 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8840 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8841 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8842 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8843 8844 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 8845 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8846 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 8847 8848 /***************** Bit definition for USB_COUNT2_RX register ****************/ 8849 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 8850 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 8851 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 8852 8853 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 8854 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8855 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8856 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8857 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8858 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8859 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8860 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8861 8862 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 8863 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8864 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 8865 8866 /***************** Bit definition for USB_COUNT3_RX register ****************/ 8867 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 8868 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 8869 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 8870 8871 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 8872 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8873 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8874 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8875 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8876 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8877 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8878 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8879 8880 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 8881 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8882 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 8883 8884 /***************** Bit definition for USB_COUNT4_RX register ****************/ 8885 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 8886 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 8887 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 8888 8889 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 8890 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8891 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8892 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8893 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8894 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8895 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8896 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8897 8898 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 8899 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8900 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 8901 8902 /***************** Bit definition for USB_COUNT5_RX register ****************/ 8903 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 8904 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 8905 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 8906 8907 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 8908 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8909 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8910 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8911 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8912 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8913 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8914 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8915 8916 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 8917 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8918 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 8919 8920 /***************** Bit definition for USB_COUNT6_RX register ****************/ 8921 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 8922 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 8923 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 8924 8925 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 8926 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8927 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8928 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8929 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8930 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8931 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8932 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8933 8934 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 8935 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8936 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 8937 8938 /***************** Bit definition for USB_COUNT7_RX register ****************/ 8939 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 8940 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 8941 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 8942 8943 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 8944 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8945 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8946 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8947 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8948 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8949 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8950 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8951 8952 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 8953 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8954 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 8955 8956 /*----------------------------------------------------------------------------*/ 8957 8958 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 8959 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8960 8961 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8962 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8963 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8964 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8965 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8966 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8967 8968 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8969 8970 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 8971 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8972 8973 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8974 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ 8975 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8976 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8977 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8978 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8979 8980 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8981 8982 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 8983 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8984 8985 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8986 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8987 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8988 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8989 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8990 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8991 8992 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8993 8994 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 8995 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8996 8997 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8998 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8999 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9000 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9001 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9002 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9003 9004 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9005 9006 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 9007 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9008 9009 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9010 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9011 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9012 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9013 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9014 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9015 9016 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9017 9018 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 9019 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9020 9021 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9022 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9023 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9024 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9025 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9026 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9027 9028 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9029 9030 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 9031 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9032 9033 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9034 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9035 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9036 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9037 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9038 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9039 9040 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9041 9042 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 9043 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9044 9045 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9046 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9047 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9048 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9049 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9050 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9051 9052 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9053 9054 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 9055 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9056 9057 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9058 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9059 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9060 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9061 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9062 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9063 9064 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9065 9066 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 9067 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9068 9069 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9070 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9071 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9072 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9073 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9074 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9075 9076 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9077 9078 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 9079 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9080 9081 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9082 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9083 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9084 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9085 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9086 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9087 9088 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9089 9090 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 9091 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9092 9093 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9094 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9095 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9096 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9097 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9098 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9099 9100 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9101 9102 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 9103 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9104 9105 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9106 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9107 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9108 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9109 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9110 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9111 9112 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9113 9114 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 9115 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9116 9117 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9118 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9119 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9120 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9121 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9122 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9123 9124 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9125 9126 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 9127 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 9128 9129 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 9130 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 9131 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 9132 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 9133 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 9134 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 9135 9136 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 9137 9138 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 9139 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 9140 9141 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 9142 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 9143 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 9144 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 9145 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 9146 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 9147 9148 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 9149 9150 /******************************************************************************/ 9151 /* */ 9152 /* Window WATCHDOG (WWDG) */ 9153 /* */ 9154 /******************************************************************************/ 9155 9156 /******************* Bit definition for WWDG_CR register ********************/ 9157 #define WWDG_CR_T_Pos (0U) 9158 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 9159 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 9160 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 9161 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 9162 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 9163 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 9164 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 9165 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 9166 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 9167 9168 /* Legacy defines */ 9169 #define WWDG_CR_T0 WWDG_CR_T_0 9170 #define WWDG_CR_T1 WWDG_CR_T_1 9171 #define WWDG_CR_T2 WWDG_CR_T_2 9172 #define WWDG_CR_T3 WWDG_CR_T_3 9173 #define WWDG_CR_T4 WWDG_CR_T_4 9174 #define WWDG_CR_T5 WWDG_CR_T_5 9175 #define WWDG_CR_T6 WWDG_CR_T_6 9176 9177 #define WWDG_CR_WDGA_Pos (7U) 9178 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 9179 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 9180 9181 /******************* Bit definition for WWDG_CFR register *******************/ 9182 #define WWDG_CFR_W_Pos (0U) 9183 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 9184 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 9185 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 9186 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 9187 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 9188 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 9189 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 9190 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 9191 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 9192 9193 /* Legacy defines */ 9194 #define WWDG_CFR_W0 WWDG_CFR_W_0 9195 #define WWDG_CFR_W1 WWDG_CFR_W_1 9196 #define WWDG_CFR_W2 WWDG_CFR_W_2 9197 #define WWDG_CFR_W3 WWDG_CFR_W_3 9198 #define WWDG_CFR_W4 WWDG_CFR_W_4 9199 #define WWDG_CFR_W5 WWDG_CFR_W_5 9200 #define WWDG_CFR_W6 WWDG_CFR_W_6 9201 9202 #define WWDG_CFR_WDGTB_Pos (7U) 9203 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 9204 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 9205 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 9206 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 9207 9208 /* Legacy defines */ 9209 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 9210 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 9211 9212 #define WWDG_CFR_EWI_Pos (9U) 9213 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 9214 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 9215 9216 /******************* Bit definition for WWDG_SR register ********************/ 9217 #define WWDG_SR_EWIF_Pos (0U) 9218 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 9219 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 9220 9221 /** 9222 * @} 9223 */ 9224 /** @addtogroup Exported_macro 9225 * @{ 9226 */ 9227 9228 /****************************** ADC Instances *********************************/ 9229 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 9230 9231 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 9232 9233 /******************************** COMP Instances ******************************/ 9234 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 9235 ((INSTANCE) == COMP2)) 9236 9237 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 9238 9239 /****************************** CRC Instances *********************************/ 9240 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 9241 9242 /****************************** DAC Instances *********************************/ 9243 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) 9244 9245 /****************************** DMA Instances *********************************/ 9246 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 9247 ((INSTANCE) == DMA1_Channel2) || \ 9248 ((INSTANCE) == DMA1_Channel3) || \ 9249 ((INSTANCE) == DMA1_Channel4) || \ 9250 ((INSTANCE) == DMA1_Channel5) || \ 9251 ((INSTANCE) == DMA1_Channel6) || \ 9252 ((INSTANCE) == DMA1_Channel7) || \ 9253 ((INSTANCE) == DMA2_Channel1) || \ 9254 ((INSTANCE) == DMA2_Channel2) || \ 9255 ((INSTANCE) == DMA2_Channel3) || \ 9256 ((INSTANCE) == DMA2_Channel4) || \ 9257 ((INSTANCE) == DMA2_Channel5)) 9258 9259 /******************************* GPIO Instances *******************************/ 9260 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 9261 ((INSTANCE) == GPIOB) || \ 9262 ((INSTANCE) == GPIOC) || \ 9263 ((INSTANCE) == GPIOD) || \ 9264 ((INSTANCE) == GPIOE) || \ 9265 ((INSTANCE) == GPIOF) || \ 9266 ((INSTANCE) == GPIOG) || \ 9267 ((INSTANCE) == GPIOH)) 9268 9269 /**************************** GPIO Alternate Function Instances ***************/ 9270 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9271 9272 /**************************** GPIO Lock Instances *****************************/ 9273 /* On L1, all GPIO Bank support the Lock mechanism */ 9274 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9275 9276 /******************************** I2C Instances *******************************/ 9277 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 9278 ((INSTANCE) == I2C2)) 9279 9280 /****************************** SMBUS Instances *******************************/ 9281 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 9282 9283 /******************************** I2S Instances *******************************/ 9284 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 9285 ((INSTANCE) == SPI3)) 9286 /****************************** IWDG Instances ********************************/ 9287 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 9288 9289 /****************************** OPAMP Instances *******************************/ 9290 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ 9291 ((INSTANCE) == OPAMP2) || \ 9292 ((INSTANCE) == OPAMP3)) 9293 9294 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON) 9295 9296 /****************************** RTC Instances *********************************/ 9297 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 9298 9299 /****************************** SDIO Instances *********************************/ 9300 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) 9301 9302 /******************************** SPI Instances *******************************/ 9303 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 9304 ((INSTANCE) == SPI2) || \ 9305 ((INSTANCE) == SPI3)) 9306 9307 /****************************** TIM Instances *********************************/ 9308 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9309 ((INSTANCE) == TIM3) || \ 9310 ((INSTANCE) == TIM4) || \ 9311 ((INSTANCE) == TIM5) || \ 9312 ((INSTANCE) == TIM6) || \ 9313 ((INSTANCE) == TIM7) || \ 9314 ((INSTANCE) == TIM9) || \ 9315 ((INSTANCE) == TIM10) || \ 9316 ((INSTANCE) == TIM11)) 9317 9318 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9319 ((INSTANCE) == TIM3) || \ 9320 ((INSTANCE) == TIM4) || \ 9321 ((INSTANCE) == TIM5) || \ 9322 ((INSTANCE) == TIM9) || \ 9323 ((INSTANCE) == TIM10) || \ 9324 ((INSTANCE) == TIM11)) 9325 9326 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9327 ((INSTANCE) == TIM3) || \ 9328 ((INSTANCE) == TIM4) || \ 9329 ((INSTANCE) == TIM5) || \ 9330 ((INSTANCE) == TIM9)) 9331 9332 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9333 ((INSTANCE) == TIM3) || \ 9334 ((INSTANCE) == TIM4) || \ 9335 ((INSTANCE) == TIM5)) 9336 9337 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9338 ((INSTANCE) == TIM3) || \ 9339 ((INSTANCE) == TIM4) || \ 9340 ((INSTANCE) == TIM5)) 9341 9342 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9343 ((INSTANCE) == TIM3) || \ 9344 ((INSTANCE) == TIM4) || \ 9345 ((INSTANCE) == TIM5) || \ 9346 ((INSTANCE) == TIM9)) 9347 9348 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9349 ((INSTANCE) == TIM3) || \ 9350 ((INSTANCE) == TIM4) || \ 9351 ((INSTANCE) == TIM5) || \ 9352 ((INSTANCE) == TIM9) || \ 9353 ((INSTANCE) == TIM10) || \ 9354 ((INSTANCE) == TIM11)) 9355 9356 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9357 ((INSTANCE) == TIM3) || \ 9358 ((INSTANCE) == TIM4) || \ 9359 ((INSTANCE) == TIM5) || \ 9360 ((INSTANCE) == TIM9)) 9361 9362 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9363 ((INSTANCE) == TIM3) || \ 9364 ((INSTANCE) == TIM4) || \ 9365 ((INSTANCE) == TIM5) || \ 9366 ((INSTANCE) == TIM9)) 9367 9368 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9369 ((INSTANCE) == TIM3) || \ 9370 ((INSTANCE) == TIM4)) 9371 9372 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9373 ((INSTANCE) == TIM3) || \ 9374 ((INSTANCE) == TIM4) || \ 9375 ((INSTANCE) == TIM5)) 9376 9377 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9378 ((INSTANCE) == TIM3) || \ 9379 ((INSTANCE) == TIM4) || \ 9380 ((INSTANCE) == TIM5) || \ 9381 ((INSTANCE) == TIM9)) 9382 9383 9384 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9385 ((INSTANCE) == TIM3) || \ 9386 ((INSTANCE) == TIM4) || \ 9387 ((INSTANCE) == TIM5) || \ 9388 ((INSTANCE) == TIM6) || \ 9389 ((INSTANCE) == TIM7) || \ 9390 ((INSTANCE) == TIM9)) 9391 9392 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9393 ((INSTANCE) == TIM3) || \ 9394 ((INSTANCE) == TIM4) || \ 9395 ((INSTANCE) == TIM9)) 9396 9397 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5) 9398 9399 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9400 ((INSTANCE) == TIM3) || \ 9401 ((INSTANCE) == TIM4) || \ 9402 ((INSTANCE) == TIM5)) 9403 9404 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 9405 ((((INSTANCE) == TIM2) && \ 9406 (((CHANNEL) == TIM_CHANNEL_1) || \ 9407 ((CHANNEL) == TIM_CHANNEL_2) || \ 9408 ((CHANNEL) == TIM_CHANNEL_3) || \ 9409 ((CHANNEL) == TIM_CHANNEL_4))) \ 9410 || \ 9411 (((INSTANCE) == TIM3) && \ 9412 (((CHANNEL) == TIM_CHANNEL_1) || \ 9413 ((CHANNEL) == TIM_CHANNEL_2) || \ 9414 ((CHANNEL) == TIM_CHANNEL_3) || \ 9415 ((CHANNEL) == TIM_CHANNEL_4))) \ 9416 || \ 9417 (((INSTANCE) == TIM4) && \ 9418 (((CHANNEL) == TIM_CHANNEL_1) || \ 9419 ((CHANNEL) == TIM_CHANNEL_2) || \ 9420 ((CHANNEL) == TIM_CHANNEL_3) || \ 9421 ((CHANNEL) == TIM_CHANNEL_4))) \ 9422 || \ 9423 (((INSTANCE) == TIM5) && \ 9424 (((CHANNEL) == TIM_CHANNEL_1) || \ 9425 ((CHANNEL) == TIM_CHANNEL_2) || \ 9426 ((CHANNEL) == TIM_CHANNEL_3) || \ 9427 ((CHANNEL) == TIM_CHANNEL_4))) \ 9428 || \ 9429 (((INSTANCE) == TIM9) && \ 9430 (((CHANNEL) == TIM_CHANNEL_1) || \ 9431 ((CHANNEL) == TIM_CHANNEL_2))) \ 9432 || \ 9433 (((INSTANCE) == TIM10) && \ 9434 (((CHANNEL) == TIM_CHANNEL_1))) \ 9435 || \ 9436 (((INSTANCE) == TIM11) && \ 9437 (((CHANNEL) == TIM_CHANNEL_1)))) 9438 9439 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9440 ((INSTANCE) == TIM3) || \ 9441 ((INSTANCE) == TIM4) || \ 9442 ((INSTANCE) == TIM5) || \ 9443 ((INSTANCE) == TIM9) || \ 9444 ((INSTANCE) == TIM10) || \ 9445 ((INSTANCE) == TIM11)) 9446 9447 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9448 ((INSTANCE) == TIM3) || \ 9449 ((INSTANCE) == TIM4) || \ 9450 ((INSTANCE) == TIM5) || \ 9451 ((INSTANCE) == TIM6) || \ 9452 ((INSTANCE) == TIM7)) 9453 9454 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9455 ((INSTANCE) == TIM3) || \ 9456 ((INSTANCE) == TIM4) || \ 9457 ((INSTANCE) == TIM5)) 9458 9459 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9460 ((INSTANCE) == TIM3) || \ 9461 ((INSTANCE) == TIM4) || \ 9462 ((INSTANCE) == TIM5) || \ 9463 ((INSTANCE) == TIM9)) 9464 9465 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9466 ((INSTANCE) == TIM3) || \ 9467 ((INSTANCE) == TIM4) || \ 9468 ((INSTANCE) == TIM5) || \ 9469 ((INSTANCE) == TIM9)) 9470 9471 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9472 ((INSTANCE) == TIM3) || \ 9473 ((INSTANCE) == TIM9) || \ 9474 ((INSTANCE) == TIM10) || \ 9475 ((INSTANCE) == TIM11)) 9476 9477 /******************** USART Instances : Synchronous mode **********************/ 9478 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9479 ((INSTANCE) == USART2) || \ 9480 ((INSTANCE) == USART3)) 9481 9482 /******************** UART Instances : Asynchronous mode **********************/ 9483 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9484 ((INSTANCE) == USART2) || \ 9485 ((INSTANCE) == USART3) || \ 9486 ((INSTANCE) == UART4) || \ 9487 ((INSTANCE) == UART5)) 9488 9489 /******************** UART Instances : Half-Duplex mode **********************/ 9490 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9491 ((INSTANCE) == USART2) || \ 9492 ((INSTANCE) == USART3) || \ 9493 ((INSTANCE) == UART4) || \ 9494 ((INSTANCE) == UART5)) 9495 9496 /******************** UART Instances : LIN mode **********************/ 9497 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9498 ((INSTANCE) == USART2) || \ 9499 ((INSTANCE) == USART3) || \ 9500 ((INSTANCE) == UART4) || \ 9501 ((INSTANCE) == UART5)) 9502 9503 /****************** UART Instances : Hardware Flow control ********************/ 9504 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9505 ((INSTANCE) == USART2) || \ 9506 ((INSTANCE) == USART3)) 9507 9508 /********************* UART Instances : Smard card mode ***********************/ 9509 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9510 ((INSTANCE) == USART2) || \ 9511 ((INSTANCE) == USART3)) 9512 9513 /*********************** UART Instances : IRDA mode ***************************/ 9514 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9515 ((INSTANCE) == USART2) || \ 9516 ((INSTANCE) == USART3) || \ 9517 ((INSTANCE) == UART4) || \ 9518 ((INSTANCE) == UART5)) 9519 9520 /***************** UART Instances : Multi-Processor mode **********************/ 9521 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9522 ((INSTANCE) == USART2) || \ 9523 ((INSTANCE) == USART3) || \ 9524 ((INSTANCE) == UART4) || \ 9525 ((INSTANCE) == UART5)) 9526 9527 /****************************** WWDG Instances ********************************/ 9528 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 9529 9530 9531 /****************************** LCD Instances ********************************/ 9532 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) 9533 9534 /****************************** USB Instances ********************************/ 9535 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 9536 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE 9537 9538 /** 9539 * @} 9540 */ 9541 9542 /******************************************************************************/ 9543 /* For a painless codes migration between the STM32L1xx device product */ 9544 /* lines, the aliases defined below are put in place to overcome the */ 9545 /* differences in the interrupt handlers and IRQn definitions. */ 9546 /* No need to update developed interrupt code when moving across */ 9547 /* product lines within the same STM32L1 Family */ 9548 /******************************************************************************/ 9549 9550 /* Aliases for __IRQn */ 9551 9552 /* Aliases for __IRQHandler */ 9553 9554 /** 9555 * @} 9556 */ 9557 9558 /** 9559 * @} 9560 */ 9561 9562 #ifdef __cplusplus 9563 } 9564 #endif /* __cplusplus */ 9565 9566 #endif /* __STM32L152xD_H */ 9567 9568 9569 9570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 9571
