1 /** 2 ****************************************************************************** 3 * @file stm32l021xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32l021xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright(c) 2016 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 /** @addtogroup CMSIS 29 * @{ 30 */ 31 32 /** @addtogroup stm32l021xx 33 * @{ 34 */ 35 36 #ifndef __STM32L021xx_H 37 #define __STM32L021xx_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /** @addtogroup Configuration_section_for_CMSIS 45 * @{ 46 */ 47 /** 48 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 49 */ 50 #define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ 51 #define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */ 52 #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ 53 #define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ 54 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 55 56 /** 57 * @} 58 */ 59 60 /** @addtogroup Peripheral_interrupt_number_definition 61 * @{ 62 */ 63 64 /** 65 * @brief stm32l021xx Interrupt Number Definition, according to the selected device 66 * in @ref Library_configuration_section 67 */ 68 69 /*!< Interrupt Number Definition */ 70 typedef enum 71 { 72 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ 73 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 74 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ 75 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ 76 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ 77 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ 78 79 /****** STM32L-0 specific Interrupt Numbers *********************************************************/ 80 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 81 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ 82 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 83 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 84 RCC_IRQn = 4, /*!< RCC Interrupt */ 85 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 86 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 87 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 88 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 89 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 90 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 91 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ 92 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ 93 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 94 TIM21_IRQn = 20, /*!< TIM21 Interrupt */ 95 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 96 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 97 USART2_IRQn = 28, /*!< USART2 Interrupt */ 98 AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ 99 } IRQn_Type; 100 101 /** 102 * @} 103 */ 104 105 #include "core_cm0plus.h" 106 #include "system_stm32l0xx.h" 107 #include <stdint.h> 108 109 /** @addtogroup Peripheral_registers_structures 110 * @{ 111 */ 112 113 /** 114 * @brief Analog to Digital Converter 115 */ 116 117 typedef struct 118 { 119 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ 120 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ 121 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ 122 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ 123 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ 124 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ 125 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 126 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 127 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ 128 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 129 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ 130 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 131 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ 132 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ 133 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ 134 } ADC_TypeDef; 135 136 typedef struct 137 { 138 __IO uint32_t CCR; 139 } ADC_Common_TypeDef; 140 141 /** 142 * @brief AES hardware accelerator 143 */ 144 145 typedef struct 146 { 147 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 148 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 149 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 150 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 151 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 152 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 153 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 154 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 155 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 156 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 157 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 158 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 159 } AES_TypeDef; 160 161 /** 162 * @brief Comparator 163 */ 164 165 typedef struct 166 { 167 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ 168 } COMP_TypeDef; 169 170 typedef struct 171 { 172 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 173 } COMP_Common_TypeDef; 174 175 176 /** 177 * @brief CRC calculation unit 178 */ 179 180 typedef struct 181 { 182 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 183 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 184 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 185 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 186 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 187 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 188 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 189 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 190 } CRC_TypeDef; 191 192 /** 193 * @brief Debug MCU 194 */ 195 196 typedef struct 197 { 198 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 199 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 200 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 201 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 202 }DBGMCU_TypeDef; 203 204 /** 205 * @brief DMA Controller 206 */ 207 208 typedef struct 209 { 210 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 211 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 212 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 213 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 214 } DMA_Channel_TypeDef; 215 216 typedef struct 217 { 218 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 219 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 220 } DMA_TypeDef; 221 222 typedef struct 223 { 224 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ 225 } DMA_Request_TypeDef; 226 227 /** 228 * @brief External Interrupt/Event Controller 229 */ 230 231 typedef struct 232 { 233 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 234 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 235 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 236 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 237 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 238 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 239 }EXTI_TypeDef; 240 241 /** 242 * @brief FLASH Registers 243 */ 244 typedef struct 245 { 246 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 247 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 248 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 249 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 250 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 251 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 252 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 253 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */ 254 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ 255 } FLASH_TypeDef; 256 257 258 /** 259 * @brief Option Bytes Registers 260 */ 261 typedef struct 262 { 263 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 264 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 265 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */ 266 } OB_TypeDef; 267 268 269 /** 270 * @brief General Purpose IO 271 */ 272 273 typedef struct 274 { 275 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 276 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 277 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 278 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 279 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 280 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 281 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 282 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 283 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 284 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 285 }GPIO_TypeDef; 286 287 /** 288 * @brief LPTIMIMER 289 */ 290 typedef struct 291 { 292 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 293 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 294 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 295 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 296 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 297 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 298 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 299 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 300 } LPTIM_TypeDef; 301 302 /** 303 * @brief SysTem Configuration 304 */ 305 306 typedef struct 307 { 308 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 309 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */ 310 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 311 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 312 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */ 313 } SYSCFG_TypeDef; 314 315 316 317 /** 318 * @brief Inter-integrated Circuit Interface 319 */ 320 321 typedef struct 322 { 323 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 324 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 325 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 326 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 327 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 328 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 329 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 330 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 331 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 332 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 333 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 334 }I2C_TypeDef; 335 336 337 /** 338 * @brief Independent WATCHDOG 339 */ 340 typedef struct 341 { 342 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 343 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 344 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 345 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 346 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 347 } IWDG_TypeDef; 348 349 /** 350 * @brief Power Control 351 */ 352 typedef struct 353 { 354 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 355 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 356 } PWR_TypeDef; 357 358 /** 359 * @brief Reset and Clock Control 360 */ 361 typedef struct 362 { 363 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 364 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 365 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */ 366 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */ 367 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */ 368 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */ 369 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */ 370 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */ 371 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */ 372 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ 373 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */ 374 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */ 375 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */ 376 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */ 377 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */ 378 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */ 379 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */ 380 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */ 381 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */ 382 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */ 383 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ 384 } RCC_TypeDef; 385 386 /** 387 * @brief Real-Time Clock 388 */ 389 typedef struct 390 { 391 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 392 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 393 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 394 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 395 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 396 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 397 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ 398 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 399 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 400 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 401 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 402 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 403 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 404 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 405 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 406 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 407 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ 408 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 409 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 410 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ 411 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 412 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 413 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 414 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 415 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 416 } RTC_TypeDef; 417 418 419 /** 420 * @brief Serial Peripheral Interface 421 */ 422 typedef struct 423 { 424 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 425 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 426 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 427 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 428 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 429 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 430 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 431 } SPI_TypeDef; 432 433 /** 434 * @brief TIM 435 */ 436 typedef struct 437 { 438 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 439 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 440 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 441 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 442 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 443 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 444 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 445 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 446 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 447 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 448 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 449 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 450 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */ 451 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 452 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 453 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 454 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 455 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */ 456 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 457 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 458 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 459 } TIM_TypeDef; 460 461 /** 462 * @brief Universal Synchronous Asynchronous Receiver Transmitter 463 */ 464 typedef struct 465 { 466 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 467 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 468 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 469 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 470 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 471 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 472 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 473 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 474 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 475 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 476 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 477 } USART_TypeDef; 478 479 /** 480 * @brief Window WATCHDOG 481 */ 482 typedef struct 483 { 484 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 485 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 486 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 487 } WWDG_TypeDef; 488 489 490 /** 491 * @} 492 */ 493 494 /** @addtogroup Peripheral_memory_map 495 * @{ 496 */ 497 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ 498 499 #define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */ 500 #define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */ 501 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ 502 #define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */ 503 504 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ 505 506 /*!< Peripheral memory map */ 507 #define APBPERIPH_BASE PERIPH_BASE 508 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 509 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL) 510 511 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) 512 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 513 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 514 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 515 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 516 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL) 517 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 518 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 519 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) 520 521 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 522 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL) 523 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL) 524 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) 525 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 526 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL) 527 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 528 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 529 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 530 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 531 532 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 533 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 534 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 535 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 536 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 537 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 538 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 539 540 541 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 542 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 543 #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ 544 #define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */ 545 #define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */ 546 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 547 #define AES_BASE (AHBPERIPH_BASE + 0x00006000UL) 548 549 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL) 550 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL) 551 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL) 552 553 /** 554 * @} 555 */ 556 557 /** @addtogroup Peripheral_declaration 558 * @{ 559 */ 560 561 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 562 #define RTC ((RTC_TypeDef *) RTC_BASE) 563 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 564 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 565 #define USART2 ((USART_TypeDef *) USART2_BASE) 566 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 567 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 568 #define PWR ((PWR_TypeDef *) PWR_BASE) 569 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 570 571 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 572 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 573 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 574 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 575 #define TIM21 ((TIM_TypeDef *) TIM21_BASE) 576 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 577 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 578 /* Legacy defines */ 579 #define ADC ADC1_COMMON 580 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 581 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 582 583 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 584 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 585 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 586 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 587 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 588 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 589 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) 590 591 592 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 593 #define OB ((OB_TypeDef *) OB_BASE) 594 #define RCC ((RCC_TypeDef *) RCC_BASE) 595 #define CRC ((CRC_TypeDef *) CRC_BASE) 596 #define AES ((AES_TypeDef *) AES_BASE) 597 598 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 599 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 600 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 601 602 /** 603 * @} 604 */ 605 606 /** @addtogroup Exported_constants 607 * @{ 608 */ 609 610 /** @addtogroup Hardware_Constant_Definition 611 * @{ 612 */ 613 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ 614 615 /** 616 * @} 617 */ 618 619 /** @addtogroup Peripheral_Registers_Bits_Definition 620 * @{ 621 */ 622 623 /******************************************************************************/ 624 /* Peripheral Registers Bits Definition */ 625 /******************************************************************************/ 626 /******************************************************************************/ 627 /* */ 628 /* Analog to Digital Converter (ADC) */ 629 /* */ 630 /******************************************************************************/ 631 /******************** Bits definition for ADC_ISR register ******************/ 632 #define ADC_ISR_EOCAL_Pos (11U) 633 #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 634 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ 635 #define ADC_ISR_AWD_Pos (7U) 636 #define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ 637 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ 638 #define ADC_ISR_OVR_Pos (4U) 639 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 640 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ 641 #define ADC_ISR_EOSEQ_Pos (3U) 642 #define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ 643 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ 644 #define ADC_ISR_EOC_Pos (2U) 645 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 646 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ 647 #define ADC_ISR_EOSMP_Pos (1U) 648 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 649 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ 650 #define ADC_ISR_ADRDY_Pos (0U) 651 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 652 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ 653 654 /* Old EOSEQ bit definition, maintained for legacy purpose */ 655 #define ADC_ISR_EOS ADC_ISR_EOSEQ 656 657 /******************** Bits definition for ADC_IER register ******************/ 658 #define ADC_IER_EOCALIE_Pos (11U) 659 #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 660 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ 661 #define ADC_IER_AWDIE_Pos (7U) 662 #define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ 663 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ 664 #define ADC_IER_OVRIE_Pos (4U) 665 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 666 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ 667 #define ADC_IER_EOSEQIE_Pos (3U) 668 #define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ 669 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ 670 #define ADC_IER_EOCIE_Pos (2U) 671 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 672 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ 673 #define ADC_IER_EOSMPIE_Pos (1U) 674 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 675 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ 676 #define ADC_IER_ADRDYIE_Pos (0U) 677 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 678 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ 679 680 /* Old EOSEQIE bit definition, maintained for legacy purpose */ 681 #define ADC_IER_EOSIE ADC_IER_EOSEQIE 682 683 /******************** Bits definition for ADC_CR register *******************/ 684 #define ADC_CR_ADCAL_Pos (31U) 685 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 686 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 687 #define ADC_CR_ADVREGEN_Pos (28U) 688 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 689 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ 690 #define ADC_CR_ADSTP_Pos (4U) 691 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 692 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ 693 #define ADC_CR_ADSTART_Pos (2U) 694 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 695 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ 696 #define ADC_CR_ADDIS_Pos (1U) 697 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 698 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ 699 #define ADC_CR_ADEN_Pos (0U) 700 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 701 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ 702 703 /******************* Bits definition for ADC_CFGR1 register *****************/ 704 #define ADC_CFGR1_AWDCH_Pos (26U) 705 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ 706 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ 707 #define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ 708 #define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ 709 #define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ 710 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ 711 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ 712 #define ADC_CFGR1_AWDEN_Pos (23U) 713 #define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ 714 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ 715 #define ADC_CFGR1_AWDSGL_Pos (22U) 716 #define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ 717 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ 718 #define ADC_CFGR1_DISCEN_Pos (16U) 719 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 720 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ 721 #define ADC_CFGR1_AUTOFF_Pos (15U) 722 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 723 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ 724 #define ADC_CFGR1_WAIT_Pos (14U) 725 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 726 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ 727 #define ADC_CFGR1_CONT_Pos (13U) 728 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 729 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ 730 #define ADC_CFGR1_OVRMOD_Pos (12U) 731 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 732 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ 733 #define ADC_CFGR1_EXTEN_Pos (10U) 734 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 735 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ 736 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 737 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 738 #define ADC_CFGR1_EXTSEL_Pos (6U) 739 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 740 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ 741 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 742 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 743 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 744 #define ADC_CFGR1_ALIGN_Pos (5U) 745 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 746 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ 747 #define ADC_CFGR1_RES_Pos (3U) 748 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 749 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ 750 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 751 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 752 #define ADC_CFGR1_SCANDIR_Pos (2U) 753 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 754 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ 755 #define ADC_CFGR1_DMACFG_Pos (1U) 756 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 757 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ 758 #define ADC_CFGR1_DMAEN_Pos (0U) 759 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 760 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ 761 762 /* Old WAIT bit definition, maintained for legacy purpose */ 763 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT 764 765 /******************* Bits definition for ADC_CFGR2 register *****************/ 766 #define ADC_CFGR2_TOVS_Pos (9U) 767 #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ 768 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ 769 #define ADC_CFGR2_OVSS_Pos (5U) 770 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 771 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ 772 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 773 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 774 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 775 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 776 #define ADC_CFGR2_OVSR_Pos (2U) 777 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 778 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ 779 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 780 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 781 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 782 #define ADC_CFGR2_OVSE_Pos (0U) 783 #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 784 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ 785 #define ADC_CFGR2_CKMODE_Pos (30U) 786 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 787 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ 788 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 789 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 790 791 792 /****************** Bit definition for ADC_SMPR register ********************/ 793 #define ADC_SMPR_SMP_Pos (0U) 794 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 795 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ 796 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 797 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 798 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 799 800 /* Legacy defines */ 801 #define ADC_SMPR_SMPR ADC_SMPR_SMP 802 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0 803 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1 804 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 805 806 /******************* Bit definition for ADC_TR register ********************/ 807 #define ADC_TR_HT_Pos (16U) 808 #define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ 809 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ 810 #define ADC_TR_LT_Pos (0U) 811 #define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */ 812 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ 813 814 /****************** Bit definition for ADC_CHSELR register ******************/ 815 #define ADC_CHSELR_CHSEL_Pos (0U) 816 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 817 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ 818 #define ADC_CHSELR_CHSEL18_Pos (18U) 819 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 820 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ 821 #define ADC_CHSELR_CHSEL17_Pos (17U) 822 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 823 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ 824 #define ADC_CHSELR_CHSEL15_Pos (15U) 825 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 826 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ 827 #define ADC_CHSELR_CHSEL14_Pos (14U) 828 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 829 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ 830 #define ADC_CHSELR_CHSEL13_Pos (13U) 831 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 832 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ 833 #define ADC_CHSELR_CHSEL12_Pos (12U) 834 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 835 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ 836 #define ADC_CHSELR_CHSEL11_Pos (11U) 837 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 838 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ 839 #define ADC_CHSELR_CHSEL10_Pos (10U) 840 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 841 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ 842 #define ADC_CHSELR_CHSEL9_Pos (9U) 843 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 844 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ 845 #define ADC_CHSELR_CHSEL8_Pos (8U) 846 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 847 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ 848 #define ADC_CHSELR_CHSEL7_Pos (7U) 849 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 850 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ 851 #define ADC_CHSELR_CHSEL6_Pos (6U) 852 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 853 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ 854 #define ADC_CHSELR_CHSEL5_Pos (5U) 855 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 856 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ 857 #define ADC_CHSELR_CHSEL4_Pos (4U) 858 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 859 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ 860 #define ADC_CHSELR_CHSEL3_Pos (3U) 861 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 862 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ 863 #define ADC_CHSELR_CHSEL2_Pos (2U) 864 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 865 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ 866 #define ADC_CHSELR_CHSEL1_Pos (1U) 867 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 868 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ 869 #define ADC_CHSELR_CHSEL0_Pos (0U) 870 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 871 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ 872 873 /******************** Bit definition for ADC_DR register ********************/ 874 #define ADC_DR_DATA_Pos (0U) 875 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 876 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ 877 878 /******************** Bit definition for ADC_CALFACT register ********************/ 879 #define ADC_CALFACT_CALFACT_Pos (0U) 880 #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 881 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ 882 883 /******************* Bit definition for ADC_CCR register ********************/ 884 #define ADC_CCR_LFMEN_Pos (25U) 885 #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ 886 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ 887 #define ADC_CCR_TSEN_Pos (23U) 888 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 889 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ 890 #define ADC_CCR_VREFEN_Pos (22U) 891 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 892 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ 893 #define ADC_CCR_PRESC_Pos (18U) 894 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 895 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ 896 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 897 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 898 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 899 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 900 901 /******************************************************************************/ 902 /* */ 903 /* Advanced Encryption Standard (AES) */ 904 /* */ 905 /******************************************************************************/ 906 /******************* Bit definition for AES_CR register *********************/ 907 #define AES_CR_EN_Pos (0U) 908 #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ 909 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 910 #define AES_CR_DATATYPE_Pos (1U) 911 #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 912 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 913 #define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 914 #define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 915 916 #define AES_CR_MODE_Pos (3U) 917 #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ 918 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 919 #define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ 920 #define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ 921 922 #define AES_CR_CHMOD_Pos (5U) 923 #define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */ 924 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 925 #define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 926 #define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 927 928 #define AES_CR_CCFC_Pos (7U) 929 #define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 930 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 931 #define AES_CR_ERRC_Pos (8U) 932 #define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 933 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 934 #define AES_CR_CCIE_Pos (9U) 935 #define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */ 936 #define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */ 937 #define AES_CR_ERRIE_Pos (10U) 938 #define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 939 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 940 #define AES_CR_DMAINEN_Pos (11U) 941 #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 942 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */ 943 #define AES_CR_DMAOUTEN_Pos (12U) 944 #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 945 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */ 946 947 /******************* Bit definition for AES_SR register *********************/ 948 #define AES_SR_CCF_Pos (0U) 949 #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ 950 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 951 #define AES_SR_RDERR_Pos (1U) 952 #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 953 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 954 #define AES_SR_WRERR_Pos (2U) 955 #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 956 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 957 958 /******************* Bit definition for AES_DINR register *******************/ 959 #define AES_DINR_Pos (0U) 960 #define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */ 961 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 962 963 /******************* Bit definition for AES_DOUTR register ******************/ 964 #define AES_DOUTR_Pos (0U) 965 #define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */ 966 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 967 968 /******************* Bit definition for AES_KEYR0 register ******************/ 969 #define AES_KEYR0_Pos (0U) 970 #define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */ 971 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 972 973 /******************* Bit definition for AES_KEYR1 register ******************/ 974 #define AES_KEYR1_Pos (0U) 975 #define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */ 976 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 977 978 /******************* Bit definition for AES_KEYR2 register ******************/ 979 #define AES_KEYR2_Pos (0U) 980 #define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */ 981 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 982 983 /******************* Bit definition for AES_KEYR3 register ******************/ 984 #define AES_KEYR3_Pos (0U) 985 #define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */ 986 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 987 988 /******************* Bit definition for AES_IVR0 register *******************/ 989 #define AES_IVR0_Pos (0U) 990 #define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */ 991 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 992 993 /******************* Bit definition for AES_IVR1 register *******************/ 994 #define AES_IVR1_Pos (0U) 995 #define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */ 996 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 997 998 /******************* Bit definition for AES_IVR2 register *******************/ 999 #define AES_IVR2_Pos (0U) 1000 #define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */ 1001 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 1002 1003 /******************* Bit definition for AES_IVR3 register *******************/ 1004 #define AES_IVR3_Pos (0U) 1005 #define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */ 1006 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 1007 1008 /******************************************************************************/ 1009 /* */ 1010 /* Analog Comparators (COMP) */ 1011 /* */ 1012 /******************************************************************************/ 1013 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ 1014 /* COMP1 bits definition */ 1015 #define COMP_CSR_COMP1EN_Pos (0U) 1016 #define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ 1017 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ 1018 #define COMP_CSR_COMP1INNSEL_Pos (4U) 1019 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ 1020 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ 1021 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ 1022 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ 1023 #define COMP_CSR_COMP1WM_Pos (8U) 1024 #define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ 1025 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ 1026 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) 1027 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ 1028 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ 1029 #define COMP_CSR_COMP1POLARITY_Pos (15U) 1030 #define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ 1031 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ 1032 #define COMP_CSR_COMP1VALUE_Pos (30U) 1033 #define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ 1034 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ 1035 #define COMP_CSR_COMP1LOCK_Pos (31U) 1036 #define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ 1037 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ 1038 /* COMP2 bits definition */ 1039 #define COMP_CSR_COMP2EN_Pos (0U) 1040 #define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ 1041 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ 1042 #define COMP_CSR_COMP2SPEED_Pos (3U) 1043 #define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ 1044 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ 1045 #define COMP_CSR_COMP2INNSEL_Pos (4U) 1046 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ 1047 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ 1048 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ 1049 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ 1050 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ 1051 #define COMP_CSR_COMP2INPSEL_Pos (8U) 1052 #define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ 1053 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ 1054 #define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ 1055 #define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ 1056 #define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ 1057 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) 1058 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ 1059 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ 1060 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) 1061 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ 1062 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ 1063 #define COMP_CSR_COMP2POLARITY_Pos (15U) 1064 #define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ 1065 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ 1066 #define COMP_CSR_COMP2VALUE_Pos (30U) 1067 #define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ 1068 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ 1069 #define COMP_CSR_COMP2LOCK_Pos (31U) 1070 #define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 1071 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 1072 1073 /********************** Bit definition for COMP_CSR register common ****************/ 1074 #define COMP_CSR_COMPxEN_Pos (0U) 1075 #define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 1076 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 1077 #define COMP_CSR_COMPxPOLARITY_Pos (15U) 1078 #define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ 1079 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ 1080 #define COMP_CSR_COMPxOUTVALUE_Pos (30U) 1081 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ 1082 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ 1083 #define COMP_CSR_COMPxLOCK_Pos (31U) 1084 #define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ 1085 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 1086 1087 /* Reference defines */ 1088 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1089 1090 /******************************************************************************/ 1091 /* */ 1092 /* CRC calculation unit (CRC) */ 1093 /* */ 1094 /******************************************************************************/ 1095 /******************* Bit definition for CRC_DR register *********************/ 1096 #define CRC_DR_DR_Pos (0U) 1097 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1098 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1099 1100 /******************* Bit definition for CRC_IDR register ********************/ 1101 #define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */ 1102 1103 /******************** Bit definition for CRC_CR register ********************/ 1104 #define CRC_CR_RESET_Pos (0U) 1105 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1106 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1107 #define CRC_CR_POLYSIZE_Pos (3U) 1108 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 1109 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 1110 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 1111 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 1112 #define CRC_CR_REV_IN_Pos (5U) 1113 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1114 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1115 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1116 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1117 #define CRC_CR_REV_OUT_Pos (7U) 1118 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1119 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1120 1121 /******************* Bit definition for CRC_INIT register *******************/ 1122 #define CRC_INIT_INIT_Pos (0U) 1123 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1124 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1125 1126 /******************* Bit definition for CRC_POL register ********************/ 1127 #define CRC_POL_POL_Pos (0U) 1128 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 1129 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 1130 1131 /******************************************************************************/ 1132 /* */ 1133 /* Debug MCU (DBGMCU) */ 1134 /* */ 1135 /******************************************************************************/ 1136 1137 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 1138 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 1139 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1140 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 1141 1142 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 1143 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1144 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 1145 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 1146 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 1147 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 1148 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 1149 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 1150 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 1151 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 1152 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 1153 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 1154 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 1155 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 1156 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 1157 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 1158 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 1159 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 1160 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 1161 1162 /****************** Bit definition for DBGMCU_CR register *******************/ 1163 #define DBGMCU_CR_DBG_Pos (0U) 1164 #define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ 1165 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ 1166 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 1167 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 1168 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 1169 #define DBGMCU_CR_DBG_STOP_Pos (1U) 1170 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1171 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 1172 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 1173 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1174 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 1175 1176 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 1177 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 1178 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 1179 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 1180 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 1181 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 1182 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 1183 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 1184 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1185 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 1186 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 1187 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1188 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 1189 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) 1190 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 1191 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 1192 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) 1193 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ 1194 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ 1195 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 1196 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) 1197 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ 1198 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ 1199 1200 /******************************************************************************/ 1201 /* */ 1202 /* DMA Controller (DMA) */ 1203 /* */ 1204 /******************************************************************************/ 1205 1206 /******************* Bit definition for DMA_ISR register ********************/ 1207 #define DMA_ISR_GIF1_Pos (0U) 1208 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1209 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1210 #define DMA_ISR_TCIF1_Pos (1U) 1211 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1212 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1213 #define DMA_ISR_HTIF1_Pos (2U) 1214 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1215 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1216 #define DMA_ISR_TEIF1_Pos (3U) 1217 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1218 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1219 #define DMA_ISR_GIF2_Pos (4U) 1220 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1221 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1222 #define DMA_ISR_TCIF2_Pos (5U) 1223 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1224 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1225 #define DMA_ISR_HTIF2_Pos (6U) 1226 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1227 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1228 #define DMA_ISR_TEIF2_Pos (7U) 1229 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1230 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1231 #define DMA_ISR_GIF3_Pos (8U) 1232 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1233 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1234 #define DMA_ISR_TCIF3_Pos (9U) 1235 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1236 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1237 #define DMA_ISR_HTIF3_Pos (10U) 1238 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1239 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1240 #define DMA_ISR_TEIF3_Pos (11U) 1241 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1242 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1243 #define DMA_ISR_GIF4_Pos (12U) 1244 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1245 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1246 #define DMA_ISR_TCIF4_Pos (13U) 1247 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1248 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1249 #define DMA_ISR_HTIF4_Pos (14U) 1250 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1251 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1252 #define DMA_ISR_TEIF4_Pos (15U) 1253 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1254 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1255 #define DMA_ISR_GIF5_Pos (16U) 1256 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1257 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1258 #define DMA_ISR_TCIF5_Pos (17U) 1259 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1260 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1261 #define DMA_ISR_HTIF5_Pos (18U) 1262 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1263 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1264 #define DMA_ISR_TEIF5_Pos (19U) 1265 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1266 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1267 1268 /******************* Bit definition for DMA_IFCR register *******************/ 1269 #define DMA_IFCR_CGIF1_Pos (0U) 1270 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1271 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1272 #define DMA_IFCR_CTCIF1_Pos (1U) 1273 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1274 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1275 #define DMA_IFCR_CHTIF1_Pos (2U) 1276 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1277 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1278 #define DMA_IFCR_CTEIF1_Pos (3U) 1279 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1280 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1281 #define DMA_IFCR_CGIF2_Pos (4U) 1282 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1283 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1284 #define DMA_IFCR_CTCIF2_Pos (5U) 1285 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1286 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1287 #define DMA_IFCR_CHTIF2_Pos (6U) 1288 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1289 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1290 #define DMA_IFCR_CTEIF2_Pos (7U) 1291 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1292 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1293 #define DMA_IFCR_CGIF3_Pos (8U) 1294 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1295 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1296 #define DMA_IFCR_CTCIF3_Pos (9U) 1297 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1298 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1299 #define DMA_IFCR_CHTIF3_Pos (10U) 1300 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1301 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1302 #define DMA_IFCR_CTEIF3_Pos (11U) 1303 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1304 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1305 #define DMA_IFCR_CGIF4_Pos (12U) 1306 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1307 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1308 #define DMA_IFCR_CTCIF4_Pos (13U) 1309 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1310 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1311 #define DMA_IFCR_CHTIF4_Pos (14U) 1312 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1313 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1314 #define DMA_IFCR_CTEIF4_Pos (15U) 1315 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1316 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1317 #define DMA_IFCR_CGIF5_Pos (16U) 1318 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1319 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1320 #define DMA_IFCR_CTCIF5_Pos (17U) 1321 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1322 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1323 #define DMA_IFCR_CHTIF5_Pos (18U) 1324 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1325 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1326 #define DMA_IFCR_CTEIF5_Pos (19U) 1327 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1328 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1329 1330 /******************* Bit definition for DMA_CCR register ********************/ 1331 #define DMA_CCR_EN_Pos (0U) 1332 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1333 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1334 #define DMA_CCR_TCIE_Pos (1U) 1335 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1336 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1337 #define DMA_CCR_HTIE_Pos (2U) 1338 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1339 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1340 #define DMA_CCR_TEIE_Pos (3U) 1341 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1342 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1343 #define DMA_CCR_DIR_Pos (4U) 1344 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1345 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1346 #define DMA_CCR_CIRC_Pos (5U) 1347 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1348 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1349 #define DMA_CCR_PINC_Pos (6U) 1350 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1351 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1352 #define DMA_CCR_MINC_Pos (7U) 1353 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1354 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1355 1356 #define DMA_CCR_PSIZE_Pos (8U) 1357 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1358 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1359 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1360 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1361 1362 #define DMA_CCR_MSIZE_Pos (10U) 1363 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1364 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1365 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1366 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1367 1368 #define DMA_CCR_PL_Pos (12U) 1369 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1370 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1371 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1372 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1373 1374 #define DMA_CCR_MEM2MEM_Pos (14U) 1375 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1376 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1377 1378 /****************** Bit definition for DMA_CNDTR register *******************/ 1379 #define DMA_CNDTR_NDT_Pos (0U) 1380 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1381 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1382 1383 /****************** Bit definition for DMA_CPAR register ********************/ 1384 #define DMA_CPAR_PA_Pos (0U) 1385 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1386 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1387 1388 /****************** Bit definition for DMA_CMAR register ********************/ 1389 #define DMA_CMAR_MA_Pos (0U) 1390 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1391 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1392 1393 1394 /******************* Bit definition for DMA_CSELR register *******************/ 1395 #define DMA_CSELR_C1S_Pos (0U) 1396 #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ 1397 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ 1398 #define DMA_CSELR_C2S_Pos (4U) 1399 #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ 1400 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ 1401 #define DMA_CSELR_C3S_Pos (8U) 1402 #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ 1403 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ 1404 #define DMA_CSELR_C4S_Pos (12U) 1405 #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ 1406 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ 1407 #define DMA_CSELR_C5S_Pos (16U) 1408 #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ 1409 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ 1410 1411 /******************************************************************************/ 1412 /* */ 1413 /* External Interrupt/Event Controller (EXTI) */ 1414 /* */ 1415 /******************************************************************************/ 1416 1417 /******************* Bit definition for EXTI_IMR register *******************/ 1418 #define EXTI_IMR_IM0_Pos (0U) 1419 #define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ 1420 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ 1421 #define EXTI_IMR_IM1_Pos (1U) 1422 #define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ 1423 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ 1424 #define EXTI_IMR_IM2_Pos (2U) 1425 #define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ 1426 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ 1427 #define EXTI_IMR_IM3_Pos (3U) 1428 #define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ 1429 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ 1430 #define EXTI_IMR_IM4_Pos (4U) 1431 #define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ 1432 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ 1433 #define EXTI_IMR_IM5_Pos (5U) 1434 #define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ 1435 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ 1436 #define EXTI_IMR_IM6_Pos (6U) 1437 #define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ 1438 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ 1439 #define EXTI_IMR_IM7_Pos (7U) 1440 #define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ 1441 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ 1442 #define EXTI_IMR_IM8_Pos (8U) 1443 #define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ 1444 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ 1445 #define EXTI_IMR_IM9_Pos (9U) 1446 #define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ 1447 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ 1448 #define EXTI_IMR_IM10_Pos (10U) 1449 #define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ 1450 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ 1451 #define EXTI_IMR_IM11_Pos (11U) 1452 #define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ 1453 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ 1454 #define EXTI_IMR_IM12_Pos (12U) 1455 #define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ 1456 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ 1457 #define EXTI_IMR_IM13_Pos (13U) 1458 #define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ 1459 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ 1460 #define EXTI_IMR_IM14_Pos (14U) 1461 #define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ 1462 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ 1463 #define EXTI_IMR_IM15_Pos (15U) 1464 #define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ 1465 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ 1466 #define EXTI_IMR_IM16_Pos (16U) 1467 #define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ 1468 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ 1469 #define EXTI_IMR_IM17_Pos (17U) 1470 #define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ 1471 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ 1472 #define EXTI_IMR_IM18_Pos (18U) 1473 #define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ 1474 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ 1475 #define EXTI_IMR_IM19_Pos (19U) 1476 #define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ 1477 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ 1478 #define EXTI_IMR_IM20_Pos (20U) 1479 #define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ 1480 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ 1481 #define EXTI_IMR_IM21_Pos (21U) 1482 #define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ 1483 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ 1484 #define EXTI_IMR_IM22_Pos (22U) 1485 #define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ 1486 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ 1487 #define EXTI_IMR_IM23_Pos (23U) 1488 #define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ 1489 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ 1490 #define EXTI_IMR_IM25_Pos (25U) 1491 #define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ 1492 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ 1493 #define EXTI_IMR_IM26_Pos (26U) 1494 #define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ 1495 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ 1496 #define EXTI_IMR_IM28_Pos (28U) 1497 #define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ 1498 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ 1499 #define EXTI_IMR_IM29_Pos (29U) 1500 #define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ 1501 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ 1502 1503 #define EXTI_IMR_IM_Pos (0U) 1504 #define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ 1505 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1506 1507 /****************** Bit definition for EXTI_EMR register ********************/ 1508 #define EXTI_EMR_EM0_Pos (0U) 1509 #define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ 1510 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ 1511 #define EXTI_EMR_EM1_Pos (1U) 1512 #define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ 1513 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ 1514 #define EXTI_EMR_EM2_Pos (2U) 1515 #define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ 1516 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ 1517 #define EXTI_EMR_EM3_Pos (3U) 1518 #define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ 1519 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ 1520 #define EXTI_EMR_EM4_Pos (4U) 1521 #define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ 1522 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ 1523 #define EXTI_EMR_EM5_Pos (5U) 1524 #define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ 1525 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ 1526 #define EXTI_EMR_EM6_Pos (6U) 1527 #define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ 1528 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ 1529 #define EXTI_EMR_EM7_Pos (7U) 1530 #define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ 1531 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ 1532 #define EXTI_EMR_EM8_Pos (8U) 1533 #define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ 1534 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ 1535 #define EXTI_EMR_EM9_Pos (9U) 1536 #define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ 1537 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ 1538 #define EXTI_EMR_EM10_Pos (10U) 1539 #define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ 1540 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ 1541 #define EXTI_EMR_EM11_Pos (11U) 1542 #define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ 1543 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ 1544 #define EXTI_EMR_EM12_Pos (12U) 1545 #define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ 1546 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ 1547 #define EXTI_EMR_EM13_Pos (13U) 1548 #define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ 1549 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ 1550 #define EXTI_EMR_EM14_Pos (14U) 1551 #define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ 1552 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ 1553 #define EXTI_EMR_EM15_Pos (15U) 1554 #define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ 1555 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ 1556 #define EXTI_EMR_EM16_Pos (16U) 1557 #define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ 1558 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ 1559 #define EXTI_EMR_EM17_Pos (17U) 1560 #define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ 1561 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ 1562 #define EXTI_EMR_EM18_Pos (18U) 1563 #define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ 1564 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ 1565 #define EXTI_EMR_EM19_Pos (19U) 1566 #define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ 1567 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ 1568 #define EXTI_EMR_EM20_Pos (20U) 1569 #define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ 1570 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ 1571 #define EXTI_EMR_EM21_Pos (21U) 1572 #define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ 1573 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ 1574 #define EXTI_EMR_EM22_Pos (22U) 1575 #define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ 1576 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ 1577 #define EXTI_EMR_EM23_Pos (23U) 1578 #define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ 1579 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ 1580 #define EXTI_EMR_EM25_Pos (25U) 1581 #define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ 1582 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ 1583 #define EXTI_EMR_EM26_Pos (26U) 1584 #define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ 1585 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ 1586 #define EXTI_EMR_EM28_Pos (28U) 1587 #define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ 1588 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ 1589 #define EXTI_EMR_EM29_Pos (29U) 1590 #define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ 1591 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ 1592 1593 /******************* Bit definition for EXTI_RTSR register ******************/ 1594 #define EXTI_RTSR_RT0_Pos (0U) 1595 #define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ 1596 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1597 #define EXTI_RTSR_RT1_Pos (1U) 1598 #define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ 1599 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1600 #define EXTI_RTSR_RT2_Pos (2U) 1601 #define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ 1602 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1603 #define EXTI_RTSR_RT3_Pos (3U) 1604 #define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ 1605 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1606 #define EXTI_RTSR_RT4_Pos (4U) 1607 #define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ 1608 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1609 #define EXTI_RTSR_RT5_Pos (5U) 1610 #define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ 1611 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1612 #define EXTI_RTSR_RT6_Pos (6U) 1613 #define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ 1614 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1615 #define EXTI_RTSR_RT7_Pos (7U) 1616 #define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ 1617 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1618 #define EXTI_RTSR_RT8_Pos (8U) 1619 #define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ 1620 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1621 #define EXTI_RTSR_RT9_Pos (9U) 1622 #define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ 1623 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1624 #define EXTI_RTSR_RT10_Pos (10U) 1625 #define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ 1626 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1627 #define EXTI_RTSR_RT11_Pos (11U) 1628 #define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ 1629 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1630 #define EXTI_RTSR_RT12_Pos (12U) 1631 #define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ 1632 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1633 #define EXTI_RTSR_RT13_Pos (13U) 1634 #define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ 1635 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1636 #define EXTI_RTSR_RT14_Pos (14U) 1637 #define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ 1638 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1639 #define EXTI_RTSR_RT15_Pos (15U) 1640 #define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ 1641 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1642 #define EXTI_RTSR_RT16_Pos (16U) 1643 #define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ 1644 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1645 #define EXTI_RTSR_RT17_Pos (17U) 1646 #define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ 1647 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1648 #define EXTI_RTSR_RT19_Pos (19U) 1649 #define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ 1650 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1651 #define EXTI_RTSR_RT20_Pos (20U) 1652 #define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ 1653 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 1654 #define EXTI_RTSR_RT21_Pos (21U) 1655 #define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ 1656 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 1657 #define EXTI_RTSR_RT22_Pos (22U) 1658 #define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ 1659 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 1660 1661 /* Legacy defines */ 1662 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 1663 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1 1664 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2 1665 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3 1666 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4 1667 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5 1668 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6 1669 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7 1670 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8 1671 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9 1672 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10 1673 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11 1674 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12 1675 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13 1676 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14 1677 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15 1678 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16 1679 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17 1680 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19 1681 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20 1682 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21 1683 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 1684 1685 /******************* Bit definition for EXTI_FTSR register *******************/ 1686 #define EXTI_FTSR_FT0_Pos (0U) 1687 #define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ 1688 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1689 #define EXTI_FTSR_FT1_Pos (1U) 1690 #define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ 1691 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1692 #define EXTI_FTSR_FT2_Pos (2U) 1693 #define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ 1694 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1695 #define EXTI_FTSR_FT3_Pos (3U) 1696 #define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ 1697 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1698 #define EXTI_FTSR_FT4_Pos (4U) 1699 #define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ 1700 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1701 #define EXTI_FTSR_FT5_Pos (5U) 1702 #define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ 1703 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1704 #define EXTI_FTSR_FT6_Pos (6U) 1705 #define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ 1706 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1707 #define EXTI_FTSR_FT7_Pos (7U) 1708 #define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ 1709 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1710 #define EXTI_FTSR_FT8_Pos (8U) 1711 #define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ 1712 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1713 #define EXTI_FTSR_FT9_Pos (9U) 1714 #define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ 1715 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1716 #define EXTI_FTSR_FT10_Pos (10U) 1717 #define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ 1718 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1719 #define EXTI_FTSR_FT11_Pos (11U) 1720 #define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ 1721 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1722 #define EXTI_FTSR_FT12_Pos (12U) 1723 #define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ 1724 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1725 #define EXTI_FTSR_FT13_Pos (13U) 1726 #define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ 1727 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1728 #define EXTI_FTSR_FT14_Pos (14U) 1729 #define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ 1730 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1731 #define EXTI_FTSR_FT15_Pos (15U) 1732 #define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ 1733 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1734 #define EXTI_FTSR_FT16_Pos (16U) 1735 #define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ 1736 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1737 #define EXTI_FTSR_FT17_Pos (17U) 1738 #define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ 1739 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1740 #define EXTI_FTSR_FT19_Pos (19U) 1741 #define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ 1742 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1743 #define EXTI_FTSR_FT20_Pos (20U) 1744 #define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ 1745 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 1746 #define EXTI_FTSR_FT21_Pos (21U) 1747 #define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ 1748 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 1749 #define EXTI_FTSR_FT22_Pos (22U) 1750 #define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ 1751 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 1752 1753 /* Legacy defines */ 1754 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 1755 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1 1756 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2 1757 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3 1758 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4 1759 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5 1760 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6 1761 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7 1762 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8 1763 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9 1764 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10 1765 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11 1766 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12 1767 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13 1768 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14 1769 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15 1770 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16 1771 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17 1772 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19 1773 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20 1774 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21 1775 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 1776 1777 /******************* Bit definition for EXTI_SWIER register *******************/ 1778 #define EXTI_SWIER_SWI0_Pos (0U) 1779 #define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ 1780 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ 1781 #define EXTI_SWIER_SWI1_Pos (1U) 1782 #define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ 1783 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ 1784 #define EXTI_SWIER_SWI2_Pos (2U) 1785 #define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ 1786 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ 1787 #define EXTI_SWIER_SWI3_Pos (3U) 1788 #define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ 1789 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ 1790 #define EXTI_SWIER_SWI4_Pos (4U) 1791 #define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ 1792 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ 1793 #define EXTI_SWIER_SWI5_Pos (5U) 1794 #define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ 1795 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ 1796 #define EXTI_SWIER_SWI6_Pos (6U) 1797 #define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ 1798 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ 1799 #define EXTI_SWIER_SWI7_Pos (7U) 1800 #define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ 1801 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ 1802 #define EXTI_SWIER_SWI8_Pos (8U) 1803 #define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ 1804 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ 1805 #define EXTI_SWIER_SWI9_Pos (9U) 1806 #define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ 1807 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ 1808 #define EXTI_SWIER_SWI10_Pos (10U) 1809 #define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ 1810 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ 1811 #define EXTI_SWIER_SWI11_Pos (11U) 1812 #define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ 1813 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ 1814 #define EXTI_SWIER_SWI12_Pos (12U) 1815 #define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ 1816 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ 1817 #define EXTI_SWIER_SWI13_Pos (13U) 1818 #define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ 1819 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ 1820 #define EXTI_SWIER_SWI14_Pos (14U) 1821 #define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ 1822 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ 1823 #define EXTI_SWIER_SWI15_Pos (15U) 1824 #define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ 1825 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ 1826 #define EXTI_SWIER_SWI16_Pos (16U) 1827 #define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ 1828 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ 1829 #define EXTI_SWIER_SWI17_Pos (17U) 1830 #define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ 1831 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ 1832 #define EXTI_SWIER_SWI19_Pos (19U) 1833 #define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ 1834 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ 1835 #define EXTI_SWIER_SWI20_Pos (20U) 1836 #define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ 1837 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ 1838 #define EXTI_SWIER_SWI21_Pos (21U) 1839 #define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ 1840 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ 1841 #define EXTI_SWIER_SWI22_Pos (22U) 1842 #define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ 1843 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ 1844 1845 /* Legacy defines */ 1846 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 1847 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1 1848 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2 1849 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3 1850 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4 1851 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5 1852 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6 1853 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7 1854 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8 1855 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9 1856 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10 1857 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11 1858 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12 1859 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13 1860 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14 1861 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15 1862 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16 1863 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17 1864 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19 1865 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20 1866 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21 1867 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 1868 1869 /****************** Bit definition for EXTI_PR register *********************/ 1870 #define EXTI_PR_PIF0_Pos (0U) 1871 #define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ 1872 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ 1873 #define EXTI_PR_PIF1_Pos (1U) 1874 #define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ 1875 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ 1876 #define EXTI_PR_PIF2_Pos (2U) 1877 #define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ 1878 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ 1879 #define EXTI_PR_PIF3_Pos (3U) 1880 #define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ 1881 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ 1882 #define EXTI_PR_PIF4_Pos (4U) 1883 #define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ 1884 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ 1885 #define EXTI_PR_PIF5_Pos (5U) 1886 #define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ 1887 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ 1888 #define EXTI_PR_PIF6_Pos (6U) 1889 #define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ 1890 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ 1891 #define EXTI_PR_PIF7_Pos (7U) 1892 #define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ 1893 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ 1894 #define EXTI_PR_PIF8_Pos (8U) 1895 #define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ 1896 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ 1897 #define EXTI_PR_PIF9_Pos (9U) 1898 #define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ 1899 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ 1900 #define EXTI_PR_PIF10_Pos (10U) 1901 #define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ 1902 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ 1903 #define EXTI_PR_PIF11_Pos (11U) 1904 #define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ 1905 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ 1906 #define EXTI_PR_PIF12_Pos (12U) 1907 #define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ 1908 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ 1909 #define EXTI_PR_PIF13_Pos (13U) 1910 #define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ 1911 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ 1912 #define EXTI_PR_PIF14_Pos (14U) 1913 #define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ 1914 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ 1915 #define EXTI_PR_PIF15_Pos (15U) 1916 #define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ 1917 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ 1918 #define EXTI_PR_PIF16_Pos (16U) 1919 #define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ 1920 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ 1921 #define EXTI_PR_PIF17_Pos (17U) 1922 #define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ 1923 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ 1924 #define EXTI_PR_PIF19_Pos (19U) 1925 #define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ 1926 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ 1927 #define EXTI_PR_PIF20_Pos (20U) 1928 #define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ 1929 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ 1930 #define EXTI_PR_PIF21_Pos (21U) 1931 #define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ 1932 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ 1933 #define EXTI_PR_PIF22_Pos (22U) 1934 #define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ 1935 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ 1936 1937 /* Legacy defines */ 1938 #define EXTI_PR_PR0 EXTI_PR_PIF0 1939 #define EXTI_PR_PR1 EXTI_PR_PIF1 1940 #define EXTI_PR_PR2 EXTI_PR_PIF2 1941 #define EXTI_PR_PR3 EXTI_PR_PIF3 1942 #define EXTI_PR_PR4 EXTI_PR_PIF4 1943 #define EXTI_PR_PR5 EXTI_PR_PIF5 1944 #define EXTI_PR_PR6 EXTI_PR_PIF6 1945 #define EXTI_PR_PR7 EXTI_PR_PIF7 1946 #define EXTI_PR_PR8 EXTI_PR_PIF8 1947 #define EXTI_PR_PR9 EXTI_PR_PIF9 1948 #define EXTI_PR_PR10 EXTI_PR_PIF10 1949 #define EXTI_PR_PR11 EXTI_PR_PIF11 1950 #define EXTI_PR_PR12 EXTI_PR_PIF12 1951 #define EXTI_PR_PR13 EXTI_PR_PIF13 1952 #define EXTI_PR_PR14 EXTI_PR_PIF14 1953 #define EXTI_PR_PR15 EXTI_PR_PIF15 1954 #define EXTI_PR_PR16 EXTI_PR_PIF16 1955 #define EXTI_PR_PR17 EXTI_PR_PIF17 1956 #define EXTI_PR_PR19 EXTI_PR_PIF19 1957 #define EXTI_PR_PR20 EXTI_PR_PIF20 1958 #define EXTI_PR_PR21 EXTI_PR_PIF21 1959 #define EXTI_PR_PR22 EXTI_PR_PIF22 1960 1961 /******************************************************************************/ 1962 /* */ 1963 /* FLASH and Option Bytes Registers */ 1964 /* */ 1965 /******************************************************************************/ 1966 1967 /******************* Bit definition for FLASH_ACR register ******************/ 1968 #define FLASH_ACR_LATENCY_Pos (0U) 1969 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 1970 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 1971 #define FLASH_ACR_PRFTEN_Pos (1U) 1972 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 1973 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 1974 #define FLASH_ACR_SLEEP_PD_Pos (3U) 1975 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 1976 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 1977 #define FLASH_ACR_RUN_PD_Pos (4U) 1978 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 1979 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 1980 #define FLASH_ACR_DISAB_BUF_Pos (5U) 1981 #define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ 1982 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ 1983 #define FLASH_ACR_PRE_READ_Pos (6U) 1984 #define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ 1985 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ 1986 1987 /******************* Bit definition for FLASH_PECR register ******************/ 1988 #define FLASH_PECR_PELOCK_Pos (0U) 1989 #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 1990 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 1991 #define FLASH_PECR_PRGLOCK_Pos (1U) 1992 #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 1993 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 1994 #define FLASH_PECR_OPTLOCK_Pos (2U) 1995 #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 1996 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 1997 #define FLASH_PECR_PROG_Pos (3U) 1998 #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 1999 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 2000 #define FLASH_PECR_DATA_Pos (4U) 2001 #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 2002 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 2003 #define FLASH_PECR_FIX_Pos (8U) 2004 #define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ 2005 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 2006 #define FLASH_PECR_ERASE_Pos (9U) 2007 #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 2008 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 2009 #define FLASH_PECR_FPRG_Pos (10U) 2010 #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 2011 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 2012 #define FLASH_PECR_EOPIE_Pos (16U) 2013 #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 2014 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 2015 #define FLASH_PECR_ERRIE_Pos (17U) 2016 #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 2017 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 2018 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 2019 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 2020 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 2021 #define FLASH_PECR_HALF_ARRAY_Pos (19U) 2022 #define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ 2023 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ 2024 2025 /****************** Bit definition for FLASH_PDKEYR register ******************/ 2026 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 2027 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 2028 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2029 2030 /****************** Bit definition for FLASH_PEKEYR register ******************/ 2031 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 2032 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 2033 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2034 2035 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 2036 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 2037 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 2038 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 2039 2040 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 2041 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 2042 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 2043 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 2044 2045 /****************** Bit definition for FLASH_SR register *******************/ 2046 #define FLASH_SR_BSY_Pos (0U) 2047 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 2048 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 2049 #define FLASH_SR_EOP_Pos (1U) 2050 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 2051 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 2052 #define FLASH_SR_HVOFF_Pos (2U) 2053 #define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ 2054 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ 2055 #define FLASH_SR_READY_Pos (3U) 2056 #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 2057 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 2058 2059 #define FLASH_SR_WRPERR_Pos (8U) 2060 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 2061 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ 2062 #define FLASH_SR_PGAERR_Pos (9U) 2063 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 2064 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 2065 #define FLASH_SR_SIZERR_Pos (10U) 2066 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 2067 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 2068 #define FLASH_SR_OPTVERR_Pos (11U) 2069 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 2070 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ 2071 #define FLASH_SR_RDERR_Pos (13U) 2072 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ 2073 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ 2074 #define FLASH_SR_NOTZEROERR_Pos (16U) 2075 #define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ 2076 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ 2077 #define FLASH_SR_FWWERR_Pos (17U) 2078 #define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ 2079 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ 2080 2081 /* Legacy defines */ 2082 #define FLASH_SR_FWWER FLASH_SR_FWWERR 2083 #define FLASH_SR_ENHV FLASH_SR_HVOFF 2084 #define FLASH_SR_ENDHV FLASH_SR_HVOFF 2085 2086 /****************** Bit definition for FLASH_OPTR register *******************/ 2087 #define FLASH_OPTR_RDPROT_Pos (0U) 2088 #define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ 2089 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ 2090 #define FLASH_OPTR_WPRMOD_Pos (8U) 2091 #define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ 2092 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ 2093 #define FLASH_OPTR_BOR_LEV_Pos (16U) 2094 #define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ 2095 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 2096 #define FLASH_OPTR_IWDG_SW_Pos (20U) 2097 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ 2098 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ 2099 #define FLASH_OPTR_nRST_STOP_Pos (21U) 2100 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ 2101 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ 2102 #define FLASH_OPTR_nRST_STDBY_Pos (22U) 2103 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ 2104 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2105 #define FLASH_OPTR_USER_Pos (20U) 2106 #define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ 2107 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ 2108 #define FLASH_OPTR_BOOT1_Pos (31U) 2109 #define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ 2110 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ 2111 2112 /****************** Bit definition for FLASH_WRPR register ******************/ 2113 #define FLASH_WRPR_WRP_Pos (0U) 2114 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 2115 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ 2116 2117 /******************************************************************************/ 2118 /* */ 2119 /* General Purpose IOs (GPIO) */ 2120 /* */ 2121 /******************************************************************************/ 2122 /******************* Bit definition for GPIO_MODER register *****************/ 2123 #define GPIO_MODER_MODE0_Pos (0U) 2124 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 2125 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 2126 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 2127 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 2128 #define GPIO_MODER_MODE1_Pos (2U) 2129 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 2130 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 2131 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 2132 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 2133 #define GPIO_MODER_MODE2_Pos (4U) 2134 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 2135 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 2136 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 2137 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 2138 #define GPIO_MODER_MODE3_Pos (6U) 2139 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 2140 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 2141 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 2142 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 2143 #define GPIO_MODER_MODE4_Pos (8U) 2144 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 2145 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 2146 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 2147 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 2148 #define GPIO_MODER_MODE5_Pos (10U) 2149 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 2150 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 2151 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 2152 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 2153 #define GPIO_MODER_MODE6_Pos (12U) 2154 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 2155 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 2156 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 2157 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 2158 #define GPIO_MODER_MODE7_Pos (14U) 2159 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 2160 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 2161 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 2162 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 2163 #define GPIO_MODER_MODE8_Pos (16U) 2164 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 2165 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 2166 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 2167 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 2168 #define GPIO_MODER_MODE9_Pos (18U) 2169 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 2170 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 2171 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 2172 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 2173 #define GPIO_MODER_MODE10_Pos (20U) 2174 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 2175 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 2176 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 2177 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 2178 #define GPIO_MODER_MODE11_Pos (22U) 2179 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 2180 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 2181 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 2182 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 2183 #define GPIO_MODER_MODE12_Pos (24U) 2184 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 2185 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 2186 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 2187 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 2188 #define GPIO_MODER_MODE13_Pos (26U) 2189 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 2190 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 2191 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 2192 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 2193 #define GPIO_MODER_MODE14_Pos (28U) 2194 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 2195 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 2196 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 2197 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 2198 #define GPIO_MODER_MODE15_Pos (30U) 2199 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 2200 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 2201 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 2202 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 2203 2204 /****************** Bit definition for GPIO_OTYPER register *****************/ 2205 #define GPIO_OTYPER_OT_0 (0x00000001U) 2206 #define GPIO_OTYPER_OT_1 (0x00000002U) 2207 #define GPIO_OTYPER_OT_2 (0x00000004U) 2208 #define GPIO_OTYPER_OT_3 (0x00000008U) 2209 #define GPIO_OTYPER_OT_4 (0x00000010U) 2210 #define GPIO_OTYPER_OT_5 (0x00000020U) 2211 #define GPIO_OTYPER_OT_6 (0x00000040U) 2212 #define GPIO_OTYPER_OT_7 (0x00000080U) 2213 #define GPIO_OTYPER_OT_8 (0x00000100U) 2214 #define GPIO_OTYPER_OT_9 (0x00000200U) 2215 #define GPIO_OTYPER_OT_10 (0x00000400U) 2216 #define GPIO_OTYPER_OT_11 (0x00000800U) 2217 #define GPIO_OTYPER_OT_12 (0x00001000U) 2218 #define GPIO_OTYPER_OT_13 (0x00002000U) 2219 #define GPIO_OTYPER_OT_14 (0x00004000U) 2220 #define GPIO_OTYPER_OT_15 (0x00008000U) 2221 2222 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 2223 #define GPIO_OSPEEDER_OSPEED0_Pos (0U) 2224 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ 2225 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk 2226 #define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ 2227 #define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ 2228 #define GPIO_OSPEEDER_OSPEED1_Pos (2U) 2229 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ 2230 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk 2231 #define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ 2232 #define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ 2233 #define GPIO_OSPEEDER_OSPEED2_Pos (4U) 2234 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ 2235 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk 2236 #define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ 2237 #define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ 2238 #define GPIO_OSPEEDER_OSPEED3_Pos (6U) 2239 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ 2240 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk 2241 #define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ 2242 #define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ 2243 #define GPIO_OSPEEDER_OSPEED4_Pos (8U) 2244 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ 2245 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk 2246 #define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ 2247 #define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ 2248 #define GPIO_OSPEEDER_OSPEED5_Pos (10U) 2249 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ 2250 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk 2251 #define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ 2252 #define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ 2253 #define GPIO_OSPEEDER_OSPEED6_Pos (12U) 2254 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ 2255 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk 2256 #define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ 2257 #define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ 2258 #define GPIO_OSPEEDER_OSPEED7_Pos (14U) 2259 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ 2260 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk 2261 #define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ 2262 #define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ 2263 #define GPIO_OSPEEDER_OSPEED8_Pos (16U) 2264 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ 2265 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk 2266 #define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ 2267 #define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ 2268 #define GPIO_OSPEEDER_OSPEED9_Pos (18U) 2269 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ 2270 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk 2271 #define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ 2272 #define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ 2273 #define GPIO_OSPEEDER_OSPEED10_Pos (20U) 2274 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ 2275 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk 2276 #define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ 2277 #define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ 2278 #define GPIO_OSPEEDER_OSPEED11_Pos (22U) 2279 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ 2280 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk 2281 #define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ 2282 #define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ 2283 #define GPIO_OSPEEDER_OSPEED12_Pos (24U) 2284 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ 2285 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk 2286 #define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ 2287 #define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ 2288 #define GPIO_OSPEEDER_OSPEED13_Pos (26U) 2289 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ 2290 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk 2291 #define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ 2292 #define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ 2293 #define GPIO_OSPEEDER_OSPEED14_Pos (28U) 2294 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ 2295 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk 2296 #define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ 2297 #define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ 2298 #define GPIO_OSPEEDER_OSPEED15_Pos (30U) 2299 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ 2300 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk 2301 #define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ 2302 #define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ 2303 2304 /******************* Bit definition for GPIO_PUPDR register ******************/ 2305 #define GPIO_PUPDR_PUPD0_Pos (0U) 2306 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 2307 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 2308 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 2309 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 2310 #define GPIO_PUPDR_PUPD1_Pos (2U) 2311 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 2312 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 2313 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 2314 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 2315 #define GPIO_PUPDR_PUPD2_Pos (4U) 2316 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 2317 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 2318 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 2319 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 2320 #define GPIO_PUPDR_PUPD3_Pos (6U) 2321 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 2322 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 2323 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 2324 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 2325 #define GPIO_PUPDR_PUPD4_Pos (8U) 2326 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 2327 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 2328 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 2329 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 2330 #define GPIO_PUPDR_PUPD5_Pos (10U) 2331 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 2332 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 2333 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 2334 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 2335 #define GPIO_PUPDR_PUPD6_Pos (12U) 2336 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 2337 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 2338 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 2339 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 2340 #define GPIO_PUPDR_PUPD7_Pos (14U) 2341 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 2342 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 2343 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 2344 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 2345 #define GPIO_PUPDR_PUPD8_Pos (16U) 2346 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 2347 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 2348 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 2349 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 2350 #define GPIO_PUPDR_PUPD9_Pos (18U) 2351 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 2352 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 2353 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 2354 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 2355 #define GPIO_PUPDR_PUPD10_Pos (20U) 2356 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 2357 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 2358 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 2359 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 2360 #define GPIO_PUPDR_PUPD11_Pos (22U) 2361 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 2362 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 2363 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 2364 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 2365 #define GPIO_PUPDR_PUPD12_Pos (24U) 2366 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 2367 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 2368 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 2369 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 2370 #define GPIO_PUPDR_PUPD13_Pos (26U) 2371 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 2372 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 2373 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 2374 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 2375 #define GPIO_PUPDR_PUPD14_Pos (28U) 2376 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 2377 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 2378 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 2379 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 2380 #define GPIO_PUPDR_PUPD15_Pos (30U) 2381 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 2382 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 2383 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 2384 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 2385 2386 /******************* Bit definition for GPIO_IDR register *******************/ 2387 #define GPIO_IDR_ID0_Pos (0U) 2388 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 2389 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 2390 #define GPIO_IDR_ID1_Pos (1U) 2391 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 2392 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 2393 #define GPIO_IDR_ID2_Pos (2U) 2394 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 2395 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 2396 #define GPIO_IDR_ID3_Pos (3U) 2397 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 2398 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 2399 #define GPIO_IDR_ID4_Pos (4U) 2400 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 2401 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 2402 #define GPIO_IDR_ID5_Pos (5U) 2403 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 2404 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 2405 #define GPIO_IDR_ID6_Pos (6U) 2406 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 2407 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 2408 #define GPIO_IDR_ID7_Pos (7U) 2409 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 2410 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 2411 #define GPIO_IDR_ID8_Pos (8U) 2412 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 2413 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 2414 #define GPIO_IDR_ID9_Pos (9U) 2415 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 2416 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 2417 #define GPIO_IDR_ID10_Pos (10U) 2418 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 2419 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 2420 #define GPIO_IDR_ID11_Pos (11U) 2421 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 2422 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 2423 #define GPIO_IDR_ID12_Pos (12U) 2424 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 2425 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 2426 #define GPIO_IDR_ID13_Pos (13U) 2427 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 2428 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 2429 #define GPIO_IDR_ID14_Pos (14U) 2430 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 2431 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 2432 #define GPIO_IDR_ID15_Pos (15U) 2433 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 2434 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 2435 2436 /****************** Bit definition for GPIO_ODR register ********************/ 2437 #define GPIO_ODR_OD0_Pos (0U) 2438 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 2439 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 2440 #define GPIO_ODR_OD1_Pos (1U) 2441 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 2442 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 2443 #define GPIO_ODR_OD2_Pos (2U) 2444 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 2445 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 2446 #define GPIO_ODR_OD3_Pos (3U) 2447 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 2448 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 2449 #define GPIO_ODR_OD4_Pos (4U) 2450 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 2451 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 2452 #define GPIO_ODR_OD5_Pos (5U) 2453 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 2454 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 2455 #define GPIO_ODR_OD6_Pos (6U) 2456 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 2457 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 2458 #define GPIO_ODR_OD7_Pos (7U) 2459 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 2460 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 2461 #define GPIO_ODR_OD8_Pos (8U) 2462 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 2463 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 2464 #define GPIO_ODR_OD9_Pos (9U) 2465 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 2466 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 2467 #define GPIO_ODR_OD10_Pos (10U) 2468 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 2469 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 2470 #define GPIO_ODR_OD11_Pos (11U) 2471 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 2472 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 2473 #define GPIO_ODR_OD12_Pos (12U) 2474 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 2475 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 2476 #define GPIO_ODR_OD13_Pos (13U) 2477 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 2478 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 2479 #define GPIO_ODR_OD14_Pos (14U) 2480 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 2481 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 2482 #define GPIO_ODR_OD15_Pos (15U) 2483 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 2484 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 2485 2486 /****************** Bit definition for GPIO_BSRR register ********************/ 2487 #define GPIO_BSRR_BS_0 (0x00000001U) 2488 #define GPIO_BSRR_BS_1 (0x00000002U) 2489 #define GPIO_BSRR_BS_2 (0x00000004U) 2490 #define GPIO_BSRR_BS_3 (0x00000008U) 2491 #define GPIO_BSRR_BS_4 (0x00000010U) 2492 #define GPIO_BSRR_BS_5 (0x00000020U) 2493 #define GPIO_BSRR_BS_6 (0x00000040U) 2494 #define GPIO_BSRR_BS_7 (0x00000080U) 2495 #define GPIO_BSRR_BS_8 (0x00000100U) 2496 #define GPIO_BSRR_BS_9 (0x00000200U) 2497 #define GPIO_BSRR_BS_10 (0x00000400U) 2498 #define GPIO_BSRR_BS_11 (0x00000800U) 2499 #define GPIO_BSRR_BS_12 (0x00001000U) 2500 #define GPIO_BSRR_BS_13 (0x00002000U) 2501 #define GPIO_BSRR_BS_14 (0x00004000U) 2502 #define GPIO_BSRR_BS_15 (0x00008000U) 2503 #define GPIO_BSRR_BR_0 (0x00010000U) 2504 #define GPIO_BSRR_BR_1 (0x00020000U) 2505 #define GPIO_BSRR_BR_2 (0x00040000U) 2506 #define GPIO_BSRR_BR_3 (0x00080000U) 2507 #define GPIO_BSRR_BR_4 (0x00100000U) 2508 #define GPIO_BSRR_BR_5 (0x00200000U) 2509 #define GPIO_BSRR_BR_6 (0x00400000U) 2510 #define GPIO_BSRR_BR_7 (0x00800000U) 2511 #define GPIO_BSRR_BR_8 (0x01000000U) 2512 #define GPIO_BSRR_BR_9 (0x02000000U) 2513 #define GPIO_BSRR_BR_10 (0x04000000U) 2514 #define GPIO_BSRR_BR_11 (0x08000000U) 2515 #define GPIO_BSRR_BR_12 (0x10000000U) 2516 #define GPIO_BSRR_BR_13 (0x20000000U) 2517 #define GPIO_BSRR_BR_14 (0x40000000U) 2518 #define GPIO_BSRR_BR_15 (0x80000000U) 2519 2520 /****************** Bit definition for GPIO_LCKR register ********************/ 2521 #define GPIO_LCKR_LCK0_Pos (0U) 2522 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2523 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2524 #define GPIO_LCKR_LCK1_Pos (1U) 2525 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2526 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2527 #define GPIO_LCKR_LCK2_Pos (2U) 2528 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2529 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2530 #define GPIO_LCKR_LCK3_Pos (3U) 2531 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2532 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2533 #define GPIO_LCKR_LCK4_Pos (4U) 2534 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2535 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2536 #define GPIO_LCKR_LCK5_Pos (5U) 2537 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2538 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2539 #define GPIO_LCKR_LCK6_Pos (6U) 2540 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2541 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2542 #define GPIO_LCKR_LCK7_Pos (7U) 2543 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2544 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2545 #define GPIO_LCKR_LCK8_Pos (8U) 2546 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2547 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2548 #define GPIO_LCKR_LCK9_Pos (9U) 2549 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2550 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2551 #define GPIO_LCKR_LCK10_Pos (10U) 2552 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2553 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2554 #define GPIO_LCKR_LCK11_Pos (11U) 2555 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2556 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2557 #define GPIO_LCKR_LCK12_Pos (12U) 2558 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2559 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2560 #define GPIO_LCKR_LCK13_Pos (13U) 2561 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2562 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2563 #define GPIO_LCKR_LCK14_Pos (14U) 2564 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2565 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2566 #define GPIO_LCKR_LCK15_Pos (15U) 2567 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2568 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2569 #define GPIO_LCKR_LCKK_Pos (16U) 2570 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2571 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2572 2573 /****************** Bit definition for GPIO_AFRL register ********************/ 2574 #define GPIO_AFRL_AFSEL0_Pos (0U) 2575 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 2576 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 2577 #define GPIO_AFRL_AFSEL1_Pos (4U) 2578 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 2579 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 2580 #define GPIO_AFRL_AFSEL2_Pos (8U) 2581 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 2582 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 2583 #define GPIO_AFRL_AFSEL3_Pos (12U) 2584 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 2585 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 2586 #define GPIO_AFRL_AFSEL4_Pos (16U) 2587 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 2588 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 2589 #define GPIO_AFRL_AFSEL5_Pos (20U) 2590 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 2591 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 2592 #define GPIO_AFRL_AFSEL6_Pos (24U) 2593 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 2594 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 2595 #define GPIO_AFRL_AFSEL7_Pos (28U) 2596 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 2597 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 2598 2599 /****************** Bit definition for GPIO_AFRH register ********************/ 2600 #define GPIO_AFRH_AFSEL8_Pos (0U) 2601 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 2602 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 2603 #define GPIO_AFRH_AFSEL9_Pos (4U) 2604 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 2605 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 2606 #define GPIO_AFRH_AFSEL10_Pos (8U) 2607 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 2608 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 2609 #define GPIO_AFRH_AFSEL11_Pos (12U) 2610 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 2611 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 2612 #define GPIO_AFRH_AFSEL12_Pos (16U) 2613 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 2614 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 2615 #define GPIO_AFRH_AFSEL13_Pos (20U) 2616 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 2617 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 2618 #define GPIO_AFRH_AFSEL14_Pos (24U) 2619 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 2620 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 2621 #define GPIO_AFRH_AFSEL15_Pos (28U) 2622 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 2623 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 2624 2625 /****************** Bit definition for GPIO_BRR register *********************/ 2626 #define GPIO_BRR_BR_0 (0x00000001U) 2627 #define GPIO_BRR_BR_1 (0x00000002U) 2628 #define GPIO_BRR_BR_2 (0x00000004U) 2629 #define GPIO_BRR_BR_3 (0x00000008U) 2630 #define GPIO_BRR_BR_4 (0x00000010U) 2631 #define GPIO_BRR_BR_5 (0x00000020U) 2632 #define GPIO_BRR_BR_6 (0x00000040U) 2633 #define GPIO_BRR_BR_7 (0x00000080U) 2634 #define GPIO_BRR_BR_8 (0x00000100U) 2635 #define GPIO_BRR_BR_9 (0x00000200U) 2636 #define GPIO_BRR_BR_10 (0x00000400U) 2637 #define GPIO_BRR_BR_11 (0x00000800U) 2638 #define GPIO_BRR_BR_12 (0x00001000U) 2639 #define GPIO_BRR_BR_13 (0x00002000U) 2640 #define GPIO_BRR_BR_14 (0x00004000U) 2641 #define GPIO_BRR_BR_15 (0x00008000U) 2642 2643 /******************************************************************************/ 2644 /* */ 2645 /* Inter-integrated Circuit Interface (I2C) */ 2646 /* */ 2647 /******************************************************************************/ 2648 2649 /******************* Bit definition for I2C_CR1 register *******************/ 2650 #define I2C_CR1_PE_Pos (0U) 2651 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2652 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2653 #define I2C_CR1_TXIE_Pos (1U) 2654 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2655 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2656 #define I2C_CR1_RXIE_Pos (2U) 2657 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2658 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2659 #define I2C_CR1_ADDRIE_Pos (3U) 2660 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2661 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2662 #define I2C_CR1_NACKIE_Pos (4U) 2663 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2664 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2665 #define I2C_CR1_STOPIE_Pos (5U) 2666 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2667 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2668 #define I2C_CR1_TCIE_Pos (6U) 2669 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2670 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2671 #define I2C_CR1_ERRIE_Pos (7U) 2672 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2673 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2674 #define I2C_CR1_DNF_Pos (8U) 2675 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2676 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2677 #define I2C_CR1_ANFOFF_Pos (12U) 2678 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2679 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2680 #define I2C_CR1_TXDMAEN_Pos (14U) 2681 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2682 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2683 #define I2C_CR1_RXDMAEN_Pos (15U) 2684 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2685 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2686 #define I2C_CR1_SBC_Pos (16U) 2687 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2688 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2689 #define I2C_CR1_NOSTRETCH_Pos (17U) 2690 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2691 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2692 #define I2C_CR1_WUPEN_Pos (18U) 2693 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 2694 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 2695 #define I2C_CR1_GCEN_Pos (19U) 2696 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2697 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2698 #define I2C_CR1_SMBHEN_Pos (20U) 2699 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2700 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2701 #define I2C_CR1_SMBDEN_Pos (21U) 2702 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2703 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2704 #define I2C_CR1_ALERTEN_Pos (22U) 2705 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2706 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2707 #define I2C_CR1_PECEN_Pos (23U) 2708 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2709 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2710 2711 /****************** Bit definition for I2C_CR2 register ********************/ 2712 #define I2C_CR2_SADD_Pos (0U) 2713 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2714 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2715 #define I2C_CR2_RD_WRN_Pos (10U) 2716 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2717 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2718 #define I2C_CR2_ADD10_Pos (11U) 2719 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2720 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2721 #define I2C_CR2_HEAD10R_Pos (12U) 2722 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2723 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2724 #define I2C_CR2_START_Pos (13U) 2725 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2726 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 2727 #define I2C_CR2_STOP_Pos (14U) 2728 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 2729 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 2730 #define I2C_CR2_NACK_Pos (15U) 2731 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 2732 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 2733 #define I2C_CR2_NBYTES_Pos (16U) 2734 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 2735 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 2736 #define I2C_CR2_RELOAD_Pos (24U) 2737 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 2738 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 2739 #define I2C_CR2_AUTOEND_Pos (25U) 2740 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 2741 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 2742 #define I2C_CR2_PECBYTE_Pos (26U) 2743 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 2744 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 2745 2746 /******************* Bit definition for I2C_OAR1 register ******************/ 2747 #define I2C_OAR1_OA1_Pos (0U) 2748 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 2749 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 2750 #define I2C_OAR1_OA1MODE_Pos (10U) 2751 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 2752 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 2753 #define I2C_OAR1_OA1EN_Pos (15U) 2754 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 2755 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 2756 2757 /******************* Bit definition for I2C_OAR2 register ******************/ 2758 #define I2C_OAR2_OA2_Pos (1U) 2759 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 2760 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 2761 #define I2C_OAR2_OA2MSK_Pos (8U) 2762 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 2763 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 2764 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 2765 #define I2C_OAR2_OA2MASK01_Pos (8U) 2766 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 2767 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 2768 #define I2C_OAR2_OA2MASK02_Pos (9U) 2769 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 2770 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 2771 #define I2C_OAR2_OA2MASK03_Pos (8U) 2772 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 2773 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 2774 #define I2C_OAR2_OA2MASK04_Pos (10U) 2775 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 2776 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 2777 #define I2C_OAR2_OA2MASK05_Pos (8U) 2778 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 2779 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 2780 #define I2C_OAR2_OA2MASK06_Pos (9U) 2781 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 2782 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 2783 #define I2C_OAR2_OA2MASK07_Pos (8U) 2784 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 2785 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 2786 #define I2C_OAR2_OA2EN_Pos (15U) 2787 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 2788 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 2789 2790 /******************* Bit definition for I2C_TIMINGR register *******************/ 2791 #define I2C_TIMINGR_SCLL_Pos (0U) 2792 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 2793 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 2794 #define I2C_TIMINGR_SCLH_Pos (8U) 2795 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 2796 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 2797 #define I2C_TIMINGR_SDADEL_Pos (16U) 2798 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 2799 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 2800 #define I2C_TIMINGR_SCLDEL_Pos (20U) 2801 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 2802 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 2803 #define I2C_TIMINGR_PRESC_Pos (28U) 2804 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 2805 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 2806 2807 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 2808 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 2809 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 2810 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 2811 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 2812 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 2813 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 2814 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 2815 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 2816 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 2817 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 2818 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 2819 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 2820 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 2821 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 2822 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 2823 2824 /****************** Bit definition for I2C_ISR register *********************/ 2825 #define I2C_ISR_TXE_Pos (0U) 2826 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 2827 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 2828 #define I2C_ISR_TXIS_Pos (1U) 2829 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 2830 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 2831 #define I2C_ISR_RXNE_Pos (2U) 2832 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 2833 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 2834 #define I2C_ISR_ADDR_Pos (3U) 2835 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 2836 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 2837 #define I2C_ISR_NACKF_Pos (4U) 2838 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 2839 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 2840 #define I2C_ISR_STOPF_Pos (5U) 2841 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 2842 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 2843 #define I2C_ISR_TC_Pos (6U) 2844 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 2845 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 2846 #define I2C_ISR_TCR_Pos (7U) 2847 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 2848 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 2849 #define I2C_ISR_BERR_Pos (8U) 2850 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 2851 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 2852 #define I2C_ISR_ARLO_Pos (9U) 2853 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 2854 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 2855 #define I2C_ISR_OVR_Pos (10U) 2856 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 2857 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 2858 #define I2C_ISR_PECERR_Pos (11U) 2859 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 2860 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 2861 #define I2C_ISR_TIMEOUT_Pos (12U) 2862 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 2863 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 2864 #define I2C_ISR_ALERT_Pos (13U) 2865 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 2866 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 2867 #define I2C_ISR_BUSY_Pos (15U) 2868 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 2869 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 2870 #define I2C_ISR_DIR_Pos (16U) 2871 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 2872 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 2873 #define I2C_ISR_ADDCODE_Pos (17U) 2874 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 2875 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 2876 2877 /****************** Bit definition for I2C_ICR register *********************/ 2878 #define I2C_ICR_ADDRCF_Pos (3U) 2879 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 2880 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 2881 #define I2C_ICR_NACKCF_Pos (4U) 2882 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 2883 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 2884 #define I2C_ICR_STOPCF_Pos (5U) 2885 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 2886 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 2887 #define I2C_ICR_BERRCF_Pos (8U) 2888 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 2889 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 2890 #define I2C_ICR_ARLOCF_Pos (9U) 2891 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 2892 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 2893 #define I2C_ICR_OVRCF_Pos (10U) 2894 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 2895 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 2896 #define I2C_ICR_PECCF_Pos (11U) 2897 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 2898 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 2899 #define I2C_ICR_TIMOUTCF_Pos (12U) 2900 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 2901 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 2902 #define I2C_ICR_ALERTCF_Pos (13U) 2903 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 2904 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 2905 2906 /****************** Bit definition for I2C_PECR register *********************/ 2907 #define I2C_PECR_PEC_Pos (0U) 2908 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 2909 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 2910 2911 /****************** Bit definition for I2C_RXDR register *********************/ 2912 #define I2C_RXDR_RXDATA_Pos (0U) 2913 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 2914 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 2915 2916 /****************** Bit definition for I2C_TXDR register *********************/ 2917 #define I2C_TXDR_TXDATA_Pos (0U) 2918 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 2919 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 2920 2921 /******************************************************************************/ 2922 /* */ 2923 /* Independent WATCHDOG (IWDG) */ 2924 /* */ 2925 /******************************************************************************/ 2926 /******************* Bit definition for IWDG_KR register ********************/ 2927 #define IWDG_KR_KEY_Pos (0U) 2928 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 2929 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 2930 2931 /******************* Bit definition for IWDG_PR register ********************/ 2932 #define IWDG_PR_PR_Pos (0U) 2933 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 2934 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 2935 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 2936 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 2937 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 2938 2939 /******************* Bit definition for IWDG_RLR register *******************/ 2940 #define IWDG_RLR_RL_Pos (0U) 2941 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 2942 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 2943 2944 /******************* Bit definition for IWDG_SR register ********************/ 2945 #define IWDG_SR_PVU_Pos (0U) 2946 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 2947 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 2948 #define IWDG_SR_RVU_Pos (1U) 2949 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 2950 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 2951 #define IWDG_SR_WVU_Pos (2U) 2952 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 2953 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 2954 2955 /******************* Bit definition for IWDG_KR register ********************/ 2956 #define IWDG_WINR_WIN_Pos (0U) 2957 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 2958 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 2959 2960 /******************************************************************************/ 2961 /* */ 2962 /* Low Power Timer (LPTTIM) */ 2963 /* */ 2964 /******************************************************************************/ 2965 /****************** Bit definition for LPTIM_ISR register *******************/ 2966 #define LPTIM_ISR_CMPM_Pos (0U) 2967 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 2968 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 2969 #define LPTIM_ISR_ARRM_Pos (1U) 2970 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 2971 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 2972 #define LPTIM_ISR_EXTTRIG_Pos (2U) 2973 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 2974 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 2975 #define LPTIM_ISR_CMPOK_Pos (3U) 2976 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 2977 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 2978 #define LPTIM_ISR_ARROK_Pos (4U) 2979 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 2980 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 2981 #define LPTIM_ISR_UP_Pos (5U) 2982 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 2983 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 2984 #define LPTIM_ISR_DOWN_Pos (6U) 2985 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 2986 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 2987 2988 /****************** Bit definition for LPTIM_ICR register *******************/ 2989 #define LPTIM_ICR_CMPMCF_Pos (0U) 2990 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 2991 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 2992 #define LPTIM_ICR_ARRMCF_Pos (1U) 2993 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 2994 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 2995 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 2996 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 2997 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 2998 #define LPTIM_ICR_CMPOKCF_Pos (3U) 2999 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 3000 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 3001 #define LPTIM_ICR_ARROKCF_Pos (4U) 3002 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 3003 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 3004 #define LPTIM_ICR_UPCF_Pos (5U) 3005 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 3006 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 3007 #define LPTIM_ICR_DOWNCF_Pos (6U) 3008 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 3009 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 3010 3011 /****************** Bit definition for LPTIM_IER register ********************/ 3012 #define LPTIM_IER_CMPMIE_Pos (0U) 3013 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 3014 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 3015 #define LPTIM_IER_ARRMIE_Pos (1U) 3016 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 3017 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 3018 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 3019 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 3020 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 3021 #define LPTIM_IER_CMPOKIE_Pos (3U) 3022 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 3023 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 3024 #define LPTIM_IER_ARROKIE_Pos (4U) 3025 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 3026 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 3027 #define LPTIM_IER_UPIE_Pos (5U) 3028 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 3029 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 3030 #define LPTIM_IER_DOWNIE_Pos (6U) 3031 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 3032 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 3033 3034 /****************** Bit definition for LPTIM_CFGR register *******************/ 3035 #define LPTIM_CFGR_CKSEL_Pos (0U) 3036 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 3037 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 3038 3039 #define LPTIM_CFGR_CKPOL_Pos (1U) 3040 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 3041 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 3042 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 3043 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 3044 3045 #define LPTIM_CFGR_CKFLT_Pos (3U) 3046 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 3047 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 3048 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 3049 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 3050 3051 #define LPTIM_CFGR_TRGFLT_Pos (6U) 3052 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 3053 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 3054 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 3055 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 3056 3057 #define LPTIM_CFGR_PRESC_Pos (9U) 3058 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 3059 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 3060 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 3061 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 3062 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 3063 3064 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 3065 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 3066 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 3067 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 3068 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 3069 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 3070 3071 #define LPTIM_CFGR_TRIGEN_Pos (17U) 3072 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 3073 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 3074 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 3075 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 3076 3077 #define LPTIM_CFGR_TIMOUT_Pos (19U) 3078 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 3079 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 3080 #define LPTIM_CFGR_WAVE_Pos (20U) 3081 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 3082 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 3083 #define LPTIM_CFGR_WAVPOL_Pos (21U) 3084 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 3085 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 3086 #define LPTIM_CFGR_PRELOAD_Pos (22U) 3087 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 3088 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 3089 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 3090 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 3091 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 3092 #define LPTIM_CFGR_ENC_Pos (24U) 3093 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 3094 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 3095 3096 /****************** Bit definition for LPTIM_CR register ********************/ 3097 #define LPTIM_CR_ENABLE_Pos (0U) 3098 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 3099 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 3100 #define LPTIM_CR_SNGSTRT_Pos (1U) 3101 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 3102 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 3103 #define LPTIM_CR_CNTSTRT_Pos (2U) 3104 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 3105 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 3106 3107 /****************** Bit definition for LPTIM_CMP register *******************/ 3108 #define LPTIM_CMP_CMP_Pos (0U) 3109 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 3110 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 3111 3112 /****************** Bit definition for LPTIM_ARR register *******************/ 3113 #define LPTIM_ARR_ARR_Pos (0U) 3114 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 3115 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 3116 3117 /****************** Bit definition for LPTIM_CNT register *******************/ 3118 #define LPTIM_CNT_CNT_Pos (0U) 3119 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 3120 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 3121 3122 /******************************************************************************/ 3123 /* */ 3124 /* Power Control (PWR) */ 3125 /* */ 3126 /******************************************************************************/ 3127 3128 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ 3129 3130 /******************** Bit definition for PWR_CR register ********************/ 3131 #define PWR_CR_LPSDSR_Pos (0U) 3132 #define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 3133 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 3134 #define PWR_CR_PDDS_Pos (1U) 3135 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 3136 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 3137 #define PWR_CR_CWUF_Pos (2U) 3138 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 3139 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 3140 #define PWR_CR_CSBF_Pos (3U) 3141 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 3142 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 3143 #define PWR_CR_PVDE_Pos (4U) 3144 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 3145 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 3146 3147 #define PWR_CR_PLS_Pos (5U) 3148 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 3149 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 3150 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 3151 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 3152 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 3153 3154 /*!< PVD level configuration */ 3155 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 3156 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 3157 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 3158 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 3159 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 3160 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 3161 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 3162 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 3163 3164 #define PWR_CR_DBP_Pos (8U) 3165 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 3166 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 3167 #define PWR_CR_ULP_Pos (9U) 3168 #define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 3169 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 3170 #define PWR_CR_FWU_Pos (10U) 3171 #define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 3172 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 3173 3174 #define PWR_CR_VOS_Pos (11U) 3175 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 3176 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 3177 #define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 3178 #define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 3179 #define PWR_CR_DSEEKOFF_Pos (13U) 3180 #define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ 3181 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ 3182 #define PWR_CR_LPRUN_Pos (14U) 3183 #define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 3184 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 3185 #define PWR_CR_LPDS_Pos (16U) 3186 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00010000 */ 3187 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */ 3188 3189 /******************* Bit definition for PWR_CSR register ********************/ 3190 #define PWR_CSR_WUF_Pos (0U) 3191 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 3192 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 3193 #define PWR_CSR_SBF_Pos (1U) 3194 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 3195 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 3196 #define PWR_CSR_PVDO_Pos (2U) 3197 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 3198 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 3199 #define PWR_CSR_VREFINTRDYF_Pos (3U) 3200 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 3201 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 3202 #define PWR_CSR_VOSF_Pos (4U) 3203 #define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 3204 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 3205 #define PWR_CSR_REGLPF_Pos (5U) 3206 #define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 3207 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 3208 3209 #define PWR_CSR_EWUP1_Pos (8U) 3210 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3211 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3212 #define PWR_CSR_EWUP3_Pos (10U) 3213 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 3214 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 3215 3216 /******************************************************************************/ 3217 /* */ 3218 /* Reset and Clock Control */ 3219 /* */ 3220 /******************************************************************************/ 3221 /* 3222 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 3223 */ 3224 /* Note: No specific macro feature on this device */ 3225 3226 /******************** Bit definition for RCC_CR register ********************/ 3227 #define RCC_CR_HSION_Pos (0U) 3228 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3229 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3230 #define RCC_CR_HSIKERON_Pos (1U) 3231 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ 3232 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ 3233 #define RCC_CR_HSIRDY_Pos (2U) 3234 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ 3235 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3236 #define RCC_CR_HSIDIVEN_Pos (3U) 3237 #define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ 3238 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ 3239 #define RCC_CR_HSIDIVF_Pos (4U) 3240 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ 3241 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ 3242 #define RCC_CR_HSIOUTEN_Pos (5U) 3243 #define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ 3244 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ 3245 #define RCC_CR_MSION_Pos (8U) 3246 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 3247 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 3248 #define RCC_CR_MSIRDY_Pos (9U) 3249 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 3250 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 3251 #define RCC_CR_HSEON_Pos (16U) 3252 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3253 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3254 #define RCC_CR_HSERDY_Pos (17U) 3255 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3256 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3257 #define RCC_CR_HSEBYP_Pos (18U) 3258 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3259 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3260 #define RCC_CR_RTCPRE_Pos (20U) 3261 #define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ 3262 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */ 3263 #define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ 3264 #define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ 3265 #define RCC_CR_PLLON_Pos (24U) 3266 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3267 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3268 #define RCC_CR_PLLRDY_Pos (25U) 3269 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3270 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3271 3272 /* Reference defines */ 3273 3274 /******************** Bit definition for RCC_ICSCR register *****************/ 3275 #define RCC_ICSCR_HSICAL_Pos (0U) 3276 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 3277 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3278 #define RCC_ICSCR_HSITRIM_Pos (8U) 3279 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 3280 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3281 3282 #define RCC_ICSCR_MSIRANGE_Pos (13U) 3283 #define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 3284 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 3285 #define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 3286 #define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 3287 #define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 3288 #define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 3289 #define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 3290 #define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 3291 #define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 3292 #define RCC_ICSCR_MSICAL_Pos (16U) 3293 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 3294 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 3295 #define RCC_ICSCR_MSITRIM_Pos (24U) 3296 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 3297 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 3298 3299 3300 /******************* Bit definition for RCC_CFGR register *******************/ 3301 /*!< SW configuration */ 3302 #define RCC_CFGR_SW_Pos (0U) 3303 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3304 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3305 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3306 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3307 3308 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 3309 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 3310 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 3311 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 3312 3313 /*!< SWS configuration */ 3314 #define RCC_CFGR_SWS_Pos (2U) 3315 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3316 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3317 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3318 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3319 3320 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 3321 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 3322 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 3323 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 3324 3325 /*!< HPRE configuration */ 3326 #define RCC_CFGR_HPRE_Pos (4U) 3327 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3328 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3329 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3330 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3331 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3332 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3333 3334 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3335 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3336 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3337 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3338 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3339 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3340 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3341 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3342 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3343 3344 /*!< PPRE1 configuration */ 3345 #define RCC_CFGR_PPRE1_Pos (8U) 3346 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 3347 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 3348 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 3349 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 3350 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 3351 3352 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 3353 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 3354 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 3355 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 3356 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 3357 3358 /*!< PPRE2 configuration */ 3359 #define RCC_CFGR_PPRE2_Pos (11U) 3360 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 3361 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 3362 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 3363 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 3364 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 3365 3366 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 3367 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 3368 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 3369 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 3370 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 3371 3372 #define RCC_CFGR_STOPWUCK_Pos (15U) 3373 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 3374 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ 3375 3376 /*!< PLL entry clock source*/ 3377 #define RCC_CFGR_PLLSRC_Pos (16U) 3378 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 3379 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3380 3381 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 3382 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 3383 3384 3385 /*!< PLLMUL configuration */ 3386 #define RCC_CFGR_PLLMUL_Pos (18U) 3387 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3388 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3389 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3390 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 3391 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 3392 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 3393 3394 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 3395 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 3396 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 3397 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 3398 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 3399 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 3400 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 3401 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 3402 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 3403 3404 /*!< PLLDIV configuration */ 3405 #define RCC_CFGR_PLLDIV_Pos (22U) 3406 #define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 3407 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 3408 #define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 3409 #define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 3410 3411 #define RCC_CFGR_PLLDIV2_Pos (22U) 3412 #define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 3413 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 3414 #define RCC_CFGR_PLLDIV3_Pos (23U) 3415 #define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 3416 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 3417 #define RCC_CFGR_PLLDIV4_Pos (22U) 3418 #define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 3419 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 3420 3421 /*!< MCO configuration */ 3422 #define RCC_CFGR_MCOSEL_Pos (24U) 3423 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 3424 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 3425 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 3426 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 3427 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 3428 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 3429 3430 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3431 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 3432 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 3433 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ 3434 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 3435 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 3436 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 3437 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 3438 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 3439 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 3440 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 3441 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 3442 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 3443 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 3444 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 3445 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 3446 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 3447 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 3448 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 3449 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 3450 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 3451 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 3452 3453 #define RCC_CFGR_MCOPRE_Pos (28U) 3454 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 3455 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 3456 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 3457 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 3458 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 3459 3460 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 3461 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 3462 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 3463 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 3464 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 3465 3466 /* Legacy defines */ 3467 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 3468 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 3469 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 3470 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 3471 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 3472 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 3473 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 3474 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 3475 #ifdef RCC_CFGR_MCOSEL_HSI48 3476 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 3477 #endif 3478 3479 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ 3480 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ 3481 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ 3482 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */ 3483 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */ 3484 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ 3485 3486 /*!<****************** Bit definition for RCC_CIER register ********************/ 3487 #define RCC_CIER_LSIRDYIE_Pos (0U) 3488 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 3489 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 3490 #define RCC_CIER_LSERDYIE_Pos (1U) 3491 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 3492 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 3493 #define RCC_CIER_HSIRDYIE_Pos (2U) 3494 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ 3495 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 3496 #define RCC_CIER_HSERDYIE_Pos (3U) 3497 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ 3498 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 3499 #define RCC_CIER_PLLRDYIE_Pos (4U) 3500 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ 3501 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 3502 #define RCC_CIER_MSIRDYIE_Pos (5U) 3503 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ 3504 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 3505 #define RCC_CIER_CSSLSE_Pos (7U) 3506 #define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ 3507 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ 3508 3509 /* Reference defines */ 3510 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE 3511 3512 /*!<****************** Bit definition for RCC_CIFR register ********************/ 3513 #define RCC_CIFR_LSIRDYF_Pos (0U) 3514 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 3515 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 3516 #define RCC_CIFR_LSERDYF_Pos (1U) 3517 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 3518 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 3519 #define RCC_CIFR_HSIRDYF_Pos (2U) 3520 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ 3521 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 3522 #define RCC_CIFR_HSERDYF_Pos (3U) 3523 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ 3524 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 3525 #define RCC_CIFR_PLLRDYF_Pos (4U) 3526 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ 3527 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 3528 #define RCC_CIFR_MSIRDYF_Pos (5U) 3529 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ 3530 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 3531 #define RCC_CIFR_CSSLSEF_Pos (7U) 3532 #define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ 3533 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ 3534 3535 /* Reference defines */ 3536 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF 3537 3538 /*!<****************** Bit definition for RCC_CICR register ********************/ 3539 #define RCC_CICR_LSIRDYC_Pos (0U) 3540 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 3541 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 3542 #define RCC_CICR_LSERDYC_Pos (1U) 3543 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 3544 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 3545 #define RCC_CICR_HSIRDYC_Pos (2U) 3546 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ 3547 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3548 #define RCC_CICR_HSERDYC_Pos (3U) 3549 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ 3550 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3551 #define RCC_CICR_PLLRDYC_Pos (4U) 3552 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ 3553 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3554 #define RCC_CICR_MSIRDYC_Pos (5U) 3555 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ 3556 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 3557 #define RCC_CICR_CSSLSEC_Pos (7U) 3558 #define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ 3559 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ 3560 3561 /* Reference defines */ 3562 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC 3563 /***************** Bit definition for RCC_IOPRSTR register ******************/ 3564 #define RCC_IOPRSTR_IOPARST_Pos (0U) 3565 #define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ 3566 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ 3567 #define RCC_IOPRSTR_IOPBRST_Pos (1U) 3568 #define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ 3569 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ 3570 #define RCC_IOPRSTR_IOPCRST_Pos (2U) 3571 #define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ 3572 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ 3573 3574 /* Reference defines */ 3575 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ 3576 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */ 3577 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */ 3578 3579 3580 /****************** Bit definition for RCC_AHBRST register ******************/ 3581 #define RCC_AHBRSTR_DMARST_Pos (0U) 3582 #define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ 3583 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ 3584 #define RCC_AHBRSTR_MIFRST_Pos (8U) 3585 #define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ 3586 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */ 3587 #define RCC_AHBRSTR_CRCRST_Pos (12U) 3588 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 3589 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 3590 #define RCC_AHBRSTR_CRYPRST_Pos (24U) 3591 #define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */ 3592 #define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */ 3593 3594 /* Reference defines */ 3595 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ 3596 3597 /***************** Bit definition for RCC_APB2RSTR register *****************/ 3598 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3599 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3600 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 3601 #define RCC_APB2RSTR_TIM21RST_Pos (2U) 3602 #define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ 3603 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */ 3604 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3605 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3606 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */ 3607 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3608 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3609 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 3610 #define RCC_APB2RSTR_DBGRST_Pos (22U) 3611 #define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ 3612 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */ 3613 3614 /* Reference defines */ 3615 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */ 3616 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */ 3617 3618 /***************** Bit definition for RCC_APB1RSTR register *****************/ 3619 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 3620 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 3621 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 3622 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3623 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3624 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 3625 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3626 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3627 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 3628 #define RCC_APB1RSTR_LPUART1RST_Pos (18U) 3629 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ 3630 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ 3631 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3632 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3633 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 3634 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3635 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3636 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 3637 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U) 3638 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ 3639 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */ 3640 3641 /***************** Bit definition for RCC_IOPENR register ******************/ 3642 #define RCC_IOPENR_IOPAEN_Pos (0U) 3643 #define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ 3644 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ 3645 #define RCC_IOPENR_IOPBEN_Pos (1U) 3646 #define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ 3647 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ 3648 #define RCC_IOPENR_IOPCEN_Pos (2U) 3649 #define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ 3650 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ 3651 3652 /* Reference defines */ 3653 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ 3654 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */ 3655 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */ 3656 3657 /***************** Bit definition for RCC_AHBENR register ******************/ 3658 #define RCC_AHBENR_DMAEN_Pos (0U) 3659 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3660 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3661 #define RCC_AHBENR_MIFEN_Pos (8U) 3662 #define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ 3663 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ 3664 #define RCC_AHBENR_CRCEN_Pos (12U) 3665 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 3666 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3667 #define RCC_AHBENR_CRYPEN_Pos (24U) 3668 #define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */ 3669 #define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/ 3670 3671 /* Reference defines */ 3672 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3673 3674 /***************** Bit definition for RCC_APB2ENR register ******************/ 3675 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 3676 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 3677 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ 3678 #define RCC_APB2ENR_TIM21EN_Pos (2U) 3679 #define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ 3680 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ 3681 #define RCC_APB2ENR_FWEN_Pos (7U) 3682 #define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ 3683 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ 3684 #define RCC_APB2ENR_ADCEN_Pos (9U) 3685 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3686 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3687 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3688 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3689 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3690 #define RCC_APB2ENR_DBGEN_Pos (22U) 3691 #define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ 3692 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ 3693 3694 /* Reference defines */ 3695 3696 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */ 3697 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3698 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ 3699 3700 /***************** Bit definition for RCC_APB1ENR register ******************/ 3701 #define RCC_APB1ENR_TIM2EN_Pos (0U) 3702 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 3703 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 3704 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3705 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3706 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3707 #define RCC_APB1ENR_USART2EN_Pos (17U) 3708 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3709 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3710 #define RCC_APB1ENR_LPUART1EN_Pos (18U) 3711 #define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ 3712 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ 3713 #define RCC_APB1ENR_I2C1EN_Pos (21U) 3714 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 3715 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 3716 #define RCC_APB1ENR_PWREN_Pos (28U) 3717 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 3718 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 3719 #define RCC_APB1ENR_LPTIM1EN_Pos (31U) 3720 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ 3721 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ 3722 3723 /****************** Bit definition for RCC_IOPSMENR register ****************/ 3724 #define RCC_IOPSMENR_IOPASMEN_Pos (0U) 3725 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ 3726 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 3727 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U) 3728 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ 3729 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 3730 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U) 3731 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ 3732 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 3733 3734 /* Reference defines */ 3735 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ 3736 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */ 3737 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */ 3738 3739 /***************** Bit definition for RCC_AHBSMENR register ******************/ 3740 #define RCC_AHBSMENR_DMASMEN_Pos (0U) 3741 #define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ 3742 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ 3743 #define RCC_AHBSMENR_MIFSMEN_Pos (8U) 3744 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ 3745 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ 3746 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U) 3747 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ 3748 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ 3749 #define RCC_AHBSMENR_CRCSMEN_Pos (12U) 3750 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 3751 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ 3752 #define RCC_AHBSMENR_CRYPSMEN_Pos (24U) 3753 #define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */ 3754 #define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */ 3755 3756 /* Reference defines */ 3757 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ 3758 3759 /***************** Bit definition for RCC_APB2SMENR register ******************/ 3760 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) 3761 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 3762 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ 3763 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U) 3764 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ 3765 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ 3766 #define RCC_APB2SMENR_ADCSMEN_Pos (9U) 3767 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ 3768 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ 3769 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 3770 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 3771 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ 3772 #define RCC_APB2SMENR_DBGSMEN_Pos (22U) 3773 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ 3774 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ 3775 3776 /* Reference defines */ 3777 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ 3778 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ 3779 3780 /***************** Bit definition for RCC_APB1SMENR register ******************/ 3781 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U) 3782 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ 3783 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 3784 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U) 3785 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ 3786 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 3787 #define RCC_APB1SMENR_USART2SMEN_Pos (17U) 3788 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ 3789 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ 3790 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) 3791 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ 3792 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ 3793 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U) 3794 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ 3795 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ 3796 #define RCC_APB1SMENR_PWRSMEN_Pos (28U) 3797 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ 3798 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ 3799 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) 3800 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 3801 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ 3802 3803 /*!< USART2 Clock source selection */ 3804 #define RCC_CCIPR_USART2SEL_Pos (2U) 3805 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ 3806 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ 3807 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ 3808 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ 3809 3810 /*!< LPUART1 Clock source selection */ 3811 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 3812 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ 3813 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ 3814 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ 3815 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ 3816 3817 /*!< I2C1 Clock source selection */ 3818 #define RCC_CCIPR_I2C1SEL_Pos (12U) 3819 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 3820 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ 3821 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 3822 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 3823 3824 3825 /*!< LPTIM1 Clock source selection */ 3826 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 3827 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 3828 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ 3829 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 3830 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 3831 3832 /******************* Bit definition for RCC_CSR register *******************/ 3833 #define RCC_CSR_LSION_Pos (0U) 3834 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 3835 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 3836 #define RCC_CSR_LSIRDY_Pos (1U) 3837 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 3838 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 3839 3840 #define RCC_CSR_LSEON_Pos (8U) 3841 #define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 3842 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 3843 #define RCC_CSR_LSERDY_Pos (9U) 3844 #define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 3845 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 3846 #define RCC_CSR_LSEBYP_Pos (10U) 3847 #define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 3848 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 3849 3850 #define RCC_CSR_LSEDRV_Pos (11U) 3851 #define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ 3852 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 3853 #define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ 3854 #define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ 3855 3856 #define RCC_CSR_LSECSSON_Pos (13U) 3857 #define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ 3858 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 3859 #define RCC_CSR_LSECSSD_Pos (14U) 3860 #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ 3861 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 3862 3863 /*!< RTC congiguration */ 3864 #define RCC_CSR_RTCSEL_Pos (16U) 3865 #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 3866 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 3867 #define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 3868 #define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 3869 3870 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3871 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 3872 #define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 3873 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 3874 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 3875 #define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 3876 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 3877 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 3878 #define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 3879 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ 3880 3881 #define RCC_CSR_RTCEN_Pos (18U) 3882 #define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ 3883 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 3884 #define RCC_CSR_RTCRST_Pos (19U) 3885 #define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ 3886 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ 3887 3888 #define RCC_CSR_RMVF_Pos (23U) 3889 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 3890 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 3891 #define RCC_CSR_OBLRSTF_Pos (25U) 3892 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 3893 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 3894 #define RCC_CSR_PINRSTF_Pos (26U) 3895 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 3896 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 3897 #define RCC_CSR_PORRSTF_Pos (27U) 3898 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 3899 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 3900 #define RCC_CSR_SFTRSTF_Pos (28U) 3901 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 3902 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 3903 #define RCC_CSR_IWDGRSTF_Pos (29U) 3904 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 3905 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 3906 #define RCC_CSR_WWDGRSTF_Pos (30U) 3907 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 3908 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 3909 #define RCC_CSR_LPWRRSTF_Pos (31U) 3910 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 3911 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 3912 3913 /* Reference defines */ 3914 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 3915 3916 3917 /******************************************************************************/ 3918 /* */ 3919 /* Real-Time Clock (RTC) */ 3920 /* */ 3921 /******************************************************************************/ 3922 /* 3923 * @brief Specific device feature definitions 3924 */ 3925 #define RTC_TAMPER2_SUPPORT 3926 #define RTC_TAMPER3_SUPPORT 3927 #define RTC_WAKEUP_SUPPORT 3928 #define RTC_BACKUP_SUPPORT 3929 3930 /******************** Bits definition for RTC_TR register *******************/ 3931 #define RTC_TR_PM_Pos (22U) 3932 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 3933 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */ 3934 #define RTC_TR_HT_Pos (20U) 3935 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 3936 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */ 3937 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 3938 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 3939 #define RTC_TR_HU_Pos (16U) 3940 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 3941 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */ 3942 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 3943 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 3944 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 3945 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 3946 #define RTC_TR_MNT_Pos (12U) 3947 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 3948 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ 3949 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 3950 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 3951 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 3952 #define RTC_TR_MNU_Pos (8U) 3953 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 3954 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ 3955 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 3956 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 3957 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 3958 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 3959 #define RTC_TR_ST_Pos (4U) 3960 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 3961 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */ 3962 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 3963 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 3964 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 3965 #define RTC_TR_SU_Pos (0U) 3966 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 3967 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */ 3968 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 3969 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 3970 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 3971 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 3972 3973 /******************** Bits definition for RTC_DR register *******************/ 3974 #define RTC_DR_YT_Pos (20U) 3975 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 3976 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */ 3977 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 3978 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 3979 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 3980 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 3981 #define RTC_DR_YU_Pos (16U) 3982 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 3983 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */ 3984 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 3985 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 3986 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 3987 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 3988 #define RTC_DR_WDU_Pos (13U) 3989 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 3990 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ 3991 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 3992 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 3993 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 3994 #define RTC_DR_MT_Pos (12U) 3995 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 3996 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */ 3997 #define RTC_DR_MU_Pos (8U) 3998 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 3999 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */ 4000 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4001 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4002 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4003 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4004 #define RTC_DR_DT_Pos (4U) 4005 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4006 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */ 4007 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4008 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4009 #define RTC_DR_DU_Pos (0U) 4010 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4011 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */ 4012 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4013 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4014 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4015 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4016 4017 /******************** Bits definition for RTC_CR register *******************/ 4018 #define RTC_CR_COE_Pos (23U) 4019 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4020 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */ 4021 #define RTC_CR_OSEL_Pos (21U) 4022 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4023 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ 4024 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4025 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4026 #define RTC_CR_POL_Pos (20U) 4027 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4028 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */ 4029 #define RTC_CR_COSEL_Pos (19U) 4030 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4031 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ 4032 #define RTC_CR_BKP_Pos (18U) 4033 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4034 #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */ 4035 #define RTC_CR_SUB1H_Pos (17U) 4036 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4037 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ 4038 #define RTC_CR_ADD1H_Pos (16U) 4039 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4040 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ 4041 #define RTC_CR_TSIE_Pos (15U) 4042 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4043 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ 4044 #define RTC_CR_WUTIE_Pos (14U) 4045 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 4046 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ 4047 #define RTC_CR_ALRBIE_Pos (13U) 4048 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 4049 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ 4050 #define RTC_CR_ALRAIE_Pos (12U) 4051 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4052 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ 4053 #define RTC_CR_TSE_Pos (11U) 4054 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4055 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ 4056 #define RTC_CR_WUTE_Pos (10U) 4057 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 4058 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ 4059 #define RTC_CR_ALRBE_Pos (9U) 4060 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 4061 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ 4062 #define RTC_CR_ALRAE_Pos (8U) 4063 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4064 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ 4065 #define RTC_CR_FMT_Pos (6U) 4066 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4067 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ 4068 #define RTC_CR_BYPSHAD_Pos (5U) 4069 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4070 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ 4071 #define RTC_CR_REFCKON_Pos (4U) 4072 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4073 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ 4074 #define RTC_CR_TSEDGE_Pos (3U) 4075 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4076 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ 4077 #define RTC_CR_WUCKSEL_Pos (0U) 4078 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 4079 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ 4080 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 4081 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 4082 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 4083 4084 /******************** Bits definition for RTC_ISR register ******************/ 4085 #define RTC_ISR_RECALPF_Pos (16U) 4086 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 4087 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ 4088 #define RTC_ISR_TAMP3F_Pos (15U) 4089 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 4090 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ 4091 #define RTC_ISR_TAMP2F_Pos (14U) 4092 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 4093 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ 4094 #define RTC_ISR_TSOVF_Pos (12U) 4095 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 4096 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ 4097 #define RTC_ISR_TSF_Pos (11U) 4098 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 4099 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ 4100 #define RTC_ISR_WUTF_Pos (10U) 4101 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 4102 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ 4103 #define RTC_ISR_ALRBF_Pos (9U) 4104 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 4105 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ 4106 #define RTC_ISR_ALRAF_Pos (8U) 4107 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 4108 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ 4109 #define RTC_ISR_INIT_Pos (7U) 4110 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 4111 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ 4112 #define RTC_ISR_INITF_Pos (6U) 4113 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 4114 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ 4115 #define RTC_ISR_RSF_Pos (5U) 4116 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 4117 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ 4118 #define RTC_ISR_INITS_Pos (4U) 4119 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 4120 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ 4121 #define RTC_ISR_SHPF_Pos (3U) 4122 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 4123 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ 4124 #define RTC_ISR_WUTWF_Pos (2U) 4125 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 4126 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ 4127 #define RTC_ISR_ALRBWF_Pos (1U) 4128 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 4129 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ 4130 #define RTC_ISR_ALRAWF_Pos (0U) 4131 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 4132 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ 4133 4134 /******************** Bits definition for RTC_PRER register *****************/ 4135 #define RTC_PRER_PREDIV_A_Pos (16U) 4136 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4137 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ 4138 #define RTC_PRER_PREDIV_S_Pos (0U) 4139 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4140 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ 4141 4142 /******************** Bits definition for RTC_WUTR register *****************/ 4143 #define RTC_WUTR_WUT_Pos (0U) 4144 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 4145 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 4146 4147 /******************** Bits definition for RTC_ALRMAR register ***************/ 4148 #define RTC_ALRMAR_MSK4_Pos (31U) 4149 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4150 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ 4151 #define RTC_ALRMAR_WDSEL_Pos (30U) 4152 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4153 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ 4154 #define RTC_ALRMAR_DT_Pos (28U) 4155 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4156 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ 4157 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4158 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4159 #define RTC_ALRMAR_DU_Pos (24U) 4160 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4161 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ 4162 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4163 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4164 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4165 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4166 #define RTC_ALRMAR_MSK3_Pos (23U) 4167 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4168 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ 4169 #define RTC_ALRMAR_PM_Pos (22U) 4170 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4171 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ 4172 #define RTC_ALRMAR_HT_Pos (20U) 4173 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4174 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ 4175 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4176 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4177 #define RTC_ALRMAR_HU_Pos (16U) 4178 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4179 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ 4180 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4181 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4182 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4183 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4184 #define RTC_ALRMAR_MSK2_Pos (15U) 4185 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4186 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ 4187 #define RTC_ALRMAR_MNT_Pos (12U) 4188 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4189 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ 4190 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4191 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4192 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4193 #define RTC_ALRMAR_MNU_Pos (8U) 4194 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4195 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ 4196 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4197 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4198 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4199 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4200 #define RTC_ALRMAR_MSK1_Pos (7U) 4201 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4202 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ 4203 #define RTC_ALRMAR_ST_Pos (4U) 4204 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4205 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ 4206 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4207 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4208 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4209 #define RTC_ALRMAR_SU_Pos (0U) 4210 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4211 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ 4212 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4213 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4214 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4215 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4216 4217 /******************** Bits definition for RTC_ALRMBR register ***************/ 4218 #define RTC_ALRMBR_MSK4_Pos (31U) 4219 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 4220 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ 4221 #define RTC_ALRMBR_WDSEL_Pos (30U) 4222 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 4223 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ 4224 #define RTC_ALRMBR_DT_Pos (28U) 4225 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 4226 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ 4227 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 4228 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 4229 #define RTC_ALRMBR_DU_Pos (24U) 4230 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 4231 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ 4232 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 4233 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 4234 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 4235 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 4236 #define RTC_ALRMBR_MSK3_Pos (23U) 4237 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 4238 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ 4239 #define RTC_ALRMBR_PM_Pos (22U) 4240 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 4241 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ 4242 #define RTC_ALRMBR_HT_Pos (20U) 4243 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 4244 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ 4245 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 4246 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 4247 #define RTC_ALRMBR_HU_Pos (16U) 4248 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 4249 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ 4250 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 4251 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 4252 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 4253 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 4254 #define RTC_ALRMBR_MSK2_Pos (15U) 4255 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 4256 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ 4257 #define RTC_ALRMBR_MNT_Pos (12U) 4258 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 4259 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ 4260 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 4261 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 4262 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 4263 #define RTC_ALRMBR_MNU_Pos (8U) 4264 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 4265 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ 4266 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 4267 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 4268 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 4269 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 4270 #define RTC_ALRMBR_MSK1_Pos (7U) 4271 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 4272 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ 4273 #define RTC_ALRMBR_ST_Pos (4U) 4274 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 4275 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ 4276 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 4277 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 4278 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 4279 #define RTC_ALRMBR_SU_Pos (0U) 4280 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 4281 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ 4282 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 4283 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 4284 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 4285 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 4286 4287 /******************** Bits definition for RTC_WPR register ******************/ 4288 #define RTC_WPR_KEY_Pos (0U) 4289 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4290 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ 4291 4292 /******************** Bits definition for RTC_SSR register ******************/ 4293 #define RTC_SSR_SS_Pos (0U) 4294 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4295 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ 4296 4297 /******************** Bits definition for RTC_SHIFTR register ***************/ 4298 #define RTC_SHIFTR_SUBFS_Pos (0U) 4299 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4300 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ 4301 #define RTC_SHIFTR_ADD1S_Pos (31U) 4302 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4303 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ 4304 4305 /******************** Bits definition for RTC_TSTR register *****************/ 4306 #define RTC_TSTR_PM_Pos (22U) 4307 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4308 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ 4309 #define RTC_TSTR_HT_Pos (20U) 4310 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4311 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ 4312 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4313 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4314 #define RTC_TSTR_HU_Pos (16U) 4315 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4316 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ 4317 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4318 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4319 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4320 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4321 #define RTC_TSTR_MNT_Pos (12U) 4322 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4323 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ 4324 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4325 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4326 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4327 #define RTC_TSTR_MNU_Pos (8U) 4328 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4329 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ 4330 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4331 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4332 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4333 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4334 #define RTC_TSTR_ST_Pos (4U) 4335 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4336 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ 4337 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4338 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4339 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4340 #define RTC_TSTR_SU_Pos (0U) 4341 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4342 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ 4343 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4344 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4345 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4346 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4347 4348 /******************** Bits definition for RTC_TSDR register *****************/ 4349 #define RTC_TSDR_WDU_Pos (13U) 4350 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4351 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ 4352 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4353 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4354 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4355 #define RTC_TSDR_MT_Pos (12U) 4356 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4357 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ 4358 #define RTC_TSDR_MU_Pos (8U) 4359 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4360 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ 4361 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4362 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4363 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4364 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4365 #define RTC_TSDR_DT_Pos (4U) 4366 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4367 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ 4368 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4369 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4370 #define RTC_TSDR_DU_Pos (0U) 4371 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4372 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ 4373 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4374 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4375 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4376 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4377 4378 /******************** Bits definition for RTC_TSSSR register ****************/ 4379 #define RTC_TSSSR_SS_Pos (0U) 4380 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4381 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 4382 4383 /******************** Bits definition for RTC_CALR register *****************/ 4384 #define RTC_CALR_CALP_Pos (15U) 4385 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4386 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ 4387 #define RTC_CALR_CALW8_Pos (14U) 4388 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4389 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ 4390 #define RTC_CALR_CALW16_Pos (13U) 4391 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4392 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ 4393 #define RTC_CALR_CALM_Pos (0U) 4394 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4395 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ 4396 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4397 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4398 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4399 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4400 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4401 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4402 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4403 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4404 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4405 4406 /* Legacy defines */ 4407 #define RTC_CAL_CALP RTC_CALR_CALP 4408 #define RTC_CAL_CALW8 RTC_CALR_CALW8 4409 #define RTC_CAL_CALW16 RTC_CALR_CALW16 4410 #define RTC_CAL_CALM RTC_CALR_CALM 4411 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0 4412 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1 4413 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2 4414 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3 4415 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4 4416 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5 4417 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6 4418 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7 4419 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 4420 4421 /******************** Bits definition for RTC_TAMPCR register ****************/ 4422 #define RTC_TAMPCR_TAMP3MF_Pos (24U) 4423 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ 4424 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ 4425 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) 4426 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ 4427 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ 4428 #define RTC_TAMPCR_TAMP3IE_Pos (22U) 4429 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ 4430 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ 4431 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 4432 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ 4433 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ 4434 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 4435 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ 4436 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ 4437 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 4438 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ 4439 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ 4440 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 4441 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 4442 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ 4443 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 4444 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 4445 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ 4446 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 4447 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 4448 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 4449 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ 4450 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ 4451 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ 4452 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ 4453 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 4454 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 4455 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ 4456 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 4457 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 4458 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 4459 #define RTC_TAMPCR_TAMPTS_Pos (7U) 4460 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ 4461 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ 4462 #define RTC_TAMPCR_TAMP3TRG_Pos (6U) 4463 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 4464 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ 4465 #define RTC_TAMPCR_TAMP3E_Pos (5U) 4466 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ 4467 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ 4468 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 4469 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 4470 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ 4471 #define RTC_TAMPCR_TAMP2E_Pos (3U) 4472 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ 4473 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ 4474 #define RTC_TAMPCR_TAMPIE_Pos (2U) 4475 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ 4476 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ 4477 4478 /******************** Bits definition for RTC_ALRMASSR register *************/ 4479 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4480 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4481 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4482 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4483 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4484 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4485 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4486 #define RTC_ALRMASSR_SS_Pos (0U) 4487 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4488 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4489 4490 /******************** Bits definition for RTC_ALRMBSSR register *************/ 4491 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 4492 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 4493 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 4494 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 4495 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 4496 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 4497 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 4498 #define RTC_ALRMBSSR_SS_Pos (0U) 4499 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 4500 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 4501 4502 /******************** Bits definition for RTC_OR register ****************/ 4503 #define RTC_OR_OUT_RMP_Pos (1U) 4504 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ 4505 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ 4506 #define RTC_OR_ALARMOUTTYPE_Pos (0U) 4507 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ 4508 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ 4509 4510 /* Legacy defines */ 4511 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP 4512 4513 /******************** Bits definition for RTC_BKP0R register ****************/ 4514 #define RTC_BKP0R_Pos (0U) 4515 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 4516 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */ 4517 4518 /******************** Bits definition for RTC_BKP1R register ****************/ 4519 #define RTC_BKP1R_Pos (0U) 4520 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 4521 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */ 4522 4523 /******************** Bits definition for RTC_BKP2R register ****************/ 4524 #define RTC_BKP2R_Pos (0U) 4525 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 4526 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */ 4527 4528 /******************** Bits definition for RTC_BKP3R register ****************/ 4529 #define RTC_BKP3R_Pos (0U) 4530 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 4531 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */ 4532 4533 /******************** Bits definition for RTC_BKP4R register ****************/ 4534 #define RTC_BKP4R_Pos (0U) 4535 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 4536 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */ 4537 4538 /******************** Number of backup registers ******************************/ 4539 #define RTC_BKP_NUMBER (0x00000005U) /*!< */ 4540 4541 /******************************************************************************/ 4542 /* */ 4543 /* Serial Peripheral Interface (SPI) */ 4544 /* */ 4545 /******************************************************************************/ 4546 4547 /* 4548 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 4549 */ 4550 /* Note: No specific macro feature on this device */ 4551 4552 /******************* Bit definition for SPI_CR1 register ********************/ 4553 #define SPI_CR1_CPHA_Pos (0U) 4554 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4555 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4556 #define SPI_CR1_CPOL_Pos (1U) 4557 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4558 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4559 #define SPI_CR1_MSTR_Pos (2U) 4560 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4561 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4562 #define SPI_CR1_BR_Pos (3U) 4563 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4564 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4565 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4566 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4567 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4568 #define SPI_CR1_SPE_Pos (6U) 4569 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4570 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4571 #define SPI_CR1_LSBFIRST_Pos (7U) 4572 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4573 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4574 #define SPI_CR1_SSI_Pos (8U) 4575 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4576 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4577 #define SPI_CR1_SSM_Pos (9U) 4578 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4579 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4580 #define SPI_CR1_RXONLY_Pos (10U) 4581 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4582 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4583 #define SPI_CR1_DFF_Pos (11U) 4584 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 4585 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 4586 #define SPI_CR1_CRCNEXT_Pos (12U) 4587 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4588 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4589 #define SPI_CR1_CRCEN_Pos (13U) 4590 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4591 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4592 #define SPI_CR1_BIDIOE_Pos (14U) 4593 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4594 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4595 #define SPI_CR1_BIDIMODE_Pos (15U) 4596 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4597 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4598 4599 /******************* Bit definition for SPI_CR2 register ********************/ 4600 #define SPI_CR2_RXDMAEN_Pos (0U) 4601 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4602 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4603 #define SPI_CR2_TXDMAEN_Pos (1U) 4604 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4605 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4606 #define SPI_CR2_SSOE_Pos (2U) 4607 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4608 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4609 #define SPI_CR2_FRF_Pos (4U) 4610 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4611 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4612 #define SPI_CR2_ERRIE_Pos (5U) 4613 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4614 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4615 #define SPI_CR2_RXNEIE_Pos (6U) 4616 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4617 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4618 #define SPI_CR2_TXEIE_Pos (7U) 4619 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4620 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4621 4622 /******************** Bit definition for SPI_SR register ********************/ 4623 #define SPI_SR_RXNE_Pos (0U) 4624 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4625 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4626 #define SPI_SR_TXE_Pos (1U) 4627 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4628 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4629 #define SPI_SR_CHSIDE_Pos (2U) 4630 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4631 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4632 #define SPI_SR_UDR_Pos (3U) 4633 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4634 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 4635 #define SPI_SR_CRCERR_Pos (4U) 4636 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4637 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4638 #define SPI_SR_MODF_Pos (5U) 4639 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4640 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4641 #define SPI_SR_OVR_Pos (6U) 4642 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4643 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 4644 #define SPI_SR_BSY_Pos (7U) 4645 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 4646 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 4647 #define SPI_SR_FRE_Pos (8U) 4648 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 4649 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 4650 4651 /******************** Bit definition for SPI_DR register ********************/ 4652 #define SPI_DR_DR_Pos (0U) 4653 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 4654 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 4655 4656 /******************* Bit definition for SPI_CRCPR register ******************/ 4657 #define SPI_CRCPR_CRCPOLY_Pos (0U) 4658 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 4659 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 4660 4661 /****************** Bit definition for SPI_RXCRCR register ******************/ 4662 #define SPI_RXCRCR_RXCRC_Pos (0U) 4663 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 4664 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 4665 4666 /****************** Bit definition for SPI_TXCRCR register ******************/ 4667 #define SPI_TXCRCR_TXCRC_Pos (0U) 4668 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 4669 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 4670 4671 /******************************************************************************/ 4672 /* */ 4673 /* System Configuration (SYSCFG) */ 4674 /* */ 4675 /******************************************************************************/ 4676 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 4677 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 4678 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 4679 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 4680 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 4681 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 4682 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U) 4683 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */ 4684 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */ 4685 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */ 4686 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */ 4687 4688 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 4689 #define SYSCFG_CFGR2_FWDISEN_Pos (0U) 4690 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */ 4691 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */ 4692 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U) 4693 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */ 4694 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 4695 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U) 4696 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */ 4697 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 4698 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U) 4699 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */ 4700 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 4701 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U) 4702 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */ 4703 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 4704 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U) 4705 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */ 4706 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 4707 4708 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 4709 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 4710 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 4711 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 4712 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 4713 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 4714 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 4715 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 4716 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 4717 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 4718 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 4719 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 4720 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 4721 4722 /** 4723 * @brief EXTI0 configuration 4724 */ 4725 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 4726 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 4727 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 4728 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 4729 4730 /** 4731 * @brief EXTI1 configuration 4732 */ 4733 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 4734 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 4735 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 4736 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 4737 4738 /** 4739 * @brief EXTI2 configuration 4740 */ 4741 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 4742 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 4743 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 4744 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 4745 4746 /** 4747 * @brief EXTI3 configuration 4748 */ 4749 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 4750 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 4751 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 4752 4753 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 4754 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 4755 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 4756 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 4757 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 4758 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 4759 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 4760 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 4761 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 4762 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 4763 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 4764 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 4765 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 4766 4767 /** 4768 * @brief EXTI4 configuration 4769 */ 4770 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 4771 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 4772 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 4773 4774 /** 4775 * @brief EXTI5 configuration 4776 */ 4777 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 4778 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 4779 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 4780 4781 /** 4782 * @brief EXTI6 configuration 4783 */ 4784 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 4785 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 4786 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 4787 4788 /** 4789 * @brief EXTI7 configuration 4790 */ 4791 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 4792 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 4793 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 4794 4795 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 4796 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 4797 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 4798 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 4799 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 4800 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 4801 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 4802 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 4803 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 4804 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 4805 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 4806 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 4807 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 4808 4809 /** 4810 * @brief EXTI8 configuration 4811 */ 4812 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 4813 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 4814 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 4815 4816 /** 4817 * @brief EXTI9 configuration 4818 */ 4819 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 4820 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 4821 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 4822 4823 /** 4824 * @brief EXTI10 configuration 4825 */ 4826 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 4827 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 4828 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 4829 4830 /** 4831 * @brief EXTI11 configuration 4832 */ 4833 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 4834 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 4835 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 4836 4837 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 4838 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 4839 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 4840 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 4841 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 4842 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 4843 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 4844 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 4845 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 4846 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 4847 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 4848 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 4849 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 4850 4851 /** 4852 * @brief EXTI12 configuration 4853 */ 4854 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 4855 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 4856 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 4857 4858 /** 4859 * @brief EXTI13 configuration 4860 */ 4861 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 4862 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 4863 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 4864 4865 /** 4866 * @brief EXTI14 configuration 4867 */ 4868 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 4869 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 4870 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 4871 4872 /** 4873 * @brief EXTI15 configuration 4874 */ 4875 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 4876 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 4877 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 4878 4879 4880 /***************** Bit definition for SYSCFG_CFGR3 register ****************/ 4881 #define SYSCFG_CFGR3_EN_VREFINT_Pos (0U) 4882 #define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */ 4883 #define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */ 4884 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U) 4885 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */ 4886 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */ 4887 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */ 4888 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */ 4889 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U) 4890 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */ 4891 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */ 4892 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U) 4893 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */ 4894 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */ 4895 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) 4896 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ 4897 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ 4898 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) 4899 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ 4900 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ 4901 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U) 4902 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */ 4903 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */ 4904 4905 /* Legacy defines */ 4906 4907 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT 4908 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC 4909 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP 4910 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 4911 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 4912 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 4913 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF 4914 4915 /******************************************************************************/ 4916 /* */ 4917 /* Timers (TIM)*/ 4918 /* */ 4919 /******************************************************************************/ 4920 /* 4921 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 4922 */ 4923 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */ 4924 4925 /******************* Bit definition for TIM_CR1 register ********************/ 4926 #define TIM_CR1_CEN_Pos (0U) 4927 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4928 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4929 #define TIM_CR1_UDIS_Pos (1U) 4930 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4931 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4932 #define TIM_CR1_URS_Pos (2U) 4933 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4934 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4935 #define TIM_CR1_OPM_Pos (3U) 4936 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4937 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4938 #define TIM_CR1_DIR_Pos (4U) 4939 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4940 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4941 4942 #define TIM_CR1_CMS_Pos (5U) 4943 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4944 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4945 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4946 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4947 4948 #define TIM_CR1_ARPE_Pos (7U) 4949 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4950 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4951 4952 #define TIM_CR1_CKD_Pos (8U) 4953 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4954 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4955 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4956 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4957 4958 /******************* Bit definition for TIM_CR2 register ********************/ 4959 #define TIM_CR2_CCDS_Pos (3U) 4960 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4961 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4962 4963 #define TIM_CR2_MMS_Pos (4U) 4964 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4965 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4966 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4967 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4968 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4969 4970 #define TIM_CR2_TI1S_Pos (7U) 4971 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4972 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4973 4974 /******************* Bit definition for TIM_SMCR register *******************/ 4975 #define TIM_SMCR_SMS_Pos (0U) 4976 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4977 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4978 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4979 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4980 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4981 4982 #define TIM_SMCR_TS_Pos (4U) 4983 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4984 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4985 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4986 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4987 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4988 4989 #define TIM_SMCR_MSM_Pos (7U) 4990 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4991 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4992 4993 #define TIM_SMCR_ETF_Pos (8U) 4994 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4995 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4996 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4997 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4998 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4999 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5000 5001 #define TIM_SMCR_ETPS_Pos (12U) 5002 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5003 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5004 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5005 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5006 5007 #define TIM_SMCR_ECE_Pos (14U) 5008 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5009 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5010 #define TIM_SMCR_ETP_Pos (15U) 5011 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5012 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5013 5014 /******************* Bit definition for TIM_DIER register *******************/ 5015 #define TIM_DIER_UIE_Pos (0U) 5016 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5017 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5018 #define TIM_DIER_CC1IE_Pos (1U) 5019 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5020 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5021 #define TIM_DIER_CC2IE_Pos (2U) 5022 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5023 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5024 #define TIM_DIER_CC3IE_Pos (3U) 5025 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5026 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5027 #define TIM_DIER_CC4IE_Pos (4U) 5028 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5029 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5030 #define TIM_DIER_TIE_Pos (6U) 5031 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5032 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5033 #define TIM_DIER_UDE_Pos (8U) 5034 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5035 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5036 #define TIM_DIER_CC1DE_Pos (9U) 5037 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5038 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5039 #define TIM_DIER_CC2DE_Pos (10U) 5040 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5041 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5042 #define TIM_DIER_CC3DE_Pos (11U) 5043 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5044 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5045 #define TIM_DIER_CC4DE_Pos (12U) 5046 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5047 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5048 #define TIM_DIER_TDE_Pos (14U) 5049 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5050 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5051 5052 /******************** Bit definition for TIM_SR register ********************/ 5053 #define TIM_SR_UIF_Pos (0U) 5054 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5055 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5056 #define TIM_SR_CC1IF_Pos (1U) 5057 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5058 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5059 #define TIM_SR_CC2IF_Pos (2U) 5060 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5061 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5062 #define TIM_SR_CC3IF_Pos (3U) 5063 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5064 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5065 #define TIM_SR_CC4IF_Pos (4U) 5066 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5067 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5068 #define TIM_SR_TIF_Pos (6U) 5069 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5070 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5071 #define TIM_SR_CC1OF_Pos (9U) 5072 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5073 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5074 #define TIM_SR_CC2OF_Pos (10U) 5075 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5076 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5077 #define TIM_SR_CC3OF_Pos (11U) 5078 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5079 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5080 #define TIM_SR_CC4OF_Pos (12U) 5081 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5082 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5083 5084 /******************* Bit definition for TIM_EGR register ********************/ 5085 #define TIM_EGR_UG_Pos (0U) 5086 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5087 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5088 #define TIM_EGR_CC1G_Pos (1U) 5089 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5090 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5091 #define TIM_EGR_CC2G_Pos (2U) 5092 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5093 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5094 #define TIM_EGR_CC3G_Pos (3U) 5095 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5096 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5097 #define TIM_EGR_CC4G_Pos (4U) 5098 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5099 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5100 #define TIM_EGR_TG_Pos (6U) 5101 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5102 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5103 5104 /****************** Bit definition for TIM_CCMR1 register *******************/ 5105 #define TIM_CCMR1_CC1S_Pos (0U) 5106 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5107 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5108 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5109 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5110 5111 #define TIM_CCMR1_OC1FE_Pos (2U) 5112 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5113 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5114 #define TIM_CCMR1_OC1PE_Pos (3U) 5115 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5116 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5117 5118 #define TIM_CCMR1_OC1M_Pos (4U) 5119 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 5120 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5121 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5122 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5123 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5124 5125 #define TIM_CCMR1_OC1CE_Pos (7U) 5126 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5127 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 5128 5129 #define TIM_CCMR1_CC2S_Pos (8U) 5130 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5131 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5132 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5133 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5134 5135 #define TIM_CCMR1_OC2FE_Pos (10U) 5136 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5137 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5138 #define TIM_CCMR1_OC2PE_Pos (11U) 5139 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5140 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5141 5142 #define TIM_CCMR1_OC2M_Pos (12U) 5143 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 5144 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5145 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5146 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5147 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5148 5149 #define TIM_CCMR1_OC2CE_Pos (15U) 5150 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5151 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5152 5153 /*----------------------------------------------------------------------------*/ 5154 5155 #define TIM_CCMR1_IC1PSC_Pos (2U) 5156 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5157 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5158 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5159 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5160 5161 #define TIM_CCMR1_IC1F_Pos (4U) 5162 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5163 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5164 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5165 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5166 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5167 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5168 5169 #define TIM_CCMR1_IC2PSC_Pos (10U) 5170 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5171 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5172 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5173 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5174 5175 #define TIM_CCMR1_IC2F_Pos (12U) 5176 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5177 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5178 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5179 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5180 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5181 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5182 5183 /****************** Bit definition for TIM_CCMR2 register *******************/ 5184 #define TIM_CCMR2_CC3S_Pos (0U) 5185 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5186 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5187 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5188 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5189 5190 #define TIM_CCMR2_OC3FE_Pos (2U) 5191 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5192 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5193 #define TIM_CCMR2_OC3PE_Pos (3U) 5194 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5195 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5196 5197 #define TIM_CCMR2_OC3M_Pos (4U) 5198 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 5199 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5200 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5201 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5202 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5203 5204 #define TIM_CCMR2_OC3CE_Pos (7U) 5205 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5206 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5207 5208 #define TIM_CCMR2_CC4S_Pos (8U) 5209 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5210 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5211 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5212 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5213 5214 #define TIM_CCMR2_OC4FE_Pos (10U) 5215 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5216 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5217 #define TIM_CCMR2_OC4PE_Pos (11U) 5218 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5219 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5220 5221 #define TIM_CCMR2_OC4M_Pos (12U) 5222 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 5223 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5224 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5225 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5226 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5227 5228 #define TIM_CCMR2_OC4CE_Pos (15U) 5229 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5230 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5231 5232 /*----------------------------------------------------------------------------*/ 5233 5234 #define TIM_CCMR2_IC3PSC_Pos (2U) 5235 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 5236 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5237 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 5238 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 5239 5240 #define TIM_CCMR2_IC3F_Pos (4U) 5241 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 5242 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5243 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 5244 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 5245 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 5246 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 5247 5248 #define TIM_CCMR2_IC4PSC_Pos (10U) 5249 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 5250 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5251 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 5252 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 5253 5254 #define TIM_CCMR2_IC4F_Pos (12U) 5255 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 5256 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5257 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 5258 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 5259 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 5260 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 5261 5262 /******************* Bit definition for TIM_CCER register *******************/ 5263 #define TIM_CCER_CC1E_Pos (0U) 5264 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 5265 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 5266 #define TIM_CCER_CC1P_Pos (1U) 5267 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 5268 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 5269 #define TIM_CCER_CC1NP_Pos (3U) 5270 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 5271 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 5272 #define TIM_CCER_CC2E_Pos (4U) 5273 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 5274 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 5275 #define TIM_CCER_CC2P_Pos (5U) 5276 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 5277 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 5278 #define TIM_CCER_CC2NP_Pos (7U) 5279 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 5280 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 5281 #define TIM_CCER_CC3E_Pos (8U) 5282 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 5283 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 5284 #define TIM_CCER_CC3P_Pos (9U) 5285 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 5286 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 5287 #define TIM_CCER_CC3NP_Pos (11U) 5288 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 5289 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 5290 #define TIM_CCER_CC4E_Pos (12U) 5291 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 5292 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 5293 #define TIM_CCER_CC4P_Pos (13U) 5294 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 5295 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 5296 #define TIM_CCER_CC4NP_Pos (15U) 5297 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 5298 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 5299 5300 /******************* Bit definition for TIM_CNT register ********************/ 5301 #define TIM_CNT_CNT_Pos (0U) 5302 #define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 5303 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 5304 5305 /******************* Bit definition for TIM_PSC register ********************/ 5306 #define TIM_PSC_PSC_Pos (0U) 5307 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 5308 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 5309 5310 /******************* Bit definition for TIM_ARR register ********************/ 5311 #define TIM_ARR_ARR_Pos (0U) 5312 #define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 5313 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 5314 5315 /******************* Bit definition for TIM_CCR1 register *******************/ 5316 #define TIM_CCR1_CCR1_Pos (0U) 5317 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 5318 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5319 5320 /******************* Bit definition for TIM_CCR2 register *******************/ 5321 #define TIM_CCR2_CCR2_Pos (0U) 5322 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 5323 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5324 5325 /******************* Bit definition for TIM_CCR3 register *******************/ 5326 #define TIM_CCR3_CCR3_Pos (0U) 5327 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 5328 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5329 5330 /******************* Bit definition for TIM_CCR4 register *******************/ 5331 #define TIM_CCR4_CCR4_Pos (0U) 5332 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 5333 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5334 5335 /******************* Bit definition for TIM_DCR register ********************/ 5336 #define TIM_DCR_DBA_Pos (0U) 5337 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5338 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5339 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5340 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5341 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5342 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5343 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5344 5345 #define TIM_DCR_DBL_Pos (8U) 5346 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5347 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5348 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5349 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5350 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5351 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5352 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5353 5354 /******************* Bit definition for TIM_DMAR register *******************/ 5355 #define TIM_DMAR_DMAB_Pos (0U) 5356 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5357 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5358 5359 /******************* Bit definition for TIM_OR register *********************/ 5360 #define TIM2_OR_ETR_RMP_Pos (0U) 5361 #define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */ 5362 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */ 5363 #define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5364 #define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5365 #define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 5366 #define TIM2_OR_TI4_RMP_Pos (3U) 5367 #define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */ 5368 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */ 5369 #define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */ 5370 #define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */ 5371 5372 #define TIM21_OR_ETR_RMP_Pos (0U) 5373 #define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5374 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */ 5375 #define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5376 #define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5377 #define TIM21_OR_TI1_RMP_Pos (2U) 5378 #define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */ 5379 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */ 5380 #define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5381 #define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */ 5382 #define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */ 5383 #define TIM21_OR_TI2_RMP_Pos (5U) 5384 #define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */ 5385 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */ 5386 5387 5388 /******************************************************************************/ 5389 /* */ 5390 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5391 /* */ 5392 /******************************************************************************/ 5393 5394 /* 5395 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 5396 */ 5397 #define USART_TCBGT_SUPPORT /*!< Transmission completed before guard time interrupt support */ 5398 5399 /****************** Bit definition for USART_CR1 register *******************/ 5400 #define USART_CR1_UE_Pos (0U) 5401 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 5402 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5403 #define USART_CR1_UESM_Pos (1U) 5404 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 5405 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 5406 #define USART_CR1_RE_Pos (2U) 5407 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5408 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5409 #define USART_CR1_TE_Pos (3U) 5410 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5411 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5412 #define USART_CR1_IDLEIE_Pos (4U) 5413 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5414 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5415 #define USART_CR1_RXNEIE_Pos (5U) 5416 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5417 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5418 #define USART_CR1_TCIE_Pos (6U) 5419 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5420 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5421 #define USART_CR1_TXEIE_Pos (7U) 5422 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5423 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 5424 #define USART_CR1_PEIE_Pos (8U) 5425 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5426 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5427 #define USART_CR1_PS_Pos (9U) 5428 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5429 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5430 #define USART_CR1_PCE_Pos (10U) 5431 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5432 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5433 #define USART_CR1_WAKE_Pos (11U) 5434 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5435 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 5436 #define USART_CR1_M_Pos (12U) 5437 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 5438 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 5439 #define USART_CR1_M0_Pos (12U) 5440 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 5441 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 5442 #define USART_CR1_MME_Pos (13U) 5443 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 5444 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 5445 #define USART_CR1_CMIE_Pos (14U) 5446 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 5447 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 5448 #define USART_CR1_OVER8_Pos (15U) 5449 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5450 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 5451 #define USART_CR1_DEDT_Pos (16U) 5452 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 5453 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 5454 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 5455 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 5456 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 5457 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 5458 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 5459 #define USART_CR1_DEAT_Pos (21U) 5460 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 5461 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 5462 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 5463 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 5464 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 5465 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 5466 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 5467 #define USART_CR1_RTOIE_Pos (26U) 5468 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 5469 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 5470 #define USART_CR1_EOBIE_Pos (27U) 5471 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 5472 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 5473 #define USART_CR1_M1_Pos (28U) 5474 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 5475 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 5476 /****************** Bit definition for USART_CR2 register *******************/ 5477 #define USART_CR2_ADDM7_Pos (4U) 5478 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 5479 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 5480 #define USART_CR2_LBDL_Pos (5U) 5481 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 5482 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 5483 #define USART_CR2_LBDIE_Pos (6U) 5484 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 5485 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 5486 #define USART_CR2_LBCL_Pos (8U) 5487 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5488 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5489 #define USART_CR2_CPHA_Pos (9U) 5490 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5491 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5492 #define USART_CR2_CPOL_Pos (10U) 5493 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5494 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5495 #define USART_CR2_CLKEN_Pos (11U) 5496 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5497 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5498 #define USART_CR2_STOP_Pos (12U) 5499 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5500 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5501 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5502 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5503 #define USART_CR2_LINEN_Pos (14U) 5504 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 5505 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 5506 #define USART_CR2_SWAP_Pos (15U) 5507 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 5508 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 5509 #define USART_CR2_RXINV_Pos (16U) 5510 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 5511 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 5512 #define USART_CR2_TXINV_Pos (17U) 5513 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 5514 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 5515 #define USART_CR2_DATAINV_Pos (18U) 5516 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 5517 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 5518 #define USART_CR2_MSBFIRST_Pos (19U) 5519 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 5520 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 5521 #define USART_CR2_ABREN_Pos (20U) 5522 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 5523 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 5524 #define USART_CR2_ABRMODE_Pos (21U) 5525 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 5526 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 5527 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 5528 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 5529 #define USART_CR2_RTOEN_Pos (23U) 5530 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 5531 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 5532 #define USART_CR2_ADD_Pos (24U) 5533 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 5534 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 5535 5536 /****************** Bit definition for USART_CR3 register *******************/ 5537 #define USART_CR3_EIE_Pos (0U) 5538 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 5539 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 5540 #define USART_CR3_IREN_Pos (1U) 5541 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 5542 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 5543 #define USART_CR3_IRLP_Pos (2U) 5544 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 5545 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 5546 #define USART_CR3_HDSEL_Pos (3U) 5547 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 5548 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 5549 #define USART_CR3_NACK_Pos (4U) 5550 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 5551 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 5552 #define USART_CR3_SCEN_Pos (5U) 5553 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 5554 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 5555 #define USART_CR3_DMAR_Pos (6U) 5556 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 5557 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 5558 #define USART_CR3_DMAT_Pos (7U) 5559 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 5560 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 5561 #define USART_CR3_RTSE_Pos (8U) 5562 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 5563 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 5564 #define USART_CR3_CTSE_Pos (9U) 5565 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 5566 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 5567 #define USART_CR3_CTSIE_Pos (10U) 5568 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 5569 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 5570 #define USART_CR3_ONEBIT_Pos (11U) 5571 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 5572 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 5573 #define USART_CR3_OVRDIS_Pos (12U) 5574 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 5575 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 5576 #define USART_CR3_DDRE_Pos (13U) 5577 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 5578 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 5579 #define USART_CR3_DEM_Pos (14U) 5580 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 5581 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 5582 #define USART_CR3_DEP_Pos (15U) 5583 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 5584 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 5585 #define USART_CR3_SCARCNT_Pos (17U) 5586 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 5587 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 5588 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 5589 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 5590 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 5591 #define USART_CR3_WUS_Pos (20U) 5592 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 5593 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 5594 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 5595 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 5596 #define USART_CR3_WUFIE_Pos (22U) 5597 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 5598 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 5599 #define USART_CR3_UCESM_Pos (23U) 5600 #define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */ 5601 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */ 5602 #define USART_CR3_TCBGTIE_Pos (24U) 5603 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 5604 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 5605 5606 /****************** Bit definition for USART_BRR register *******************/ 5607 #define USART_BRR_DIV_FRACTION_Pos (0U) 5608 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 5609 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 5610 #define USART_BRR_DIV_MANTISSA_Pos (4U) 5611 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 5612 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 5613 5614 /****************** Bit definition for USART_GTPR register ******************/ 5615 #define USART_GTPR_PSC_Pos (0U) 5616 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 5617 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 5618 #define USART_GTPR_GT_Pos (8U) 5619 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 5620 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 5621 5622 5623 /******************* Bit definition for USART_RTOR register *****************/ 5624 #define USART_RTOR_RTO_Pos (0U) 5625 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 5626 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 5627 #define USART_RTOR_BLEN_Pos (24U) 5628 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 5629 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 5630 5631 /******************* Bit definition for USART_RQR register ******************/ 5632 #define USART_RQR_ABRRQ_Pos (0U) 5633 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 5634 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 5635 #define USART_RQR_SBKRQ_Pos (1U) 5636 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 5637 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 5638 #define USART_RQR_MMRQ_Pos (2U) 5639 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 5640 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 5641 #define USART_RQR_RXFRQ_Pos (3U) 5642 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 5643 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 5644 #define USART_RQR_TXFRQ_Pos (4U) 5645 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 5646 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 5647 5648 /******************* Bit definition for USART_ISR register ******************/ 5649 #define USART_ISR_PE_Pos (0U) 5650 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 5651 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 5652 #define USART_ISR_FE_Pos (1U) 5653 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 5654 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 5655 #define USART_ISR_NE_Pos (2U) 5656 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 5657 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 5658 #define USART_ISR_ORE_Pos (3U) 5659 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 5660 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 5661 #define USART_ISR_IDLE_Pos (4U) 5662 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 5663 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 5664 #define USART_ISR_RXNE_Pos (5U) 5665 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 5666 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 5667 #define USART_ISR_TC_Pos (6U) 5668 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 5669 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 5670 #define USART_ISR_TXE_Pos (7U) 5671 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 5672 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 5673 #define USART_ISR_LBDF_Pos (8U) 5674 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 5675 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 5676 #define USART_ISR_CTSIF_Pos (9U) 5677 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 5678 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 5679 #define USART_ISR_CTS_Pos (10U) 5680 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 5681 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 5682 #define USART_ISR_RTOF_Pos (11U) 5683 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 5684 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 5685 #define USART_ISR_EOBF_Pos (12U) 5686 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 5687 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 5688 #define USART_ISR_ABRE_Pos (14U) 5689 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 5690 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 5691 #define USART_ISR_ABRF_Pos (15U) 5692 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 5693 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 5694 #define USART_ISR_BUSY_Pos (16U) 5695 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 5696 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 5697 #define USART_ISR_CMF_Pos (17U) 5698 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 5699 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 5700 #define USART_ISR_SBKF_Pos (18U) 5701 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 5702 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 5703 #define USART_ISR_RWU_Pos (19U) 5704 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 5705 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 5706 #define USART_ISR_WUF_Pos (20U) 5707 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 5708 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 5709 #define USART_ISR_TEACK_Pos (21U) 5710 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 5711 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 5712 #define USART_ISR_REACK_Pos (22U) 5713 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 5714 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 5715 #define USART_ISR_TCBGT_Pos (25U) 5716 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 5717 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ 5718 5719 /******************* Bit definition for USART_ICR register ******************/ 5720 #define USART_ICR_PECF_Pos (0U) 5721 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 5722 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 5723 #define USART_ICR_FECF_Pos (1U) 5724 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 5725 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 5726 #define USART_ICR_NCF_Pos (2U) 5727 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 5728 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 5729 #define USART_ICR_ORECF_Pos (3U) 5730 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 5731 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 5732 #define USART_ICR_IDLECF_Pos (4U) 5733 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 5734 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 5735 #define USART_ICR_TCCF_Pos (6U) 5736 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 5737 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 5738 #define USART_ICR_TCBGTCF_Pos (7U) 5739 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 5740 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 5741 #define USART_ICR_LBDCF_Pos (8U) 5742 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 5743 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 5744 #define USART_ICR_CTSCF_Pos (9U) 5745 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 5746 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 5747 #define USART_ICR_RTOCF_Pos (11U) 5748 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 5749 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 5750 #define USART_ICR_EOBCF_Pos (12U) 5751 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 5752 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 5753 #define USART_ICR_CMCF_Pos (17U) 5754 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 5755 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 5756 #define USART_ICR_WUCF_Pos (20U) 5757 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 5758 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 5759 5760 /* Compatibility defines with other series */ 5761 #define USART_ICR_NECF USART_ICR_NCF 5762 5763 /******************* Bit definition for USART_RDR register ******************/ 5764 #define USART_RDR_RDR_Pos (0U) 5765 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 5766 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 5767 5768 /******************* Bit definition for USART_TDR register ******************/ 5769 #define USART_TDR_TDR_Pos (0U) 5770 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 5771 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 5772 5773 /******************************************************************************/ 5774 /* */ 5775 /* Window WATCHDOG (WWDG) */ 5776 /* */ 5777 /******************************************************************************/ 5778 5779 /******************* Bit definition for WWDG_CR register ********************/ 5780 #define WWDG_CR_T_Pos (0U) 5781 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 5782 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 5783 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 5784 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 5785 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 5786 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 5787 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 5788 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 5789 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 5790 5791 /* Legacy defines */ 5792 #define WWDG_CR_T0 WWDG_CR_T_0 5793 #define WWDG_CR_T1 WWDG_CR_T_1 5794 #define WWDG_CR_T2 WWDG_CR_T_2 5795 #define WWDG_CR_T3 WWDG_CR_T_3 5796 #define WWDG_CR_T4 WWDG_CR_T_4 5797 #define WWDG_CR_T5 WWDG_CR_T_5 5798 #define WWDG_CR_T6 WWDG_CR_T_6 5799 5800 #define WWDG_CR_WDGA_Pos (7U) 5801 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 5802 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 5803 5804 /******************* Bit definition for WWDG_CFR register *******************/ 5805 #define WWDG_CFR_W_Pos (0U) 5806 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 5807 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 5808 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 5809 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 5810 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 5811 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 5812 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 5813 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 5814 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 5815 5816 /* Legacy defines */ 5817 #define WWDG_CFR_W0 WWDG_CFR_W_0 5818 #define WWDG_CFR_W1 WWDG_CFR_W_1 5819 #define WWDG_CFR_W2 WWDG_CFR_W_2 5820 #define WWDG_CFR_W3 WWDG_CFR_W_3 5821 #define WWDG_CFR_W4 WWDG_CFR_W_4 5822 #define WWDG_CFR_W5 WWDG_CFR_W_5 5823 #define WWDG_CFR_W6 WWDG_CFR_W_6 5824 5825 #define WWDG_CFR_WDGTB_Pos (7U) 5826 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 5827 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 5828 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 5829 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 5830 5831 /* Legacy defines */ 5832 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 5833 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 5834 5835 #define WWDG_CFR_EWI_Pos (9U) 5836 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 5837 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 5838 5839 /******************* Bit definition for WWDG_SR register ********************/ 5840 #define WWDG_SR_EWIF_Pos (0U) 5841 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 5842 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 5843 5844 /** 5845 * @} 5846 */ 5847 5848 /** 5849 * @} 5850 */ 5851 5852 /** @addtogroup Exported_macros 5853 * @{ 5854 */ 5855 5856 /******************************* ADC Instances ********************************/ 5857 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 5858 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 5859 5860 /******************************* AES Instances ********************************/ 5861 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) 5862 5863 /******************************* COMP Instances *******************************/ 5864 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 5865 ((INSTANCE) == COMP2)) 5866 5867 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 5868 5869 /******************************* CRC Instances ********************************/ 5870 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 5871 5872 /******************************* DMA Instances *********************************/ 5873 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 5874 ((INSTANCE) == DMA1_Channel2) || \ 5875 ((INSTANCE) == DMA1_Channel3) || \ 5876 ((INSTANCE) == DMA1_Channel4) || \ 5877 ((INSTANCE) == DMA1_Channel5)) 5878 5879 /******************************* GPIO Instances *******************************/ 5880 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5881 ((INSTANCE) == GPIOB) || \ 5882 ((INSTANCE) == GPIOC)) 5883 5884 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5885 ((INSTANCE) == GPIOB)) 5886 5887 /******************************** I2C Instances *******************************/ 5888 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 5889 5890 /****************** I2C Instances : wakeup capability from stop modes *********/ 5891 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) 5892 5893 5894 5895 5896 /****************************** RTC Instances *********************************/ 5897 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 5898 5899 /******************************** SMBUS Instances *****************************/ 5900 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 5901 5902 /******************************** SPI Instances *******************************/ 5903 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 5904 5905 /****************** LPTIM Instances : All supported instances *****************/ 5906 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 5907 5908 /************* LPTIM instances supporting the encoder mode feature ************/ 5909 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 5910 5911 /****************** TIM Instances : All supported instances *******************/ 5912 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5913 ((INSTANCE) == TIM21)) 5914 5915 /************* TIM Instances : at least 1 capture/compare channel *************/ 5916 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5917 ((INSTANCE) == TIM21)) 5918 5919 /************ TIM Instances : at least 2 capture/compare channels *************/ 5920 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5921 ((INSTANCE) == TIM21)) 5922 5923 /************ TIM Instances : at least 3 capture/compare channels *************/ 5924 #define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5925 5926 /************ TIM Instances : at least 4 capture/compare channels *************/ 5927 #define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5928 5929 /****************** TIM Instances : DMA requests generation (UDE) *************/ 5930 #define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5931 5932 /************ TIM Instances : DMA requests generation (CCxDE) *****************/ 5933 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5934 5935 /******************** TIM Instances : DMA burst feature ***********************/ 5936 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5937 5938 /******************* TIM Instances : output(s) available **********************/ 5939 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 5940 ((((INSTANCE) == TIM2) && \ 5941 (((CHANNEL) == TIM_CHANNEL_1) || \ 5942 ((CHANNEL) == TIM_CHANNEL_2) || \ 5943 ((CHANNEL) == TIM_CHANNEL_3) || \ 5944 ((CHANNEL) == TIM_CHANNEL_4))) \ 5945 || \ 5946 (((INSTANCE) == TIM21) && \ 5947 (((CHANNEL) == TIM_CHANNEL_1) || \ 5948 ((CHANNEL) == TIM_CHANNEL_2)))) 5949 5950 /****************** TIM Instances : supporting clock division *****************/ 5951 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5952 ((INSTANCE) == TIM21)) 5953 5954 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 5955 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5956 ((INSTANCE) == TIM21)) 5957 5958 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 5959 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5960 ((INSTANCE) == TIM21)) 5961 5962 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 5963 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5964 ((INSTANCE) == TIM21)) 5965 5966 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 5967 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5968 ((INSTANCE) == TIM21)) 5969 5970 /****************** TIM Instances : supporting counting mode selection ********/ 5971 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5972 ((INSTANCE) == TIM21)) 5973 5974 /****************** TIM Instances : supporting encoder interface **************/ 5975 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5976 ((INSTANCE) == TIM21)) 5977 5978 /***************** TIM Instances : external trigger input availabe ************/ 5979 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5980 ((INSTANCE) == TIM21)) 5981 5982 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ 5983 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5984 ((INSTANCE) == TIM21)) 5985 5986 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 5987 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5988 ((INSTANCE) == TIM21)) 5989 5990 /****************** TIM Instances : remapping capability **********************/ 5991 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5992 ((INSTANCE) == TIM21)) 5993 5994 /******************* TIM Instances : output(s) OCXEC register *****************/ 5995 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5996 5997 /******************* TIM Instances : Timer input XOR function *****************/ 5998 #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 5999 6000 /******************** UART Instances : Asynchronous mode **********************/ 6001 #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2) 6002 6003 /******************** USART Instances : Synchronous mode **********************/ 6004 #define IS_USART_INSTANCE(INSTANCE) (1 == 0) 6005 6006 /****************** USART Instances : Auto Baud Rate detection ****************/ 6007 6008 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0) 6009 6010 /****************** UART Instances : Driver Enable *****************/ 6011 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \ 6012 ((INSTANCE) == LPUART1)) 6013 6014 /******************** UART Instances : Half-Duplex mode **********************/ 6015 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \ 6016 ((INSTANCE) == LPUART1)) 6017 6018 /******************** UART Instances : LIN mode **********************/ 6019 #define IS_UART_LIN_INSTANCE(INSTANCE) (1==0) 6020 6021 /******************** UART Instances : Wake-up from Stop mode **********************/ 6022 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 6023 6024 /****************** UART Instances : Hardware Flow control ********************/ 6025 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \ 6026 ((INSTANCE) == LPUART1)) 6027 6028 /********************* UART Instances : Smard card mode ***********************/ 6029 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2) 6030 6031 /*********************** UART Instances : IRDA mode ***************************/ 6032 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2) 6033 6034 /******************** LPUART Instance *****************************************/ 6035 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 6036 6037 /****************************** IWDG Instances ********************************/ 6038 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6039 6040 /****************************** WWDG Instances ********************************/ 6041 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6042 6043 /** 6044 * @} 6045 */ 6046 6047 /******************************************************************************/ 6048 /* For a painless codes migration between the STM32L0xx device product */ 6049 /* lines, the aliases defined below are put in place to overcome the */ 6050 /* differences in the interrupt handlers and IRQn definitions. */ 6051 /* No need to update developed interrupt code when moving across */ 6052 /* product lines within the same STM32L0 Family */ 6053 /******************************************************************************/ 6054 6055 /* Aliases for __IRQn */ 6056 6057 #define RNG_LPUART1_IRQn AES_LPUART1_IRQn 6058 #define LPUART1_IRQn AES_LPUART1_IRQn 6059 #define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn 6060 #define RCC_CRS_IRQn RCC_IRQn 6061 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 6062 #define ADC1_IRQn ADC1_COMP_IRQn 6063 6064 /* Aliases for __IRQHandler */ 6065 #define LPUART1_IRQHandler AES_LPUART1_IRQHandler 6066 #define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6067 #define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6068 #define RCC_CRS_IRQHandler RCC_IRQHandler 6069 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 6070 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 6071 6072 /** 6073 * @} 6074 */ 6075 6076 /** 6077 * @} 6078 */ 6079 6080 #ifdef __cplusplus 6081 } 6082 #endif /* __cplusplus */ 6083 6084 #endif /* __STM32L021xx_H */ 6085 6086 6087 6088 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 6089
