1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright(c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32l0xx_ll_rcc.h"
21 #include "stm32l0xx_ll_utils.h"
22 #include "stm32l0xx_ll_system.h"
23 #include "stm32l0xx_ll_pwr.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 /** @addtogroup UTILS_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44 #define UTILS_MAX_FREQUENCY_SCALE1 (32000000U) /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 (16000000U) /*!< Maximum frequency for system clock at power scale2, in Hz */
46 #define UTILS_MAX_FREQUENCY_SCALE3 (4194304U) /*!< Maximum frequency for system clock at power scale3, in Hz */
47
48 /* Defines used for PLL range */
49 #define UTILS_PLLVCO_OUTPUT_SCALE1 (96000000U) /*!< Frequency max for PLLVCO output at power scale1, in Hz */
50 #define UTILS_PLLVCO_OUTPUT_SCALE2 (48000000U) /*!< Frequency max for PLLVCO output at power scale2, in Hz */
51 #define UTILS_PLLVCO_OUTPUT_SCALE3 (24000000U) /*!< Frequency max for PLLVCO output at power scale3, in Hz */
52
53 /* Defines used for HSE range */
54 #define UTILS_HSE_FREQUENCY_MIN (1000000U) /*!< Frequency min for HSE frequency, in Hz */
55 #define UTILS_HSE_FREQUENCY_MAX (24000000U) /*!< Frequency max for HSE frequency, in Hz */
56
57 /* Defines used for FLASH latency according to HCLK Frequency */
58 #define UTILS_SCALE1_LATENCY1_FREQ (16000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
59 #define UTILS_SCALE2_LATENCY1_FREQ (8000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
60 #define UTILS_SCALE3_LATENCY1_FREQ (2000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
61 /**
62 * @}
63 */
64 /* Private macros ------------------------------------------------------------*/
65 /** @addtogroup UTILS_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
69 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
70 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
71 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
72 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
73 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
74 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
75 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
76 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
77
78 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
79 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
80 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
81 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
82 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
83
84 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
85 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
86 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
87 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
88 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
89
90 #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \
91 || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
92 || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
93 || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
94 || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
95 || ((__VALUE__) == LL_RCC_PLL_MUL_16) \
96 || ((__VALUE__) == LL_RCC_PLL_MUL_24) \
97 || ((__VALUE__) == LL_RCC_PLL_MUL_32) \
98 || ((__VALUE__) == LL_RCC_PLL_MUL_48))
99
100 #define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \
101 ((__VALUE__) == LL_RCC_PLL_DIV_4))
102
103 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \
104 ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \
105 ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3)))
106
107 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
108 ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
109 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)))
110
111 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
112 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
113
114 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
115 /**
116 * @}
117 */
118 /* Private function prototypes -----------------------------------------------*/
119 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
120 * @{
121 */
122 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
123 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
124 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
125 static ErrorStatus UTILS_PLL_IsBusy(void);
126 /**
127 * @}
128 */
129
130 /* Exported functions --------------------------------------------------------*/
131 /** @addtogroup UTILS_LL_Exported_Functions
132 * @{
133 */
134
135 /** @addtogroup UTILS_LL_EF_DELAY
136 * @{
137 */
138
139 /**
140 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
141 * @note When a RTOS is used, it is recommended to avoid changing the Systick
142 * configuration by calling this function, for a delay use rather osDelay RTOS service.
143 * @param HCLKFrequency HCLK frequency in Hz
144 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
145 * @retval None
146 */
LL_Init1msTick(uint32_t HCLKFrequency)147 void LL_Init1msTick(uint32_t HCLKFrequency)
148 {
149 /* Use frequency provided in argument */
150 LL_InitTick(HCLKFrequency, 1000U);
151 }
152
153 /**
154 * @brief This function provides accurate delay (in milliseconds) based
155 * on SysTick counter flag
156 * @note When a RTOS is used, it is recommended to avoid using blocking delay
157 * and use rather osDelay service.
158 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
159 * will configure Systick to 1ms
160 * @param Delay specifies the delay time length, in milliseconds.
161 * @retval None
162 */
LL_mDelay(uint32_t Delay)163 void LL_mDelay(uint32_t Delay)
164 {
165 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
166 /* Add this code to indicate that local variable is not used */
167 ((void)tmp);
168
169 /* Add a period to guaranty minimum wait */
170 if (Delay < LL_MAX_DELAY)
171 {
172 Delay++;
173 }
174
175 while (Delay)
176 {
177 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
178 {
179 Delay--;
180 }
181 }
182 }
183
184 /**
185 * @}
186 */
187
188 /** @addtogroup UTILS_EF_SYSTEM
189 * @brief System Configuration functions
190 *
191 @verbatim
192 ===============================================================================
193 ##### System Configuration functions #####
194 ===============================================================================
195 [..]
196 System, AHB and APB buses clocks configuration
197
198 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz.
199 @endverbatim
200 @internal
201 Depending on the device voltage range, the maximum frequency should be
202 adapted accordingly:
203 (++) +----------------------------------------------------------------+
204 (++) | Wait states | HCLK clock frequency (MHz) |
205 (++) | |------------------------------------------------|
206 (++) | (Latency) | voltage range | voltage range |
207 (++) | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
208 (++) | |----------------|---------------|---------------|
209 (++) | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
210 (++) |-------------- |----------------|---------------|---------------|
211 (++) |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
212 (++) |---------------|----------------|---------------|---------------|
213 (++) |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
214 (++) +----------------------------------------------------------------+
215 @endinternal
216 * @{
217 */
218
219 /**
220 * @brief This function sets directly SystemCoreClock CMSIS variable.
221 * @note Variable can be calculated also through SystemCoreClockUpdate function.
222 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
223 * @retval None
224 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)225 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
226 {
227 /* HCLK clock frequency */
228 SystemCoreClock = HCLKFrequency;
229 }
230
231 /**
232 * @brief Update number of Flash wait states in line with new frequency and current
233 voltage range.
234 * @param Frequency HCLK frequency
235 * @retval An ErrorStatus enumeration value:
236 * - SUCCESS: Latency has been modified
237 * - ERROR: Latency cannot be modified
238 */
LL_SetFlashLatency(uint32_t Frequency)239 ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
240 {
241 uint32_t timeout;
242 uint32_t getlatency;
243 uint32_t latency;
244 ErrorStatus status = SUCCESS;
245
246 /* Frequency cannot be equal to 0 */
247 if ((Frequency == 0U) || (Frequency > UTILS_MAX_FREQUENCY_SCALE1))
248 {
249 status = ERROR;
250 }
251 else
252 {
253 if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
254 {
255 if (Frequency > UTILS_SCALE1_LATENCY1_FREQ)
256 {
257 /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
258 latency = LL_FLASH_LATENCY_1;
259 }
260 else
261 {
262 /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */
263 latency = LL_FLASH_LATENCY_0;
264 }
265 }
266 else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
267 {
268 if (Frequency > UTILS_SCALE2_LATENCY1_FREQ)
269 {
270 /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
271 latency = LL_FLASH_LATENCY_1;
272 }
273 else
274 {
275 /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */
276 latency = LL_FLASH_LATENCY_0;
277 }
278 }
279 else
280 {
281 if (Frequency > UTILS_SCALE3_LATENCY1_FREQ)
282 {
283 /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */
284 latency = LL_FLASH_LATENCY_1;
285 }
286 else
287 {
288 /* else HCLK < 2MHz default LL_FLASH_LATENCY_0 0WS */
289 latency = LL_FLASH_LATENCY_0;
290 }
291 }
292
293 if (status != ERROR)
294 {
295 LL_FLASH_SetLatency(latency);
296
297 /* Check that the new number of wait states is taken into account to access the Flash
298 memory by reading the FLASH_ACR register */
299 timeout = 2;
300 do
301 {
302 /* Wait for Flash latency to be updated */
303 getlatency = LL_FLASH_GetLatency();
304 timeout--;
305 } while ((getlatency != latency) && (timeout > 0));
306
307 if(getlatency != latency)
308 {
309 status = ERROR;
310 }
311 else
312 {
313 status = SUCCESS;
314 }
315 }
316 }
317 return status;
318 }
319
320 /**
321 * @brief This function configures system clock with HSI as clock source of the PLL
322 * @note The application need to ensure that PLL is disabled.
323 * @note Function is based on the following formula:
324 * - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv)
325 * - PLLMul: The application software must set correctly the PLL multiplication factor to ensure
326 * - PLLVCO does not exceed 96 MHz when the product is in range 1,
327 * - PLLVCO does not exceed 48 MHz when the product is in range 2,
328 * - PLLVCO does not exceed 24 MHz when the product is in range 3
329 * @note FLASH latency can be modified through this function.
330 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
331 * the configuration information for the PLL.
332 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
333 * the configuration information for the BUS prescalers.
334 * @retval An ErrorStatus enumeration value:
335 * - SUCCESS: Max frequency configuration done
336 * - ERROR: Max frequency configuration not done
337 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)338 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
339 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
340 {
341 ErrorStatus status = SUCCESS;
342 uint32_t pllfreq = 0U;
343
344 /* Check if one of the PLL is enabled */
345 if (UTILS_PLL_IsBusy() == SUCCESS)
346 {
347 /* Calculate the new PLL output frequency */
348 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
349
350 /* Enable HSI if not enabled */
351 if (LL_RCC_HSI_IsReady() != 1U)
352 {
353 LL_RCC_HSI_Enable();
354 while (LL_RCC_HSI_IsReady() != 1U)
355 {
356 /* Wait for HSI ready */
357 }
358 }
359
360 /* Configure PLL */
361 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
362
363 /* Enable PLL and switch system clock to PLL */
364 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
365 }
366 else
367 {
368 /* Current PLL configuration cannot be modified */
369 status = ERROR;
370 }
371
372 return status;
373 }
374
375 /**
376 * @brief This function configures system clock with HSE as clock source of the PLL
377 * @note The application need to ensure that PLL is disabled.
378 * @note Function is based on the following formula:
379 * - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv)
380 * - PLLMul: The application software must set correctly the PLL multiplication factor to to ensure
381 * - PLLVCO does not exceed 96 MHz when the product is in range 1,
382 * - PLLVCO does not exceed 48 MHz when the product is in range 2,
383 * - PLLVCO does not exceed 24 MHz when the product is in range 3
384 * @note FLASH latency can be modified through this function.
385 * @param HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000
386 * @param HSEBypass This parameter can be one of the following values:
387 * @arg @ref LL_UTILS_HSEBYPASS_ON
388 * @arg @ref LL_UTILS_HSEBYPASS_OFF
389 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
390 * the configuration information for the PLL.
391 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
392 * the configuration information for the BUS prescalers.
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: Max frequency configuration done
395 * - ERROR: Max frequency configuration not done
396 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)397 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
398 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
399 {
400 ErrorStatus status = SUCCESS;
401 uint32_t pllfreq = 0U;
402
403 /* Check the parameters */
404 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
405 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
406
407 /* Check if one of the PLL is enabled */
408 if (UTILS_PLL_IsBusy() == SUCCESS)
409 {
410 /* Calculate the new PLL output frequency */
411 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
412
413 /* Enable HSE if not enabled */
414 if (LL_RCC_HSE_IsReady() != 1U)
415 {
416 /* Check if need to enable HSE bypass feature or not */
417 if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
418 {
419 LL_RCC_HSE_EnableBypass();
420 }
421 else
422 {
423 LL_RCC_HSE_DisableBypass();
424 }
425
426 /* Enable HSE */
427 LL_RCC_HSE_Enable();
428 while (LL_RCC_HSE_IsReady() != 1U)
429 {
430 /* Wait for HSE ready */
431 }
432 }
433
434 /* Configure PLL */
435 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
436
437 /* Enable PLL and switch system clock to PLL */
438 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
439 }
440 else
441 {
442 /* Current PLL configuration cannot be modified */
443 status = ERROR;
444 }
445
446 return status;
447 }
448
449 /**
450 * @}
451 */
452
453 /**
454 * @}
455 */
456
457 /** @addtogroup UTILS_LL_Private_Functions
458 * @{
459 */
460 /**
461 * @brief Function to check that PLL can be modified
462 * @param PLL_InputFrequency PLL input frequency (in Hz)
463 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
464 * the configuration information for the PLL.
465 * @retval PLL output frequency (in Hz)
466 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)467 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
468 {
469 uint32_t pllfreq = 0U;
470
471 /* Check the parameters */
472 assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
473 assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
474
475 /* Check different PLL parameters according to RM */
476 /* The application software must set correctly the PLL multiplication factor to avoid exceeding
477 96 MHz as PLLVCO when the product is in range 1,
478 48 MHz as PLLVCO when the product is in range 2,
479 24 MHz when the product is in range 3. */
480 pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_CFGR_PLLMUL_Pos]);
481 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
482
483 /* The application software must set correctly the PLL multiplication factor to avoid exceeding
484 maximum frequency 32000000 in range 1 */
485 pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U);
486 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
487
488 return pllfreq;
489 }
490
491 /**
492 * @brief Function to check that PLL can be modified
493 * @retval An ErrorStatus enumeration value:
494 * - SUCCESS: PLL modification can be done
495 * - ERROR: PLL is busy
496 */
UTILS_PLL_IsBusy(void)497 static ErrorStatus UTILS_PLL_IsBusy(void)
498 {
499 ErrorStatus status = SUCCESS;
500
501 /* Check if PLL is busy*/
502 if (LL_RCC_PLL_IsReady() != 0U)
503 {
504 /* PLL configuration cannot be modified */
505 status = ERROR;
506 }
507
508
509 return status;
510 }
511
512 /**
513 * @brief Function to enable PLL and switch system clock to PLL
514 * @param SYSCLK_Frequency SYSCLK frequency
515 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
516 * the configuration information for the BUS prescalers.
517 * @retval An ErrorStatus enumeration value:
518 * - SUCCESS: No problem to switch system to PLL
519 * - ERROR: Problem to switch system to PLL
520 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)521 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
522 {
523 ErrorStatus status = SUCCESS;
524 uint32_t hclk_frequency = 0U;
525
526 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
527 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
528 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
529
530 /* Calculate HCLK frequency */
531 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
532
533 /* Increasing the number of wait states because of higher CPU frequency */
534 if (SystemCoreClock < hclk_frequency)
535 {
536 /* Set FLASH latency to highest latency */
537 status = LL_SetFlashLatency(hclk_frequency);
538 }
539
540 /* Update system clock configuration */
541 if (status == SUCCESS)
542 {
543 /* Enable PLL */
544 LL_RCC_PLL_Enable();
545 while (LL_RCC_PLL_IsReady() != 1U)
546 {
547 /* Wait for PLL ready */
548 }
549
550 /* Sysclk activation on the main PLL */
551 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
552 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
553 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
554 {
555 /* Wait for system clock switch to PLL */
556 }
557
558 /* Set APB1 & APB2 prescaler*/
559 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
560 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
561 }
562
563 /* Decreasing the number of wait states because of lower CPU frequency */
564 if (SystemCoreClock > hclk_frequency)
565 {
566 /* Set FLASH latency to lowest latency */
567 status = LL_SetFlashLatency(hclk_frequency);
568 }
569
570 /* Update SystemCoreClock variable */
571 if (status == SUCCESS)
572 {
573 LL_SetSystemCoreClock(hclk_frequency);
574 }
575
576 return status;
577 }
578
579 /**
580 * @}
581 */
582
583 /**
584 * @}
585 */
586
587 /**
588 * @}
589 */
590
591 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
592
