1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L0xx_LL_LPUART_H
22 #define STM32L0xx_LL_LPUART_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx.h"
30
31 /** @addtogroup STM32L0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (LPUART1)
36
37 /** @defgroup LPUART_LL LPUART
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
46 * @{
47 */
48 /* Defines used in Baud Rate related macros and corresponding register setting computation */
49 #define LPUART_LPUARTDIV_FREQ_MUL 256U
50 #define LPUART_BRR_MASK 0x000FFFFFU
51 #define LPUART_BRR_MIN_VALUE 0x00000300U
52 /**
53 * @}
54 */
55
56
57 /* Private macros ------------------------------------------------------------*/
58 #if defined(USE_FULL_LL_DRIVER)
59 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
60 * @{
61 */
62 /**
63 * @}
64 */
65 #endif /*USE_FULL_LL_DRIVER*/
66
67 /* Exported types ------------------------------------------------------------*/
68 #if defined(USE_FULL_LL_DRIVER)
69 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
70 * @{
71 */
72
73 /**
74 * @brief LL LPUART Init Structure definition
75 */
76 typedef struct
77 {
78 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
79
80 This feature can be modified afterwards using unitary
81 function @ref LL_LPUART_SetBaudRate().*/
82
83 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
84 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
85
86 This feature can be modified afterwards using unitary
87 function @ref LL_LPUART_SetDataWidth().*/
88
89 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
90 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
91
92 This feature can be modified afterwards using unitary
93 function @ref LL_LPUART_SetStopBitsLength().*/
94
95 uint32_t Parity; /*!< Specifies the parity mode.
96 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
97
98 This feature can be modified afterwards using unitary
99 function @ref LL_LPUART_SetParity().*/
100
101 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
102 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
103
104 This feature can be modified afterwards using unitary
105 function @ref LL_LPUART_SetTransferDirection().*/
106
107 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
108 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
109
110 This feature can be modified afterwards using unitary
111 function @ref LL_LPUART_SetHWFlowCtrl().*/
112
113 } LL_LPUART_InitTypeDef;
114
115 /**
116 * @}
117 */
118 #endif /* USE_FULL_LL_DRIVER */
119
120 /* Exported constants --------------------------------------------------------*/
121 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
122 * @{
123 */
124
125 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
126 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
127 * @{
128 */
129 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
130 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
131 #define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise error detected clear flag */
132 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
133 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
134 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
135 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
136 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
137 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
138 /**
139 * @}
140 */
141
142 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
143 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
144 * @{
145 */
146 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
147 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
148 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
149 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
150 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
151 #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
152 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
153 #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
154 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
155 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
156 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
157 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
158 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
159 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
160 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
161 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
162 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
163 /**
164 * @}
165 */
166
167 /** @defgroup LPUART_LL_EC_IT IT Defines
168 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
169 * @{
170 */
171 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
172 #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
173 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
174 #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
175 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
176 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
177 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
178 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
179 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
180 /**
181 * @}
182 */
183
184 /** @defgroup LPUART_LL_EC_DIRECTION Direction
185 * @{
186 */
187 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
188 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
189 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
190 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
191 /**
192 * @}
193 */
194
195 /** @defgroup LPUART_LL_EC_PARITY Parity Control
196 * @{
197 */
198 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
199 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
200 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
201 /**
202 * @}
203 */
204
205 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
206 * @{
207 */
208 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
209 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
210 /**
211 * @}
212 */
213
214 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
215 * @{
216 */
217 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
218 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
219 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
220 /**
221 * @}
222 */
223
224 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
225 * @{
226 */
227 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
228 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
229 /**
230 * @}
231 */
232
233 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
234 * @{
235 */
236 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
237 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
238 /**
239 * @}
240 */
241
242 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
243 * @{
244 */
245 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
246 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
247 /**
248 * @}
249 */
250
251 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
252 * @{
253 */
254 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
255 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
256 /**
257 * @}
258 */
259
260 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
261 * @{
262 */
263 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
264 in positive/direct logic. (1=H, 0=L) */
265 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
266 in negative/inverse logic. (1=L, 0=H).
267 The parity bit is also inverted. */
268 /**
269 * @}
270 */
271
272 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
273 * @{
274 */
275 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
276 following the start bit */
277 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
278 following the start bit */
279 /**
280 * @}
281 */
282
283 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
284 * @{
285 */
286 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
287 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
288 /**
289 * @}
290 */
291
292 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
293 * @{
294 */
295 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
296 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
297 when there is space in the receive buffer */
298 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
299 when the nCTS input is asserted (tied to 0)*/
300 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
301 /**
302 * @}
303 */
304
305 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
306 * @{
307 */
308 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
309 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
310 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
311 /**
312 * @}
313 */
314
315 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
316 * @{
317 */
318 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
319 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
320 /**
321 * @}
322 */
323
324 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
325 * @{
326 */
327 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
328 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /* Exported macro ------------------------------------------------------------*/
338 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
339 * @{
340 */
341
342 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
343 * @{
344 */
345
346 /**
347 * @brief Write a value in LPUART register
348 * @param __INSTANCE__ LPUART Instance
349 * @param __REG__ Register to be written
350 * @param __VALUE__ Value to be written in the register
351 * @retval None
352 */
353 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
354
355 /**
356 * @brief Read a value in LPUART register
357 * @param __INSTANCE__ LPUART Instance
358 * @param __REG__ Register to be read
359 * @retval Register value
360 */
361 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
362 /**
363 * @}
364 */
365
366 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
367 * @{
368 */
369
370 /**
371 * @brief Compute LPUARTDIV value according to Peripheral Clock and
372 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
373 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
374 * @param __BAUDRATE__ Baud Rate value to achieve
375 * @retval LPUARTDIV value to be used for BRR register filling
376 */
377 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\
378 & LPUART_BRR_MASK)
379
380 /**
381 * @}
382 */
383
384 /**
385 * @}
386 */
387
388 /* Exported functions --------------------------------------------------------*/
389 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
390 * @{
391 */
392
393 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
394 * @{
395 */
396
397 /**
398 * @brief LPUART Enable
399 * @rmtoll CR1 UE LL_LPUART_Enable
400 * @param LPUARTx LPUART Instance
401 * @retval None
402 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)403 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
404 {
405 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
406 }
407
408 /**
409 * @brief LPUART Disable
410 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
411 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
412 * flags, in the LPUARTx_ISR are set to their default values.
413 * @note In order to go into low-power mode without generating errors on the line,
414 * the TE bit must be reset before and the software must wait
415 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
416 * The DMA requests are also reset when UE = 0 so the DMA channel must
417 * be disabled before resetting the UE bit.
418 * @rmtoll CR1 UE LL_LPUART_Disable
419 * @param LPUARTx LPUART Instance
420 * @retval None
421 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)422 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
423 {
424 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
425 }
426
427 /**
428 * @brief Indicate if LPUART is enabled
429 * @rmtoll CR1 UE LL_LPUART_IsEnabled
430 * @param LPUARTx LPUART Instance
431 * @retval State of bit (1 or 0).
432 */
LL_LPUART_IsEnabled(USART_TypeDef * LPUARTx)433 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
434 {
435 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
436 }
437
438
439 /**
440 * @brief LPUART enabled in STOP Mode
441 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
442 * LPUART clock selection is HSI or LSE in RCC.
443 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
444 * @param LPUARTx LPUART Instance
445 * @retval None
446 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)447 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
448 {
449 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
450 }
451
452 /**
453 * @brief LPUART disabled in STOP Mode
454 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
455 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
456 * @param LPUARTx LPUART Instance
457 * @retval None
458 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)459 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
460 {
461 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
462 }
463
464 /**
465 * @brief Indicate if LPUART is enabled in STOP Mode
466 * (able to wake up MCU from Stop mode or not)
467 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
468 * @param LPUARTx LPUART Instance
469 * @retval State of bit (1 or 0).
470 */
LL_LPUART_IsEnabledInStopMode(USART_TypeDef * LPUARTx)471 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
472 {
473 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
474 }
475
476 /**
477 * @brief LPUART Clock enabled in STOP Mode
478 * @note When this function is called, LPUART Clock is enabled while in STOP mode
479 * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode
480 * @param LPUARTx LPUART Instance
481 * @retval None
482 */
LL_LPUART_EnableClockInStopMode(USART_TypeDef * LPUARTx)483 __STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
484 {
485 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
486 }
487
488 /**
489 * @brief LPUART clock disabled in STOP Mode
490 * @note When this function is called, LPUART Clock is disabled while in STOP mode
491 * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode
492 * @param LPUARTx LPUART Instance
493 * @retval None
494 */
LL_LPUART_DisableClockInStopMode(USART_TypeDef * LPUARTx)495 __STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
496 {
497 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
498 }
499
500 /**
501 * @brief Indicate if LPUART clock is enabled in STOP Mode
502 * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode
503 * @param LPUARTx LPUART Instance
504 * @retval State of bit (1 or 0).
505 */
LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef * LPUARTx)506 __STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx)
507 {
508 return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL);
509 }
510
511 /**
512 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
513 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
514 * @param LPUARTx LPUART Instance
515 * @retval None
516 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)517 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
518 {
519 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
520 }
521
522 /**
523 * @brief Receiver Disable
524 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
525 * @param LPUARTx LPUART Instance
526 * @retval None
527 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)528 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
529 {
530 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
531 }
532
533 /**
534 * @brief Transmitter Enable
535 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
536 * @param LPUARTx LPUART Instance
537 * @retval None
538 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)539 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
540 {
541 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
542 }
543
544 /**
545 * @brief Transmitter Disable
546 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
547 * @param LPUARTx LPUART Instance
548 * @retval None
549 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)550 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
551 {
552 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
553 }
554
555 /**
556 * @brief Configure simultaneously enabled/disabled states
557 * of Transmitter and Receiver
558 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
559 * CR1 TE LL_LPUART_SetTransferDirection
560 * @param LPUARTx LPUART Instance
561 * @param TransferDirection This parameter can be one of the following values:
562 * @arg @ref LL_LPUART_DIRECTION_NONE
563 * @arg @ref LL_LPUART_DIRECTION_RX
564 * @arg @ref LL_LPUART_DIRECTION_TX
565 * @arg @ref LL_LPUART_DIRECTION_TX_RX
566 * @retval None
567 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)568 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
569 {
570 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
571 }
572
573 /**
574 * @brief Return enabled/disabled states of Transmitter and Receiver
575 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
576 * CR1 TE LL_LPUART_GetTransferDirection
577 * @param LPUARTx LPUART Instance
578 * @retval Returned value can be one of the following values:
579 * @arg @ref LL_LPUART_DIRECTION_NONE
580 * @arg @ref LL_LPUART_DIRECTION_RX
581 * @arg @ref LL_LPUART_DIRECTION_TX
582 * @arg @ref LL_LPUART_DIRECTION_TX_RX
583 */
LL_LPUART_GetTransferDirection(USART_TypeDef * LPUARTx)584 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
585 {
586 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
587 }
588
589 /**
590 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
591 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
592 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
593 * (depending on data width) and parity is checked on the received data.
594 * @rmtoll CR1 PS LL_LPUART_SetParity\n
595 * CR1 PCE LL_LPUART_SetParity
596 * @param LPUARTx LPUART Instance
597 * @param Parity This parameter can be one of the following values:
598 * @arg @ref LL_LPUART_PARITY_NONE
599 * @arg @ref LL_LPUART_PARITY_EVEN
600 * @arg @ref LL_LPUART_PARITY_ODD
601 * @retval None
602 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)603 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
604 {
605 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
606 }
607
608 /**
609 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
610 * @rmtoll CR1 PS LL_LPUART_GetParity\n
611 * CR1 PCE LL_LPUART_GetParity
612 * @param LPUARTx LPUART Instance
613 * @retval Returned value can be one of the following values:
614 * @arg @ref LL_LPUART_PARITY_NONE
615 * @arg @ref LL_LPUART_PARITY_EVEN
616 * @arg @ref LL_LPUART_PARITY_ODD
617 */
LL_LPUART_GetParity(USART_TypeDef * LPUARTx)618 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
619 {
620 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
621 }
622
623 /**
624 * @brief Set Receiver Wake Up method from Mute mode.
625 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
626 * @param LPUARTx LPUART Instance
627 * @param Method This parameter can be one of the following values:
628 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
629 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
630 * @retval None
631 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)632 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
633 {
634 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
635 }
636
637 /**
638 * @brief Return Receiver Wake Up method from Mute mode
639 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
640 * @param LPUARTx LPUART Instance
641 * @retval Returned value can be one of the following values:
642 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
643 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
644 */
LL_LPUART_GetWakeUpMethod(USART_TypeDef * LPUARTx)645 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
646 {
647 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
648 }
649
650 /**
651 * @brief Set Word length (nb of data bits, excluding start and stop bits)
652 * @rmtoll CR1 M LL_LPUART_SetDataWidth
653 * @param LPUARTx LPUART Instance
654 * @param DataWidth This parameter can be one of the following values:
655 * @arg @ref LL_LPUART_DATAWIDTH_7B
656 * @arg @ref LL_LPUART_DATAWIDTH_8B
657 * @arg @ref LL_LPUART_DATAWIDTH_9B
658 * @retval None
659 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)660 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
661 {
662 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
663 }
664
665 /**
666 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
667 * @rmtoll CR1 M LL_LPUART_GetDataWidth
668 * @param LPUARTx LPUART Instance
669 * @retval Returned value can be one of the following values:
670 * @arg @ref LL_LPUART_DATAWIDTH_7B
671 * @arg @ref LL_LPUART_DATAWIDTH_8B
672 * @arg @ref LL_LPUART_DATAWIDTH_9B
673 */
LL_LPUART_GetDataWidth(USART_TypeDef * LPUARTx)674 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
675 {
676 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
677 }
678
679 /**
680 * @brief Allow switch between Mute Mode and Active mode
681 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
682 * @param LPUARTx LPUART Instance
683 * @retval None
684 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)685 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
686 {
687 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
688 }
689
690 /**
691 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
692 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
693 * @param LPUARTx LPUART Instance
694 * @retval None
695 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)696 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
697 {
698 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
699 }
700
701 /**
702 * @brief Indicate if switch between Mute Mode and Active mode is allowed
703 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
704 * @param LPUARTx LPUART Instance
705 * @retval State of bit (1 or 0).
706 */
LL_LPUART_IsEnabledMuteMode(USART_TypeDef * LPUARTx)707 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
708 {
709 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
710 }
711
712
713 /**
714 * @brief Set the length of the stop bits
715 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
716 * @param LPUARTx LPUART Instance
717 * @param StopBits This parameter can be one of the following values:
718 * @arg @ref LL_LPUART_STOPBITS_1
719 * @arg @ref LL_LPUART_STOPBITS_2
720 * @retval None
721 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)722 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
723 {
724 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
725 }
726
727 /**
728 * @brief Retrieve the length of the stop bits
729 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
730 * @param LPUARTx LPUART Instance
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_LPUART_STOPBITS_1
733 * @arg @ref LL_LPUART_STOPBITS_2
734 */
LL_LPUART_GetStopBitsLength(USART_TypeDef * LPUARTx)735 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
736 {
737 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
738 }
739
740 /**
741 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
742 * @note Call of this function is equivalent to following function call sequence :
743 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
744 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
745 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
746 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
747 * CR1 PCE LL_LPUART_ConfigCharacter\n
748 * CR1 M LL_LPUART_ConfigCharacter\n
749 * CR2 STOP LL_LPUART_ConfigCharacter
750 * @param LPUARTx LPUART Instance
751 * @param DataWidth This parameter can be one of the following values:
752 * @arg @ref LL_LPUART_DATAWIDTH_7B
753 * @arg @ref LL_LPUART_DATAWIDTH_8B
754 * @arg @ref LL_LPUART_DATAWIDTH_9B
755 * @param Parity This parameter can be one of the following values:
756 * @arg @ref LL_LPUART_PARITY_NONE
757 * @arg @ref LL_LPUART_PARITY_EVEN
758 * @arg @ref LL_LPUART_PARITY_ODD
759 * @param StopBits This parameter can be one of the following values:
760 * @arg @ref LL_LPUART_STOPBITS_1
761 * @arg @ref LL_LPUART_STOPBITS_2
762 * @retval None
763 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)764 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
765 uint32_t StopBits)
766 {
767 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
768 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
769 }
770
771 /**
772 * @brief Configure TX/RX pins swapping setting.
773 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
774 * @param LPUARTx LPUART Instance
775 * @param SwapConfig This parameter can be one of the following values:
776 * @arg @ref LL_LPUART_TXRX_STANDARD
777 * @arg @ref LL_LPUART_TXRX_SWAPPED
778 * @retval None
779 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)780 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
781 {
782 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
783 }
784
785 /**
786 * @brief Retrieve TX/RX pins swapping configuration.
787 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
788 * @param LPUARTx LPUART Instance
789 * @retval Returned value can be one of the following values:
790 * @arg @ref LL_LPUART_TXRX_STANDARD
791 * @arg @ref LL_LPUART_TXRX_SWAPPED
792 */
LL_LPUART_GetTXRXSwap(USART_TypeDef * LPUARTx)793 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
794 {
795 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
796 }
797
798 /**
799 * @brief Configure RX pin active level logic
800 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
801 * @param LPUARTx LPUART Instance
802 * @param PinInvMethod This parameter can be one of the following values:
803 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
804 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
805 * @retval None
806 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)807 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
808 {
809 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
810 }
811
812 /**
813 * @brief Retrieve RX pin active level logic configuration
814 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
815 * @param LPUARTx LPUART Instance
816 * @retval Returned value can be one of the following values:
817 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
818 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
819 */
LL_LPUART_GetRXPinLevel(USART_TypeDef * LPUARTx)820 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
821 {
822 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
823 }
824
825 /**
826 * @brief Configure TX pin active level logic
827 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
828 * @param LPUARTx LPUART Instance
829 * @param PinInvMethod This parameter can be one of the following values:
830 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
831 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
832 * @retval None
833 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)834 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
835 {
836 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
837 }
838
839 /**
840 * @brief Retrieve TX pin active level logic configuration
841 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
842 * @param LPUARTx LPUART Instance
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
845 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
846 */
LL_LPUART_GetTXPinLevel(USART_TypeDef * LPUARTx)847 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
848 {
849 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
850 }
851
852 /**
853 * @brief Configure Binary data logic.
854 *
855 * @note Allow to define how Logical data from the data register are send/received :
856 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
857 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
858 * @param LPUARTx LPUART Instance
859 * @param DataLogic This parameter can be one of the following values:
860 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
861 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
862 * @retval None
863 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)864 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
865 {
866 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
867 }
868
869 /**
870 * @brief Retrieve Binary data configuration
871 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
872 * @param LPUARTx LPUART Instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
875 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
876 */
LL_LPUART_GetBinaryDataLogic(USART_TypeDef * LPUARTx)877 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
878 {
879 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
880 }
881
882 /**
883 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
884 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
885 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
886 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
887 * @param LPUARTx LPUART Instance
888 * @param BitOrder This parameter can be one of the following values:
889 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
890 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
891 * @retval None
892 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)893 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
894 {
895 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
896 }
897
898 /**
899 * @brief Return transfer bit order (either Less or Most Significant Bit First)
900 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
901 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
902 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
903 * @param LPUARTx LPUART Instance
904 * @retval Returned value can be one of the following values:
905 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
906 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
907 */
LL_LPUART_GetTransferBitOrder(USART_TypeDef * LPUARTx)908 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
909 {
910 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
911 }
912
913 /**
914 * @brief Set Address of the LPUART node.
915 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
916 * for wake up with address mark detection.
917 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
918 * (b7-b4 should be set to 0)
919 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
920 * (This is used in multiprocessor communication during Mute mode or Stop mode,
921 * for wake up with 7-bit address mark detection.
922 * The MSB of the character sent by the transmitter should be equal to 1.
923 * It may also be used for character detection during normal reception,
924 * Mute mode inactive (for example, end of block detection in ModBus protocol).
925 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
926 * value and CMF flag is set on match)
927 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
928 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
929 * @param LPUARTx LPUART Instance
930 * @param AddressLen This parameter can be one of the following values:
931 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
932 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
933 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
934 * @retval None
935 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)936 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
937 {
938 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
939 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
940 }
941
942 /**
943 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
944 * @note If 4-bit Address Detection is selected in ADDM7,
945 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
946 * If 7-bit Address Detection is selected in ADDM7,
947 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
948 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
949 * @param LPUARTx LPUART Instance
950 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
951 */
LL_LPUART_GetNodeAddress(USART_TypeDef * LPUARTx)952 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
953 {
954 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
955 }
956
957 /**
958 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
959 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
960 * @param LPUARTx LPUART Instance
961 * @retval Returned value can be one of the following values:
962 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
963 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
964 */
LL_LPUART_GetNodeAddressLen(USART_TypeDef * LPUARTx)965 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
966 {
967 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
968 }
969
970 /**
971 * @brief Enable RTS HW Flow Control
972 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
973 * @param LPUARTx LPUART Instance
974 * @retval None
975 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)976 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
977 {
978 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
979 }
980
981 /**
982 * @brief Disable RTS HW Flow Control
983 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
984 * @param LPUARTx LPUART Instance
985 * @retval None
986 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)987 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
988 {
989 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
990 }
991
992 /**
993 * @brief Enable CTS HW Flow Control
994 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
995 * @param LPUARTx LPUART Instance
996 * @retval None
997 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)998 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
999 {
1000 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1001 }
1002
1003 /**
1004 * @brief Disable CTS HW Flow Control
1005 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1006 * @param LPUARTx LPUART Instance
1007 * @retval None
1008 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1009 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1010 {
1011 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1012 }
1013
1014 /**
1015 * @brief Configure HW Flow Control mode (both CTS and RTS)
1016 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1017 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1018 * @param LPUARTx LPUART Instance
1019 * @param HardwareFlowControl This parameter can be one of the following values:
1020 * @arg @ref LL_LPUART_HWCONTROL_NONE
1021 * @arg @ref LL_LPUART_HWCONTROL_RTS
1022 * @arg @ref LL_LPUART_HWCONTROL_CTS
1023 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1024 * @retval None
1025 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1026 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1027 {
1028 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1029 }
1030
1031 /**
1032 * @brief Return HW Flow Control configuration (both CTS and RTS)
1033 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1034 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1035 * @param LPUARTx LPUART Instance
1036 * @retval Returned value can be one of the following values:
1037 * @arg @ref LL_LPUART_HWCONTROL_NONE
1038 * @arg @ref LL_LPUART_HWCONTROL_RTS
1039 * @arg @ref LL_LPUART_HWCONTROL_CTS
1040 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1041 */
LL_LPUART_GetHWFlowCtrl(USART_TypeDef * LPUARTx)1042 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
1043 {
1044 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1045 }
1046
1047 /**
1048 * @brief Enable Overrun detection
1049 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1050 * @param LPUARTx LPUART Instance
1051 * @retval None
1052 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1053 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1054 {
1055 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1056 }
1057
1058 /**
1059 * @brief Disable Overrun detection
1060 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1061 * @param LPUARTx LPUART Instance
1062 * @retval None
1063 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1064 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1065 {
1066 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1067 }
1068
1069 /**
1070 * @brief Indicate if Overrun detection is enabled
1071 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1072 * @param LPUARTx LPUART Instance
1073 * @retval State of bit (1 or 0).
1074 */
LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef * LPUARTx)1075 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
1076 {
1077 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1078 }
1079
1080 /**
1081 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1082 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1083 * @param LPUARTx LPUART Instance
1084 * @param Type This parameter can be one of the following values:
1085 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1086 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1087 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1088 * @retval None
1089 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1090 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1091 {
1092 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1093 }
1094
1095 /**
1096 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1097 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1098 * @param LPUARTx LPUART Instance
1099 * @retval Returned value can be one of the following values:
1100 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1101 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1102 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1103 */
LL_LPUART_GetWKUPType(USART_TypeDef * LPUARTx)1104 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
1105 {
1106 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1107 }
1108
1109 /**
1110 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1111 *
1112 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1113 * according to used Peripheral Clock and expected Baud Rate values
1114 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1115 * (Baud rate value != 0).
1116 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1117 * a care should be taken when generating high baud rates using high PeriphClk
1118 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1119 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1120 * @param LPUARTx LPUART Instance
1121 * @param PeriphClk Peripheral Clock
1122 * @param BaudRate Baud Rate
1123 * @retval None
1124 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t BaudRate)1125 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)
1126 {
1127 if (BaudRate != 0U)
1128 {
1129 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
1130 }
1131 }
1132
1133 /**
1134 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1135 * (full BRR content), and to used Peripheral Clock values
1136 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1137 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1138 * @param LPUARTx LPUART Instance
1139 * @param PeriphClk Peripheral Clock
1140 * @retval Baud Rate
1141 */
LL_LPUART_GetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk)1142 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)
1143 {
1144 uint32_t lpuartdiv;
1145 uint32_t brrresult;
1146
1147 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1148
1149 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1150 {
1151 brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1152 }
1153 else
1154 {
1155 brrresult = 0x0UL;
1156 }
1157
1158 return (brrresult);
1159 }
1160
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1166 * @{
1167 */
1168
1169 /**
1170 * @brief Enable Single Wire Half-Duplex mode
1171 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1172 * @param LPUARTx LPUART Instance
1173 * @retval None
1174 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1175 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1176 {
1177 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1178 }
1179
1180 /**
1181 * @brief Disable Single Wire Half-Duplex mode
1182 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1183 * @param LPUARTx LPUART Instance
1184 * @retval None
1185 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1186 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1187 {
1188 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1189 }
1190
1191 /**
1192 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1193 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1194 * @param LPUARTx LPUART Instance
1195 * @retval State of bit (1 or 0).
1196 */
LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef * LPUARTx)1197 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
1198 {
1199 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1200 }
1201
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1207 * @{
1208 */
1209
1210 /**
1211 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1212 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1213 * @param LPUARTx LPUART Instance
1214 * @param Time Value between Min_Data=0 and Max_Data=31
1215 * @retval None
1216 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1217 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1218 {
1219 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1220 }
1221
1222 /**
1223 * @brief Return DEDT (Driver Enable De-Assertion Time)
1224 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1225 * @param LPUARTx LPUART Instance
1226 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1227 */
LL_LPUART_GetDEDeassertionTime(USART_TypeDef * LPUARTx)1228 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
1229 {
1230 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1231 }
1232
1233 /**
1234 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1235 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1236 * @param LPUARTx LPUART Instance
1237 * @param Time Value between Min_Data=0 and Max_Data=31
1238 * @retval None
1239 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1240 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1241 {
1242 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1243 }
1244
1245 /**
1246 * @brief Return DEAT (Driver Enable Assertion Time)
1247 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1248 * @param LPUARTx LPUART Instance
1249 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1250 */
LL_LPUART_GetDEAssertionTime(USART_TypeDef * LPUARTx)1251 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
1252 {
1253 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1254 }
1255
1256 /**
1257 * @brief Enable Driver Enable (DE) Mode
1258 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1259 * @param LPUARTx LPUART Instance
1260 * @retval None
1261 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1262 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1263 {
1264 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1265 }
1266
1267 /**
1268 * @brief Disable Driver Enable (DE) Mode
1269 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1270 * @param LPUARTx LPUART Instance
1271 * @retval None
1272 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1273 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1274 {
1275 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1276 }
1277
1278 /**
1279 * @brief Indicate if Driver Enable (DE) Mode is enabled
1280 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1281 * @param LPUARTx LPUART Instance
1282 * @retval State of bit (1 or 0).
1283 */
LL_LPUART_IsEnabledDEMode(USART_TypeDef * LPUARTx)1284 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
1285 {
1286 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1287 }
1288
1289 /**
1290 * @brief Select Driver Enable Polarity
1291 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1292 * @param LPUARTx LPUART Instance
1293 * @param Polarity This parameter can be one of the following values:
1294 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1295 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1296 * @retval None
1297 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1298 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1299 {
1300 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1301 }
1302
1303 /**
1304 * @brief Return Driver Enable Polarity
1305 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1306 * @param LPUARTx LPUART Instance
1307 * @retval Returned value can be one of the following values:
1308 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1309 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1310 */
LL_LPUART_GetDESignalPolarity(USART_TypeDef * LPUARTx)1311 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
1312 {
1313 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1314 }
1315
1316 /**
1317 * @}
1318 */
1319
1320 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1321 * @{
1322 */
1323
1324 /**
1325 * @brief Check if the LPUART Parity Error Flag is set or not
1326 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1327 * @param LPUARTx LPUART Instance
1328 * @retval State of bit (1 or 0).
1329 */
LL_LPUART_IsActiveFlag_PE(USART_TypeDef * LPUARTx)1330 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
1331 {
1332 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1333 }
1334
1335 /**
1336 * @brief Check if the LPUART Framing Error Flag is set or not
1337 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1338 * @param LPUARTx LPUART Instance
1339 * @retval State of bit (1 or 0).
1340 */
LL_LPUART_IsActiveFlag_FE(USART_TypeDef * LPUARTx)1341 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
1342 {
1343 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1344 }
1345
1346 /**
1347 * @brief Check if the LPUART Noise error detected Flag is set or not
1348 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1349 * @param LPUARTx LPUART Instance
1350 * @retval State of bit (1 or 0).
1351 */
LL_LPUART_IsActiveFlag_NE(USART_TypeDef * LPUARTx)1352 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
1353 {
1354 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1355 }
1356
1357 /**
1358 * @brief Check if the LPUART OverRun Error Flag is set or not
1359 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1360 * @param LPUARTx LPUART Instance
1361 * @retval State of bit (1 or 0).
1362 */
LL_LPUART_IsActiveFlag_ORE(USART_TypeDef * LPUARTx)1363 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
1364 {
1365 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1366 }
1367
1368 /**
1369 * @brief Check if the LPUART IDLE line detected Flag is set or not
1370 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1371 * @param LPUARTx LPUART Instance
1372 * @retval State of bit (1 or 0).
1373 */
LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef * LPUARTx)1374 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
1375 {
1376 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1377 }
1378
1379 /**
1380 * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not
1381 * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE
1382 * @param LPUARTx LPUART Instance
1383 * @retval State of bit (1 or 0).
1384 */
LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef * LPUARTx)1385 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)
1386 {
1387 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
1388 }
1389
1390 /**
1391 * @brief Check if the LPUART Transmission Complete Flag is set or not
1392 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1393 * @param LPUARTx LPUART Instance
1394 * @retval State of bit (1 or 0).
1395 */
LL_LPUART_IsActiveFlag_TC(USART_TypeDef * LPUARTx)1396 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
1397 {
1398 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1399 }
1400
1401 /**
1402 * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not
1403 * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE
1404 * @param LPUARTx LPUART Instance
1405 * @retval State of bit (1 or 0).
1406 */
LL_LPUART_IsActiveFlag_TXE(USART_TypeDef * LPUARTx)1407 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)
1408 {
1409 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
1410 }
1411
1412 /**
1413 * @brief Check if the LPUART CTS interrupt Flag is set or not
1414 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1415 * @param LPUARTx LPUART Instance
1416 * @retval State of bit (1 or 0).
1417 */
LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef * LPUARTx)1418 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
1419 {
1420 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1421 }
1422
1423 /**
1424 * @brief Check if the LPUART CTS Flag is set or not
1425 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1426 * @param LPUARTx LPUART Instance
1427 * @retval State of bit (1 or 0).
1428 */
LL_LPUART_IsActiveFlag_CTS(USART_TypeDef * LPUARTx)1429 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
1430 {
1431 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1432 }
1433
1434 /**
1435 * @brief Check if the LPUART Busy Flag is set or not
1436 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1437 * @param LPUARTx LPUART Instance
1438 * @retval State of bit (1 or 0).
1439 */
LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef * LPUARTx)1440 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
1441 {
1442 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1443 }
1444
1445 /**
1446 * @brief Check if the LPUART Character Match Flag is set or not
1447 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1448 * @param LPUARTx LPUART Instance
1449 * @retval State of bit (1 or 0).
1450 */
LL_LPUART_IsActiveFlag_CM(USART_TypeDef * LPUARTx)1451 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
1452 {
1453 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1454 }
1455
1456 /**
1457 * @brief Check if the LPUART Send Break Flag is set or not
1458 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1459 * @param LPUARTx LPUART Instance
1460 * @retval State of bit (1 or 0).
1461 */
LL_LPUART_IsActiveFlag_SBK(USART_TypeDef * LPUARTx)1462 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
1463 {
1464 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1465 }
1466
1467 /**
1468 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1469 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1470 * @param LPUARTx LPUART Instance
1471 * @retval State of bit (1 or 0).
1472 */
LL_LPUART_IsActiveFlag_RWU(USART_TypeDef * LPUARTx)1473 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
1474 {
1475 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1476 }
1477
1478 /**
1479 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1480 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1481 * @param LPUARTx LPUART Instance
1482 * @retval State of bit (1 or 0).
1483 */
LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef * LPUARTx)1484 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
1485 {
1486 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1487 }
1488
1489 /**
1490 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1491 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1492 * @param LPUARTx LPUART Instance
1493 * @retval State of bit (1 or 0).
1494 */
LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef * LPUARTx)1495 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
1496 {
1497 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1498 }
1499
1500 /**
1501 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1502 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1503 * @param LPUARTx LPUART Instance
1504 * @retval State of bit (1 or 0).
1505 */
LL_LPUART_IsActiveFlag_REACK(USART_TypeDef * LPUARTx)1506 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
1507 {
1508 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1509 }
1510
1511
1512 /**
1513 * @brief Clear Parity Error Flag
1514 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1515 * @param LPUARTx LPUART Instance
1516 * @retval None
1517 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1518 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1519 {
1520 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1521 }
1522
1523 /**
1524 * @brief Clear Framing Error Flag
1525 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1526 * @param LPUARTx LPUART Instance
1527 * @retval None
1528 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1529 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1530 {
1531 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1532 }
1533
1534 /**
1535 * @brief Clear Noise detected Flag
1536 * @rmtoll ICR NCF LL_LPUART_ClearFlag_NE
1537 * @param LPUARTx LPUART Instance
1538 * @retval None
1539 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1540 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1541 {
1542 WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);
1543 }
1544
1545 /**
1546 * @brief Clear OverRun Error Flag
1547 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1548 * @param LPUARTx LPUART Instance
1549 * @retval None
1550 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1551 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1552 {
1553 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1554 }
1555
1556 /**
1557 * @brief Clear IDLE line detected Flag
1558 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1559 * @param LPUARTx LPUART Instance
1560 * @retval None
1561 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1562 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1563 {
1564 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1565 }
1566
1567
1568 /**
1569 * @brief Clear Transmission Complete Flag
1570 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1571 * @param LPUARTx LPUART Instance
1572 * @retval None
1573 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1574 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1575 {
1576 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1577 }
1578
1579 /**
1580 * @brief Clear CTS Interrupt Flag
1581 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1582 * @param LPUARTx LPUART Instance
1583 * @retval None
1584 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1585 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1586 {
1587 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1588 }
1589
1590 /**
1591 * @brief Clear Character Match Flag
1592 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1593 * @param LPUARTx LPUART Instance
1594 * @retval None
1595 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1596 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1597 {
1598 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1599 }
1600
1601 /**
1602 * @brief Clear Wake Up from stop mode Flag
1603 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1604 * @param LPUARTx LPUART Instance
1605 * @retval None
1606 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)1607 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1608 {
1609 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1610 }
1611
1612 /**
1613 * @}
1614 */
1615
1616 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1617 * @{
1618 */
1619
1620 /**
1621 * @brief Enable IDLE Interrupt
1622 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1623 * @param LPUARTx LPUART Instance
1624 * @retval None
1625 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1626 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1627 {
1628 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1629 }
1630
1631
1632 /**
1633 * @brief Enable RX Not Empty Interrupt
1634 * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE
1635 * @param LPUARTx LPUART Instance
1636 * @retval None
1637 */
LL_LPUART_EnableIT_RXNE(USART_TypeDef * LPUARTx)1638 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)
1639 {
1640 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
1641 }
1642
1643 /**
1644 * @brief Enable Transmission Complete Interrupt
1645 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1646 * @param LPUARTx LPUART Instance
1647 * @retval None
1648 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1649 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1650 {
1651 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1652 }
1653
1654
1655 /**
1656 * @brief Enable TX Empty Interrupt
1657 * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE
1658 * @param LPUARTx LPUART Instance
1659 * @retval None
1660 */
LL_LPUART_EnableIT_TXE(USART_TypeDef * LPUARTx)1661 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)
1662 {
1663 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
1664 }
1665
1666 /**
1667 * @brief Enable Parity Error Interrupt
1668 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1669 * @param LPUARTx LPUART Instance
1670 * @retval None
1671 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1672 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1673 {
1674 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1675 }
1676
1677 /**
1678 * @brief Enable Character Match Interrupt
1679 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1680 * @param LPUARTx LPUART Instance
1681 * @retval None
1682 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)1683 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1684 {
1685 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1686 }
1687
1688
1689 /**
1690 * @brief Enable Error Interrupt
1691 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
1692 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
1693 * - 0: Interrupt is inhibited
1694 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
1695 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
1696 * @param LPUARTx LPUART Instance
1697 * @retval None
1698 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)1699 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
1700 {
1701 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
1702 }
1703
1704 /**
1705 * @brief Enable CTS Interrupt
1706 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
1707 * @param LPUARTx LPUART Instance
1708 * @retval None
1709 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)1710 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
1711 {
1712 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
1713 }
1714
1715 /**
1716 * @brief Enable Wake Up from Stop Mode Interrupt
1717 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
1718 * @param LPUARTx LPUART Instance
1719 * @retval None
1720 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)1721 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
1722 {
1723 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
1724 }
1725
1726
1727 /**
1728 * @brief Disable IDLE Interrupt
1729 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
1730 * @param LPUARTx LPUART Instance
1731 * @retval None
1732 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)1733 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
1734 {
1735 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1736 }
1737
1738
1739 /**
1740 * @brief Disable RX Not Empty Interrupt
1741 * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE
1742 * @param LPUARTx LPUART Instance
1743 * @retval None
1744 */
LL_LPUART_DisableIT_RXNE(USART_TypeDef * LPUARTx)1745 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)
1746 {
1747 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);
1748 }
1749
1750 /**
1751 * @brief Disable Transmission Complete Interrupt
1752 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
1753 * @param LPUARTx LPUART Instance
1754 * @retval None
1755 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)1756 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
1757 {
1758 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1759 }
1760
1761
1762 /**
1763 * @brief Disable TX Empty Interrupt
1764 * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE
1765 * @param LPUARTx LPUART Instance
1766 * @retval None
1767 */
LL_LPUART_DisableIT_TXE(USART_TypeDef * LPUARTx)1768 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)
1769 {
1770 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);
1771 }
1772
1773 /**
1774 * @brief Disable Parity Error Interrupt
1775 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
1776 * @param LPUARTx LPUART Instance
1777 * @retval None
1778 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)1779 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
1780 {
1781 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1782 }
1783
1784 /**
1785 * @brief Disable Character Match Interrupt
1786 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
1787 * @param LPUARTx LPUART Instance
1788 * @retval None
1789 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)1790 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
1791 {
1792 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1793 }
1794
1795
1796 /**
1797 * @brief Disable Error Interrupt
1798 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
1799 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
1800 * - 0: Interrupt is inhibited
1801 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
1802 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
1803 * @param LPUARTx LPUART Instance
1804 * @retval None
1805 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)1806 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
1807 {
1808 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
1809 }
1810
1811 /**
1812 * @brief Disable CTS Interrupt
1813 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
1814 * @param LPUARTx LPUART Instance
1815 * @retval None
1816 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)1817 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
1818 {
1819 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
1820 }
1821
1822 /**
1823 * @brief Disable Wake Up from Stop Mode Interrupt
1824 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
1825 * @param LPUARTx LPUART Instance
1826 * @retval None
1827 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)1828 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
1829 {
1830 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
1831 }
1832
1833
1834 /**
1835 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
1836 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
1837 * @param LPUARTx LPUART Instance
1838 * @retval State of bit (1 or 0).
1839 */
LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef * LPUARTx)1840 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
1841 {
1842 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
1843 }
1844
1845
1846 /**
1847 * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled.
1848 * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE
1849 * @param LPUARTx LPUART Instance
1850 * @retval State of bit (1 or 0).
1851 */
LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef * LPUARTx)1852 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)
1853 {
1854 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL);
1855 }
1856
1857 /**
1858 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
1859 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
1860 * @param LPUARTx LPUART Instance
1861 * @retval State of bit (1 or 0).
1862 */
LL_LPUART_IsEnabledIT_TC(USART_TypeDef * LPUARTx)1863 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
1864 {
1865 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
1866 }
1867
1868
1869 /**
1870 * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled.
1871 * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE
1872 * @param LPUARTx LPUART Instance
1873 * @retval State of bit (1 or 0).
1874 */
LL_LPUART_IsEnabledIT_TXE(USART_TypeDef * LPUARTx)1875 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)
1876 {
1877 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL);
1878 }
1879
1880 /**
1881 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
1882 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
1883 * @param LPUARTx LPUART Instance
1884 * @retval State of bit (1 or 0).
1885 */
LL_LPUART_IsEnabledIT_PE(USART_TypeDef * LPUARTx)1886 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
1887 {
1888 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
1889 }
1890
1891 /**
1892 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
1893 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
1894 * @param LPUARTx LPUART Instance
1895 * @retval State of bit (1 or 0).
1896 */
LL_LPUART_IsEnabledIT_CM(USART_TypeDef * LPUARTx)1897 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
1898 {
1899 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
1900 }
1901
1902
1903 /**
1904 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
1905 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
1906 * @param LPUARTx LPUART Instance
1907 * @retval State of bit (1 or 0).
1908 */
LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef * LPUARTx)1909 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
1910 {
1911 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
1912 }
1913
1914 /**
1915 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
1916 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
1917 * @param LPUARTx LPUART Instance
1918 * @retval State of bit (1 or 0).
1919 */
LL_LPUART_IsEnabledIT_CTS(USART_TypeDef * LPUARTx)1920 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
1921 {
1922 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
1923 }
1924
1925 /**
1926 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
1927 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
1928 * @param LPUARTx LPUART Instance
1929 * @retval State of bit (1 or 0).
1930 */
LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef * LPUARTx)1931 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
1932 {
1933 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
1934 }
1935
1936
1937 /**
1938 * @}
1939 */
1940
1941 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
1942 * @{
1943 */
1944
1945 /**
1946 * @brief Enable DMA Mode for reception
1947 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
1948 * @param LPUARTx LPUART Instance
1949 * @retval None
1950 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)1951 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
1952 {
1953 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
1954 }
1955
1956 /**
1957 * @brief Disable DMA Mode for reception
1958 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
1959 * @param LPUARTx LPUART Instance
1960 * @retval None
1961 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)1962 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
1963 {
1964 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
1965 }
1966
1967 /**
1968 * @brief Check if DMA Mode is enabled for reception
1969 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
1970 * @param LPUARTx LPUART Instance
1971 * @retval State of bit (1 or 0).
1972 */
LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef * LPUARTx)1973 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
1974 {
1975 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
1976 }
1977
1978 /**
1979 * @brief Enable DMA Mode for transmission
1980 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
1981 * @param LPUARTx LPUART Instance
1982 * @retval None
1983 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)1984 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
1985 {
1986 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
1987 }
1988
1989 /**
1990 * @brief Disable DMA Mode for transmission
1991 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
1992 * @param LPUARTx LPUART Instance
1993 * @retval None
1994 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)1995 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
1996 {
1997 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
1998 }
1999
2000 /**
2001 * @brief Check if DMA Mode is enabled for transmission
2002 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2003 * @param LPUARTx LPUART Instance
2004 * @retval State of bit (1 or 0).
2005 */
LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef * LPUARTx)2006 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
2007 {
2008 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2009 }
2010
2011 /**
2012 * @brief Enable DMA Disabling on Reception Error
2013 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2014 * @param LPUARTx LPUART Instance
2015 * @retval None
2016 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2017 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2018 {
2019 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2020 }
2021
2022 /**
2023 * @brief Disable DMA Disabling on Reception Error
2024 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2025 * @param LPUARTx LPUART Instance
2026 * @retval None
2027 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2028 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2029 {
2030 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2031 }
2032
2033 /**
2034 * @brief Indicate if DMA Disabling on Reception Error is disabled
2035 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2036 * @param LPUARTx LPUART Instance
2037 * @retval State of bit (1 or 0).
2038 */
LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef * LPUARTx)2039 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2040 {
2041 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2042 }
2043
2044 /**
2045 * @brief Get the LPUART data register address used for DMA transfer
2046 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2047 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2048 * @param LPUARTx LPUART Instance
2049 * @param Direction This parameter can be one of the following values:
2050 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2051 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2052 * @retval Address of data register
2053 */
LL_LPUART_DMA_GetRegAddr(USART_TypeDef * LPUARTx,uint32_t Direction)2054 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
2055 {
2056 uint32_t data_reg_addr;
2057
2058 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2059 {
2060 /* return address of TDR register */
2061 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2062 }
2063 else
2064 {
2065 /* return address of RDR register */
2066 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2067 }
2068
2069 return data_reg_addr;
2070 }
2071
2072 /**
2073 * @}
2074 */
2075
2076 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2077 * @{
2078 */
2079
2080 /**
2081 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2082 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2083 * @param LPUARTx LPUART Instance
2084 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2085 */
LL_LPUART_ReceiveData8(USART_TypeDef * LPUARTx)2086 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
2087 {
2088 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2089 }
2090
2091 /**
2092 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2093 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2094 * @param LPUARTx LPUART Instance
2095 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2096 */
LL_LPUART_ReceiveData9(USART_TypeDef * LPUARTx)2097 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
2098 {
2099 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2100 }
2101
2102 /**
2103 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2104 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2105 * @param LPUARTx LPUART Instance
2106 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2107 * @retval None
2108 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2109 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2110 {
2111 LPUARTx->TDR = Value;
2112 }
2113
2114 /**
2115 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2116 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2117 * @param LPUARTx LPUART Instance
2118 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2119 * @retval None
2120 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2121 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2122 {
2123 LPUARTx->TDR = Value & 0x1FFUL;
2124 }
2125
2126 /**
2127 * @}
2128 */
2129
2130 /** @defgroup LPUART_LL_EF_Execution Execution
2131 * @{
2132 */
2133
2134 /**
2135 * @brief Request Break sending
2136 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2137 * @param LPUARTx LPUART Instance
2138 * @retval None
2139 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2140 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2141 {
2142 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2143 }
2144
2145 /**
2146 * @brief Put LPUART in mute mode and set the RWU flag
2147 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2148 * @param LPUARTx LPUART Instance
2149 * @retval None
2150 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2151 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2152 {
2153 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2154 }
2155
2156 /**
2157 * @brief Request a Receive Data flush
2158 * @note Allows to discard the received data without reading them, and avoid an overrun
2159 * condition.
2160 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2161 * @param LPUARTx LPUART Instance
2162 * @retval None
2163 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2164 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2165 {
2166 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2167 }
2168
2169 /**
2170 * @}
2171 */
2172
2173 #if defined(USE_FULL_LL_DRIVER)
2174 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2175 * @{
2176 */
2177 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
2178 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
2179 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2180 /**
2181 * @}
2182 */
2183 #endif /* USE_FULL_LL_DRIVER */
2184
2185 /**
2186 * @}
2187 */
2188
2189 /**
2190 * @}
2191 */
2192
2193 #endif /* LPUART1 */
2194
2195 /**
2196 * @}
2197 */
2198
2199 #ifdef __cplusplus
2200 }
2201 #endif
2202
2203 #endif /* STM32L0xx_LL_LPUART_H */
2204
2205 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2206
