1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L0xx_LL_I2C_H
22 #define STM32L0xx_LL_I2C_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx.h"
30
31 /** @addtogroup STM32L0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
36
37 /** @defgroup I2C_LL I2C
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
55 * @{
56 */
57 /**
58 * @}
59 */
60 #endif /*USE_FULL_LL_DRIVER*/
61
62 /* Exported types ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
65 * @{
66 */
67 typedef struct
68 {
69 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
70 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_I2C_SetMode(). */
74
75 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
76 This parameter must be set by referring to the STM32CubeMX Tool and
77 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
78
79 This feature can be modified afterwards using unitary function
80 @ref LL_I2C_SetTiming(). */
81
82 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
83 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
84
85 This feature can be modified afterwards using unitary functions
86 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
87
88 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
89 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
90
91 This feature can be modified afterwards using unitary function
92 @ref LL_I2C_SetDigitalFilter(). */
93
94 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
95 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
96
97 This feature can be modified afterwards using unitary function
98 @ref LL_I2C_SetOwnAddress1(). */
99
100 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
101 match code or next received byte.
102 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
103
104 This feature can be modified afterwards using unitary function
105 @ref LL_I2C_AcknowledgeNextData(). */
106
107 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
108 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
109
110 This feature can be modified afterwards using unitary function
111 @ref LL_I2C_SetOwnAddress1(). */
112 } LL_I2C_InitTypeDef;
113 /**
114 * @}
115 */
116 #endif /*USE_FULL_LL_DRIVER*/
117
118 /* Exported constants --------------------------------------------------------*/
119 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
120 * @{
121 */
122
123 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
124 * @brief Flags defines which can be used with LL_I2C_WriteReg function
125 * @{
126 */
127 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
128 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
129 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
130 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
131 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
132 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
133 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
134 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
135 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
136 /**
137 * @}
138 */
139
140 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
141 * @brief Flags defines which can be used with LL_I2C_ReadReg function
142 * @{
143 */
144 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
145 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
146 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
147 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
148 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
149 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
150 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
151 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
152 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
153 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
154 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
155 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
156 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
157 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
158 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
159 /**
160 * @}
161 */
162
163 /** @defgroup I2C_LL_EC_IT IT Defines
164 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
165 * @{
166 */
167 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
168 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
169 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
170 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
171 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
172 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
173 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
174 /**
175 * @}
176 */
177
178 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
179 * @{
180 */
181 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
182 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
183 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
184 (Default address not acknowledge) */
185 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
186 /**
187 * @}
188 */
189
190 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
191 * @{
192 */
193 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
194 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
195 /**
196 * @}
197 */
198
199 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
200 * @{
201 */
202 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
203 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
209 * @{
210 */
211 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
212 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
213 /**
214 * @}
215 */
216
217 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
218 * @{
219 */
220 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
221 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
222 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
223 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
227 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
228 All Address2 are acknowledged. */
229 /**
230 * @}
231 */
232
233 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
234 * @{
235 */
236 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
237 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
238 /**
239 * @}
240 */
241
242 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
243 * @{
244 */
245 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
246 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
247 /**
248 * @}
249 */
250
251 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
252 * @{
253 */
254 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
255 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
256 /**
257 * @}
258 */
259
260 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
261 * @{
262 */
263 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
264 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
265 with no HW PEC comparison. */
266 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
267 with no HW PEC comparison. */
268 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
269 with HW PEC comparison. */
270 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
271 with HW PEC comparison. */
272 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
273 with HW PEC comparison. */
274 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
275 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
276 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
277 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
278 /**
279 * @}
280 */
281
282 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
283 * @{
284 */
285 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
286 /*!< Don't Generate Stop and Start condition. */
287 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
288 /*!< Generate Stop condition (Size should be set to 0). */
289 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
290 /*!< Generate Start for read request. */
291 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
292 /*!< Generate Start for write request. */
293 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
294 /*!< Generate Restart for read request, slave 7Bit address. */
295 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
296 /*!< Generate Restart for write request, slave 7Bit address. */
297 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
298 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
299 /*!< Generate Restart for read request, slave 10Bit address. */
300 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
301 /*!< Generate Restart for write request, slave 10Bit address.*/
302 /**
303 * @}
304 */
305
306 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
307 * @{
308 */
309 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
310 slave enters receiver mode. */
311 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
312 slave enters transmitter mode.*/
313 /**
314 * @}
315 */
316
317 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
318 * @{
319 */
320 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
321 transmission */
322 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
323 reception */
324 /**
325 * @}
326 */
327
328 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
329 * @{
330 */
331 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
332 SCL low level timeout. */
333 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
334 both SCL and SDA high level timeout.*/
335 /**
336 * @}
337 */
338
339 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
340 * @{
341 */
342 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
343 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
344 enable bit */
345 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
346 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
347 (extended clock) enable bits */
348 /**
349 * @}
350 */
351
352 /**
353 * @}
354 */
355
356 /* Exported macro ------------------------------------------------------------*/
357 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
358 * @{
359 */
360
361 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
362 * @{
363 */
364
365 /**
366 * @brief Write a value in I2C register
367 * @param __INSTANCE__ I2C Instance
368 * @param __REG__ Register to be written
369 * @param __VALUE__ Value to be written in the register
370 * @retval None
371 */
372 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
373
374 /**
375 * @brief Read a value in I2C register
376 * @param __INSTANCE__ I2C Instance
377 * @param __REG__ Register to be read
378 * @retval Register value
379 */
380 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
381 /**
382 * @}
383 */
384
385 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
386 * @{
387 */
388 /**
389 * @brief Configure the SDA setup, hold time and the SCL high, low period.
390 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
391 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
392 (tscldel = (SCLDEL+1)xtpresc)
393 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
394 (tsdadel = SDADELxtpresc)
395 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
396 (tsclh = (SCLH+1)xtpresc)
397 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
398 (tscll = (SCLL+1)xtpresc)
399 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
400 */
401 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
402 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
403 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
404 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
405 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
406 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
407 /**
408 * @}
409 */
410
411 /**
412 * @}
413 */
414
415 /* Exported functions --------------------------------------------------------*/
416 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
417 * @{
418 */
419
420 /** @defgroup I2C_LL_EF_Configuration Configuration
421 * @{
422 */
423
424 /**
425 * @brief Enable I2C peripheral (PE = 1).
426 * @rmtoll CR1 PE LL_I2C_Enable
427 * @param I2Cx I2C Instance.
428 * @retval None
429 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)430 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
431 {
432 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
433 }
434
435 /**
436 * @brief Disable I2C peripheral (PE = 0).
437 * @note When PE = 0, the I2C SCL and SDA lines are released.
438 * Internal state machines and status bits are put back to their reset value.
439 * When cleared, PE must be kept low for at least 3 APB clock cycles.
440 * @rmtoll CR1 PE LL_I2C_Disable
441 * @param I2Cx I2C Instance.
442 * @retval None
443 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)444 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
445 {
446 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
447 }
448
449 /**
450 * @brief Check if the I2C peripheral is enabled or disabled.
451 * @rmtoll CR1 PE LL_I2C_IsEnabled
452 * @param I2Cx I2C Instance.
453 * @retval State of bit (1 or 0).
454 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)455 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
456 {
457 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
458 }
459
460 /**
461 * @brief Configure Noise Filters (Analog and Digital).
462 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
463 * The filters can only be programmed when the I2C is disabled (PE = 0).
464 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
465 * CR1 DNF LL_I2C_ConfigFilters
466 * @param I2Cx I2C Instance.
467 * @param AnalogFilter This parameter can be one of the following values:
468 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
469 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
470 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
471 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
472 * This parameter is used to configure the digital noise filter on SDA and SCL input.
473 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
474 * @retval None
475 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)476 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
477 {
478 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
479 }
480
481 /**
482 * @brief Configure Digital Noise Filter.
483 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
484 * This filter can only be programmed when the I2C is disabled (PE = 0).
485 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
486 * @param I2Cx I2C Instance.
487 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
488 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
489 * This parameter is used to configure the digital noise filter on SDA and SCL input.
490 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
491 * @retval None
492 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)493 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
494 {
495 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
496 }
497
498 /**
499 * @brief Get the current Digital Noise Filter configuration.
500 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
501 * @param I2Cx I2C Instance.
502 * @retval Value between Min_Data=0x0 and Max_Data=0xF
503 */
LL_I2C_GetDigitalFilter(I2C_TypeDef * I2Cx)504 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
505 {
506 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
507 }
508
509 /**
510 * @brief Enable Analog Noise Filter.
511 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
512 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
513 * @param I2Cx I2C Instance.
514 * @retval None
515 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)516 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
517 {
518 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
519 }
520
521 /**
522 * @brief Disable Analog Noise Filter.
523 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
524 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
525 * @param I2Cx I2C Instance.
526 * @retval None
527 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)528 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
529 {
530 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
531 }
532
533 /**
534 * @brief Check if Analog Noise Filter is enabled or disabled.
535 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
536 * @param I2Cx I2C Instance.
537 * @retval State of bit (1 or 0).
538 */
LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef * I2Cx)539 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
540 {
541 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
542 }
543
544 /**
545 * @brief Enable DMA transmission requests.
546 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
547 * @param I2Cx I2C Instance.
548 * @retval None
549 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)550 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
551 {
552 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
553 }
554
555 /**
556 * @brief Disable DMA transmission requests.
557 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
558 * @param I2Cx I2C Instance.
559 * @retval None
560 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)561 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
562 {
563 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
564 }
565
566 /**
567 * @brief Check if DMA transmission requests are enabled or disabled.
568 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
569 * @param I2Cx I2C Instance.
570 * @retval State of bit (1 or 0).
571 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)572 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
573 {
574 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
575 }
576
577 /**
578 * @brief Enable DMA reception requests.
579 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
580 * @param I2Cx I2C Instance.
581 * @retval None
582 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)583 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
584 {
585 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
586 }
587
588 /**
589 * @brief Disable DMA reception requests.
590 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
591 * @param I2Cx I2C Instance.
592 * @retval None
593 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)594 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
595 {
596 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
597 }
598
599 /**
600 * @brief Check if DMA reception requests are enabled or disabled.
601 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
602 * @param I2Cx I2C Instance.
603 * @retval State of bit (1 or 0).
604 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)605 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
606 {
607 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
608 }
609
610 /**
611 * @brief Get the data register address used for DMA transfer
612 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
613 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
614 * @param I2Cx I2C Instance
615 * @param Direction This parameter can be one of the following values:
616 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
617 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
618 * @retval Address of data register
619 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx,uint32_t Direction)620 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
621 {
622 uint32_t data_reg_addr;
623
624 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
625 {
626 /* return address of TXDR register */
627 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
628 }
629 else
630 {
631 /* return address of RXDR register */
632 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
633 }
634
635 return data_reg_addr;
636 }
637
638 /**
639 * @brief Enable Clock stretching.
640 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
641 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
642 * @param I2Cx I2C Instance.
643 * @retval None
644 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)645 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
646 {
647 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
648 }
649
650 /**
651 * @brief Disable Clock stretching.
652 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
653 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
654 * @param I2Cx I2C Instance.
655 * @retval None
656 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)657 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
658 {
659 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
660 }
661
662 /**
663 * @brief Check if Clock stretching is enabled or disabled.
664 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
665 * @param I2Cx I2C Instance.
666 * @retval State of bit (1 or 0).
667 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)668 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
669 {
670 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
671 }
672
673 /**
674 * @brief Enable hardware byte control in slave mode.
675 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
676 * @param I2Cx I2C Instance.
677 * @retval None
678 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)679 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
680 {
681 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
682 }
683
684 /**
685 * @brief Disable hardware byte control in slave mode.
686 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
687 * @param I2Cx I2C Instance.
688 * @retval None
689 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)690 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
691 {
692 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
693 }
694
695 /**
696 * @brief Check if hardware byte control in slave mode is enabled or disabled.
697 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
698 * @param I2Cx I2C Instance.
699 * @retval State of bit (1 or 0).
700 */
LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef * I2Cx)701 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
702 {
703 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
704 }
705
706 /**
707 * @brief Enable Wakeup from STOP.
708 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
709 * WakeUpFromStop feature is supported by the I2Cx Instance.
710 * @note This bit can only be programmed when Digital Filter is disabled.
711 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
712 * @param I2Cx I2C Instance.
713 * @retval None
714 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)715 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
716 {
717 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
718 }
719
720 /**
721 * @brief Disable Wakeup from STOP.
722 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
723 * WakeUpFromStop feature is supported by the I2Cx Instance.
724 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
725 * @param I2Cx I2C Instance.
726 * @retval None
727 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)728 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
729 {
730 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
731 }
732
733 /**
734 * @brief Check if Wakeup from STOP is enabled or disabled.
735 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
736 * WakeUpFromStop feature is supported by the I2Cx Instance.
737 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
738 * @param I2Cx I2C Instance.
739 * @retval State of bit (1 or 0).
740 */
LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef * I2Cx)741 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
742 {
743 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
744 }
745
746 /**
747 * @brief Enable General Call.
748 * @note When enabled the Address 0x00 is ACKed.
749 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
750 * @param I2Cx I2C Instance.
751 * @retval None
752 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)753 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
754 {
755 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
756 }
757
758 /**
759 * @brief Disable General Call.
760 * @note When disabled the Address 0x00 is NACKed.
761 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
762 * @param I2Cx I2C Instance.
763 * @retval None
764 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)765 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
766 {
767 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
768 }
769
770 /**
771 * @brief Check if General Call is enabled or disabled.
772 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
773 * @param I2Cx I2C Instance.
774 * @retval State of bit (1 or 0).
775 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)776 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
777 {
778 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
779 }
780
781 /**
782 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
783 * @note Changing this bit is not allowed, when the START bit is set.
784 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
785 * @param I2Cx I2C Instance.
786 * @param AddressingMode This parameter can be one of the following values:
787 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
788 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
789 * @retval None
790 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)791 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
792 {
793 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
794 }
795
796 /**
797 * @brief Get the Master addressing mode.
798 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
799 * @param I2Cx I2C Instance.
800 * @retval Returned value can be one of the following values:
801 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
802 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
803 */
LL_I2C_GetMasterAddressingMode(I2C_TypeDef * I2Cx)804 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
805 {
806 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
807 }
808
809 /**
810 * @brief Set the Own Address1.
811 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
812 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
813 * @param I2Cx I2C Instance.
814 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
815 * @param OwnAddrSize This parameter can be one of the following values:
816 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
817 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
818 * @retval None
819 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)820 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
821 {
822 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
823 }
824
825 /**
826 * @brief Enable acknowledge on Own Address1 match address.
827 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
828 * @param I2Cx I2C Instance.
829 * @retval None
830 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)831 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
832 {
833 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
834 }
835
836 /**
837 * @brief Disable acknowledge on Own Address1 match address.
838 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
839 * @param I2Cx I2C Instance.
840 * @retval None
841 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)842 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
843 {
844 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
845 }
846
847 /**
848 * @brief Check if Own Address1 acknowledge is enabled or disabled.
849 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
850 * @param I2Cx I2C Instance.
851 * @retval State of bit (1 or 0).
852 */
LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef * I2Cx)853 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
854 {
855 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
856 }
857
858 /**
859 * @brief Set the 7bits Own Address2.
860 * @note This action has no effect if own address2 is enabled.
861 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
862 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
863 * @param I2Cx I2C Instance.
864 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
865 * @param OwnAddrMask This parameter can be one of the following values:
866 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
867 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
868 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
869 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
870 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
871 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
872 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
873 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
874 * @retval None
875 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)876 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
877 {
878 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
879 }
880
881 /**
882 * @brief Enable acknowledge on Own Address2 match address.
883 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
884 * @param I2Cx I2C Instance.
885 * @retval None
886 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)887 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
888 {
889 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
890 }
891
892 /**
893 * @brief Disable acknowledge on Own Address2 match address.
894 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
895 * @param I2Cx I2C Instance.
896 * @retval None
897 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)898 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
899 {
900 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
901 }
902
903 /**
904 * @brief Check if Own Address1 acknowledge is enabled or disabled.
905 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
906 * @param I2Cx I2C Instance.
907 * @retval State of bit (1 or 0).
908 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)909 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
910 {
911 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
912 }
913
914 /**
915 * @brief Configure the SDA setup, hold time and the SCL high, low period.
916 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
917 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
918 * @param I2Cx I2C Instance.
919 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
920 * @note This parameter is computed with the STM32CubeMX Tool.
921 * @retval None
922 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)923 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
924 {
925 WRITE_REG(I2Cx->TIMINGR, Timing);
926 }
927
928 /**
929 * @brief Get the Timing Prescaler setting.
930 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
931 * @param I2Cx I2C Instance.
932 * @retval Value between Min_Data=0x0 and Max_Data=0xF
933 */
LL_I2C_GetTimingPrescaler(I2C_TypeDef * I2Cx)934 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
935 {
936 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
937 }
938
939 /**
940 * @brief Get the SCL low period setting.
941 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
942 * @param I2Cx I2C Instance.
943 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
944 */
LL_I2C_GetClockLowPeriod(I2C_TypeDef * I2Cx)945 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
946 {
947 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
948 }
949
950 /**
951 * @brief Get the SCL high period setting.
952 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
953 * @param I2Cx I2C Instance.
954 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
955 */
LL_I2C_GetClockHighPeriod(I2C_TypeDef * I2Cx)956 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
957 {
958 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
959 }
960
961 /**
962 * @brief Get the SDA hold time.
963 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
964 * @param I2Cx I2C Instance.
965 * @retval Value between Min_Data=0x0 and Max_Data=0xF
966 */
LL_I2C_GetDataHoldTime(I2C_TypeDef * I2Cx)967 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
968 {
969 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
970 }
971
972 /**
973 * @brief Get the SDA setup time.
974 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
975 * @param I2Cx I2C Instance.
976 * @retval Value between Min_Data=0x0 and Max_Data=0xF
977 */
LL_I2C_GetDataSetupTime(I2C_TypeDef * I2Cx)978 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
979 {
980 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
981 }
982
983 /**
984 * @brief Configure peripheral mode.
985 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
986 * SMBus feature is supported by the I2Cx Instance.
987 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
988 * CR1 SMBDEN LL_I2C_SetMode
989 * @param I2Cx I2C Instance.
990 * @param PeripheralMode This parameter can be one of the following values:
991 * @arg @ref LL_I2C_MODE_I2C
992 * @arg @ref LL_I2C_MODE_SMBUS_HOST
993 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
994 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
995 * @retval None
996 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)997 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
998 {
999 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1000 }
1001
1002 /**
1003 * @brief Get peripheral mode.
1004 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1005 * SMBus feature is supported by the I2Cx Instance.
1006 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1007 * CR1 SMBDEN LL_I2C_GetMode
1008 * @param I2Cx I2C Instance.
1009 * @retval Returned value can be one of the following values:
1010 * @arg @ref LL_I2C_MODE_I2C
1011 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1012 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1013 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1014 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)1015 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
1016 {
1017 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1018 }
1019
1020 /**
1021 * @brief Enable SMBus alert (Host or Device mode)
1022 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1023 * SMBus feature is supported by the I2Cx Instance.
1024 * @note SMBus Device mode:
1025 * - SMBus Alert pin is drived low and
1026 * Alert Response Address Header acknowledge is enabled.
1027 * SMBus Host mode:
1028 * - SMBus Alert pin management is supported.
1029 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1030 * @param I2Cx I2C Instance.
1031 * @retval None
1032 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1033 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1034 {
1035 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1036 }
1037
1038 /**
1039 * @brief Disable SMBus alert (Host or Device mode)
1040 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1041 * SMBus feature is supported by the I2Cx Instance.
1042 * @note SMBus Device mode:
1043 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1044 * Alert Response Address Header acknowledge is disabled.
1045 * SMBus Host mode:
1046 * - SMBus Alert pin management is not supported.
1047 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1048 * @param I2Cx I2C Instance.
1049 * @retval None
1050 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1051 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1052 {
1053 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1054 }
1055
1056 /**
1057 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1058 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1059 * SMBus feature is supported by the I2Cx Instance.
1060 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1061 * @param I2Cx I2C Instance.
1062 * @retval State of bit (1 or 0).
1063 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)1064 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1065 {
1066 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1067 }
1068
1069 /**
1070 * @brief Enable SMBus Packet Error Calculation (PEC).
1071 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1072 * SMBus feature is supported by the I2Cx Instance.
1073 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1074 * @param I2Cx I2C Instance.
1075 * @retval None
1076 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1077 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1078 {
1079 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1080 }
1081
1082 /**
1083 * @brief Disable SMBus Packet Error Calculation (PEC).
1084 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1085 * SMBus feature is supported by the I2Cx Instance.
1086 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1087 * @param I2Cx I2C Instance.
1088 * @retval None
1089 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1090 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1091 {
1092 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1093 }
1094
1095 /**
1096 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1097 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1098 * SMBus feature is supported by the I2Cx Instance.
1099 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1100 * @param I2Cx I2C Instance.
1101 * @retval State of bit (1 or 0).
1102 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)1103 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1104 {
1105 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1106 }
1107
1108 /**
1109 * @brief Configure the SMBus Clock Timeout.
1110 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1111 * SMBus feature is supported by the I2Cx Instance.
1112 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1113 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1114 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1115 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1116 * @param I2Cx I2C Instance.
1117 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1118 * @param TimeoutAMode This parameter can be one of the following values:
1119 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1120 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1121 * @param TimeoutB
1122 * @retval None
1123 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1124 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1125 uint32_t TimeoutB)
1126 {
1127 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1128 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1129 }
1130
1131 /**
1132 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1133 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1134 * SMBus feature is supported by the I2Cx Instance.
1135 * @note These bits can only be programmed when TimeoutA is disabled.
1136 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1137 * @param I2Cx I2C Instance.
1138 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1139 * @retval None
1140 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1141 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1142 {
1143 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1144 }
1145
1146 /**
1147 * @brief Get the SMBus Clock TimeoutA setting.
1148 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1149 * SMBus feature is supported by the I2Cx Instance.
1150 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1151 * @param I2Cx I2C Instance.
1152 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1153 */
LL_I2C_GetSMBusTimeoutA(I2C_TypeDef * I2Cx)1154 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1155 {
1156 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1157 }
1158
1159 /**
1160 * @brief Set the SMBus Clock TimeoutA mode.
1161 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1162 * SMBus feature is supported by the I2Cx Instance.
1163 * @note This bit can only be programmed when TimeoutA is disabled.
1164 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1165 * @param I2Cx I2C Instance.
1166 * @param TimeoutAMode This parameter can be one of the following values:
1167 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1168 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1169 * @retval None
1170 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1171 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1172 {
1173 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1174 }
1175
1176 /**
1177 * @brief Get the SMBus Clock TimeoutA mode.
1178 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1179 * SMBus feature is supported by the I2Cx Instance.
1180 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1181 * @param I2Cx I2C Instance.
1182 * @retval Returned value can be one of the following values:
1183 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1184 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1185 */
LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef * I2Cx)1186 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1187 {
1188 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1189 }
1190
1191 /**
1192 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1193 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1194 * SMBus feature is supported by the I2Cx Instance.
1195 * @note These bits can only be programmed when TimeoutB is disabled.
1196 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1197 * @param I2Cx I2C Instance.
1198 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1199 * @retval None
1200 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1201 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1202 {
1203 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1204 }
1205
1206 /**
1207 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1208 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1209 * SMBus feature is supported by the I2Cx Instance.
1210 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1211 * @param I2Cx I2C Instance.
1212 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1213 */
LL_I2C_GetSMBusTimeoutB(I2C_TypeDef * I2Cx)1214 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1215 {
1216 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1217 }
1218
1219 /**
1220 * @brief Enable the SMBus Clock Timeout.
1221 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1222 * SMBus feature is supported by the I2Cx Instance.
1223 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1224 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1225 * @param I2Cx I2C Instance.
1226 * @param ClockTimeout This parameter can be one of the following values:
1227 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1228 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1229 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1230 * @retval None
1231 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1232 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1233 {
1234 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1235 }
1236
1237 /**
1238 * @brief Disable the SMBus Clock Timeout.
1239 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1240 * SMBus feature is supported by the I2Cx Instance.
1241 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1242 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1243 * @param I2Cx I2C Instance.
1244 * @param ClockTimeout This parameter can be one of the following values:
1245 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1246 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1247 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1248 * @retval None
1249 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1250 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1251 {
1252 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1253 }
1254
1255 /**
1256 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1257 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1258 * SMBus feature is supported by the I2Cx Instance.
1259 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1260 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1261 * @param I2Cx I2C Instance.
1262 * @param ClockTimeout This parameter can be one of the following values:
1263 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1264 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1265 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1266 * @retval State of bit (1 or 0).
1267 */
LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1268 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1269 {
1270 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1271 (ClockTimeout)) ? 1UL : 0UL);
1272 }
1273
1274 /**
1275 * @}
1276 */
1277
1278 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1279 * @{
1280 */
1281
1282 /**
1283 * @brief Enable TXIS interrupt.
1284 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1285 * @param I2Cx I2C Instance.
1286 * @retval None
1287 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1288 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1289 {
1290 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1291 }
1292
1293 /**
1294 * @brief Disable TXIS interrupt.
1295 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1296 * @param I2Cx I2C Instance.
1297 * @retval None
1298 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1299 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1300 {
1301 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1302 }
1303
1304 /**
1305 * @brief Check if the TXIS Interrupt is enabled or disabled.
1306 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1307 * @param I2Cx I2C Instance.
1308 * @retval State of bit (1 or 0).
1309 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)1310 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1311 {
1312 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1313 }
1314
1315 /**
1316 * @brief Enable RXNE interrupt.
1317 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1318 * @param I2Cx I2C Instance.
1319 * @retval None
1320 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1321 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1322 {
1323 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1324 }
1325
1326 /**
1327 * @brief Disable RXNE interrupt.
1328 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1329 * @param I2Cx I2C Instance.
1330 * @retval None
1331 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1332 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1333 {
1334 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1335 }
1336
1337 /**
1338 * @brief Check if the RXNE Interrupt is enabled or disabled.
1339 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1340 * @param I2Cx I2C Instance.
1341 * @retval State of bit (1 or 0).
1342 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)1343 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1344 {
1345 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1346 }
1347
1348 /**
1349 * @brief Enable Address match interrupt (slave mode only).
1350 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1351 * @param I2Cx I2C Instance.
1352 * @retval None
1353 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1354 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1355 {
1356 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1357 }
1358
1359 /**
1360 * @brief Disable Address match interrupt (slave mode only).
1361 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1362 * @param I2Cx I2C Instance.
1363 * @retval None
1364 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1365 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1366 {
1367 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1368 }
1369
1370 /**
1371 * @brief Check if Address match interrupt is enabled or disabled.
1372 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1373 * @param I2Cx I2C Instance.
1374 * @retval State of bit (1 or 0).
1375 */
LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef * I2Cx)1376 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1377 {
1378 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @brief Enable Not acknowledge received interrupt.
1383 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1384 * @param I2Cx I2C Instance.
1385 * @retval None
1386 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1387 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1388 {
1389 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1390 }
1391
1392 /**
1393 * @brief Disable Not acknowledge received interrupt.
1394 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1395 * @param I2Cx I2C Instance.
1396 * @retval None
1397 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1398 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1399 {
1400 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1401 }
1402
1403 /**
1404 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1405 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1406 * @param I2Cx I2C Instance.
1407 * @retval State of bit (1 or 0).
1408 */
LL_I2C_IsEnabledIT_NACK(I2C_TypeDef * I2Cx)1409 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1410 {
1411 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @brief Enable STOP detection interrupt.
1416 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1417 * @param I2Cx I2C Instance.
1418 * @retval None
1419 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1420 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1421 {
1422 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1423 }
1424
1425 /**
1426 * @brief Disable STOP detection interrupt.
1427 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1428 * @param I2Cx I2C Instance.
1429 * @retval None
1430 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1431 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1432 {
1433 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1434 }
1435
1436 /**
1437 * @brief Check if STOP detection interrupt is enabled or disabled.
1438 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1439 * @param I2Cx I2C Instance.
1440 * @retval State of bit (1 or 0).
1441 */
LL_I2C_IsEnabledIT_STOP(I2C_TypeDef * I2Cx)1442 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1443 {
1444 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Enable Transfer Complete interrupt.
1449 * @note Any of these events will generate interrupt :
1450 * Transfer Complete (TC)
1451 * Transfer Complete Reload (TCR)
1452 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1453 * @param I2Cx I2C Instance.
1454 * @retval None
1455 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1456 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1457 {
1458 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1459 }
1460
1461 /**
1462 * @brief Disable Transfer Complete interrupt.
1463 * @note Any of these events will generate interrupt :
1464 * Transfer Complete (TC)
1465 * Transfer Complete Reload (TCR)
1466 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1467 * @param I2Cx I2C Instance.
1468 * @retval None
1469 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1470 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1471 {
1472 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1473 }
1474
1475 /**
1476 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1477 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1478 * @param I2Cx I2C Instance.
1479 * @retval State of bit (1 or 0).
1480 */
LL_I2C_IsEnabledIT_TC(I2C_TypeDef * I2Cx)1481 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1482 {
1483 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1484 }
1485
1486 /**
1487 * @brief Enable Error interrupts.
1488 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1489 * SMBus feature is supported by the I2Cx Instance.
1490 * @note Any of these errors will generate interrupt :
1491 * Arbitration Loss (ARLO)
1492 * Bus Error detection (BERR)
1493 * Overrun/Underrun (OVR)
1494 * SMBus Timeout detection (TIMEOUT)
1495 * SMBus PEC error detection (PECERR)
1496 * SMBus Alert pin event detection (ALERT)
1497 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1498 * @param I2Cx I2C Instance.
1499 * @retval None
1500 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1501 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1502 {
1503 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1504 }
1505
1506 /**
1507 * @brief Disable Error interrupts.
1508 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1509 * SMBus feature is supported by the I2Cx Instance.
1510 * @note Any of these errors will generate interrupt :
1511 * Arbitration Loss (ARLO)
1512 * Bus Error detection (BERR)
1513 * Overrun/Underrun (OVR)
1514 * SMBus Timeout detection (TIMEOUT)
1515 * SMBus PEC error detection (PECERR)
1516 * SMBus Alert pin event detection (ALERT)
1517 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1518 * @param I2Cx I2C Instance.
1519 * @retval None
1520 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1521 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1522 {
1523 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1524 }
1525
1526 /**
1527 * @brief Check if Error interrupts are enabled or disabled.
1528 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1529 * @param I2Cx I2C Instance.
1530 * @retval State of bit (1 or 0).
1531 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1532 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1533 {
1534 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1535 }
1536
1537 /**
1538 * @}
1539 */
1540
1541 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1542 * @{
1543 */
1544
1545 /**
1546 * @brief Indicate the status of Transmit data register empty flag.
1547 * @note RESET: When next data is written in Transmit data register.
1548 * SET: When Transmit data register is empty.
1549 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1550 * @param I2Cx I2C Instance.
1551 * @retval State of bit (1 or 0).
1552 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1554 {
1555 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1556 }
1557
1558 /**
1559 * @brief Indicate the status of Transmit interrupt flag.
1560 * @note RESET: When next data is written in Transmit data register.
1561 * SET: When Transmit data register is empty.
1562 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1563 * @param I2Cx I2C Instance.
1564 * @retval State of bit (1 or 0).
1565 */
LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef * I2Cx)1566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1567 {
1568 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1569 }
1570
1571 /**
1572 * @brief Indicate the status of Receive data register not empty flag.
1573 * @note RESET: When Receive data register is read.
1574 * SET: When the received data is copied in Receive data register.
1575 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1576 * @param I2Cx I2C Instance.
1577 * @retval State of bit (1 or 0).
1578 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1580 {
1581 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1582 }
1583
1584 /**
1585 * @brief Indicate the status of Address matched flag (slave mode).
1586 * @note RESET: Clear default value.
1587 * SET: When the received slave address matched with one of the enabled slave address.
1588 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1589 * @param I2Cx I2C Instance.
1590 * @retval State of bit (1 or 0).
1591 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1593 {
1594 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1595 }
1596
1597 /**
1598 * @brief Indicate the status of Not Acknowledge received flag.
1599 * @note RESET: Clear default value.
1600 * SET: When a NACK is received after a byte transmission.
1601 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1602 * @param I2Cx I2C Instance.
1603 * @retval State of bit (1 or 0).
1604 */
LL_I2C_IsActiveFlag_NACK(I2C_TypeDef * I2Cx)1605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1606 {
1607 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1608 }
1609
1610 /**
1611 * @brief Indicate the status of Stop detection flag.
1612 * @note RESET: Clear default value.
1613 * SET: When a Stop condition is detected.
1614 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1615 * @param I2Cx I2C Instance.
1616 * @retval State of bit (1 or 0).
1617 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1619 {
1620 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1621 }
1622
1623 /**
1624 * @brief Indicate the status of Transfer complete flag (master mode).
1625 * @note RESET: Clear default value.
1626 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1627 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1628 * @param I2Cx I2C Instance.
1629 * @retval State of bit (1 or 0).
1630 */
LL_I2C_IsActiveFlag_TC(I2C_TypeDef * I2Cx)1631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1632 {
1633 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1634 }
1635
1636 /**
1637 * @brief Indicate the status of Transfer complete flag (master mode).
1638 * @note RESET: Clear default value.
1639 * SET: When RELOAD=1 and NBYTES date have been transferred.
1640 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1641 * @param I2Cx I2C Instance.
1642 * @retval State of bit (1 or 0).
1643 */
LL_I2C_IsActiveFlag_TCR(I2C_TypeDef * I2Cx)1644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1645 {
1646 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Indicate the status of Bus error flag.
1651 * @note RESET: Clear default value.
1652 * SET: When a misplaced Start or Stop condition is detected.
1653 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1654 * @param I2Cx I2C Instance.
1655 * @retval State of bit (1 or 0).
1656 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1658 {
1659 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1660 }
1661
1662 /**
1663 * @brief Indicate the status of Arbitration lost flag.
1664 * @note RESET: Clear default value.
1665 * SET: When arbitration lost.
1666 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1667 * @param I2Cx I2C Instance.
1668 * @retval State of bit (1 or 0).
1669 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1670 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1671 {
1672 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1673 }
1674
1675 /**
1676 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1677 * @note RESET: Clear default value.
1678 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1679 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1680 * @param I2Cx I2C Instance.
1681 * @retval State of bit (1 or 0).
1682 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1683 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1684 {
1685 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1686 }
1687
1688 /**
1689 * @brief Indicate the status of SMBus PEC error flag in reception.
1690 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1691 * SMBus feature is supported by the I2Cx Instance.
1692 * @note RESET: Clear default value.
1693 * SET: When the received PEC does not match with the PEC register content.
1694 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1695 * @param I2Cx I2C Instance.
1696 * @retval State of bit (1 or 0).
1697 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1698 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1699 {
1700 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1701 }
1702
1703 /**
1704 * @brief Indicate the status of SMBus Timeout detection flag.
1705 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1706 * SMBus feature is supported by the I2Cx Instance.
1707 * @note RESET: Clear default value.
1708 * SET: When a timeout or extended clock timeout occurs.
1709 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1710 * @param I2Cx I2C Instance.
1711 * @retval State of bit (1 or 0).
1712 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1713 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1714 {
1715 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1716 }
1717
1718 /**
1719 * @brief Indicate the status of SMBus alert flag.
1720 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1721 * SMBus feature is supported by the I2Cx Instance.
1722 * @note RESET: Clear default value.
1723 * SET: When SMBus host configuration, SMBus alert enabled and
1724 * a falling edge event occurs on SMBA pin.
1725 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1726 * @param I2Cx I2C Instance.
1727 * @retval State of bit (1 or 0).
1728 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1729 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1730 {
1731 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1732 }
1733
1734 /**
1735 * @brief Indicate the status of Bus Busy flag.
1736 * @note RESET: Clear default value.
1737 * SET: When a Start condition is detected.
1738 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1739 * @param I2Cx I2C Instance.
1740 * @retval State of bit (1 or 0).
1741 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1742 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1743 {
1744 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1745 }
1746
1747 /**
1748 * @brief Clear Address Matched flag.
1749 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1750 * @param I2Cx I2C Instance.
1751 * @retval None
1752 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1753 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1754 {
1755 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1756 }
1757
1758 /**
1759 * @brief Clear Not Acknowledge flag.
1760 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1761 * @param I2Cx I2C Instance.
1762 * @retval None
1763 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1764 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1765 {
1766 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1767 }
1768
1769 /**
1770 * @brief Clear Stop detection flag.
1771 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1772 * @param I2Cx I2C Instance.
1773 * @retval None
1774 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1775 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1776 {
1777 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1778 }
1779
1780 /**
1781 * @brief Clear Transmit data register empty flag (TXE).
1782 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1783 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1784 * @param I2Cx I2C Instance.
1785 * @retval None
1786 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1787 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1788 {
1789 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1790 }
1791
1792 /**
1793 * @brief Clear Bus error flag.
1794 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1795 * @param I2Cx I2C Instance.
1796 * @retval None
1797 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1798 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1799 {
1800 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1801 }
1802
1803 /**
1804 * @brief Clear Arbitration lost flag.
1805 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1806 * @param I2Cx I2C Instance.
1807 * @retval None
1808 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1809 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1810 {
1811 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1812 }
1813
1814 /**
1815 * @brief Clear Overrun/Underrun flag.
1816 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1817 * @param I2Cx I2C Instance.
1818 * @retval None
1819 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1820 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1821 {
1822 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1823 }
1824
1825 /**
1826 * @brief Clear SMBus PEC error flag.
1827 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1828 * SMBus feature is supported by the I2Cx Instance.
1829 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1830 * @param I2Cx I2C Instance.
1831 * @retval None
1832 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1834 {
1835 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1836 }
1837
1838 /**
1839 * @brief Clear SMBus Timeout detection flag.
1840 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1841 * SMBus feature is supported by the I2Cx Instance.
1842 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1843 * @param I2Cx I2C Instance.
1844 * @retval None
1845 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1846 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1847 {
1848 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1849 }
1850
1851 /**
1852 * @brief Clear SMBus Alert flag.
1853 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
1854 * SMBus feature is supported by the I2Cx Instance.
1855 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1856 * @param I2Cx I2C Instance.
1857 * @retval None
1858 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1859 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1860 {
1861 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1862 }
1863
1864 /**
1865 * @}
1866 */
1867
1868 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1869 * @{
1870 */
1871
1872 /**
1873 * @brief Enable automatic STOP condition generation (master mode).
1874 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1875 * This bit has no effect in slave mode or when RELOAD bit is set.
1876 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1877 * @param I2Cx I2C Instance.
1878 * @retval None
1879 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1880 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1881 {
1882 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1883 }
1884
1885 /**
1886 * @brief Disable automatic STOP condition generation (master mode).
1887 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1888 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1889 * @param I2Cx I2C Instance.
1890 * @retval None
1891 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1892 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1893 {
1894 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1895 }
1896
1897 /**
1898 * @brief Check if automatic STOP condition is enabled or disabled.
1899 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1900 * @param I2Cx I2C Instance.
1901 * @retval State of bit (1 or 0).
1902 */
LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef * I2Cx)1903 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1904 {
1905 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
1906 }
1907
1908 /**
1909 * @brief Enable reload mode (master mode).
1910 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1911 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1912 * @param I2Cx I2C Instance.
1913 * @retval None
1914 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)1915 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1916 {
1917 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1918 }
1919
1920 /**
1921 * @brief Disable reload mode (master mode).
1922 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1923 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1924 * @param I2Cx I2C Instance.
1925 * @retval None
1926 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)1927 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1928 {
1929 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1930 }
1931
1932 /**
1933 * @brief Check if reload mode is enabled or disabled.
1934 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1935 * @param I2Cx I2C Instance.
1936 * @retval State of bit (1 or 0).
1937 */
LL_I2C_IsEnabledReloadMode(I2C_TypeDef * I2Cx)1938 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1939 {
1940 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
1941 }
1942
1943 /**
1944 * @brief Configure the number of bytes for transfer.
1945 * @note Changing these bits when START bit is set is not allowed.
1946 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1947 * @param I2Cx I2C Instance.
1948 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1949 * @retval None
1950 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)1951 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1952 {
1953 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1954 }
1955
1956 /**
1957 * @brief Get the number of bytes configured for transfer.
1958 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1959 * @param I2Cx I2C Instance.
1960 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1961 */
LL_I2C_GetTransferSize(I2C_TypeDef * I2Cx)1962 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1963 {
1964 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1965 }
1966
1967 /**
1968 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
1969 or next received byte.
1970 * @note Usage in Slave mode only.
1971 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1972 * @param I2Cx I2C Instance.
1973 * @param TypeAcknowledge This parameter can be one of the following values:
1974 * @arg @ref LL_I2C_ACK
1975 * @arg @ref LL_I2C_NACK
1976 * @retval None
1977 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)1978 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1979 {
1980 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1981 }
1982
1983 /**
1984 * @brief Generate a START or RESTART condition
1985 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1986 * This action has no effect when RELOAD is set.
1987 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1988 * @param I2Cx I2C Instance.
1989 * @retval None
1990 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)1991 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1992 {
1993 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1994 }
1995
1996 /**
1997 * @brief Generate a STOP condition after the current byte transfer (master mode).
1998 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1999 * @param I2Cx I2C Instance.
2000 * @retval None
2001 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2002 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2003 {
2004 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2005 }
2006
2007 /**
2008 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2009 * @note The master sends the complete 10bit slave address read sequence :
2010 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2011 in Read direction.
2012 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2013 * @param I2Cx I2C Instance.
2014 * @retval None
2015 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2016 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2017 {
2018 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2019 }
2020
2021 /**
2022 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2023 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2024 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2025 * @param I2Cx I2C Instance.
2026 * @retval None
2027 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2028 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2029 {
2030 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2031 }
2032
2033 /**
2034 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2035 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2036 * @param I2Cx I2C Instance.
2037 * @retval State of bit (1 or 0).
2038 */
LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef * I2Cx)2039 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
2040 {
2041 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2042 }
2043
2044 /**
2045 * @brief Configure the transfer direction (master mode).
2046 * @note Changing these bits when START bit is set is not allowed.
2047 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2048 * @param I2Cx I2C Instance.
2049 * @param TransferRequest This parameter can be one of the following values:
2050 * @arg @ref LL_I2C_REQUEST_WRITE
2051 * @arg @ref LL_I2C_REQUEST_READ
2052 * @retval None
2053 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2054 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2055 {
2056 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2057 }
2058
2059 /**
2060 * @brief Get the transfer direction requested (master mode).
2061 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2062 * @param I2Cx I2C Instance.
2063 * @retval Returned value can be one of the following values:
2064 * @arg @ref LL_I2C_REQUEST_WRITE
2065 * @arg @ref LL_I2C_REQUEST_READ
2066 */
LL_I2C_GetTransferRequest(I2C_TypeDef * I2Cx)2067 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2068 {
2069 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2070 }
2071
2072 /**
2073 * @brief Configure the slave address for transfer (master mode).
2074 * @note Changing these bits when START bit is set is not allowed.
2075 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2076 * @param I2Cx I2C Instance.
2077 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2078 * @retval None
2079 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2080 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2081 {
2082 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2083 }
2084
2085 /**
2086 * @brief Get the slave address programmed for transfer.
2087 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2088 * @param I2Cx I2C Instance.
2089 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2090 */
LL_I2C_GetSlaveAddr(I2C_TypeDef * I2Cx)2091 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2092 {
2093 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2094 }
2095
2096 /**
2097 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2098 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2099 * CR2 ADD10 LL_I2C_HandleTransfer\n
2100 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2101 * CR2 START LL_I2C_HandleTransfer\n
2102 * CR2 STOP LL_I2C_HandleTransfer\n
2103 * CR2 RELOAD LL_I2C_HandleTransfer\n
2104 * CR2 NBYTES LL_I2C_HandleTransfer\n
2105 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2106 * CR2 HEAD10R LL_I2C_HandleTransfer
2107 * @param I2Cx I2C Instance.
2108 * @param SlaveAddr Specifies the slave address to be programmed.
2109 * @param SlaveAddrSize This parameter can be one of the following values:
2110 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2111 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2112 * @param TransferSize Specifies the number of bytes to be programmed.
2113 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2114 * @param EndMode This parameter can be one of the following values:
2115 * @arg @ref LL_I2C_MODE_RELOAD
2116 * @arg @ref LL_I2C_MODE_AUTOEND
2117 * @arg @ref LL_I2C_MODE_SOFTEND
2118 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2119 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2120 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2121 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2122 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2123 * @param Request This parameter can be one of the following values:
2124 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2125 * @arg @ref LL_I2C_GENERATE_STOP
2126 * @arg @ref LL_I2C_GENERATE_START_READ
2127 * @arg @ref LL_I2C_GENERATE_START_WRITE
2128 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2129 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2130 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2131 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2132 * @retval None
2133 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2134 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2135 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2136 {
2137 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2138 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2139 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2140 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2141 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2142 }
2143
2144 /**
2145 * @brief Indicate the value of transfer direction (slave mode).
2146 * @note RESET: Write transfer, Slave enters in receiver mode.
2147 * SET: Read transfer, Slave enters in transmitter mode.
2148 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2149 * @param I2Cx I2C Instance.
2150 * @retval Returned value can be one of the following values:
2151 * @arg @ref LL_I2C_DIRECTION_WRITE
2152 * @arg @ref LL_I2C_DIRECTION_READ
2153 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)2154 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2155 {
2156 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2157 }
2158
2159 /**
2160 * @brief Return the slave matched address.
2161 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2162 * @param I2Cx I2C Instance.
2163 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2164 */
LL_I2C_GetAddressMatchCode(I2C_TypeDef * I2Cx)2165 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2166 {
2167 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2168 }
2169
2170 /**
2171 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2172 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
2173 * SMBus feature is supported by the I2Cx Instance.
2174 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2175 or an Address Matched is received.
2176 * This bit has no effect when RELOAD bit is set.
2177 * This bit has no effect in device mode when SBC bit is not set.
2178 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2179 * @param I2Cx I2C Instance.
2180 * @retval None
2181 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2182 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2183 {
2184 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2185 }
2186
2187 /**
2188 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2189 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
2190 * SMBus feature is supported by the I2Cx Instance.
2191 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2192 * @param I2Cx I2C Instance.
2193 * @retval State of bit (1 or 0).
2194 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)2195 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2196 {
2197 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2198 }
2199
2200 /**
2201 * @brief Get the SMBus Packet Error byte calculated.
2202 * @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
2203 * SMBus feature is supported by the I2Cx Instance.
2204 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2205 * @param I2Cx I2C Instance.
2206 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2207 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)2208 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2209 {
2210 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2211 }
2212
2213 /**
2214 * @brief Read Receive Data register.
2215 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2216 * @param I2Cx I2C Instance.
2217 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2218 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)2219 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2220 {
2221 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2222 }
2223
2224 /**
2225 * @brief Write in Transmit Data Register .
2226 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2227 * @param I2Cx I2C Instance.
2228 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2229 * @retval None
2230 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2231 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2232 {
2233 WRITE_REG(I2Cx->TXDR, Data);
2234 }
2235
2236 /**
2237 * @}
2238 */
2239
2240 #if defined(USE_FULL_LL_DRIVER)
2241 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2242 * @{
2243 */
2244
2245 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2246 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2247 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2248
2249
2250 /**
2251 * @}
2252 */
2253 #endif /* USE_FULL_LL_DRIVER */
2254
2255 /**
2256 * @}
2257 */
2258
2259 /**
2260 * @}
2261 */
2262
2263 #endif /* I2C1 || I2C2 || I2C3 */
2264
2265 /**
2266 * @}
2267 */
2268
2269 #ifdef __cplusplus
2270 }
2271 #endif
2272
2273 #endif /* STM32L0xx_LL_I2C_H */
2274
2275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2276
