1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L0xx_HAL_DMA_H 22 #define STM32L0xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l0xx_hal_def.h" 30 31 /** @addtogroup STM32L0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 }HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 }HAL_DMA_LevelCompleteTypeDef; 96 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 106 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 107 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 108 }HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 136 137 uint32_t ChannelIndex; /*!< DMA Channel Index */ 138 139 }DMA_HandleTypeDef; 140 141 /** 142 * @} 143 */ 144 145 /* Exported constants --------------------------------------------------------*/ 146 147 /** @defgroup DMA_Exported_Constants DMA Exported Constants 148 * @{ 149 */ 150 151 /** @defgroup DMA_Error_Code DMA Error Code 152 * @{ 153 */ 154 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 155 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 156 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 157 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 158 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 159 160 /** 161 * @} 162 */ 163 164 /** @defgroup DMA_request DMA request 165 * @{ 166 */ 167 168 #if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xC) 169 170 #define DMA_REQUEST_0 0U 171 #define DMA_REQUEST_1 1U 172 #define DMA_REQUEST_4 4U 173 #define DMA_REQUEST_5 5U 174 #define DMA_REQUEST_6 6U 175 #define DMA_REQUEST_8 8U 176 177 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 178 ((REQUEST) == DMA_REQUEST_1) || \ 179 ((REQUEST) == DMA_REQUEST_4) || \ 180 ((REQUEST) == DMA_REQUEST_5) || \ 181 ((REQUEST) == DMA_REQUEST_6) || \ 182 ((REQUEST) == DMA_REQUEST_8)) 183 184 /* STM32L010x4 || STM32L010x6 || STM32L010x8 || STM32L010xC */ 185 186 #elif defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 187 188 #define DMA_REQUEST_0 0U 189 #define DMA_REQUEST_1 1U 190 #define DMA_REQUEST_2 2U 191 #define DMA_REQUEST_3 3U 192 #define DMA_REQUEST_4 4U 193 #define DMA_REQUEST_5 5U 194 #define DMA_REQUEST_6 6U 195 #define DMA_REQUEST_7 7U 196 #define DMA_REQUEST_8 8U 197 #define DMA_REQUEST_9 9U 198 #define DMA_REQUEST_10 10U 199 #define DMA_REQUEST_11 11U /* AES product only */ 200 #define DMA_REQUEST_12 12U 201 #define DMA_REQUEST_13 13U 202 #define DMA_REQUEST_14 14U 203 #define DMA_REQUEST_15 15U 204 205 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 206 ((REQUEST) == DMA_REQUEST_1) || \ 207 ((REQUEST) == DMA_REQUEST_2) || \ 208 ((REQUEST) == DMA_REQUEST_3) || \ 209 ((REQUEST) == DMA_REQUEST_4) || \ 210 ((REQUEST) == DMA_REQUEST_5) || \ 211 ((REQUEST) == DMA_REQUEST_6) || \ 212 ((REQUEST) == DMA_REQUEST_7) || \ 213 ((REQUEST) == DMA_REQUEST_8) || \ 214 ((REQUEST) == DMA_REQUEST_9) || \ 215 ((REQUEST) == DMA_REQUEST_10) || \ 216 ((REQUEST) == DMA_REQUEST_11) || \ 217 ((REQUEST) == DMA_REQUEST_12) || \ 218 ((REQUEST) == DMA_REQUEST_13) || \ 219 ((REQUEST) == DMA_REQUEST_14) || \ 220 ((REQUEST) == DMA_REQUEST_15)) 221 222 /* (STM32L021xx) || (STM32L041xx) || (STM32L062xx) || (STM32L063xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */ 223 224 #else 225 226 #define DMA_REQUEST_0 0U 227 #define DMA_REQUEST_1 1U 228 #define DMA_REQUEST_2 2U 229 #define DMA_REQUEST_3 3U 230 #define DMA_REQUEST_4 4U 231 #define DMA_REQUEST_5 5U 232 #define DMA_REQUEST_6 6U 233 #define DMA_REQUEST_7 7U 234 #define DMA_REQUEST_8 8U 235 #define DMA_REQUEST_9 9U 236 #define DMA_REQUEST_10 10U 237 #define DMA_REQUEST_12 12U 238 #define DMA_REQUEST_13 13U 239 #define DMA_REQUEST_14 14U 240 #define DMA_REQUEST_15 15U 241 242 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 243 ((REQUEST) == DMA_REQUEST_1) || \ 244 ((REQUEST) == DMA_REQUEST_2) || \ 245 ((REQUEST) == DMA_REQUEST_3) || \ 246 ((REQUEST) == DMA_REQUEST_4) || \ 247 ((REQUEST) == DMA_REQUEST_5) || \ 248 ((REQUEST) == DMA_REQUEST_6) || \ 249 ((REQUEST) == DMA_REQUEST_7) || \ 250 ((REQUEST) == DMA_REQUEST_8) || \ 251 ((REQUEST) == DMA_REQUEST_9) || \ 252 ((REQUEST) == DMA_REQUEST_10) || \ 253 ((REQUEST) == DMA_REQUEST_12) || \ 254 ((REQUEST) == DMA_REQUEST_13) || \ 255 ((REQUEST) == DMA_REQUEST_14) || \ 256 ((REQUEST) == DMA_REQUEST_15)) 257 258 #endif /* (STM32L031xx) || (STM32L051xx) || (STM32L052xx) || (STM32L053xx) || (STM32L071xx) || (STM32L072xx) || (STM32L073xx) */ 259 260 261 262 /** 263 * @} 264 */ 265 266 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 267 * @{ 268 */ 269 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 270 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 271 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 277 * @{ 278 */ 279 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 280 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 281 /** 282 * @} 283 */ 284 285 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 286 * @{ 287 */ 288 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 289 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 295 * @{ 296 */ 297 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 298 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 299 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup DMA_Memory_data_size DMA Memory data size 305 * @{ 306 */ 307 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 308 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 309 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup DMA_mode DMA mode 315 * @{ 316 */ 317 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 318 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup DMA_Priority_level DMA Priority level 324 * @{ 325 */ 326 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 327 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 328 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 329 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 330 /** 331 * @} 332 */ 333 334 335 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 336 * @{ 337 */ 338 #define DMA_IT_TC DMA_CCR_TCIE 339 #define DMA_IT_HT DMA_CCR_HTIE 340 #define DMA_IT_TE DMA_CCR_TEIE 341 /** 342 * @} 343 */ 344 345 /** @defgroup DMA_flag_definitions DMA flag definitions 346 * @{ 347 */ 348 #define DMA_FLAG_GL1 DMA_ISR_GIF1 349 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 350 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 351 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 352 #define DMA_FLAG_GL2 DMA_ISR_GIF2 353 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 354 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 355 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 356 #define DMA_FLAG_GL3 DMA_ISR_GIF3 357 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 358 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 359 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 360 #define DMA_FLAG_GL4 DMA_ISR_GIF4 361 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 362 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 363 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 364 #define DMA_FLAG_GL5 DMA_ISR_GIF5 365 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 366 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 367 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 368 #define DMA_FLAG_GL6 DMA_ISR_GIF6 369 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 370 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 371 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 372 #define DMA_FLAG_GL7 DMA_ISR_GIF7 373 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 374 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 375 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 376 /** 377 * @} 378 */ 379 380 /** 381 * @} 382 */ 383 384 /* Exported macros -----------------------------------------------------------*/ 385 /** @defgroup DMA_Exported_Macros DMA Exported Macros 386 * @{ 387 */ 388 389 /** @brief Reset DMA handle state 390 * @param __HANDLE__ DMA handle 391 * @retval None 392 */ 393 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 394 395 /** 396 * @brief Enable the specified DMA Channel. 397 * @param __HANDLE__ DMA handle 398 * @retval None 399 */ 400 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 401 402 /** 403 * @brief Disable the specified DMA Channel. 404 * @param __HANDLE__ DMA handle 405 * @retval None 406 */ 407 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 408 409 410 /* Interrupt & Flag management */ 411 412 /** 413 * @brief Return the current DMA Channel transfer complete flag. 414 * @param __HANDLE__: DMA handle 415 * @retval The specified transfer complete flag index. 416 */ 417 418 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 419 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 420 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 421 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 422 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 423 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 424 DMA_FLAG_TC5) 425 #else 426 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 427 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 433 DMA_FLAG_TC7) 434 #endif 435 /** 436 * @brief Return the current DMA Channel half transfer complete flag. 437 * @param __HANDLE__ DMA handle 438 * @retval The specified half transfer complete flag index. 439 */ 440 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 441 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 442 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 446 DMA_FLAG_HT5) 447 #else 448 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 449 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 455 DMA_FLAG_HT7) 456 #endif 457 /** 458 * @brief Returns the current DMA Channel transfer error flag. 459 * @param __HANDLE__ DMA handle 460 * @retval The specified transfer error flag index. 461 */ 462 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 463 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 464 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 468 DMA_FLAG_TE5) 469 #else 470 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 477 DMA_FLAG_TE7) 478 #endif 479 /** 480 * @brief Returns the current DMA Channel Global interrupt flag. 481 * @param __HANDLE__ DMA handle 482 * @retval The specified transfer error flag index. 483 */ 484 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 485 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 486 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 490 DMA_ISR_GIF5) 491 #else 492 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 493 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 499 DMA_ISR_GIF7) 500 #endif 501 /** 502 * @brief Get the DMA Channel pending flags. 503 * @param __HANDLE__ DMA handle 504 * @param __FLAG__ Get the specified flag. 505 * This parameter can be any combination of the following values: 506 * @arg DMA_FLAG_TCIFx: Transfer complete flag 507 * @arg DMA_FLAG_HTIFx: Half transfer complete flag 508 * @arg DMA_FLAG_TEIFx: Transfer error flag 509 * @arg DMA_ISR_GIFx: Global interrupt flag 510 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 511 * @retval The state of FLAG (SET or RESET). 512 */ 513 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 514 515 /** 516 * @brief Clears the DMA Channel pending flags. 517 * @param __HANDLE__ DMA handle 518 * @param __FLAG__ specifies the flag to clear. 519 * This parameter can be any combination of the following values: 520 * @arg DMA_FLAG_TCx: Transfer complete flag 521 * @arg DMA_FLAG_HTx: Half transfer complete flag 522 * @arg DMA_FLAG_TEx: Transfer error flag 523 * @arg DMA_FLAG_GLx: Global interrupt flag 524 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. 525 * @retval None 526 */ 527 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) 528 529 /** 530 * @brief Enable the specified DMA Channel interrupts. 531 * @param __HANDLE__ DMA handle 532 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 533 * This parameter can be any combination of the following values: 534 * @arg DMA_IT_TC: Transfer complete interrupt mask 535 * @arg DMA_IT_HT: Half transfer complete interrupt mask 536 * @arg DMA_IT_TE: Transfer error interrupt mask 537 * @retval None 538 */ 539 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 540 541 /** 542 * @brief Disable the specified DMA Channel interrupts. 543 * @param __HANDLE__ DMA handle 544 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 545 * This parameter can be any combination of the following values: 546 * @arg DMA_IT_TC: Transfer complete interrupt mask 547 * @arg DMA_IT_HT: Half transfer complete interrupt mask 548 * @arg DMA_IT_TE: Transfer error interrupt mask 549 * @retval None 550 */ 551 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 552 553 /** 554 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 555 * @param __HANDLE__ DMA handle 556 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 557 * This parameter can be one of the following values: 558 * @arg DMA_IT_TC: Transfer complete interrupt mask 559 * @arg DMA_IT_HT: Half transfer complete interrupt mask 560 * @arg DMA_IT_TE: Transfer error interrupt mask 561 * @retval The state of DMA_IT (SET or RESET). 562 */ 563 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 564 565 /** 566 * @brief Return the number of remaining data units in the current DMA Channel transfer. 567 * @param __HANDLE__ DMA handle 568 * @retval The number of remaining data units in the current DMA Channel transfer. 569 */ 570 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 571 572 /** 573 * @} 574 */ 575 576 /* Exported functions --------------------------------------------------------*/ 577 578 /** @addtogroup DMA_Exported_Functions 579 * @{ 580 */ 581 582 /** @addtogroup DMA_Exported_Functions_Group1 583 * @{ 584 */ 585 /* Initialization and de-initialization functions *****************************/ 586 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 587 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 588 /** 589 * @} 590 */ 591 592 /** @addtogroup DMA_Exported_Functions_Group2 593 * @{ 594 */ 595 /* IO operation functions *****************************************************/ 596 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 597 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 598 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 599 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 600 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 601 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 602 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 603 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 604 605 /** 606 * @} 607 */ 608 609 /** @addtogroup DMA_Exported_Functions_Group3 610 * @{ 611 */ 612 /* Peripheral State and Error functions ***************************************/ 613 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 614 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 615 /** 616 * @} 617 */ 618 619 /** 620 * @} 621 */ 622 /* Define the private group ***********************************/ 623 /**************************************************************/ 624 /** @defgroup DMA_Private DMA Private 625 * @{ 626 */ 627 628 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 629 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 630 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 631 632 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 633 634 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 635 ((STATE) == DMA_PINC_DISABLE)) 636 637 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 638 ((STATE) == DMA_MINC_DISABLE)) 639 640 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 641 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 642 ((SIZE) == DMA_PDATAALIGN_WORD)) 643 644 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 645 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 646 ((SIZE) == DMA_MDATAALIGN_WORD )) 647 648 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 649 ((MODE) == DMA_CIRCULAR)) 650 651 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 652 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 653 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 654 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 655 656 /** 657 * @} 658 */ 659 /**************************************************************/ 660 661 /** 662 * @} 663 */ 664 665 /** 666 * @} 667 */ 668 669 #ifdef __cplusplus 670 } 671 #endif 672 673 #endif /* STM32L0xx_HAL_DMA_H */ 674 675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 676
