1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_PWR_EX_H 22 #define STM32H7xx_HAL_PWR_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup PWREx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup PWREx_Exported_Types PWREx Exported Types 41 * @{ 42 */ 43 /** 44 * @brief PWREx AVD configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This 49 parameter can be a value of @ref 50 PWREx_AVD_detection_level 51 */ 52 53 uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD 54 event. This parameter can be a value of @ref 55 PWREx_AVD_Mode. 56 */ 57 }PWREx_AVDTypeDef; 58 59 /** 60 * @brief PWREx Wakeup pin configuration structure definition 61 */ 62 typedef struct 63 { 64 uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. 65 This parameter can be a value of @ref 66 PWREx_WakeUp_Pins 67 */ 68 69 uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. 70 This parameter can be a value of @ref 71 PWREx_PIN_Polarity 72 */ 73 74 uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This 75 parameter can be a value of @ref 76 PWREx_PIN_Pull 77 */ 78 }PWREx_WakeupPinTypeDef; 79 80 #if defined (PWR_CSR1_MMCVDO) 81 /** 82 * @brief PWR VDDMMC voltage level enum definition 83 */ 84 typedef enum 85 { 86 PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ 87 PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ 88 } PWREx_MMC_VoltageLevel; 89 #endif /* defined (PWR_CSR1_MMCVDO) */ 90 91 /** 92 * @} 93 */ 94 95 /* Exported constants --------------------------------------------------------*/ 96 97 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants 98 * @{ 99 */ 100 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins 101 * @{ 102 */ 103 /* High level and No pull (default configuration) */ 104 #define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 105 #if defined (PWR_WKUPEPR_WKUPEN5) 106 #define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 107 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 108 #define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 109 #if defined (PWR_WKUPEPR_WKUPEN3) 110 #define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 111 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 112 #define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 113 #define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 114 115 /* High level and No pull */ 116 #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 117 #if defined (PWR_WKUPEPR_WKUPEN5) 118 #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 119 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 120 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 121 #if defined (PWR_WKUPEPR_WKUPEN3) 122 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 123 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 124 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 125 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 126 127 /* Low level and No pull */ 128 #define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) 129 #if defined (PWR_WKUPEPR_WKUPP5) 130 #define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) 131 #endif /* defined (PWR_WKUPEPR_WKUPP5) */ 132 #define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) 133 #if defined (PWR_WKUPEPR_WKUPP3) 134 #define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) 135 #endif /* defined (PWR_WKUPEPR_WKUPP3) */ 136 #define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) 137 #define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) 138 /** 139 * @} 140 */ 141 142 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration 143 * @{ 144 */ 145 #define PWR_PIN_POLARITY_HIGH (0x00000000U) 146 #define PWR_PIN_POLARITY_LOW (0x00000001U) 147 /** 148 * @} 149 */ 150 151 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration 152 * @{ 153 */ 154 #define PWR_PIN_NO_PULL (0x00000000U) 155 #define PWR_PIN_PULL_UP (0x00000001U) 156 #define PWR_PIN_PULL_DOWN (0x00000002U) 157 /** 158 * @} 159 */ 160 161 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. 162 * @{ 163 */ 164 #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ 165 #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ 166 #if defined (PWR_WKUPFR_WKUPF3) 167 #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ 168 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 169 #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ 170 #if defined (PWR_WKUPFR_WKUPF5) 171 #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ 172 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 173 #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ 174 #if defined (PWR_WKUPFR_WKUPF3) 175 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 176 PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ 177 PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) 178 #else 179 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ 180 PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) 181 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 182 /** 183 * @} 184 */ 185 186 #if defined (DUAL_CORE) 187 /** @defgroup PWREx_Core_Select PWREx Core definition 188 * @{ 189 */ 190 #define PWR_CORE_CPU1 (0x00000000U) 191 #define PWR_CORE_CPU2 (0x00000001U) 192 /** 193 * @} 194 */ 195 #endif /* defined (DUAL_CORE) */ 196 197 /** @defgroup PWREx_Domains PWREx Domains definition 198 * @{ 199 */ 200 #define PWR_D1_DOMAIN (0x00000000U) 201 #if defined (PWR_CPUCR_PDDS_D2) 202 #define PWR_D2_DOMAIN (0x00000001U) 203 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 204 #define PWR_D3_DOMAIN (0x00000002U) 205 /** 206 * @} 207 */ 208 209 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition 210 * @{ 211 */ 212 #if defined (DUAL_CORE) 213 #define PWR_D1_DOMAIN_FLAGS (0x00000000U) 214 #define PWR_D2_DOMAIN_FLAGS (0x00000001U) 215 #define PWR_ALL_DOMAIN_FLAGS (0x00000002U) 216 #else 217 #define PWR_CPU_FLAGS (0x00000000U) 218 #endif /* defined (DUAL_CORE) */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup PWREx_D3_State PWREx D3 Domain State 224 * @{ 225 */ 226 #define PWR_D3_DOMAIN_STOP (0x00000000U) 227 #define PWR_D3_DOMAIN_RUN (0x00000800U) 228 229 /** 230 * @} 231 */ 232 233 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration 234 * @{ 235 */ 236 #define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ 237 #if defined (SMPS) 238 #define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ 239 #define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ 240 #define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ 241 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 242 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 243 #define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ 244 #define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ 245 #endif /* defined (SMPS) */ 246 #define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ 247 248 #if defined (SMPS) 249 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ 250 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 251 #else 252 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) 253 #endif /* defined (SMPS) */ 254 /** 255 * @} 256 */ 257 258 259 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level 260 * @{ 261 */ 262 #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 263 selection : 1V7 */ 264 #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 265 selection : 2V1 */ 266 #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 267 selection : 2V5 */ 268 #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 269 selection : 2V8 */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode 275 * @{ 276 */ 277 #define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 278 #define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 279 #define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 280 #define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 281 #define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 282 #define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 283 #define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 284 /** 285 * @} 286 */ 287 288 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale 289 * @{ 290 */ 291 #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) 292 #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) 293 #define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) 294 /** 295 * @} 296 */ 297 298 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection 299 * @{ 300 */ 301 #define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ 302 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds 308 * @{ 309 */ 310 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 311 #define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL 312 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH 313 /** 314 * @} 315 */ 316 317 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds 318 * @{ 319 */ 320 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) 321 #define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL 322 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH 323 /** 324 * @} 325 */ 326 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 327 * @{ 328 */ 329 #define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 330 Connected to the AVD EXTI Line */ 331 /** 332 * @} 333 */ 334 335 #if defined (PWR_CR1_SRDRAMSO) 336 /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection 337 * @{ 338 */ 339 #define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ 340 #define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ 341 #define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ 342 #define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ 343 #define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ 344 #define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ 345 #define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ 346 #define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ 347 #define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ 348 #define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ 349 #define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ 350 /** 351 * @} 352 */ 353 #endif /* defined (PWR_CR1_SRDRAMSO) */ 354 /** 355 * @} 356 */ 357 358 /* Exported macro ------------------------------------------------------------*/ 359 360 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro 361 * @{ 362 */ 363 364 /** 365 * @brief Enable the AVD EXTI Line 16. 366 * @retval None. 367 */ 368 #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 369 370 #if defined (DUAL_CORE) 371 /** 372 * @brief Enable the AVD EXTI D2 Line 16. 373 * @retval None. 374 */ 375 #define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 376 #endif /* defined (DUAL_CORE) */ 377 378 /** 379 * @brief Disable the AVD EXTI Line 16 380 * @retval None. 381 */ 382 #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) 383 384 #if defined (DUAL_CORE) 385 /** 386 * @brief Disable the AVD EXTI D2 Line 16. 387 * @retval None. 388 */ 389 #define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) 390 #endif /* defined (DUAL_CORE) */ 391 392 /** 393 * @brief Enable event on AVD EXTI Line 16. 394 * @retval None. 395 */ 396 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 397 398 #if defined (DUAL_CORE) 399 /** 400 * @brief Enable event on AVD EXTI D2 Line 16. 401 * @retval None. 402 */ 403 #define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 404 #endif /* defined (DUAL_CORE) */ 405 406 /** 407 * @brief Disable event on AVD EXTI Line 16. 408 * @retval None. 409 */ 410 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) 411 412 #if defined (DUAL_CORE) 413 /** 414 * @brief Disable event on AVD EXTI D2 Line 16. 415 * @retval None. 416 */ 417 #define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) 418 #endif /* defined (DUAL_CORE) */ 419 420 /** 421 * @brief Enable the AVD Extended Interrupt Rising Trigger. 422 * @retval None. 423 */ 424 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 425 426 /** 427 * @brief Disable the AVD Extended Interrupt Rising Trigger. 428 * @retval None. 429 */ 430 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) 431 432 /** 433 * @brief Enable the AVD Extended Interrupt Falling Trigger. 434 * @retval None. 435 */ 436 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 437 438 /** 439 * @brief Disable the AVD Extended Interrupt Falling Trigger. 440 * @retval None. 441 */ 442 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) 443 444 /** 445 * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. 446 * @retval None. 447 */ 448 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 449 do { \ 450 __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ 451 __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ 452 } while(0); 453 454 /** 455 * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. 456 * @retval None. 457 */ 458 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 459 do { \ 460 __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ 461 __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ 462 } while(0); 463 464 /** 465 * @brief Check whether the specified AVD EXTI interrupt flag is set or not. 466 * @retval EXTI AVD Line Status. 467 */ 468 #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 469 470 #if defined (DUAL_CORE) 471 /** 472 * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. 473 * @retval EXTI D2 AVD Line Status. 474 */ 475 #define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) 476 #endif /* defined (DUAL_CORE) */ 477 478 /** 479 * @brief Clear the AVD EXTI flag. 480 * @retval None. 481 */ 482 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) 483 484 #if defined (DUAL_CORE) 485 /** 486 * @brief Clear the AVD EXTI D2 flag. 487 * @retval None. 488 */ 489 #define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) 490 #endif /* defined (DUAL_CORE) */ 491 492 /** 493 * @brief Generates a Software interrupt on AVD EXTI line. 494 * @retval None. 495 */ 496 #define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) 497 /** 498 * @} 499 */ 500 501 /* Exported functions --------------------------------------------------------*/ 502 503 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions 504 * @{ 505 */ 506 507 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions 508 * @{ 509 */ 510 HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); 511 uint32_t HAL_PWREx_GetSupplyConfig (void); 512 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); 513 uint32_t HAL_PWREx_GetVoltageRange (void); 514 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); 515 uint32_t HAL_PWREx_GetStopModeVoltageRange (void); 516 /** 517 * @} 518 */ 519 520 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions 521 * @{ 522 */ 523 /* System low power control functions */ 524 #if defined (PWR_CPUCR_RETDS_CD) 525 void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); 526 #endif /* defined (PWR_CPUCR_RETDS_CD) */ 527 void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); 528 void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); 529 void HAL_PWREx_ConfigD3Domain (uint32_t D3State); 530 /* Clear Cortex-Mx pending flag */ 531 void HAL_PWREx_ClearPendingEvent (void); 532 #if defined (DUAL_CORE) 533 /* Clear domain flags */ 534 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); 535 /* Core Hold/Release functions */ 536 HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); 537 void HAL_PWREx_ReleaseCore (uint32_t CPU); 538 #endif /* defined (DUAL_CORE) */ 539 /* Flash low power control functions */ 540 void HAL_PWREx_EnableFlashPowerDown (void); 541 void HAL_PWREx_DisableFlashPowerDown (void); 542 #if defined (PWR_CR1_SRDRAMSO) 543 /* Memory shut-off functions */ 544 void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); 545 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); 546 #endif /* defined(PWR_CR1_SRDRAMSO) */ 547 /* Wakeup Pins control functions */ 548 void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); 549 void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); 550 uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); 551 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); 552 /* Power Wakeup PIN IRQ Handler */ 553 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); 554 void HAL_PWREx_WKUP1_Callback (void); 555 void HAL_PWREx_WKUP2_Callback (void); 556 #if defined (PWR_WKUPEPR_WKUPEN3) 557 void HAL_PWREx_WKUP3_Callback (void); 558 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 559 void HAL_PWREx_WKUP4_Callback (void); 560 #if defined (PWR_WKUPEPR_WKUPEN5) 561 void HAL_PWREx_WKUP5_Callback (void); 562 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 563 void HAL_PWREx_WKUP6_Callback (void); 564 /** 565 * @} 566 */ 567 568 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions 569 * @{ 570 */ 571 /* Backup regulator control functions */ 572 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); 573 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); 574 /* USB regulator control functions */ 575 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); 576 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); 577 void HAL_PWREx_EnableUSBVoltageDetector (void); 578 void HAL_PWREx_DisableUSBVoltageDetector (void); 579 /* Battery control functions */ 580 void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); 581 void HAL_PWREx_DisableBatteryCharging (void); 582 #if defined (PWR_CR1_BOOSTE) 583 /* Analog Booster functions */ 584 void HAL_PWREx_EnableAnalogBooster (void); 585 void HAL_PWREx_DisableAnalogBooster (void); 586 #endif /* PWR_CR1_BOOSTE */ 587 /** 588 * @} 589 */ 590 591 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions 592 * @{ 593 */ 594 /* Power VBAT/Temperature monitoring functions */ 595 void HAL_PWREx_EnableMonitoring (void); 596 void HAL_PWREx_DisableMonitoring (void); 597 uint32_t HAL_PWREx_GetTemperatureLevel (void); 598 uint32_t HAL_PWREx_GetVBATLevel (void); 599 #if defined (PWR_CSR1_MMCVDO) 600 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); 601 #endif /* PWR_CSR1_MMCVDO */ 602 /* Power AVD configuration functions */ 603 void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); 604 void HAL_PWREx_EnableAVD (void); 605 void HAL_PWREx_DisableAVD (void); 606 /* Power PVD/AVD IRQ Handler */ 607 void HAL_PWREx_PVD_AVD_IRQHandler (void); 608 void HAL_PWREx_AVDCallback (void); 609 /** 610 * @} 611 */ 612 613 /** 614 * @} 615 */ 616 /* Private types -------------------------------------------------------------*/ 617 /* Private variables ---------------------------------------------------------*/ 618 /* Private constants ---------------------------------------------------------*/ 619 /* Private macros ------------------------------------------------------------*/ 620 /** @defgroup PWREx_Private_Macros PWREx Private Macros 621 * @{ 622 */ 623 624 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters 625 * @{ 626 */ 627 /* Check PWR regulator configuration parameter */ 628 #if defined (SMPS) 629 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 630 ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ 631 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ 632 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ 633 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ 634 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ 635 ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ 636 ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ 637 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 638 639 #else 640 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ 641 ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) 642 #endif /* defined (SMPS) */ 643 644 /* Check PWR regulator configuration in STOP mode parameter */ 645 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ 646 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ 647 ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) 648 649 /* Check PWR domain parameter */ 650 #if defined (PWR_CPUCR_PDDS_D2) 651 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 652 ((DOMAIN) == PWR_D2_DOMAIN) ||\ 653 ((DOMAIN) == PWR_D3_DOMAIN)) 654 #else 655 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ 656 ((DOMAIN) == PWR_D3_DOMAIN)) 657 #endif /* defined (PWR_CPUCR_PDDS_D2) */ 658 659 /* Check D3/SRD domain state parameter */ 660 #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ 661 ((STATE) == PWR_D3_DOMAIN_RUN)) 662 663 /* Check wake up pin parameter */ 664 #if defined (PWR_WKUPEPR_WKUPEN3) 665 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 666 ((PIN) == PWR_WAKEUP_PIN2) ||\ 667 ((PIN) == PWR_WAKEUP_PIN3) ||\ 668 ((PIN) == PWR_WAKEUP_PIN4) ||\ 669 ((PIN) == PWR_WAKEUP_PIN5) ||\ 670 ((PIN) == PWR_WAKEUP_PIN6) ||\ 671 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 672 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 673 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 674 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 675 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 676 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 677 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 678 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 679 ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ 680 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 681 ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ 682 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 683 #else 684 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ 685 ((PIN) == PWR_WAKEUP_PIN2) ||\ 686 ((PIN) == PWR_WAKEUP_PIN4) ||\ 687 ((PIN) == PWR_WAKEUP_PIN6) ||\ 688 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 689 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 690 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 691 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 692 ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ 693 ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 694 ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 695 ((PIN) == PWR_WAKEUP_PIN6_LOW)) 696 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 697 698 /* Check wake up pin polarity parameter */ 699 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ 700 ((POLARITY) == PWR_PIN_POLARITY_LOW)) 701 702 /* Check wake up pin pull configuration parameter */ 703 #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ 704 ((PULL) == PWR_PIN_PULL_UP) ||\ 705 ((PULL) == PWR_PIN_PULL_DOWN)) 706 707 /* Check wake up flag parameter */ 708 #if defined (PWR_WKUPEPR_WKUPEN3) 709 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 710 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 711 ((FLAG) == PWR_WAKEUP_FLAG3) ||\ 712 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 713 ((FLAG) == PWR_WAKEUP_FLAG5) ||\ 714 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 715 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 716 #else 717 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ 718 ((FLAG) == PWR_WAKEUP_FLAG2) ||\ 719 ((FLAG) == PWR_WAKEUP_FLAG4) ||\ 720 ((FLAG) == PWR_WAKEUP_FLAG6) ||\ 721 ((FLAG) == PWR_WAKEUP_FLAG_ALL)) 722 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 723 724 /* Check wake up flag parameter */ 725 #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ 726 ((LEVEL) == PWR_AVDLEVEL_1) ||\ 727 ((LEVEL) == PWR_AVDLEVEL_2) ||\ 728 ((LEVEL) == PWR_AVDLEVEL_3)) 729 730 /* Check AVD mode parameter */ 731 #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ 732 ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ 733 ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ 734 ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ 735 ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ 736 ((MODE) == PWR_AVD_MODE_NORMAL) ||\ 737 ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) 738 739 /* Check resistor battery parameter */ 740 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 741 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 742 /* Check D1/CD CPU ID parameter */ 743 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) 744 745 #if defined (DUAL_CORE) 746 /* Check CPU parameter */ 747 #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) 748 749 /* Check D2 CPU ID parameter */ 750 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) 751 752 /* Check PWR domain flag parameter */ 753 #define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ 754 ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ 755 ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) 756 #endif /* defined (DUAL_CORE) */ 757 758 #if defined (PWR_CR1_SRDRAMSO) 759 /* Check memory block parameter */ 760 #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ 761 ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ 762 ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ 763 ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ 764 ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ 765 ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ 766 ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ 767 ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ 768 ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) 769 #endif /* defined (PWR_CR1_SRDRAMSO) */ 770 /** 771 * @} 772 */ 773 /** 774 * @} 775 */ 776 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 #ifdef __cplusplus 785 } 786 #endif /* __cplusplus */ 787 788 789 #endif /* STM32H7xx_HAL_PWR_EX_H */ 790 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 792
