1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_HRTIM_H
22 #define STM32G4xx_LL_HRTIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (HRTIM1)
36
37 /** @defgroup HRTIM_LL HRTIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
44 * @{
45 */
46 static const uint16_t REG_OFFSET_TAB_TIMER[] =
47 {
48 0x00U, /* 0: MASTER */
49 0x80U, /* 1: TIMER A */
50 0x100U, /* 2: TIMER B */
51 0x180U, /* 3: TIMER C */
52 0x200U, /* 4: TIMER D */
53 0x280U, /* 5: TIMER E */
54 0x300U, /* 6: TIMER F */
55 };
56
57 static const uint8_t REG_OFFSET_TAB_ADCER[] =
58 {
59 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_ADC1R */
60 0x04U, /* LL_HRTIM_ADCTRIG_2: HRTIM_ADC2R */
61 0x08U, /* LL_HRTIM_ADCTRIG_3: HRTIM_ADC3R */
62 0x0CU, /* LL_HRTIM_ADCTRIG_4: HRTIM_ADC4R */
63 0x3CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCER */
64 0x3CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCER */
65 0x3CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCER */
66 0x3CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCER */
67 0x3CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCER */
68 0x3CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
69 };
70
71 static const uint8_t REG_OFFSET_TAB_ADCUR[] =
72 {
73 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_CR1 */
74 0x00U, /* LL_HRTIM_ADCTRIG_2: HRTIM_CR1 */
75 0x00U, /* LL_HRTIM_ADCTRIG_3: HRTIM_CR1 */
76 0x00U, /* LL_HRTIM_ADCTRIG_4: HRTIM_CR1 */
77 0x7CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCUR */
78 0x7CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCUR */
79 0x7CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCUR */
80 0x7CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCUR */
81 0x7CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCUR */
82 0x7CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
83 };
84
85 static const uint8_t REG_SHIFT_TAB_ADCER[] =
86 {
87 0, /* LL_HRTIM_ADCTRIG_1 */
88 0, /* LL_HRTIM_ADCTRIG_2 */
89 0, /* LL_HRTIM_ADCTRIG_3 */
90 0, /* LL_HRTIM_ADCTRIG_4 */
91 0, /* LL_HRTIM_ADCTRIG_5 */
92 5, /* LL_HRTIM_ADCTRIG_6 */
93 10, /* LL_HRTIM_ADCTRIG_7 */
94 16, /* LL_HRTIM_ADCTRIG_8 */
95 21, /* LL_HRTIM_ADCTRIG_9 */
96 26 /* LL_HRTIM_ADCTRIG_10 */
97 };
98
99 static const uint8_t REG_SHIFT_TAB_ADCUR[] =
100 {
101 16, /* LL_HRTIM_ADCTRIG_1 */
102 19, /* LL_HRTIM_ADCTRIG_2 */
103 22, /* LL_HRTIM_ADCTRIG_3 */
104 25, /* LL_HRTIM_ADCTRIG_4 */
105 0, /* LL_HRTIM_ADCTRIG_5 */
106 4, /* LL_HRTIM_ADCTRIG_6 */
107 8, /* LL_HRTIM_ADCTRIG_7 */
108 12, /* LL_HRTIM_ADCTRIG_8 */
109 16, /* LL_HRTIM_ADCTRIG_9 */
110 20 /* LL_HRTIM_ADCTRIG_10 */
111 };
112
113 static const uint32_t REG_MASK_TAB_ADCER[] =
114 {
115 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_1 */
116 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_2 */
117 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_3 */
118 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_4 */
119 0x0000001FU, /* LL_HRTIM_ADCTRIG_5 */
120 0x000003E0U, /* LL_HRTIM_ADCTRIG_6 */
121 0x00007C00U, /* LL_HRTIM_ADCTRIG_7 */
122 0x001F0000U, /* LL_HRTIM_ADCTRIG_8 */
123 0x03E00000U, /* LL_HRTIM_ADCTRIG_9 */
124 0x7C000000U /* LL_HRTIM_ADCTRIG_10 */
125 };
126
127 static const uint32_t REG_MASK_TAB_ADCUR[] =
128 {
129 0x00070000U, /* LL_HRTIM_ADCTRIG_1 */
130 0x00380000U, /* LL_HRTIM_ADCTRIG_2 */
131 0x01C00000U, /* LL_HRTIM_ADCTRIG_3 */
132 0x0E000000U, /* LL_HRTIM_ADCTRIG_4 */
133 0x00000007U, /* LL_HRTIM_ADCTRIG_5 */
134 0x00000070U, /* LL_HRTIM_ADCTRIG_6 */
135 0x00000700U, /* LL_HRTIM_ADCTRIG_7 */
136 0x00007000U, /* LL_HRTIM_ADCTRIG_8 */
137 0x00070000U, /* LL_HRTIM_ADCTRIG_9 */
138 0x00700000U /* LL_HRTIM_ADCTRIG_10 */
139 };
140
141 static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
142 {
143 0U, /* 0: HRTIM_ADC1R */
144 6U, /* 1: HRTIM_ADC2R */
145 12U, /* 2: HRTIM_ADC3R */
146 18U, /* 3: HRTIM_ADC4R */
147 24U, /* 4: HRTIM_ADC5R */
148 32U, /* 5: HRTIM_ADC6R */
149 38U, /* 6: HRTIM_ADC7R */
150 44U, /* 7: HRTIM_ADC8R */
151 50U, /* 8: HRTIM_ADC9R */
152 56U /* 9: HRTIM_ADC10R */
153 };
154
155 static const uint16_t REG_OFFSET_TAB_SETxR[] =
156 {
157 0x00U, /* 0: TA1 */
158 0x08U, /* 1: TA2 */
159 0x80U, /* 2: TB1 */
160 0x88U, /* 3: TB2 */
161 0x100U, /* 4: TC1 */
162 0x108U, /* 5: TC2 */
163 0x180U, /* 6: TD1 */
164 0x188U, /* 7: TD2 */
165 0x200U, /* 8: TE1 */
166 0x208U, /* 9: TE2 */
167 0x280U, /* 10: TF1 */
168 0x288U /* 11: TF2 */
169 };
170
171 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
172 {
173 0x00U, /* 0: TA1 */
174 0x00U, /* 1: TA2 */
175 0x80U, /* 2: TB1 */
176 0x80U, /* 3: TB2 */
177 0x100U, /* 4: TC1 */
178 0x100U, /* 5: TC2 */
179 0x180U, /* 6: TD1 */
180 0x180U, /* 7: TD2 */
181 0x200U, /* 8: TE1 */
182 0x200U, /* 9: TE2 */
183 0x280U, /* 10: TF1 */
184 0x280U /* 11: TF2 */
185 };
186
187 static const uint8_t REG_OFFSET_TAB_EECR[] =
188 {
189 0x00U, /* LL_HRTIM_EVENT_1 */
190 0x00U, /* LL_HRTIM_EVENT_2 */
191 0x00U, /* LL_HRTIM_EVENT_3 */
192 0x00U, /* LL_HRTIM_EVENT_4 */
193 0x00U, /* LL_HRTIM_EVENT_5 */
194 0x04U, /* LL_HRTIM_EVENT_6 */
195 0x04U, /* LL_HRTIM_EVENT_7 */
196 0x04U, /* LL_HRTIM_EVENT_8 */
197 0x04U, /* LL_HRTIM_EVENT_9 */
198 0x04U /* LL_HRTIM_EVENT_10 */
199 };
200
201 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
202 {
203 0x00U, /* LL_HRTIM_FAULT_1 */
204 0x00U, /* LL_HRTIM_FAULT_2 */
205 0x00U, /* LL_HRTIM_FAULT_3 */
206 0x00U, /* LL_HRTIM_FAULT_4 */
207 0x04U, /* LL_HRTIM_FAULT_5 */
208 0x04U /* LL_HRTIM_FAULT_6 */
209 };
210
211 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
212 {
213 0x20000000U, /* 0: MASTER */
214 0x01FF0000U, /* 1: TIMER A */
215 0x01FF0000U, /* 2: TIMER B */
216 0x01FF0000U, /* 3: TIMER C */
217 0x01FF0000U, /* 4: TIMER D */
218 0x01FF0000U, /* 5: TIMER E */
219 0x01FF0000U, /* 5: TIMER E */
220 0x01FF0000U /* 6: TIMER F */
221 };
222
223 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
224 {
225 12U, /* 0: MASTER */
226 0U, /* 1: TIMER A */
227 0U, /* 2: TIMER B */
228 0U, /* 3: TIMER C */
229 0U, /* 4: TIMER D */
230 0U, /* 5: TIMER E */
231 0U /* 6: TIMER F */
232 };
233
234 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
235 {
236 0U, /* LL_HRTIM_EVENT_1 */
237 6U, /* LL_HRTIM_EVENT_2 */
238 12U, /* LL_HRTIM_EVENT_3 */
239 18U, /* LL_HRTIM_EVENT_4 */
240 24U, /* LL_HRTIM_EVENT_5 */
241 0U, /* LL_HRTIM_EVENT_6 */
242 6U, /* LL_HRTIM_EVENT_7 */
243 12U, /* LL_HRTIM_EVENT_8 */
244 18U, /* LL_HRTIM_EVENT_9 */
245 24U /* LL_HRTIM_EVENT_10 */
246 };
247
248 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
249 {
250 HRTIM_MCR_BRSTDMA, /* 0: MASTER */
251 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
252 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
253 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
254 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
255 HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
256 HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
257 };
258
259 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
260 {
261 2U, /* 0: MASTER */
262 0U, /* 1: TIMER A */
263 0U, /* 2: TIMER B */
264 0U, /* 3: TIMER C */
265 0U, /* 4: TIMER D */
266 0U, /* 5: TIMER E */
267 0U /* 6: TIMER F */
268 };
269
270 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
271 {
272 0U, /* 0: TA1 */
273 16U, /* 1: TA2 */
274 0U, /* 2: TB1 */
275 16U, /* 3: TB2 */
276 0U, /* 4: TC1 */
277 16U, /* 5: TC2 */
278 0U, /* 6: TD1 */
279 16U, /* 7: TD2 */
280 0U, /* 8: TE1 */
281 16U, /* 9: TE2 */
282 0U, /* 10: TF1 */
283 16U /* 11: TF2 */
284 };
285
286 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
287 {
288 0U, /* 0: TA1 */
289 1U, /* 1: TA2 */
290 0U, /* 2: TB1 */
291 1U, /* 3: TB2 */
292 0U, /* 4: TC1 */
293 1U, /* 5: TC2 */
294 0U, /* 6: TD1 */
295 1U, /* 7: TD2 */
296 0U, /* 8: TE1 */
297 1U, /* 9: TE2 */
298 0U, /* 10: TF1 */
299 1U /* 11: TF2 */
300 };
301
302 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
303 {
304 0U, /* LL_HRTIM_FAULT_1 */
305 8U, /* LL_HRTIM_FAULT_2 */
306 16U, /* LL_HRTIM_FAULT_3 */
307 24U, /* LL_HRTIM_FAULT_4 */
308 0U, /* LL_HRTIM_FAULT_5 */
309 8U /* LL_HRTIM_FAULT_6 */
310 };
311
312 static const uint8_t REG_SHIFT_TAB_FLTxF[] =
313 {
314 0U, /* LL_HRTIM_FAULT_1 */
315 8U, /* LL_HRTIM_FAULT_2 */
316 16U, /* LL_HRTIM_FAULT_3 */
317 24U, /* LL_HRTIM_FAULT_4 */
318 32U, /* LL_HRTIM_FAULT_5 */
319 40U /* LL_HRTIM_FAULT_6 */
320 };
321
322 static const uint8_t REG_SHIFT_TAB_FLTx[] =
323 {
324 0, /* LL_HRTIM_FAULT_1 */
325 1, /* LL_HRTIM_FAULT_2 */
326 2, /* LL_HRTIM_FAULT_3 */
327 3, /* LL_HRTIM_FAULT_4 */
328 4, /* LL_HRTIM_FAULT_5 */
329 5 /* LL_HRTIM_FAULT_6 */
330 };
331
332 static const uint8_t REG_SHIFT_TAB_INTLVD[] =
333 {
334 0U, /* 0: MASTER */
335 1U, /* 1: TIMER A */
336 1U, /* 2: TIMER B */
337 1U, /* 3: TIMER C */
338 1U, /* 4: TIMER D */
339 1U, /* 5: TIMER E */
340 1U, /* 6: TIMER F */
341 };
342
343 static const uint32_t REG_MASK_TAB_INTLVD[] =
344 {
345 0x000000E0U, /* 0: MASTER */
346 0x000001A0U, /* 1: TIMER A */
347 0x000001A0U, /* 2: TIMER B */
348 0x000001A0U, /* 3: TIMER C */
349 0x000001A0U, /* 4: TIMER D */
350 0x000001A0U, /* 5: TIMER E */
351 0x000001A0U, /* 6: TIMER F */
352 };
353
354 static const uint8_t REG_SHIFT_TAB_CPT[] =
355 {
356 12U, /* 1: TIMER A */
357 16U, /* 2: TIMER B */
358 20U, /* 3: TIMER C */
359 24U, /* 4: TIMER D */
360 28U, /* 5: TIMER E */
361 32U, /* 6: TIMER F */
362 };
363
364 static const uint32_t REG_MASK_TAB_CPT[] =
365 {
366 0xFFFF0000U, /* 1: TIMER A */
367 0xFFF0F000U, /* 2: TIMER B */
368 0xFF0FF000U, /* 3: TIMER C */
369 0xF0FFF000U, /* 4: TIMER D */
370 0x0FFFF000U, /* 5: TIMER E */
371 0xFFFFF000U, /* 6: TIMER F */
372 };
373
374 /**
375 * @}
376 */
377
378
379 /* Private constants ---------------------------------------------------------*/
380 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
381 * @{
382 */
383 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
384 HRTIM_CR1_TAUDIS |\
385 HRTIM_CR1_TBUDIS |\
386 HRTIM_CR1_TCUDIS |\
387 HRTIM_CR1_TDUDIS |\
388 HRTIM_CR1_TEUDIS |\
389 HRTIM_CR1_TFUDIS))
390
391 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
392 HRTIM_CR2_TASWU |\
393 HRTIM_CR2_TBSWU |\
394 HRTIM_CR2_TCSWU |\
395 HRTIM_CR2_TDSWU |\
396 HRTIM_CR2_TESWU |\
397 HRTIM_CR2_TFSWU))
398
399 #define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
400 HRTIM_CR2_SWPB |\
401 HRTIM_CR2_SWPC |\
402 HRTIM_CR2_SWPD |\
403 HRTIM_CR2_SWPE |\
404 HRTIM_CR2_SWPF))
405
406 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
407 HRTIM_CR2_TARST |\
408 HRTIM_CR2_TBRST |\
409 HRTIM_CR2_TCRST |\
410 HRTIM_CR2_TDRST |\
411 HRTIM_CR2_TERST |\
412 HRTIM_CR2_TFRST))
413
414 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
415 HRTIM_OENR_TA2OEN |\
416 HRTIM_OENR_TB1OEN |\
417 HRTIM_OENR_TB2OEN |\
418 HRTIM_OENR_TC1OEN |\
419 HRTIM_OENR_TC2OEN |\
420 HRTIM_OENR_TD1OEN |\
421 HRTIM_OENR_TD2OEN |\
422 HRTIM_OENR_TE1OEN |\
423 HRTIM_OENR_TE2OEN |\
424 HRTIM_OENR_TF1OEN |\
425 HRTIM_OENR_TF2OEN))
426
427 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
428 HRTIM_ODISR_TA2ODIS |\
429 HRTIM_ODISR_TB1ODIS |\
430 HRTIM_ODISR_TB2ODIS |\
431 HRTIM_ODISR_TC1ODIS |\
432 HRTIM_ODISR_TC2ODIS |\
433 HRTIM_ODISR_TD1ODIS |\
434 HRTIM_ODISR_TD2ODIS |\
435 HRTIM_ODISR_TE1ODIS |\
436 HRTIM_ODISR_TE2ODIS |\
437 HRTIM_ODISR_TF1ODIS |\
438 HRTIM_ODISR_TF2ODIS))
439
440 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
441 HRTIM_OUTR_IDLM1 |\
442 HRTIM_OUTR_IDLES1 |\
443 HRTIM_OUTR_FAULT1 |\
444 HRTIM_OUTR_CHP1 |\
445 HRTIM_OUTR_DIDL1))
446
447 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
448 HRTIM_EECR1_EE1POL |\
449 HRTIM_EECR1_EE1SNS |\
450 HRTIM_EECR1_EE1FAST))
451
452 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
453 HRTIM_FLTINR1_FLT1SRC_0 ))
454
455 #define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
456 HRTIM_FLTINR2_FLT5SRC_1 |\
457 HRTIM_FLTINR2_FLT4SRC_1 |\
458 HRTIM_FLTINR2_FLT3SRC_1 |\
459 HRTIM_FLTINR2_FLT2SRC_1 |\
460 HRTIM_FLTINR2_FLT1SRC_1))
461
462 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
463 HRTIM_BMCR_BMCLK |\
464 HRTIM_BMCR_BMOM))
465
466 /**
467 * @}
468 */
469
470
471 /* Private macros ------------------------------------------------------------*/
472 /* Exported types ------------------------------------------------------------*/
473 /* Exported constants --------------------------------------------------------*/
474 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
475 * @{
476 */
477
478 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
479 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
480 * @{
481 */
482 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
483 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
484 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
485 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
486 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
487 #define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
488 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
489 #define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
490 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
491
492 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
493 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
494 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
495 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
496 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
497 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
498 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
499
500 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
501 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
502 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
503 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
504 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
505 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
506 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
507 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
508 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
509 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
510 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
511 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
512 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
513 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
514 /**
515 * @}
516 */
517
518 /** @defgroup HRTIM_LL_EC_IT IT Defines
519 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
520 * @{
521 */
522 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
523 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
524 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
525 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
526 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
527 #define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
528 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
529 #define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
530 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
531
532 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
533 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
534 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
535 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
536 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
537 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
538 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
539
540 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
541 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
542 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
543 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
544 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
545 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
546 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
547 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
548 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
549 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
550 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
551 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
552 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
553 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
554 /**
555 * @}
556 */
557
558 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
559 * @{
560 * @brief Constants defining defining the synchronization input source.
561 */
562 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
563 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
564 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
565 /**
566 * @}
567 */
568
569 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
570 * @{
571 * @brief Constants defining the source and event to be sent on the synchronization output.
572 */
573 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
574 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
575 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
576 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
577 /**
578 * @}
579 */
580
581 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
582 * @{
583 * @brief Constants defining the routing and conditioning of the synchronization output event.
584 */
585 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
586 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
587 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
588 /**
589 * @}
590 */
591
592 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
593 * @{
594 * @brief Constants identifying a timing unit.
595 */
596 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
597 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
598 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
599 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
600 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
601 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
602 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
603 #define LL_HRTIM_TIMER_F HRTIM_MCR_TFCEN /*!< Timer F identifier */
604
605 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
606 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
607 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
608 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
609
610 /**
611 * @}
612 */
613
614 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
615 * @{
616 * @brief Constants identifying an HRTIM output.
617 */
618 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
619 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
620 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
621 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
622 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
623 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
624 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
625 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
626 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
627 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
628 #define LL_HRTIM_OUTPUT_TF1 HRTIM_OENR_TF1OEN /*!< Timer F - Output 1 identifier */
629 #define LL_HRTIM_OUTPUT_TF2 HRTIM_OENR_TF2OEN /*!< Timer F - Output 2 identifier */
630 /**
631 * @}
632 */
633
634 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
635 * @{
636 * @brief Constants identifying a compare unit.
637 */
638 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
639 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
640 /**
641 * @}
642 */
643
644 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
645 * @{
646 * @brief Constants identifying a capture unit.
647 */
648 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
649 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
650 /**
651 * @}
652 */
653
654 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
655 * @{
656 * @brief Constants identifying a fault channel.
657 */
658 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
659 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
660 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
661 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
662 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
663 #define LL_HRTIM_FAULT_6 HRTIM_FLTR_FLT6EN /*!< Fault channel 6 identifier */
664 /**
665 * @}
666 */
667
668 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
669 * @{
670 * @brief Constants identifying an external event channel.
671 */
672 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
673 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
674 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
675 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
676 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
677 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
678 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
679 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
680 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
681 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
682 /**
683 * @}
684 */
685
686 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
687 * @{
688 * @brief Constants defining the state of an HRTIM output.
689 */
690 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
691 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
692 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
693 /**
694 * @}
695 */
696
697 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
698 * @{
699 * @brief Constants identifying an ADC trigger.
700 */
701 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
702 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
703 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
704 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
705 #define LL_HRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /*!< ADC trigger 5 identifier */
706 #define LL_HRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /*!< ADC trigger 6 identifier */
707 #define LL_HRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /*!< ADC trigger 7 identifier */
708 #define LL_HRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /*!< ADC trigger 8 identifier */
709 #define LL_HRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /*!< ADC trigger 9 identifier */
710 #define LL_HRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /*!< ADC trigger 10 identifier */
711 /**
712 * @}
713 */
714
715 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
716 * @{
717 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
718 */
719 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
720 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
721 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
722 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
723 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
724 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
725 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
726 /**
727 * @}
728 */
729
730 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
731 * @{
732 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
733 */
734 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
735 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
736 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
737 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
738 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
739 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
740 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
741 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
742 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
743 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
744 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
745 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
746 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
747 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
748 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
749 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
750 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
751 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
752 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
753 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
754 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
755 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
756 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
757 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
758 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
759 #define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
760 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
761 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
762 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
763 #define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
764 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
765 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
766 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
767 /**
768 * @}
769 */
770
771 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
772 * @{
773 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
774 */
775 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
776 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
777 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
778 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
779 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
780 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
781 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
782 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
783 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
784 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
785 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
786 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
787 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
788 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
789 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
790 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
791 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
792 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
793 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
794 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
795 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
796 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
797 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
798 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
799 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
800 #define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
801 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
802 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
803 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
804 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
805 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
806 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
807 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
808 /**
809 * @}
810 */
811
812 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
813 * @{
814 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
815 */
816 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
817 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
818 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
819 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
820 #define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
821 #define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
822 #define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
823 #define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
824 #define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
825 #define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
826 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
827 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
828 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
829 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
830 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
831 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
832 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
833 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
834 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
835 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
836 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
837 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
838 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
839 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
840 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
841 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
842 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
843 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
844 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
845 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
846 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
847 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
848 /**
849 * @}
850 */
851
852 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
853 * @{
854 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
855 */
856 #define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
857 #define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
858 #define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
859 #define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
860 #define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
861 #define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
862 #define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
863 #define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
864 #define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
865 #define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
866 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
867 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
868 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
869 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
870 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
871 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
872 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
873 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
874 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
875 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
876 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
877 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
878 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
879 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
880 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
881 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
882 #define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
883 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
884 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
885 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
886 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
887 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
888 /**
889 * @}
890 */
891
892 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
893 * @{
894 * @brief Constants defining the DLL calibration mode.
895 */
896 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is performed only once */
897 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
898 /**
899 * @}
900 */
901
902 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
903 * @{
904 * @brief Constants defining the DLL calibration periods (in micro seconds).
905 */
906 #define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
907 #define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
908 #define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
909 #define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
910 /**
911 * @}
912 */
913
914 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
915 * @{
916 * @brief Constants defining timer high-resolution clock prescaler ratio.
917 */
918 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
919 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
920 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
921 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
922 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
923 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
924 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
925 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
926 /**
927 * @}
928 */
929
930 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
931 * @{
932 * @brief Constants defining timer counter operating mode.
933 */
934 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
935 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
936 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
937 /**
938 * @}
939 */
940
941 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
942 * @{
943 * @brief Constants defining on which output the DAC synchronization event is sent.
944 */
945 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
946 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
947 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
948 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
949 /**
950 * @}
951 */
952
953 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
954 * @{
955 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
956 */
957 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
958 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
959 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
960 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
961 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
962 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
963 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
964 #define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
965 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
966 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
967 /**
968 * @}
969 */
970
971 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
972 * @{
973 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
974 */
975 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
976 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
977 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
978 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
979 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
980 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
981 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
982 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
983 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
984 /**
985 * @}
986 */
987
988 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
989 * @{
990 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
991 */
992 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
993 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
994 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
995 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
996 /**
997 * @}
998 */
999
1000 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
1001 * @{
1002 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
1003 */
1004 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
1005 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
1006 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
1007 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
1008 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
1009 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
1010 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
1011 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
1012 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
1013 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
1014 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
1015 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
1016 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
1017 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
1018 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
1019 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
1020 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
1021 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
1022 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
1023 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1024 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1025 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1026 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1027 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1028 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1029 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1030 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1031 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1032 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1033 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1034 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1035 #define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1036 #define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
1042 * @{
1043 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
1044 */
1045 #define LL_HRTIM_CAPTURETRIG_NONE (uint64_t)0 /*!< Capture trigger is disabled */
1046 #define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
1047 #define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
1048 #define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
1049 #define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
1050 #define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
1051 #define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
1052 #define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
1053 #define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
1054 #define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
1055 #define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
1056 #define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
1057 #define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
1058 #define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
1059 #define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
1060 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
1061 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
1062 #define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
1063 #define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
1064 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
1065 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
1066 #define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
1067 #define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
1068 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
1069 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
1070 #define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
1071 #define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
1072 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
1073 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
1074 #define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
1075 #define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
1076 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
1077 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
1078 #define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
1079 #define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
1080 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
1081 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
1087 * @{
1088 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
1089 */
1090 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
1091 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
1092 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
1093 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
1094 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
1095 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
1096 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
1097 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
1098
1099 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
1100 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
1101 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
1102 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
1103 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
1104 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
1105 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
1106 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
1107 /**
1108 * @}
1109 */
1110
1111 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
1112 * @{
1113 * @brief Constants defining how the timer behaves during a burst mode operation.
1114 */
1115 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
1116 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
1117 /**
1118 * @}
1119 */
1120
1121 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
1122 * @{
1123 * @brief Constants defining the registers that can be written during a burst DMA operation.
1124 */
1125 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
1126 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
1127 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
1128 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
1129 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
1130 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
1131 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
1132 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
1133 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
1134 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
1135 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
1136 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
1137 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
1138 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
1139 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
1140 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
1141 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
1142 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
1143 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
1144 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
1145 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
1146 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
1147 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
1148 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
1149 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
1150 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
1151 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
1152 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
1153 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
1154 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
1155 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
1156 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
1157 #define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
1158 #define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
1159 /**
1160 * @}
1161 */
1162
1163 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
1164 * @{
1165 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
1166 */
1167 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
1168 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
1169 /**
1170 * @}
1171 */
1172
1173 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
1174 * @{
1175 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
1176 */
1177 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1178 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1179 /**
1180 * @}
1181 */
1182
1183 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
1184 * @{
1185 * @brief Constants defining the event filtering applied to external events by a timer.
1186 */
1187 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
1188 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
1189 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
1190 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
1191 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
1192 /* Blanking Filter for TIMER A */
1193 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1194 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1195 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1196 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1197 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1198 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1199 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1200 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1201 /* Blanking Filter for TIMER B */
1202 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1203 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1204 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1205 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1206 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1207 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1208 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1209 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1210 /* Blanking Filter for TIMER C */
1211 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1212 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1213 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1214 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1215 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1216 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1217 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1218 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1219 /* Blanking Filter for TIMER D */
1220 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1221 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1222 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1223 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1224 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1225 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1226 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1227 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1228 /* Blanking Filter for TIMER E */
1229 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1230 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1231 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1232 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1233 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1234 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1235 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1236 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1237 /* Blanking Filter for TIMER F */
1238 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1239 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1240 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1241 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1242 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1243 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1244 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1245 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1246
1247 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
1248 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
1249 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
1250 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1251 /**
1252 * @}
1253 */
1254
1255 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
1256 * @{
1257 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
1258 */
1259 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
1260 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1261 /**
1262 * @}
1263 */
1264
1265 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
1266 * @{
1267 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
1268 */
1269 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
1270 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
1271 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
1272 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1273 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
1274 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
1275 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
1276 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
1282 * @{
1283 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
1284 */
1285 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
1286 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
1292 * @{
1293 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
1294 */
1295 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
1296 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1297 /**
1298 * @}
1299 */
1300
1301 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
1302 * @{
1303 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
1304 */
1305 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
1306 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
1307 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
1308 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1309 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
1310 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1311 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1312 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1313 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
1314 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1315 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1316 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1317 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1318 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1319 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1320 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1321 /**
1322 * @}
1323 */
1324
1325 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
1326 * @{
1327 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
1328 */
1329 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
1330 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
1331 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
1332 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
1333 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
1334 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
1335 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
1336 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
1337 /**
1338 * @}
1339 */
1340
1341 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
1342 * @{
1343 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
1344 */
1345 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
1346 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
1347 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
1348 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1349 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
1350 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1351 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1352 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1353 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
1354 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1355 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1356 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1357 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1358 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1359 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1360 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1361 /**
1362 * @}
1363 */
1364
1365 /** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
1366 * @{
1367 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1368 */
1369 #define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
1370 #define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
1371 #define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
1372 #define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
1373 #define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
1374 #define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
1375 #define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
1376 #define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
1377 #define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
1378 #define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
1379 #define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
1380 #define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
1381 /* Timer Events mapping for Timer A */
1382 #define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1383 #define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1384 #define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1385 #define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1386 #define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1387 #define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1388 #define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1389 #define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1390 #define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1391 /* Timer Events mapping for Timer B */
1392 #define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1393 #define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1394 #define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1395 #define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1396 #define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1397 #define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1398 #define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1399 #define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1400 #define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1401 /* Timer Events mapping for Timer C */
1402 #define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1403 #define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1404 #define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1405 #define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1406 #define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1407 #define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1408 #define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1409 #define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1410 #define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1411 /* Timer Events mapping for Timer D */
1412 #define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1413 #define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1414 #define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1415 #define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1416 #define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1417 #define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1418 #define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1419 #define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1420 #define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1421 /* Timer Events mapping for Timer E */
1422 #define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1423 #define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1424 #define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1425 #define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1426 #define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1427 #define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1428 #define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1429 #define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1430 #define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1431 /* Timer Events mapping for Timer F */
1432 #define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1433 #define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1434 #define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1435 #define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1436 #define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1437 #define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1438 #define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1439 #define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1440 #define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1441 #define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
1442 #define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
1443 #define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
1444 #define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
1445 #define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
1446 #define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
1447 #define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
1448 #define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
1449 #define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
1450 #define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
1451 #define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
1452 /**
1453 * @}
1454 */
1455
1456 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1457 * @{
1458 * @brief Constants defining the events that can be selected to configure the
1459 * set crossbar of a timer output
1460 */
1461 #define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
1462 #define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1463 #define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1464 #define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1465 #define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1466 #define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1467 #define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1468 #define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1469 #define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1470 #define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1471 #define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1472 #define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1473 /* Timer Events mapping for Timer A */
1474 #define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1475 #define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1476 #define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1477 #define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1478 #define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1479 #define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1480 #define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1481 #define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1482 #define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1483 /* Timer Events mapping for Timer B */
1484 #define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1485 #define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1486 #define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1487 #define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1488 #define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1489 #define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1490 #define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1491 #define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1492 #define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1493 /* Timer Events mapping for Timer C */
1494 #define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1495 #define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1496 #define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1497 #define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1498 #define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1499 #define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1500 #define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1501 #define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1502 #define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1503 /* Timer Events mapping for Timer D */
1504 #define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1505 #define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1506 #define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1507 #define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1508 #define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1509 #define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1510 #define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1511 #define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1512 #define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1513 /* Timer Events mapping for Timer E */
1514 #define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1515 #define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1516 #define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1517 #define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1518 #define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1519 #define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1520 #define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1521 #define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1522 #define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1523 /* Timer Events mapping for Timer F */
1524 #define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1525 #define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1526 #define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1527 #define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1528 #define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1529 #define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1530 #define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1531 #define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1532 #define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1533 #define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1534 #define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1535 #define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1536 #define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1537 #define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1538 #define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1539 #define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1540 #define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1541 #define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1542 #define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1543 #define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1544 /**
1545 * @}
1546 */
1547
1548 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1549 * @{
1550 * @brief Constants defining the polarity of a timer output.
1551 */
1552 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
1553 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1554 /**
1555 * @}
1556 */
1557
1558 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1559 * @{
1560 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1561 */
1562 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1563 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1564 /**
1565 * @}
1566 */
1567
1568 /** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
1569 * @{
1570 * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
1571 */
1572 #define LL_HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
1573 #define LL_HRTIM_INTERLEAVED_MODE_DUAL HRTIM_MCR_HALF /*!< HRTIM interleaved Mode is Dual */
1574 #define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
1575 #define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
1576 /**
1577 * @}
1578 */
1579 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1580 * @{
1581 * @brief Constants defining the half mode of an HRTIM Timer instance.
1582 */
1583 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
1584 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
1585 /**
1586 * @}
1587 */
1588
1589 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1590 * @{
1591 * @brief Constants defining the output level when output is in IDLE state
1592 */
1593 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1594 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1595 /**
1596 * @}
1597 */
1598
1599 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1600 * @{
1601 * @brief Constants defining the output level when output is in FAULT state.
1602 */
1603 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1604 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1605 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1606 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1607 /**
1608 * @}
1609 */
1610
1611 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1612 * @{
1613 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1614 */
1615 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
1616 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1617 /**
1618 * @}
1619 */
1620
1621 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1622 * @{
1623 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1624 during a programmable period before the output takes its idle state.
1625 */
1626 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1627 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1628 /**
1629 * @}
1630 */
1631 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1632 * @{
1633 * @brief Constants defining the level of a timer output.
1634 */
1635 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1636 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1637 /**
1638 * @}
1639 */
1640
1641 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1642 * @{
1643 * @brief Constants defining available sources associated to external events.
1644 */
1645 #define LL_HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 1 */
1646 #define LL_HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 2 */
1647 #define LL_HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 3 */
1648 #define LL_HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 4 */
1649 #define LL_HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 5 */
1650 #define LL_HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 6 */
1651 #define LL_HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 7 */
1652 #define LL_HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 8 */
1653 #define LL_HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 9 */
1654 #define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
1655 #define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
1656 #define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
1657 #define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
1658 #define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
1659 #define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
1660 #define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
1661 #define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
1662 #define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
1663 #define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
1664 #define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
1665 #define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
1666 #define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
1667 #define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
1668 #define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
1669 #define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
1670 #define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
1671 #define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
1672 #define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
1673 #define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
1674 #define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
1675 #define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
1676 #define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
1677 #define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
1678 #define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
1679 #define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
1680 #define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
1681 #define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
1682 #define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
1683 #define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
1684 #define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
1685 /**
1686 * @}
1687 */
1688 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1689 * @{
1690 * @brief Constants defining the polarity of an external event.
1691 */
1692 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
1693 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1694 /**
1695 * @}
1696 */
1697
1698 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1699 * @{
1700 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1701 */
1702 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
1703 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1704 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1705 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1706 /**
1707 * @}
1708 */
1709
1710 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1711 * @{
1712 * @brief Constants defining whether or not an external event is programmed in fast mode.
1713 */
1714 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1715 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1716 /**
1717 * @}
1718 */
1719
1720 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1721 * @{
1722 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1723 */
1724 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
1725 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
1726 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
1727 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1728 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
1729 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1730 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1731 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1732 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
1733 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1734 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1735 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1736 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1737 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1738 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1739 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1745 * @{
1746 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1747 */
1748 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
1749 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
1750 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
1751 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1752 /**
1753 * @}
1754 */
1755
1756 /** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
1757 * @{
1758 * @brief Constants defining the external event counter.
1759 */
1760 #define LL_HRTIM_EE_COUNTER_A ((uint32_t)0U) /*!< External Event A Counter */
1761 #define LL_HRTIM_EE_COUNTER_B ((uint32_t)16U) /*!< External Event B Counter */
1762 /**
1763 * @}
1764 */
1765
1766 /** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
1767 * @{
1768 * @brief Constants defining the external event reset mode.
1769 */
1770 #define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
1771 #define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
1772 /**
1773 * @}
1774 */
1775
1776 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1777 * @{
1778 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1779 */
1780 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
1781 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1782 #define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
1783 /**
1784 * @}
1785 */
1786
1787 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1788 * @{
1789 * @brief Constants defining the polarity of a fault event.
1790 */
1791 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
1792 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1793 /**
1794 * @}
1795 */
1796
1797 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1798 * @{
1799 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1800 */
1801 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
1802 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1803 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1804 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1805 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1806 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1807 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1808 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1809 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1810 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1811 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1812 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1813 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1814 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1815 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1816 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1817 /**
1818 * @}
1819 */
1820
1821 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1822 * @{
1823 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1824 */
1825 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
1826 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
1827 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
1828 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1829 /**
1830 * @}
1831 */
1832
1833 /** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
1834 * @{
1835 * @brief Constants defining the Blanking Source of a fault event.
1836 */
1837 #define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
1838 #define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
1839 /**
1840 * @}
1841 */
1842
1843 /** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
1844 * @{
1845 * @brief Constants defining the Counter RESet Mode of a fault event.
1846 */
1847 #define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
1848 #define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
1849 period. */
1850 /**
1851 * @}
1852 */
1853
1854 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1855 * @{
1856 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1857 */
1858 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1859 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1860 /**
1861 * @}
1862 */
1863
1864 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1865 * @{
1866 * @brief Constants defining the clock source for the burst mode counter.
1867 */
1868 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1869 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1870 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1871 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1872 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1873 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1874 #define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
1875 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1876 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1877 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1878 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1879 /**
1880 * @}
1881 */
1882
1883 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1884 * @{
1885 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1886 */
1887 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
1888 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
1889 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
1890 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1891 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
1892 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1893 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1894 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1895 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
1896 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1897 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1898 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1899 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1900 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1901 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1902 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1903 /**
1904 * @}
1905 */
1906
1907 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1908 * @{
1909 * @brief Constants defining the events that can be used to trig the burst mode operation.
1910 */
1911 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
1912 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1913 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1914 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1915 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1916 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1917 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1918 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1919 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1920 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1921 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1922 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1923 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1924 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1925 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1926 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1927 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1928 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1929 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1930 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1931 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1932 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1933 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1934 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1935 #define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
1936 #define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
1937 #define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
1938 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1939 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1940 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1941 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1942 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1943 /**
1944 * @}
1945 */
1946
1947 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1948 * @{
1949 * @brief Constants defining the operating state of the burst mode controller.
1950 */
1951 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
1952 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
1953 /**
1954 * @}
1955 */
1956
1957 /** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
1958 * @{
1959 * @brief Constants defining the Counter Up Down Mode.
1960 */
1961 #define LL_HRTIM_COUNTING_MODE_UP 0x00000000U /*!< counter is operating in up-counting mode */
1962 #define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
1963 /**
1964 * @}
1965 */
1966
1967 /** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
1968 * @{
1969 * @brief Constants defining the Roll-Over counter Mode.
1970 */
1971 #define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
1972 #define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
1973 #define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
1974 /**
1975 * @}
1976 */
1977
1978 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
1979 * @{
1980 * @brief Constants defining how the timer counter operates.
1981 */
1982 #define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
1983 #define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
1984 /**
1985 * @}
1986 */
1987
1988 /** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
1989 * @{
1990 * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
1991 */
1992 #define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
1993 #define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
1994 #define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
1995 #define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
1996 /**
1997 * @}
1998 */
1999
2000 /** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
2001 * @{
2002 * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
2003 */
2004 #define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2005 #define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
2006 /**
2007 * @}
2008 */
2009
2010 /** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
2011 * @{
2012 * @brief Constants defining the Dual Channel DAC Reset trigger.
2013 */
2014 #define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2015 #define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
2016 /**
2017 * @}
2018 */
2019
2020 /** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
2021 * @{
2022 * @brief Constants defining the Dual Channel DAC Step trigger.
2023 */
2024 #define LL_HRTIM_DCDS_CMP2 0x00000000U /*!< trigger is generated on compare 2 event */
2025 #define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
2026 /**
2027 * @}
2028 */
2029
2030 /**
2031 * @}
2032 */
2033
2034 /* Exported macro ------------------------------------------------------------*/
2035 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
2036 * @{
2037 */
2038
2039 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
2040 * @{
2041 */
2042
2043 /**
2044 * @brief Write a value in HRTIM register
2045 * @param __INSTANCE__ HRTIM Instance
2046 * @param __REG__ Register to be written
2047 * @param __VALUE__ Value to be written in the register
2048 * @retval None
2049 */
2050 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2051
2052 /**
2053 * @brief Read a value in HRTIM register
2054 * @param __INSTANCE__ HRTIM Instance
2055 * @param __REG__ Register to be read
2056 * @retval Register value
2057 */
2058 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2059 /**
2060 * @}
2061 */
2062
2063 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
2064 * @{
2065 */
2066 /**
2067 * @brief HELPER macro returning the output state from output enable/disable status
2068 * @param __OUTPUT_STATUS_EN__ output enable status
2069 * @param __OUTPUT_STATUS_DIS__ output Disable status
2070 * @retval Returned value can be one of the following values:
2071 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
2072 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
2073 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
2074 */
2075 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
2076 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
2077 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
2078 /**
2079 * @}
2080 */
2081
2082 /**
2083 * @}
2084 */
2085
2086 /* Exported functions --------------------------------------------------------*/
2087 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
2088 * @{
2089 */
2090 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
2091 * @{
2092 */
2093
2094 /**
2095 * @brief Select the HRTIM synchronization input source.
2096 * @note This function must not be called when the concerned timer(s) is (are) enabled .
2097 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2098 * @param HRTIMx High Resolution Timer instance
2099 * @param SyncInSrc This parameter can be one of the following values:
2100 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2101 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2102 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2103 * @retval None
2104 */
LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncInSrc)2105 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
2106 {
2107 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
2108 }
2109
2110 /**
2111 * @brief Get actual HRTIM synchronization input source.
2112 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2113 * @param HRTIMx High Resolution Timer instance
2114 * @retval SyncInSrc Returned value can be one of the following values:
2115 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2116 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2117 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2118 */
LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef * HRTIMx)2119 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
2120 {
2121 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
2122 }
2123
2124 /**
2125 * @brief Configure the HRTIM synchronization output.
2126 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
2127 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
2128 * @param HRTIMx High Resolution Timer instance
2129 * @param Config This parameter can be one of the following values:
2130 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2131 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2132 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2133 * @param Src This parameter can be one of the following values:
2134 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2135 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2136 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2137 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2138 * @retval None
2139 */
LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef * HRTIMx,uint32_t Config,uint32_t Src)2140 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
2141 {
2142 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
2143 }
2144
2145 /**
2146 * @brief Set the routing and conditioning of the synchronization output event.
2147 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
2148 * @note This function can be called only when the master timer is enabled.
2149 * @param HRTIMx High Resolution Timer instance
2150 * @param SyncOutConfig This parameter can be one of the following values:
2151 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2152 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2153 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2154 * @retval None
2155 */
LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutConfig)2156 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
2157 {
2158 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
2159 }
2160
2161 /**
2162 * @brief Get actual routing and conditioning of the synchronization output event.
2163 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
2164 * @param HRTIMx High Resolution Timer instance
2165 * @retval SyncOutConfig Returned value can be one of the following values:
2166 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2167 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2168 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2169 */
LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef * HRTIMx)2170 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
2171 {
2172 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
2173 }
2174
2175 /**
2176 * @brief Set the source and event to be sent on the HRTIM synchronization output.
2177 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
2178 * @param HRTIMx High Resolution Timer instance
2179 * @param SyncOutSrc This parameter can be one of the following values:
2180 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2181 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2182 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2183 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2184 * @retval None
2185 */
LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutSrc)2186 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
2187 {
2188 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
2189 }
2190
2191 /**
2192 * @brief Get actual source and event sent on the HRTIM synchronization output.
2193 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
2194 * @param HRTIMx High Resolution Timer instance
2195 * @retval SyncOutSrc Returned value can be one of the following values:
2196 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2197 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2198 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2199 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2200 */
LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef * HRTIMx)2201 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
2202 {
2203 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
2204 }
2205
2206 /**
2207 * @brief Disable (temporarily) update event generation.
2208 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
2209 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
2210 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
2211 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
2212 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
2213 * CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
2214 * CR1 TFUDIS LL_HRTIM_SuspendUpdate
2215 * @note Allow to temporarily disable the transfer from preload to active
2216 * registers, whatever the selected update event. This allows to modify
2217 * several registers in multiple timers.
2218 * @param HRTIMx High Resolution Timer instance
2219 * @param Timers This parameter can be a combination of the following values:
2220 * @arg @ref LL_HRTIM_TIMER_MASTER
2221 * @arg @ref LL_HRTIM_TIMER_A
2222 * @arg @ref LL_HRTIM_TIMER_B
2223 * @arg @ref LL_HRTIM_TIMER_C
2224 * @arg @ref LL_HRTIM_TIMER_D
2225 * @arg @ref LL_HRTIM_TIMER_E
2226 * @arg @ref LL_HRTIM_TIMER_F
2227 * @retval None
2228 */
LL_HRTIM_SuspendUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2229 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2230 {
2231 /* clear register before applying the new value */
2232 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2233 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2234 }
2235
2236 /**
2237 * @brief Enable update event generation.
2238 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
2239 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
2240 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
2241 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
2242 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
2243 * CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
2244 * CR1 TFUDIS LL_HRTIM_ResumeUpdate
2245 * @note The regular update event takes place.
2246 * @param HRTIMx High Resolution Timer instance
2247 * @param Timers This parameter can be a combination of the following values:
2248 * @arg @ref LL_HRTIM_TIMER_MASTER
2249 * @arg @ref LL_HRTIM_TIMER_A
2250 * @arg @ref LL_HRTIM_TIMER_B
2251 * @arg @ref LL_HRTIM_TIMER_C
2252 * @arg @ref LL_HRTIM_TIMER_D
2253 * @arg @ref LL_HRTIM_TIMER_E
2254 * @arg @ref LL_HRTIM_TIMER_F
2255 * @retval None
2256 */
LL_HRTIM_ResumeUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2257 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2258 {
2259 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2260 }
2261
2262 /**
2263 * @brief Force an immediate transfer from the preload to the active register .
2264 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
2265 * CR2 TASWU LL_HRTIM_ForceUpdate\n
2266 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
2267 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
2268 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
2269 * CR2 TESWU LL_HRTIM_ForceUpdate\n
2270 * CR2 TFSWU LL_HRTIM_ForceUpdate
2271 * @note Any pending update request is cancelled.
2272 * @param HRTIMx High Resolution Timer instance
2273 * @param Timers This parameter can be a combination of the following values:
2274 * @arg @ref LL_HRTIM_TIMER_MASTER
2275 * @arg @ref LL_HRTIM_TIMER_A
2276 * @arg @ref LL_HRTIM_TIMER_B
2277 * @arg @ref LL_HRTIM_TIMER_C
2278 * @arg @ref LL_HRTIM_TIMER_D
2279 * @arg @ref LL_HRTIM_TIMER_E
2280 * @arg @ref LL_HRTIM_TIMER_F
2281 * @retval None
2282 */
LL_HRTIM_ForceUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2283 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2284 {
2285 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
2286 }
2287
2288 /**
2289 * @brief Reset the HRTIM timer(s) counter.
2290 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
2291 * CR2 TARST LL_HRTIM_CounterReset\n
2292 * CR2 TBRST LL_HRTIM_CounterReset\n
2293 * CR2 TCRST LL_HRTIM_CounterReset\n
2294 * CR2 TDRST LL_HRTIM_CounterReset\n
2295 * CR2 TERST LL_HRTIM_CounterReset\n
2296 * CR2 TFRST LL_HRTIM_CounterReset
2297 * @param HRTIMx High Resolution Timer instance
2298 * @param Timers This parameter can be a combination of the following values:
2299 * @arg @ref LL_HRTIM_TIMER_MASTER
2300 * @arg @ref LL_HRTIM_TIMER_A
2301 * @arg @ref LL_HRTIM_TIMER_B
2302 * @arg @ref LL_HRTIM_TIMER_C
2303 * @arg @ref LL_HRTIM_TIMER_D
2304 * @arg @ref LL_HRTIM_TIMER_E
2305 * @arg @ref LL_HRTIM_TIMER_F
2306 * @retval None
2307 */
LL_HRTIM_CounterReset(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2308 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2309 {
2310 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
2311 }
2312
2313 /**
2314 * @brief enable the swap of the Timer Output.
2315 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2316 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2317 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2318 * @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
2319 * CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
2320 * CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
2321 * CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
2322 * CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
2323 * CR2 SWPF LL_HRTIM_EnableSwapOutputs
2324 * @param HRTIMx High Resolution Timer instance
2325 * @param Timer This parameter can be one of the following values:
2326 * @arg @ref LL_HRTIM_TIMER_A
2327 * @arg @ref LL_HRTIM_TIMER_B
2328 * @arg @ref LL_HRTIM_TIMER_C
2329 * @arg @ref LL_HRTIM_TIMER_D
2330 * @arg @ref LL_HRTIM_TIMER_E
2331 * @arg @ref LL_HRTIM_TIMER_F
2332 * @retval None
2333 */
LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2334 __STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2335 {
2336 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2337
2338 SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
2339 }
2340
2341 /**
2342 * @brief disable the swap of the Timer Output.
2343 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2344 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2345 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2346 * @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
2347 * CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
2348 * CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
2349 * CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
2350 * CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
2351 * CR2 SWPF LL_HRTIM_DisableSwapOutputs
2352 * @param HRTIMx High Resolution Timer instance
2353 * @param Timer This parameter can be one of the following values:
2354 * @arg @ref LL_HRTIM_TIMER_A
2355 * @arg @ref LL_HRTIM_TIMER_B
2356 * @arg @ref LL_HRTIM_TIMER_C
2357 * @arg @ref LL_HRTIM_TIMER_D
2358 * @arg @ref LL_HRTIM_TIMER_E
2359 * @arg @ref LL_HRTIM_TIMER_F
2360 * @retval None
2361 */
LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2362 __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2363 {
2364 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2365
2366 CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
2367 }
2368
2369 /**
2370 * @brief reports the Timer Outputs swap position.
2371 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2372 * @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
2373 * CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
2374 * CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
2375 * CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
2376 * CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
2377 * CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
2378 * @param HRTIMx High Resolution Timer instance
2379 * @param Timer This parameter can be one of the following values:
2380 * @arg @ref LL_HRTIM_TIMER_A
2381 * @arg @ref LL_HRTIM_TIMER_B
2382 * @arg @ref LL_HRTIM_TIMER_C
2383 * @arg @ref LL_HRTIM_TIMER_D
2384 * @arg @ref LL_HRTIM_TIMER_E
2385 * @arg @ref LL_HRTIM_TIMER_F
2386 * @retval
2387 * 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2388 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2389 * 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2390 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2391 */
LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2392 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2393 {
2394 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
2395
2396 return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
2397 }
2398
2399 /**
2400 * @brief Enable the HRTIM timer(s) output(s) .
2401 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
2402 * OENR TA2OEN LL_HRTIM_EnableOutput\n
2403 * OENR TB1OEN LL_HRTIM_EnableOutput\n
2404 * OENR TB2OEN LL_HRTIM_EnableOutput\n
2405 * OENR TC1OEN LL_HRTIM_EnableOutput\n
2406 * OENR TC2OEN LL_HRTIM_EnableOutput\n
2407 * OENR TD1OEN LL_HRTIM_EnableOutput\n
2408 * OENR TD2OEN LL_HRTIM_EnableOutput\n
2409 * OENR TE1OEN LL_HRTIM_EnableOutput\n
2410 * OENR TE2OEN LL_HRTIM_EnableOutput\n
2411 * OENR TF1OEN LL_HRTIM_EnableOutput\n
2412 * OENR TF2OEN LL_HRTIM_EnableOutput
2413 * @param HRTIMx High Resolution Timer instance
2414 * @param Outputs This parameter can be a combination of the following values:
2415 * @arg @ref LL_HRTIM_OUTPUT_TA1
2416 * @arg @ref LL_HRTIM_OUTPUT_TA2
2417 * @arg @ref LL_HRTIM_OUTPUT_TB1
2418 * @arg @ref LL_HRTIM_OUTPUT_TB2
2419 * @arg @ref LL_HRTIM_OUTPUT_TC1
2420 * @arg @ref LL_HRTIM_OUTPUT_TC2
2421 * @arg @ref LL_HRTIM_OUTPUT_TD1
2422 * @arg @ref LL_HRTIM_OUTPUT_TD2
2423 * @arg @ref LL_HRTIM_OUTPUT_TE1
2424 * @arg @ref LL_HRTIM_OUTPUT_TE2
2425 * @arg @ref LL_HRTIM_OUTPUT_TF1
2426 * @arg @ref LL_HRTIM_OUTPUT_TF2
2427 * @retval None
2428 */
LL_HRTIM_EnableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2429 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2430 {
2431 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
2432 }
2433
2434 /**
2435 * @brief Disable the HRTIM timer(s) output(s) .
2436 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
2437 * OENR TA2OEN LL_HRTIM_DisableOutput\n
2438 * OENR TB1OEN LL_HRTIM_DisableOutput\n
2439 * OENR TB2OEN LL_HRTIM_DisableOutput\n
2440 * OENR TC1OEN LL_HRTIM_DisableOutput\n
2441 * OENR TC2OEN LL_HRTIM_DisableOutput\n
2442 * OENR TD1OEN LL_HRTIM_DisableOutput\n
2443 * OENR TD2OEN LL_HRTIM_DisableOutput\n
2444 * OENR TE1OEN LL_HRTIM_DisableOutput\n
2445 * OENR TE2OEN LL_HRTIM_DisableOutput\n
2446 * OENR TF1OEN LL_HRTIM_DisableOutput\n
2447 * OENR TF2OEN LL_HRTIM_DisableOutput
2448 * @param HRTIMx High Resolution Timer instance
2449 * @param Outputs This parameter can be a combination of the following values:
2450 * @arg @ref LL_HRTIM_OUTPUT_TA1
2451 * @arg @ref LL_HRTIM_OUTPUT_TA2
2452 * @arg @ref LL_HRTIM_OUTPUT_TB1
2453 * @arg @ref LL_HRTIM_OUTPUT_TB2
2454 * @arg @ref LL_HRTIM_OUTPUT_TC1
2455 * @arg @ref LL_HRTIM_OUTPUT_TC2
2456 * @arg @ref LL_HRTIM_OUTPUT_TD1
2457 * @arg @ref LL_HRTIM_OUTPUT_TD2
2458 * @arg @ref LL_HRTIM_OUTPUT_TE1
2459 * @arg @ref LL_HRTIM_OUTPUT_TE2
2460 * @arg @ref LL_HRTIM_OUTPUT_TF1
2461 * @arg @ref LL_HRTIM_OUTPUT_TF2
2462 * @retval None
2463 */
LL_HRTIM_DisableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2464 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2465 {
2466 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
2467 }
2468
2469 /**
2470 * @brief Indicates whether the HRTIM timer output is enabled.
2471 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
2472 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
2473 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
2474 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
2475 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
2476 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
2477 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
2478 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
2479 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
2480 * OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
2481 * OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
2482 * OENR TF2OEN LL_HRTIM_IsEnabledOutput
2483 * @param HRTIMx High Resolution Timer instance
2484 * @param Output This parameter can be one of the following values:
2485 * @arg @ref LL_HRTIM_OUTPUT_TA1
2486 * @arg @ref LL_HRTIM_OUTPUT_TA2
2487 * @arg @ref LL_HRTIM_OUTPUT_TB1
2488 * @arg @ref LL_HRTIM_OUTPUT_TB2
2489 * @arg @ref LL_HRTIM_OUTPUT_TC1
2490 * @arg @ref LL_HRTIM_OUTPUT_TC2
2491 * @arg @ref LL_HRTIM_OUTPUT_TD1
2492 * @arg @ref LL_HRTIM_OUTPUT_TD2
2493 * @arg @ref LL_HRTIM_OUTPUT_TE1
2494 * @arg @ref LL_HRTIM_OUTPUT_TE2
2495 * @arg @ref LL_HRTIM_OUTPUT_TF1
2496 * @arg @ref LL_HRTIM_OUTPUT_TF2
2497 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
2498 */
LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef * HRTIMx,uint32_t Output)2499 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
2500 {
2501 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
2502 }
2503
2504 /**
2505 * @brief Indicates whether the HRTIM timer output is disabled.
2506 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
2507 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
2508 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
2509 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
2510 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
2511 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
2512 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
2513 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
2514 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
2515 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
2516 * ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
2517 * ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
2518 * @param HRTIMx High Resolution Timer instance
2519 * @param Output This parameter can be one of the following values:
2520 * @arg @ref LL_HRTIM_OUTPUT_TA1
2521 * @arg @ref LL_HRTIM_OUTPUT_TA2
2522 * @arg @ref LL_HRTIM_OUTPUT_TB1
2523 * @arg @ref LL_HRTIM_OUTPUT_TB2
2524 * @arg @ref LL_HRTIM_OUTPUT_TC1
2525 * @arg @ref LL_HRTIM_OUTPUT_TC2
2526 * @arg @ref LL_HRTIM_OUTPUT_TD1
2527 * @arg @ref LL_HRTIM_OUTPUT_TD2
2528 * @arg @ref LL_HRTIM_OUTPUT_TE1
2529 * @arg @ref LL_HRTIM_OUTPUT_TE2
2530 * @arg @ref LL_HRTIM_OUTPUT_TF1
2531 * @arg @ref LL_HRTIM_OUTPUT_TF2
2532 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
2533 */
LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef * HRTIMx,uint32_t Output)2534 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
2535 {
2536 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
2537 }
2538
2539 /**
2540 * @brief Configure an ADC trigger.
2541 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
2542 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
2543 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
2544 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
2545 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
2546 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
2547 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
2548 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
2549 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
2550 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
2551 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
2552 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
2553 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
2554 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
2555 * ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
2556 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
2557 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
2558 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
2559 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
2560 * ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
2561 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
2562 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
2563 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
2564 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
2565 * ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
2566 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
2567 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
2568 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
2569 * ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
2570 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
2571 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
2572 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
2573 * ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
2574 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
2575 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
2576 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
2577 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
2578 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
2579 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
2580 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
2581 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
2582 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
2583 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
2584 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
2585 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
2586 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
2587 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
2588 * ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
2589 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
2590 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
2591 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
2592 * ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
2593 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
2594 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
2595 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
2596 * ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
2597 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
2598 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
2599 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
2600 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
2601 * ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
2602 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
2603 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
2604 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
2605 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
2606 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
2607 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
2608 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
2609 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
2610 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
2611 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
2612 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
2613 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
2614 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
2615 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
2616 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
2617 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
2618 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
2619 * ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
2620 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
2621 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
2622 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
2623 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
2624 * ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
2625 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
2626 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
2627 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
2628 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
2629 * ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
2630 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
2631 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
2632 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
2633 * ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
2634 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
2635 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
2636 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
2637 * ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
2638 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
2639 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
2640 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
2641 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
2642 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
2643 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
2644 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
2645 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
2646 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
2647 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
2648 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
2649 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
2650 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
2651 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
2652 * ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
2653 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
2654 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
2655 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
2656 * ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
2657 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
2658 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
2659 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
2660 * ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
2661 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
2662 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
2663 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
2664 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
2665 * ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
2666 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
2667 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
2668 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
2669 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
2670 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
2671 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
2672 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
2673 * @param HRTIMx High Resolution Timer instance
2674 * @param ADCTrig This parameter can be one of the following values:
2675 * @arg @ref LL_HRTIM_ADCTRIG_1
2676 * @arg @ref LL_HRTIM_ADCTRIG_2
2677 * @arg @ref LL_HRTIM_ADCTRIG_3
2678 * @arg @ref LL_HRTIM_ADCTRIG_4
2679 * @param Update This parameter can be one of the following values:
2680 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2681 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2682 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2683 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2684 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2685 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2686 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2687 * @param Src This parameter can be a combination of the following values:
2688 *
2689 * For ADC trigger 1 and ADC trigger 3:
2690 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2691 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2692 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2693 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2694 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2695 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2696 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2697 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2698 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2699 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2700 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2701 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2702 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2703 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2704 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2705 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2706 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2707 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2708 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2709 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2710 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2711 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2712 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2713 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2714 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2715 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2716 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2717 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2718 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
2719 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
2720 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
2721 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
2722 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
2723 *
2724 * For ADC trigger 2 and ADC trigger 4:
2725 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2726 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2727 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2728 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2729 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2730 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2731 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2732 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2733 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2734 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2735 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2736 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2737 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2738 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2739 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2740 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2741 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2742 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2743 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2744 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2745 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2746 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2747 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2748 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2749 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2750 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2751 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2752 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2753 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2754 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
2755 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
2756 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
2757 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
2758 *
2759 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
2760 * can be one of the following values:
2761 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
2762 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
2763 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
2764 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
2765 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
2766 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
2767 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
2768 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
2769 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
2770 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
2771 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
2772 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
2773 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
2774 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
2775 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
2776 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
2777 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
2778 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
2779 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
2780 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
2781 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
2782 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
2783 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
2784 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
2785 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
2786 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
2787 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
2788 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
2789 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
2790 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
2791 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
2792 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
2793 *
2794 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
2795 * can be one of the following values:
2796 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
2797 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
2798 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
2799 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
2800 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
2801 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
2802 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
2803 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
2804 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
2805 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
2806 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
2807 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
2808 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
2809 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
2810 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
2811 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
2812 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
2813 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
2814 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
2815 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
2816 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
2817 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
2818 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
2819 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
2820 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
2821 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
2822 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
2823 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
2824 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
2825 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
2826 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
2827 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
2828 * @retval None
2829 */
LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update,uint32_t Src)2830 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
2831 {
2832 __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2833 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2834 __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2835 REG_OFFSET_TAB_ADCER[ADCTrig]));
2836 MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2837 MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
2838 }
2839
2840 /**
2841 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
2842 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
2843 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
2844 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
2845 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
2846 * ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
2847 * ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
2848 * ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
2849 * ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
2850 * ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
2851 * ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
2852 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
2853 * registers are not preloaded either: a write access will result in an
2854 * immediate update of the trigger source.
2855 * @param HRTIMx High Resolution Timer instance
2856 * @param ADCTrig This parameter can be one of the following values:
2857 * @arg @ref LL_HRTIM_ADCTRIG_1
2858 * @arg @ref LL_HRTIM_ADCTRIG_2
2859 * @arg @ref LL_HRTIM_ADCTRIG_3
2860 * @arg @ref LL_HRTIM_ADCTRIG_4
2861 * @arg @ref LL_HRTIM_ADCTRIG_5
2862 * @arg @ref LL_HRTIM_ADCTRIG_6
2863 * @arg @ref LL_HRTIM_ADCTRIG_7
2864 * @arg @ref LL_HRTIM_ADCTRIG_8
2865 * @arg @ref LL_HRTIM_ADCTRIG_9
2866 * @arg @ref LL_HRTIM_ADCTRIG_10
2867 * @param Update This parameter can be one of the following values:
2868 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2869 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2870 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2871 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2872 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2873 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2874 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2875 * @retval None
2876 */
LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update)2877 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2878 {
2879 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2880 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2881 MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2882 }
2883
2884 /**
2885 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2886 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2887 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2888 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2889 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2890 * ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
2891 * ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
2892 * ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
2893 * ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
2894 * ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
2895 * ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
2896 * @param HRTIMx High Resolution Timer instance
2897 * @param ADCTrig This parameter can be one of the following values:
2898 * @arg @ref LL_HRTIM_ADCTRIG_1
2899 * @arg @ref LL_HRTIM_ADCTRIG_2
2900 * @arg @ref LL_HRTIM_ADCTRIG_3
2901 * @arg @ref LL_HRTIM_ADCTRIG_4
2902 * @arg @ref LL_HRTIM_ADCTRIG_5
2903 * @arg @ref LL_HRTIM_ADCTRIG_6
2904 * @arg @ref LL_HRTIM_ADCTRIG_7
2905 * @arg @ref LL_HRTIM_ADCTRIG_8
2906 * @arg @ref LL_HRTIM_ADCTRIG_9
2907 * @arg @ref LL_HRTIM_ADCTRIG_10
2908 * @retval Update Returned value can be one of the following values:
2909 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2910 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2911 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2912 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2913 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2914 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2915 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2916 */
LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2917 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2918 {
2919 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2920 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2921 return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
2922 }
2923
2924 /**
2925 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2926 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2927 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2928 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2929 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2930 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2931 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2932 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2933 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2934 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2935 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2936 * ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
2937 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2938 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2939 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2940 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2941 * ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
2942 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2943 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2944 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2945 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2946 * ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
2947 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2948 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2949 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2950 * ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
2951 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2952 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2953 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2954 * ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
2955 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2956 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2957 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2958 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2959 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2960 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2961 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2962 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2963 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2964 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2965 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2966 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2967 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2968 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2969 * ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
2970 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2971 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2972 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2973 * ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
2974 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2975 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2976 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2977 * ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
2978 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2979 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2980 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2981 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2982 * ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
2983 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2984 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2985 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2986 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2987 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2988 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2989 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2990 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
2991 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
2992 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
2993 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
2994 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
2995 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
2996 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
2997 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
2998 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
2999 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
3000 * ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
3001 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
3002 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
3003 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
3004 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
3005 * ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
3006 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
3007 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
3008 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
3009 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
3010 * ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
3011 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
3012 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
3013 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
3014 * ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
3015 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
3016 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
3017 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
3018 * ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
3019 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
3020 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
3021 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
3022 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
3023 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
3024 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
3025 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
3026 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
3027 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
3028 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
3029 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
3030 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
3031 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
3032 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
3033 * ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
3034 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
3035 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
3036 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
3037 * ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
3038 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
3039 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
3040 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
3041 * ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
3042 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
3043 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
3044 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
3045 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
3046 * ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
3047 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
3048 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
3049 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
3050 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
3051 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
3052 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
3053 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
3054 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3055 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3056 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3057 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3058 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3059 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3060 * @param HRTIMx High Resolution Timer instance
3061 * @param ADCTrig This parameter can be one of the following values:
3062 * @arg @ref LL_HRTIM_ADCTRIG_1
3063 * @arg @ref LL_HRTIM_ADCTRIG_2
3064 * @arg @ref LL_HRTIM_ADCTRIG_3
3065 * @arg @ref LL_HRTIM_ADCTRIG_4
3066 * @arg @ref LL_HRTIM_ADCTRIG_5
3067 * @arg @ref LL_HRTIM_ADCTRIG_6
3068 * @arg @ref LL_HRTIM_ADCTRIG_7
3069 * @arg @ref LL_HRTIM_ADCTRIG_8
3070 * @arg @ref LL_HRTIM_ADCTRIG_9
3071 * @arg @ref LL_HRTIM_ADCTRIG_10
3072 * @param Src
3073 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3074 * combination of the following values:
3075 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3076 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3077 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3078 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3079 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3080 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3081 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3082 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3083 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3084 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3085 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3086 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3087 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3088 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3089 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3090 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3091 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3092 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3093 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3094 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3095 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3096 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3097 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3098 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3099 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3100 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3101 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3102 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3103 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3104 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3105 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3106 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3107 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3108 *
3109 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3110 * combination of the following values:
3111 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3112 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3113 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3114 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3115 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3116 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3117 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3118 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3119 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3120 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3121 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3122 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3123 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3124 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3125 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3126 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3127 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3128 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3129 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3130 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3131 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3132 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3133 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3134 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3135 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3136 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3137 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3138 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3139 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3140 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3141 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3142 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3143 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3144 *
3145 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3146 * can be one of the following values:
3147 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3148 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3149 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3150 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3151 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3152 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3153 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3154 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3155 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3156 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3157 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3158 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3159 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3160 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3161 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3162 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3163 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3164 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3165 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3166 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3167 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3168 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3169 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3170 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3171 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3172 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3173 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3174 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3175 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3176 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3177 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3178 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3179 *
3180 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3181 * can be one of the following values:
3182 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3183 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3184 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3185 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3186 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3187 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3188 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3189 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3190 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3191 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3192 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3193 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3194 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3195 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3196 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3197 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3198 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3199 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3200 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3201 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3202 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3203 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3204 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3205 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3206 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3207 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3208 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3209 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3210 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3211 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3212 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3213 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3214 * @retval None
3215 */
LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Src)3216 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
3217 {
3218 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3219 REG_OFFSET_TAB_ADCER[ADCTrig]));
3220 MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
3221 }
3222
3223 /**
3224 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
3225 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
3226 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
3227 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
3228 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
3229 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
3230 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
3231 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
3232 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
3233 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
3234 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
3235 * ADC1R ADC1TFC2 LL_HRTIM_GetADCTrigSrc\n
3236 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
3237 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
3238 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
3239 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
3240 * ADC1R ADC1TFC3 LL_HRTIM_GetADCTrigSrc\n
3241 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
3242 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
3243 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
3244 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
3245 * ADC1R ADC1TFC4 LL_HRTIM_GetADCTrigSrc\n
3246 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
3247 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
3248 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
3249 * ADC1R ADC1TFPER LL_HRTIM_GetADCTrigSrc\n
3250 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
3251 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
3252 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
3253 * ADC1R ADC1TFRST LL_HRTIM_GetADCTrigSrc\n
3254 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
3255 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
3256 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
3257 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
3258 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
3259 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
3260 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
3261 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
3262 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
3263 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
3264 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
3265 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
3266 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
3267 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
3268 * ADC2R ADC2TFC2 LL_HRTIM_GetADCTrigSrc\n
3269 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
3270 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
3271 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
3272 * ADC2R ADC2TFC3 LL_HRTIM_GetADCTrigSrc\n
3273 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
3274 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
3275 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
3276 * ADC2R ADC2TFC4 LL_HRTIM_GetADCTrigSrc\n
3277 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
3278 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
3279 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
3280 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
3281 * ADC2R ADC2TFPER LL_HRTIM_GetADCTrigSrc\n
3282 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
3283 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
3284 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
3285 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
3286 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
3287 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
3288 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
3289 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
3290 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
3291 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
3292 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
3293 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
3294 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
3295 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
3296 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
3297 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
3298 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
3299 * ADC3R ADC3TFC2 LL_HRTIM_GetADCTrigSrc\n
3300 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
3301 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
3302 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
3303 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
3304 * ADC3R ADC3TFC3 LL_HRTIM_GetADCTrigSrc\n
3305 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
3306 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
3307 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
3308 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
3309 * ADC3R ADC3TFC4 LL_HRTIM_GetADCTrigSrc\n
3310 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
3311 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
3312 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
3313 * ADC3R ADC3TFPER LL_HRTIM_GetADCTrigSrc\n
3314 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
3315 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
3316 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
3317 * ADC3R ADC3TFRST LL_HRTIM_GetADCTrigSrc\n
3318 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
3319 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
3320 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
3321 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
3322 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
3323 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
3324 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
3325 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
3326 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
3327 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
3328 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
3329 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
3330 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
3331 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
3332 * ADC4R ADC4TFC2 LL_HRTIM_GetADCTrigSrc\n
3333 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
3334 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
3335 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
3336 * ADC4R ADC4TFC3 LL_HRTIM_GetADCTrigSrc\n
3337 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
3338 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
3339 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
3340 * ADC4R ADC4TFC4 LL_HRTIM_GetADCTrigSrc\n
3341 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
3342 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
3343 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
3344 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
3345 * ADC4R ADC4TFPER LL_HRTIM_GetADCTrigSrc\n
3346 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
3347 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
3348 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
3349 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
3350 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
3351 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
3352 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
3353 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3354 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3355 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3356 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3357 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3358 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3359 * @param HRTIMx High Resolution Timer instance
3360 * @param HRTIMx High Resolution Timer instance
3361 * @param ADCTrig This parameter can be one of the following values:
3362 * @arg @ref LL_HRTIM_ADCTRIG_1
3363 * @arg @ref LL_HRTIM_ADCTRIG_2
3364 * @arg @ref LL_HRTIM_ADCTRIG_3
3365 * @arg @ref LL_HRTIM_ADCTRIG_4
3366 * @arg @ref LL_HRTIM_ADCTRIG_5
3367 * @arg @ref LL_HRTIM_ADCTRIG_6
3368 * @arg @ref LL_HRTIM_ADCTRIG_7
3369 * @arg @ref LL_HRTIM_ADCTRIG_8
3370 * @arg @ref LL_HRTIM_ADCTRIG_9
3371 * @arg @ref LL_HRTIM_ADCTRIG_10
3372 * @retval Src This parameter can be a combination of the following values:
3373 *
3374 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3375 * combination of the following values:
3376 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3377 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3378 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3379 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3380 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3381 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3382 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3383 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3384 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3385 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3386 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3387 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3388 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3389 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3390 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3391 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3392 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3393 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3409 *
3410 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3411 * combination of the following values:
3412 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3413 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3414 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3415 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3416 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3417 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3418 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3419 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3420 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3421 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3422 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3423 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3424 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3425 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3426 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3427 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3428 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3429 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3445 *
3446 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3447 * can be one of the following values:
3448 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3449 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3450 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3451 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3452 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3453 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3454 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3455 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3456 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3457 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3458 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3459 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3460 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3461 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3462 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3463 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3464 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3465 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3466 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3467 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3468 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3469 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3470 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3471 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3472 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3473 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3474 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3475 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3476 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3477 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3478 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3479 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3480 *
3481 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3482 * can be one of the following values:
3483 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3484 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3485 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3486 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3487 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3488 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3489 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3490 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3491 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3492 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3493 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3494 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3495 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3496 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3497 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3498 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3499 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3500 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3501 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3502 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3503 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3504 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3505 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3506 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3507 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3508 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3509 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3510 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3511 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3512 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3513 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3514 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3515 */
LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3516 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3517 {
3518 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3519 REG_OFFSET_TAB_ADCER[ADCTrig]));
3520 return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
3521
3522 }
3523
3524
3525 /**
3526 * @brief Select the ADC post scaler.
3527 * @note This function allows to adjust each ADC trigger rate individually.
3528 * @note In center-aligned mode, the ADC trigger rate is also dependent on
3529 * ADROM[1:0] bitfield, programmed in the source timer
3530 * (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
3531 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_SetADCPostScaler\n
3532 * ADCPS2 ADC9PSC LL_HRTIM_SetADCPostScaler\n
3533 * ADCPS2 ADC8PSC LL_HRTIM_SetADCPostScaler\n
3534 * ADCPS2 ADC7PSC LL_HRTIM_SetADCPostScaler\n
3535 * ADCPS2 ADC6PSC LL_HRTIM_SetADCPostScaler\n
3536 * ADCPS1 ADC5PSC LL_HRTIM_SetADCPostScaler\n
3537 * ADCPS1 ADC4PSC LL_HRTIM_SetADCPostScaler\n
3538 * ADCPS1 ADC3PSC LL_HRTIM_SetADCPostScaler\n
3539 * ADCPS1 ADC2PSC LL_HRTIM_SetADCPostScaler\n
3540 * ADCPS1 ADC1PSC LL_HRTIM_SetADCPostScaler
3541 * @param HRTIMx High Resolution Timer instance
3542 * @param ADCTrig This parameter can be one of the following values:
3543 * @arg @ref LL_HRTIM_ADCTRIG_1
3544 * @arg @ref LL_HRTIM_ADCTRIG_2
3545 * @arg @ref LL_HRTIM_ADCTRIG_3
3546 * @arg @ref LL_HRTIM_ADCTRIG_4
3547 * @arg @ref LL_HRTIM_ADCTRIG_5
3548 * @arg @ref LL_HRTIM_ADCTRIG_6
3549 * @arg @ref LL_HRTIM_ADCTRIG_7
3550 * @arg @ref LL_HRTIM_ADCTRIG_8
3551 * @arg @ref LL_HRTIM_ADCTRIG_9
3552 * @arg @ref LL_HRTIM_ADCTRIG_10
3553 * @param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3554 * @retval None
3555 */
LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t PostScaler)3556 __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
3557 {
3558
3559 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3560 uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3561
3562 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
3563 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
3564
3565 }
3566
3567 /**
3568 * @brief Get the selected ADC post scaler.
3569 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_GetADCPostScaler\n
3570 * ADCPS2 ADC9PSC LL_HRTIM_GetADCPostScaler\n
3571 * ADCPS2 ADC8PSC LL_HRTIM_GetADCPostScaler\n
3572 * ADCPS2 ADC7PSC LL_HRTIM_GetADCPostScaler\n
3573 * ADCPS2 ADC6PSC LL_HRTIM_GetADCPostScaler\n
3574 * ADCPS1 ADC5PSC LL_HRTIM_GetADCPostScaler\n
3575 * ADCPS1 ADC4PSC LL_HRTIM_GetADCPostScaler\n
3576 * ADCPS1 ADC3PSC LL_HRTIM_GetADCPostScaler\n
3577 * ADCPS1 ADC2PSC LL_HRTIM_GetADCPostScaler\n
3578 * ADCPS1 ADC1PSC LL_HRTIM_GetADCPostScaler
3579 * @param HRTIMx High Resolution Timer instance
3580 * @param ADCTrig This parameter can be one of the following values:
3581 * @arg @ref LL_HRTIM_ADCTRIG_1
3582 * @arg @ref LL_HRTIM_ADCTRIG_2
3583 * @arg @ref LL_HRTIM_ADCTRIG_3
3584 * @arg @ref LL_HRTIM_ADCTRIG_4
3585 * @arg @ref LL_HRTIM_ADCTRIG_5
3586 * @arg @ref LL_HRTIM_ADCTRIG_6
3587 * @arg @ref LL_HRTIM_ADCTRIG_7
3588 * @arg @ref LL_HRTIM_ADCTRIG_8
3589 * @arg @ref LL_HRTIM_ADCTRIG_9
3590 * @arg @ref LL_HRTIM_ADCTRIG_10
3591 * @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3592 */
LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3593 __STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3594 {
3595
3596 uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
3597 uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
3598
3599 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3600 uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
3601
3602 return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
3603
3604 }
3605
3606 /**
3607 * @brief Configure the DLL calibration mode.
3608 * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
3609 * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
3610 * @param HRTIMx High Resolution Timer instance
3611 * @param Mode This parameter can be one of the following values:
3612 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
3613 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
3614 * @param Period This parameter can be one of the following values:
3615 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
3616 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
3617 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
3618 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
3619 * @retval None
3620 */
LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef * HRTIMx,uint32_t Mode,uint32_t Period)3621 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
3622 {
3623 MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
3624 }
3625
3626 /**
3627 * @brief Launch DLL calibration
3628 * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
3629 * @param HRTIMx High Resolution Timer instance
3630 * @retval None
3631 */
LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef * HRTIMx)3632 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
3633 {
3634 SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
3635 }
3636
3637 /**
3638 * @}
3639 */
3640
3641 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
3642 * @{
3643 */
3644
3645 /**
3646 * @brief Enable timer(s) counter.
3647 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterEnable\n
3648 * MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
3649 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
3650 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
3651 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
3652 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
3653 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
3654 * @param HRTIMx High Resolution Timer instance
3655 * @param Timers This parameter can be a combination of the following values:
3656 * @arg @ref LL_HRTIM_TIMER_MASTER
3657 * @arg @ref LL_HRTIM_TIMER_A
3658 * @arg @ref LL_HRTIM_TIMER_B
3659 * @arg @ref LL_HRTIM_TIMER_C
3660 * @arg @ref LL_HRTIM_TIMER_D
3661 * @arg @ref LL_HRTIM_TIMER_E
3662 * @arg @ref LL_HRTIM_TIMER_F
3663 * @retval None
3664 */
LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3665 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3666 {
3667 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3668 }
3669
3670 /**
3671 * @brief Disable timer(s) counter.
3672 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterDisable\n
3673 * MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
3674 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
3675 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
3676 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
3677 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
3678 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
3679 * @param HRTIMx High Resolution Timer instance
3680 * @param Timers This parameter can be a combination of the following values:
3681 * @arg @ref LL_HRTIM_TIMER_MASTER
3682 * @arg @ref LL_HRTIM_TIMER_A
3683 * @arg @ref LL_HRTIM_TIMER_B
3684 * @arg @ref LL_HRTIM_TIMER_C
3685 * @arg @ref LL_HRTIM_TIMER_D
3686 * @arg @ref LL_HRTIM_TIMER_E
3687 * @arg @ref LL_HRTIM_TIMER_F
3688 * @retval None
3689 */
LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3690 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3691 {
3692 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3693 }
3694
3695 /**
3696 * @brief Indicate whether the timer counter is enabled.
3697 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_IsCounterEnabled\n
3698 * MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
3699 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
3700 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
3701 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
3702 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
3703 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
3704 * @param HRTIMx High Resolution Timer instance
3705 * @param Timer This parameter can be one of the following values:
3706 * @arg @ref LL_HRTIM_TIMER_MASTER
3707 * @arg @ref LL_HRTIM_TIMER_A
3708 * @arg @ref LL_HRTIM_TIMER_B
3709 * @arg @ref LL_HRTIM_TIMER_C
3710 * @arg @ref LL_HRTIM_TIMER_D
3711 * @arg @ref LL_HRTIM_TIMER_E
3712 * @arg @ref LL_HRTIM_TIMER_F
3713 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
3714 */
LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3715 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3716 {
3717 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
3718 }
3719
3720 /**
3721 * @brief Set the timer clock prescaler ratio.
3722 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
3723 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
3724 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
3725 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
3726 * @param HRTIMx High Resolution Timer instance
3727 * @param Timer This parameter can be one of the following values:
3728 * @arg @ref LL_HRTIM_TIMER_MASTER
3729 * @arg @ref LL_HRTIM_TIMER_A
3730 * @arg @ref LL_HRTIM_TIMER_B
3731 * @arg @ref LL_HRTIM_TIMER_C
3732 * @arg @ref LL_HRTIM_TIMER_D
3733 * @arg @ref LL_HRTIM_TIMER_E
3734 * @arg @ref LL_HRTIM_TIMER_F
3735 * @param Prescaler This parameter can be one of the following values:
3736 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3737 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3738 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3739 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3740 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3741 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3742 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3743 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3744 * @retval None
3745 */
LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)3746 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
3747 {
3748 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3749 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3750 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
3751 }
3752
3753 /**
3754 * @brief Get the timer clock prescaler ratio
3755 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
3756 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
3757 * @param HRTIMx High Resolution Timer instance
3758 * @param Timer This parameter can be one of the following values:
3759 * @arg @ref LL_HRTIM_TIMER_MASTER
3760 * @arg @ref LL_HRTIM_TIMER_A
3761 * @arg @ref LL_HRTIM_TIMER_B
3762 * @arg @ref LL_HRTIM_TIMER_C
3763 * @arg @ref LL_HRTIM_TIMER_D
3764 * @arg @ref LL_HRTIM_TIMER_E
3765 * @arg @ref LL_HRTIM_TIMER_F
3766 * @retval Prescaler Returned value can be one of the following values:
3767 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3768 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3769 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3770 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3771 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3772 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3773 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3774 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3775 */
LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3776 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3777 {
3778 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3779 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3780 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
3781 }
3782
3783 /**
3784 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
3785 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
3786 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
3787 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
3788 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
3789 * @param HRTIMx High Resolution Timer instance
3790 * @param Timer This parameter can be one of the following values:
3791 * @arg @ref LL_HRTIM_TIMER_MASTER
3792 * @arg @ref LL_HRTIM_TIMER_A
3793 * @arg @ref LL_HRTIM_TIMER_B
3794 * @arg @ref LL_HRTIM_TIMER_C
3795 * @arg @ref LL_HRTIM_TIMER_D
3796 * @arg @ref LL_HRTIM_TIMER_E
3797 * @arg @ref LL_HRTIM_TIMER_F
3798 * @param Mode This parameter can be one of the following values:
3799 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3800 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3801 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3802 * @retval None
3803 */
LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)3804 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
3805 {
3806 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3807 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3808 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
3809 }
3810
3811 /**
3812 * @brief Get the counter operating mode mode
3813 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
3814 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
3815 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
3816 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
3817 * @param HRTIMx High Resolution Timer instance
3818 * @param Timer This parameter can be one of the following values:
3819 * @arg @ref LL_HRTIM_TIMER_MASTER
3820 * @arg @ref LL_HRTIM_TIMER_A
3821 * @arg @ref LL_HRTIM_TIMER_B
3822 * @arg @ref LL_HRTIM_TIMER_C
3823 * @arg @ref LL_HRTIM_TIMER_D
3824 * @arg @ref LL_HRTIM_TIMER_E
3825 * @arg @ref LL_HRTIM_TIMER_F
3826 * @retval Mode Returned value can be one of the following values:
3827 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3828 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3829 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3830 */
LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3831 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3832 {
3833 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3834 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3835 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
3836 }
3837
3838 /**
3839 * @brief Enable the half duty-cycle mode.
3840 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
3841 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
3842 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
3843 * active register is automatically updated with HRTIM_MPER/2
3844 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
3845 * @param HRTIMx High Resolution Timer instance
3846 * @param Timer This parameter can be one of the following values:
3847 * @arg @ref LL_HRTIM_TIMER_MASTER
3848 * @arg @ref LL_HRTIM_TIMER_A
3849 * @arg @ref LL_HRTIM_TIMER_B
3850 * @arg @ref LL_HRTIM_TIMER_C
3851 * @arg @ref LL_HRTIM_TIMER_D
3852 * @arg @ref LL_HRTIM_TIMER_E
3853 * @arg @ref LL_HRTIM_TIMER_F
3854 * @retval None
3855 */
LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3856 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3857 {
3858 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3859 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3860 SET_BIT(*pReg, HRTIM_MCR_HALF);
3861 }
3862
3863 /**
3864 * @brief Disable the half duty-cycle mode.
3865 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
3866 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
3867 * @param HRTIMx High Resolution Timer instance
3868 * @param Timer This parameter can be one of the following values:
3869 * @arg @ref LL_HRTIM_TIMER_MASTER
3870 * @arg @ref LL_HRTIM_TIMER_A
3871 * @arg @ref LL_HRTIM_TIMER_B
3872 * @arg @ref LL_HRTIM_TIMER_C
3873 * @arg @ref LL_HRTIM_TIMER_D
3874 * @arg @ref LL_HRTIM_TIMER_E
3875 * @arg @ref LL_HRTIM_TIMER_F
3876 * @retval None
3877 */
LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3878 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3879 {
3880 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3881 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3882 CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
3883 CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
3884 }
3885
3886 /**
3887 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
3888 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
3889 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
3890 * @param HRTIMx High Resolution Timer instance
3891 * @param Timer This parameter can be one of the following values:
3892 * @arg @ref LL_HRTIM_TIMER_MASTER
3893 * @arg @ref LL_HRTIM_TIMER_A
3894 * @arg @ref LL_HRTIM_TIMER_B
3895 * @arg @ref LL_HRTIM_TIMER_C
3896 * @arg @ref LL_HRTIM_TIMER_D
3897 * @arg @ref LL_HRTIM_TIMER_E
3898 * @arg @ref LL_HRTIM_TIMER_F
3899 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
3900 */
LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3901 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3902 {
3903 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3904 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3905
3906 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
3907 }
3908
3909 /**
3910 * @brief Enable the Re-Syncronisation Update.
3911 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3912 * or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
3913 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_EnableResyncUpdate
3914 * @param HRTIMx High Resolution Timer instance
3915 * @param Timer This parameter can be one of the following values:
3916 * @arg @ref LL_HRTIM_TIMER_A
3917 * @arg @ref LL_HRTIM_TIMER_B
3918 * @arg @ref LL_HRTIM_TIMER_C
3919 * @arg @ref LL_HRTIM_TIMER_D
3920 * @arg @ref LL_HRTIM_TIMER_E
3921 * @arg @ref LL_HRTIM_TIMER_F
3922 * @retval None
3923 */
LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3924 __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3925 {
3926 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3927 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3928 REG_OFFSET_TAB_TIMER[iTimer]));
3929 SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3930 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3931 }
3932
3933 /**
3934 * @brief Disable the Re-Syncronisation Update.
3935 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3936 * or from a software update (TxSWU bit) is taken into account immediately.
3937 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_DisableResyncUpdate
3938 * @param HRTIMx High Resolution Timer instance
3939 * @param Timer This parameter can be one of the following values:
3940 * @arg @ref LL_HRTIM_TIMER_A
3941 * @arg @ref LL_HRTIM_TIMER_B
3942 * @arg @ref LL_HRTIM_TIMER_C
3943 * @arg @ref LL_HRTIM_TIMER_D
3944 * @arg @ref LL_HRTIM_TIMER_E
3945 * @arg @ref LL_HRTIM_TIMER_F
3946 * @retval None
3947 */
LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3948 __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3949 {
3950 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3951 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3952 REG_OFFSET_TAB_TIMER[iTimer]));
3953
3954 CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3955 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3956 }
3957
3958 /**
3959 * @brief Indicate whether the Re-Syncronisation Update is enabled.
3960 * @note This bit specifies whether update source coming outside
3961 * from the timing unit must be synchronized
3962 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_IsEnabledResyncUpdate
3963 * @param HRTIMx High Resolution Timer instance
3964 * @param Timer This parameter can be one of the following values:
3965 * @arg @ref LL_HRTIM_TIMER_A
3966 * @arg @ref LL_HRTIM_TIMER_B
3967 * @arg @ref LL_HRTIM_TIMER_C
3968 * @arg @ref LL_HRTIM_TIMER_D
3969 * @arg @ref LL_HRTIM_TIMER_E
3970 * @arg @ref LL_HRTIM_TIMER_F
3971 * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
3972 */
LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3973 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3974 {
3975 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3976 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3977 REG_OFFSET_TAB_TIMER[iTimer]));
3978
3979 return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
3980 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3981 }
3982
3983 /**
3984 * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
3985 * @note When interleaved mode is enabled, the content of the compare registers is overridden.
3986 * @rmtoll MCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
3987 * MCR INTLVD LL_HRTIM_TIM_SetInterleavedMode\n
3988 * TIMxCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
3989 * TIMxCR INTLVD LL_HRTIM_TIM_SetInterleavedMode
3990 * @param HRTIMx High Resolution Timer instance
3991 * @param Timer This parameter can be one of the following values:
3992 * @arg @ref LL_HRTIM_TIMER_MASTER
3993 * @arg @ref LL_HRTIM_TIMER_A
3994 * @arg @ref LL_HRTIM_TIMER_B
3995 * @arg @ref LL_HRTIM_TIMER_C
3996 * @arg @ref LL_HRTIM_TIMER_D
3997 * @arg @ref LL_HRTIM_TIMER_E
3998 * @arg @ref LL_HRTIM_TIMER_F
3999 * @param Mode This parameter can be one of the following values:
4000 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4001 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4002 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4003 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4004 * @retval None
4005 */
LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)4006 __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
4007 {
4008 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4009 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4010
4011 MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
4012 ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
4013 }
4014
4015 /**
4016 * @brief get the Interleaved configuration.
4017 * @rmtoll MCR INTLVD LL_HRTIM_TIM_GetInterleavedMode\n
4018 * TIMxCR INTLVD LL_HRTIM_TIM_GetInterleavedMode
4019 * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
4020 * the interleaved Mode is dual if HALF bit is set,
4021
4022 * HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
4023 * with HRTIM_MPER/2 or HRTIM_MPER/4
4024 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
4025
4026 * @param HRTIMx High Resolution Timer instance
4027 * @param Timer This parameter can be one of the following values:
4028 * @arg @ref LL_HRTIM_TIMER_MASTER
4029 * @arg @ref LL_HRTIM_TIMER_A
4030 * @arg @ref LL_HRTIM_TIMER_B
4031 * @arg @ref LL_HRTIM_TIMER_C
4032 * @arg @ref LL_HRTIM_TIMER_D
4033 * @arg @ref LL_HRTIM_TIMER_E
4034 * @arg @ref LL_HRTIM_TIMER_F
4035 * @retval This parameter can be one of the following values:
4036 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4037 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4038 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4039 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4040 */
LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4041 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4042 {
4043 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4044 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4045
4046 uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
4047 return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD));
4048 }
4049
4050 /**
4051 * @brief Enable the timer start when receiving a synchronization input event.
4052 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
4053 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
4054 * @param HRTIMx High Resolution Timer instance
4055 * @param Timer This parameter can be one of the following values:
4056 * @arg @ref LL_HRTIM_TIMER_MASTER
4057 * @arg @ref LL_HRTIM_TIMER_A
4058 * @arg @ref LL_HRTIM_TIMER_B
4059 * @arg @ref LL_HRTIM_TIMER_C
4060 * @arg @ref LL_HRTIM_TIMER_D
4061 * @arg @ref LL_HRTIM_TIMER_E
4062 * @arg @ref LL_HRTIM_TIMER_F
4063 * @retval None
4064 */
LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4065 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4066 {
4067 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4068 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4069 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4070 }
4071
4072 /**
4073 * @brief Disable the timer start when receiving a synchronization input event.
4074 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
4075 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
4076 * @param HRTIMx High Resolution Timer instance
4077 * @param Timer This parameter can be one of the following values:
4078 * @arg @ref LL_HRTIM_TIMER_MASTER
4079 * @arg @ref LL_HRTIM_TIMER_A
4080 * @arg @ref LL_HRTIM_TIMER_B
4081 * @arg @ref LL_HRTIM_TIMER_C
4082 * @arg @ref LL_HRTIM_TIMER_D
4083 * @arg @ref LL_HRTIM_TIMER_E
4084 * @arg @ref LL_HRTIM_TIMER_F
4085 * @retval None
4086 */
LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4087 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4088 {
4089 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4090 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4091 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4092 }
4093
4094 /**
4095 * @brief Indicate whether the timer start when receiving a synchronization input event.
4096 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
4097 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
4098 * @param HRTIMx High Resolution Timer instance
4099 * @param Timer This parameter can be one of the following values:
4100 * @arg @ref LL_HRTIM_TIMER_MASTER
4101 * @arg @ref LL_HRTIM_TIMER_A
4102 * @arg @ref LL_HRTIM_TIMER_B
4103 * @arg @ref LL_HRTIM_TIMER_C
4104 * @arg @ref LL_HRTIM_TIMER_D
4105 * @arg @ref LL_HRTIM_TIMER_E
4106 * @arg @ref LL_HRTIM_TIMER_F
4107 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4108 */
LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4109 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4110 {
4111 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4112 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4113
4114 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
4115 }
4116
4117 /**
4118 * @brief Enable the timer reset when receiving a synchronization input event.
4119 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
4120 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
4121 * @param HRTIMx High Resolution Timer instance
4122 * @param Timer This parameter can be one of the following values:
4123 * @arg @ref LL_HRTIM_TIMER_MASTER
4124 * @arg @ref LL_HRTIM_TIMER_A
4125 * @arg @ref LL_HRTIM_TIMER_B
4126 * @arg @ref LL_HRTIM_TIMER_C
4127 * @arg @ref LL_HRTIM_TIMER_D
4128 * @arg @ref LL_HRTIM_TIMER_E
4129 * @arg @ref LL_HRTIM_TIMER_F
4130 * @retval None
4131 */
LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4132 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4133 {
4134 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4135 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4136 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4137 }
4138
4139 /**
4140 * @brief Disable the timer reset when receiving a synchronization input event.
4141 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
4142 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
4143 * @param HRTIMx High Resolution Timer instance
4144 * @param Timer This parameter can be one of the following values:
4145 * @arg @ref LL_HRTIM_TIMER_MASTER
4146 * @arg @ref LL_HRTIM_TIMER_A
4147 * @arg @ref LL_HRTIM_TIMER_B
4148 * @arg @ref LL_HRTIM_TIMER_C
4149 * @arg @ref LL_HRTIM_TIMER_D
4150 * @arg @ref LL_HRTIM_TIMER_E
4151 * @arg @ref LL_HRTIM_TIMER_F
4152 * @retval None
4153 */
LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4154 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4155 {
4156 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4157 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4158 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4159 }
4160
4161 /**
4162 * @brief Indicate whether the timer reset when receiving a synchronization input event.
4163 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
4164 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
4165 * @param HRTIMx High Resolution Timer instance
4166 * @param Timer This parameter can be one of the following values:
4167 * @arg @ref LL_HRTIM_TIMER_MASTER
4168 * @arg @ref LL_HRTIM_TIMER_A
4169 * @arg @ref LL_HRTIM_TIMER_B
4170 * @arg @ref LL_HRTIM_TIMER_C
4171 * @arg @ref LL_HRTIM_TIMER_D
4172 * @arg @ref LL_HRTIM_TIMER_E
4173 * @arg @ref LL_HRTIM_TIMER_F
4174 * @retval None
4175 */
LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4176 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4177 {
4178 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4179 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4180
4181 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
4182 }
4183
4184 /**
4185 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4186 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
4187 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
4188 * @param HRTIMx High Resolution Timer instance
4189 * @param Timer This parameter can be one of the following values:
4190 * @arg @ref LL_HRTIM_TIMER_MASTER
4191 * @arg @ref LL_HRTIM_TIMER_A
4192 * @arg @ref LL_HRTIM_TIMER_B
4193 * @arg @ref LL_HRTIM_TIMER_C
4194 * @arg @ref LL_HRTIM_TIMER_D
4195 * @arg @ref LL_HRTIM_TIMER_E
4196 * @arg @ref LL_HRTIM_TIMER_F
4197 * @param DACTrig This parameter can be one of the following values:
4198 * @arg @ref LL_HRTIM_DACTRIG_NONE
4199 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4200 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4201 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4202 * @retval None
4203 */
LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DACTrig)4204 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
4205 {
4206 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4207 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4208 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
4209 }
4210
4211 /**
4212 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4213 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
4214 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
4215 * @param HRTIMx High Resolution Timer instance
4216 * @param Timer This parameter can be one of the following values:
4217 * @arg @ref LL_HRTIM_TIMER_MASTER
4218 * @arg @ref LL_HRTIM_TIMER_A
4219 * @arg @ref LL_HRTIM_TIMER_B
4220 * @arg @ref LL_HRTIM_TIMER_C
4221 * @arg @ref LL_HRTIM_TIMER_D
4222 * @arg @ref LL_HRTIM_TIMER_E
4223 * @arg @ref LL_HRTIM_TIMER_F
4224 * @retval DACTrig Returned value can be one of the following values:
4225 * @arg @ref LL_HRTIM_DACTRIG_NONE
4226 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4227 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4228 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4229 */
LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4230 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4231 {
4232 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4233 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4234 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
4235 }
4236
4237 /**
4238 * @brief Enable the timer registers preload mechanism.
4239 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
4240 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
4241 * @note When the preload mode is enabled, accessed registers are shadow registers.
4242 * Their content is transferred into the active register after an update request,
4243 * either software or synchronized with an event.
4244 * @param HRTIMx High Resolution Timer instance
4245 * @param Timer This parameter can be one of the following values:
4246 * @arg @ref LL_HRTIM_TIMER_MASTER
4247 * @arg @ref LL_HRTIM_TIMER_A
4248 * @arg @ref LL_HRTIM_TIMER_B
4249 * @arg @ref LL_HRTIM_TIMER_C
4250 * @arg @ref LL_HRTIM_TIMER_D
4251 * @arg @ref LL_HRTIM_TIMER_E
4252 * @arg @ref LL_HRTIM_TIMER_F
4253 * @retval None
4254 */
LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4255 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4256 {
4257 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4258 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4259 SET_BIT(*pReg, HRTIM_MCR_PREEN);
4260 }
4261
4262 /**
4263 * @brief Disable the timer registers preload mechanism.
4264 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
4265 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
4266 * @param HRTIMx High Resolution Timer instance
4267 * @param Timer This parameter can be one of the following values:
4268 * @arg @ref LL_HRTIM_TIMER_MASTER
4269 * @arg @ref LL_HRTIM_TIMER_A
4270 * @arg @ref LL_HRTIM_TIMER_B
4271 * @arg @ref LL_HRTIM_TIMER_C
4272 * @arg @ref LL_HRTIM_TIMER_D
4273 * @arg @ref LL_HRTIM_TIMER_E
4274 * @arg @ref LL_HRTIM_TIMER_F
4275 * @retval None
4276 */
LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4277 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4278 {
4279 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4280 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4281 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
4282 }
4283
4284 /**
4285 * @brief Indicate whether the timer registers preload mechanism is enabled.
4286 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
4287 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
4288 * @param HRTIMx High Resolution Timer instance
4289 * @param Timer This parameter can be one of the following values:
4290 * @arg @ref LL_HRTIM_TIMER_MASTER
4291 * @arg @ref LL_HRTIM_TIMER_A
4292 * @arg @ref LL_HRTIM_TIMER_B
4293 * @arg @ref LL_HRTIM_TIMER_C
4294 * @arg @ref LL_HRTIM_TIMER_D
4295 * @arg @ref LL_HRTIM_TIMER_E
4296 * @arg @ref LL_HRTIM_TIMER_F
4297 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4298 */
LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4299 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4300 {
4301 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4302 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4303
4304 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
4305 }
4306
4307 /**
4308 * @brief Set the timer register update trigger.
4309 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
4310 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
4311 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
4312 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
4313 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
4314 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
4315 * TIMxCR TFU LL_HRTIM_TIM_SetUpdateTrig\n
4316 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
4317 * @param HRTIMx High Resolution Timer instance
4318 * @param Timer This parameter can be one of the following values:
4319 * @arg @ref LL_HRTIM_TIMER_MASTER
4320 * @arg @ref LL_HRTIM_TIMER_A
4321 * @arg @ref LL_HRTIM_TIMER_B
4322 * @arg @ref LL_HRTIM_TIMER_C
4323 * @arg @ref LL_HRTIM_TIMER_D
4324 * @arg @ref LL_HRTIM_TIMER_E
4325 * @arg @ref LL_HRTIM_TIMER_F
4326 * @param UpdateTrig This parameter can be one of the following values:
4327 *
4328 * For the master timer this parameter can be one of the following values:
4329 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4330 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4331 *
4332 * For timer A..F this parameter can be:
4333 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4334 * or a combination of the following values:
4335 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4336 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4337 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4338 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4339 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4340 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4341 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4342 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4343 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4344 * @retval None
4345 */
LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateTrig)4346 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
4347 {
4348 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4349 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4350 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4351 }
4352
4353 /**
4354 * @brief Get the timer register update trigger.
4355 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
4356 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
4357 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
4358 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
4359 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
4360 * TIMxCR TFU LL_HRTIM_TIM_GetUpdateTrig\n
4361 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
4362 * @param HRTIMx High Resolution Timer instance
4363 * @param Timer This parameter can be one of the following values:
4364 * @arg @ref LL_HRTIM_TIMER_MASTER
4365 * @arg @ref LL_HRTIM_TIMER_A
4366 * @arg @ref LL_HRTIM_TIMER_B
4367 * @arg @ref LL_HRTIM_TIMER_C
4368 * @arg @ref LL_HRTIM_TIMER_D
4369 * @arg @ref LL_HRTIM_TIMER_E
4370 * @arg @ref LL_HRTIM_TIMER_F
4371 * @retval UpdateTrig Returned value can be one of the following values:
4372 *
4373 * For the master timer this parameter can be one of the following values:
4374 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4375 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4376 *
4377 * For timer A..F this parameter can be:
4378 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4379 * or a combination of the following values:
4380 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4381 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4382 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4383 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4384 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4385 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4386 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4387 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4388 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4389 */
LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4390 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4391 {
4392 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4393 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4394 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4395 }
4396
4397 /**
4398 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
4399 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
4400 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
4401 * @param HRTIMx High Resolution Timer instance
4402 * @param Timer This parameter can be one of the following values:
4403 * @arg @ref LL_HRTIM_TIMER_MASTER
4404 * @arg @ref LL_HRTIM_TIMER_A
4405 * @arg @ref LL_HRTIM_TIMER_B
4406 * @arg @ref LL_HRTIM_TIMER_C
4407 * @arg @ref LL_HRTIM_TIMER_D
4408 * @arg @ref LL_HRTIM_TIMER_E
4409 * @arg @ref LL_HRTIM_TIMER_F
4410 * @param UpdateGating This parameter can be one of the following values:
4411 *
4412 * For the master timer this parameter can be one of the following values:
4413 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4414 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4415 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4416 *
4417 * For the timer A..F this parameter can be one of the following values:
4418 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4419 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4420 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4421 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4422 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4423 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4424 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4425 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4426 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4427 * @retval None
4428 */
LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateGating)4429 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
4430 {
4431 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4432 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4433 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
4434 }
4435
4436 /**
4437 * @brief Get the timer registers update condition.
4438 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
4439 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
4440 * @param HRTIMx High Resolution Timer instance
4441 * @param Timer This parameter can be one of the following values:
4442 * @arg @ref LL_HRTIM_TIMER_MASTER
4443 * @arg @ref LL_HRTIM_TIMER_A
4444 * @arg @ref LL_HRTIM_TIMER_B
4445 * @arg @ref LL_HRTIM_TIMER_C
4446 * @arg @ref LL_HRTIM_TIMER_D
4447 * @arg @ref LL_HRTIM_TIMER_E
4448 * @arg @ref LL_HRTIM_TIMER_F
4449 * @retval UpdateGating Returned value can be one of the following values:
4450 *
4451 * For the master timer this parameter can be one of the following values:
4452 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4453 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4454 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4455 *
4456 * For the timer A..F this parameter can be one of the following values:
4457 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4458 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4459 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4460 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4461 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4462 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4463 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4464 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4465 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4466 */
LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4467 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4468 {
4469 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4470 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4471 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
4472 }
4473
4474 /**
4475 * @brief Enable the push-pull mode.
4476 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
4477 * @param HRTIMx High Resolution Timer instance
4478 * @param Timer This parameter can be one of the following values:
4479 * @arg @ref LL_HRTIM_TIMER_A
4480 * @arg @ref LL_HRTIM_TIMER_B
4481 * @arg @ref LL_HRTIM_TIMER_C
4482 * @arg @ref LL_HRTIM_TIMER_D
4483 * @arg @ref LL_HRTIM_TIMER_E
4484 * @arg @ref LL_HRTIM_TIMER_F
4485 * @retval None
4486 */
LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4487 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4488 {
4489 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4490 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4491 REG_OFFSET_TAB_TIMER[iTimer]));
4492 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4493 }
4494
4495 /**
4496 * @brief Disable the push-pull mode.
4497 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
4498 * @param HRTIMx High Resolution Timer instance
4499 * @param Timer This parameter can be one of the following values:
4500 * @arg @ref LL_HRTIM_TIMER_A
4501 * @arg @ref LL_HRTIM_TIMER_B
4502 * @arg @ref LL_HRTIM_TIMER_C
4503 * @arg @ref LL_HRTIM_TIMER_D
4504 * @arg @ref LL_HRTIM_TIMER_E
4505 * @arg @ref LL_HRTIM_TIMER_F
4506 * @retval None
4507 */
LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4508 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4509 {
4510 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4511 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4512 REG_OFFSET_TAB_TIMER[iTimer]));
4513 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4514 }
4515
4516 /**
4517 * @brief Indicate whether the push-pull mode is enabled.
4518 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
4519 * @param HRTIMx High Resolution Timer instance
4520 * @param Timer This parameter can be one of the following values:
4521 * @arg @ref LL_HRTIM_TIMER_A
4522 * @arg @ref LL_HRTIM_TIMER_B
4523 * @arg @ref LL_HRTIM_TIMER_C
4524 * @arg @ref LL_HRTIM_TIMER_D
4525 * @arg @ref LL_HRTIM_TIMER_E
4526 * @arg @ref LL_HRTIM_TIMER_F
4527 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
4528 */
LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4529 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4530 {
4531 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4532 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4533 REG_OFFSET_TAB_TIMER[iTimer]));
4534 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
4535 }
4536
4537 /**
4538 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
4539 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
4540 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
4541 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
4542 * @param HRTIMx High Resolution Timer instance
4543 * @param Timer This parameter can be one of the following values:
4544 * @arg @ref LL_HRTIM_TIMER_A
4545 * @arg @ref LL_HRTIM_TIMER_B
4546 * @arg @ref LL_HRTIM_TIMER_C
4547 * @arg @ref LL_HRTIM_TIMER_D
4548 * @arg @ref LL_HRTIM_TIMER_E
4549 * @arg @ref LL_HRTIM_TIMER_F
4550 * @param CompareUnit This parameter can be one of the following values:
4551 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4552 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4553 * @param Mode This parameter can be one of the following values:
4554 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4555 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4556 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4557 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4558 * @retval None
4559 */
LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit,uint32_t Mode)4560 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
4561 uint32_t Mode)
4562 {
4563 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4564 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4565 REG_OFFSET_TAB_TIMER[iTimer]));
4566 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4567 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
4568 }
4569
4570 /**
4571 * @brief Get the functioning mode of the compare unit.
4572 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
4573 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
4574 * @param HRTIMx High Resolution Timer instance
4575 * @param Timer This parameter can be one of the following values:
4576 * @arg @ref LL_HRTIM_TIMER_A
4577 * @arg @ref LL_HRTIM_TIMER_B
4578 * @arg @ref LL_HRTIM_TIMER_C
4579 * @arg @ref LL_HRTIM_TIMER_D
4580 * @arg @ref LL_HRTIM_TIMER_E
4581 * @arg @ref LL_HRTIM_TIMER_F
4582 * @param CompareUnit This parameter can be one of the following values:
4583 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4584 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4585 * @retval Mode Returned value can be one of the following values:
4586 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4587 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4588 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4589 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4590 */
LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit)4591 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
4592 {
4593 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4594 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4595 REG_OFFSET_TAB_TIMER[iTimer]));
4596 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4597 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
4598 }
4599
4600 /**
4601 * @brief Set the timer counter value.
4602 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
4603 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
4604 * @note This function can only be called when the timer is stopped.
4605 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
4606 * significant bits of the counter are not significant. They cannot be
4607 * written and return 0 when read.
4608 * @note The timer behavior is not guaranteed if the counter value is set above
4609 * the period.
4610 * @param HRTIMx High Resolution Timer instance
4611 * @param Timer This parameter can be one of the following values:
4612 * @arg @ref LL_HRTIM_TIMER_MASTER
4613 * @arg @ref LL_HRTIM_TIMER_A
4614 * @arg @ref LL_HRTIM_TIMER_B
4615 * @arg @ref LL_HRTIM_TIMER_C
4616 * @arg @ref LL_HRTIM_TIMER_D
4617 * @arg @ref LL_HRTIM_TIMER_E
4618 * @arg @ref LL_HRTIM_TIMER_F
4619 * @param Counter Value between 0 and 0xFFFF
4620 * @retval None
4621 */
LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Counter)4622 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
4623 {
4624 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4625 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4626 REG_OFFSET_TAB_TIMER[iTimer]));
4627 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
4628 }
4629
4630 /**
4631 * @brief Get actual timer counter value.
4632 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
4633 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
4634 * @param HRTIMx High Resolution Timer instance
4635 * @param Timer This parameter can be one of the following values:
4636 * @arg @ref LL_HRTIM_TIMER_MASTER
4637 * @arg @ref LL_HRTIM_TIMER_A
4638 * @arg @ref LL_HRTIM_TIMER_B
4639 * @arg @ref LL_HRTIM_TIMER_C
4640 * @arg @ref LL_HRTIM_TIMER_D
4641 * @arg @ref LL_HRTIM_TIMER_E
4642 * @arg @ref LL_HRTIM_TIMER_F
4643 * @retval Counter Value between 0 and 0xFFFF
4644 */
LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4645 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4646 {
4647 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4648 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4649 REG_OFFSET_TAB_TIMER[iTimer]));
4650 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
4651 }
4652
4653 /**
4654 * @brief Set the timer period value.
4655 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
4656 * PERxR PERx LL_HRTIM_TIM_SetPeriod
4657 * @param HRTIMx High Resolution Timer instance
4658 * @param Timer This parameter can be one of the following values:
4659 * @arg @ref LL_HRTIM_TIMER_MASTER
4660 * @arg @ref LL_HRTIM_TIMER_A
4661 * @arg @ref LL_HRTIM_TIMER_B
4662 * @arg @ref LL_HRTIM_TIMER_C
4663 * @arg @ref LL_HRTIM_TIMER_D
4664 * @arg @ref LL_HRTIM_TIMER_E
4665 * @arg @ref LL_HRTIM_TIMER_F
4666 * @param Period Value between 0 and 0xFFFF
4667 * @retval None
4668 */
LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Period)4669 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
4670 {
4671 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4672 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4673 REG_OFFSET_TAB_TIMER[iTimer]));
4674 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
4675 }
4676
4677 /**
4678 * @brief Get actual timer period value.
4679 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
4680 * PERxR PERx LL_HRTIM_TIM_GetPeriod
4681 * @param HRTIMx High Resolution Timer instance
4682 * @param Timer This parameter can be one of the following values:
4683 * @arg @ref LL_HRTIM_TIMER_MASTER
4684 * @arg @ref LL_HRTIM_TIMER_A
4685 * @arg @ref LL_HRTIM_TIMER_B
4686 * @arg @ref LL_HRTIM_TIMER_C
4687 * @arg @ref LL_HRTIM_TIMER_D
4688 * @arg @ref LL_HRTIM_TIMER_E
4689 * @arg @ref LL_HRTIM_TIMER_F
4690 * @retval Period Value between 0 and 0xFFFF
4691 */
LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4692 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4693 {
4694 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4695 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4696 REG_OFFSET_TAB_TIMER[iTimer]));
4697 return (READ_BIT(*pReg, HRTIM_MPER_MPER));
4698 }
4699
4700 /**
4701 * @brief Set the timer repetition period value.
4702 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
4703 * REPxR REPx LL_HRTIM_TIM_SetRepetition
4704 * @param HRTIMx High Resolution Timer instance
4705 * @param Timer This parameter can be one of the following values:
4706 * @arg @ref LL_HRTIM_TIMER_MASTER
4707 * @arg @ref LL_HRTIM_TIMER_A
4708 * @arg @ref LL_HRTIM_TIMER_B
4709 * @arg @ref LL_HRTIM_TIMER_C
4710 * @arg @ref LL_HRTIM_TIMER_D
4711 * @arg @ref LL_HRTIM_TIMER_E
4712 * @arg @ref LL_HRTIM_TIMER_F
4713 * @param Repetition Value between 0 and 0xFF
4714 * @retval None
4715 */
LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Repetition)4716 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
4717 {
4718 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4719 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4720 REG_OFFSET_TAB_TIMER[iTimer]));
4721 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
4722 }
4723
4724 /**
4725 * @brief Get actual timer repetition period value.
4726 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
4727 * REPxR REPx LL_HRTIM_TIM_GetRepetition
4728 * @param HRTIMx High Resolution Timer instance
4729 * @param Timer This parameter can be one of the following values:
4730 * @arg @ref LL_HRTIM_TIMER_MASTER
4731 * @arg @ref LL_HRTIM_TIMER_A
4732 * @arg @ref LL_HRTIM_TIMER_B
4733 * @arg @ref LL_HRTIM_TIMER_C
4734 * @arg @ref LL_HRTIM_TIMER_D
4735 * @arg @ref LL_HRTIM_TIMER_E
4736 * @arg @ref LL_HRTIM_TIMER_F
4737 * @retval Repetition Value between 0 and 0xFF
4738 */
LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4739 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4740 {
4741 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4742 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4743 REG_OFFSET_TAB_TIMER[iTimer]));
4744 return (READ_BIT(*pReg, HRTIM_MREP_MREP));
4745 }
4746
4747 /**
4748 * @brief Set the compare value of the compare unit 1.
4749 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
4750 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
4751 * @param HRTIMx High Resolution Timer instance
4752 * @param Timer This parameter can be one of the following values:
4753 * @arg @ref LL_HRTIM_TIMER_MASTER
4754 * @arg @ref LL_HRTIM_TIMER_A
4755 * @arg @ref LL_HRTIM_TIMER_B
4756 * @arg @ref LL_HRTIM_TIMER_C
4757 * @arg @ref LL_HRTIM_TIMER_D
4758 * @arg @ref LL_HRTIM_TIMER_E
4759 * @arg @ref LL_HRTIM_TIMER_F
4760 * @param CompareValue Compare value must be above or equal to 3
4761 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4762 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4763 * @retval None
4764 */
LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4765 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4766 {
4767 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4768 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4769 REG_OFFSET_TAB_TIMER[iTimer]));
4770 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
4771 }
4772
4773 /**
4774 * @brief Get actual compare value of the compare unit 1.
4775 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
4776 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
4777 * @param HRTIMx High Resolution Timer instance
4778 * @param Timer This parameter can be one of the following values:
4779 * @arg @ref LL_HRTIM_TIMER_MASTER
4780 * @arg @ref LL_HRTIM_TIMER_A
4781 * @arg @ref LL_HRTIM_TIMER_B
4782 * @arg @ref LL_HRTIM_TIMER_C
4783 * @arg @ref LL_HRTIM_TIMER_D
4784 * @arg @ref LL_HRTIM_TIMER_E
4785 * @arg @ref LL_HRTIM_TIMER_F
4786 * @retval CompareValue Compare value must be above or equal to 3
4787 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4788 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4789 */
LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4790 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4791 {
4792 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4793 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4794 REG_OFFSET_TAB_TIMER[iTimer]));
4795 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
4796 }
4797
4798 /**
4799 * @brief Set the compare value of the compare unit 2.
4800 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
4801 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
4802 * @param HRTIMx High Resolution Timer instance
4803 * @param Timer This parameter can be one of the following values:
4804 * @arg @ref LL_HRTIM_TIMER_MASTER
4805 * @arg @ref LL_HRTIM_TIMER_A
4806 * @arg @ref LL_HRTIM_TIMER_B
4807 * @arg @ref LL_HRTIM_TIMER_C
4808 * @arg @ref LL_HRTIM_TIMER_D
4809 * @arg @ref LL_HRTIM_TIMER_E
4810 * @arg @ref LL_HRTIM_TIMER_F
4811 * @param CompareValue Compare value must be above or equal to 3
4812 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4813 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4814 * @retval None
4815 */
LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4816 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4817 {
4818 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4819 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4820 REG_OFFSET_TAB_TIMER[iTimer]));
4821 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
4822 }
4823
4824 /**
4825 * @brief Get actual compare value of the compare unit 2.
4826 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
4827 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
4828 * @param HRTIMx High Resolution Timer instance
4829 * @param Timer This parameter can be one of the following values:
4830 * @arg @ref LL_HRTIM_TIMER_MASTER
4831 * @arg @ref LL_HRTIM_TIMER_A
4832 * @arg @ref LL_HRTIM_TIMER_B
4833 * @arg @ref LL_HRTIM_TIMER_C
4834 * @arg @ref LL_HRTIM_TIMER_D
4835 * @arg @ref LL_HRTIM_TIMER_E
4836 * @arg @ref LL_HRTIM_TIMER_F
4837 * @retval CompareValue Compare value must be above or equal to 3
4838 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4839 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4840 */
LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4841 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4842 {
4843 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4844 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4845 REG_OFFSET_TAB_TIMER[iTimer]));
4846 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
4847 }
4848
4849 /**
4850 * @brief Set the compare value of the compare unit 3.
4851 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
4852 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
4853 * @param HRTIMx High Resolution Timer instance
4854 * @param Timer This parameter can be one of the following values:
4855 * @arg @ref LL_HRTIM_TIMER_MASTER
4856 * @arg @ref LL_HRTIM_TIMER_A
4857 * @arg @ref LL_HRTIM_TIMER_B
4858 * @arg @ref LL_HRTIM_TIMER_C
4859 * @arg @ref LL_HRTIM_TIMER_D
4860 * @arg @ref LL_HRTIM_TIMER_E
4861 * @arg @ref LL_HRTIM_TIMER_F
4862 * @param CompareValue Compare value must be above or equal to 3
4863 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4864 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4865 * @retval None
4866 */
LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4867 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4868 {
4869 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4870 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4871 REG_OFFSET_TAB_TIMER[iTimer]));
4872 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
4873 }
4874
4875 /**
4876 * @brief Get actual compare value of the compare unit 3.
4877 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
4878 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
4879 * @param HRTIMx High Resolution Timer instance
4880 * @param Timer This parameter can be one of the following values:
4881 * @arg @ref LL_HRTIM_TIMER_MASTER
4882 * @arg @ref LL_HRTIM_TIMER_A
4883 * @arg @ref LL_HRTIM_TIMER_B
4884 * @arg @ref LL_HRTIM_TIMER_C
4885 * @arg @ref LL_HRTIM_TIMER_D
4886 * @arg @ref LL_HRTIM_TIMER_E
4887 * @arg @ref LL_HRTIM_TIMER_F
4888 * @retval CompareValue Compare value must be above or equal to 3
4889 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4890 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4891 */
LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4892 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4893 {
4894 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4895 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4896 REG_OFFSET_TAB_TIMER[iTimer]));
4897 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
4898 }
4899
4900 /**
4901 * @brief Set the compare value of the compare unit 4.
4902 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
4903 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
4904 * @param HRTIMx High Resolution Timer instance
4905 * @param Timer This parameter can be one of the following values:
4906 * @arg @ref LL_HRTIM_TIMER_MASTER
4907 * @arg @ref LL_HRTIM_TIMER_A
4908 * @arg @ref LL_HRTIM_TIMER_B
4909 * @arg @ref LL_HRTIM_TIMER_C
4910 * @arg @ref LL_HRTIM_TIMER_D
4911 * @arg @ref LL_HRTIM_TIMER_E
4912 * @arg @ref LL_HRTIM_TIMER_F
4913 * @param CompareValue Compare value must be above or equal to 3
4914 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4915 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4916 * @retval None
4917 */
LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4918 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4919 {
4920 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4921 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4922 REG_OFFSET_TAB_TIMER[iTimer]));
4923 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
4924 }
4925
4926 /**
4927 * @brief Get actual compare value of the compare unit 4.
4928 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
4929 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
4930 * @param HRTIMx High Resolution Timer instance
4931 * @param Timer This parameter can be one of the following values:
4932 * @arg @ref LL_HRTIM_TIMER_MASTER
4933 * @arg @ref LL_HRTIM_TIMER_A
4934 * @arg @ref LL_HRTIM_TIMER_B
4935 * @arg @ref LL_HRTIM_TIMER_C
4936 * @arg @ref LL_HRTIM_TIMER_D
4937 * @arg @ref LL_HRTIM_TIMER_E
4938 * @arg @ref LL_HRTIM_TIMER_F
4939 * @retval CompareValue Compare value must be above or equal to 3
4940 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4941 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4942 */
LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4943 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4944 {
4945 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4946 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4947 REG_OFFSET_TAB_TIMER[iTimer]));
4948 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
4949 }
4950
4951 /**
4952 * @brief Set the reset trigger of a timer counter.
4953 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
4954 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
4955 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
4956 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
4957 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
4958 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
4959 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
4960 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
4961 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
4962 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
4963 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
4964 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
4965 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
4966 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
4967 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
4968 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
4969 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
4970 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
4971 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
4972 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
4973 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
4974 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
4975 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
4976 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
4977 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
4978 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
4979 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
4980 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
4981 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
4982 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig\n
4983 * RSTxR TIMFCMP1 LL_HRTIM_TIM_SetResetTrig\n
4984 * RSTxR TIMFCMP2 LL_HRTIM_TIM_SetResetTrig
4985 * @note The reset of the timer counter can be triggered by up to 30 events
4986 * that can be selected among the following sources:
4987 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
4988 * @arg The master timer: Reset and Compare 1..4 (5 events).
4989 * @arg The external events EXTEVNT1..10 (10 events).
4990 * @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
4991 * @param HRTIMx High Resolution Timer instance
4992 * @param Timer This parameter can be one of the following values:
4993 * @arg @ref LL_HRTIM_TIMER_A
4994 * @arg @ref LL_HRTIM_TIMER_B
4995 * @arg @ref LL_HRTIM_TIMER_C
4996 * @arg @ref LL_HRTIM_TIMER_D
4997 * @arg @ref LL_HRTIM_TIMER_E
4998 * @arg @ref LL_HRTIM_TIMER_F
4999 * @param ResetTrig This parameter can be a combination of the following values:
5000 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5001 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5002 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5003 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5004 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5005 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5006 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5007 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5008 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5009 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5010 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5011 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5012 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5013 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5014 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5015 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5016 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5017 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5018 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5019 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5020 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5021 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5022 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5023 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5024 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5025 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5026 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5027 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5028 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5029 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5030 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5031 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5032 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5033 * @retval None
5034 */
LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t ResetTrig)5035 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
5036 {
5037 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5038 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5039 REG_OFFSET_TAB_TIMER[iTimer]));
5040 WRITE_REG(*pReg, ResetTrig);
5041 }
5042
5043 /**
5044 * @brief Get actual reset trigger of a timer counter.
5045 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
5046 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
5047 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
5048 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
5049 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
5050 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
5051 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
5052 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
5053 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
5054 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
5055 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
5056 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
5057 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
5058 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
5059 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
5060 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
5061 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
5062 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
5063 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
5064 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
5065 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
5066 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
5067 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
5068 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
5069 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
5070 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
5071 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
5072 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
5073 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
5074 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig\n
5075 * RSTxR TIMFCMP1 LL_HRTIM_TIM_GetResetTrig\n
5076 * RSTxR TIMFCMP2 LL_HRTIM_TIM_GetResetTrig
5077 * @param HRTIMx High Resolution Timer instance
5078 * @param Timer This parameter can be one of the following values:
5079 * @arg @ref LL_HRTIM_TIMER_A
5080 * @arg @ref LL_HRTIM_TIMER_B
5081 * @arg @ref LL_HRTIM_TIMER_C
5082 * @arg @ref LL_HRTIM_TIMER_D
5083 * @arg @ref LL_HRTIM_TIMER_E
5084 * @arg @ref LL_HRTIM_TIMER_F
5085 * @retval ResetTrig Returned value can be one of the following values:
5086 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5087 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5088 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5089 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5090 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5091 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5092 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5093 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5094 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5095 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5096 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5097 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5098 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5099 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5100 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5101 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5102 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5103 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5104 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5105 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5106 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5107 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5108 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5109 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5110 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5111 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5112 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5113 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5114 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5115 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5116 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5117 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5118 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5119 */
LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5120 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5121 {
5122 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5123 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5124 REG_OFFSET_TAB_TIMER[iTimer]));
5125 return (READ_REG(*pReg));
5126 }
5127
5128 /**
5129 * @brief Get captured value for capture unit 1.
5130 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
5131 * @param HRTIMx High Resolution Timer instance
5132 * @param Timer This parameter can be one of the following values:
5133 * @arg @ref LL_HRTIM_TIMER_A
5134 * @arg @ref LL_HRTIM_TIMER_B
5135 * @arg @ref LL_HRTIM_TIMER_C
5136 * @arg @ref LL_HRTIM_TIMER_D
5137 * @arg @ref LL_HRTIM_TIMER_E
5138 * @arg @ref LL_HRTIM_TIMER_F
5139 * @retval Captured value
5140 */
LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5141 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5142 {
5143 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5144 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5145 REG_OFFSET_TAB_TIMER[iTimer]));
5146 return (READ_REG(*pReg));
5147 }
5148
5149 /**
5150 * @brief Get the counting direction when capture 1 event occurred.
5151 * @rmtoll CPT1xR DIR LL_HRTIM_TIM_GetCapture1Direction
5152 * @param HRTIMx High Resolution Timer instance
5153 * @param Timer This parameter can be one of the following values:
5154 * @arg @ref LL_HRTIM_TIMER_A
5155 * @arg @ref LL_HRTIM_TIMER_B
5156 * @arg @ref LL_HRTIM_TIMER_C
5157 * @arg @ref LL_HRTIM_TIMER_D
5158 * @arg @ref LL_HRTIM_TIMER_E
5159 * @arg @ref LL_HRTIM_TIMER_F
5160 * @retval Filter This parameter can be one of the following values:
5161 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5162 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5163 */
LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5164 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5165 {
5166 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5167 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5168 REG_OFFSET_TAB_TIMER[iTimer]));
5169 return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5170 }
5171
5172 /**
5173 * @brief Get captured value for capture unit 2.
5174 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
5175 * @param HRTIMx High Resolution Timer instance
5176 * @param Timer This parameter can be one of the following values:
5177 * @arg @ref LL_HRTIM_TIMER_A
5178 * @arg @ref LL_HRTIM_TIMER_B
5179 * @arg @ref LL_HRTIM_TIMER_C
5180 * @arg @ref LL_HRTIM_TIMER_D
5181 * @arg @ref LL_HRTIM_TIMER_E
5182 * @arg @ref LL_HRTIM_TIMER_F
5183 * @retval Captured value
5184 */
LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5185 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5186 {
5187 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5188 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5189 REG_OFFSET_TAB_TIMER[iTimer]));
5190 return (READ_REG(*pReg));
5191 }
5192
5193 /**
5194 * @brief Get the counting direction when capture 2 event occurred.
5195 * @rmtoll CPT2xR DIR LL_HRTIM_TIM_GetCapture2Direction
5196 * @param HRTIMx High Resolution Timer instance
5197 * @param Timer This parameter can be one of the following values:
5198 * @arg @ref LL_HRTIM_TIMER_A
5199 * @arg @ref LL_HRTIM_TIMER_B
5200 * @arg @ref LL_HRTIM_TIMER_C
5201 * @arg @ref LL_HRTIM_TIMER_D
5202 * @arg @ref LL_HRTIM_TIMER_E
5203 * @arg @ref LL_HRTIM_TIMER_F
5204 * @retval Filter This parameter can be one of the following values:
5205 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5206 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5207 */
LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5208 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5209 {
5210 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5211 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5212 REG_OFFSET_TAB_TIMER[iTimer]));
5213 return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5214 }
5215
5216 /**
5217 * @brief Set the trigger of a capture unit for a given timer.
5218 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
5219 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
5220 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
5221 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
5222 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
5223 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
5224 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
5225 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
5226 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
5227 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
5228 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
5229 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
5230 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
5231 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
5232 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5233 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5234 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
5235 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
5236 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5237 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5238 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
5239 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
5240 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5241 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5242 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
5243 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
5244 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5245 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5246 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
5247 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
5248 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5249 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5250 * CPT1xCR TF1SET LL_HRTIM_TIM_SetCaptureTrig\n
5251 * CPT1xCR TF1RST LL_HRTIM_TIM_SetCaptureTrig\n
5252 * CPT1xCR TFCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5253 * CPT1xCR TFCMP2 LL_HRTIM_TIM_SetCaptureTrig
5254 * @param HRTIMx High Resolution Timer instance
5255 * @param Timer This parameter can be one of the following values:
5256 * @arg @ref LL_HRTIM_TIMER_A
5257 * @arg @ref LL_HRTIM_TIMER_B
5258 * @arg @ref LL_HRTIM_TIMER_C
5259 * @arg @ref LL_HRTIM_TIMER_D
5260 * @arg @ref LL_HRTIM_TIMER_E
5261 * @arg @ref LL_HRTIM_TIMER_F
5262 * @param CaptureUnit This parameter can be one of the following values:
5263 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5264 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5265 * @param CaptureTrig This parameter can be a combination of the following values:
5266 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5267 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5268 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5269 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5270 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5271 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5272 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5273 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5274 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5275 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5276 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5277 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5278 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5279 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5280 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5281 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5282 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5283 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5284 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5285 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5286 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5287 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5288 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5289 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5290 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5291 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5292 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5293 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5294 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5295 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5296 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5297 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5298 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5299 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5300 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5301 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5302 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5303 * @retval None
5304 */
LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit,uint64_t CaptureTrig)5305 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
5306 uint64_t CaptureTrig)
5307 {
5308 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5309 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5310 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
5311
5312 uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
5313 uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
5314
5315 cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
5316
5317 WRITE_REG(*pReg, (cfg1 | cfg2));
5318
5319 }
5320
5321 /**
5322 * @brief Get actual trigger of a capture unit for a given timer.
5323 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
5324 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
5325 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
5326 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
5327 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
5328 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
5329 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
5330 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
5331 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
5332 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
5333 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
5334 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
5335 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
5336 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
5337 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5338 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5339 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
5340 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
5341 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5342 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5343 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
5344 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
5345 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5346 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5347 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
5348 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
5349 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5350 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5351 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
5352 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
5353 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5354 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5355 * CPT1xCR TF1SET LL_HRTIM_TIM_GetCaptureTrig\n
5356 * CPT1xCR TF1RST LL_HRTIM_TIM_GetCaptureTrig\n
5357 * CPT1xCR TFCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5358 * CPT1xCR TFCMP2 LL_HRTIM_TIM_GetCaptureTrig
5359 * @param HRTIMx High Resolution Timer instance
5360 * @param Timer This parameter can be one of the following values:
5361 * @arg @ref LL_HRTIM_TIMER_A
5362 * @arg @ref LL_HRTIM_TIMER_B
5363 * @arg @ref LL_HRTIM_TIMER_C
5364 * @arg @ref LL_HRTIM_TIMER_D
5365 * @arg @ref LL_HRTIM_TIMER_E
5366 * @arg @ref LL_HRTIM_TIMER_F
5367 * @param CaptureUnit This parameter can be one of the following values:
5368 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5369 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5370 * @retval CaptureTrig This parameter can be a combination of the following values:
5371 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5372 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5373 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5374 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5375 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5376 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5377 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5378 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5379 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5380 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5381 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5382 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5383 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5384 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5385 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5386 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5387 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5388 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5389 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5390 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5391 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5392 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5393 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5394 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5395 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5396 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5397 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5398 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5399 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5400 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5401 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5402 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5403 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5404 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5405 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5406 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5407 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5408 */
LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit)5409 __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
5410 {
5411 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5412 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5413 (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
5414
5415 uint64_t cfg;
5416 uint32_t CaptureTrig = READ_REG(*pReg);
5417
5418 cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
5419
5420 return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
5421 }
5422
5423 /**
5424 * @brief Enable deadtime insertion for a given timer.
5425 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
5426 * @param HRTIMx High Resolution Timer instance
5427 * @param Timer This parameter can be one of the following values:
5428 * @arg @ref LL_HRTIM_TIMER_A
5429 * @arg @ref LL_HRTIM_TIMER_B
5430 * @arg @ref LL_HRTIM_TIMER_C
5431 * @arg @ref LL_HRTIM_TIMER_D
5432 * @arg @ref LL_HRTIM_TIMER_E
5433 * @arg @ref LL_HRTIM_TIMER_F
5434 * @retval None
5435 */
LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5436 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5437 {
5438 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5439 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5440 REG_OFFSET_TAB_TIMER[iTimer]));
5441 SET_BIT(*pReg, HRTIM_OUTR_DTEN);
5442 }
5443
5444 /**
5445 * @brief Disable deadtime insertion for a given timer.
5446 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
5447 * @param HRTIMx High Resolution Timer instance
5448 * @param Timer This parameter can be one of the following values:
5449 * @arg @ref LL_HRTIM_TIMER_A
5450 * @arg @ref LL_HRTIM_TIMER_B
5451 * @arg @ref LL_HRTIM_TIMER_C
5452 * @arg @ref LL_HRTIM_TIMER_D
5453 * @arg @ref LL_HRTIM_TIMER_E
5454 * @arg @ref LL_HRTIM_TIMER_F
5455 * @retval None
5456 */
LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5457 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5458 {
5459 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5460 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5461 REG_OFFSET_TAB_TIMER[iTimer]));
5462 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
5463 }
5464
5465 /**
5466 * @brief Indicate whether deadtime insertion is enabled for a given timer.
5467 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
5468 * @param HRTIMx High Resolution Timer instance
5469 * @param Timer This parameter can be one of the following values:
5470 * @arg @ref LL_HRTIM_TIMER_A
5471 * @arg @ref LL_HRTIM_TIMER_B
5472 * @arg @ref LL_HRTIM_TIMER_C
5473 * @arg @ref LL_HRTIM_TIMER_D
5474 * @arg @ref LL_HRTIM_TIMER_E
5475 * @arg @ref LL_HRTIM_TIMER_F
5476 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
5477 */
LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5478 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5479 {
5480 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5481 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5482 REG_OFFSET_TAB_TIMER[iTimer]));
5483
5484 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
5485 }
5486
5487 /**
5488 * @brief Set the delayed protection (DLYPRT) mode.
5489 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
5490 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
5491 * @note This function must be called prior enabling the delayed protection
5492 * @note Balanced Idle mode is only available in push-pull mode
5493 * @param HRTIMx High Resolution Timer instance
5494 * @param Timer This parameter can be one of the following values:
5495 * @arg @ref LL_HRTIM_TIMER_A
5496 * @arg @ref LL_HRTIM_TIMER_B
5497 * @arg @ref LL_HRTIM_TIMER_C
5498 * @arg @ref LL_HRTIM_TIMER_D
5499 * @arg @ref LL_HRTIM_TIMER_E
5500 * @arg @ref LL_HRTIM_TIMER_F
5501 * @param DLYPRTMode Delayed protection (DLYPRT) mode
5502 *
5503 * For timers A, B and C this parameter can be one of the following values:
5504 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5505 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5506 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5507 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5508 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5509 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5510 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5511 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5512 *
5513 * For timers D, E and F this parameter can be one of the following values:
5514 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5515 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5516 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5517 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5518 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5519 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5520 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5521 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5522 * @retval None
5523 */
LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DLYPRTMode)5524 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
5525 {
5526 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5527 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5528 REG_OFFSET_TAB_TIMER[iTimer]));
5529 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
5530 }
5531
5532 /**
5533 * @brief Get the delayed protection (DLYPRT) mode.
5534 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
5535 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
5536 * @param HRTIMx High Resolution Timer instance
5537 * @param Timer This parameter can be one of the following values:
5538 * @arg @ref LL_HRTIM_TIMER_A
5539 * @arg @ref LL_HRTIM_TIMER_B
5540 * @arg @ref LL_HRTIM_TIMER_C
5541 * @arg @ref LL_HRTIM_TIMER_D
5542 * @arg @ref LL_HRTIM_TIMER_E
5543 * @arg @ref LL_HRTIM_TIMER_F
5544 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
5545 *
5546 * For timers A, B and C this parameter can be one of the following values:
5547 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5548 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5549 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5550 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5551 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5552 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5553 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5554 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5555 *
5556 * For timers D, E and F this parameter can be one of the following values:
5557 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5558 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5559 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5560 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5561 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5562 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5563 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5564 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5565 */
LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5566 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5567 {
5568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5569 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5570 REG_OFFSET_TAB_TIMER[iTimer]));
5571 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
5572 }
5573
5574 /**
5575 * @brief Enable delayed protection (DLYPRT) for a given timer.
5576 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
5577 * @note This function must not be called once the concerned timer is enabled
5578 * @param HRTIMx High Resolution Timer instance
5579 * @param Timer This parameter can be one of the following values:
5580 * @arg @ref LL_HRTIM_TIMER_A
5581 * @arg @ref LL_HRTIM_TIMER_B
5582 * @arg @ref LL_HRTIM_TIMER_C
5583 * @arg @ref LL_HRTIM_TIMER_D
5584 * @arg @ref LL_HRTIM_TIMER_E
5585 * @arg @ref LL_HRTIM_TIMER_F
5586 * @retval None
5587 */
LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5588 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5589 {
5590 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5591 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5592 REG_OFFSET_TAB_TIMER[iTimer]));
5593 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5594 }
5595
5596 /**
5597 * @brief Disable delayed protection (DLYPRT) for a given timer.
5598 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
5599 * @note This function must not be called once the concerned timer is enabled
5600 * @param HRTIMx High Resolution Timer instance
5601 * @param Timer This parameter can be one of the following values:
5602 * @arg @ref LL_HRTIM_TIMER_A
5603 * @arg @ref LL_HRTIM_TIMER_B
5604 * @arg @ref LL_HRTIM_TIMER_C
5605 * @arg @ref LL_HRTIM_TIMER_D
5606 * @arg @ref LL_HRTIM_TIMER_E
5607 * @arg @ref LL_HRTIM_TIMER_F
5608 * @retval None
5609 */
LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5610 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5611 {
5612 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5613 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5614 REG_OFFSET_TAB_TIMER[iTimer]));
5615 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5616 }
5617
5618 /**
5619 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
5620 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
5621 * @param HRTIMx High Resolution Timer instance
5622 * @param Timer This parameter can be one of the following values:
5623 * @arg @ref LL_HRTIM_TIMER_A
5624 * @arg @ref LL_HRTIM_TIMER_B
5625 * @arg @ref LL_HRTIM_TIMER_C
5626 * @arg @ref LL_HRTIM_TIMER_D
5627 * @arg @ref LL_HRTIM_TIMER_E
5628 * @arg @ref LL_HRTIM_TIMER_F
5629 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5630 */
LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5631 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5632 {
5633 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5634 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5635 REG_OFFSET_TAB_TIMER[iTimer]));
5636 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
5637 }
5638
5639 /**
5640 * @brief Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5641 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_EnableBIAR
5642 * @note This function must not be called once the concerned timer is enabled
5643 * @param HRTIMx High Resolution Timer instance
5644 * @param Timer This parameter can be one of the following values:
5645 * @arg @ref LL_HRTIM_TIMER_A
5646 * @arg @ref LL_HRTIM_TIMER_B
5647 * @arg @ref LL_HRTIM_TIMER_C
5648 * @arg @ref LL_HRTIM_TIMER_D
5649 * @arg @ref LL_HRTIM_TIMER_E
5650 * @arg @ref LL_HRTIM_TIMER_F
5651 * @retval None
5652 */
LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5653 __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5654 {
5655 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5656 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5657 REG_OFFSET_TAB_TIMER[iTimer]));
5658 SET_BIT(*pReg, HRTIM_OUTR_BIAR);
5659 }
5660
5661 /**
5662 * @brief Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5663 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_DisableBIAR
5664 * @note This function must not be called once the concerned timer is enabled
5665 * @param HRTIMx High Resolution Timer instance
5666 * @param Timer This parameter can be one of the following values:
5667 * @arg @ref LL_HRTIM_TIMER_A
5668 * @arg @ref LL_HRTIM_TIMER_B
5669 * @arg @ref LL_HRTIM_TIMER_C
5670 * @arg @ref LL_HRTIM_TIMER_D
5671 * @arg @ref LL_HRTIM_TIMER_E
5672 * @arg @ref LL_HRTIM_TIMER_F
5673 * @retval None
5674 */
LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5675 __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5676 {
5677 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5678 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
5679 REG_OFFSET_TAB_TIMER[iTimer]));
5680 CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
5681 }
5682
5683 /**
5684 * @brief Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
5685 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_IsEnabledBIAR
5686 * @param HRTIMx High Resolution Timer instance
5687 * @param Timer This parameter can be one of the following values:
5688 * @arg @ref LL_HRTIM_TIMER_A
5689 * @arg @ref LL_HRTIM_TIMER_B
5690 * @arg @ref LL_HRTIM_TIMER_C
5691 * @arg @ref LL_HRTIM_TIMER_D
5692 * @arg @ref LL_HRTIM_TIMER_E
5693 * @arg @ref LL_HRTIM_TIMER_F
5694 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5695 */
LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5696 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5697 {
5698 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5699 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5700 REG_OFFSET_TAB_TIMER[iTimer]));
5701
5702 return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
5703 }
5704
5705 /**
5706 * @brief Enable the fault channel(s) for a given timer.
5707 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
5708 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
5709 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
5710 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
5711 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault\n
5712 * FLTxR FLT6EN LL_HRTIM_TIM_EnableFault
5713 * @param HRTIMx High Resolution Timer instance
5714 * @param Timer This parameter can be one of the following values:
5715 * @arg @ref LL_HRTIM_TIMER_A
5716 * @arg @ref LL_HRTIM_TIMER_B
5717 * @arg @ref LL_HRTIM_TIMER_C
5718 * @arg @ref LL_HRTIM_TIMER_D
5719 * @arg @ref LL_HRTIM_TIMER_E
5720 * @arg @ref LL_HRTIM_TIMER_F
5721 * @param Faults This parameter can be a combination of the following values:
5722 * @arg @ref LL_HRTIM_FAULT_1
5723 * @arg @ref LL_HRTIM_FAULT_2
5724 * @arg @ref LL_HRTIM_FAULT_3
5725 * @arg @ref LL_HRTIM_FAULT_4
5726 * @arg @ref LL_HRTIM_FAULT_5
5727 * @arg @ref LL_HRTIM_FAULT_6
5728 * @retval None
5729 */
LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5730 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5731 {
5732 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5733 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5734 REG_OFFSET_TAB_TIMER[iTimer]));
5735 SET_BIT(*pReg, Faults);
5736 }
5737
5738 /**
5739 * @brief Disable the fault channel(s) for a given timer.
5740 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
5741 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
5742 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
5743 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
5744 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault\n
5745 * FLTxR FLT6EN LL_HRTIM_TIM_DisableFault
5746 * @param HRTIMx High Resolution Timer instance
5747 * @param Timer This parameter can be one of the following values:
5748 * @arg @ref LL_HRTIM_TIMER_A
5749 * @arg @ref LL_HRTIM_TIMER_B
5750 * @arg @ref LL_HRTIM_TIMER_C
5751 * @arg @ref LL_HRTIM_TIMER_D
5752 * @arg @ref LL_HRTIM_TIMER_E
5753 * @arg @ref LL_HRTIM_TIMER_F
5754 * @param Faults This parameter can be a combination of the following values:
5755 * @arg @ref LL_HRTIM_FAULT_1
5756 * @arg @ref LL_HRTIM_FAULT_2
5757 * @arg @ref LL_HRTIM_FAULT_3
5758 * @arg @ref LL_HRTIM_FAULT_4
5759 * @arg @ref LL_HRTIM_FAULT_5
5760 * @arg @ref LL_HRTIM_FAULT_6
5761 * @retval None
5762 */
LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5763 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5764 {
5765 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5766 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5767 REG_OFFSET_TAB_TIMER[iTimer]));
5768 CLEAR_BIT(*pReg, Faults);
5769 }
5770
5771 /**
5772 * @brief Indicate whether the fault channel is enabled for a given timer.
5773 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
5774 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
5775 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
5776 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
5777 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault\n
5778 * FLTxR FLT6EN LL_HRTIM_TIM_IsEnabledFault
5779 * @param HRTIMx High Resolution Timer instance
5780 * @param Timer This parameter can be one of the following values:
5781 * @arg @ref LL_HRTIM_TIMER_A
5782 * @arg @ref LL_HRTIM_TIMER_B
5783 * @arg @ref LL_HRTIM_TIMER_C
5784 * @arg @ref LL_HRTIM_TIMER_D
5785 * @arg @ref LL_HRTIM_TIMER_E
5786 * @arg @ref LL_HRTIM_TIMER_F
5787 * @param Fault This parameter can be one of the following values:
5788 * @arg @ref LL_HRTIM_FAULT_1
5789 * @arg @ref LL_HRTIM_FAULT_2
5790 * @arg @ref LL_HRTIM_FAULT_3
5791 * @arg @ref LL_HRTIM_FAULT_4
5792 * @arg @ref LL_HRTIM_FAULT_5
5793 * @arg @ref LL_HRTIM_FAULT_6
5794 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
5795 */
LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Fault)5796 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
5797 {
5798 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5799 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5800 REG_OFFSET_TAB_TIMER[iTimer]));
5801
5802 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
5803 }
5804
5805 /**
5806 * @brief Lock the fault conditioning set-up for a given timer.
5807 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
5808 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
5809 * @param HRTIMx High Resolution Timer instance
5810 * @param Timer This parameter can be one of the following values:
5811 * @arg @ref LL_HRTIM_TIMER_A
5812 * @arg @ref LL_HRTIM_TIMER_B
5813 * @arg @ref LL_HRTIM_TIMER_C
5814 * @arg @ref LL_HRTIM_TIMER_D
5815 * @arg @ref LL_HRTIM_TIMER_E
5816 * @arg @ref LL_HRTIM_TIMER_F
5817 * @retval None
5818 */
LL_HRTIM_TIM_LockFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5819 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5820 {
5821 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5822 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5823 REG_OFFSET_TAB_TIMER[iTimer]));
5824 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
5825 }
5826
5827 /**
5828 * @brief Define how the timer behaves during a burst mode operation.
5829 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
5830 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
5831 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
5832 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
5833 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
5834 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption\n
5835 * BMCR TFBM LL_HRTIM_TIM_SetBurstModeOption
5836 * @note This function must not be called when the burst mode is enabled
5837 * @param HRTIMx High Resolution Timer instance
5838 * @param Timer This parameter can be one of the following values:
5839 * @arg @ref LL_HRTIM_TIMER_MASTER
5840 * @arg @ref LL_HRTIM_TIMER_A
5841 * @arg @ref LL_HRTIM_TIMER_B
5842 * @arg @ref LL_HRTIM_TIMER_C
5843 * @arg @ref LL_HRTIM_TIMER_D
5844 * @arg @ref LL_HRTIM_TIMER_E
5845 * @arg @ref LL_HRTIM_TIMER_F
5846 * @param BurtsModeOption This parameter can be one of the following values:
5847 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5848 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5849 * @retval None
5850 */
LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t BurtsModeOption)5851 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
5852 {
5853 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5854 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
5855 }
5856
5857 /**
5858 * @brief Retrieve how the timer behaves during a burst mode operation.
5859 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
5860 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
5861 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
5862 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
5863 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
5864 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption\n
5865 * BMCR TFBM LL_HRTIM_TIM_GetBurstModeOption
5866 * @param HRTIMx High Resolution Timer instance
5867 * @param Timer This parameter can be one of the following values:
5868 * @arg @ref LL_HRTIM_TIMER_MASTER
5869 * @arg @ref LL_HRTIM_TIMER_A
5870 * @arg @ref LL_HRTIM_TIMER_B
5871 * @arg @ref LL_HRTIM_TIMER_C
5872 * @arg @ref LL_HRTIM_TIMER_D
5873 * @arg @ref LL_HRTIM_TIMER_E
5874 * @arg @ref LL_HRTIM_TIMER_F
5875 * @retval BurtsMode This parameter can be one of the following values:
5876 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5877 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5878 */
LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5879 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5880 {
5881 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5882 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
5883 }
5884
5885 /**
5886 * @brief Program which registers are to be written by Burst DMA transfers.
5887 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
5888 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
5889 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5890 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5891 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
5892 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
5893 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5894 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5895 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5896 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5897 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
5898 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
5899 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5900 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5901 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
5902 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
5903 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5904 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5905 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5906 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5907 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
5908 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
5909 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
5910 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
5911 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
5912 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
5913 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
5914 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
5915 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
5916 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
5917 * @param HRTIMx High Resolution Timer instance
5918 * @param Timer This parameter can be one of the following values:
5919 * @arg @ref LL_HRTIM_TIMER_MASTER
5920 * @arg @ref LL_HRTIM_TIMER_A
5921 * @arg @ref LL_HRTIM_TIMER_B
5922 * @arg @ref LL_HRTIM_TIMER_C
5923 * @arg @ref LL_HRTIM_TIMER_D
5924 * @arg @ref LL_HRTIM_TIMER_E
5925 * @arg @ref LL_HRTIM_TIMER_F
5926 * @param Registers Registers to be updated by the DMA request
5927 *
5928 * For Master timer this parameter can be can be a combination of the following values:
5929 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5930 * @arg @ref LL_HRTIM_BURSTDMA_MCR
5931 * @arg @ref LL_HRTIM_BURSTDMA_MICR
5932 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
5933 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
5934 * @arg @ref LL_HRTIM_BURSTDMA_MPER
5935 * @arg @ref LL_HRTIM_BURSTDMA_MREP
5936 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
5937 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
5938 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
5939 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
5940 *
5941 * For Timers A..F this parameter can be can be a combination of the following values:
5942 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5943 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
5944 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
5945 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
5946 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
5947 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
5948 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
5949 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
5950 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
5951 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
5952 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
5953 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
5954 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
5955 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
5956 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
5957 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
5958 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
5959 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
5960 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
5961 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
5962 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
5963 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
5964 * @arg @ref LL_HRTIM_BURSTDMA_CR2
5965 * @arg @ref LL_HRTIM_BURSTDMA_EEFR3
5966 * @retval None
5967 */
LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Registers)5968 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
5969 {
5970 const uint8_t REG_OFFSET_TAB_BDTUPR[] =
5971 {
5972 0x00U, /* BDMUPR ; offset = 0x000 */
5973 0x04U, /* BDAUPR ; offset = 0x05C */
5974 0x08U, /* BDBUPR ; offset = 0x060 */
5975 0x0CU, /* BDCUPR ; offset = 0x064 */
5976 0x10U, /* BDDUPR ; offset = 0x068 */
5977 0x14U, /* BDEUPR ; offset = 0x06C */
5978 0x1CU /* BDFUPR ; offset = 0x074 */
5979 };
5980
5981 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
5982 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
5983 WRITE_REG(*pReg, Registers);
5984 }
5985
5986 /**
5987 * @brief Indicate on which output the signal is currently applied.
5988 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
5989 * @note Only significant when the timer operates in push-pull mode.
5990 * @param HRTIMx High Resolution Timer instance
5991 * @param Timer This parameter can be one of the following values:
5992 * @arg @ref LL_HRTIM_TIMER_A
5993 * @arg @ref LL_HRTIM_TIMER_B
5994 * @arg @ref LL_HRTIM_TIMER_C
5995 * @arg @ref LL_HRTIM_TIMER_D
5996 * @arg @ref LL_HRTIM_TIMER_E
5997 * @arg @ref LL_HRTIM_TIMER_F
5998 * @retval CPPSTAT This parameter can be one of the following values:
5999 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
6000 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
6001 */
LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6002 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6003 {
6004 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6005 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6006 REG_OFFSET_TAB_TIMER[iTimer]));
6007 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
6008 }
6009
6010 /**
6011 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
6012 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
6013 * @param HRTIMx High Resolution Timer instance
6014 * @param Timer This parameter can be one of the following values:
6015 * @arg @ref LL_HRTIM_TIMER_A
6016 * @arg @ref LL_HRTIM_TIMER_B
6017 * @arg @ref LL_HRTIM_TIMER_C
6018 * @arg @ref LL_HRTIM_TIMER_D
6019 * @arg @ref LL_HRTIM_TIMER_E
6020 * @arg @ref LL_HRTIM_TIMER_F
6021 * @retval IPPSTAT This parameter can be one of the following values:
6022 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
6023 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
6024 */
LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6025 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6026 {
6027 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6028 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6029 REG_OFFSET_TAB_TIMER[iTimer]));
6030 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
6031 }
6032
6033 /**
6034 * @brief Set the event filter for a given timer.
6035 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
6036 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
6037 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
6038 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
6039 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
6040 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
6041 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
6042 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
6043 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
6044 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
6045 * @note This function must not be called when the timer counter is enabled.
6046 * @param HRTIMx High Resolution Timer instance
6047 * @param Timer This parameter can be one of the following values:
6048 * @arg @ref LL_HRTIM_TIMER_A
6049 * @arg @ref LL_HRTIM_TIMER_B
6050 * @arg @ref LL_HRTIM_TIMER_C
6051 * @arg @ref LL_HRTIM_TIMER_D
6052 * @arg @ref LL_HRTIM_TIMER_E
6053 * @arg @ref LL_HRTIM_TIMER_F
6054 * @param Event This parameter can be one of the following values:
6055 * @arg @ref LL_HRTIM_EVENT_1
6056 * @arg @ref LL_HRTIM_EVENT_2
6057 * @arg @ref LL_HRTIM_EVENT_3
6058 * @arg @ref LL_HRTIM_EVENT_4
6059 * @arg @ref LL_HRTIM_EVENT_5
6060 * @arg @ref LL_HRTIM_EVENT_6
6061 * @arg @ref LL_HRTIM_EVENT_7
6062 * @arg @ref LL_HRTIM_EVENT_8
6063 * @arg @ref LL_HRTIM_EVENT_9
6064 * @arg @ref LL_HRTIM_EVENT_10
6065 * @param Filter This parameter can be one of the following values:
6066 * @arg @ref LL_HRTIM_EEFLTR_NONE
6067 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6068 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6069 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6070 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6071 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6072 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6073 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6074 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6075 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6076 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6077 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6078 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6079 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6080 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6081 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6082 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6083 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6084 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6085 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6086 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6087 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6088 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6089 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6090 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6091 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6092 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6093 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6094 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6095 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6096 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6097 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6098 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6099 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6100 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6101 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6102 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6103 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6104 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6105 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6106 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6107 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6108 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6109 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6110 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6111 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6112 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6113 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6114 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6115 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6116 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6117 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6118 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6119 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6120 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6121 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6122
6123 * @retval None
6124 */
LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t Filter)6125 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
6126 {
6127 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6128 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6129 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6130 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6131 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6132 }
6133
6134 /**
6135 * @brief Get actual event filter settings for a given timer.
6136 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
6137 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
6138 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
6139 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
6140 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
6141 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
6142 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
6143 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
6144 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
6145 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
6146 * @param HRTIMx High Resolution Timer instance
6147 * @param Timer This parameter can be one of the following values:
6148 * @arg @ref LL_HRTIM_TIMER_A
6149 * @arg @ref LL_HRTIM_TIMER_B
6150 * @arg @ref LL_HRTIM_TIMER_C
6151 * @arg @ref LL_HRTIM_TIMER_D
6152 * @arg @ref LL_HRTIM_TIMER_E
6153 * @arg @ref LL_HRTIM_TIMER_F
6154 * @param Event This parameter can be one of the following values:
6155 * @arg @ref LL_HRTIM_EVENT_1
6156 * @arg @ref LL_HRTIM_EVENT_2
6157 * @arg @ref LL_HRTIM_EVENT_3
6158 * @arg @ref LL_HRTIM_EVENT_4
6159 * @arg @ref LL_HRTIM_EVENT_5
6160 * @arg @ref LL_HRTIM_EVENT_6
6161 * @arg @ref LL_HRTIM_EVENT_7
6162 * @arg @ref LL_HRTIM_EVENT_8
6163 * @arg @ref LL_HRTIM_EVENT_9
6164 * @arg @ref LL_HRTIM_EVENT_10
6165 * @retval Filter This parameter can be one of the following values:
6166 * @arg @ref LL_HRTIM_EEFLTR_NONE
6167 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6168 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6169 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6170 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6171 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6172 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6173 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6174 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6175 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6176 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6177 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6178 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6179 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6180 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6181 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6182 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6183 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6184 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6185 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6186 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6187 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6188 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6189 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6190 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6191 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6192 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6193 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6194 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6195 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6196 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6197 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6198 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6199 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6200 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6201 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6202 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6203 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6204 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6205 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6206 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6207 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6208 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6209 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6210 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6211 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6212 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6213 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6214 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6215 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6216 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6217 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6218 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6219 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6220 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6221 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6222 */
LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6223 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6224 {
6225 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6226 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6227 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6228 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6229 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6230 }
6231
6232 /**
6233 * @brief Enable or disable event latch mechanism for a given timer.
6234 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6235 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6236 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6237 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6238 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6239 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6240 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6241 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6242 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6243 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
6244 * @note This function must not be called when the timer counter is enabled.
6245 * @param HRTIMx High Resolution Timer instance
6246 * @param Timer This parameter can be one of the following values:
6247 * @arg @ref LL_HRTIM_TIMER_A
6248 * @arg @ref LL_HRTIM_TIMER_B
6249 * @arg @ref LL_HRTIM_TIMER_C
6250 * @arg @ref LL_HRTIM_TIMER_D
6251 * @arg @ref LL_HRTIM_TIMER_E
6252 * @arg @ref LL_HRTIM_TIMER_F
6253 * @param Event This parameter can be one of the following values:
6254 * @arg @ref LL_HRTIM_EVENT_1
6255 * @arg @ref LL_HRTIM_EVENT_2
6256 * @arg @ref LL_HRTIM_EVENT_3
6257 * @arg @ref LL_HRTIM_EVENT_4
6258 * @arg @ref LL_HRTIM_EVENT_5
6259 * @arg @ref LL_HRTIM_EVENT_6
6260 * @arg @ref LL_HRTIM_EVENT_7
6261 * @arg @ref LL_HRTIM_EVENT_8
6262 * @arg @ref LL_HRTIM_EVENT_9
6263 * @arg @ref LL_HRTIM_EVENT_10
6264 * @param LatchStatus This parameter can be one of the following values:
6265 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6266 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6267 * @retval None
6268 */
LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t LatchStatus)6269 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
6270 uint32_t LatchStatus)
6271 {
6272 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6273 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6274 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6275 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6276 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
6277 }
6278
6279 /**
6280 * @brief Get actual event latch status for a given timer.
6281 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6282 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6283 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6284 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6285 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6286 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6287 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6288 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6289 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6290 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
6291 * @param HRTIMx High Resolution Timer instance
6292 * @param Timer This parameter can be one of the following values:
6293 * @arg @ref LL_HRTIM_TIMER_A
6294 * @arg @ref LL_HRTIM_TIMER_B
6295 * @arg @ref LL_HRTIM_TIMER_C
6296 * @arg @ref LL_HRTIM_TIMER_D
6297 * @arg @ref LL_HRTIM_TIMER_E
6298 * @arg @ref LL_HRTIM_TIMER_F
6299 * @param Event This parameter can be one of the following values:
6300 * @arg @ref LL_HRTIM_EVENT_1
6301 * @arg @ref LL_HRTIM_EVENT_2
6302 * @arg @ref LL_HRTIM_EVENT_3
6303 * @arg @ref LL_HRTIM_EVENT_4
6304 * @arg @ref LL_HRTIM_EVENT_5
6305 * @arg @ref LL_HRTIM_EVENT_6
6306 * @arg @ref LL_HRTIM_EVENT_7
6307 * @arg @ref LL_HRTIM_EVENT_8
6308 * @arg @ref LL_HRTIM_EVENT_9
6309 * @arg @ref LL_HRTIM_EVENT_10
6310 * @retval LatchStatus This parameter can be one of the following values:
6311 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6312 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6313 */
LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6314 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6315 {
6316 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6317 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6318 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6319 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6320 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6321 }
6322
6323 /**
6324 * @brief Select the Trigger-Half operating mode for a given timer.
6325 * @note This bitfield defines whether the compare 2 register
6326 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6327 * @note or in triggered-half mode
6328 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_SetTriggeredHalfMode
6329 * @param HRTIMx High Resolution Timer instance
6330 * @param Timer This parameter can be one of the following values:
6331 * @arg @ref LL_HRTIM_TIMER_A
6332 * @arg @ref LL_HRTIM_TIMER_B
6333 * @arg @ref LL_HRTIM_TIMER_C
6334 * @arg @ref LL_HRTIM_TIMER_D
6335 * @arg @ref LL_HRTIM_TIMER_E
6336 * @arg @ref LL_HRTIM_TIMER_F
6337 * @param Mode This parameter can be one of the following values:
6338 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6339 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6340 * @retval None
6341 */
LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6342 __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6343 {
6344 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6345 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6346 REG_OFFSET_TAB_TIMER[iTimer]));
6347 MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
6348 }
6349
6350 /**
6351 * @brief Get the Trigger-Half operating mode for a given timer.
6352 * @note This bitfield reports whether the compare 2 register
6353 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6354 * @note or in triggered-half mode
6355 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_GetTriggeredHalfMode
6356 * @param HRTIMx High Resolution Timer instance
6357 * @param Timer This parameter can be one of the following values:
6358 * @arg @ref LL_HRTIM_TIMER_A
6359 * @arg @ref LL_HRTIM_TIMER_B
6360 * @arg @ref LL_HRTIM_TIMER_C
6361 * @arg @ref LL_HRTIM_TIMER_D
6362 * @arg @ref LL_HRTIM_TIMER_E
6363 * @arg @ref LL_HRTIM_TIMER_F
6364 * @retval Mode This parameter can be one of the following values:
6365 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6366 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6367 */
LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6368 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6369 {
6370 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6371 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6372 REG_OFFSET_TAB_TIMER[iTimer]));
6373 return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
6374 }
6375
6376 /**
6377 * @brief Select the compare 1 operating mode.
6378 * @note This bit defines the compare 1 operating mode:
6379 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6380 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6381 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_SetComp1Mode
6382 * @param HRTIMx High Resolution Timer instance
6383 * @param Timer This parameter can be one of the following values:
6384 * @arg @ref LL_HRTIM_TIMER_A
6385 * @arg @ref LL_HRTIM_TIMER_B
6386 * @arg @ref LL_HRTIM_TIMER_C
6387 * @arg @ref LL_HRTIM_TIMER_D
6388 * @arg @ref LL_HRTIM_TIMER_E
6389 * @arg @ref LL_HRTIM_TIMER_F
6390 * @param Mode This parameter can be one of the following values:
6391 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6392 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6393 * @retval None
6394 */
LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6395 __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6396 {
6397 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6398 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6399 REG_OFFSET_TAB_TIMER[iTimer]));
6400 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
6401 }
6402
6403 /**
6404 * @brief Get the selected compare 1 operating mode.
6405 * @note This bit reports the compare 1 operating mode:
6406 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6407 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6408 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_GetComp1Mode
6409 * @param HRTIMx High Resolution Timer instance
6410 * @param Timer This parameter can be one of the following values:
6411 * @arg @ref LL_HRTIM_TIMER_A
6412 * @arg @ref LL_HRTIM_TIMER_B
6413 * @arg @ref LL_HRTIM_TIMER_C
6414 * @arg @ref LL_HRTIM_TIMER_D
6415 * @arg @ref LL_HRTIM_TIMER_E
6416 * @arg @ref LL_HRTIM_TIMER_F
6417 * @retval Mode This parameter can be one of the following values:
6418 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6419 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6420 */
LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6421 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6422 {
6423 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6424 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6425 REG_OFFSET_TAB_TIMER[iTimer]));
6426 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
6427 }
6428
6429 /**
6430 * @brief Select the compare 3 operating mode.
6431 * @note This bit defines the compare 3 operating mode:
6432 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6433 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6434 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_SetComp3Mode
6435 * @param HRTIMx High Resolution Timer instance
6436 * @param Timer This parameter can be one of the following values:
6437 * @arg @ref LL_HRTIM_TIMER_A
6438 * @arg @ref LL_HRTIM_TIMER_B
6439 * @arg @ref LL_HRTIM_TIMER_C
6440 * @arg @ref LL_HRTIM_TIMER_D
6441 * @arg @ref LL_HRTIM_TIMER_E
6442 * @arg @ref LL_HRTIM_TIMER_F
6443 * @param Mode This parameter can be one of the following values:
6444 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6445 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6446 * @retval None
6447 */
LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6448 __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6449 {
6450 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6451 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6452 REG_OFFSET_TAB_TIMER[iTimer]));
6453 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
6454 }
6455
6456 /**
6457 * @brief Get the selected compare 3 operating mode.
6458 * @note This bit reports the compare 3 operating mode:
6459 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6460 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6461 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_GetComp1Mode
6462 * @param HRTIMx High Resolution Timer instance
6463 * @param Timer This parameter can be one of the following values:
6464 * @arg @ref LL_HRTIM_TIMER_A
6465 * @arg @ref LL_HRTIM_TIMER_B
6466 * @arg @ref LL_HRTIM_TIMER_C
6467 * @arg @ref LL_HRTIM_TIMER_D
6468 * @arg @ref LL_HRTIM_TIMER_E
6469 * @arg @ref LL_HRTIM_TIMER_F
6470 * @retval Mode This parameter can be one of the following values:
6471 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6472 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6473 */
LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6474 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6475 {
6476 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6477 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
6478 REG_OFFSET_TAB_TIMER[iTimer]));
6479 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
6480 }
6481
6482 /**
6483 * @brief Select the roll-over mode.
6484 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6485 * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
6486 * and DMA requests, repetition counter decrement and External Event filtering.
6487 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_SetRollOverMode
6488 * @param HRTIMx High Resolution Timer instance
6489 * @param Timer This parameter can be one of the following values:
6490 * @arg @ref LL_HRTIM_TIMER_A
6491 * @arg @ref LL_HRTIM_TIMER_B
6492 * @arg @ref LL_HRTIM_TIMER_C
6493 * @arg @ref LL_HRTIM_TIMER_D
6494 * @arg @ref LL_HRTIM_TIMER_E
6495 * @arg @ref LL_HRTIM_TIMER_F
6496 * @param Mode This parameter can be one of the following values:
6497 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6498 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6499 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6500 * @retval None
6501 */
LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6502 __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6503 {
6504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6506 REG_OFFSET_TAB_TIMER[iTimer]));
6507 MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
6508 }
6509
6510 /**
6511 * @brief Get selected the roll-over mode.
6512 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetRollOverMode
6513 * @param HRTIMx High Resolution Timer instance
6514 * @param Timer This parameter can be one of the following values:
6515 * @arg @ref LL_HRTIM_TIMER_A
6516 * @arg @ref LL_HRTIM_TIMER_B
6517 * @arg @ref LL_HRTIM_TIMER_C
6518 * @arg @ref LL_HRTIM_TIMER_D
6519 * @arg @ref LL_HRTIM_TIMER_E
6520 * @arg @ref LL_HRTIM_TIMER_F
6521 * @retval Mode returned value can be one of the following values:
6522 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6523 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6524 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6525 */
LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6526 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6527 {
6528 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6529 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6530 REG_OFFSET_TAB_TIMER[iTimer]));
6531 return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
6532 }
6533
6534 /**
6535 * @brief Select Fault and Event roll-over mode.
6536 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6537 * @note only concerns the Roll-over event used by the Fault and Event counters.
6538 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_SetFaultEventRollOverMode
6539 * @param HRTIMx High Resolution Timer instance
6540 * @param Timer This parameter can be one of the following values:
6541 * @arg @ref LL_HRTIM_TIMER_A
6542 * @arg @ref LL_HRTIM_TIMER_B
6543 * @arg @ref LL_HRTIM_TIMER_C
6544 * @arg @ref LL_HRTIM_TIMER_D
6545 * @arg @ref LL_HRTIM_TIMER_E
6546 * @arg @ref LL_HRTIM_TIMER_F
6547 * @param Mode This parameter can be one of the following values:
6548 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6549 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6550 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6551 * @retval None
6552 */
LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6553 __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6554 {
6555 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6556 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6557 REG_OFFSET_TAB_TIMER[iTimer]));
6558 MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
6559 }
6560
6561 /**
6562 * @brief Get selected Fault and Event role-over mode.
6563 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_GetFaultEventRollOverMode
6564 * @param HRTIMx High Resolution Timer instance
6565 * @param Timer This parameter can be one of the following values:
6566 * @arg @ref LL_HRTIM_TIMER_A
6567 * @arg @ref LL_HRTIM_TIMER_B
6568 * @arg @ref LL_HRTIM_TIMER_C
6569 * @arg @ref LL_HRTIM_TIMER_D
6570 * @arg @ref LL_HRTIM_TIMER_E
6571 * @arg @ref LL_HRTIM_TIMER_F
6572 * @retval Mode returned value can be one of the following values:
6573 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6574 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6575 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6576 */
LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6577 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6578 {
6579 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6580 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6581 REG_OFFSET_TAB_TIMER[iTimer]));
6582 return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
6583 }
6584
6585 /**
6586 * @brief Select the Burst mode roll-over mode.
6587 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6588 * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
6589 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetBMRollOverMode
6590 * @param HRTIMx High Resolution Timer instance
6591 * @param Timer This parameter can be one of the following values:
6592 * @arg @ref LL_HRTIM_TIMER_A
6593 * @arg @ref LL_HRTIM_TIMER_B
6594 * @arg @ref LL_HRTIM_TIMER_C
6595 * @arg @ref LL_HRTIM_TIMER_D
6596 * @arg @ref LL_HRTIM_TIMER_E
6597 * @arg @ref LL_HRTIM_TIMER_F
6598 * @param Mode This parameter can be one of the following values:
6599 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6600 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6601 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6602 * @retval None
6603 */
LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6604 __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6605 {
6606 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6607 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6608 REG_OFFSET_TAB_TIMER[iTimer]));
6609 MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
6610 }
6611
6612 /**
6613 * @brief Get selected Burst mode roll-over mode.
6614 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetBMRollOverMode
6615 * @param HRTIMx High Resolution Timer instance
6616 * @param Timer This parameter can be one of the following values:
6617 * @arg @ref LL_HRTIM_TIMER_A
6618 * @arg @ref LL_HRTIM_TIMER_B
6619 * @arg @ref LL_HRTIM_TIMER_C
6620 * @arg @ref LL_HRTIM_TIMER_D
6621 * @arg @ref LL_HRTIM_TIMER_E
6622 * @arg @ref LL_HRTIM_TIMER_F
6623 * @retval Mode returned value can be one of the following values:
6624 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6625 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6626 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6627 */
LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6628 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6629 {
6630 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6631 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6632 REG_OFFSET_TAB_TIMER[iTimer]));
6633 return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
6634 }
6635
6636 /**
6637 * @brief Select the ADC roll-over mode.
6638 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6639 * @note Only concerns the Roll-over event used to trigger the ADC.
6640 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetADCRollOverMode
6641 * @param HRTIMx High Resolution Timer instance
6642 * @param Timer This parameter can be one of the following values:
6643 * @arg @ref LL_HRTIM_TIMER_A
6644 * @arg @ref LL_HRTIM_TIMER_B
6645 * @arg @ref LL_HRTIM_TIMER_C
6646 * @arg @ref LL_HRTIM_TIMER_D
6647 * @arg @ref LL_HRTIM_TIMER_E
6648 * @arg @ref LL_HRTIM_TIMER_F
6649 * @param Mode This parameter can be one of the following values:
6650 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6651 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6652 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6653 * @retval None
6654 */
LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6655 __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6656 {
6657 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6658 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6659 REG_OFFSET_TAB_TIMER[iTimer]));
6660 MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
6661 }
6662
6663 /**
6664 * @brief Get selected ADC roll-over mode.
6665 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_GetADCRollOverMode
6666 * @param HRTIMx High Resolution Timer instance
6667 * @param Timer This parameter can be one of the following values:
6668 * @arg @ref LL_HRTIM_TIMER_A
6669 * @arg @ref LL_HRTIM_TIMER_B
6670 * @arg @ref LL_HRTIM_TIMER_C
6671 * @arg @ref LL_HRTIM_TIMER_D
6672 * @arg @ref LL_HRTIM_TIMER_E
6673 * @arg @ref LL_HRTIM_TIMER_F
6674 * @retval Mode returned value can be one of the following values:
6675 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6676 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6677 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6678 */
LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6679 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6680 {
6681 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6682 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6683 REG_OFFSET_TAB_TIMER[iTimer]));
6684 return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
6685 }
6686
6687 /**
6688 * @brief Select the ADC roll-over mode.
6689 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6690 * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
6691 * as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
6692 * and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
6693 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode
6694 * @param HRTIMx High Resolution Timer instance
6695 * @param Timer This parameter can be one of the following values:
6696 * @arg @ref LL_HRTIM_TIMER_A
6697 * @arg @ref LL_HRTIM_TIMER_B
6698 * @arg @ref LL_HRTIM_TIMER_C
6699 * @arg @ref LL_HRTIM_TIMER_D
6700 * @arg @ref LL_HRTIM_TIMER_E
6701 * @arg @ref LL_HRTIM_TIMER_F
6702 * @param Mode This parameter can be one of the following values:
6703 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6704 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6705 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6706 * @retval None
6707 */
LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6708 __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6709 {
6710 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6711 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6712 REG_OFFSET_TAB_TIMER[iTimer]));
6713 MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
6714 }
6715
6716 /**
6717 * @brief Get selected ADC roll-over mode.
6718 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_GetOutputRollOverMode
6719 * @param HRTIMx High Resolution Timer instance
6720 * @param Timer This parameter can be one of the following values:
6721 * @arg @ref LL_HRTIM_TIMER_A
6722 * @arg @ref LL_HRTIM_TIMER_B
6723 * @arg @ref LL_HRTIM_TIMER_C
6724 * @arg @ref LL_HRTIM_TIMER_D
6725 * @arg @ref LL_HRTIM_TIMER_E
6726 * @arg @ref LL_HRTIM_TIMER_F
6727 * @retval Mode returned value can be one of the following values:
6728 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6729 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6730 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6731 */
LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6732 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6733 {
6734 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6735 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6736 REG_OFFSET_TAB_TIMER[iTimer]));
6737 return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
6738 }
6739
6740 /**
6741 * @brief Select the counting mode.
6742 * @note The up-down counting mode is available for both continuous and single-shot
6743 * (retriggerable and nonretriggerable) operating modes
6744 * (see function @ref LL_HRTIM_TIM_SetCounterMode()).
6745 * @note The counter roll-over event is defined differently in-up-down counting mode to
6746 * support various operating condition.
6747 * See @ref LL_HRTIM_TIM_SetCounterMode()
6748 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_SetCountingMode
6749 * @param HRTIMx High Resolution Timer instance
6750 * @param Timer This parameter can be one of the following values:
6751 * @arg @ref LL_HRTIM_TIMER_A
6752 * @arg @ref LL_HRTIM_TIMER_B
6753 * @arg @ref LL_HRTIM_TIMER_C
6754 * @arg @ref LL_HRTIM_TIMER_D
6755 * @arg @ref LL_HRTIM_TIMER_E
6756 * @arg @ref LL_HRTIM_TIMER_F
6757 * @param Mode This parameter can be one of the following values:
6758 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6759 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6760 * @retval None
6761 */
LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6762 __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6763 {
6764 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6765 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6766 REG_OFFSET_TAB_TIMER[iTimer]));
6767 MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
6768 }
6769
6770 /**
6771 * @brief Get selected counting mode.
6772 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_GetCountingMode
6773 * @param HRTIMx High Resolution Timer instance
6774 * @param Timer This parameter can be one of the following values:
6775 * @arg @ref LL_HRTIM_TIMER_A
6776 * @arg @ref LL_HRTIM_TIMER_B
6777 * @arg @ref LL_HRTIM_TIMER_C
6778 * @arg @ref LL_HRTIM_TIMER_D
6779 * @arg @ref LL_HRTIM_TIMER_E
6780 * @arg @ref LL_HRTIM_TIMER_F
6781 * @retval Mode returned value can be one of the following values:
6782 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6783 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6784 * @retval None
6785 */
LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6786 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6787 {
6788 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6789 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6790 REG_OFFSET_TAB_TIMER[iTimer]));
6791 return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
6792 }
6793
6794 /**
6795 * @brief Select Dual Channel DAC Reset trigger.
6796 * @note Significant only when Dual channel DAC trigger is enabled
6797 * (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
6798 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_SetDualDacResetTrigger
6799 * @param HRTIMx High Resolution Timer instance
6800 * @param Timer This parameter can be one of the following values:
6801 * @arg @ref LL_HRTIM_TIMER_A
6802 * @arg @ref LL_HRTIM_TIMER_B
6803 * @arg @ref LL_HRTIM_TIMER_C
6804 * @arg @ref LL_HRTIM_TIMER_D
6805 * @arg @ref LL_HRTIM_TIMER_E
6806 * @arg @ref LL_HRTIM_TIMER_F
6807 * @param Mode This parameter can be one of the following values:
6808 * @arg @ref LL_HRTIM_DCDR_COUNTER
6809 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6810 * @retval None
6811 */
LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6812 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6813 {
6814 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6815 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6816 REG_OFFSET_TAB_TIMER[iTimer]));
6817 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
6818 }
6819
6820 /**
6821 * @brief Get selected Dual Channel DAC Reset trigger.
6822 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_GetDualDacResetTrigger
6823 * @param HRTIMx High Resolution Timer instance
6824 * @param Timer This parameter can be one of the following values:
6825 * @arg @ref LL_HRTIM_TIMER_A
6826 * @arg @ref LL_HRTIM_TIMER_B
6827 * @arg @ref LL_HRTIM_TIMER_C
6828 * @arg @ref LL_HRTIM_TIMER_D
6829 * @arg @ref LL_HRTIM_TIMER_E
6830 * @arg @ref LL_HRTIM_TIMER_F
6831 * @retval Trigger returned value can be one of the following values:
6832 * @arg @ref LL_HRTIM_DCDR_COUNTER
6833 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6834 */
LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6835 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6836 {
6837 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6838 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6839 REG_OFFSET_TAB_TIMER[iTimer]));
6840 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
6841 }
6842
6843 /**
6844 * @brief Select Dual Channel DAC Reset trigger.
6845 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_SetDualDacStepTrigger
6846 * @param HRTIMx High Resolution Timer instance
6847 * @param Timer This parameter can be one of the following values:
6848 * @arg @ref LL_HRTIM_TIMER_A
6849 * @arg @ref LL_HRTIM_TIMER_B
6850 * @arg @ref LL_HRTIM_TIMER_C
6851 * @arg @ref LL_HRTIM_TIMER_D
6852 * @arg @ref LL_HRTIM_TIMER_E
6853 * @arg @ref LL_HRTIM_TIMER_F
6854 * @param Mode This parameter can be one of the following values:
6855 * @arg @ref LL_HRTIM_DCDS_CMP2
6856 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6857 * @retval None
6858 */
LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6859 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6860 {
6861 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6862 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6863 REG_OFFSET_TAB_TIMER[iTimer]));
6864 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
6865 }
6866
6867 /**
6868 * @brief Get selected Dual Channel DAC Reset trigger.
6869 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_GetDualDacStepTrigger
6870 * @param HRTIMx High Resolution Timer instance
6871 * @param Timer This parameter can be one of the following values:
6872 * @arg @ref LL_HRTIM_TIMER_A
6873 * @arg @ref LL_HRTIM_TIMER_B
6874 * @arg @ref LL_HRTIM_TIMER_C
6875 * @arg @ref LL_HRTIM_TIMER_D
6876 * @arg @ref LL_HRTIM_TIMER_E
6877 * @arg @ref LL_HRTIM_TIMER_F
6878 * @retval Trigger returned value can be one of the following values:
6879 * @arg @ref LL_HRTIM_DCDS_CMP2
6880 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6881 */
LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6882 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6883 {
6884 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6885 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6886 REG_OFFSET_TAB_TIMER[iTimer]));
6887 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
6888 }
6889
6890 /**
6891 * @brief Enable Dual Channel DAC trigger.
6892 * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
6893 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_EnableDualDacTrigger
6894 * @param HRTIMx High Resolution Timer instance
6895 * @param Timer This parameter can be one of the following values:
6896 * @arg @ref LL_HRTIM_TIMER_A
6897 * @arg @ref LL_HRTIM_TIMER_B
6898 * @arg @ref LL_HRTIM_TIMER_C
6899 * @arg @ref LL_HRTIM_TIMER_D
6900 * @arg @ref LL_HRTIM_TIMER_E
6901 * @arg @ref LL_HRTIM_TIMER_F
6902 * @retval None
6903 */
LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6904 __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6905 {
6906 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6907 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6908 REG_OFFSET_TAB_TIMER[iTimer]));
6909 SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6910 }
6911
6912 /**
6913 * @brief Disable Dual Channel DAC trigger.
6914 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_DisableDualDacTrigger
6915 * @param HRTIMx High Resolution Timer instance
6916 * @param Timer This parameter can be one of the following values:
6917 * @arg @ref LL_HRTIM_TIMER_A
6918 * @arg @ref LL_HRTIM_TIMER_B
6919 * @arg @ref LL_HRTIM_TIMER_C
6920 * @arg @ref LL_HRTIM_TIMER_D
6921 * @arg @ref LL_HRTIM_TIMER_E
6922 * @arg @ref LL_HRTIM_TIMER_F
6923 * @retval None
6924 */
LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6925 __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6926 {
6927 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6929 REG_OFFSET_TAB_TIMER[iTimer]));
6930 CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6931 }
6932
6933 /**
6934 * @brief Indicate whether Dual Channel DAC trigger is enabled for a given timer.
6935 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_IsEnabledDualDacTrigger
6936 * @param HRTIMx High Resolution Timer instance
6937 * @param Timer This parameter can be one of the following values:
6938 * @arg @ref LL_HRTIM_TIMER_A
6939 * @arg @ref LL_HRTIM_TIMER_B
6940 * @arg @ref LL_HRTIM_TIMER_C
6941 * @arg @ref LL_HRTIM_TIMER_D
6942 * @arg @ref LL_HRTIM_TIMER_E
6943 * @arg @ref LL_HRTIM_TIMER_F
6944 * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
6945 */
LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6946 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6947 {
6948 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6949 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6950 REG_OFFSET_TAB_TIMER[iTimer]));
6951
6952 return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
6953 }
6954
6955
6956 /**
6957 * @brief Set the external event counter threshold.
6958 * @note The external event is propagated to the timer only if the number
6959 * of active edges is greater than the external event counter threshold.
6960 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_SetEventCounterThreshold\n
6961 * EEFxR3 EEVACNT LL_HRTIM_TIM_SetEventCounterThreshold
6962 * @param HRTIMx High Resolution Timer instance
6963 * @param Timer This parameter can be one of the following values:
6964 * @arg @ref LL_HRTIM_TIMER_A
6965 * @arg @ref LL_HRTIM_TIMER_B
6966 * @arg @ref LL_HRTIM_TIMER_C
6967 * @arg @ref LL_HRTIM_TIMER_D
6968 * @arg @ref LL_HRTIM_TIMER_E
6969 * @arg @ref LL_HRTIM_TIMER_F
6970 * @param EventCounter This parameter can be one of the following values:
6971 * @arg @ref LL_HRTIM_EE_COUNTER_A
6972 * @arg @ref LL_HRTIM_EE_COUNTER_B
6973 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
6974 * @retval None
6975 */
LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Threshold)6976 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
6977 uint32_t Threshold)
6978 {
6979 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6980 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
6981
6982 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
6983 }
6984
6985 /**
6986 * @brief Get the programmed external event counter threshold.
6987 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_GetEventCounterThreshold\n
6988 * EEFxR3 EEVACNT LL_HRTIM_TIM_GetEventCounterThreshold
6989 * @param HRTIMx High Resolution Timer instance
6990 * @param Timer This parameter can be one of the following values:
6991 * @arg @ref LL_HRTIM_TIMER_A
6992 * @arg @ref LL_HRTIM_TIMER_B
6993 * @arg @ref LL_HRTIM_TIMER_C
6994 * @arg @ref LL_HRTIM_TIMER_D
6995 * @arg @ref LL_HRTIM_TIMER_E
6996 * @arg @ref LL_HRTIM_TIMER_F
6997 * @param EventCounter This parameter can be one of the following values:
6998 * @arg @ref LL_HRTIM_EE_COUNTER_A
6999 * @arg @ref LL_HRTIM_EE_COUNTER_B
7000 * @retval Threshold Value between Min_Data=0 and Max_Data=63
7001 */
LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7002 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7003 uint32_t EventCounter)
7004 {
7005 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7006 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7007
7008 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ;
7009 }
7010
7011 /**
7012 * @brief Select the external event counter source.
7013 * @note External event counting is only valid for edge-sensitive
7014 * external events (See function LL_HRTIM_EE_Config() and function
7015 * LL_HRTIM_EE_SetSensitivity()).
7016 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_SetEventCounterSource\n
7017 * EEFxR3 EEVASEL LL_HRTIM_TIM_SetEventCounterSource
7018 * @param HRTIMx High Resolution Timer instance
7019 * @param Timer This parameter can be one of the following values:
7020 * @arg @ref LL_HRTIM_TIMER_A
7021 * @arg @ref LL_HRTIM_TIMER_B
7022 * @arg @ref LL_HRTIM_TIMER_C
7023 * @arg @ref LL_HRTIM_TIMER_D
7024 * @arg @ref LL_HRTIM_TIMER_E
7025 * @arg @ref LL_HRTIM_TIMER_F
7026 * @param EventCounter This parameter can be one of the following values:
7027 * @arg @ref LL_HRTIM_EE_COUNTER_A
7028 * @arg @ref LL_HRTIM_EE_COUNTER_B
7029 * @param Event This parameter can be one of the following values:
7030 * @arg @ref LL_HRTIM_EVENT_1
7031 * @arg @ref LL_HRTIM_EVENT_2
7032 * @arg @ref LL_HRTIM_EVENT_3
7033 * @arg @ref LL_HRTIM_EVENT_4
7034 * @arg @ref LL_HRTIM_EVENT_5
7035 * @arg @ref LL_HRTIM_EVENT_6
7036 * @arg @ref LL_HRTIM_EVENT_7
7037 * @arg @ref LL_HRTIM_EVENT_8
7038 * @arg @ref LL_HRTIM_EVENT_9
7039 * @arg @ref LL_HRTIM_EVENT_10
7040 * @retval None
7041 */
LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Event)7042 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7043 uint32_t Event)
7044 {
7045 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7046 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7047 uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
7048
7049 /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
7050 and 9 if LL_HRTIM_EVENT_10 */
7051 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7052 }
7053
7054 /**
7055 * @brief get the selected external event counter source.
7056 * LL_HRTIM_EE_SetSensitivity()).
7057 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_GetEventCounterSource\n
7058 * EEFxR3 EEVASEL LL_HRTIM_TIM_GetEventCounterSource
7059 * @param HRTIMx High Resolution Timer instance
7060 * @param Timer This parameter can be one of the following values:
7061 * @arg @ref LL_HRTIM_TIMER_A
7062 * @arg @ref LL_HRTIM_TIMER_B
7063 * @arg @ref LL_HRTIM_TIMER_C
7064 * @arg @ref LL_HRTIM_TIMER_D
7065 * @arg @ref LL_HRTIM_TIMER_E
7066 * @arg @ref LL_HRTIM_TIMER_F
7067 * @param EventCounter This parameter can be one of the following values:
7068 * @arg @ref LL_HRTIM_EE_COUNTER_A
7069 * @arg @ref LL_HRTIM_EE_COUNTER_B
7070 * @retval Event This parameter can be one of the following values:
7071 * @arg @ref LL_HRTIM_EVENT_1
7072 * @arg @ref LL_HRTIM_EVENT_2
7073 * @arg @ref LL_HRTIM_EVENT_3
7074 * @arg @ref LL_HRTIM_EVENT_4
7075 * @arg @ref LL_HRTIM_EVENT_5
7076 * @arg @ref LL_HRTIM_EVENT_6
7077 * @arg @ref LL_HRTIM_EVENT_7
7078 * @arg @ref LL_HRTIM_EVENT_8
7079 * @arg @ref LL_HRTIM_EVENT_9
7080 * @arg @ref LL_HRTIM_EVENT_10
7081 */
LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7082 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7083 uint32_t EventCounter)
7084 {
7085 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7086 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7087
7088 uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7089
7090 /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
7091 and 9 if SEL is LL_HRTIM_EVENT_10 */
7092 return ((uint32_t)0x1U << iEvent) ;
7093 }
7094
7095 /**
7096 * @brief Select the external event counter reset mode.
7097 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_SetEventCounterResetMode\n
7098 * EEFxR3 EEVARSTM LL_HRTIM_TIM_SetEventCounterResetMode
7099 * @param HRTIMx High Resolution Timer instance
7100 * @param Timer This parameter can be one of the following values:
7101 * @arg @ref LL_HRTIM_TIMER_A
7102 * @arg @ref LL_HRTIM_TIMER_B
7103 * @arg @ref LL_HRTIM_TIMER_C
7104 * @arg @ref LL_HRTIM_TIMER_D
7105 * @arg @ref LL_HRTIM_TIMER_E
7106 * @arg @ref LL_HRTIM_TIMER_F
7107 * @param EventCounter This parameter can be one of the following values:
7108 * @arg @ref LL_HRTIM_EE_COUNTER_A
7109 * @arg @ref LL_HRTIM_EE_COUNTER_B
7110 * @param Mode This parameter can be one of the following values:
7111 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7112 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7113 * @retval None
7114 */
LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Mode)7115 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7116 uint32_t Mode)
7117 {
7118 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7119 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7120
7121 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
7122 }
7123
7124 /**
7125 * @brief Get selected external event counter reset mode.
7126 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_GetEventCounterResetMode\n
7127 * EEFxR3 EEVARSTM LL_HRTIM_TIM_GetEventCounterResetMode
7128 * @param HRTIMx High Resolution Timer instance
7129 * @param Timer This parameter can be one of the following values:
7130 * @arg @ref LL_HRTIM_TIMER_A
7131 * @arg @ref LL_HRTIM_TIMER_B
7132 * @arg @ref LL_HRTIM_TIMER_C
7133 * @arg @ref LL_HRTIM_TIMER_D
7134 * @arg @ref LL_HRTIM_TIMER_E
7135 * @arg @ref LL_HRTIM_TIMER_F
7136 * @param EventCounter This parameter can be one of the following values:
7137 * @arg @ref LL_HRTIM_EE_COUNTER_A
7138 * @arg @ref LL_HRTIM_EE_COUNTER_B
7139 * @retval Mode This parameter can be one of the following values:
7140 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7141 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7142 */
LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7143 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7144 uint32_t EventCounter)
7145 {
7146 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7147 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7148
7149 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ;
7150 }
7151
7152 /**
7153 * @brief Reset the external event counter.
7154 * @rmtoll EEFxR3 EEVACRES LL_HRTIM_TIM_ResetEventCounter\n
7155 * EEFxR3 EEVBCRES LL_HRTIM_TIM_ResetEventCounter
7156 * @param HRTIMx High Resolution Timer instance
7157 * @param Timer This parameter can be one of the following values:
7158 * @arg @ref LL_HRTIM_TIMER_A
7159 * @arg @ref LL_HRTIM_TIMER_B
7160 * @arg @ref LL_HRTIM_TIMER_C
7161 * @arg @ref LL_HRTIM_TIMER_D
7162 * @arg @ref LL_HRTIM_TIMER_E
7163 * @arg @ref LL_HRTIM_TIMER_F
7164 * @param EventCounter This parameter can be one of the following values:
7165 * @arg @ref LL_HRTIM_EE_COUNTER_A
7166 * @arg @ref LL_HRTIM_EE_COUNTER_B
7167 * @retval None
7168 */
LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7169 __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7170 {
7171 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7172 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7173
7174 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
7175 }
7176
7177 /**
7178 * @brief Enable the external event counter.
7179 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_EnableEventCounter\n
7180 * EEFxR3 EEVBCE LL_HRTIM_TIM_EnableEventCounter
7181 * @param HRTIMx High Resolution Timer instance
7182 * @param Timer This parameter can be one of the following values:
7183 * @arg @ref LL_HRTIM_TIMER_A
7184 * @arg @ref LL_HRTIM_TIMER_B
7185 * @arg @ref LL_HRTIM_TIMER_C
7186 * @arg @ref LL_HRTIM_TIMER_D
7187 * @arg @ref LL_HRTIM_TIMER_E
7188 * @arg @ref LL_HRTIM_TIMER_F
7189 * @param EventCounter This parameter can be one of the following values:
7190 * @arg @ref LL_HRTIM_EE_COUNTER_A
7191 * @arg @ref LL_HRTIM_EE_COUNTER_B
7192 * @retval None
7193 */
LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7194 __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7195 {
7196 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7197 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7198
7199 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7200 }
7201
7202 /**
7203 * @brief Disable the external event counter.
7204 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_DisableEventCounter\n
7205 * EEFxR3 EEVBCE LL_HRTIM_TIM_DisableEventCounter
7206 * @param HRTIMx High Resolution Timer instance
7207 * @param Timer This parameter can be one of the following values:
7208 * @arg @ref LL_HRTIM_TIMER_A
7209 * @arg @ref LL_HRTIM_TIMER_B
7210 * @arg @ref LL_HRTIM_TIMER_C
7211 * @arg @ref LL_HRTIM_TIMER_D
7212 * @arg @ref LL_HRTIM_TIMER_E
7213 * @arg @ref LL_HRTIM_TIMER_F
7214 * @param EventCounter This parameter can be one of the following values:
7215 * @arg @ref LL_HRTIM_EE_COUNTER_A
7216 * @arg @ref LL_HRTIM_EE_COUNTER_B
7217 * @retval None
7218 */
LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7219 __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7220 {
7221 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7222 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7223
7224 CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
7225 }
7226
7227
7228 /**
7229 * @brief Indicate whether the external event counter is enabled for a given timer.
7230 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_IsEnabledEventCounter\n
7231 * EEFxR3 EEVBCE LL_HRTIM_TIM_IsEnabledEventCounter
7232 * @param HRTIMx High Resolution Timer instance
7233 * @param Timer This parameter can be one of the following values:
7234 * @arg @ref LL_HRTIM_TIMER_A
7235 * @arg @ref LL_HRTIM_TIMER_B
7236 * @arg @ref LL_HRTIM_TIMER_C
7237 * @arg @ref LL_HRTIM_TIMER_D
7238 * @arg @ref LL_HRTIM_TIMER_E
7239 * @arg @ref LL_HRTIM_TIMER_F
7240 * @param EventCounter This parameter can be one of the following values:
7241 * @arg @ref LL_HRTIM_EE_COUNTER_A
7242 * @arg @ref LL_HRTIM_EE_COUNTER_B
7243 * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
7244 */
LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7245 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7246 uint32_t EventCounter)
7247 {
7248 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7249 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7250
7251 uint32_t temp; /* MISRAC-2012 compliance */
7252 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7253
7254 return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
7255 }
7256
7257 /**
7258 * @}
7259 */
7260
7261 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
7262 * @{
7263 */
7264
7265 /**
7266 * @brief Configure the dead time insertion feature for a given timer.
7267 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
7268 * DTxR SDTF LL_HRTIM_DT_Config\n
7269 * DTxR SDRT LL_HRTIM_DT_Config
7270 * @param HRTIMx High Resolution Timer instance
7271 * @param Timer This parameter can be one of the following values:
7272 * @arg @ref LL_HRTIM_TIMER_A
7273 * @arg @ref LL_HRTIM_TIMER_B
7274 * @arg @ref LL_HRTIM_TIMER_C
7275 * @arg @ref LL_HRTIM_TIMER_D
7276 * @arg @ref LL_HRTIM_TIMER_E
7277 * @arg @ref LL_HRTIM_TIMER_F
7278 * @param Configuration This parameter must be a combination of all the following values:
7279 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
7280 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
7281 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
7282 * @retval None
7283 */
LL_HRTIM_DT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7284 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7285 {
7286 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7287 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7288 REG_OFFSET_TAB_TIMER[iTimer]));
7289 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
7290 }
7291
7292 /**
7293 * @brief Set the deadtime prescaler value.
7294 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
7295 * @param HRTIMx High Resolution Timer instance
7296 * @param Timer This parameter can be one of the following values:
7297 * @arg @ref LL_HRTIM_TIMER_A
7298 * @arg @ref LL_HRTIM_TIMER_B
7299 * @arg @ref LL_HRTIM_TIMER_C
7300 * @arg @ref LL_HRTIM_TIMER_D
7301 * @arg @ref LL_HRTIM_TIMER_E
7302 * @arg @ref LL_HRTIM_TIMER_F
7303 * @param Prescaler This parameter can be one of the following values:
7304 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7305 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7306 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7307 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7308 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7309 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7310 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7311 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7312 * @retval None
7313 */
LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7314 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7315 {
7316 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7317 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7318 REG_OFFSET_TAB_TIMER[iTimer]));
7319 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
7320 }
7321
7322 /**
7323 * @brief Get actual deadtime prescaler value.
7324 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
7325 * @param HRTIMx High Resolution Timer instance
7326 * @param Timer This parameter can be one of the following values:
7327 * @arg @ref LL_HRTIM_TIMER_A
7328 * @arg @ref LL_HRTIM_TIMER_B
7329 * @arg @ref LL_HRTIM_TIMER_C
7330 * @arg @ref LL_HRTIM_TIMER_D
7331 * @arg @ref LL_HRTIM_TIMER_E
7332 * @arg @ref LL_HRTIM_TIMER_F
7333 * @retval Prescaler This parameter can be one of the following values:
7334 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7335 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7336 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7337 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7338 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7339 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7340 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7341 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7342 */
LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7343 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7344 {
7345 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7346 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7347 REG_OFFSET_TAB_TIMER[iTimer]));
7348 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
7349 }
7350
7351 /**
7352 * @brief Set the deadtime rising value.
7353 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
7354 * @param HRTIMx High Resolution Timer instance
7355 * @param Timer This parameter can be one of the following values:
7356 * @arg @ref LL_HRTIM_TIMER_A
7357 * @arg @ref LL_HRTIM_TIMER_B
7358 * @arg @ref LL_HRTIM_TIMER_C
7359 * @arg @ref LL_HRTIM_TIMER_D
7360 * @arg @ref LL_HRTIM_TIMER_E
7361 * @arg @ref LL_HRTIM_TIMER_F
7362 * @param RisingValue Value between 0 and 0x1FF
7363 * @retval None
7364 */
LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingValue)7365 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
7366 {
7367 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7368 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7369 REG_OFFSET_TAB_TIMER[iTimer]));
7370 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
7371 }
7372
7373 /**
7374 * @brief Get actual deadtime rising value.
7375 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
7376 * @param HRTIMx High Resolution Timer instance
7377 * @param Timer This parameter can be one of the following values:
7378 * @arg @ref LL_HRTIM_TIMER_A
7379 * @arg @ref LL_HRTIM_TIMER_B
7380 * @arg @ref LL_HRTIM_TIMER_C
7381 * @arg @ref LL_HRTIM_TIMER_D
7382 * @arg @ref LL_HRTIM_TIMER_E
7383 * @arg @ref LL_HRTIM_TIMER_F
7384 * @retval RisingValue Value between 0 and 0x1FF
7385 */
LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7386 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7387 {
7388 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7389 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7390 REG_OFFSET_TAB_TIMER[iTimer]));
7391 return (READ_BIT(*pReg, HRTIM_DTR_DTR));
7392 }
7393
7394 /**
7395 * @brief Set the deadtime sign on rising edge.
7396 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
7397 * @param HRTIMx High Resolution Timer instance
7398 * @param Timer This parameter can be one of the following values:
7399 * @arg @ref LL_HRTIM_TIMER_A
7400 * @arg @ref LL_HRTIM_TIMER_B
7401 * @arg @ref LL_HRTIM_TIMER_C
7402 * @arg @ref LL_HRTIM_TIMER_D
7403 * @arg @ref LL_HRTIM_TIMER_E
7404 * @arg @ref LL_HRTIM_TIMER_F
7405 * @param RisingSign This parameter can be one of the following values:
7406 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7407 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7408 * @retval None
7409 */
LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingSign)7410 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
7411 {
7412 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7413 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7414 REG_OFFSET_TAB_TIMER[iTimer]));
7415 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
7416 }
7417
7418 /**
7419 * @brief Get actual deadtime sign on rising edge.
7420 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
7421 * @param HRTIMx High Resolution Timer instance
7422 * @param Timer This parameter can be one of the following values:
7423 * @arg @ref LL_HRTIM_TIMER_A
7424 * @arg @ref LL_HRTIM_TIMER_B
7425 * @arg @ref LL_HRTIM_TIMER_C
7426 * @arg @ref LL_HRTIM_TIMER_D
7427 * @arg @ref LL_HRTIM_TIMER_E
7428 * @arg @ref LL_HRTIM_TIMER_F
7429 * @retval RisingSign This parameter can be one of the following values:
7430 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7431 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7432 */
LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7433 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7434 {
7435 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7436 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7437 REG_OFFSET_TAB_TIMER[iTimer]));
7438 return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
7439 }
7440
7441 /**
7442 * @brief Set the deadime falling value.
7443 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
7444 * @param HRTIMx High Resolution Timer instance
7445 * @param Timer This parameter can be one of the following values:
7446 * @arg @ref LL_HRTIM_TIMER_A
7447 * @arg @ref LL_HRTIM_TIMER_B
7448 * @arg @ref LL_HRTIM_TIMER_C
7449 * @arg @ref LL_HRTIM_TIMER_D
7450 * @arg @ref LL_HRTIM_TIMER_E
7451 * @arg @ref LL_HRTIM_TIMER_F
7452 * @param FallingValue Value between 0 and 0x1FF
7453 * @retval None
7454 */
LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingValue)7455 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
7456 {
7457 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7458 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7459 REG_OFFSET_TAB_TIMER[iTimer]));
7460 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
7461 }
7462
7463 /**
7464 * @brief Get actual deadtime falling value
7465 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
7466 * @param HRTIMx High Resolution Timer instance
7467 * @param Timer This parameter can be one of the following values:
7468 * @arg @ref LL_HRTIM_TIMER_A
7469 * @arg @ref LL_HRTIM_TIMER_B
7470 * @arg @ref LL_HRTIM_TIMER_C
7471 * @arg @ref LL_HRTIM_TIMER_D
7472 * @arg @ref LL_HRTIM_TIMER_E
7473 * @arg @ref LL_HRTIM_TIMER_F
7474 * @retval FallingValue Value between 0 and 0x1FF
7475 */
LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7476 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7477 {
7478 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7479 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7480 REG_OFFSET_TAB_TIMER[iTimer]));
7481 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
7482 }
7483
7484 /**
7485 * @brief Set the deadtime sign on falling edge.
7486 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
7487 * @param HRTIMx High Resolution Timer instance
7488 * @param Timer This parameter can be one of the following values:
7489 * @arg @ref LL_HRTIM_TIMER_A
7490 * @arg @ref LL_HRTIM_TIMER_B
7491 * @arg @ref LL_HRTIM_TIMER_C
7492 * @arg @ref LL_HRTIM_TIMER_D
7493 * @arg @ref LL_HRTIM_TIMER_E
7494 * @arg @ref LL_HRTIM_TIMER_F
7495 * @param FallingSign This parameter can be one of the following values:
7496 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7497 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7498 * @retval None
7499 */
LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingSign)7500 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
7501 {
7502 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7503 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7504 REG_OFFSET_TAB_TIMER[iTimer]));
7505 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
7506 }
7507
7508 /**
7509 * @brief Get actual deadtime sign on falling edge.
7510 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
7511 * @param HRTIMx High Resolution Timer instance
7512 * @param Timer This parameter can be one of the following values:
7513 * @arg @ref LL_HRTIM_TIMER_A
7514 * @arg @ref LL_HRTIM_TIMER_B
7515 * @arg @ref LL_HRTIM_TIMER_C
7516 * @arg @ref LL_HRTIM_TIMER_D
7517 * @arg @ref LL_HRTIM_TIMER_E
7518 * @arg @ref LL_HRTIM_TIMER_F
7519 * @retval FallingSign This parameter can be one of the following values:
7520 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7521 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7522 */
LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7523 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7524 {
7525 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7526 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7527 REG_OFFSET_TAB_TIMER[iTimer]));
7528 return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
7529 }
7530
7531 /**
7532 * @brief Lock the deadtime value and sign on rising edge.
7533 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
7534 * @param HRTIMx High Resolution Timer instance
7535 * @param Timer This parameter can be one of the following values:
7536 * @arg @ref LL_HRTIM_TIMER_A
7537 * @arg @ref LL_HRTIM_TIMER_B
7538 * @arg @ref LL_HRTIM_TIMER_C
7539 * @arg @ref LL_HRTIM_TIMER_D
7540 * @arg @ref LL_HRTIM_TIMER_E
7541 * @arg @ref LL_HRTIM_TIMER_F
7542 * @retval None
7543 */
LL_HRTIM_DT_LockRising(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7544 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7545 {
7546 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7547 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7548 REG_OFFSET_TAB_TIMER[iTimer]));
7549 SET_BIT(*pReg, HRTIM_DTR_DTRLK);
7550 }
7551
7552 /**
7553 * @brief Lock the deadtime sign on rising edge.
7554 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
7555 * @param HRTIMx High Resolution Timer instance
7556 * @param Timer This parameter can be one of the following values:
7557 * @arg @ref LL_HRTIM_TIMER_A
7558 * @arg @ref LL_HRTIM_TIMER_B
7559 * @arg @ref LL_HRTIM_TIMER_C
7560 * @arg @ref LL_HRTIM_TIMER_D
7561 * @arg @ref LL_HRTIM_TIMER_E
7562 * @arg @ref LL_HRTIM_TIMER_F
7563 * @retval None
7564 */
LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7565 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7566 {
7567 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7568 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7569 REG_OFFSET_TAB_TIMER[iTimer]));
7570 SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
7571 }
7572
7573 /**
7574 * @brief Lock the deadtime value and sign on falling edge.
7575 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
7576 * @param HRTIMx High Resolution Timer instance
7577 * @param Timer This parameter can be one of the following values:
7578 * @arg @ref LL_HRTIM_TIMER_A
7579 * @arg @ref LL_HRTIM_TIMER_B
7580 * @arg @ref LL_HRTIM_TIMER_C
7581 * @arg @ref LL_HRTIM_TIMER_D
7582 * @arg @ref LL_HRTIM_TIMER_E
7583 * @arg @ref LL_HRTIM_TIMER_F
7584 * @retval None
7585 */
LL_HRTIM_DT_LockFalling(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7586 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7587 {
7588 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7589 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7590 REG_OFFSET_TAB_TIMER[iTimer]));
7591 SET_BIT(*pReg, HRTIM_DTR_DTFLK);
7592 }
7593
7594 /**
7595 * @brief Lock the deadtime sign on falling edge.
7596 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
7597 * @param HRTIMx High Resolution Timer instance
7598 * @param Timer This parameter can be one of the following values:
7599 * @arg @ref LL_HRTIM_TIMER_A
7600 * @arg @ref LL_HRTIM_TIMER_B
7601 * @arg @ref LL_HRTIM_TIMER_C
7602 * @arg @ref LL_HRTIM_TIMER_D
7603 * @arg @ref LL_HRTIM_TIMER_E
7604 * @arg @ref LL_HRTIM_TIMER_F
7605 * @retval None
7606 */
LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7607 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7608 {
7609 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7610 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7611 REG_OFFSET_TAB_TIMER[iTimer]));
7612 SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
7613 }
7614
7615 /**
7616 * @}
7617 */
7618
7619 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
7620 * @{
7621 */
7622
7623 /**
7624 * @brief Configure the chopper stage for a given timer.
7625 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
7626 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
7627 * CHPxR STRTPW LL_HRTIM_CHP_Config
7628 * @note This function must not be called if the chopper mode is already
7629 * enabled for one of the timer outputs.
7630 * @param HRTIMx High Resolution Timer instance
7631 * @param Timer This parameter can be one of the following values:
7632 * @arg @ref LL_HRTIM_TIMER_A
7633 * @arg @ref LL_HRTIM_TIMER_B
7634 * @arg @ref LL_HRTIM_TIMER_C
7635 * @arg @ref LL_HRTIM_TIMER_D
7636 * @arg @ref LL_HRTIM_TIMER_E
7637 * @arg @ref LL_HRTIM_TIMER_F
7638 * @param Configuration This parameter must be a combination of all the following values:
7639 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
7640 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
7641 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
7642 * @retval None
7643 */
LL_HRTIM_CHP_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7644 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7645 {
7646 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7647 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7648 REG_OFFSET_TAB_TIMER[iTimer]));
7649 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
7650 }
7651
7652 /**
7653 * @brief Set prescaler determining the carrier frequency to be added on top
7654 * of the timer output signals when chopper mode is enabled.
7655 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
7656 * @note This function must not be called if the chopper mode is already
7657 * enabled for one of the timer outputs.
7658 * @param HRTIMx High Resolution Timer instance
7659 * @param Timer This parameter can be one of the following values:
7660 * @arg @ref LL_HRTIM_TIMER_A
7661 * @arg @ref LL_HRTIM_TIMER_B
7662 * @arg @ref LL_HRTIM_TIMER_C
7663 * @arg @ref LL_HRTIM_TIMER_D
7664 * @arg @ref LL_HRTIM_TIMER_E
7665 * @arg @ref LL_HRTIM_TIMER_F
7666 * @param Prescaler This parameter can be one of the following values:
7667 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7668 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7669 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7670 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7671 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7672 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7673 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7674 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7675 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7676 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7677 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7678 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7679 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7680 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7681 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7682 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7683 * @retval None
7684 */
LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7685 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7686 {
7687 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7688 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7689 REG_OFFSET_TAB_TIMER[iTimer]));
7690 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
7691 }
7692
7693 /**
7694 * @brief Get actual chopper stage prescaler value.
7695 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
7696 * @param HRTIMx High Resolution Timer instance
7697 * @param Timer This parameter can be one of the following values:
7698 * @arg @ref LL_HRTIM_TIMER_A
7699 * @arg @ref LL_HRTIM_TIMER_B
7700 * @arg @ref LL_HRTIM_TIMER_C
7701 * @arg @ref LL_HRTIM_TIMER_D
7702 * @arg @ref LL_HRTIM_TIMER_E
7703 * @arg @ref LL_HRTIM_TIMER_F
7704 * @retval Prescaler This parameter can be one of the following values:
7705 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7706 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7707 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7708 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7709 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7710 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7711 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7712 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7713 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7714 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7715 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7716 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7717 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7718 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7719 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7720 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7721 */
LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7722 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7723 {
7724 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7725 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7726 REG_OFFSET_TAB_TIMER[iTimer]));
7727 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
7728 }
7729
7730 /**
7731 * @brief Set the chopper duty cycle.
7732 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
7733 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
7734 * @note This function must not be called if the chopper mode is already
7735 * enabled for one of the timer outputs.
7736 * @param HRTIMx High Resolution Timer instance
7737 * @param Timer This parameter can be one of the following values:
7738 * @arg @ref LL_HRTIM_TIMER_A
7739 * @arg @ref LL_HRTIM_TIMER_B
7740 * @arg @ref LL_HRTIM_TIMER_C
7741 * @arg @ref LL_HRTIM_TIMER_D
7742 * @arg @ref LL_HRTIM_TIMER_E
7743 * @arg @ref LL_HRTIM_TIMER_F
7744 * @param DutyCycle This parameter can be one of the following values:
7745 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7746 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7747 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7748 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7749 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7750 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7751 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7752 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7753 * @retval None
7754 */
LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DutyCycle)7755 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
7756 {
7757 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7759 REG_OFFSET_TAB_TIMER[iTimer]));
7760 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
7761 }
7762
7763 /**
7764 * @brief Get actual chopper duty cycle.
7765 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
7766 * @param HRTIMx High Resolution Timer instance
7767 * @param Timer This parameter can be one of the following values:
7768 * @arg @ref LL_HRTIM_TIMER_A
7769 * @arg @ref LL_HRTIM_TIMER_B
7770 * @arg @ref LL_HRTIM_TIMER_C
7771 * @arg @ref LL_HRTIM_TIMER_D
7772 * @arg @ref LL_HRTIM_TIMER_E
7773 * @arg @ref LL_HRTIM_TIMER_F
7774 * @retval DutyCycle This parameter can be one of the following values:
7775 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7776 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7777 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7778 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7779 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7780 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7781 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7782 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7783 */
LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7784 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7785 {
7786 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7787 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7788 REG_OFFSET_TAB_TIMER[iTimer]));
7789 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
7790 }
7791
7792 /**
7793 * @brief Set the start pulse width.
7794 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
7795 * @note This function must not be called if the chopper mode is already
7796 * enabled for one of the timer outputs.
7797 * @param HRTIMx High Resolution Timer instance
7798 * @param Timer This parameter can be one of the following values:
7799 * @arg @ref LL_HRTIM_TIMER_A
7800 * @arg @ref LL_HRTIM_TIMER_B
7801 * @arg @ref LL_HRTIM_TIMER_C
7802 * @arg @ref LL_HRTIM_TIMER_D
7803 * @arg @ref LL_HRTIM_TIMER_E
7804 * @arg @ref LL_HRTIM_TIMER_F
7805 * @param PulseWidth This parameter can be one of the following values:
7806 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7807 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7808 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7809 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7810 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7811 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7812 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7813 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7814 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7815 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7816 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7817 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7818 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7819 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7820 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7821 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7822 * @retval None
7823 */
LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t PulseWidth)7824 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
7825 {
7826 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7827 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7828 REG_OFFSET_TAB_TIMER[iTimer]));
7829 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
7830 }
7831
7832 /**
7833 * @brief Get actual start pulse width.
7834 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
7835 * @param HRTIMx High Resolution Timer instance
7836 * @param Timer This parameter can be one of the following values:
7837 * @arg @ref LL_HRTIM_TIMER_A
7838 * @arg @ref LL_HRTIM_TIMER_B
7839 * @arg @ref LL_HRTIM_TIMER_C
7840 * @arg @ref LL_HRTIM_TIMER_D
7841 * @arg @ref LL_HRTIM_TIMER_E
7842 * @arg @ref LL_HRTIM_TIMER_F
7843 * @retval PulseWidth This parameter can be one of the following values:
7844 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7845 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7846 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7847 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7848 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7849 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7850 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7851 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7852 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7853 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7854 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7855 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7856 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7857 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7858 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7859 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7860 */
LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7861 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7862 {
7863 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7864 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7865 REG_OFFSET_TAB_TIMER[iTimer]));
7866 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
7867 }
7868
7869 /**
7870 * @}
7871 */
7872
7873 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
7874 * @{
7875 */
7876
7877 /**
7878 * @brief Set the timer output set source.
7879 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7880 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7881 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7882 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7883 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7884 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7885 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7886 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7887 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7888 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7889 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7890 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7891 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7892 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7893 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7894 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7895 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7896 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7897 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7898 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7899 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7900 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7901 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7902 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7903 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7904 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7905 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7906 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7907 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7908 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7909 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7910 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
7911 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7912 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7913 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7914 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7915 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7916 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7917 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7918 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7919 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7920 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7921 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7922 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7923 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7924 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7925 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7926 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7927 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7928 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7929 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7930 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7931 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7932 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7933 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7934 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7935 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7936 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7937 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7938 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7939 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7940 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7941 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7942 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
7943 * @param HRTIMx High Resolution Timer instance
7944 * @param Output This parameter can be one of the following values:
7945 * @arg @ref LL_HRTIM_OUTPUT_TA1
7946 * @arg @ref LL_HRTIM_OUTPUT_TA2
7947 * @arg @ref LL_HRTIM_OUTPUT_TB1
7948 * @arg @ref LL_HRTIM_OUTPUT_TB2
7949 * @arg @ref LL_HRTIM_OUTPUT_TC1
7950 * @arg @ref LL_HRTIM_OUTPUT_TC2
7951 * @arg @ref LL_HRTIM_OUTPUT_TD1
7952 * @arg @ref LL_HRTIM_OUTPUT_TD2
7953 * @arg @ref LL_HRTIM_OUTPUT_TE1
7954 * @arg @ref LL_HRTIM_OUTPUT_TE2
7955 * @arg @ref LL_HRTIM_OUTPUT_TF1
7956 * @arg @ref LL_HRTIM_OUTPUT_TF2
7957 * @param SetSrc This parameter can be a combination of the following values:
7958 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
7959 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
7960 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
7961 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
7962 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
7963 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
7964 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
7965 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
7966 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
7967 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
7968 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
7969 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
7970 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
7971 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
7972 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
7973 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
7974 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
7975 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
7976 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
7977 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
7978 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
7979 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
7980 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
7981 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
7982 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
7983 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
7984 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
7985 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
7986 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
7987 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
7988 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
7989 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
7990 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
7991 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
7992 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
7993 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
7994 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
7995 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
7996 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
7997 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
7998 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
7999 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8000 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8001 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8002 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8003 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8004 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8005 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8006 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8007 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8008 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8009 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8010 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8011 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8012 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8013 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8014 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8015 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8016 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8017 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8018 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8019 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8020 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8021 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8022 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8023 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8024 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8025 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8026 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8027 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8028 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8029 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8030 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8031 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8032 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8033 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8034 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8035 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8036 * @retval None
8037 */
LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t SetSrc)8038 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
8039 {
8040 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8041 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8042 REG_OFFSET_TAB_SETxR[iOutput]));
8043 WRITE_REG(*pReg, SetSrc);
8044 }
8045
8046 /**
8047 * @brief Get the timer output set source.
8048 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8049 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8050 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8051 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8052 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8053 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8054 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8055 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8056 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8057 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8058 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8059 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8060 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8061 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8062 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8063 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8064 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8065 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8066 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8067 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8068 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8069 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8070 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8071 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8072 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8073 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8074 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8075 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8076 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8077 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8078 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8079 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
8080 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8081 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8082 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8083 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8084 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8085 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8086 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8087 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8088 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8089 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8090 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8091 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8092 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8093 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8094 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8095 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8096 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8097 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8098 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8099 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8100 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8101 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8102 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8103 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8104 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8105 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8106 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8107 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8108 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8109 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8110 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8111 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
8112 * @param HRTIMx High Resolution Timer instance
8113 * @param Output This parameter can be one of the following values:
8114 * @arg @ref LL_HRTIM_OUTPUT_TA1
8115 * @arg @ref LL_HRTIM_OUTPUT_TA2
8116 * @arg @ref LL_HRTIM_OUTPUT_TB1
8117 * @arg @ref LL_HRTIM_OUTPUT_TB2
8118 * @arg @ref LL_HRTIM_OUTPUT_TC1
8119 * @arg @ref LL_HRTIM_OUTPUT_TC2
8120 * @arg @ref LL_HRTIM_OUTPUT_TD1
8121 * @arg @ref LL_HRTIM_OUTPUT_TD2
8122 * @arg @ref LL_HRTIM_OUTPUT_TE1
8123 * @arg @ref LL_HRTIM_OUTPUT_TE2
8124 * @arg @ref LL_HRTIM_OUTPUT_TF1
8125 * @arg @ref LL_HRTIM_OUTPUT_TF2
8126 * @retval SetSrc This parameter can be a combination of the following values:
8127 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
8128 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
8129 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
8130 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
8131 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
8132 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
8133 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
8134 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
8135 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
8136 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
8137 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
8138 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
8139 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
8140 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
8141 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
8142 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
8143 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
8144 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
8145 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
8146 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
8147 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
8148 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
8149 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
8150 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
8151 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
8152 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
8153 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
8154 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
8155 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
8156 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
8157 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8158 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8159 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8160 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8161 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8162 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8163 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
8164 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
8165 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
8166 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8167 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8168 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8169 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8170 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8171 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8172 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8173 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8174 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8175 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8176 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8177 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8178 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8179 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8180 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8181 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8182 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8183 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8184 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8185 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8186 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8187 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8188 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8189 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8190 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8191 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8192 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8193 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8194 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8195 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8196 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8197 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8198 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8199 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8200 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8201 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8202 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8203 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8204 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8205 */
LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output)8206 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8207 {
8208 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8209 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8210 REG_OFFSET_TAB_SETxR[iOutput]));
8211 return (uint32_t) READ_REG(*pReg);
8212 }
8213
8214 /**
8215 * @brief Set the timer output reset source.
8216 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8217 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8218 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8219 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8220 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8221 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8222 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8223 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8224 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8225 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8226 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8227 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8228 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8229 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8230 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8231 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8232 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8233 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8234 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8235 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8236 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8237 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8238 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8239 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8240 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8241 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8242 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8243 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8244 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8245 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8246 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8247 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
8248 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8249 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8250 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8251 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8252 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8253 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8254 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8255 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8256 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8257 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8258 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8259 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8260 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8261 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8262 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8263 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8264 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8265 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8266 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8267 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8268 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8269 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8270 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8271 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8272 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8273 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8274 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8275 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8276 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8277 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8278 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8279 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
8280 * @param HRTIMx High Resolution Timer instance
8281 * @param Output This parameter can be one of the following values:
8282 * @arg @ref LL_HRTIM_OUTPUT_TA1
8283 * @arg @ref LL_HRTIM_OUTPUT_TA2
8284 * @arg @ref LL_HRTIM_OUTPUT_TB1
8285 * @arg @ref LL_HRTIM_OUTPUT_TB2
8286 * @arg @ref LL_HRTIM_OUTPUT_TC1
8287 * @arg @ref LL_HRTIM_OUTPUT_TC2
8288 * @arg @ref LL_HRTIM_OUTPUT_TD1
8289 * @arg @ref LL_HRTIM_OUTPUT_TD2
8290 * @arg @ref LL_HRTIM_OUTPUT_TE1
8291 * @arg @ref LL_HRTIM_OUTPUT_TE2
8292 * @arg @ref LL_HRTIM_OUTPUT_TF1
8293 * @arg @ref LL_HRTIM_OUTPUT_TF2
8294 * @param ResetSrc This parameter can be a combination of the following values:
8295 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8296 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8297 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8298 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8299 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8300 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8301 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8302 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8303 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8304 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8305 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8306 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8307 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8308 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8309 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8310 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8311 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8312 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8313 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8314 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8315 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8316 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8317 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8318 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8319 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8320 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8321 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8322 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8323 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8324 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8325 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8326 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8327 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8328 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8329 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8330 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8331 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8332 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8333 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8334 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8335 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8336 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8337 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8338 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8339 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8340 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8341 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8342 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8343 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8344 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8345 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8346 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8347 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8348 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8349 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8350 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8351 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8352 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8353 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8354 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8355 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8356 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8357 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8358 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8359 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8360 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8361 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8362 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8363 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8364 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8365 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8366 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8367 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8368 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8369 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8370 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8371 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8372 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8373 * @retval None
8374 */
LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ResetSrc)8375 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
8376 {
8377 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8378 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8379 REG_OFFSET_TAB_SETxR[iOutput]));
8380 WRITE_REG(*pReg, ResetSrc);
8381 }
8382
8383 /**
8384 * @brief Get the timer output set source.
8385 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8386 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8387 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8388 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8389 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8390 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8391 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8392 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8393 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8394 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8395 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8396 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8397 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8398 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8399 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8400 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8401 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8402 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8403 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8404 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8405 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8406 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8407 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8408 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8409 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8410 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8411 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8412 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8413 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8414 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8415 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8416 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
8417 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8418 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8419 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8420 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8421 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8422 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8423 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8424 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8425 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8426 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8427 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8428 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8429 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8430 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8431 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8432 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8433 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8434 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8435 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8436 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8437 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8438 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8439 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8440 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8441 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8442 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8443 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8444 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8445 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8446 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8447 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8448 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
8449 * @param HRTIMx High Resolution Timer instance
8450 * @param Output This parameter can be one of the following values:
8451 * @arg @ref LL_HRTIM_OUTPUT_TA1
8452 * @arg @ref LL_HRTIM_OUTPUT_TA2
8453 * @arg @ref LL_HRTIM_OUTPUT_TB1
8454 * @arg @ref LL_HRTIM_OUTPUT_TB2
8455 * @arg @ref LL_HRTIM_OUTPUT_TC1
8456 * @arg @ref LL_HRTIM_OUTPUT_TC2
8457 * @arg @ref LL_HRTIM_OUTPUT_TD1
8458 * @arg @ref LL_HRTIM_OUTPUT_TD2
8459 * @arg @ref LL_HRTIM_OUTPUT_TE1
8460 * @arg @ref LL_HRTIM_OUTPUT_TE2
8461 * @arg @ref LL_HRTIM_OUTPUT_TF1
8462 * @arg @ref LL_HRTIM_OUTPUT_TF2
8463 * @retval ResetSrc This parameter can be a combination of the following values:
8464 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8465 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8466 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8467 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8468 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8469 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8470 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8471 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8472 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8473 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8474 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8475 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8476 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8477 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8478 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8479 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8480 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8481 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8482 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8483 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8484 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8485 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8486 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8487 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8488 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8489 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8490 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8491 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8492 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8493 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8494 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8495 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8496 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8497 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8498 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8499 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8500 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8501 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8502 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8503 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8504 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8505 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8506 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8507 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8508 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8509 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8510 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8511 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8512 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8513 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8514 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8515 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8516 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8517 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8518 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8519 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8520 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8521 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8522 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8523 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8524 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8525 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8526 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8527 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8528 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8529 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8530 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8531 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8532 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8533 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8534 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8535 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8536 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8537 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8538 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8539 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8540 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8541 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8542 */
LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output)8543 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8544 {
8545 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8546 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8547 REG_OFFSET_TAB_SETxR[iOutput]));
8548 return (uint32_t) READ_REG(*pReg);
8549 }
8550
8551 /**
8552 * @brief Configure a timer output.
8553 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
8554 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
8555 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
8556 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
8557 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
8558 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
8559 * OUTxR POL2 LL_HRTIM_OUT_Config\n
8560 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
8561 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
8562 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
8563 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
8564 * OUTxR DIDL2 LL_HRTIM_OUT_Config
8565 * @param HRTIMx High Resolution Timer instance
8566 * @param Output This parameter can be one of the following values:
8567 * @arg @ref LL_HRTIM_OUTPUT_TA1
8568 * @arg @ref LL_HRTIM_OUTPUT_TA2
8569 * @arg @ref LL_HRTIM_OUTPUT_TB1
8570 * @arg @ref LL_HRTIM_OUTPUT_TB2
8571 * @arg @ref LL_HRTIM_OUTPUT_TC1
8572 * @arg @ref LL_HRTIM_OUTPUT_TC2
8573 * @arg @ref LL_HRTIM_OUTPUT_TD1
8574 * @arg @ref LL_HRTIM_OUTPUT_TD2
8575 * @arg @ref LL_HRTIM_OUTPUT_TE1
8576 * @arg @ref LL_HRTIM_OUTPUT_TE2
8577 * @arg @ref LL_HRTIM_OUTPUT_TF1
8578 * @arg @ref LL_HRTIM_OUTPUT_TF2
8579 * @param Configuration This parameter must be a combination of all the following values:
8580 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8581 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8582 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8583 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8584 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8585 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8586 * @retval None
8587 */
LL_HRTIM_OUT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Configuration)8588 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
8589 {
8590 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8591 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8592 REG_OFFSET_TAB_OUTxR[iOutput]));
8593 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
8594 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
8595 }
8596
8597 /**
8598 * @brief Set the polarity of a timer output.
8599 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
8600 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
8601 * @param HRTIMx High Resolution Timer instance
8602 * @param Output This parameter can be one of the following values:
8603 * @arg @ref LL_HRTIM_OUTPUT_TA1
8604 * @arg @ref LL_HRTIM_OUTPUT_TA2
8605 * @arg @ref LL_HRTIM_OUTPUT_TB1
8606 * @arg @ref LL_HRTIM_OUTPUT_TB2
8607 * @arg @ref LL_HRTIM_OUTPUT_TC1
8608 * @arg @ref LL_HRTIM_OUTPUT_TC2
8609 * @arg @ref LL_HRTIM_OUTPUT_TD1
8610 * @arg @ref LL_HRTIM_OUTPUT_TD2
8611 * @arg @ref LL_HRTIM_OUTPUT_TE1
8612 * @arg @ref LL_HRTIM_OUTPUT_TE2
8613 * @arg @ref LL_HRTIM_OUTPUT_TF1
8614 * @arg @ref LL_HRTIM_OUTPUT_TF2
8615 * @param Polarity This parameter can be one of the following values:
8616 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8617 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8618 * @retval None
8619 */
LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Polarity)8620 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
8621 {
8622 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8623 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8624 REG_OFFSET_TAB_OUTxR[iOutput]));
8625 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
8626 }
8627
8628 /**
8629 * @brief Get actual polarity of the timer output.
8630 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
8631 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
8632 * @param HRTIMx High Resolution Timer instance
8633 * @param Output This parameter can be one of the following values:
8634 * @arg @ref LL_HRTIM_OUTPUT_TA1
8635 * @arg @ref LL_HRTIM_OUTPUT_TA2
8636 * @arg @ref LL_HRTIM_OUTPUT_TB1
8637 * @arg @ref LL_HRTIM_OUTPUT_TB2
8638 * @arg @ref LL_HRTIM_OUTPUT_TC1
8639 * @arg @ref LL_HRTIM_OUTPUT_TC2
8640 * @arg @ref LL_HRTIM_OUTPUT_TD1
8641 * @arg @ref LL_HRTIM_OUTPUT_TD2
8642 * @arg @ref LL_HRTIM_OUTPUT_TE1
8643 * @arg @ref LL_HRTIM_OUTPUT_TE2
8644 * @arg @ref LL_HRTIM_OUTPUT_TF1
8645 * @arg @ref LL_HRTIM_OUTPUT_TF2
8646 * @retval Polarity This parameter can be one of the following values:
8647 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8648 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8649 */
LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output)8650 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8651 {
8652 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8653 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8654 REG_OFFSET_TAB_OUTxR[iOutput]));
8655 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8656 }
8657
8658 /**
8659 * @brief Set the output IDLE mode.
8660 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
8661 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
8662 * @note This function must not be called when the burst mode is active
8663 * @param HRTIMx High Resolution Timer instance
8664 * @param Output This parameter can be one of the following values:
8665 * @arg @ref LL_HRTIM_OUTPUT_TA1
8666 * @arg @ref LL_HRTIM_OUTPUT_TA2
8667 * @arg @ref LL_HRTIM_OUTPUT_TB1
8668 * @arg @ref LL_HRTIM_OUTPUT_TB2
8669 * @arg @ref LL_HRTIM_OUTPUT_TC1
8670 * @arg @ref LL_HRTIM_OUTPUT_TC2
8671 * @arg @ref LL_HRTIM_OUTPUT_TD1
8672 * @arg @ref LL_HRTIM_OUTPUT_TD2
8673 * @arg @ref LL_HRTIM_OUTPUT_TE1
8674 * @arg @ref LL_HRTIM_OUTPUT_TE2
8675 * @arg @ref LL_HRTIM_OUTPUT_TF1
8676 * @arg @ref LL_HRTIM_OUTPUT_TF2
8677 * @param IdleMode This parameter can be one of the following values:
8678 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8679 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8680 * @retval None
8681 */
LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleMode)8682 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
8683 {
8684 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8685 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8686 REG_OFFSET_TAB_OUTxR[iOutput]));
8687 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
8688 }
8689
8690 /**
8691 * @brief Get actual output IDLE mode.
8692 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
8693 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
8694 * @param HRTIMx High Resolution Timer instance
8695 * @param Output This parameter can be one of the following values:
8696 * @arg @ref LL_HRTIM_OUTPUT_TA1
8697 * @arg @ref LL_HRTIM_OUTPUT_TA2
8698 * @arg @ref LL_HRTIM_OUTPUT_TB1
8699 * @arg @ref LL_HRTIM_OUTPUT_TB2
8700 * @arg @ref LL_HRTIM_OUTPUT_TC1
8701 * @arg @ref LL_HRTIM_OUTPUT_TC2
8702 * @arg @ref LL_HRTIM_OUTPUT_TD1
8703 * @arg @ref LL_HRTIM_OUTPUT_TD2
8704 * @arg @ref LL_HRTIM_OUTPUT_TE1
8705 * @arg @ref LL_HRTIM_OUTPUT_TE2
8706 * @arg @ref LL_HRTIM_OUTPUT_TF1
8707 * @arg @ref LL_HRTIM_OUTPUT_TF2
8708 * @retval IdleMode This parameter can be one of the following values:
8709 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8710 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8711 */
LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8712 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8713 {
8714 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8715 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8716 REG_OFFSET_TAB_OUTxR[iOutput]));
8717 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8718 }
8719
8720 /**
8721 * @brief Set the output IDLE level.
8722 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
8723 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
8724 * @note This function must be called prior enabling the timer.
8725 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
8726 * @param HRTIMx High Resolution Timer instance
8727 * @param Output This parameter can be one of the following values:
8728 * @arg @ref LL_HRTIM_OUTPUT_TA1
8729 * @arg @ref LL_HRTIM_OUTPUT_TA2
8730 * @arg @ref LL_HRTIM_OUTPUT_TB1
8731 * @arg @ref LL_HRTIM_OUTPUT_TB2
8732 * @arg @ref LL_HRTIM_OUTPUT_TC1
8733 * @arg @ref LL_HRTIM_OUTPUT_TC2
8734 * @arg @ref LL_HRTIM_OUTPUT_TD1
8735 * @arg @ref LL_HRTIM_OUTPUT_TD2
8736 * @arg @ref LL_HRTIM_OUTPUT_TE1
8737 * @arg @ref LL_HRTIM_OUTPUT_TE2
8738 * @arg @ref LL_HRTIM_OUTPUT_TF1
8739 * @arg @ref LL_HRTIM_OUTPUT_TF2
8740 * @param IdleLevel This parameter can be one of the following values:
8741 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8742 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8743 * @retval None
8744 */
LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleLevel)8745 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
8746 {
8747 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8748 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8749 REG_OFFSET_TAB_OUTxR[iOutput]));
8750 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
8751 }
8752
8753 /**
8754 * @brief Get actual output IDLE level.
8755 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
8756 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
8757 * @param HRTIMx High Resolution Timer instance
8758 * @param Output This parameter can be one of the following values:
8759 * @arg @ref LL_HRTIM_OUTPUT_TA1
8760 * @arg @ref LL_HRTIM_OUTPUT_TA2
8761 * @arg @ref LL_HRTIM_OUTPUT_TB1
8762 * @arg @ref LL_HRTIM_OUTPUT_TB2
8763 * @arg @ref LL_HRTIM_OUTPUT_TC1
8764 * @arg @ref LL_HRTIM_OUTPUT_TC2
8765 * @arg @ref LL_HRTIM_OUTPUT_TD1
8766 * @arg @ref LL_HRTIM_OUTPUT_TD2
8767 * @arg @ref LL_HRTIM_OUTPUT_TE1
8768 * @arg @ref LL_HRTIM_OUTPUT_TE2
8769 * @arg @ref LL_HRTIM_OUTPUT_TF1
8770 * @arg @ref LL_HRTIM_OUTPUT_TF2
8771 * @retval IdleLevel This parameter can be one of the following values:
8772 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8773 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8774 */
LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output)8775 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8776 {
8777 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8778 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8779 REG_OFFSET_TAB_OUTxR[iOutput]));
8780 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8781 }
8782
8783 /**
8784 * @brief Set the output FAULT state.
8785 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
8786 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
8787 * @note This function must not called when the timer is enabled and a fault
8788 * channel is enabled at timer level.
8789 * @param HRTIMx High Resolution Timer instance
8790 * @param Output This parameter can be one of the following values:
8791 * @arg @ref LL_HRTIM_OUTPUT_TA1
8792 * @arg @ref LL_HRTIM_OUTPUT_TA2
8793 * @arg @ref LL_HRTIM_OUTPUT_TB1
8794 * @arg @ref LL_HRTIM_OUTPUT_TB2
8795 * @arg @ref LL_HRTIM_OUTPUT_TC1
8796 * @arg @ref LL_HRTIM_OUTPUT_TC2
8797 * @arg @ref LL_HRTIM_OUTPUT_TD1
8798 * @arg @ref LL_HRTIM_OUTPUT_TD2
8799 * @arg @ref LL_HRTIM_OUTPUT_TE1
8800 * @arg @ref LL_HRTIM_OUTPUT_TE2
8801 * @arg @ref LL_HRTIM_OUTPUT_TF1
8802 * @arg @ref LL_HRTIM_OUTPUT_TF2
8803 * @param FaultState This parameter can be one of the following values:
8804 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8805 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8806 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8807 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8808 * @retval None
8809 */
LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t FaultState)8810 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
8811 {
8812 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8813 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8814 REG_OFFSET_TAB_OUTxR[iOutput]));
8815 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
8816 }
8817
8818 /**
8819 * @brief Get actual FAULT state.
8820 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
8821 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
8822 * @param HRTIMx High Resolution Timer instance
8823 * @param Output This parameter can be one of the following values:
8824 * @arg @ref LL_HRTIM_OUTPUT_TA1
8825 * @arg @ref LL_HRTIM_OUTPUT_TA2
8826 * @arg @ref LL_HRTIM_OUTPUT_TB1
8827 * @arg @ref LL_HRTIM_OUTPUT_TB2
8828 * @arg @ref LL_HRTIM_OUTPUT_TC1
8829 * @arg @ref LL_HRTIM_OUTPUT_TC2
8830 * @arg @ref LL_HRTIM_OUTPUT_TD1
8831 * @arg @ref LL_HRTIM_OUTPUT_TD2
8832 * @arg @ref LL_HRTIM_OUTPUT_TE1
8833 * @arg @ref LL_HRTIM_OUTPUT_TE2
8834 * @arg @ref LL_HRTIM_OUTPUT_TF1
8835 * @arg @ref LL_HRTIM_OUTPUT_TF2
8836 * @retval FaultState This parameter can be one of the following values:
8837 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8838 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8839 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8840 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8841 */
LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output)8842 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8843 {
8844 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8845 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8846 REG_OFFSET_TAB_OUTxR[iOutput]));
8847 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8848 }
8849
8850 /**
8851 * @brief Set the output chopper mode.
8852 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
8853 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
8854 * @note This function must not called when the timer is enabled.
8855 * @param HRTIMx High Resolution Timer instance
8856 * @param Output This parameter can be one of the following values:
8857 * @arg @ref LL_HRTIM_OUTPUT_TA1
8858 * @arg @ref LL_HRTIM_OUTPUT_TA2
8859 * @arg @ref LL_HRTIM_OUTPUT_TB1
8860 * @arg @ref LL_HRTIM_OUTPUT_TB2
8861 * @arg @ref LL_HRTIM_OUTPUT_TC1
8862 * @arg @ref LL_HRTIM_OUTPUT_TC2
8863 * @arg @ref LL_HRTIM_OUTPUT_TD1
8864 * @arg @ref LL_HRTIM_OUTPUT_TD2
8865 * @arg @ref LL_HRTIM_OUTPUT_TE1
8866 * @arg @ref LL_HRTIM_OUTPUT_TE2
8867 * @arg @ref LL_HRTIM_OUTPUT_TF1
8868 * @arg @ref LL_HRTIM_OUTPUT_TF2
8869 * @param ChopperMode This parameter can be one of the following values:
8870 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8871 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8872 * @retval None
8873 */
LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ChopperMode)8874 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
8875 {
8876 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8877 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8878 REG_OFFSET_TAB_OUTxR[iOutput]));
8879 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8880 }
8881
8882 /**
8883 * @brief Get actual output chopper mode
8884 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
8885 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
8886 * @param HRTIMx High Resolution Timer instance
8887 * @param Output This parameter can be one of the following values:
8888 * @arg @ref LL_HRTIM_OUTPUT_TA1
8889 * @arg @ref LL_HRTIM_OUTPUT_TA2
8890 * @arg @ref LL_HRTIM_OUTPUT_TB1
8891 * @arg @ref LL_HRTIM_OUTPUT_TB2
8892 * @arg @ref LL_HRTIM_OUTPUT_TC1
8893 * @arg @ref LL_HRTIM_OUTPUT_TC2
8894 * @arg @ref LL_HRTIM_OUTPUT_TD1
8895 * @arg @ref LL_HRTIM_OUTPUT_TD2
8896 * @arg @ref LL_HRTIM_OUTPUT_TE1
8897 * @arg @ref LL_HRTIM_OUTPUT_TE2
8898 * @arg @ref LL_HRTIM_OUTPUT_TF1
8899 * @arg @ref LL_HRTIM_OUTPUT_TF2
8900 * @retval ChopperMode This parameter can be one of the following values:
8901 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8902 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8903 */
LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8904 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8905 {
8906 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8907 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8908 REG_OFFSET_TAB_OUTxR[iOutput]));
8909 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8910 }
8911
8912 /**
8913 * @brief Set the output burst mode entry mode.
8914 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
8915 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
8916 * @note This function must not called when the timer is enabled.
8917 * @param HRTIMx High Resolution Timer instance
8918 * @param Output This parameter can be one of the following values:
8919 * @arg @ref LL_HRTIM_OUTPUT_TA1
8920 * @arg @ref LL_HRTIM_OUTPUT_TA2
8921 * @arg @ref LL_HRTIM_OUTPUT_TB1
8922 * @arg @ref LL_HRTIM_OUTPUT_TB2
8923 * @arg @ref LL_HRTIM_OUTPUT_TC1
8924 * @arg @ref LL_HRTIM_OUTPUT_TC2
8925 * @arg @ref LL_HRTIM_OUTPUT_TD1
8926 * @arg @ref LL_HRTIM_OUTPUT_TD2
8927 * @arg @ref LL_HRTIM_OUTPUT_TE1
8928 * @arg @ref LL_HRTIM_OUTPUT_TE2
8929 * @arg @ref LL_HRTIM_OUTPUT_TF1
8930 * @arg @ref LL_HRTIM_OUTPUT_TF2
8931 * @param BMEntryMode This parameter can be one of the following values:
8932 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8933 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8934 * @retval None
8935 */
LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t BMEntryMode)8936 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
8937 {
8938 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8939 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8940 REG_OFFSET_TAB_OUTxR[iOutput]));
8941 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8942 }
8943
8944 /**
8945 * @brief Get actual output burst mode entry mode.
8946 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
8947 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
8948 * @param HRTIMx High Resolution Timer instance
8949 * @param Output This parameter can be one of the following values:
8950 * @arg @ref LL_HRTIM_OUTPUT_TA1
8951 * @arg @ref LL_HRTIM_OUTPUT_TA2
8952 * @arg @ref LL_HRTIM_OUTPUT_TB1
8953 * @arg @ref LL_HRTIM_OUTPUT_TB2
8954 * @arg @ref LL_HRTIM_OUTPUT_TC1
8955 * @arg @ref LL_HRTIM_OUTPUT_TC2
8956 * @arg @ref LL_HRTIM_OUTPUT_TD1
8957 * @arg @ref LL_HRTIM_OUTPUT_TD2
8958 * @arg @ref LL_HRTIM_OUTPUT_TE1
8959 * @arg @ref LL_HRTIM_OUTPUT_TE2
8960 * @arg @ref LL_HRTIM_OUTPUT_TF1
8961 * @arg @ref LL_HRTIM_OUTPUT_TF2
8962 * @retval BMEntryMode This parameter can be one of the following values:
8963 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8964 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8965 */
LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8966 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8967 {
8968 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8969 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8970 REG_OFFSET_TAB_OUTxR[iOutput]));
8971 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8972 }
8973
8974 /**
8975 * @brief Get the level (active or inactive) of the designated output when the
8976 * delayed protection was triggered.
8977 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
8978 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
8979 * @param HRTIMx High Resolution Timer instance
8980 * @param Output This parameter can be one of the following values:
8981 * @arg @ref LL_HRTIM_OUTPUT_TA1
8982 * @arg @ref LL_HRTIM_OUTPUT_TA2
8983 * @arg @ref LL_HRTIM_OUTPUT_TB1
8984 * @arg @ref LL_HRTIM_OUTPUT_TB2
8985 * @arg @ref LL_HRTIM_OUTPUT_TC1
8986 * @arg @ref LL_HRTIM_OUTPUT_TC2
8987 * @arg @ref LL_HRTIM_OUTPUT_TD1
8988 * @arg @ref LL_HRTIM_OUTPUT_TD2
8989 * @arg @ref LL_HRTIM_OUTPUT_TE1
8990 * @arg @ref LL_HRTIM_OUTPUT_TE2
8991 * @arg @ref LL_HRTIM_OUTPUT_TF1
8992 * @arg @ref LL_HRTIM_OUTPUT_TF2
8993 * @retval OutputLevel This parameter can be one of the following values:
8994 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
8995 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
8996 */
LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef * HRTIMx,uint32_t Output)8997 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8998 {
8999 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9000 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9001 REG_OFFSET_TAB_OUTxR[iOutput]));
9002 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9003 HRTIM_TIMISR_O1STAT_Pos);
9004 }
9005
9006 /**
9007 * @brief Force the timer output to its active or inactive level.
9008 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
9009 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
9010 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
9011 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
9012 * @param HRTIMx High Resolution Timer instance
9013 * @param Output This parameter can be one of the following values:
9014 * @arg @ref LL_HRTIM_OUTPUT_TA1
9015 * @arg @ref LL_HRTIM_OUTPUT_TA2
9016 * @arg @ref LL_HRTIM_OUTPUT_TB1
9017 * @arg @ref LL_HRTIM_OUTPUT_TB2
9018 * @arg @ref LL_HRTIM_OUTPUT_TC1
9019 * @arg @ref LL_HRTIM_OUTPUT_TC2
9020 * @arg @ref LL_HRTIM_OUTPUT_TD1
9021 * @arg @ref LL_HRTIM_OUTPUT_TD2
9022 * @arg @ref LL_HRTIM_OUTPUT_TE1
9023 * @arg @ref LL_HRTIM_OUTPUT_TE2
9024 * @arg @ref LL_HRTIM_OUTPUT_TF1
9025 * @arg @ref LL_HRTIM_OUTPUT_TF2
9026 * @param OutputLevel This parameter can be one of the following values:
9027 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9028 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9029 * @retval None
9030 */
LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t OutputLevel)9031 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
9032 {
9033 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
9034 {
9035 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
9036 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
9037 };
9038
9039 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9040 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
9041 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
9042 SET_BIT(*pReg, HRTIM_SET1R_SST);
9043 }
9044
9045 /**
9046 * @brief Get actual output level, before the output stage (chopper, polarity).
9047 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
9048 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
9049 * @param HRTIMx High Resolution Timer instance
9050 * @param Output This parameter can be one of the following values:
9051 * @arg @ref LL_HRTIM_OUTPUT_TA1
9052 * @arg @ref LL_HRTIM_OUTPUT_TA2
9053 * @arg @ref LL_HRTIM_OUTPUT_TB1
9054 * @arg @ref LL_HRTIM_OUTPUT_TB2
9055 * @arg @ref LL_HRTIM_OUTPUT_TC1
9056 * @arg @ref LL_HRTIM_OUTPUT_TC2
9057 * @arg @ref LL_HRTIM_OUTPUT_TD1
9058 * @arg @ref LL_HRTIM_OUTPUT_TD2
9059 * @arg @ref LL_HRTIM_OUTPUT_TE1
9060 * @arg @ref LL_HRTIM_OUTPUT_TE2
9061 * @arg @ref LL_HRTIM_OUTPUT_TF1
9062 * @arg @ref LL_HRTIM_OUTPUT_TF2
9063 * @retval OutputLevel This parameter can be one of the following values:
9064 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9065 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9066 */
LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output)9067 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
9068 {
9069 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9070 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9071 REG_OFFSET_TAB_OUTxR[iOutput]));
9072 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9073 HRTIM_TIMISR_O1CPY_Pos);
9074 }
9075
9076 /**
9077 * @}
9078 */
9079
9080 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
9081 * @{
9082 */
9083
9084 /**
9085 * @brief Configure external event conditioning.
9086 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
9087 * EECR1 EE1POL LL_HRTIM_EE_Config\n
9088 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
9089 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
9090 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
9091 * EECR1 EE2POL LL_HRTIM_EE_Config\n
9092 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
9093 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
9094 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
9095 * EECR1 EE3POL LL_HRTIM_EE_Config\n
9096 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
9097 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
9098 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
9099 * EECR1 EE4POL LL_HRTIM_EE_Config\n
9100 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
9101 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
9102 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
9103 * EECR1 EE5POL LL_HRTIM_EE_Config\n
9104 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
9105 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
9106 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
9107 * EECR2 EE6POL LL_HRTIM_EE_Config\n
9108 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
9109 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
9110 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
9111 * EECR2 EE7POL LL_HRTIM_EE_Config\n
9112 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
9113 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
9114 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
9115 * EECR2 EE8POL LL_HRTIM_EE_Config\n
9116 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
9117 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
9118 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
9119 * EECR2 EE9POL LL_HRTIM_EE_Config\n
9120 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
9121 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
9122 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
9123 * EECR2 EE10POL LL_HRTIM_EE_Config\n
9124 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
9125 * EECR2 EE10FAST LL_HRTIM_EE_Config
9126 * @note This function must not be called when the timer counter is enabled.
9127 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
9128 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
9129 * @param HRTIMx High Resolution Timer instance
9130 * @param Event This parameter can be one of the following values:
9131 * @arg @ref LL_HRTIM_EVENT_1
9132 * @arg @ref LL_HRTIM_EVENT_2
9133 * @arg @ref LL_HRTIM_EVENT_3
9134 * @arg @ref LL_HRTIM_EVENT_4
9135 * @arg @ref LL_HRTIM_EVENT_5
9136 * @arg @ref LL_HRTIM_EVENT_6
9137 * @arg @ref LL_HRTIM_EVENT_7
9138 * @arg @ref LL_HRTIM_EVENT_8
9139 * @arg @ref LL_HRTIM_EVENT_9
9140 * @arg @ref LL_HRTIM_EVENT_10
9141 * @param Configuration This parameter must be a combination of all the following values:
9142 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
9143 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
9144 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9145 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
9146 * @retval None
9147 */
LL_HRTIM_EE_Config(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Configuration)9148 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
9149 {
9150 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9151 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9152 REG_OFFSET_TAB_EECR[iEvent]));
9153 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
9154 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
9155 }
9156
9157 /**
9158 * @brief Set the external event source.
9159 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
9160 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
9161 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
9162 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
9163 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
9164 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
9165 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
9166 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
9167 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
9168 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
9169 * @param HRTIMx High Resolution Timer instance
9170 * @param Event This parameter can be one of the following values:
9171 * @arg @ref LL_HRTIM_EVENT_1
9172 * @arg @ref LL_HRTIM_EVENT_2
9173 * @arg @ref LL_HRTIM_EVENT_3
9174 * @arg @ref LL_HRTIM_EVENT_4
9175 * @arg @ref LL_HRTIM_EVENT_5
9176 * @arg @ref LL_HRTIM_EVENT_6
9177 * @arg @ref LL_HRTIM_EVENT_7
9178 * @arg @ref LL_HRTIM_EVENT_8
9179 * @arg @ref LL_HRTIM_EVENT_9
9180 * @arg @ref LL_HRTIM_EVENT_10
9181 * @param Src This parameter can be one of the following values:
9182 * @arg External event source 1
9183 * @arg External event source 2
9184 * @arg External event source 3
9185 * @arg External event source 4
9186 * @retval None
9187 */
LL_HRTIM_EE_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Src)9188 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
9189 {
9190 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9191 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9192 REG_OFFSET_TAB_EECR[iEvent]));
9193 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
9194 }
9195
9196 /**
9197 * @brief Get actual external event source.
9198 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
9199 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
9200 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
9201 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
9202 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
9203 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
9204 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
9205 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
9206 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
9207 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
9208 * @param HRTIMx High Resolution Timer instance
9209 * @param Event This parameter can be one of the following values:
9210 * @arg @ref LL_HRTIM_EVENT_1
9211 * @arg @ref LL_HRTIM_EVENT_2
9212 * @arg @ref LL_HRTIM_EVENT_3
9213 * @arg @ref LL_HRTIM_EVENT_4
9214 * @arg @ref LL_HRTIM_EVENT_5
9215 * @arg @ref LL_HRTIM_EVENT_6
9216 * @arg @ref LL_HRTIM_EVENT_7
9217 * @arg @ref LL_HRTIM_EVENT_8
9218 * @arg @ref LL_HRTIM_EVENT_9
9219 * @arg @ref LL_HRTIM_EVENT_10
9220 * @retval EventSrc This parameter can be one of the following values:
9221 * @arg External event source 1
9222 * @arg External event source 2
9223 * @arg External event source 3
9224 * @arg External event source 4
9225 */
LL_HRTIM_EE_GetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event)9226 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9227 {
9228 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9229 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9230 REG_OFFSET_TAB_EECR[iEvent]));
9231 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9232 }
9233
9234 /**
9235 * @brief Set the polarity of an external event.
9236 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
9237 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
9238 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
9239 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
9240 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
9241 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
9242 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
9243 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
9244 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
9245 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
9246 * @note This function must not be called when the timer counter is enabled.
9247 * @note Event polarity is only significant when event detection is level-sensitive.
9248 * @param HRTIMx High Resolution Timer instance
9249 * @param Event This parameter can be one of the following values:
9250 * @arg @ref LL_HRTIM_EVENT_1
9251 * @arg @ref LL_HRTIM_EVENT_2
9252 * @arg @ref LL_HRTIM_EVENT_3
9253 * @arg @ref LL_HRTIM_EVENT_4
9254 * @arg @ref LL_HRTIM_EVENT_5
9255 * @arg @ref LL_HRTIM_EVENT_6
9256 * @arg @ref LL_HRTIM_EVENT_7
9257 * @arg @ref LL_HRTIM_EVENT_8
9258 * @arg @ref LL_HRTIM_EVENT_9
9259 * @arg @ref LL_HRTIM_EVENT_10
9260 * @param Polarity This parameter can be one of the following values:
9261 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9262 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9263 * @retval None
9264 */
LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Polarity)9265 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
9266 {
9267 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9268 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9269 REG_OFFSET_TAB_EECR[iEvent]));
9270 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
9271 }
9272
9273 /**
9274 * @brief Get actual polarity setting of an external event.
9275 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
9276 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
9277 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
9278 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
9279 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
9280 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
9281 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
9282 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
9283 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
9284 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
9285 * @param HRTIMx High Resolution Timer instance
9286 * @param Event This parameter can be one of the following values:
9287 * @arg @ref LL_HRTIM_EVENT_1
9288 * @arg @ref LL_HRTIM_EVENT_2
9289 * @arg @ref LL_HRTIM_EVENT_3
9290 * @arg @ref LL_HRTIM_EVENT_4
9291 * @arg @ref LL_HRTIM_EVENT_5
9292 * @arg @ref LL_HRTIM_EVENT_6
9293 * @arg @ref LL_HRTIM_EVENT_7
9294 * @arg @ref LL_HRTIM_EVENT_8
9295 * @arg @ref LL_HRTIM_EVENT_9
9296 * @arg @ref LL_HRTIM_EVENT_10
9297 * @retval Polarity This parameter can be one of the following values:
9298 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9299 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9300 */
LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event)9301 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9302 {
9303 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9304 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9305 REG_OFFSET_TAB_EECR[iEvent]));
9306 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9307 }
9308
9309 /**
9310 * @brief Set the sensitivity of an external event.
9311 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
9312 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
9313 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
9314 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
9315 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
9316 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
9317 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
9318 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
9319 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
9320 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
9321 * @param HRTIMx High Resolution Timer instance
9322 * @param Event This parameter can be one of the following values:
9323 * @arg @ref LL_HRTIM_EVENT_1
9324 * @arg @ref LL_HRTIM_EVENT_2
9325 * @arg @ref LL_HRTIM_EVENT_3
9326 * @arg @ref LL_HRTIM_EVENT_4
9327 * @arg @ref LL_HRTIM_EVENT_5
9328 * @arg @ref LL_HRTIM_EVENT_6
9329 * @arg @ref LL_HRTIM_EVENT_7
9330 * @arg @ref LL_HRTIM_EVENT_8
9331 * @arg @ref LL_HRTIM_EVENT_9
9332 * @arg @ref LL_HRTIM_EVENT_10
9333 * @param Sensitivity This parameter can be one of the following values:
9334 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9335 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9336 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9337 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9338 * @retval None
9339 */
9340
LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Sensitivity)9341 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
9342 {
9343 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9344 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9345 REG_OFFSET_TAB_EECR[iEvent]));
9346 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
9347 }
9348
9349 /**
9350 * @brief Get actual sensitivity setting of an external event.
9351 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
9352 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
9353 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
9354 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
9355 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
9356 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
9357 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
9358 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
9359 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
9360 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
9361 * @param HRTIMx High Resolution Timer instance
9362 * @param Event This parameter can be one of the following values:
9363 * @arg @ref LL_HRTIM_EVENT_1
9364 * @arg @ref LL_HRTIM_EVENT_2
9365 * @arg @ref LL_HRTIM_EVENT_3
9366 * @arg @ref LL_HRTIM_EVENT_4
9367 * @arg @ref LL_HRTIM_EVENT_5
9368 * @arg @ref LL_HRTIM_EVENT_6
9369 * @arg @ref LL_HRTIM_EVENT_7
9370 * @arg @ref LL_HRTIM_EVENT_8
9371 * @arg @ref LL_HRTIM_EVENT_9
9372 * @arg @ref LL_HRTIM_EVENT_10
9373 * @retval Polarity This parameter can be one of the following values:
9374 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9375 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9376 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9377 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9378 */
LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event)9379 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9380 {
9381 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9382 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9383 REG_OFFSET_TAB_EECR[iEvent]));
9384 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9385 }
9386
9387 /**
9388 * @brief Set the fast mode of an external event.
9389 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
9390 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
9391 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
9392 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
9393 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
9394 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
9395 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
9396 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
9397 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
9398 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
9399 * @note This function must not be called when the timer counter is enabled.
9400 * @param HRTIMx High Resolution Timer instance
9401 * @param Event This parameter can be one of the following values:
9402 * @arg @ref LL_HRTIM_EVENT_1
9403 * @arg @ref LL_HRTIM_EVENT_2
9404 * @arg @ref LL_HRTIM_EVENT_3
9405 * @arg @ref LL_HRTIM_EVENT_4
9406 * @arg @ref LL_HRTIM_EVENT_5
9407 * @param FastMode This parameter can be one of the following values:
9408 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9409 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9410 * @retval None
9411 */
LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t FastMode)9412 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
9413 {
9414 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9415 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9416 REG_OFFSET_TAB_EECR[iEvent]));
9417 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
9418 }
9419
9420 /**
9421 * @brief Get actual fast mode setting of an external event.
9422 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
9423 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
9424 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
9425 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
9426 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
9427 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
9428 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
9429 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
9430 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
9431 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
9432 * @param HRTIMx High Resolution Timer instance
9433 * @param Event This parameter can be one of the following values:
9434 * @arg @ref LL_HRTIM_EVENT_1
9435 * @arg @ref LL_HRTIM_EVENT_2
9436 * @arg @ref LL_HRTIM_EVENT_3
9437 * @arg @ref LL_HRTIM_EVENT_4
9438 * @arg @ref LL_HRTIM_EVENT_5
9439 * @retval FastMode This parameter can be one of the following values:
9440 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9441 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9442 */
LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event)9443 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9444 {
9445 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9446 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9447 REG_OFFSET_TAB_EECR[iEvent]));
9448 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9449 }
9450
9451 /**
9452 * @brief Set the digital noise filter of a external event.
9453 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
9454 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
9455 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
9456 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
9457 * EECR3 EE10F LL_HRTIM_EE_SetFilter
9458 * @param HRTIMx High Resolution Timer instance
9459 * @param Event This parameter can be one of the following values:
9460 * @arg @ref LL_HRTIM_EVENT_6
9461 * @arg @ref LL_HRTIM_EVENT_7
9462 * @arg @ref LL_HRTIM_EVENT_8
9463 * @arg @ref LL_HRTIM_EVENT_9
9464 * @arg @ref LL_HRTIM_EVENT_10
9465 * @param Filter This parameter can be one of the following values:
9466 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9467 * @arg @ref LL_HRTIM_EE_FILTER_1
9468 * @arg @ref LL_HRTIM_EE_FILTER_2
9469 * @arg @ref LL_HRTIM_EE_FILTER_3
9470 * @arg @ref LL_HRTIM_EE_FILTER_4
9471 * @arg @ref LL_HRTIM_EE_FILTER_5
9472 * @arg @ref LL_HRTIM_EE_FILTER_6
9473 * @arg @ref LL_HRTIM_EE_FILTER_7
9474 * @arg @ref LL_HRTIM_EE_FILTER_8
9475 * @arg @ref LL_HRTIM_EE_FILTER_9
9476 * @arg @ref LL_HRTIM_EE_FILTER_10
9477 * @arg @ref LL_HRTIM_EE_FILTER_11
9478 * @arg @ref LL_HRTIM_EE_FILTER_12
9479 * @arg @ref LL_HRTIM_EE_FILTER_13
9480 * @arg @ref LL_HRTIM_EE_FILTER_14
9481 * @arg @ref LL_HRTIM_EE_FILTER_15
9482 * @retval None
9483 */
LL_HRTIM_EE_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Filter)9484 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
9485 {
9486 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9487 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
9488 (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
9489 }
9490
9491 /**
9492 * @brief Get actual digital noise filter setting of a external event.
9493 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
9494 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
9495 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
9496 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
9497 * EECR3 EE10F LL_HRTIM_EE_GetFilter
9498 * @param HRTIMx High Resolution Timer instance
9499 * @param Event This parameter can be one of the following values:
9500 * @arg @ref LL_HRTIM_EVENT_6
9501 * @arg @ref LL_HRTIM_EVENT_7
9502 * @arg @ref LL_HRTIM_EVENT_8
9503 * @arg @ref LL_HRTIM_EVENT_9
9504 * @arg @ref LL_HRTIM_EVENT_10
9505 * @retval Filter This parameter can be one of the following values:
9506 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9507 * @arg @ref LL_HRTIM_EE_FILTER_1
9508 * @arg @ref LL_HRTIM_EE_FILTER_2
9509 * @arg @ref LL_HRTIM_EE_FILTER_3
9510 * @arg @ref LL_HRTIM_EE_FILTER_4
9511 * @arg @ref LL_HRTIM_EE_FILTER_5
9512 * @arg @ref LL_HRTIM_EE_FILTER_6
9513 * @arg @ref LL_HRTIM_EE_FILTER_7
9514 * @arg @ref LL_HRTIM_EE_FILTER_8
9515 * @arg @ref LL_HRTIM_EE_FILTER_9
9516 * @arg @ref LL_HRTIM_EE_FILTER_10
9517 * @arg @ref LL_HRTIM_EE_FILTER_11
9518 * @arg @ref LL_HRTIM_EE_FILTER_12
9519 * @arg @ref LL_HRTIM_EE_FILTER_13
9520 * @arg @ref LL_HRTIM_EE_FILTER_14
9521 * @arg @ref LL_HRTIM_EE_FILTER_15
9522 */
LL_HRTIM_EE_GetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event)9523 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9524 {
9525 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
9526 return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
9527 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9528 }
9529
9530 /**
9531 * @brief Set the external event prescaler.
9532 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
9533 * @param HRTIMx High Resolution Timer instance
9534 * @param Prescaler This parameter can be one of the following values:
9535 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9536 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9537 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9538 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9539 * @retval None
9540 */
9541
LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9542 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9543 {
9544 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
9545 }
9546
9547 /**
9548 * @brief Get actual external event prescaler setting.
9549 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
9550 * @param HRTIMx High Resolution Timer instance
9551 * @retval Prescaler This parameter can be one of the following values:
9552 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9553 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9554 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9555 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9556 */
9557
LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef * HRTIMx)9558 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
9559 {
9560 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
9561 }
9562
9563 /**
9564 * @}
9565 */
9566
9567 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
9568 * @{
9569 */
9570 /**
9571 * @brief Configure fault signal conditioning Polarity and Source.
9572 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
9573 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
9574 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
9575 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
9576 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
9577 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
9578 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
9579 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
9580 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
9581 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config\n
9582 * FLTINR2 FLT6P LL_HRTIM_FLT_Config\n
9583 * FLTINR2 FLT6SRC LL_HRTIM_FLT_Config
9584 * @note This function must not be called when the fault channel is enabled.
9585 * @param HRTIMx High Resolution Timer instance
9586 * @param Fault This parameter can be one of the following values:
9587 * @arg @ref LL_HRTIM_FAULT_1
9588 * @arg @ref LL_HRTIM_FAULT_2
9589 * @arg @ref LL_HRTIM_FAULT_3
9590 * @arg @ref LL_HRTIM_FAULT_4
9591 * @arg @ref LL_HRTIM_FAULT_5
9592 * @arg @ref LL_HRTIM_FAULT_6
9593 * @param Configuration This parameter must be a combination of all the following values:
9594 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
9595 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
9596 * @retval None
9597 */
LL_HRTIM_FLT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Configuration)9598 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
9599 {
9600 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9601 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9602 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9603
9604 uint64_t cfg;
9605 uint64_t mask;
9606
9607 cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9608 (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9609
9610 mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9611 ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U); /* this for SouRCe bit 1 */
9612
9613 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9614 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9615
9616 }
9617
9618 /**
9619 * @brief Set the source of a fault signal.
9620 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
9621 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
9622 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
9623 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
9624 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc\n
9625 * FLTINR2 FLT6SRC LL_HRTIM_FLT_SetSrc
9626 * @note This function must not be called when the fault channel is enabled.
9627 * @param HRTIMx High Resolution Timer instance
9628 * @param Fault This parameter can be one of the following values:
9629 * @arg @ref LL_HRTIM_FAULT_1
9630 * @arg @ref LL_HRTIM_FAULT_2
9631 * @arg @ref LL_HRTIM_FAULT_3
9632 * @arg @ref LL_HRTIM_FAULT_4
9633 * @arg @ref LL_HRTIM_FAULT_5
9634 * @arg @ref LL_HRTIM_FAULT_6
9635 * @param Src This parameter can be one of the following values:
9636 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9637 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9638 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9639 * @retval None
9640 */
LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Src)9641 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
9642 {
9643 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9644 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9645 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9646
9647 uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */
9648 (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9649 uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
9650 (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
9651
9652 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9653 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9654 }
9655
9656 /**
9657 * @brief Get actual source of a fault signal.
9658 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
9659 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
9660 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
9661 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
9662 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc\n
9663 * FLTINR2 FLT6SRC LL_HRTIM_FLT_GetSrc
9664 * @param HRTIMx High Resolution Timer instance
9665 * @param Fault This parameter can be one of the following values:
9666 * @arg @ref LL_HRTIM_FAULT_1
9667 * @arg @ref LL_HRTIM_FAULT_2
9668 * @arg @ref LL_HRTIM_FAULT_3
9669 * @arg @ref LL_HRTIM_FAULT_4
9670 * @arg @ref LL_HRTIM_FAULT_5
9671 * @arg @ref LL_HRTIM_FAULT_6
9672 * @retval Source This parameter can be one of the following values:
9673 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9674 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9675 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9676 */
LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9677 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9678 {
9679 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9680 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9681 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9682
9683 uint64_t Src0;
9684 uint32_t Src1;
9685 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9686
9687 /* this for SouRCe bit 1 */
9688 Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
9689 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
9690 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
9691
9692 /* this for SouRCe bit 0 */
9693 Src0 = (uint64_t)temp1 << 32U;
9694 Src0 |= (uint64_t)temp2;
9695 Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9696
9697 return ((uint32_t)(Src0 | Src1));
9698 }
9699
9700 /**
9701 * @brief Set the polarity of a fault signal.
9702 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
9703 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
9704 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
9705 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
9706 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity\n
9707 * FLTINR2 FLT6P LL_HRTIM_FLT_SetPolarity
9708 * @note This function must not be called when the fault channel is enabled.
9709 * @param HRTIMx High Resolution Timer instance
9710 * @param Fault This parameter can be one of the following values:
9711 * @arg @ref LL_HRTIM_FAULT_1
9712 * @arg @ref LL_HRTIM_FAULT_2
9713 * @arg @ref LL_HRTIM_FAULT_3
9714 * @arg @ref LL_HRTIM_FAULT_4
9715 * @arg @ref LL_HRTIM_FAULT_5
9716 * @arg @ref LL_HRTIM_FAULT_6
9717 * @param Polarity This parameter can be one of the following values:
9718 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9719 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9720 * @retval None
9721 */
LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Polarity)9722 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
9723 {
9724 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9725 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9726 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9727
9728 uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9729 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9730
9731 /* for Polarity bit */
9732 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9733 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9734 }
9735
9736 /**
9737 * @brief Get actual polarity of a fault signal.
9738 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
9739 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
9740 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
9741 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
9742 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity\n
9743 * FLTINR2 FLT6P LL_HRTIM_FLT_GetPolarity
9744 * @param HRTIMx High Resolution Timer instance
9745 * @param Fault This parameter can be one of the following values:
9746 * @arg @ref LL_HRTIM_FAULT_1
9747 * @arg @ref LL_HRTIM_FAULT_2
9748 * @arg @ref LL_HRTIM_FAULT_3
9749 * @arg @ref LL_HRTIM_FAULT_4
9750 * @arg @ref LL_HRTIM_FAULT_5
9751 * @arg @ref LL_HRTIM_FAULT_6
9752 * @retval Polarity This parameter can be one of the following values:
9753 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9754 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9755 */
LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9756 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9757 {
9758 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9759 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9760 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9761 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9762 uint64_t cfg;
9763
9764 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
9765 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
9766
9767 cfg = (uint64_t)temp1 << 32 ;
9768 cfg |= (uint64_t)temp2;
9769 cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9770
9771 return (uint32_t)(cfg);
9772
9773 }
9774
9775 /**
9776 * @brief Set the digital noise filter of a fault signal.
9777 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
9778 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
9779 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
9780 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
9781 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter\n
9782 * FLTINR2 FLT6F LL_HRTIM_FLT_SetFilter
9783 * @note This function must not be called when the fault channel is enabled.
9784 * @param HRTIMx High Resolution Timer instance
9785 * @param Fault This parameter can be one of the following values:
9786 * @arg @ref LL_HRTIM_FAULT_1
9787 * @arg @ref LL_HRTIM_FAULT_2
9788 * @arg @ref LL_HRTIM_FAULT_3
9789 * @arg @ref LL_HRTIM_FAULT_4
9790 * @arg @ref LL_HRTIM_FAULT_5
9791 * @arg @ref LL_HRTIM_FAULT_6
9792 * @param Filter This parameter can be one of the following values:
9793 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9794 * @arg @ref LL_HRTIM_FLT_FILTER_1
9795 * @arg @ref LL_HRTIM_FLT_FILTER_2
9796 * @arg @ref LL_HRTIM_FLT_FILTER_3
9797 * @arg @ref LL_HRTIM_FLT_FILTER_4
9798 * @arg @ref LL_HRTIM_FLT_FILTER_5
9799 * @arg @ref LL_HRTIM_FLT_FILTER_6
9800 * @arg @ref LL_HRTIM_FLT_FILTER_7
9801 * @arg @ref LL_HRTIM_FLT_FILTER_8
9802 * @arg @ref LL_HRTIM_FLT_FILTER_9
9803 * @arg @ref LL_HRTIM_FLT_FILTER_10
9804 * @arg @ref LL_HRTIM_FLT_FILTER_11
9805 * @arg @ref LL_HRTIM_FLT_FILTER_12
9806 * @arg @ref LL_HRTIM_FLT_FILTER_13
9807 * @arg @ref LL_HRTIM_FLT_FILTER_14
9808 * @arg @ref LL_HRTIM_FLT_FILTER_15
9809 * @retval None
9810 */
LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Filter)9811 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
9812 {
9813 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9814 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9815 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9816
9817 uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */
9818 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9819
9820 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
9821 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt >> 32U));
9822 }
9823
9824 /**
9825 * @brief Get actual digital noise filter setting of a fault signal.
9826 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
9827 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
9828 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
9829 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
9830 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter\n
9831 * FLTINR2 FLT6F LL_HRTIM_FLT_GetFilter
9832 * @param HRTIMx High Resolution Timer instance
9833 * @param Fault This parameter can be one of the following values:
9834 * @arg @ref LL_HRTIM_FAULT_1
9835 * @arg @ref LL_HRTIM_FAULT_2
9836 * @arg @ref LL_HRTIM_FAULT_3
9837 * @arg @ref LL_HRTIM_FAULT_4
9838 * @arg @ref LL_HRTIM_FAULT_5
9839 * @arg @ref LL_HRTIM_FAULT_6
9840 * @retval Filter This parameter can be one of the following values:
9841 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9842 * @arg @ref LL_HRTIM_FLT_FILTER_1
9843 * @arg @ref LL_HRTIM_FLT_FILTER_2
9844 * @arg @ref LL_HRTIM_FLT_FILTER_3
9845 * @arg @ref LL_HRTIM_FLT_FILTER_4
9846 * @arg @ref LL_HRTIM_FLT_FILTER_5
9847 * @arg @ref LL_HRTIM_FLT_FILTER_6
9848 * @arg @ref LL_HRTIM_FLT_FILTER_7
9849 * @arg @ref LL_HRTIM_FLT_FILTER_8
9850 * @arg @ref LL_HRTIM_FLT_FILTER_9
9851 * @arg @ref LL_HRTIM_FLT_FILTER_10
9852 * @arg @ref LL_HRTIM_FLT_FILTER_11
9853 * @arg @ref LL_HRTIM_FLT_FILTER_12
9854 * @arg @ref LL_HRTIM_FLT_FILTER_13
9855 * @arg @ref LL_HRTIM_FLT_FILTER_14
9856 * @arg @ref LL_HRTIM_FLT_FILTER_15
9857 */
LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9858 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9859 {
9860 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9861 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9862 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9863 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9864 uint64_t flt;
9865 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
9866 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
9867
9868 flt = (uint64_t)temp1 << 32U;
9869 flt |= (uint64_t)temp2;
9870 flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9871
9872 return (uint32_t)(flt);
9873
9874 }
9875
9876 /**
9877 * @brief Set the fault circuitry prescaler.
9878 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
9879 * @param HRTIMx High Resolution Timer instance
9880 * @param Prescaler This parameter can be one of the following values:
9881 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9882 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9883 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9884 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9885 * @retval None
9886 */
LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9887 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9888 {
9889 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
9890 }
9891
9892 /**
9893 * @brief Get actual fault circuitry prescaler setting.
9894 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
9895 * @param HRTIMx High Resolution Timer instance
9896 * @retval Prescaler This parameter can be one of the following values:
9897 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9898 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9899 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9900 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9901 */
LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef * HRTIMx)9902 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
9903 {
9904 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
9905 }
9906
9907 /**
9908 * @brief Lock the fault signal conditioning settings.
9909 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
9910 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
9911 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
9912 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
9913 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock\n
9914 * FLTINR2 FLT6LCK LL_HRTIM_FLT_Lock
9915 * @param HRTIMx High Resolution Timer instance
9916 * @param Fault This parameter can be one of the following values:
9917 * @arg @ref LL_HRTIM_FAULT_1
9918 * @arg @ref LL_HRTIM_FAULT_2
9919 * @arg @ref LL_HRTIM_FAULT_3
9920 * @arg @ref LL_HRTIM_FAULT_4
9921 * @arg @ref LL_HRTIM_FAULT_5
9922 * @arg @ref LL_HRTIM_FAULT_6
9923 * @retval None
9924 */
LL_HRTIM_FLT_Lock(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9925 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9926 {
9927 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9929 REG_OFFSET_TAB_FLTINR[iFault]));
9930 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
9931 }
9932
9933 /**
9934 * @brief Enable the fault circuitry for the designated fault input.
9935 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
9936 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
9937 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
9938 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
9939 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable\n
9940 * FLTINR2 FLT6E LL_HRTIM_FLT_Enable
9941 * @param HRTIMx High Resolution Timer instance
9942 * @param Fault This parameter can be one of the following values:
9943 * @arg @ref LL_HRTIM_FAULT_1
9944 * @arg @ref LL_HRTIM_FAULT_2
9945 * @arg @ref LL_HRTIM_FAULT_3
9946 * @arg @ref LL_HRTIM_FAULT_4
9947 * @arg @ref LL_HRTIM_FAULT_5
9948 * @arg @ref LL_HRTIM_FAULT_6
9949 * @retval None
9950 */
LL_HRTIM_FLT_Enable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9951 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9952 {
9953 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9954 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9955 REG_OFFSET_TAB_FLTINR[iFault]));
9956 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9957 }
9958
9959 /**
9960 * @brief Disable the fault circuitry for for the designated fault input.
9961 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
9962 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
9963 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
9964 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
9965 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable\n
9966 * FLTINR2 FLT6E LL_HRTIM_FLT_Disable
9967 * @param HRTIMx High Resolution Timer instance
9968 * @param Fault This parameter can be one of the following values:
9969 * @arg @ref LL_HRTIM_FAULT_1
9970 * @arg @ref LL_HRTIM_FAULT_2
9971 * @arg @ref LL_HRTIM_FAULT_3
9972 * @arg @ref LL_HRTIM_FAULT_4
9973 * @arg @ref LL_HRTIM_FAULT_5
9974 * @arg @ref LL_HRTIM_FAULT_6
9975 * @retval None
9976 */
LL_HRTIM_FLT_Disable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9977 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9978 {
9979 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9980 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9981 REG_OFFSET_TAB_FLTINR[iFault]));
9982 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9983
9984 }
9985
9986 /**
9987 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
9988 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
9989 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
9990 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
9991 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
9992 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled\n
9993 * FLTINR2 FLT6E LL_HRTIM_FLT_IsEnabled
9994 * @param HRTIMx High Resolution Timer instance
9995 * @param Fault This parameter can be one of the following values:
9996 * @arg @ref LL_HRTIM_FAULT_1
9997 * @arg @ref LL_HRTIM_FAULT_2
9998 * @arg @ref LL_HRTIM_FAULT_3
9999 * @arg @ref LL_HRTIM_FAULT_4
10000 * @arg @ref LL_HRTIM_FAULT_5
10001 * @arg @ref LL_HRTIM_FAULT_6
10002 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
10003 */
LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10004 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10005 {
10006 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10007 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10008 REG_OFFSET_TAB_FLTINR[iFault]));
10009 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
10010 (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
10011 }
10012
10013 /**
10014 * @brief Enable the Blanking of the fault circuitry for the designated fault input.
10015 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_EnableBlanking\n
10016 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_EnableBlanking\n
10017 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_EnableBlanking\n
10018 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_EnableBlanking\n
10019 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_EnableBlanking\n
10020 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_EnableBlanking
10021 * @param HRTIMx High Resolution Timer instance
10022 * @param Fault This parameter can be one of the following values:
10023 * @arg @ref LL_HRTIM_FAULT_1
10024 * @arg @ref LL_HRTIM_FAULT_2
10025 * @arg @ref LL_HRTIM_FAULT_3
10026 * @arg @ref LL_HRTIM_FAULT_4
10027 * @arg @ref LL_HRTIM_FAULT_5
10028 * @arg @ref LL_HRTIM_FAULT_6
10029 * @retval None
10030 */
LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10031 __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10032 {
10033 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10034 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10035 REG_OFFSET_TAB_FLTINR[iFault]));
10036 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
10037 }
10038
10039 /**
10040 * @brief Disable the Blanking of the fault circuitry for the designated fault input.
10041 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_DisableBlanking\n
10042 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_DisableBlanking\n
10043 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_DisableBlanking\n
10044 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_DisableBlanking\n
10045 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_DisableBlanking\n
10046 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_DisableBlanking
10047 * @param HRTIMx High Resolution Timer instance
10048 * @param Fault This parameter can be one of the following values:
10049 * @arg @ref LL_HRTIM_FAULT_1
10050 * @arg @ref LL_HRTIM_FAULT_2
10051 * @arg @ref LL_HRTIM_FAULT_3
10052 * @arg @ref LL_HRTIM_FAULT_4
10053 * @arg @ref LL_HRTIM_FAULT_5
10054 * @arg @ref LL_HRTIM_FAULT_6
10055 * @retval None
10056 */
LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10057 __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10058 {
10059 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10060 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10061 REG_OFFSET_TAB_FLTINR[iFault]));
10062 CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
10063 }
10064
10065 /**
10066 * @brief Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
10067 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10068 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10069 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10070 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10071 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10072 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_IsEnabledBlanking
10073 * @param HRTIMx High Resolution Timer instance
10074 * @param Fault This parameter can be one of the following values:
10075 * @arg @ref LL_HRTIM_FAULT_1
10076 * @arg @ref LL_HRTIM_FAULT_2
10077 * @arg @ref LL_HRTIM_FAULT_3
10078 * @arg @ref LL_HRTIM_FAULT_4
10079 * @arg @ref LL_HRTIM_FAULT_5
10080 * @arg @ref LL_HRTIM_FAULT_6
10081 * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
10082 */
LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10083 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10084 {
10085 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10086 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10087 REG_OFFSET_TAB_FLTINR[iFault]));
10088 uint32_t temp; /* MISRAC-2012 compliance */
10089 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
10090
10091 return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
10092 }
10093
10094 /**
10095 * @brief Set the Blanking Source of the fault circuitry for a given fault input.
10096 * @note Fault inputs can be temporary disabled to blank spurious fault events.
10097 * @note This function allows for selection amongst 2 possible blanking sources.
10098 * @note Events triggering blanking window start and blanking window end depend
10099 * on both the selected blanking source and the fault input.
10100 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10101 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10102 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10103 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10104 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10105 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_SetBlankingSrc
10106 * @param HRTIMx High Resolution Timer instance
10107 * @param Fault This parameter can be one of the following values:
10108 * @arg @ref LL_HRTIM_FAULT_1
10109 * @arg @ref LL_HRTIM_FAULT_2
10110 * @arg @ref LL_HRTIM_FAULT_3
10111 * @arg @ref LL_HRTIM_FAULT_4
10112 * @arg @ref LL_HRTIM_FAULT_5
10113 * @arg @ref LL_HRTIM_FAULT_6
10114 * @param Source parameter can be one of the following values:
10115 * @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
10116 * @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
10117 * @retval None
10118 */
LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Source)10119 __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
10120 {
10121 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10122 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10123 REG_OFFSET_TAB_FLTINR[iFault]));
10124 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
10125
10126 }
10127
10128 /**
10129 * @brief Get the Blanking Source of the fault circuitry is enabled for a given fault input.
10130 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10131 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10132 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10133 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10134 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10135 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_GetBlankingSrc
10136 * @param HRTIMx High Resolution Timer instance
10137 * @param Fault This parameter can be one of the following values:
10138 * @arg @ref LL_HRTIM_FAULT_1
10139 * @arg @ref LL_HRTIM_FAULT_2
10140 * @arg @ref LL_HRTIM_FAULT_3
10141 * @arg @ref LL_HRTIM_FAULT_4
10142 * @arg @ref LL_HRTIM_FAULT_5
10143 * @arg @ref LL_HRTIM_FAULT_6
10144 */
LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10145 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10146 {
10147 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10148 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10149 REG_OFFSET_TAB_FLTINR[iFault]));
10150 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
10151 }
10152
10153 /**
10154 * @brief Set the Counter threshold value of a fault counter.
10155 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_SetCounterThreshold\n
10156 * FLTINR3 FLT2CNT LL_HRTIM_FLT_SetCounterThreshold\n
10157 * FLTINR3 FLT3CNT LL_HRTIM_FLT_SetCounterThreshold\n
10158 * FLTINR3 FLT4CNT LL_HRTIM_FLT_SetCounterThreshold\n
10159 * FLTINR4 FLT5CNT LL_HRTIM_FLT_SetCounterThreshold\n
10160 * FLTINR4 FLT6CNT LL_HRTIM_FLT_SetCounterThreshold
10161 * @note This function must not be called when the fault channel is enabled.
10162 * @param HRTIMx High Resolution Timer instance
10163 * @param Fault This parameter can be one of the following values:
10164 * @arg @ref LL_HRTIM_FAULT_1
10165 * @arg @ref LL_HRTIM_FAULT_2
10166 * @arg @ref LL_HRTIM_FAULT_3
10167 * @arg @ref LL_HRTIM_FAULT_4
10168 * @arg @ref LL_HRTIM_FAULT_5
10169 * @arg @ref LL_HRTIM_FAULT_6
10170 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10171 * @retval None
10172 */
LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Threshold)10173 __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
10174 {
10175 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10176 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10177 REG_OFFSET_TAB_FLTINR[iFault]));
10178 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault]));
10179 }
10180
10181 /**
10182 * @brief Get actual the Counter threshold value of a fault counter.
10183 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_GetCounterThreshold\n
10184 * FLTINR3 FLT2CNT LL_HRTIM_FLT_GetCounterThreshold\n
10185 * FLTINR3 FLT3CNT LL_HRTIM_FLT_GetCounterThreshold\n
10186 * FLTINR3 FLT4CNT LL_HRTIM_FLT_GetCounterThreshold\n
10187 * FLTINR4 FLT5CNT LL_HRTIM_FLT_GetCounterThreshold\n
10188 * FLTINR4 FLT6CNT LL_HRTIM_FLT_GetCounterThreshold
10189 * @param HRTIMx High Resolution Timer instance
10190 * @param Fault This parameter can be one of the following values:
10191 * @arg @ref LL_HRTIM_FAULT_1
10192 * @arg @ref LL_HRTIM_FAULT_2
10193 * @arg @ref LL_HRTIM_FAULT_3
10194 * @arg @ref LL_HRTIM_FAULT_4
10195 * @arg @ref LL_HRTIM_FAULT_5
10196 * @arg @ref LL_HRTIM_FAULT_6
10197 * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10198 */
LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10199 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10200 {
10201 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10202 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10203 REG_OFFSET_TAB_FLTINR[iFault]));
10204 return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
10205 }
10206
10207 /**
10208 * @brief Set the mode of reset of a fault counter to 'always reset'.
10209 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_SetResetMode\n
10210 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_SetResetMode\n
10211 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_SetResetMode\n
10212 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_SetResetMode\n
10213 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_SetResetMode\n
10214 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_SetResetMode
10215 * @param HRTIMx High Resolution Timer instance
10216 * @param Fault This parameter can be one of the following values:
10217 * @arg @ref LL_HRTIM_FAULT_1
10218 * @arg @ref LL_HRTIM_FAULT_2
10219 * @arg @ref LL_HRTIM_FAULT_3
10220 * @arg @ref LL_HRTIM_FAULT_4
10221 * @arg @ref LL_HRTIM_FAULT_5
10222 * @arg @ref LL_HRTIM_FAULT_6
10223 * @param Mode This parameter can be one of the following values:
10224 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10225 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10226 * @retval None
10227 */
LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Mode)10228 __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
10229 {
10230 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10231 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10232 REG_OFFSET_TAB_FLTINR[iFault]));
10233 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
10234
10235 }
10236
10237 /**
10238 * @brief Get the mode of reset of a fault counter to 'reset on event'.
10239 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_GetResetMode\n
10240 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_GetResetMode\n
10241 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_GetResetMode\n
10242 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_GetResetMode\n
10243 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_GetResetMode\n
10244 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_GetResetMode
10245 * @param HRTIMx High Resolution Timer instance
10246 * @param Fault This parameter can be one of the following values:
10247 * @arg @ref LL_HRTIM_FAULT_1
10248 * @arg @ref LL_HRTIM_FAULT_2
10249 * @arg @ref LL_HRTIM_FAULT_3
10250 * @arg @ref LL_HRTIM_FAULT_4
10251 * @arg @ref LL_HRTIM_FAULT_5
10252 * @arg @ref LL_HRTIM_FAULT_6
10253 * @retval Mode This parameter can be one of the following values:
10254 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10255 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10256 */
LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10257 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10258 {
10259 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10260 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10261 REG_OFFSET_TAB_FLTINR[iFault]));
10262 return READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]);
10263 }
10264
10265 /**
10266 * @brief Reset the fault counter for a fault circuitry
10267 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_ResetCounter\n
10268 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_ResetCounter\n
10269 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_ResetCounter\n
10270 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_ResetCounter\n
10271 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_ResetCounter\n
10272 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_ResetCounter
10273 * @param HRTIMx High Resolution Timer instance
10274 * @param Fault This parameter can be one of the following values:
10275 * @arg @ref LL_HRTIM_FAULT_1
10276 * @arg @ref LL_HRTIM_FAULT_2
10277 * @arg @ref LL_HRTIM_FAULT_3
10278 * @arg @ref LL_HRTIM_FAULT_4
10279 * @arg @ref LL_HRTIM_FAULT_5
10280 * @arg @ref LL_HRTIM_FAULT_6
10281 * @retval None
10282 */
LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10283 __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10284 {
10285 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10286 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10287 REG_OFFSET_TAB_FLTINR[iFault]));
10288 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
10289
10290 }
10291
10292 /**
10293 * @}
10294 */
10295
10296 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
10297 * @{
10298 */
10299
10300 /**
10301 * @brief Configure the burst mode controller.
10302 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
10303 * BMCR BMCLK LL_HRTIM_BM_Config\n
10304 * BMCR BMPRSC LL_HRTIM_BM_Config
10305 * @param HRTIMx High Resolution Timer instance
10306 * @param Configuration This parameter must be a combination of all the following values:
10307 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
10308 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10309 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
10310 * @retval None
10311 */
LL_HRTIM_BM_Config(HRTIM_TypeDef * HRTIMx,uint32_t Configuration)10312 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
10313 {
10314 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
10315 }
10316
10317 /**
10318 * @brief Set the burst mode controller operating mode.
10319 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
10320 * @param HRTIMx High Resolution Timer instance
10321 * @param Mode This parameter can be one of the following values:
10322 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10323 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10324 * @retval None
10325 */
LL_HRTIM_BM_SetMode(HRTIM_TypeDef * HRTIMx,uint32_t Mode)10326 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
10327 {
10328 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
10329 }
10330
10331 /**
10332 * @brief Get actual burst mode controller operating mode.
10333 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
10334 * @param HRTIMx High Resolution Timer instance
10335 * @retval Mode This parameter can be one of the following values:
10336 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10337 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10338 */
LL_HRTIM_BM_GetMode(HRTIM_TypeDef * HRTIMx)10339 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
10340 {
10341 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
10342 }
10343
10344 /**
10345 * @brief Set the burst mode controller clock source.
10346 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
10347 * @param HRTIMx High Resolution Timer instance
10348 * @param ClockSrc This parameter can be one of the following values:
10349 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10350 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10351 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10352 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10353 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10354 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10355 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10356 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10357 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10358 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10359 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10360 * @retval None
10361 */
LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef * HRTIMx,uint32_t ClockSrc)10362 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
10363 {
10364 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
10365 }
10366
10367 /**
10368 * @brief Get actual burst mode controller clock source.
10369 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
10370 * @param HRTIMx High Resolution Timer instance
10371 * @retval ClockSrc This parameter can be one of the following values:
10372 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10373 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10374 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10375 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10376 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10377 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10378 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10379 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10380 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10381 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10382 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10383 * @retval ClockSrc This parameter can be one of the following values:
10384 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10385 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10386 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10387 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10388 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10389 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10390 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10391 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10392 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10393 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10394 */
LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef * HRTIMx)10395 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
10396 {
10397 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
10398 }
10399
10400 /**
10401 * @brief Set the burst mode controller prescaler.
10402 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
10403 * @param HRTIMx High Resolution Timer instance
10404 * @param Prescaler This parameter can be one of the following values:
10405 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10406 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10407 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10408 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10409 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10410 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10411 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10412 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10413 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10414 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10415 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10416 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10417 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10418 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10419 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10420 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10421 * @retval None
10422 */
LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)10423 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
10424 {
10425 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
10426 }
10427
10428 /**
10429 * @brief Get actual burst mode controller prescaler setting.
10430 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
10431 * @param HRTIMx High Resolution Timer instance
10432 * @retval Prescaler This parameter can be one of the following values:
10433 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10434 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10435 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10436 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10437 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10438 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10439 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10440 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10441 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10442 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10443 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10444 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10445 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10446 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10447 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10448 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10449 */
LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef * HRTIMx)10450 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
10451 {
10452 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
10453 }
10454
10455 /**
10456 * @brief Enable burst mode compare and period registers preload.
10457 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
10458 * @param HRTIMx High Resolution Timer instance
10459 * @retval None
10460 */
LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef * HRTIMx)10461 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
10462 {
10463 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10464 }
10465
10466 /**
10467 * @brief Disable burst mode compare and period registers preload.
10468 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
10469 * @param HRTIMx High Resolution Timer instance
10470 * @retval None
10471 */
LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef * HRTIMx)10472 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
10473 {
10474 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10475 }
10476
10477 /**
10478 * @brief Indicate whether burst mode compare and period registers are preloaded.
10479 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
10480 * @param HRTIMx High Resolution Timer instance
10481 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
10482 */
LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef * HRTIMx)10483 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
10484 {
10485 uint32_t temp; /* MISRAC-2012 compliance */
10486 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10487
10488 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
10489 }
10490
10491 /**
10492 * @brief Set the burst mode controller trigger
10493 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
10494 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
10495 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
10496 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
10497 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
10498 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
10499 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
10500 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
10501 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
10502 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
10503 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
10504 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
10505 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
10506 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
10507 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
10508 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
10509 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
10510 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
10511 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
10512 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
10513 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
10514 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
10515 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
10516 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
10517 * BMTRGR TFREP LL_HRTIM_BM_SetTrig\n
10518 * BMTRGR TFRST LL_HRTIM_BM_SetTrig\n
10519 * BMTRGR TFCMP1 LL_HRTIM_BM_SetTrig\n
10520 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
10521 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
10522 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
10523 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
10524 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
10525 * @param HRTIMx High Resolution Timer instance
10526 * @param Trig This parameter can be a combination of the following values:
10527 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10528 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10529 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10530 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10531 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10532 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10533 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10534 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10535 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10536 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10537 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10538 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10539 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10540 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10541 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10542 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10543 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10544 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10545 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10546 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10547 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10548 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10549 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10550 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10551 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10552 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10553 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10554 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10555 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10556 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10557 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10558 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10559 * @retval None
10560 */
LL_HRTIM_BM_SetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Trig)10561 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
10562 {
10563 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
10564 }
10565
10566 /**
10567 * @brief Get actual burst mode controller trigger.
10568 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
10569 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
10570 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
10571 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
10572 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
10573 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
10574 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
10575 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
10576 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
10577 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
10578 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
10579 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
10580 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
10581 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
10582 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
10583 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
10584 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
10585 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
10586 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
10587 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
10588 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
10589 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
10590 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
10591 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
10592 * BMTRGR TFREP LL_HRTIM_BM_GetTrig\n
10593 * BMTRGR TFRST LL_HRTIM_BM_GetTrig\n
10594 * BMTRGR TFCMP1 LL_HRTIM_BM_GetTrig\n
10595 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
10596 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
10597 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
10598 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
10599 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
10600 * @param HRTIMx High Resolution Timer instance
10601 * @retval Trig This parameter can be a combination of the following values:
10602 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10603 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10604 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10605 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10606 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10607 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10608 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10609 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10610 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10611 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10612 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10613 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10614 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10615 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10616 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10617 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10618 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10619 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10620 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10621 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10622 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10623 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10624 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10625 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10626 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10627 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10628 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10629 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10630 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10631 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10632 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10633 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10634 */
LL_HRTIM_BM_GetTrig(HRTIM_TypeDef * HRTIMx)10635 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
10636 {
10637 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
10638 }
10639
10640 /**
10641 * @brief Set the burst mode controller compare value.
10642 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
10643 * @param HRTIMx High Resolution Timer instance
10644 * @param CompareValue Compare value must be above or equal to 3
10645 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10646 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10647 * @retval None
10648 */
LL_HRTIM_BM_SetCompare(HRTIM_TypeDef * HRTIMx,uint32_t CompareValue)10649 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
10650 {
10651 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
10652 }
10653
10654 /**
10655 * @brief Get actual burst mode controller compare value.
10656 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
10657 * @param HRTIMx High Resolution Timer instance
10658 * @retval CompareValue Compare value must be above or equal to 3
10659 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10660 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10661 */
LL_HRTIM_BM_GetCompare(HRTIM_TypeDef * HRTIMx)10662 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
10663 {
10664 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
10665 }
10666
10667 /**
10668 * @brief Set the burst mode controller period.
10669 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
10670 * @param HRTIMx High Resolution Timer instance
10671 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
10672 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10673 * The maximum value is 0x0000 FFDF.
10674 * @retval None
10675 */
LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Period)10676 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
10677 {
10678 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
10679 }
10680
10681 /**
10682 * @brief Get actual burst mode controller period.
10683 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
10684 * @param HRTIMx High Resolution Timer instance
10685 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
10686 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10687 * The maximum value is 0x0000 FFDF.
10688 */
LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef * HRTIMx)10689 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
10690 {
10691 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
10692 }
10693
10694 /**
10695 * @brief Enable the burst mode controller
10696 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
10697 * @param HRTIMx High Resolution Timer instance
10698 * @retval None
10699 */
LL_HRTIM_BM_Enable(HRTIM_TypeDef * HRTIMx)10700 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
10701 {
10702 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10703 }
10704
10705 /**
10706 * @brief Disable the burst mode controller
10707 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
10708 * @param HRTIMx High Resolution Timer instance
10709 * @retval None
10710 */
LL_HRTIM_BM_Disable(HRTIM_TypeDef * HRTIMx)10711 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
10712 {
10713 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10714 }
10715
10716 /**
10717 * @brief Indicate whether the burst mode controller is enabled.
10718 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
10719 * @param HRTIMx High Resolution Timer instance
10720 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
10721 */
LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef * HRTIMx)10722 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
10723 {
10724 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
10725 }
10726
10727 /**
10728 * @brief Trigger the burst operation (software trigger)
10729 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
10730 * @param HRTIMx High Resolution Timer instance
10731 * @retval None
10732 */
LL_HRTIM_BM_Start(HRTIM_TypeDef * HRTIMx)10733 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
10734 {
10735 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
10736 }
10737
10738 /**
10739 * @brief Stop the burst mode operation.
10740 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
10741 * @note Causes a burst mode early termination.
10742 * @param HRTIMx High Resolution Timer instance
10743 * @retval None
10744 */
LL_HRTIM_BM_Stop(HRTIM_TypeDef * HRTIMx)10745 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
10746 {
10747 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
10748 }
10749
10750 /**
10751 * @brief Get actual burst mode status
10752 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
10753 * @param HRTIMx High Resolution Timer instance
10754 * @retval Status This parameter can be one of the following values:
10755 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
10756 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
10757 */
LL_HRTIM_BM_GetStatus(HRTIM_TypeDef * HRTIMx)10758 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
10759 {
10760 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
10761 }
10762
10763 /**
10764 * @}
10765 */
10766
10767 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
10768 * @{
10769 */
10770
10771 /**
10772 * @brief Clear the Fault 1 interrupt flag.
10773 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
10774 * @param HRTIMx High Resolution Timer instance
10775 * @retval None
10776 */
LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef * HRTIMx)10777 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10778 {
10779 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
10780 }
10781
10782 /**
10783 * @brief Indicate whether Fault 1 interrupt occurred.
10784 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
10785 * @param HRTIMx High Resolution Timer instance
10786 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
10787 */
LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef * HRTIMx)10788 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10789 {
10790 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
10791 }
10792
10793 /**
10794 * @brief Clear the Fault 2 interrupt flag.
10795 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
10796 * @param HRTIMx High Resolution Timer instance
10797 * @retval None
10798 */
LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef * HRTIMx)10799 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10800 {
10801 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
10802 }
10803
10804 /**
10805 * @brief Indicate whether Fault 2 interrupt occurred.
10806 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
10807 * @param HRTIMx High Resolution Timer instance
10808 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
10809 */
LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef * HRTIMx)10810 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10811 {
10812 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
10813 }
10814
10815 /**
10816 * @brief Clear the Fault 3 interrupt flag.
10817 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
10818 * @param HRTIMx High Resolution Timer instance
10819 * @retval None
10820 */
LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef * HRTIMx)10821 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10822 {
10823 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
10824 }
10825
10826 /**
10827 * @brief Indicate whether Fault 3 interrupt occurred.
10828 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
10829 * @param HRTIMx High Resolution Timer instance
10830 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
10831 */
LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef * HRTIMx)10832 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10833 {
10834 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
10835 }
10836
10837 /**
10838 * @brief Clear the Fault 4 interrupt flag.
10839 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
10840 * @param HRTIMx High Resolution Timer instance
10841 * @retval None
10842 */
LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef * HRTIMx)10843 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10844 {
10845 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
10846 }
10847
10848 /**
10849 * @brief Indicate whether Fault 4 interrupt occurred.
10850 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
10851 * @param HRTIMx High Resolution Timer instance
10852 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
10853 */
LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef * HRTIMx)10854 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10855 {
10856 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
10857 }
10858
10859 /**
10860 * @brief Clear the Fault 5 interrupt flag.
10861 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
10862 * @param HRTIMx High Resolution Timer instance
10863 * @retval None
10864 */
LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef * HRTIMx)10865 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10866 {
10867 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
10868 }
10869
10870 /**
10871 * @brief Indicate whether Fault 5 interrupt occurred.
10872 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
10873 * @param HRTIMx High Resolution Timer instance
10874 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
10875 */
LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef * HRTIMx)10876 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10877 {
10878 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
10879 }
10880
10881 /**
10882 * @brief Clear the Fault 6 interrupt flag.
10883 * @rmtoll ICR FLT6C LL_HRTIM_ClearFlag_FLT6
10884 * @param HRTIMx High Resolution Timer instance
10885 * @retval None
10886 */
LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef * HRTIMx)10887 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10888 {
10889 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
10890 }
10891
10892 /**
10893 * @brief Indicate whether Fault 6 interrupt occurred.
10894 * @rmtoll ICR FLT6 LL_HRTIM_IsActiveFlag_FLT6
10895 * @param HRTIMx High Resolution Timer instance
10896 * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
10897 */
LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef * HRTIMx)10898 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10899 {
10900 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
10901 }
10902
10903 /**
10904 * @brief Clear the System Fault interrupt flag.
10905 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
10906 * @param HRTIMx High Resolution Timer instance
10907 * @retval None
10908 */
LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)10909 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10910 {
10911 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
10912 }
10913
10914 /**
10915 * @brief Indicate whether System Fault interrupt occurred.
10916 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
10917 * @param HRTIMx High Resolution Timer instance
10918 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
10919 */
LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)10920 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10921 {
10922 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
10923 }
10924
10925 /**
10926 * @brief Clear the DLL ready interrupt flag.
10927 * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
10928 * @param HRTIMx High Resolution Timer instance
10929 * @retval None
10930 */
LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)10931 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10932 {
10933 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
10934 }
10935
10936 /**
10937 * @brief Indicate whether DLL ready interrupt occurred.
10938 * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
10939 * @param HRTIMx High Resolution Timer instance
10940 * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
10941 */
LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)10942 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10943 {
10944 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
10945 }
10946
10947 /**
10948 * @brief Clear the Burst Mode period interrupt flag.
10949 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
10950 * @param HRTIMx High Resolution Timer instance
10951 * @retval None
10952 */
LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef * HRTIMx)10953 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10954 {
10955 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
10956 }
10957
10958 /**
10959 * @brief Indicate whether Burst Mode period interrupt occurred.
10960 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
10961 * @param HRTIMx High Resolution Timer instance
10962 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
10963 */
LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef * HRTIMx)10964 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10965 {
10966 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
10967 }
10968
10969 /**
10970 * @brief Clear the Synchronization Input interrupt flag.
10971 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
10972 * @param HRTIMx High Resolution Timer instance
10973 * @retval None
10974 */
LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef * HRTIMx)10975 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10976 {
10977 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
10978 }
10979
10980 /**
10981 * @brief Indicate whether the Synchronization Input interrupt occurred.
10982 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
10983 * @param HRTIMx High Resolution Timer instance
10984 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
10985 */
LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef * HRTIMx)10986 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10987 {
10988 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
10989 }
10990
10991 /**
10992 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
10993 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
10994 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
10995 * @param HRTIMx High Resolution Timer instance
10996 * @param Timer This parameter can be one of the following values:
10997 * @arg @ref LL_HRTIM_TIMER_MASTER
10998 * @arg @ref LL_HRTIM_TIMER_A
10999 * @arg @ref LL_HRTIM_TIMER_B
11000 * @arg @ref LL_HRTIM_TIMER_C
11001 * @arg @ref LL_HRTIM_TIMER_D
11002 * @arg @ref LL_HRTIM_TIMER_E
11003 * @arg @ref LL_HRTIM_TIMER_F
11004 * @retval None
11005 */
LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11006 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11007 {
11008 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11009 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11010 REG_OFFSET_TAB_TIMER[iTimer]));
11011 SET_BIT(*pReg, HRTIM_MICR_MUPD);
11012 }
11013
11014 /**
11015 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
11016 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
11017 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
11018 * @param HRTIMx High Resolution Timer instance
11019 * @param Timer This parameter can be one of the following values:
11020 * @arg @ref LL_HRTIM_TIMER_MASTER
11021 * @arg @ref LL_HRTIM_TIMER_A
11022 * @arg @ref LL_HRTIM_TIMER_B
11023 * @arg @ref LL_HRTIM_TIMER_C
11024 * @arg @ref LL_HRTIM_TIMER_D
11025 * @arg @ref LL_HRTIM_TIMER_E
11026 * @arg @ref LL_HRTIM_TIMER_F
11027 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11028 */
LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11029 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11030 {
11031 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11032 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11033 REG_OFFSET_TAB_TIMER[iTimer]));
11034
11035 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
11036 }
11037
11038 /**
11039 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
11040 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
11041 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
11042 * @param HRTIMx High Resolution Timer instance
11043 * @param Timer This parameter can be one of the following values:
11044 * @arg @ref LL_HRTIM_TIMER_MASTER
11045 * @arg @ref LL_HRTIM_TIMER_A
11046 * @arg @ref LL_HRTIM_TIMER_B
11047 * @arg @ref LL_HRTIM_TIMER_C
11048 * @arg @ref LL_HRTIM_TIMER_D
11049 * @arg @ref LL_HRTIM_TIMER_E
11050 * @arg @ref LL_HRTIM_TIMER_F
11051 * @retval None
11052 */
LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11053 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11054 {
11055 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11056 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11057 REG_OFFSET_TAB_TIMER[iTimer]));
11058 SET_BIT(*pReg, HRTIM_MICR_MREP);
11059
11060 }
11061
11062 /**
11063 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
11064 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
11065 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
11066 * @param HRTIMx High Resolution Timer instance
11067 * @param Timer This parameter can be one of the following values:
11068 * @arg @ref LL_HRTIM_TIMER_MASTER
11069 * @arg @ref LL_HRTIM_TIMER_A
11070 * @arg @ref LL_HRTIM_TIMER_B
11071 * @arg @ref LL_HRTIM_TIMER_C
11072 * @arg @ref LL_HRTIM_TIMER_D
11073 * @arg @ref LL_HRTIM_TIMER_E
11074 * @arg @ref LL_HRTIM_TIMER_F
11075 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11076 */
LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11077 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11078 {
11079 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11080 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11081 REG_OFFSET_TAB_TIMER[iTimer]));
11082
11083 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
11084 }
11085
11086 /**
11087 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
11088 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
11089 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
11090 * @param HRTIMx High Resolution Timer instance
11091 * @param Timer This parameter can be one of the following values:
11092 * @arg @ref LL_HRTIM_TIMER_MASTER
11093 * @arg @ref LL_HRTIM_TIMER_A
11094 * @arg @ref LL_HRTIM_TIMER_B
11095 * @arg @ref LL_HRTIM_TIMER_C
11096 * @arg @ref LL_HRTIM_TIMER_D
11097 * @arg @ref LL_HRTIM_TIMER_E
11098 * @arg @ref LL_HRTIM_TIMER_F
11099 * @retval None
11100 */
LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11101 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11102 {
11103 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11104 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11105 REG_OFFSET_TAB_TIMER[iTimer]));
11106 SET_BIT(*pReg, HRTIM_MICR_MCMP1);
11107 }
11108
11109 /**
11110 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
11111 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
11112 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
11113 * @param HRTIMx High Resolution Timer instance
11114 * @param Timer This parameter can be one of the following values:
11115 * @arg @ref LL_HRTIM_TIMER_MASTER
11116 * @arg @ref LL_HRTIM_TIMER_A
11117 * @arg @ref LL_HRTIM_TIMER_B
11118 * @arg @ref LL_HRTIM_TIMER_C
11119 * @arg @ref LL_HRTIM_TIMER_D
11120 * @arg @ref LL_HRTIM_TIMER_E
11121 * @arg @ref LL_HRTIM_TIMER_F
11122 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11123 */
LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11124 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11125 {
11126 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11127 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11128 REG_OFFSET_TAB_TIMER[iTimer]));
11129
11130 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
11131 }
11132
11133 /**
11134 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
11135 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
11136 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
11137 * @param HRTIMx High Resolution Timer instance
11138 * @param Timer This parameter can be one of the following values:
11139 * @arg @ref LL_HRTIM_TIMER_MASTER
11140 * @arg @ref LL_HRTIM_TIMER_A
11141 * @arg @ref LL_HRTIM_TIMER_B
11142 * @arg @ref LL_HRTIM_TIMER_C
11143 * @arg @ref LL_HRTIM_TIMER_D
11144 * @arg @ref LL_HRTIM_TIMER_E
11145 * @arg @ref LL_HRTIM_TIMER_F
11146 * @retval None
11147 */
LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11148 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11149 {
11150 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11151 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11152 REG_OFFSET_TAB_TIMER[iTimer]));
11153 SET_BIT(*pReg, HRTIM_MICR_MCMP2);
11154 }
11155
11156 /**
11157 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
11158 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
11159 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
11160 * @param HRTIMx High Resolution Timer instance
11161 * @param Timer This parameter can be one of the following values:
11162 * @arg @ref LL_HRTIM_TIMER_MASTER
11163 * @arg @ref LL_HRTIM_TIMER_A
11164 * @arg @ref LL_HRTIM_TIMER_B
11165 * @arg @ref LL_HRTIM_TIMER_C
11166 * @arg @ref LL_HRTIM_TIMER_D
11167 * @arg @ref LL_HRTIM_TIMER_E
11168 * @arg @ref LL_HRTIM_TIMER_F
11169 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11170 */
LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11171 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11172 {
11173 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11174 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11175 REG_OFFSET_TAB_TIMER[iTimer]));
11176
11177 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
11178 }
11179
11180 /**
11181 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
11182 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
11183 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
11184 * @param HRTIMx High Resolution Timer instance
11185 * @param Timer This parameter can be one of the following values:
11186 * @arg @ref LL_HRTIM_TIMER_MASTER
11187 * @arg @ref LL_HRTIM_TIMER_A
11188 * @arg @ref LL_HRTIM_TIMER_B
11189 * @arg @ref LL_HRTIM_TIMER_C
11190 * @arg @ref LL_HRTIM_TIMER_D
11191 * @arg @ref LL_HRTIM_TIMER_E
11192 * @arg @ref LL_HRTIM_TIMER_F
11193 * @retval None
11194 */
LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11195 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11196 {
11197 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11198 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11199 REG_OFFSET_TAB_TIMER[iTimer]));
11200 SET_BIT(*pReg, HRTIM_MICR_MCMP3);
11201 }
11202
11203 /**
11204 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
11205 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
11206 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
11207 * @param HRTIMx High Resolution Timer instance
11208 * @param Timer This parameter can be one of the following values:
11209 * @arg @ref LL_HRTIM_TIMER_MASTER
11210 * @arg @ref LL_HRTIM_TIMER_A
11211 * @arg @ref LL_HRTIM_TIMER_B
11212 * @arg @ref LL_HRTIM_TIMER_C
11213 * @arg @ref LL_HRTIM_TIMER_D
11214 * @arg @ref LL_HRTIM_TIMER_E
11215 * @arg @ref LL_HRTIM_TIMER_F
11216 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11217 */
LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11218 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11219 {
11220 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11221 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11222 REG_OFFSET_TAB_TIMER[iTimer]));
11223
11224 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
11225 }
11226
11227 /**
11228 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
11229 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
11230 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
11231 * @param HRTIMx High Resolution Timer instance
11232 * @param Timer This parameter can be one of the following values:
11233 * @arg @ref LL_HRTIM_TIMER_MASTER
11234 * @arg @ref LL_HRTIM_TIMER_A
11235 * @arg @ref LL_HRTIM_TIMER_B
11236 * @arg @ref LL_HRTIM_TIMER_C
11237 * @arg @ref LL_HRTIM_TIMER_D
11238 * @arg @ref LL_HRTIM_TIMER_E
11239 * @arg @ref LL_HRTIM_TIMER_F
11240 * @retval None
11241 */
LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11242 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11243 {
11244 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11245 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11246 REG_OFFSET_TAB_TIMER[iTimer]));
11247 SET_BIT(*pReg, HRTIM_MICR_MCMP4);
11248 }
11249
11250 /**
11251 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
11252 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
11253 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
11254 * @param HRTIMx High Resolution Timer instance
11255 * @param Timer This parameter can be one of the following values:
11256 * @arg @ref LL_HRTIM_TIMER_MASTER
11257 * @arg @ref LL_HRTIM_TIMER_A
11258 * @arg @ref LL_HRTIM_TIMER_B
11259 * @arg @ref LL_HRTIM_TIMER_C
11260 * @arg @ref LL_HRTIM_TIMER_D
11261 * @arg @ref LL_HRTIM_TIMER_E
11262 * @arg @ref LL_HRTIM_TIMER_F
11263 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11264 */
LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11265 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11266 {
11267 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11268 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11269 REG_OFFSET_TAB_TIMER[iTimer]));
11270
11271 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
11272 }
11273
11274 /**
11275 * @brief Clear the capture 1 interrupt flag for a given timer.
11276 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
11277 * @param HRTIMx High Resolution Timer instance
11278 * @param Timer This parameter can be one of the following values:
11279 * @arg @ref LL_HRTIM_TIMER_A
11280 * @arg @ref LL_HRTIM_TIMER_B
11281 * @arg @ref LL_HRTIM_TIMER_C
11282 * @arg @ref LL_HRTIM_TIMER_D
11283 * @arg @ref LL_HRTIM_TIMER_E
11284 * @arg @ref LL_HRTIM_TIMER_F
11285 * @retval None
11286 */
LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11287 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11288 {
11289 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11290 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11291 REG_OFFSET_TAB_TIMER[iTimer]));
11292 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
11293 }
11294
11295 /**
11296 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
11297 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
11298 * @param HRTIMx High Resolution Timer instance
11299 * @param Timer This parameter can be one of the following values:
11300 * @arg @ref LL_HRTIM_TIMER_A
11301 * @arg @ref LL_HRTIM_TIMER_B
11302 * @arg @ref LL_HRTIM_TIMER_C
11303 * @arg @ref LL_HRTIM_TIMER_D
11304 * @arg @ref LL_HRTIM_TIMER_E
11305 * @arg @ref LL_HRTIM_TIMER_F
11306 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
11307 */
LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11308 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11309 {
11310 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11311 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11312 REG_OFFSET_TAB_TIMER[iTimer]));
11313
11314 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
11315 }
11316
11317 /**
11318 * @brief Clear the capture 2 interrupt flag for a given timer.
11319 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
11320 * @param HRTIMx High Resolution Timer instance
11321 * @param Timer This parameter can be one of the following values:
11322 * @arg @ref LL_HRTIM_TIMER_A
11323 * @arg @ref LL_HRTIM_TIMER_B
11324 * @arg @ref LL_HRTIM_TIMER_C
11325 * @arg @ref LL_HRTIM_TIMER_D
11326 * @arg @ref LL_HRTIM_TIMER_E
11327 * @arg @ref LL_HRTIM_TIMER_F
11328 * @retval None
11329 */
LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11330 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11331 {
11332 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11333 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11334 REG_OFFSET_TAB_TIMER[iTimer]));
11335 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
11336 }
11337
11338 /**
11339 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
11340 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
11341 * @param HRTIMx High Resolution Timer instance
11342 * @param Timer This parameter can be one of the following values:
11343 * @arg @ref LL_HRTIM_TIMER_A
11344 * @arg @ref LL_HRTIM_TIMER_B
11345 * @arg @ref LL_HRTIM_TIMER_C
11346 * @arg @ref LL_HRTIM_TIMER_D
11347 * @arg @ref LL_HRTIM_TIMER_E
11348 * @arg @ref LL_HRTIM_TIMER_F
11349 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
11350 */
LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11351 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11352 {
11353 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11354 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11355 REG_OFFSET_TAB_TIMER[iTimer]));
11356
11357 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
11358 }
11359
11360 /**
11361 * @brief Clear the output 1 set interrupt flag for a given timer.
11362 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
11363 * @param HRTIMx High Resolution Timer instance
11364 * @param Timer This parameter can be one of the following values:
11365 * @arg @ref LL_HRTIM_TIMER_A
11366 * @arg @ref LL_HRTIM_TIMER_B
11367 * @arg @ref LL_HRTIM_TIMER_C
11368 * @arg @ref LL_HRTIM_TIMER_D
11369 * @arg @ref LL_HRTIM_TIMER_E
11370 * @arg @ref LL_HRTIM_TIMER_F
11371 * @retval None
11372 */
LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11373 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11374 {
11375 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11376 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11377 REG_OFFSET_TAB_TIMER[iTimer]));
11378 SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
11379 }
11380
11381 /**
11382 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
11383 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
11384 * @param HRTIMx High Resolution Timer instance
11385 * @param Timer This parameter can be one of the following values:
11386 * @arg @ref LL_HRTIM_TIMER_A
11387 * @arg @ref LL_HRTIM_TIMER_B
11388 * @arg @ref LL_HRTIM_TIMER_C
11389 * @arg @ref LL_HRTIM_TIMER_D
11390 * @arg @ref LL_HRTIM_TIMER_E
11391 * @arg @ref LL_HRTIM_TIMER_F
11392 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
11393 */
LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11394 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11395 {
11396 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11397 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11398 REG_OFFSET_TAB_TIMER[iTimer]));
11399
11400 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
11401 }
11402
11403 /**
11404 * @brief Clear the output 1 reset interrupt flag for a given timer.
11405 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
11406 * @param HRTIMx High Resolution Timer instance
11407 * @param Timer This parameter can be one of the following values:
11408 * @arg @ref LL_HRTIM_TIMER_A
11409 * @arg @ref LL_HRTIM_TIMER_B
11410 * @arg @ref LL_HRTIM_TIMER_C
11411 * @arg @ref LL_HRTIM_TIMER_D
11412 * @arg @ref LL_HRTIM_TIMER_E
11413 * @arg @ref LL_HRTIM_TIMER_F
11414 * @retval None
11415 */
LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11416 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11417 {
11418 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11419 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11420 REG_OFFSET_TAB_TIMER[iTimer]));
11421 SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
11422 }
11423
11424 /**
11425 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
11426 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
11427 * @param HRTIMx High Resolution Timer instance
11428 * @param Timer This parameter can be one of the following values:
11429 * @arg @ref LL_HRTIM_TIMER_A
11430 * @arg @ref LL_HRTIM_TIMER_B
11431 * @arg @ref LL_HRTIM_TIMER_C
11432 * @arg @ref LL_HRTIM_TIMER_D
11433 * @arg @ref LL_HRTIM_TIMER_E
11434 * @arg @ref LL_HRTIM_TIMER_F
11435 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
11436 */
LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11437 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11438 {
11439 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11440 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11441 REG_OFFSET_TAB_TIMER[iTimer]));
11442
11443 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
11444 }
11445
11446 /**
11447 * @brief Clear the output 2 set interrupt flag for a given timer.
11448 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
11449 * @param HRTIMx High Resolution Timer instance
11450 * @param Timer This parameter can be one of the following values:
11451 * @arg @ref LL_HRTIM_TIMER_A
11452 * @arg @ref LL_HRTIM_TIMER_B
11453 * @arg @ref LL_HRTIM_TIMER_C
11454 * @arg @ref LL_HRTIM_TIMER_D
11455 * @arg @ref LL_HRTIM_TIMER_E
11456 * @arg @ref LL_HRTIM_TIMER_F
11457 * @retval None
11458 */
LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11459 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11460 {
11461 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11462 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11463 REG_OFFSET_TAB_TIMER[iTimer]));
11464 SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
11465 }
11466
11467 /**
11468 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
11469 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
11470 * @param HRTIMx High Resolution Timer instance
11471 * @param Timer This parameter can be one of the following values:
11472 * @arg @ref LL_HRTIM_TIMER_A
11473 * @arg @ref LL_HRTIM_TIMER_B
11474 * @arg @ref LL_HRTIM_TIMER_C
11475 * @arg @ref LL_HRTIM_TIMER_D
11476 * @arg @ref LL_HRTIM_TIMER_E
11477 * @arg @ref LL_HRTIM_TIMER_F
11478 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
11479 */
LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11480 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11481 {
11482 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11483 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11484 REG_OFFSET_TAB_TIMER[iTimer]));
11485
11486 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
11487 }
11488
11489 /**
11490 * @brief Clear the output 2reset interrupt flag for a given timer.
11491 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
11492 * @param HRTIMx High Resolution Timer instance
11493 * @param Timer This parameter can be one of the following values:
11494 * @arg @ref LL_HRTIM_TIMER_A
11495 * @arg @ref LL_HRTIM_TIMER_B
11496 * @arg @ref LL_HRTIM_TIMER_C
11497 * @arg @ref LL_HRTIM_TIMER_D
11498 * @arg @ref LL_HRTIM_TIMER_E
11499 * @arg @ref LL_HRTIM_TIMER_F
11500 * @retval None
11501 */
LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11502 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11503 {
11504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11506 REG_OFFSET_TAB_TIMER[iTimer]));
11507 SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
11508 }
11509
11510 /**
11511 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
11512 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
11513 * @param HRTIMx High Resolution Timer instance
11514 * @param Timer This parameter can be one of the following values:
11515 * @arg @ref LL_HRTIM_TIMER_A
11516 * @arg @ref LL_HRTIM_TIMER_B
11517 * @arg @ref LL_HRTIM_TIMER_C
11518 * @arg @ref LL_HRTIM_TIMER_D
11519 * @arg @ref LL_HRTIM_TIMER_E
11520 * @arg @ref LL_HRTIM_TIMER_F
11521 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
11522 */
LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11523 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11524 {
11525 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11526 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11527 REG_OFFSET_TAB_TIMER[iTimer]));
11528
11529 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
11530 }
11531
11532 /**
11533 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
11534 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
11535 * @param HRTIMx High Resolution Timer instance
11536 * @param Timer This parameter can be one of the following values:
11537 * @arg @ref LL_HRTIM_TIMER_A
11538 * @arg @ref LL_HRTIM_TIMER_B
11539 * @arg @ref LL_HRTIM_TIMER_C
11540 * @arg @ref LL_HRTIM_TIMER_D
11541 * @arg @ref LL_HRTIM_TIMER_E
11542 * @arg @ref LL_HRTIM_TIMER_F
11543 * @retval None
11544 */
LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11545 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11546 {
11547 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11548 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11549 REG_OFFSET_TAB_TIMER[iTimer]));
11550 SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
11551 }
11552
11553 /**
11554 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
11555 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
11556 * @param HRTIMx High Resolution Timer instance
11557 * @param Timer This parameter can be one of the following values:
11558 * @arg @ref LL_HRTIM_TIMER_A
11559 * @arg @ref LL_HRTIM_TIMER_B
11560 * @arg @ref LL_HRTIM_TIMER_C
11561 * @arg @ref LL_HRTIM_TIMER_D
11562 * @arg @ref LL_HRTIM_TIMER_E
11563 * @arg @ref LL_HRTIM_TIMER_F
11564 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
11565 */
LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11566 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11567 {
11568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11569 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11570 REG_OFFSET_TAB_TIMER[iTimer]));
11571
11572 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
11573 }
11574
11575 /**
11576 * @brief Clear the delayed protection interrupt flag for a given timer.
11577 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
11578 * @param HRTIMx High Resolution Timer instance
11579 * @param Timer This parameter can be one of the following values:
11580 * @arg @ref LL_HRTIM_TIMER_A
11581 * @arg @ref LL_HRTIM_TIMER_B
11582 * @arg @ref LL_HRTIM_TIMER_C
11583 * @arg @ref LL_HRTIM_TIMER_D
11584 * @arg @ref LL_HRTIM_TIMER_E
11585 * @arg @ref LL_HRTIM_TIMER_F
11586 * @retval None
11587 */
LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11588 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11589 {
11590 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11591 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11592 REG_OFFSET_TAB_TIMER[iTimer]));
11593 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
11594 }
11595
11596 /**
11597 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
11598 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
11599 * @param HRTIMx High Resolution Timer instance
11600 * @param Timer This parameter can be one of the following values:
11601 * @arg @ref LL_HRTIM_TIMER_A
11602 * @arg @ref LL_HRTIM_TIMER_B
11603 * @arg @ref LL_HRTIM_TIMER_C
11604 * @arg @ref LL_HRTIM_TIMER_D
11605 * @arg @ref LL_HRTIM_TIMER_E
11606 * @arg @ref LL_HRTIM_TIMER_F
11607 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
11608 */
LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11609 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11610 {
11611 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11612 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11613 REG_OFFSET_TAB_TIMER[iTimer]));
11614
11615 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
11616 }
11617
11618 /**
11619 * @}
11620 */
11621
11622 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
11623 * @{
11624 */
11625
11626 /**
11627 * @brief Enable the fault 1 interrupt.
11628 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
11629 * @param HRTIMx High Resolution Timer instance
11630 * @retval None
11631 */
LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef * HRTIMx)11632 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11633 {
11634 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11635 }
11636
11637 /**
11638 * @brief Disable the fault 1 interrupt.
11639 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
11640 * @param HRTIMx High Resolution Timer instance
11641 * @retval None
11642 */
LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef * HRTIMx)11643 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11644 {
11645 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11646 }
11647
11648 /**
11649 * @brief Indicate whether the fault 1 interrupt is enabled.
11650 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
11651 * @param HRTIMx High Resolution Timer instance
11652 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
11653 */
LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef * HRTIMx)11654 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
11655 {
11656 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
11657 }
11658
11659 /**
11660 * @brief Enable the fault 2 interrupt.
11661 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
11662 * @param HRTIMx High Resolution Timer instance
11663 * @retval None
11664 */
LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef * HRTIMx)11665 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11666 {
11667 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11668 }
11669
11670 /**
11671 * @brief Disable the fault 2 interrupt.
11672 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
11673 * @param HRTIMx High Resolution Timer instance
11674 * @retval None
11675 */
LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef * HRTIMx)11676 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11677 {
11678 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11679 }
11680
11681 /**
11682 * @brief Indicate whether the fault 2 interrupt is enabled.
11683 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
11684 * @param HRTIMx High Resolution Timer instance
11685 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
11686 */
LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef * HRTIMx)11687 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
11688 {
11689 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
11690 }
11691
11692 /**
11693 * @brief Enable the fault 3 interrupt.
11694 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
11695 * @param HRTIMx High Resolution Timer instance
11696 * @retval None
11697 */
LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef * HRTIMx)11698 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11699 {
11700 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11701 }
11702
11703 /**
11704 * @brief Disable the fault 3 interrupt.
11705 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
11706 * @param HRTIMx High Resolution Timer instance
11707 * @retval None
11708 */
LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef * HRTIMx)11709 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11710 {
11711 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11712 }
11713
11714 /**
11715 * @brief Indicate whether the fault 3 interrupt is enabled.
11716 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
11717 * @param HRTIMx High Resolution Timer instance
11718 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
11719 */
LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef * HRTIMx)11720 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
11721 {
11722 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
11723 }
11724
11725 /**
11726 * @brief Enable the fault 4 interrupt.
11727 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
11728 * @param HRTIMx High Resolution Timer instance
11729 * @retval None
11730 */
LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef * HRTIMx)11731 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11732 {
11733 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11734 }
11735
11736 /**
11737 * @brief Disable the fault 4 interrupt.
11738 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
11739 * @param HRTIMx High Resolution Timer instance
11740 * @retval None
11741 */
LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef * HRTIMx)11742 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11743 {
11744 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11745 }
11746
11747 /**
11748 * @brief Indicate whether the fault 4 interrupt is enabled.
11749 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
11750 * @param HRTIMx High Resolution Timer instance
11751 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
11752 */
LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef * HRTIMx)11753 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
11754 {
11755 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
11756 }
11757
11758 /**
11759 * @brief Enable the fault 5 interrupt.
11760 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
11761 * @param HRTIMx High Resolution Timer instance
11762 * @retval None
11763 */
LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef * HRTIMx)11764 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11765 {
11766 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11767 }
11768
11769 /**
11770 * @brief Disable the fault 5 interrupt.
11771 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
11772 * @param HRTIMx High Resolution Timer instance
11773 * @retval None
11774 */
LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef * HRTIMx)11775 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11776 {
11777 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11778 }
11779
11780 /**
11781 * @brief Indicate whether the fault 5 interrupt is enabled.
11782 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
11783 * @param HRTIMx High Resolution Timer instance
11784 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
11785 */
LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef * HRTIMx)11786 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
11787 {
11788 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
11789 }
11790
11791 /**
11792 * @brief Enable the fault 6 interrupt.
11793 * @rmtoll IER FLT6IE LL_HRTIM_EnableIT_FLT6
11794 * @param HRTIMx High Resolution Timer instance
11795 * @retval None
11796 */
LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef * HRTIMx)11797 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11798 {
11799 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11800 }
11801
11802 /**
11803 * @brief Disable the fault 6 interrupt.
11804 * @rmtoll IER FLT6IE LL_HRTIM_DisableIT_FLT6
11805 * @param HRTIMx High Resolution Timer instance
11806 * @retval None
11807 */
LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef * HRTIMx)11808 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11809 {
11810 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11811 }
11812
11813 /**
11814 * @brief Indicate whether the fault 6 interrupt is enabled.
11815 * @rmtoll IER FLT6IE LL_HRTIM_IsEnabledIT_FLT6
11816 * @param HRTIMx High Resolution Timer instance
11817 * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
11818 */
LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef * HRTIMx)11819 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef *HRTIMx)
11820 {
11821 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
11822 }
11823
11824 /**
11825 * @brief Enable the system fault interrupt.
11826 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
11827 * @param HRTIMx High Resolution Timer instance
11828 * @retval None
11829 */
LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11830 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11831 {
11832 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11833 }
11834
11835 /**
11836 * @brief Disable the system fault interrupt.
11837 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
11838 * @param HRTIMx High Resolution Timer instance
11839 * @retval None
11840 */
LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11841 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11842 {
11843 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11844 }
11845
11846 /**
11847 * @brief Indicate whether the system fault interrupt is enabled.
11848 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
11849 * @param HRTIMx High Resolution Timer instance
11850 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
11851 */
LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11852 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11853 {
11854 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
11855 }
11856
11857 /**
11858 * @brief Enable the DLL ready interrupt.
11859 * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
11860 * @param HRTIMx High Resolution Timer instance
11861 * @retval None
11862 */
LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11863 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11864 {
11865 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11866 }
11867
11868 /**
11869 * @brief Disable the DLL ready interrupt.
11870 * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
11871 * @param HRTIMx High Resolution Timer instance
11872 * @retval None
11873 */
LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11874 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11875 {
11876 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11877 }
11878
11879 /**
11880 * @brief Indicate whether the DLL ready interrupt is enabled.
11881 * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
11882 * @param HRTIMx High Resolution Timer instance
11883 * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
11884 */
LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11885 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11886 {
11887 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
11888 }
11889
11890 /**
11891 * @brief Enable the burst mode period interrupt.
11892 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
11893 * @param HRTIMx High Resolution Timer instance
11894 * @retval None
11895 */
LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef * HRTIMx)11896 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11897 {
11898 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11899 }
11900
11901 /**
11902 * @brief Disable the burst mode period interrupt.
11903 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
11904 * @param HRTIMx High Resolution Timer instance
11905 * @retval None
11906 */
LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef * HRTIMx)11907 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11908 {
11909 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11910 }
11911
11912 /**
11913 * @brief Indicate whether the burst mode period interrupt is enabled.
11914 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
11915 * @param HRTIMx High Resolution Timer instance
11916 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
11917 */
LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef * HRTIMx)11918 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
11919 {
11920 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
11921 }
11922
11923 /**
11924 * @brief Enable the synchronization input interrupt.
11925 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
11926 * @param HRTIMx High Resolution Timer instance
11927 * @retval None
11928 */
LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef * HRTIMx)11929 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11930 {
11931 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11932 }
11933
11934 /**
11935 * @brief Disable the synchronization input interrupt.
11936 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
11937 * @param HRTIMx High Resolution Timer instance
11938 * @retval None
11939 */
LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef * HRTIMx)11940 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11941 {
11942 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11943 }
11944
11945 /**
11946 * @brief Indicate whether the synchronization input interrupt is enabled.
11947 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
11948 * @param HRTIMx High Resolution Timer instance
11949 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
11950 */
LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef * HRTIMx)11951 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
11952 {
11953 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
11954 }
11955
11956 /**
11957 * @brief Enable the update interrupt for a given timer.
11958 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
11959 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
11960 * @param HRTIMx High Resolution Timer instance
11961 * @param Timer This parameter can be one of the following values:
11962 * @arg @ref LL_HRTIM_TIMER_MASTER
11963 * @arg @ref LL_HRTIM_TIMER_A
11964 * @arg @ref LL_HRTIM_TIMER_B
11965 * @arg @ref LL_HRTIM_TIMER_C
11966 * @arg @ref LL_HRTIM_TIMER_D
11967 * @arg @ref LL_HRTIM_TIMER_E
11968 * @arg @ref LL_HRTIM_TIMER_F
11969 * @retval None
11970 */
LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11971 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11972 {
11973 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11974 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11975 REG_OFFSET_TAB_TIMER[iTimer]));
11976 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
11977 }
11978
11979 /**
11980 * @brief Disable the update interrupt for a given timer.
11981 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
11982 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
11983 * @param HRTIMx High Resolution Timer instance
11984 * @param Timer This parameter can be one of the following values:
11985 * @arg @ref LL_HRTIM_TIMER_MASTER
11986 * @arg @ref LL_HRTIM_TIMER_A
11987 * @arg @ref LL_HRTIM_TIMER_B
11988 * @arg @ref LL_HRTIM_TIMER_C
11989 * @arg @ref LL_HRTIM_TIMER_D
11990 * @arg @ref LL_HRTIM_TIMER_E
11991 * @arg @ref LL_HRTIM_TIMER_F
11992 * @retval None
11993 */
LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11994 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11995 {
11996 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11997 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11998 REG_OFFSET_TAB_TIMER[iTimer]));
11999 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
12000 }
12001
12002 /**
12003 * @brief Indicate whether the update interrupt is enabled for a given timer.
12004 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
12005 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
12006 * @param HRTIMx High Resolution Timer instance
12007 * @param Timer This parameter can be one of the following values:
12008 * @arg @ref LL_HRTIM_TIMER_MASTER
12009 * @arg @ref LL_HRTIM_TIMER_A
12010 * @arg @ref LL_HRTIM_TIMER_B
12011 * @arg @ref LL_HRTIM_TIMER_C
12012 * @arg @ref LL_HRTIM_TIMER_D
12013 * @arg @ref LL_HRTIM_TIMER_E
12014 * @arg @ref LL_HRTIM_TIMER_F
12015 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12016 */
LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12017 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12018 {
12019 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12020 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12021 REG_OFFSET_TAB_TIMER[iTimer]));
12022
12023 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
12024 }
12025
12026 /**
12027 * @brief Enable the repetition interrupt for a given timer.
12028 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
12029 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
12030 * @param HRTIMx High Resolution Timer instance
12031 * @param Timer This parameter can be one of the following values:
12032 * @arg @ref LL_HRTIM_TIMER_MASTER
12033 * @arg @ref LL_HRTIM_TIMER_A
12034 * @arg @ref LL_HRTIM_TIMER_B
12035 * @arg @ref LL_HRTIM_TIMER_C
12036 * @arg @ref LL_HRTIM_TIMER_D
12037 * @arg @ref LL_HRTIM_TIMER_E
12038 * @arg @ref LL_HRTIM_TIMER_F
12039 * @retval None
12040 */
LL_HRTIM_EnableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12041 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12042 {
12043 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12044 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12045 REG_OFFSET_TAB_TIMER[iTimer]));
12046 SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
12047 }
12048
12049 /**
12050 * @brief Disable the repetition interrupt for a given timer.
12051 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
12052 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
12053 * @param HRTIMx High Resolution Timer instance
12054 * @param Timer This parameter can be one of the following values:
12055 * @arg @ref LL_HRTIM_TIMER_MASTER
12056 * @arg @ref LL_HRTIM_TIMER_A
12057 * @arg @ref LL_HRTIM_TIMER_B
12058 * @arg @ref LL_HRTIM_TIMER_C
12059 * @arg @ref LL_HRTIM_TIMER_D
12060 * @arg @ref LL_HRTIM_TIMER_E
12061 * @arg @ref LL_HRTIM_TIMER_F
12062 * @retval None
12063 */
LL_HRTIM_DisableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12064 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12065 {
12066 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12067 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12068 REG_OFFSET_TAB_TIMER[iTimer]));
12069 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
12070 }
12071
12072 /**
12073 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
12074 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
12075 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
12076 * @param HRTIMx High Resolution Timer instance
12077 * @param Timer This parameter can be one of the following values:
12078 * @arg @ref LL_HRTIM_TIMER_MASTER
12079 * @arg @ref LL_HRTIM_TIMER_A
12080 * @arg @ref LL_HRTIM_TIMER_B
12081 * @arg @ref LL_HRTIM_TIMER_C
12082 * @arg @ref LL_HRTIM_TIMER_D
12083 * @arg @ref LL_HRTIM_TIMER_E
12084 * @arg @ref LL_HRTIM_TIMER_F
12085 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12086 */
LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12087 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12088 {
12089 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12090 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12091 REG_OFFSET_TAB_TIMER[iTimer]));
12092
12093 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
12094 }
12095
12096 /**
12097 * @brief Enable the compare 1 interrupt for a given timer.
12098 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
12099 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
12100 * @param HRTIMx High Resolution Timer instance
12101 * @param Timer This parameter can be one of the following values:
12102 * @arg @ref LL_HRTIM_TIMER_MASTER
12103 * @arg @ref LL_HRTIM_TIMER_A
12104 * @arg @ref LL_HRTIM_TIMER_B
12105 * @arg @ref LL_HRTIM_TIMER_C
12106 * @arg @ref LL_HRTIM_TIMER_D
12107 * @arg @ref LL_HRTIM_TIMER_E
12108 * @arg @ref LL_HRTIM_TIMER_F
12109 * @retval None
12110 */
LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12111 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12112 {
12113 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12114 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12115 REG_OFFSET_TAB_TIMER[iTimer]));
12116 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12117 }
12118
12119 /**
12120 * @brief Disable the compare 1 interrupt for a given timer.
12121 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
12122 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
12123 * @param HRTIMx High Resolution Timer instance
12124 * @param Timer This parameter can be one of the following values:
12125 * @arg @ref LL_HRTIM_TIMER_MASTER
12126 * @arg @ref LL_HRTIM_TIMER_A
12127 * @arg @ref LL_HRTIM_TIMER_B
12128 * @arg @ref LL_HRTIM_TIMER_C
12129 * @arg @ref LL_HRTIM_TIMER_D
12130 * @arg @ref LL_HRTIM_TIMER_E
12131 * @arg @ref LL_HRTIM_TIMER_F
12132 * @retval None
12133 */
LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12134 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12135 {
12136 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12137 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12138 REG_OFFSET_TAB_TIMER[iTimer]));
12139 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12140 }
12141
12142 /**
12143 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
12144 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
12145 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
12146 * @param HRTIMx High Resolution Timer instance
12147 * @param Timer This parameter can be one of the following values:
12148 * @arg @ref LL_HRTIM_TIMER_MASTER
12149 * @arg @ref LL_HRTIM_TIMER_A
12150 * @arg @ref LL_HRTIM_TIMER_B
12151 * @arg @ref LL_HRTIM_TIMER_C
12152 * @arg @ref LL_HRTIM_TIMER_D
12153 * @arg @ref LL_HRTIM_TIMER_E
12154 * @arg @ref LL_HRTIM_TIMER_F
12155 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12156 */
LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12157 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12158 {
12159 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12160 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12161 REG_OFFSET_TAB_TIMER[iTimer]));
12162
12163 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
12164 }
12165
12166 /**
12167 * @brief Enable the compare 2 interrupt for a given timer.
12168 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
12169 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
12170 * @param HRTIMx High Resolution Timer instance
12171 * @param Timer This parameter can be one of the following values:
12172 * @arg @ref LL_HRTIM_TIMER_MASTER
12173 * @arg @ref LL_HRTIM_TIMER_A
12174 * @arg @ref LL_HRTIM_TIMER_B
12175 * @arg @ref LL_HRTIM_TIMER_C
12176 * @arg @ref LL_HRTIM_TIMER_D
12177 * @arg @ref LL_HRTIM_TIMER_E
12178 * @arg @ref LL_HRTIM_TIMER_F
12179 * @retval None
12180 */
LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12181 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12182 {
12183 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12184 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12185 REG_OFFSET_TAB_TIMER[iTimer]));
12186 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12187 }
12188
12189 /**
12190 * @brief Disable the compare 2 interrupt for a given timer.
12191 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
12192 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
12193 * @param HRTIMx High Resolution Timer instance
12194 * @param Timer This parameter can be one of the following values:
12195 * @arg @ref LL_HRTIM_TIMER_MASTER
12196 * @arg @ref LL_HRTIM_TIMER_A
12197 * @arg @ref LL_HRTIM_TIMER_B
12198 * @arg @ref LL_HRTIM_TIMER_C
12199 * @arg @ref LL_HRTIM_TIMER_D
12200 * @arg @ref LL_HRTIM_TIMER_E
12201 * @arg @ref LL_HRTIM_TIMER_F
12202 * @retval None
12203 */
LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12204 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12205 {
12206 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12207 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12208 REG_OFFSET_TAB_TIMER[iTimer]));
12209 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12210 }
12211
12212 /**
12213 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
12214 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
12215 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
12216 * @param HRTIMx High Resolution Timer instance
12217 * @param Timer This parameter can be one of the following values:
12218 * @arg @ref LL_HRTIM_TIMER_MASTER
12219 * @arg @ref LL_HRTIM_TIMER_A
12220 * @arg @ref LL_HRTIM_TIMER_B
12221 * @arg @ref LL_HRTIM_TIMER_C
12222 * @arg @ref LL_HRTIM_TIMER_D
12223 * @arg @ref LL_HRTIM_TIMER_E
12224 * @arg @ref LL_HRTIM_TIMER_F
12225 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12226 */
LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12227 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12228 {
12229 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12230 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12231 REG_OFFSET_TAB_TIMER[iTimer]));
12232
12233 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
12234 }
12235
12236 /**
12237 * @brief Enable the compare 3 interrupt for a given timer.
12238 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
12239 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
12240 * @param HRTIMx High Resolution Timer instance
12241 * @param Timer This parameter can be one of the following values:
12242 * @arg @ref LL_HRTIM_TIMER_MASTER
12243 * @arg @ref LL_HRTIM_TIMER_A
12244 * @arg @ref LL_HRTIM_TIMER_B
12245 * @arg @ref LL_HRTIM_TIMER_C
12246 * @arg @ref LL_HRTIM_TIMER_D
12247 * @arg @ref LL_HRTIM_TIMER_E
12248 * @arg @ref LL_HRTIM_TIMER_F
12249 * @retval None
12250 */
LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12251 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12252 {
12253 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12254 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12255 REG_OFFSET_TAB_TIMER[iTimer]));
12256 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12257 }
12258
12259 /**
12260 * @brief Disable the compare 3 interrupt for a given timer.
12261 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
12262 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
12263 * @param HRTIMx High Resolution Timer instance
12264 * @param Timer This parameter can be one of the following values:
12265 * @arg @ref LL_HRTIM_TIMER_MASTER
12266 * @arg @ref LL_HRTIM_TIMER_A
12267 * @arg @ref LL_HRTIM_TIMER_B
12268 * @arg @ref LL_HRTIM_TIMER_C
12269 * @arg @ref LL_HRTIM_TIMER_D
12270 * @arg @ref LL_HRTIM_TIMER_E
12271 * @arg @ref LL_HRTIM_TIMER_F
12272 * @retval None
12273 */
LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12274 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12275 {
12276 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12277 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12278 REG_OFFSET_TAB_TIMER[iTimer]));
12279 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12280 }
12281
12282 /**
12283 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
12284 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
12285 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
12286 * @param HRTIMx High Resolution Timer instance
12287 * @param Timer This parameter can be one of the following values:
12288 * @arg @ref LL_HRTIM_TIMER_MASTER
12289 * @arg @ref LL_HRTIM_TIMER_A
12290 * @arg @ref LL_HRTIM_TIMER_B
12291 * @arg @ref LL_HRTIM_TIMER_C
12292 * @arg @ref LL_HRTIM_TIMER_D
12293 * @arg @ref LL_HRTIM_TIMER_E
12294 * @arg @ref LL_HRTIM_TIMER_F
12295 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12296 */
LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12297 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12298 {
12299 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12300 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12301 REG_OFFSET_TAB_TIMER[iTimer]));
12302
12303 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
12304 }
12305
12306 /**
12307 * @brief Enable the compare 4 interrupt for a given timer.
12308 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
12309 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
12310 * @param HRTIMx High Resolution Timer instance
12311 * @param Timer This parameter can be one of the following values:
12312 * @arg @ref LL_HRTIM_TIMER_MASTER
12313 * @arg @ref LL_HRTIM_TIMER_A
12314 * @arg @ref LL_HRTIM_TIMER_B
12315 * @arg @ref LL_HRTIM_TIMER_C
12316 * @arg @ref LL_HRTIM_TIMER_D
12317 * @arg @ref LL_HRTIM_TIMER_E
12318 * @arg @ref LL_HRTIM_TIMER_F
12319 * @retval None
12320 */
LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12321 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12322 {
12323 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12324 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12325 REG_OFFSET_TAB_TIMER[iTimer]));
12326 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12327 }
12328
12329 /**
12330 * @brief Disable the compare 4 interrupt for a given timer.
12331 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
12332 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
12333 * @param HRTIMx High Resolution Timer instance
12334 * @param Timer This parameter can be one of the following values:
12335 * @arg @ref LL_HRTIM_TIMER_MASTER
12336 * @arg @ref LL_HRTIM_TIMER_A
12337 * @arg @ref LL_HRTIM_TIMER_B
12338 * @arg @ref LL_HRTIM_TIMER_C
12339 * @arg @ref LL_HRTIM_TIMER_D
12340 * @arg @ref LL_HRTIM_TIMER_E
12341 * @arg @ref LL_HRTIM_TIMER_F
12342 * @retval None
12343 */
LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12344 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12345 {
12346 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12347 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12348 REG_OFFSET_TAB_TIMER[iTimer]));
12349 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12350 }
12351
12352 /**
12353 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
12354 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
12355 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
12356 * @param HRTIMx High Resolution Timer instance
12357 * @param Timer This parameter can be one of the following values:
12358 * @arg @ref LL_HRTIM_TIMER_MASTER
12359 * @arg @ref LL_HRTIM_TIMER_A
12360 * @arg @ref LL_HRTIM_TIMER_B
12361 * @arg @ref LL_HRTIM_TIMER_C
12362 * @arg @ref LL_HRTIM_TIMER_D
12363 * @arg @ref LL_HRTIM_TIMER_E
12364 * @arg @ref LL_HRTIM_TIMER_F
12365 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12366 */
LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12367 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12368 {
12369 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12370 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12371 REG_OFFSET_TAB_TIMER[iTimer]));
12372
12373 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
12374 }
12375
12376 /**
12377 * @brief Enable the capture 1 interrupt for a given timer.
12378 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
12379 * @param HRTIMx High Resolution Timer instance
12380 * @param Timer This parameter can be one of the following values:
12381 * @arg @ref LL_HRTIM_TIMER_A
12382 * @arg @ref LL_HRTIM_TIMER_B
12383 * @arg @ref LL_HRTIM_TIMER_C
12384 * @arg @ref LL_HRTIM_TIMER_D
12385 * @arg @ref LL_HRTIM_TIMER_E
12386 * @arg @ref LL_HRTIM_TIMER_F
12387 * @retval None
12388 */
LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12389 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12390 {
12391 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12392 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12393 REG_OFFSET_TAB_TIMER[iTimer]));
12394 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12395 }
12396
12397 /**
12398 * @brief Enable the capture 1 interrupt for a given timer.
12399 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
12400 * @param HRTIMx High Resolution Timer instance
12401 * @param Timer This parameter can be one of the following values:
12402 * @arg @ref LL_HRTIM_TIMER_A
12403 * @arg @ref LL_HRTIM_TIMER_B
12404 * @arg @ref LL_HRTIM_TIMER_C
12405 * @arg @ref LL_HRTIM_TIMER_D
12406 * @arg @ref LL_HRTIM_TIMER_E
12407 * @arg @ref LL_HRTIM_TIMER_F
12408 * @retval None
12409 */
LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12410 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12411 {
12412 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12413 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12414 REG_OFFSET_TAB_TIMER[iTimer]));
12415 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12416 }
12417
12418 /**
12419 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
12420 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
12421 * @param HRTIMx High Resolution Timer instance
12422 * @param Timer This parameter can be one of the following values:
12423 * @arg @ref LL_HRTIM_TIMER_A
12424 * @arg @ref LL_HRTIM_TIMER_B
12425 * @arg @ref LL_HRTIM_TIMER_C
12426 * @arg @ref LL_HRTIM_TIMER_D
12427 * @arg @ref LL_HRTIM_TIMER_E
12428 * @arg @ref LL_HRTIM_TIMER_F
12429 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
12430 */
LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12431 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12432 {
12433 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12434 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12435 REG_OFFSET_TAB_TIMER[iTimer]));
12436
12437 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
12438 }
12439
12440 /**
12441 * @brief Enable the capture 2 interrupt for a given timer.
12442 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
12443 * @param HRTIMx High Resolution Timer instance
12444 * @param Timer This parameter can be one of the following values:
12445 * @arg @ref LL_HRTIM_TIMER_A
12446 * @arg @ref LL_HRTIM_TIMER_B
12447 * @arg @ref LL_HRTIM_TIMER_C
12448 * @arg @ref LL_HRTIM_TIMER_D
12449 * @arg @ref LL_HRTIM_TIMER_E
12450 * @arg @ref LL_HRTIM_TIMER_F
12451 * @retval None
12452 */
LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12453 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12454 {
12455 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12456 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12457 REG_OFFSET_TAB_TIMER[iTimer]));
12458 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12459 }
12460
12461 /**
12462 * @brief Enable the capture 2 interrupt for a given timer.
12463 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
12464 * @param HRTIMx High Resolution Timer instance
12465 * @param Timer This parameter can be one of the following values:
12466 * @arg @ref LL_HRTIM_TIMER_A
12467 * @arg @ref LL_HRTIM_TIMER_B
12468 * @arg @ref LL_HRTIM_TIMER_C
12469 * @arg @ref LL_HRTIM_TIMER_D
12470 * @arg @ref LL_HRTIM_TIMER_E
12471 * @arg @ref LL_HRTIM_TIMER_F
12472 * @retval None
12473 */
LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12474 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12475 {
12476 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12477 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12478 REG_OFFSET_TAB_TIMER[iTimer]));
12479 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12480 }
12481
12482 /**
12483 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
12484 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
12485 * @param HRTIMx High Resolution Timer instance
12486 * @param Timer This parameter can be one of the following values:
12487 * @arg @ref LL_HRTIM_TIMER_A
12488 * @arg @ref LL_HRTIM_TIMER_B
12489 * @arg @ref LL_HRTIM_TIMER_C
12490 * @arg @ref LL_HRTIM_TIMER_D
12491 * @arg @ref LL_HRTIM_TIMER_E
12492 * @arg @ref LL_HRTIM_TIMER_F
12493 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
12494 */
LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12495 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12496 {
12497 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12498 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12499 REG_OFFSET_TAB_TIMER[iTimer]));
12500
12501 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
12502 }
12503
12504 /**
12505 * @brief Enable the output 1 set interrupt for a given timer.
12506 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
12507 * @param HRTIMx High Resolution Timer instance
12508 * @param Timer This parameter can be one of the following values:
12509 * @arg @ref LL_HRTIM_TIMER_A
12510 * @arg @ref LL_HRTIM_TIMER_B
12511 * @arg @ref LL_HRTIM_TIMER_C
12512 * @arg @ref LL_HRTIM_TIMER_D
12513 * @arg @ref LL_HRTIM_TIMER_E
12514 * @arg @ref LL_HRTIM_TIMER_F
12515 * @retval None
12516 */
LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12517 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12518 {
12519 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12520 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12521 REG_OFFSET_TAB_TIMER[iTimer]));
12522 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12523 }
12524
12525 /**
12526 * @brief Disable the output 1 set interrupt for a given timer.
12527 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
12528 * @param HRTIMx High Resolution Timer instance
12529 * @param Timer This parameter can be one of the following values:
12530 * @arg @ref LL_HRTIM_TIMER_A
12531 * @arg @ref LL_HRTIM_TIMER_B
12532 * @arg @ref LL_HRTIM_TIMER_C
12533 * @arg @ref LL_HRTIM_TIMER_D
12534 * @arg @ref LL_HRTIM_TIMER_E
12535 * @arg @ref LL_HRTIM_TIMER_F
12536 * @retval None
12537 */
LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12538 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12539 {
12540 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12541 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12542 REG_OFFSET_TAB_TIMER[iTimer]));
12543 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12544 }
12545
12546 /**
12547 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
12548 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
12549 * @param HRTIMx High Resolution Timer instance
12550 * @param Timer This parameter can be one of the following values:
12551 * @arg @ref LL_HRTIM_TIMER_A
12552 * @arg @ref LL_HRTIM_TIMER_B
12553 * @arg @ref LL_HRTIM_TIMER_C
12554 * @arg @ref LL_HRTIM_TIMER_D
12555 * @arg @ref LL_HRTIM_TIMER_E
12556 * @arg @ref LL_HRTIM_TIMER_F
12557 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12558 */
LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12559 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12560 {
12561 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12562 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12563 REG_OFFSET_TAB_TIMER[iTimer]));
12564
12565 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
12566 }
12567
12568 /**
12569 * @brief Enable the output 1 reset interrupt for a given timer.
12570 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
12571 * @param HRTIMx High Resolution Timer instance
12572 * @param Timer This parameter can be one of the following values:
12573 * @arg @ref LL_HRTIM_TIMER_A
12574 * @arg @ref LL_HRTIM_TIMER_B
12575 * @arg @ref LL_HRTIM_TIMER_C
12576 * @arg @ref LL_HRTIM_TIMER_D
12577 * @arg @ref LL_HRTIM_TIMER_E
12578 * @arg @ref LL_HRTIM_TIMER_F
12579 * @retval None
12580 */
LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12581 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12582 {
12583 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12584 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12585 REG_OFFSET_TAB_TIMER[iTimer]));
12586 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12587 }
12588
12589 /**
12590 * @brief Disable the output 1 reset interrupt for a given timer.
12591 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
12592 * @param HRTIMx High Resolution Timer instance
12593 * @param Timer This parameter can be one of the following values:
12594 * @arg @ref LL_HRTIM_TIMER_A
12595 * @arg @ref LL_HRTIM_TIMER_B
12596 * @arg @ref LL_HRTIM_TIMER_C
12597 * @arg @ref LL_HRTIM_TIMER_D
12598 * @arg @ref LL_HRTIM_TIMER_E
12599 * @arg @ref LL_HRTIM_TIMER_F
12600 * @retval None
12601 */
LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12602 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12603 {
12604 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12605 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12606 REG_OFFSET_TAB_TIMER[iTimer]));
12607 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12608 }
12609
12610 /**
12611 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
12612 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
12613 * @param HRTIMx High Resolution Timer instance
12614 * @param Timer This parameter can be one of the following values:
12615 * @arg @ref LL_HRTIM_TIMER_A
12616 * @arg @ref LL_HRTIM_TIMER_B
12617 * @arg @ref LL_HRTIM_TIMER_C
12618 * @arg @ref LL_HRTIM_TIMER_D
12619 * @arg @ref LL_HRTIM_TIMER_E
12620 * @arg @ref LL_HRTIM_TIMER_F
12621 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12622 */
LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12623 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12624 {
12625 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12626 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12627 REG_OFFSET_TAB_TIMER[iTimer]));
12628
12629 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
12630 }
12631
12632 /**
12633 * @brief Enable the output 2 set interrupt for a given timer.
12634 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
12635 * @param HRTIMx High Resolution Timer instance
12636 * @param Timer This parameter can be one of the following values:
12637 * @arg @ref LL_HRTIM_TIMER_A
12638 * @arg @ref LL_HRTIM_TIMER_B
12639 * @arg @ref LL_HRTIM_TIMER_C
12640 * @arg @ref LL_HRTIM_TIMER_D
12641 * @arg @ref LL_HRTIM_TIMER_E
12642 * @arg @ref LL_HRTIM_TIMER_F
12643 * @retval None
12644 */
LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12645 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12646 {
12647 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12648 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12649 REG_OFFSET_TAB_TIMER[iTimer]));
12650 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12651 }
12652
12653 /**
12654 * @brief Disable the output 2 set interrupt for a given timer.
12655 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
12656 * @param HRTIMx High Resolution Timer instance
12657 * @param Timer This parameter can be one of the following values:
12658 * @arg @ref LL_HRTIM_TIMER_A
12659 * @arg @ref LL_HRTIM_TIMER_B
12660 * @arg @ref LL_HRTIM_TIMER_C
12661 * @arg @ref LL_HRTIM_TIMER_D
12662 * @arg @ref LL_HRTIM_TIMER_E
12663 * @arg @ref LL_HRTIM_TIMER_F
12664 * @retval None
12665 */
LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12666 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12667 {
12668 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12669 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12670 REG_OFFSET_TAB_TIMER[iTimer]));
12671 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12672 }
12673
12674 /**
12675 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
12676 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
12677 * @param HRTIMx High Resolution Timer instance
12678 * @param Timer This parameter can be one of the following values:
12679 * @arg @ref LL_HRTIM_TIMER_A
12680 * @arg @ref LL_HRTIM_TIMER_B
12681 * @arg @ref LL_HRTIM_TIMER_C
12682 * @arg @ref LL_HRTIM_TIMER_D
12683 * @arg @ref LL_HRTIM_TIMER_E
12684 * @arg @ref LL_HRTIM_TIMER_F
12685 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12686 */
LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12687 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12688 {
12689 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12690 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12691 REG_OFFSET_TAB_TIMER[iTimer]));
12692
12693 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
12694 }
12695
12696 /**
12697 * @brief Enable the output 2 reset interrupt for a given timer.
12698 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
12699 * @param HRTIMx High Resolution Timer instance
12700 * @param Timer This parameter can be one of the following values:
12701 * @arg @ref LL_HRTIM_TIMER_A
12702 * @arg @ref LL_HRTIM_TIMER_B
12703 * @arg @ref LL_HRTIM_TIMER_C
12704 * @arg @ref LL_HRTIM_TIMER_D
12705 * @arg @ref LL_HRTIM_TIMER_E
12706 * @arg @ref LL_HRTIM_TIMER_F
12707 * @retval None
12708 */
LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12709 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12710 {
12711 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12712 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12713 REG_OFFSET_TAB_TIMER[iTimer]));
12714 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12715 }
12716
12717 /**
12718 * @brief Disable the output 2 reset interrupt for a given timer.
12719 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12720 * @param HRTIMx High Resolution Timer instance
12721 * @param Timer This parameter can be one of the following values:
12722 * @arg @ref LL_HRTIM_TIMER_A
12723 * @arg @ref LL_HRTIM_TIMER_B
12724 * @arg @ref LL_HRTIM_TIMER_C
12725 * @arg @ref LL_HRTIM_TIMER_D
12726 * @arg @ref LL_HRTIM_TIMER_E
12727 * @arg @ref LL_HRTIM_TIMER_F
12728 * @retval None
12729 */
LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12730 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12731 {
12732 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12733 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12734 REG_OFFSET_TAB_TIMER[iTimer]));
12735 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12736 }
12737
12738 /**
12739 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
12740 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12741 * @param HRTIMx High Resolution Timer instance
12742 * @param Timer This parameter can be one of the following values:
12743 * @arg @ref LL_HRTIM_TIMER_A
12744 * @arg @ref LL_HRTIM_TIMER_B
12745 * @arg @ref LL_HRTIM_TIMER_C
12746 * @arg @ref LL_HRTIM_TIMER_D
12747 * @arg @ref LL_HRTIM_TIMER_E
12748 * @arg @ref LL_HRTIM_TIMER_F
12749 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12750 */
LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12751 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12752 {
12753 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12754 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12755 REG_OFFSET_TAB_TIMER[iTimer]));
12756
12757 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
12758 }
12759
12760 /**
12761 * @brief Enable the reset/roll-over interrupt for a given timer.
12762 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
12763 * @param HRTIMx High Resolution Timer instance
12764 * @param Timer This parameter can be one of the following values:
12765 * @arg @ref LL_HRTIM_TIMER_A
12766 * @arg @ref LL_HRTIM_TIMER_B
12767 * @arg @ref LL_HRTIM_TIMER_C
12768 * @arg @ref LL_HRTIM_TIMER_D
12769 * @arg @ref LL_HRTIM_TIMER_E
12770 * @arg @ref LL_HRTIM_TIMER_F
12771 * @retval None
12772 */
LL_HRTIM_EnableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12773 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12774 {
12775 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12776 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12777 REG_OFFSET_TAB_TIMER[iTimer]));
12778 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12779 }
12780
12781 /**
12782 * @brief Disable the reset/roll-over interrupt for a given timer.
12783 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
12784 * @param HRTIMx High Resolution Timer instance
12785 * @param Timer This parameter can be one of the following values:
12786 * @arg @ref LL_HRTIM_TIMER_A
12787 * @arg @ref LL_HRTIM_TIMER_B
12788 * @arg @ref LL_HRTIM_TIMER_C
12789 * @arg @ref LL_HRTIM_TIMER_D
12790 * @arg @ref LL_HRTIM_TIMER_E
12791 * @arg @ref LL_HRTIM_TIMER_F
12792 * @retval None
12793 */
LL_HRTIM_DisableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12794 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12795 {
12796 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12797 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12798 REG_OFFSET_TAB_TIMER[iTimer]));
12799 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12800 }
12801
12802 /**
12803 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
12804 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
12805 * @param HRTIMx High Resolution Timer instance
12806 * @param Timer This parameter can be one of the following values:
12807 * @arg @ref LL_HRTIM_TIMER_A
12808 * @arg @ref LL_HRTIM_TIMER_B
12809 * @arg @ref LL_HRTIM_TIMER_C
12810 * @arg @ref LL_HRTIM_TIMER_D
12811 * @arg @ref LL_HRTIM_TIMER_E
12812 * @arg @ref LL_HRTIM_TIMER_F
12813 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
12814 */
LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12815 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12816 {
12817 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12818 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12819 REG_OFFSET_TAB_TIMER[iTimer]));
12820
12821 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
12822 }
12823
12824 /**
12825 * @brief Enable the delayed protection interrupt for a given timer.
12826 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
12827 * @param HRTIMx High Resolution Timer instance
12828 * @param Timer This parameter can be one of the following values:
12829 * @arg @ref LL_HRTIM_TIMER_A
12830 * @arg @ref LL_HRTIM_TIMER_B
12831 * @arg @ref LL_HRTIM_TIMER_C
12832 * @arg @ref LL_HRTIM_TIMER_D
12833 * @arg @ref LL_HRTIM_TIMER_E
12834 * @arg @ref LL_HRTIM_TIMER_F
12835 * @retval None
12836 */
LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12837 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12838 {
12839 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12840 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12841 REG_OFFSET_TAB_TIMER[iTimer]));
12842 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12843 }
12844
12845 /**
12846 * @brief Disable the delayed protection interrupt for a given timer.
12847 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
12848 * @param HRTIMx High Resolution Timer instance
12849 * @param Timer This parameter can be one of the following values:
12850 * @arg @ref LL_HRTIM_TIMER_A
12851 * @arg @ref LL_HRTIM_TIMER_B
12852 * @arg @ref LL_HRTIM_TIMER_C
12853 * @arg @ref LL_HRTIM_TIMER_D
12854 * @arg @ref LL_HRTIM_TIMER_E
12855 * @arg @ref LL_HRTIM_TIMER_F
12856 * @retval None
12857 */
LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12858 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12859 {
12860 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12861 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12862 REG_OFFSET_TAB_TIMER[iTimer]));
12863 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12864 }
12865
12866 /**
12867 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
12868 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
12869 * @param HRTIMx High Resolution Timer instance
12870 * @param Timer This parameter can be one of the following values:
12871 * @arg @ref LL_HRTIM_TIMER_A
12872 * @arg @ref LL_HRTIM_TIMER_B
12873 * @arg @ref LL_HRTIM_TIMER_C
12874 * @arg @ref LL_HRTIM_TIMER_D
12875 * @arg @ref LL_HRTIM_TIMER_E
12876 * @arg @ref LL_HRTIM_TIMER_F
12877 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
12878 */
LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12879 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12880 {
12881 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12882 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12883 REG_OFFSET_TAB_TIMER[iTimer]));
12884
12885 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
12886 }
12887
12888 /**
12889 * @}
12890 */
12891
12892 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
12893 * @{
12894 */
12895
12896 /**
12897 * @brief Enable the synchronization input DMA request.
12898 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
12899 * @param HRTIMx High Resolution Timer instance
12900 * @retval None
12901 */
LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12902 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12903 {
12904 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12905 }
12906
12907 /**
12908 * @brief Disable the synchronization input DMA request
12909 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
12910 * @param HRTIMx High Resolution Timer instance
12911 * @retval None
12912 */
LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12913 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12914 {
12915 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12916 }
12917
12918 /**
12919 * @brief Indicate whether the synchronization input DMA request is enabled.
12920 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
12921 * @param HRTIMx High Resolution Timer instance
12922 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
12923 */
LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12924 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12925 {
12926 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
12927 }
12928
12929 /**
12930 * @brief Enable the update DMA request for a given timer.
12931 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
12932 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
12933 * @param HRTIMx High Resolution Timer instance
12934 * @param Timer This parameter can be one of the following values:
12935 * @arg @ref LL_HRTIM_TIMER_MASTER
12936 * @arg @ref LL_HRTIM_TIMER_A
12937 * @arg @ref LL_HRTIM_TIMER_B
12938 * @arg @ref LL_HRTIM_TIMER_C
12939 * @arg @ref LL_HRTIM_TIMER_D
12940 * @arg @ref LL_HRTIM_TIMER_E
12941 * @arg @ref LL_HRTIM_TIMER_F
12942 * @retval None
12943 */
LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12944 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12945 {
12946 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12947 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12948 REG_OFFSET_TAB_TIMER[iTimer]));
12949 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12950 }
12951
12952 /**
12953 * @brief Disable the update DMA request for a given timer.
12954 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
12955 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
12956 * @param HRTIMx High Resolution Timer instance
12957 * @param Timer This parameter can be one of the following values:
12958 * @arg @ref LL_HRTIM_TIMER_MASTER
12959 * @arg @ref LL_HRTIM_TIMER_A
12960 * @arg @ref LL_HRTIM_TIMER_B
12961 * @arg @ref LL_HRTIM_TIMER_C
12962 * @arg @ref LL_HRTIM_TIMER_D
12963 * @arg @ref LL_HRTIM_TIMER_E
12964 * @arg @ref LL_HRTIM_TIMER_F
12965 * @retval None
12966 */
LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12967 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12968 {
12969 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12970 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12971 REG_OFFSET_TAB_TIMER[iTimer]));
12972 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12973 }
12974
12975 /**
12976 * @brief Indicate whether the update DMA request is enabled for a given timer.
12977 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
12978 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
12979 * @param HRTIMx High Resolution Timer instance
12980 * @param Timer This parameter can be one of the following values:
12981 * @arg @ref LL_HRTIM_TIMER_MASTER
12982 * @arg @ref LL_HRTIM_TIMER_A
12983 * @arg @ref LL_HRTIM_TIMER_B
12984 * @arg @ref LL_HRTIM_TIMER_C
12985 * @arg @ref LL_HRTIM_TIMER_D
12986 * @arg @ref LL_HRTIM_TIMER_E
12987 * @arg @ref LL_HRTIM_TIMER_F
12988 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12989 */
LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12990 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12991 {
12992 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12993 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12994 REG_OFFSET_TAB_TIMER[iTimer]));
12995
12996 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
12997 }
12998
12999 /**
13000 * @brief Enable the repetition DMA request for a given timer.
13001 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
13002 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
13003 * @param HRTIMx High Resolution Timer instance
13004 * @param Timer This parameter can be one of the following values:
13005 * @arg @ref LL_HRTIM_TIMER_MASTER
13006 * @arg @ref LL_HRTIM_TIMER_A
13007 * @arg @ref LL_HRTIM_TIMER_B
13008 * @arg @ref LL_HRTIM_TIMER_C
13009 * @arg @ref LL_HRTIM_TIMER_D
13010 * @arg @ref LL_HRTIM_TIMER_E
13011 * @arg @ref LL_HRTIM_TIMER_F
13012 * @retval None
13013 */
LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13014 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13015 {
13016 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13017 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13018 REG_OFFSET_TAB_TIMER[iTimer]));
13019 SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
13020 }
13021
13022 /**
13023 * @brief Disable the repetition DMA request for a given timer.
13024 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
13025 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
13026 * @param HRTIMx High Resolution Timer instance
13027 * @param Timer This parameter can be one of the following values:
13028 * @arg @ref LL_HRTIM_TIMER_MASTER
13029 * @arg @ref LL_HRTIM_TIMER_A
13030 * @arg @ref LL_HRTIM_TIMER_B
13031 * @arg @ref LL_HRTIM_TIMER_C
13032 * @arg @ref LL_HRTIM_TIMER_D
13033 * @arg @ref LL_HRTIM_TIMER_E
13034 * @arg @ref LL_HRTIM_TIMER_F
13035 * @retval None
13036 */
LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13037 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13038 {
13039 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13040 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13041 REG_OFFSET_TAB_TIMER[iTimer]));
13042 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
13043 }
13044
13045 /**
13046 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
13047 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
13048 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
13049 * @param HRTIMx High Resolution Timer instance
13050 * @param Timer This parameter can be one of the following values:
13051 * @arg @ref LL_HRTIM_TIMER_MASTER
13052 * @arg @ref LL_HRTIM_TIMER_A
13053 * @arg @ref LL_HRTIM_TIMER_B
13054 * @arg @ref LL_HRTIM_TIMER_C
13055 * @arg @ref LL_HRTIM_TIMER_D
13056 * @arg @ref LL_HRTIM_TIMER_E
13057 * @arg @ref LL_HRTIM_TIMER_F
13058 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13059 */
LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13060 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13061 {
13062 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13063 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13064 REG_OFFSET_TAB_TIMER[iTimer]));
13065
13066 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
13067 }
13068
13069 /**
13070 * @brief Enable the compare 1 DMA request for a given timer.
13071 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
13072 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
13073 * @param HRTIMx High Resolution Timer instance
13074 * @param Timer This parameter can be one of the following values:
13075 * @arg @ref LL_HRTIM_TIMER_MASTER
13076 * @arg @ref LL_HRTIM_TIMER_A
13077 * @arg @ref LL_HRTIM_TIMER_B
13078 * @arg @ref LL_HRTIM_TIMER_C
13079 * @arg @ref LL_HRTIM_TIMER_D
13080 * @arg @ref LL_HRTIM_TIMER_E
13081 * @arg @ref LL_HRTIM_TIMER_F
13082 * @retval None
13083 */
LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13084 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13085 {
13086 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13087 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13088 REG_OFFSET_TAB_TIMER[iTimer]));
13089 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13090 }
13091
13092 /**
13093 * @brief Disable the compare 1 DMA request for a given timer.
13094 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
13095 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
13096 * @param HRTIMx High Resolution Timer instance
13097 * @param Timer This parameter can be one of the following values:
13098 * @arg @ref LL_HRTIM_TIMER_MASTER
13099 * @arg @ref LL_HRTIM_TIMER_A
13100 * @arg @ref LL_HRTIM_TIMER_B
13101 * @arg @ref LL_HRTIM_TIMER_C
13102 * @arg @ref LL_HRTIM_TIMER_D
13103 * @arg @ref LL_HRTIM_TIMER_E
13104 * @arg @ref LL_HRTIM_TIMER_F
13105 * @retval None
13106 */
LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13107 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13108 {
13109 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13110 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13111 REG_OFFSET_TAB_TIMER[iTimer]));
13112 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13113 }
13114
13115 /**
13116 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
13117 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
13118 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
13119 * @param HRTIMx High Resolution Timer instance
13120 * @param Timer This parameter can be one of the following values:
13121 * @arg @ref LL_HRTIM_TIMER_MASTER
13122 * @arg @ref LL_HRTIM_TIMER_A
13123 * @arg @ref LL_HRTIM_TIMER_B
13124 * @arg @ref LL_HRTIM_TIMER_C
13125 * @arg @ref LL_HRTIM_TIMER_D
13126 * @arg @ref LL_HRTIM_TIMER_E
13127 * @arg @ref LL_HRTIM_TIMER_F
13128 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13129 */
LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13130 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13131 {
13132 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13133 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13134 REG_OFFSET_TAB_TIMER[iTimer]));
13135
13136 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
13137 }
13138
13139 /**
13140 * @brief Enable the compare 2 DMA request for a given timer.
13141 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
13142 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
13143 * @param HRTIMx High Resolution Timer instance
13144 * @param Timer This parameter can be one of the following values:
13145 * @arg @ref LL_HRTIM_TIMER_MASTER
13146 * @arg @ref LL_HRTIM_TIMER_A
13147 * @arg @ref LL_HRTIM_TIMER_B
13148 * @arg @ref LL_HRTIM_TIMER_C
13149 * @arg @ref LL_HRTIM_TIMER_D
13150 * @arg @ref LL_HRTIM_TIMER_E
13151 * @arg @ref LL_HRTIM_TIMER_F
13152 * @retval None
13153 */
LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13154 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13155 {
13156 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13157 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13158 REG_OFFSET_TAB_TIMER[iTimer]));
13159 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13160 }
13161
13162 /**
13163 * @brief Disable the compare 2 DMA request for a given timer.
13164 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
13165 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
13166 * @param HRTIMx High Resolution Timer instance
13167 * @param Timer This parameter can be one of the following values:
13168 * @arg @ref LL_HRTIM_TIMER_MASTER
13169 * @arg @ref LL_HRTIM_TIMER_A
13170 * @arg @ref LL_HRTIM_TIMER_B
13171 * @arg @ref LL_HRTIM_TIMER_C
13172 * @arg @ref LL_HRTIM_TIMER_D
13173 * @arg @ref LL_HRTIM_TIMER_E
13174 * @arg @ref LL_HRTIM_TIMER_F
13175 * @retval None
13176 */
LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13177 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13178 {
13179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13180 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13181 REG_OFFSET_TAB_TIMER[iTimer]));
13182 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13183 }
13184
13185 /**
13186 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
13187 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
13188 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
13189 * @param HRTIMx High Resolution Timer instance
13190 * @param Timer This parameter can be one of the following values:
13191 * @arg @ref LL_HRTIM_TIMER_MASTER
13192 * @arg @ref LL_HRTIM_TIMER_A
13193 * @arg @ref LL_HRTIM_TIMER_B
13194 * @arg @ref LL_HRTIM_TIMER_C
13195 * @arg @ref LL_HRTIM_TIMER_D
13196 * @arg @ref LL_HRTIM_TIMER_E
13197 * @arg @ref LL_HRTIM_TIMER_F
13198 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13199 */
LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13200 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13201 {
13202 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13203 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13204 REG_OFFSET_TAB_TIMER[iTimer]));
13205
13206 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
13207 }
13208
13209 /**
13210 * @brief Enable the compare 3 DMA request for a given timer.
13211 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
13212 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
13213 * @param HRTIMx High Resolution Timer instance
13214 * @param Timer This parameter can be one of the following values:
13215 * @arg @ref LL_HRTIM_TIMER_MASTER
13216 * @arg @ref LL_HRTIM_TIMER_A
13217 * @arg @ref LL_HRTIM_TIMER_B
13218 * @arg @ref LL_HRTIM_TIMER_C
13219 * @arg @ref LL_HRTIM_TIMER_D
13220 * @arg @ref LL_HRTIM_TIMER_E
13221 * @arg @ref LL_HRTIM_TIMER_F
13222 * @retval None
13223 */
LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13224 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13225 {
13226 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13227 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13228 REG_OFFSET_TAB_TIMER[iTimer]));
13229 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13230 }
13231
13232 /**
13233 * @brief Disable the compare 3 DMA request for a given timer.
13234 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
13235 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
13236 * @param HRTIMx High Resolution Timer instance
13237 * @param Timer This parameter can be one of the following values:
13238 * @arg @ref LL_HRTIM_TIMER_MASTER
13239 * @arg @ref LL_HRTIM_TIMER_A
13240 * @arg @ref LL_HRTIM_TIMER_B
13241 * @arg @ref LL_HRTIM_TIMER_C
13242 * @arg @ref LL_HRTIM_TIMER_D
13243 * @arg @ref LL_HRTIM_TIMER_E
13244 * @arg @ref LL_HRTIM_TIMER_F
13245 * @retval None
13246 */
LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13247 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13248 {
13249 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13250 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13251 REG_OFFSET_TAB_TIMER[iTimer]));
13252 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13253 }
13254
13255 /**
13256 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
13257 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
13258 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
13259 * @param HRTIMx High Resolution Timer instance
13260 * @param Timer This parameter can be one of the following values:
13261 * @arg @ref LL_HRTIM_TIMER_MASTER
13262 * @arg @ref LL_HRTIM_TIMER_A
13263 * @arg @ref LL_HRTIM_TIMER_B
13264 * @arg @ref LL_HRTIM_TIMER_C
13265 * @arg @ref LL_HRTIM_TIMER_D
13266 * @arg @ref LL_HRTIM_TIMER_E
13267 * @arg @ref LL_HRTIM_TIMER_F
13268 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13269 */
LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13270 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13271 {
13272 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13273 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13274 REG_OFFSET_TAB_TIMER[iTimer]));
13275
13276 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
13277 }
13278
13279 /**
13280 * @brief Enable the compare 4 DMA request for a given timer.
13281 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
13282 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
13283 * @param HRTIMx High Resolution Timer instance
13284 * @param Timer This parameter can be one of the following values:
13285 * @arg @ref LL_HRTIM_TIMER_MASTER
13286 * @arg @ref LL_HRTIM_TIMER_A
13287 * @arg @ref LL_HRTIM_TIMER_B
13288 * @arg @ref LL_HRTIM_TIMER_C
13289 * @arg @ref LL_HRTIM_TIMER_D
13290 * @arg @ref LL_HRTIM_TIMER_E
13291 * @arg @ref LL_HRTIM_TIMER_F
13292 * @retval None
13293 */
LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13294 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13295 {
13296 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13297 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13298 REG_OFFSET_TAB_TIMER[iTimer]));
13299 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13300 }
13301
13302 /**
13303 * @brief Disable the compare 4 DMA request for a given timer.
13304 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
13305 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
13306 * @param HRTIMx High Resolution Timer instance
13307 * @param Timer This parameter can be one of the following values:
13308 * @arg @ref LL_HRTIM_TIMER_MASTER
13309 * @arg @ref LL_HRTIM_TIMER_A
13310 * @arg @ref LL_HRTIM_TIMER_B
13311 * @arg @ref LL_HRTIM_TIMER_C
13312 * @arg @ref LL_HRTIM_TIMER_D
13313 * @arg @ref LL_HRTIM_TIMER_E
13314 * @arg @ref LL_HRTIM_TIMER_F
13315 * @retval None
13316 */
LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13317 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13318 {
13319 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13320 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13321 REG_OFFSET_TAB_TIMER[iTimer]));
13322 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13323 }
13324
13325 /**
13326 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
13327 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
13328 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
13329 * @param HRTIMx High Resolution Timer instance
13330 * @param Timer This parameter can be one of the following values:
13331 * @arg @ref LL_HRTIM_TIMER_MASTER
13332 * @arg @ref LL_HRTIM_TIMER_A
13333 * @arg @ref LL_HRTIM_TIMER_B
13334 * @arg @ref LL_HRTIM_TIMER_C
13335 * @arg @ref LL_HRTIM_TIMER_D
13336 * @arg @ref LL_HRTIM_TIMER_E
13337 * @arg @ref LL_HRTIM_TIMER_F
13338 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13339 */
LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13340 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13341 {
13342 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13343 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13344 REG_OFFSET_TAB_TIMER[iTimer]));
13345
13346 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
13347 }
13348
13349 /**
13350 * @brief Enable the capture 1 DMA request for a given timer.
13351 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
13352 * @param HRTIMx High Resolution Timer instance
13353 * @param Timer This parameter can be one of the following values:
13354 * @arg @ref LL_HRTIM_TIMER_A
13355 * @arg @ref LL_HRTIM_TIMER_B
13356 * @arg @ref LL_HRTIM_TIMER_C
13357 * @arg @ref LL_HRTIM_TIMER_D
13358 * @arg @ref LL_HRTIM_TIMER_E
13359 * @arg @ref LL_HRTIM_TIMER_F
13360 * @retval None
13361 */
LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13362 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13363 {
13364 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13365 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13366 REG_OFFSET_TAB_TIMER[iTimer]));
13367 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13368 }
13369
13370 /**
13371 * @brief Disable the capture 1 DMA request for a given timer.
13372 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
13373 * @param HRTIMx High Resolution Timer instance
13374 * @param Timer This parameter can be one of the following values:
13375 * @arg @ref LL_HRTIM_TIMER_A
13376 * @arg @ref LL_HRTIM_TIMER_B
13377 * @arg @ref LL_HRTIM_TIMER_C
13378 * @arg @ref LL_HRTIM_TIMER_D
13379 * @arg @ref LL_HRTIM_TIMER_E
13380 * @arg @ref LL_HRTIM_TIMER_F
13381 * @retval None
13382 */
LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13383 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13384 {
13385 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13386 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13387 REG_OFFSET_TAB_TIMER[iTimer]));
13388 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13389 }
13390
13391 /**
13392 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
13393 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
13394 * @param HRTIMx High Resolution Timer instance
13395 * @param Timer This parameter can be one of the following values:
13396 * @arg @ref LL_HRTIM_TIMER_A
13397 * @arg @ref LL_HRTIM_TIMER_B
13398 * @arg @ref LL_HRTIM_TIMER_C
13399 * @arg @ref LL_HRTIM_TIMER_D
13400 * @arg @ref LL_HRTIM_TIMER_E
13401 * @arg @ref LL_HRTIM_TIMER_F
13402 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
13403 */
LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13404 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13405 {
13406 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13407 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13408 REG_OFFSET_TAB_TIMER[iTimer]));
13409
13410 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
13411 }
13412
13413 /**
13414 * @brief Enable the capture 2 DMA request for a given timer.
13415 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
13416 * @param HRTIMx High Resolution Timer instance
13417 * @param Timer This parameter can be one of the following values:
13418 * @arg @ref LL_HRTIM_TIMER_A
13419 * @arg @ref LL_HRTIM_TIMER_B
13420 * @arg @ref LL_HRTIM_TIMER_C
13421 * @arg @ref LL_HRTIM_TIMER_D
13422 * @arg @ref LL_HRTIM_TIMER_E
13423 * @arg @ref LL_HRTIM_TIMER_F
13424 * @retval None
13425 */
LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13426 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13427 {
13428 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13429 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13430 REG_OFFSET_TAB_TIMER[iTimer]));
13431 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13432 }
13433
13434 /**
13435 * @brief Disable the capture 2 DMA request for a given timer.
13436 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
13437 * @param HRTIMx High Resolution Timer instance
13438 * @param Timer This parameter can be one of the following values:
13439 * @arg @ref LL_HRTIM_TIMER_A
13440 * @arg @ref LL_HRTIM_TIMER_B
13441 * @arg @ref LL_HRTIM_TIMER_C
13442 * @arg @ref LL_HRTIM_TIMER_D
13443 * @arg @ref LL_HRTIM_TIMER_E
13444 * @arg @ref LL_HRTIM_TIMER_F
13445 * @retval None
13446 */
LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13447 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13448 {
13449 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13450 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13451 REG_OFFSET_TAB_TIMER[iTimer]));
13452 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13453 }
13454
13455 /**
13456 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
13457 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
13458 * @param HRTIMx High Resolution Timer instance
13459 * @param Timer This parameter can be one of the following values:
13460 * @arg @ref LL_HRTIM_TIMER_A
13461 * @arg @ref LL_HRTIM_TIMER_B
13462 * @arg @ref LL_HRTIM_TIMER_C
13463 * @arg @ref LL_HRTIM_TIMER_D
13464 * @arg @ref LL_HRTIM_TIMER_E
13465 * @arg @ref LL_HRTIM_TIMER_F
13466 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
13467 */
LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13468 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13469 {
13470 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13471 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13472 REG_OFFSET_TAB_TIMER[iTimer]));
13473
13474 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
13475 }
13476
13477 /**
13478 * @brief Enable the output 1 set DMA request for a given timer.
13479 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
13480 * @param HRTIMx High Resolution Timer instance
13481 * @param Timer This parameter can be one of the following values:
13482 * @arg @ref LL_HRTIM_TIMER_A
13483 * @arg @ref LL_HRTIM_TIMER_B
13484 * @arg @ref LL_HRTIM_TIMER_C
13485 * @arg @ref LL_HRTIM_TIMER_D
13486 * @arg @ref LL_HRTIM_TIMER_E
13487 * @arg @ref LL_HRTIM_TIMER_F
13488 * @retval None
13489 */
LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13490 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13491 {
13492 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13493 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13494 REG_OFFSET_TAB_TIMER[iTimer]));
13495 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13496 }
13497
13498 /**
13499 * @brief Disable the output 1 set DMA request for a given timer.
13500 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
13501 * @param HRTIMx High Resolution Timer instance
13502 * @param Timer This parameter can be one of the following values:
13503 * @arg @ref LL_HRTIM_TIMER_A
13504 * @arg @ref LL_HRTIM_TIMER_B
13505 * @arg @ref LL_HRTIM_TIMER_C
13506 * @arg @ref LL_HRTIM_TIMER_D
13507 * @arg @ref LL_HRTIM_TIMER_E
13508 * @arg @ref LL_HRTIM_TIMER_F
13509 * @retval None
13510 */
LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13511 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13512 {
13513 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13514 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13515 REG_OFFSET_TAB_TIMER[iTimer]));
13516 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13517 }
13518
13519 /**
13520 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
13521 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
13522 * @param HRTIMx High Resolution Timer instance
13523 * @param Timer This parameter can be one of the following values:
13524 * @arg @ref LL_HRTIM_TIMER_A
13525 * @arg @ref LL_HRTIM_TIMER_B
13526 * @arg @ref LL_HRTIM_TIMER_C
13527 * @arg @ref LL_HRTIM_TIMER_D
13528 * @arg @ref LL_HRTIM_TIMER_E
13529 * @arg @ref LL_HRTIM_TIMER_F
13530 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13531 */
LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13532 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13533 {
13534 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13535 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13536 REG_OFFSET_TAB_TIMER[iTimer]));
13537
13538 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
13539 }
13540
13541 /**
13542 * @brief Enable the output 1 reset DMA request for a given timer.
13543 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
13544 * @param HRTIMx High Resolution Timer instance
13545 * @param Timer This parameter can be one of the following values:
13546 * @arg @ref LL_HRTIM_TIMER_A
13547 * @arg @ref LL_HRTIM_TIMER_B
13548 * @arg @ref LL_HRTIM_TIMER_C
13549 * @arg @ref LL_HRTIM_TIMER_D
13550 * @arg @ref LL_HRTIM_TIMER_E
13551 * @arg @ref LL_HRTIM_TIMER_F
13552 * @retval None
13553 */
LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13554 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13555 {
13556 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13557 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13558 REG_OFFSET_TAB_TIMER[iTimer]));
13559 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13560 }
13561
13562 /**
13563 * @brief Disable the output 1 reset DMA request for a given timer.
13564 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
13565 * @param HRTIMx High Resolution Timer instance
13566 * @param Timer This parameter can be one of the following values:
13567 * @arg @ref LL_HRTIM_TIMER_A
13568 * @arg @ref LL_HRTIM_TIMER_B
13569 * @arg @ref LL_HRTIM_TIMER_C
13570 * @arg @ref LL_HRTIM_TIMER_D
13571 * @arg @ref LL_HRTIM_TIMER_E
13572 * @arg @ref LL_HRTIM_TIMER_F
13573 * @retval None
13574 */
LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13575 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13576 {
13577 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13578 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13579 REG_OFFSET_TAB_TIMER[iTimer]));
13580 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13581 }
13582
13583 /**
13584 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
13585 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
13586 * @param HRTIMx High Resolution Timer instance
13587 * @param Timer This parameter can be one of the following values:
13588 * @arg @ref LL_HRTIM_TIMER_A
13589 * @arg @ref LL_HRTIM_TIMER_B
13590 * @arg @ref LL_HRTIM_TIMER_C
13591 * @arg @ref LL_HRTIM_TIMER_D
13592 * @arg @ref LL_HRTIM_TIMER_E
13593 * @arg @ref LL_HRTIM_TIMER_F
13594 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13595 */
LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13596 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13597 {
13598 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13599 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13600 REG_OFFSET_TAB_TIMER[iTimer]));
13601
13602 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
13603 }
13604
13605 /**
13606 * @brief Enable the output 2 set DMA request for a given timer.
13607 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
13608 * @param HRTIMx High Resolution Timer instance
13609 * @param Timer This parameter can be one of the following values:
13610 * @arg @ref LL_HRTIM_TIMER_A
13611 * @arg @ref LL_HRTIM_TIMER_B
13612 * @arg @ref LL_HRTIM_TIMER_C
13613 * @arg @ref LL_HRTIM_TIMER_D
13614 * @arg @ref LL_HRTIM_TIMER_E
13615 * @arg @ref LL_HRTIM_TIMER_F
13616 * @retval None
13617 */
LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13618 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13619 {
13620 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13621 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13622 REG_OFFSET_TAB_TIMER[iTimer]));
13623 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13624 }
13625
13626 /**
13627 * @brief Disable the output 2 set DMA request for a given timer.
13628 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
13629 * @param HRTIMx High Resolution Timer instance
13630 * @param Timer This parameter can be one of the following values:
13631 * @arg @ref LL_HRTIM_TIMER_A
13632 * @arg @ref LL_HRTIM_TIMER_B
13633 * @arg @ref LL_HRTIM_TIMER_C
13634 * @arg @ref LL_HRTIM_TIMER_D
13635 * @arg @ref LL_HRTIM_TIMER_E
13636 * @arg @ref LL_HRTIM_TIMER_F
13637 * @retval None
13638 */
LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13639 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13640 {
13641 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13642 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13643 REG_OFFSET_TAB_TIMER[iTimer]));
13644 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13645 }
13646
13647 /**
13648 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
13649 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
13650 * @param HRTIMx High Resolution Timer instance
13651 * @param Timer This parameter can be one of the following values:
13652 * @arg @ref LL_HRTIM_TIMER_A
13653 * @arg @ref LL_HRTIM_TIMER_B
13654 * @arg @ref LL_HRTIM_TIMER_C
13655 * @arg @ref LL_HRTIM_TIMER_D
13656 * @arg @ref LL_HRTIM_TIMER_E
13657 * @arg @ref LL_HRTIM_TIMER_F
13658 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13659 */
LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13660 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13661 {
13662 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13663 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13664 REG_OFFSET_TAB_TIMER[iTimer]));
13665
13666 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
13667 }
13668
13669 /**
13670 * @brief Enable the output 2 reset DMA request for a given timer.
13671 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
13672 * @param HRTIMx High Resolution Timer instance
13673 * @param Timer This parameter can be one of the following values:
13674 * @arg @ref LL_HRTIM_TIMER_A
13675 * @arg @ref LL_HRTIM_TIMER_B
13676 * @arg @ref LL_HRTIM_TIMER_C
13677 * @arg @ref LL_HRTIM_TIMER_D
13678 * @arg @ref LL_HRTIM_TIMER_E
13679 * @arg @ref LL_HRTIM_TIMER_F
13680 * @retval None
13681 */
LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13682 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13683 {
13684 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13685 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13686 REG_OFFSET_TAB_TIMER[iTimer]));
13687 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13688 }
13689
13690 /**
13691 * @brief Disable the output 2 reset DMA request for a given timer.
13692 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
13693 * @param HRTIMx High Resolution Timer instance
13694 * @param Timer This parameter can be one of the following values:
13695 * @arg @ref LL_HRTIM_TIMER_A
13696 * @arg @ref LL_HRTIM_TIMER_B
13697 * @arg @ref LL_HRTIM_TIMER_C
13698 * @arg @ref LL_HRTIM_TIMER_D
13699 * @arg @ref LL_HRTIM_TIMER_E
13700 * @arg @ref LL_HRTIM_TIMER_F
13701 * @retval None
13702 */
LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13703 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13704 {
13705 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13706 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13707 REG_OFFSET_TAB_TIMER[iTimer]));
13708 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13709 }
13710
13711 /**
13712 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
13713 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
13714 * @param HRTIMx High Resolution Timer instance
13715 * @param Timer This parameter can be one of the following values:
13716 * @arg @ref LL_HRTIM_TIMER_A
13717 * @arg @ref LL_HRTIM_TIMER_B
13718 * @arg @ref LL_HRTIM_TIMER_C
13719 * @arg @ref LL_HRTIM_TIMER_D
13720 * @arg @ref LL_HRTIM_TIMER_E
13721 * @arg @ref LL_HRTIM_TIMER_F
13722 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13723 */
LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13724 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13725 {
13726 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13727 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13728 REG_OFFSET_TAB_TIMER[iTimer]));
13729
13730 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
13731 }
13732
13733 /**
13734 * @brief Enable the reset/roll-over DMA request for a given timer.
13735 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
13736 * @param HRTIMx High Resolution Timer instance
13737 * @param Timer This parameter can be one of the following values:
13738 * @arg @ref LL_HRTIM_TIMER_A
13739 * @arg @ref LL_HRTIM_TIMER_B
13740 * @arg @ref LL_HRTIM_TIMER_C
13741 * @arg @ref LL_HRTIM_TIMER_D
13742 * @arg @ref LL_HRTIM_TIMER_E
13743 * @arg @ref LL_HRTIM_TIMER_F
13744 * @retval None
13745 */
LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13746 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13747 {
13748 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13749 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13750 REG_OFFSET_TAB_TIMER[iTimer]));
13751 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13752 }
13753
13754 /**
13755 * @brief Disable the reset/roll-over DMA request for a given timer.
13756 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
13757 * @param HRTIMx High Resolution Timer instance
13758 * @param Timer This parameter can be one of the following values:
13759 * @arg @ref LL_HRTIM_TIMER_A
13760 * @arg @ref LL_HRTIM_TIMER_B
13761 * @arg @ref LL_HRTIM_TIMER_C
13762 * @arg @ref LL_HRTIM_TIMER_D
13763 * @arg @ref LL_HRTIM_TIMER_E
13764 * @arg @ref LL_HRTIM_TIMER_F
13765 * @retval None
13766 */
LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13767 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13768 {
13769 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13770 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13771 REG_OFFSET_TAB_TIMER[iTimer]));
13772 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13773 }
13774
13775 /**
13776 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
13777 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
13778 * @param HRTIMx High Resolution Timer instance
13779 * @param Timer This parameter can be one of the following values:
13780 * @arg @ref LL_HRTIM_TIMER_A
13781 * @arg @ref LL_HRTIM_TIMER_B
13782 * @arg @ref LL_HRTIM_TIMER_C
13783 * @arg @ref LL_HRTIM_TIMER_D
13784 * @arg @ref LL_HRTIM_TIMER_E
13785 * @arg @ref LL_HRTIM_TIMER_F
13786 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
13787 */
LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13788 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13789 {
13790 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13791 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13792 REG_OFFSET_TAB_TIMER[iTimer]));
13793
13794 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
13795 }
13796
13797 /**
13798 * @brief Enable the delayed protection DMA request for a given timer.
13799 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
13800 * @param HRTIMx High Resolution Timer instance
13801 * @param Timer This parameter can be one of the following values:
13802 * @arg @ref LL_HRTIM_TIMER_A
13803 * @arg @ref LL_HRTIM_TIMER_B
13804 * @arg @ref LL_HRTIM_TIMER_C
13805 * @arg @ref LL_HRTIM_TIMER_D
13806 * @arg @ref LL_HRTIM_TIMER_E
13807 * @arg @ref LL_HRTIM_TIMER_F
13808 * @retval None
13809 */
LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13810 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13811 {
13812 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13813 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13814 REG_OFFSET_TAB_TIMER[iTimer]));
13815 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13816 }
13817
13818 /**
13819 * @brief Disable the delayed protection DMA request for a given timer.
13820 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
13821 * @param HRTIMx High Resolution Timer instance
13822 * @param Timer This parameter can be one of the following values:
13823 * @arg @ref LL_HRTIM_TIMER_A
13824 * @arg @ref LL_HRTIM_TIMER_B
13825 * @arg @ref LL_HRTIM_TIMER_C
13826 * @arg @ref LL_HRTIM_TIMER_D
13827 * @arg @ref LL_HRTIM_TIMER_E
13828 * @arg @ref LL_HRTIM_TIMER_F
13829 * @retval None
13830 */
LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13831 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13832 {
13833 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13834 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13835 REG_OFFSET_TAB_TIMER[iTimer]));
13836 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13837 }
13838
13839 /**
13840 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
13841 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
13842 * @param HRTIMx High Resolution Timer instance
13843 * @param Timer This parameter can be one of the following values:
13844 * @arg @ref LL_HRTIM_TIMER_A
13845 * @arg @ref LL_HRTIM_TIMER_B
13846 * @arg @ref LL_HRTIM_TIMER_C
13847 * @arg @ref LL_HRTIM_TIMER_D
13848 * @arg @ref LL_HRTIM_TIMER_E
13849 * @arg @ref LL_HRTIM_TIMER_F
13850 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
13851 */
LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13852 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13853 {
13854 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13855 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13856 REG_OFFSET_TAB_TIMER[iTimer]));
13857
13858 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
13859 }
13860
13861 /**
13862 * @}
13863 */
13864
13865 #if defined(USE_FULL_LL_DRIVER)
13866 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
13867 * @{
13868 */
13869 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
13870 /**
13871 * @}
13872 */
13873 #endif /* USE_FULL_LL_DRIVER */
13874
13875 /**
13876 * @}
13877 */
13878
13879 /**
13880 * @}
13881 */
13882
13883 #endif /* HRTIM1 */
13884
13885 /**
13886 * @}
13887 */
13888
13889 #ifdef __cplusplus
13890 }
13891 #endif
13892
13893 #endif /* STM32G4xx_LL_HRTIM_H */
13894
13895 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
13896
13897
13898
