1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32G0xx_HAL_DMA_H 22 #define STM32G0xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32g0xx_hal_def.h" 30 #include "stm32g0xx_ll_dma.h" 31 32 /** @addtogroup STM32G0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup DMA 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Request; /*!< Specifies the request selected for the specified channel. 51 This parameter can be a value of @ref DMA_request */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Channel */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 } DMA_InitTypeDef; 77 78 /** 79 * @brief HAL DMA State structures definition 80 */ 81 typedef enum 82 { 83 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 84 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 85 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 86 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 87 } HAL_DMA_StateTypeDef; 88 89 /** 90 * @brief HAL DMA Error Code structure definition 91 */ 92 typedef enum 93 { 94 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 95 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 96 } HAL_DMA_LevelCompleteTypeDef; 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 106 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 107 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 108 109 } HAL_DMA_CallbackIDTypeDef; 110 111 /** 112 * @brief DMA handle Structure definition 113 */ 114 typedef struct __DMA_HandleTypeDef 115 { 116 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 117 118 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 119 120 HAL_LockTypeDef Lock; /*!< DMA locking object */ 121 122 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 123 124 void *Parent; /*!< Parent object state */ 125 126 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 127 128 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 129 130 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 131 132 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 133 134 __IO uint32_t ErrorCode; /*!< DMA Error code */ 135 136 #if defined(DMA2) 137 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 138 139 #endif /* DMA2 */ 140 uint32_t ChannelIndex; /*!< DMA Channel Index */ 141 142 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 143 144 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 145 146 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 147 148 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 149 150 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 151 152 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 153 } DMA_HandleTypeDef; 154 /** 155 * @} 156 */ 157 158 /* Exported constants --------------------------------------------------------*/ 159 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants 161 * @{ 162 */ 163 164 /** @defgroup DMA_Error_Code DMA Error Code 165 * @{ 166 */ 167 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 168 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 169 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 170 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 171 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 172 #define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ 173 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 174 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 175 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 176 177 /** 178 * @} 179 */ 180 181 /** @defgroup DMA_request DMA request 182 * @{ 183 */ 184 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 185 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 186 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 187 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 188 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 189 #define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ 190 #if defined(AES) 191 #define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ 192 #define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ 193 #endif /* AES */ 194 #if defined(DAC1) 195 #define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */ 196 #define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */ 197 #endif /* DAC1 */ 198 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 199 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 200 #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ 201 #define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ 202 #if defined(LPUART1) 203 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ 204 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ 205 #endif /* LPUART1 */ 206 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 207 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 208 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 209 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 210 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 211 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 212 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 213 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 214 #define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */ 215 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 216 #if defined(TIM2) 217 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 218 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 219 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 220 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 221 #define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ 222 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 223 #endif /* TIM2 */ 224 #define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ 225 #define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ 226 #define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ 227 #define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */ 228 #define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */ 229 #define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ 230 #if defined(TIM6) 231 #define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ 232 #endif /* TIM6 */ 233 #if defined(TIM7) 234 #define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ 235 #endif /* TIM7 */ 236 #if defined(TIM15) 237 #define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ 238 #define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ 239 #define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ 240 #define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ 241 #endif /* TIM15 */ 242 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 243 #define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ 244 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 245 #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 246 #define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM /*!< DMAMUX TIM17 COM request */ 247 #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 248 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 249 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 250 #define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ 251 #define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ 252 #if defined(USART3) 253 #define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ 254 #define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ 255 #endif /* USART3 */ 256 #if defined(USART4) 257 #define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ 258 #define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ 259 #endif /* USART4 */ 260 #if defined(UCPD1) 261 #define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */ 262 #define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */ 263 #endif/* UCPD1 */ 264 #if defined(UCPD2) 265 #define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */ 266 #define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */ 267 #endif /* UCPD2 */ 268 269 #if defined(I2C3) 270 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 271 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 272 #endif /* I2C3 */ 273 274 #if defined(LPUART2) 275 #define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ 276 #define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ 277 #endif /* LPUART2 */ 278 279 #if defined(SPI3) 280 #define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ 281 #define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ 282 #endif /* SPI3 */ 283 284 #if defined(TIM4) 285 #define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */ 286 #define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2 /*!< DMAMUX TIM4 CH2 request */ 287 #define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3 /*!< DMAMUX TIM4 CH3 request */ 288 #define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */ 289 #define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */ 290 #define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */ 291 #endif /* TIM4 */ 292 293 #if defined(USART5) 294 #define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */ 295 #define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */ 296 #endif /* USART5 */ 297 298 #if defined(USART6) 299 #define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */ 300 #define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */ 301 #endif /* USART6 */ 302 303 304 #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 310 * @{ 311 */ 312 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 313 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 314 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 315 316 /** 317 * @} 318 */ 319 320 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 321 * @{ 322 */ 323 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 324 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 330 * @{ 331 */ 332 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 333 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 339 * @{ 340 */ 341 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 342 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 343 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup DMA_Memory_data_size DMA Memory data size 349 * @{ 350 */ 351 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 352 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 353 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup DMA_mode DMA mode 359 * @{ 360 */ 361 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 362 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup DMA_Priority_level DMA Priority level 368 * @{ 369 */ 370 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 371 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 372 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 373 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 374 /** 375 * @} 376 */ 377 378 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 379 * @{ 380 */ 381 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ 382 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ 383 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ 384 /** 385 * @} 386 */ 387 388 /** @defgroup DMA_flag_definitions DMA flag definitions 389 * @{ 390 */ 391 392 #define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ 393 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ 394 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ 395 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ 396 #define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ 397 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ 398 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ 399 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ 400 #define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ 401 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ 402 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ 403 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ 404 #define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ 405 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ 406 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ 407 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ 408 #define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ 409 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ 410 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ 411 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ 412 #if defined(DMA1_Channel6) 413 #define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ 414 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ 415 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ 416 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ 417 #endif /* DMA1_Channel6 */ 418 #if defined(DMA1_Channel7) 419 #define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ 420 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ 421 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ 422 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ 423 #endif /* DMA1_Channel7 */ 424 /** 425 * @} 426 */ 427 428 /** 429 * @} 430 */ 431 432 /* Exported macros -----------------------------------------------------------*/ 433 /** @defgroup DMA_Exported_Macros DMA Exported Macros 434 * @{ 435 */ 436 437 /** @brief Reset DMA handle state 438 * @param __HANDLE__ DMA handle 439 * @retval None 440 */ 441 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 442 443 /** 444 * @brief Enable the specified DMA Channel. 445 * @param __HANDLE__ DMA handle 446 * @retval None 447 */ 448 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 449 450 /** 451 * @brief Disable the specified DMA Channel. 452 * @param __HANDLE__ DMA handle 453 * @retval None 454 */ 455 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 456 457 /** 458 * @brief Return the current DMA Channel transfer complete flag. 459 * @param __HANDLE__ DMA handle 460 * @retval The specified transfer complete flag index. 461 */ 462 #if defined(DMA2) 463 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 464 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 475 DMA_FLAG_TC7) 476 #else /* DMA1 */ 477 #if defined(DMA1_Channel7) 478 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 479 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 485 DMA_FLAG_TC7) 486 #else 487 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 488 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 492 DMA_FLAG_TC5) 493 #endif /* DMA1_Channel8 */ 494 #endif /* DMA2 */ 495 496 /** 497 * @brief Return the current DMA Channel half transfer complete flag. 498 * @param __HANDLE__ DMA handle 499 * @retval The specified half transfer complete flag index. 500 */ 501 #if defined(DMA2) 502 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 514 DMA_FLAG_HT7) 515 #else /* DMA1 */ 516 #if defined(DMA1_Channel7) 517 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 518 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 524 DMA_FLAG_HT7) 525 #else 526 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 527 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 531 DMA_FLAG_HT5) 532 #endif /* DMA1_Channel8 */ 533 #endif /* DMA2 */ 534 535 /** 536 * @brief Return the current DMA Channel transfer error flag. 537 * @param __HANDLE__ DMA handle 538 * @retval The specified transfer error flag index. 539 */ 540 #if defined(DMA2) 541 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 542 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 551 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 552 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 553 DMA_FLAG_TE7) 554 #else /* DMA1 */ 555 #if defined(DMA1_Channel7) 556 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 557 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 563 DMA_FLAG_TE7) 564 #else 565 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 566 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 567 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 568 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 569 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 570 DMA_FLAG_TE5) 571 #endif /* DMA1_Channel8 */ 572 #endif /* DMA2 */ 573 574 /** 575 * @brief Return the current DMA Channel Global interrupt flag. 576 * @param __HANDLE__ DMA handle 577 * @retval The specified transfer error flag index. 578 */ 579 #if defined(DMA2) 580 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 581 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 582 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ 583 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 584 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ 585 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 586 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ 587 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 588 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ 589 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 590 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ 591 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 592 DMA_FLAG_GI7) 593 #else /* DMA1 */ 594 #if defined(DMA1_Channel7) 595 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 596 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 602 DMA_FLAG_GI7) 603 #else 604 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 605 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 606 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 609 DMA_FLAG_GI5) 610 #endif /* DMA1_Channel8 */ 611 #endif /* DMA2 */ 612 613 /** 614 * @brief Get the DMA Channel pending flags. 615 * @param __HANDLE__ DMA handle 616 * @param __FLAG__ Get the specified flag. 617 * This parameter can be any combination of the following values: 618 * @arg DMA_FLAG_TCx: Transfer complete flag 619 * @arg DMA_FLAG_HTx: Half transfer complete flag 620 * @arg DMA_FLAG_TEx: Transfer error flag 621 * @arg DMA_FLAG_GIx: Global interrupt flag 622 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 623 * @retval The state of FLAG (SET or RESET). 624 */ 625 #if defined(DMA2) 626 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 627 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 628 #else /* DMA1 */ 629 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) 630 #endif /* DMA2 */ 631 632 /** 633 * @brief Clear the DMA Channel pending flags. 634 * @param __HANDLE__ DMA handle 635 * @param __FLAG__ specifies the flag to clear. 636 * This parameter can be any combination of the following values: 637 * @arg DMA_FLAG_TCx: Transfer complete flag 638 * @arg DMA_FLAG_HTx: Half transfer complete flag 639 * @arg DMA_FLAG_TEx: Transfer error flag 640 * @arg DMA_FLAG_GIx: Global interrupt flag 641 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 642 * @retval None 643 */ 644 #if defined(DMA2) 645 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 646 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 647 #else /* DMA1 */ 648 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) 649 #endif /* DMA2 */ 650 651 /** 652 * @brief Enable the specified DMA Channel interrupts. 653 * @param __HANDLE__ DMA handle 654 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 655 * This parameter can be any combination of the following values: 656 * @arg DMA_IT_TC: Transfer complete interrupt mask 657 * @arg DMA_IT_HT: Half transfer complete interrupt mask 658 * @arg DMA_IT_TE: Transfer error interrupt mask 659 * @retval None 660 */ 661 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 662 663 /** 664 * @brief Disable the specified DMA Channel interrupts. 665 * @param __HANDLE__ DMA handle 666 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 667 * This parameter can be any combination of the following values: 668 * @arg DMA_IT_TC: Transfer complete interrupt mask 669 * @arg DMA_IT_HT: Half transfer complete interrupt mask 670 * @arg DMA_IT_TE: Transfer error interrupt mask 671 * @retval None 672 */ 673 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 674 675 /** 676 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 677 * @param __HANDLE__ DMA handle 678 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 679 * This parameter can be one of the following values: 680 * @arg DMA_IT_TC: Transfer complete interrupt mask 681 * @arg DMA_IT_HT: Half transfer complete interrupt mask 682 * @arg DMA_IT_TE: Transfer error interrupt mask 683 * @retval The state of DMA_IT (SET or RESET). 684 */ 685 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 686 687 /** 688 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 689 * @param __HANDLE__ DMA handle 690 * @retval The number of remaining data units in the current DMA Channel transfer. 691 */ 692 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 693 694 /** 695 * @} 696 */ 697 698 /* Include DMA HAL Extension module */ 699 #include "stm32g0xx_hal_dma_ex.h" 700 701 /* Exported functions --------------------------------------------------------*/ 702 703 /** @addtogroup DMA_Exported_Functions 704 * @{ 705 */ 706 707 /** @addtogroup DMA_Exported_Functions_Group1 708 * @{ 709 */ 710 /* Initialization and de-initialization functions *****************************/ 711 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 712 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 713 /** 714 * @} 715 */ 716 717 /** @addtogroup DMA_Exported_Functions_Group2 718 * @{ 719 */ 720 /* IO operation functions *****************************************************/ 721 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 722 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 723 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 724 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 725 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 726 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 727 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 728 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 729 730 /** 731 * @} 732 */ 733 734 /** @addtogroup DMA_Exported_Functions_Group3 735 * @{ 736 */ 737 /* Peripheral State and Error functions ***************************************/ 738 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 739 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 740 /** 741 * @} 742 */ 743 744 /** 745 * @} 746 */ 747 748 /* Private macros ------------------------------------------------------------*/ 749 /** @defgroup DMA_Private_Macros DMA Private Macros 750 * @{ 751 */ 752 753 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 754 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 755 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 756 757 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) 758 759 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 760 ((STATE) == DMA_PINC_DISABLE)) 761 762 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 763 ((STATE) == DMA_MINC_DISABLE)) 764 765 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) 766 767 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 768 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 769 ((SIZE) == DMA_PDATAALIGN_WORD)) 770 771 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 772 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 773 ((SIZE) == DMA_MDATAALIGN_WORD )) 774 775 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 776 ((MODE) == DMA_CIRCULAR)) 777 778 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 779 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 780 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 781 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 782 783 /** 784 * @} 785 */ 786 787 /* Private functions ---------------------------------------------------------*/ 788 789 /** 790 * @} 791 */ 792 793 /** 794 * @} 795 */ 796 797 #ifdef __cplusplus 798 } 799 #endif 800 801 #endif /* STM32G0xx_HAL_DMA_H */ 802 803 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 804
