1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F7xx_HAL_TIM_H 22 #define STM32F7xx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f7xx_hal_def.h" 30 31 /** @addtogroup STM32F7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TIM_Exported_Types TIM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TIM Time base Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 58 59 uint32_t ClockDivision; /*!< Specifies the clock division. 60 This parameter can be a value of @ref TIM_ClockDivision */ 61 62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 63 reaches zero, an update event is generated and counting restarts 64 from the RCR value (N). 65 This means in PWM mode that (N+1) corresponds to: 66 - the number of PWM periods in edge-aligned mode 67 - the number of half PWM period in center-aligned mode 68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 70 71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 72 This parameter can be a value of @ref TIM_AutoReloadPreload */ 73 } TIM_Base_InitTypeDef; 74 75 /** 76 * @brief TIM Output Compare Configuration Structure definition 77 */ 78 typedef struct 79 { 80 uint32_t OCMode; /*!< Specifies the TIM mode. 81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 82 83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 85 86 uint32_t OCPolarity; /*!< Specifies the output polarity. 87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 88 89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 91 @note This parameter is valid only for timer instances supporting break feature. */ 92 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 94 This parameter can be a value of @ref TIM_Output_Fast_State 95 @note This parameter is valid only in PWM1 and PWM2 mode. */ 96 97 98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 100 @note This parameter is valid only for timer instances supporting break feature. */ 101 102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 104 @note This parameter is valid only for timer instances supporting break feature. */ 105 } TIM_OC_InitTypeDef; 106 107 /** 108 * @brief TIM One Pulse Mode Configuration Structure definition 109 */ 110 typedef struct 111 { 112 uint32_t OCMode; /*!< Specifies the TIM mode. 113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 114 115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 117 118 uint32_t OCPolarity; /*!< Specifies the output polarity. 119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 120 121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 123 @note This parameter is valid only for timer instances supporting break feature. */ 124 125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 127 @note This parameter is valid only for timer instances supporting break feature. */ 128 129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 131 @note This parameter is valid only for timer instances supporting break feature. */ 132 133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 135 136 uint32_t ICSelection; /*!< Specifies the input. 137 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 138 139 uint32_t ICFilter; /*!< Specifies the input capture filter. 140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 141 } TIM_OnePulse_InitTypeDef; 142 143 /** 144 * @brief TIM Input Capture Configuration Structure definition 145 */ 146 typedef struct 147 { 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 150 151 uint32_t ICSelection; /*!< Specifies the input. 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 153 154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 156 157 uint32_t ICFilter; /*!< Specifies the input capture filter. 158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 159 } TIM_IC_InitTypeDef; 160 161 /** 162 * @brief TIM Encoder Configuration Structure definition 163 */ 164 typedef struct 165 { 166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 167 This parameter can be a value of @ref TIM_Encoder_Mode */ 168 169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 170 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 171 172 uint32_t IC1Selection; /*!< Specifies the input. 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 174 175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 177 178 uint32_t IC1Filter; /*!< Specifies the input capture filter. 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 180 181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 182 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 183 184 uint32_t IC2Selection; /*!< Specifies the input. 185 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 186 187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 189 190 uint32_t IC2Filter; /*!< Specifies the input capture filter. 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 192 } TIM_Encoder_InitTypeDef; 193 194 /** 195 * @brief Clock Configuration Handle Structure definition 196 */ 197 typedef struct 198 { 199 uint32_t ClockSource; /*!< TIM clock sources 200 This parameter can be a value of @ref TIM_Clock_Source */ 201 uint32_t ClockPolarity; /*!< TIM clock polarity 202 This parameter can be a value of @ref TIM_Clock_Polarity */ 203 uint32_t ClockPrescaler; /*!< TIM clock prescaler 204 This parameter can be a value of @ref TIM_Clock_Prescaler */ 205 uint32_t ClockFilter; /*!< TIM clock filter 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 207 } TIM_ClockConfigTypeDef; 208 209 /** 210 * @brief TIM Clear Input Configuration Handle Structure definition 211 */ 212 typedef struct 213 { 214 uint32_t ClearInputState; /*!< TIM clear Input state 215 This parameter can be ENABLE or DISABLE */ 216 uint32_t ClearInputSource; /*!< TIM clear Input sources 217 This parameter can be a value of @ref TIM_ClearInput_Source */ 218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 219 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 224 } TIM_ClearInputConfigTypeDef; 225 226 /** 227 * @brief TIM Master configuration Structure definition 228 * @note Advanced timers provide TRGO2 internal line which is redirected 229 * to the ADC 230 */ 231 typedef struct 232 { 233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 234 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 238 This parameter can be a value of @ref TIM_Master_Slave_Mode 239 @note When the Master/slave mode is enabled, the effect of 240 an event on the trigger input (TRGI) is delayed to allow a 241 perfect synchronization between the current timer and its 242 slaves (through TRGO). It is not mandatory in case of timer 243 synchronization mode. */ 244 } TIM_MasterConfigTypeDef; 245 246 /** 247 * @brief TIM Slave configuration Structure definition 248 */ 249 typedef struct 250 { 251 uint32_t SlaveMode; /*!< Slave mode selection 252 This parameter can be a value of @ref TIM_Slave_Mode */ 253 uint32_t InputTrigger; /*!< Input Trigger source 254 This parameter can be a value of @ref TIM_Trigger_Selection */ 255 uint32_t TriggerPolarity; /*!< Input Trigger polarity 256 This parameter can be a value of @ref TIM_Trigger_Polarity */ 257 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 258 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 259 uint32_t TriggerFilter; /*!< Input trigger filter 260 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 261 262 } TIM_SlaveConfigTypeDef; 263 264 /** 265 * @brief TIM Break input(s) and Dead time configuration Structure definition 266 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 267 * filter and polarity. 268 */ 269 typedef struct 270 { 271 uint32_t OffStateRunMode; /*!< TIM off state in run mode 272 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 273 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 274 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 275 uint32_t LockLevel; /*!< TIM Lock level 276 This parameter can be a value of @ref TIM_Lock_level */ 277 uint32_t DeadTime; /*!< TIM dead Time 278 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 279 uint32_t BreakState; /*!< TIM Break State 280 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 281 uint32_t BreakPolarity; /*!< TIM Break input polarity 282 This parameter can be a value of @ref TIM_Break_Polarity */ 283 uint32_t BreakFilter; /*!< Specifies the break input filter. 284 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 285 uint32_t Break2State; /*!< TIM Break2 State 286 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 287 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 288 This parameter can be a value of @ref TIM_Break2_Polarity */ 289 uint32_t Break2Filter; /*!< TIM break2 input filter. 290 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 291 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 292 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 293 } TIM_BreakDeadTimeConfigTypeDef; 294 295 /** 296 * @brief HAL State structures definition 297 */ 298 typedef enum 299 { 300 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 301 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 302 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 303 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 304 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 305 } HAL_TIM_StateTypeDef; 306 307 /** 308 * @brief TIM Channel States definition 309 */ 310 typedef enum 311 { 312 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 313 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 314 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 315 } HAL_TIM_ChannelStateTypeDef; 316 317 /** 318 * @brief DMA Burst States definition 319 */ 320 typedef enum 321 { 322 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 323 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 324 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 325 } HAL_TIM_DMABurstStateTypeDef; 326 327 /** 328 * @brief HAL Active channel structures definition 329 */ 330 typedef enum 331 { 332 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 333 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 334 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 335 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 336 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 337 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 338 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 339 } HAL_TIM_ActiveChannel; 340 341 /** 342 * @brief TIM Time Base Handle Structure definition 343 */ 344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 345 typedef struct __TIM_HandleTypeDef 346 #else 347 typedef struct 348 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 349 { 350 TIM_TypeDef *Instance; /*!< Register base address */ 351 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 352 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 353 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 354 This array is accessed by a @ref DMA_Handle_index */ 355 HAL_LockTypeDef Lock; /*!< Locking object */ 356 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 357 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 358 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 359 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 360 361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 362 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 363 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 364 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 365 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 366 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 367 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 368 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 369 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 370 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 371 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 372 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 373 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 374 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 375 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 376 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 377 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 378 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 379 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 380 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 381 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 382 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 383 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 384 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 385 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 386 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 387 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 388 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 389 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 390 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 391 } TIM_HandleTypeDef; 392 393 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 394 /** 395 * @brief HAL TIM Callback ID enumeration definition 396 */ 397 typedef enum 398 { 399 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 400 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 401 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 402 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 403 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 404 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 405 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 406 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 407 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 408 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 409 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 410 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 411 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 412 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 413 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 414 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 415 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 416 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 417 418 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 419 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 420 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 421 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 422 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 423 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 424 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 425 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 426 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 427 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 428 } HAL_TIM_CallbackIDTypeDef; 429 430 /** 431 * @brief HAL TIM Callback pointer definition 432 */ 433 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 434 435 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 436 437 /** 438 * @} 439 */ 440 /* End of exported types -----------------------------------------------------*/ 441 442 /* Exported constants --------------------------------------------------------*/ 443 /** @defgroup TIM_Exported_Constants TIM Exported Constants 444 * @{ 445 */ 446 447 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 448 * @{ 449 */ 450 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 451 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 452 /** 453 * @} 454 */ 455 456 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 457 * @{ 458 */ 459 #define TIM_DMABASE_CR1 0x00000000U 460 #define TIM_DMABASE_CR2 0x00000001U 461 #define TIM_DMABASE_SMCR 0x00000002U 462 #define TIM_DMABASE_DIER 0x00000003U 463 #define TIM_DMABASE_SR 0x00000004U 464 #define TIM_DMABASE_EGR 0x00000005U 465 #define TIM_DMABASE_CCMR1 0x00000006U 466 #define TIM_DMABASE_CCMR2 0x00000007U 467 #define TIM_DMABASE_CCER 0x00000008U 468 #define TIM_DMABASE_CNT 0x00000009U 469 #define TIM_DMABASE_PSC 0x0000000AU 470 #define TIM_DMABASE_ARR 0x0000000BU 471 #define TIM_DMABASE_RCR 0x0000000CU 472 #define TIM_DMABASE_CCR1 0x0000000DU 473 #define TIM_DMABASE_CCR2 0x0000000EU 474 #define TIM_DMABASE_CCR3 0x0000000FU 475 #define TIM_DMABASE_CCR4 0x00000010U 476 #define TIM_DMABASE_BDTR 0x00000011U 477 #define TIM_DMABASE_DCR 0x00000012U 478 #define TIM_DMABASE_DMAR 0x00000013U 479 #define TIM_DMABASE_OR 0x00000014U 480 #define TIM_DMABASE_CCMR3 0x00000015U 481 #define TIM_DMABASE_CCR5 0x00000016U 482 #define TIM_DMABASE_CCR6 0x00000017U 483 #if defined(TIM_BREAK_INPUT_SUPPORT) 484 #define TIM_DMABASE_AF1 0x00000018U 485 #define TIM_DMABASE_AF2 0x00000019U 486 #endif /* TIM_BREAK_INPUT_SUPPORT */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup TIM_Event_Source TIM Event Source 492 * @{ 493 */ 494 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 495 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 496 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 497 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 498 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 499 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 500 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 501 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 502 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 508 * @{ 509 */ 510 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 511 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 512 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 518 * @{ 519 */ 520 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 521 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 527 * @{ 528 */ 529 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 530 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 531 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 532 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup TIM_Counter_Mode TIM Counter Mode 538 * @{ 539 */ 540 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 541 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 542 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 543 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 544 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 550 * @{ 551 */ 552 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 553 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 554 /** 555 * @} 556 */ 557 558 /** @defgroup TIM_ClockDivision TIM Clock Division 559 * @{ 560 */ 561 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 562 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 563 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 569 * @{ 570 */ 571 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 572 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 573 /** 574 * @} 575 */ 576 577 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 578 * @{ 579 */ 580 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 581 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 582 583 /** 584 * @} 585 */ 586 587 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 588 * @{ 589 */ 590 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 591 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 597 * @{ 598 */ 599 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 600 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 606 * @{ 607 */ 608 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 609 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 610 /** 611 * @} 612 */ 613 614 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 615 * @{ 616 */ 617 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 618 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 624 * @{ 625 */ 626 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 627 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 633 * @{ 634 */ 635 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 636 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 642 * @{ 643 */ 644 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 645 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 646 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 647 /** 648 * @} 649 */ 650 651 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 652 * @{ 653 */ 654 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 655 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 661 * @{ 662 */ 663 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 664 connected to IC1, IC2, IC3 or IC4, respectively */ 665 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 666 connected to IC2, IC1, IC4 or IC3, respectively */ 667 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 668 /** 669 * @} 670 */ 671 672 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 673 * @{ 674 */ 675 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 676 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 677 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 678 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 684 * @{ 685 */ 686 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 687 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 693 * @{ 694 */ 695 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 696 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 697 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 698 /** 699 * @} 700 */ 701 702 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 703 * @{ 704 */ 705 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 706 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 707 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 708 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 709 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 710 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 711 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 712 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup TIM_Commutation_Source TIM Commutation Source 718 * @{ 719 */ 720 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 721 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup TIM_DMA_sources TIM DMA Sources 727 * @{ 728 */ 729 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 730 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 731 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 732 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 733 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 734 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 735 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 736 /** 737 * @} 738 */ 739 740 /** @defgroup TIM_Flag_definition TIM Flag Definition 741 * @{ 742 */ 743 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 744 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 745 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 746 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 747 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 748 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 749 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 750 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 751 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 752 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 753 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 754 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 755 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 756 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 757 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 758 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 759 /** 760 * @} 761 */ 762 763 /** @defgroup TIM_Channel TIM Channel 764 * @{ 765 */ 766 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 767 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 768 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 769 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 770 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 771 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 772 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup TIM_Clock_Source TIM Clock Source 778 * @{ 779 */ 780 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 781 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 782 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 783 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 784 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 785 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 786 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 787 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 788 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 789 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 790 /** 791 * @} 792 */ 793 794 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 795 * @{ 796 */ 797 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 798 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 799 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 800 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 801 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 802 /** 803 * @} 804 */ 805 806 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 807 * @{ 808 */ 809 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 810 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 811 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 812 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 818 * @{ 819 */ 820 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 821 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 822 /** 823 * @} 824 */ 825 826 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 827 * @{ 828 */ 829 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 830 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 831 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 832 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 833 /** 834 * @} 835 */ 836 837 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 838 * @{ 839 */ 840 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 841 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 842 /** 843 * @} 844 */ 845 846 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 847 * @{ 848 */ 849 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 850 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 851 /** 852 * @} 853 */ 854 /** @defgroup TIM_Lock_level TIM Lock level 855 * @{ 856 */ 857 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 858 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 859 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 860 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 861 /** 862 * @} 863 */ 864 865 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 866 * @{ 867 */ 868 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 869 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 870 /** 871 * @} 872 */ 873 874 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 875 * @{ 876 */ 877 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 878 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 879 /** 880 * @} 881 */ 882 883 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 884 * @{ 885 */ 886 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 887 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 888 /** 889 * @} 890 */ 891 892 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 893 * @{ 894 */ 895 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 896 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 897 /** 898 * @} 899 */ 900 901 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 902 * @{ 903 */ 904 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 905 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 906 (if none of the break inputs BRK and BRK2 is active) */ 907 /** 908 * @} 909 */ 910 911 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 912 * @{ 913 */ 914 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 915 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 916 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 917 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 918 /** 919 * @} 920 */ 921 922 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 923 * @{ 924 */ 925 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 926 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 927 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 928 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 929 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 930 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 931 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 932 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 933 /** 934 * @} 935 */ 936 937 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 938 * @{ 939 */ 940 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 941 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 942 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 943 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 944 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 945 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 946 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 947 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 948 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 949 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 950 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 951 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 952 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 953 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 954 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 955 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 956 /** 957 * @} 958 */ 959 960 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 961 * @{ 962 */ 963 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 964 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 965 /** 966 * @} 967 */ 968 969 /** @defgroup TIM_Slave_Mode TIM Slave mode 970 * @{ 971 */ 972 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 973 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 974 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 975 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 976 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 977 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 978 /** 979 * @} 980 */ 981 982 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 983 * @{ 984 */ 985 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 986 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 987 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 988 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 989 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 990 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 991 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 992 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 993 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 994 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 995 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 996 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 997 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 998 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 999 /** 1000 * @} 1001 */ 1002 1003 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1004 * @{ 1005 */ 1006 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1007 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1008 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1009 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1010 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1011 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1012 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1013 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1014 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1015 /** 1016 * @} 1017 */ 1018 1019 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1020 * @{ 1021 */ 1022 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1023 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1024 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1025 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1026 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1032 * @{ 1033 */ 1034 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1035 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1036 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1037 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1038 /** 1039 * @} 1040 */ 1041 1042 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1043 * @{ 1044 */ 1045 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1046 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1047 /** 1048 * @} 1049 */ 1050 1051 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1052 * @{ 1053 */ 1054 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1055 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1056 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1057 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1058 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1059 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1060 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1061 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1062 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1063 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1064 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1065 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1066 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1067 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1068 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1069 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1070 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1071 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1072 /** 1073 * @} 1074 */ 1075 1076 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1077 * @{ 1078 */ 1079 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1080 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1081 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1082 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1083 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1084 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1085 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1086 /** 1087 * @} 1088 */ 1089 1090 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1091 * @{ 1092 */ 1093 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1094 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1095 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1096 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1097 /** 1098 * @} 1099 */ 1100 1101 /** @defgroup TIM_Break_System TIM Break System 1102 * @{ 1103 */ 1104 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ 1105 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1106 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ 1107 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1108 /** 1109 * @} 1110 */ 1111 1112 /** 1113 * @} 1114 */ 1115 /* End of exported constants -------------------------------------------------*/ 1116 1117 /* Exported macros -----------------------------------------------------------*/ 1118 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1119 * @{ 1120 */ 1121 1122 /** @brief Reset TIM handle state. 1123 * @param __HANDLE__ TIM handle. 1124 * @retval None 1125 */ 1126 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1127 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1128 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1129 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1130 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1131 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1132 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1133 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1134 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1135 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1136 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1137 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1138 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1139 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1140 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1141 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1142 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1143 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1144 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1145 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1146 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1147 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1148 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1149 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1150 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1151 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1152 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1153 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1154 } while(0) 1155 #else 1156 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1157 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1158 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1159 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1160 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1161 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1162 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1163 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1164 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1165 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1166 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1167 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1168 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1169 } while(0) 1170 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1171 1172 /** 1173 * @brief Enable the TIM peripheral. 1174 * @param __HANDLE__ TIM handle 1175 * @retval None 1176 */ 1177 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1178 1179 /** 1180 * @brief Enable the TIM main Output. 1181 * @param __HANDLE__ TIM handle 1182 * @retval None 1183 */ 1184 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1185 1186 /** 1187 * @brief Disable the TIM peripheral. 1188 * @param __HANDLE__ TIM handle 1189 * @retval None 1190 */ 1191 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1192 do { \ 1193 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1194 { \ 1195 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1196 { \ 1197 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1198 } \ 1199 } \ 1200 } while(0) 1201 1202 /** 1203 * @brief Disable the TIM main Output. 1204 * @param __HANDLE__ TIM handle 1205 * @retval None 1206 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1207 */ 1208 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1209 do { \ 1210 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1211 { \ 1212 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1213 { \ 1214 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1215 } \ 1216 } \ 1217 } while(0) 1218 1219 /** 1220 * @brief Disable the TIM main Output. 1221 * @param __HANDLE__ TIM handle 1222 * @retval None 1223 * @note The Main Output Enable of a timer instance is disabled unconditionally 1224 */ 1225 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1226 1227 /** @brief Enable the specified TIM interrupt. 1228 * @param __HANDLE__ specifies the TIM Handle. 1229 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1230 * This parameter can be one of the following values: 1231 * @arg TIM_IT_UPDATE: Update interrupt 1232 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1233 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1234 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1235 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1236 * @arg TIM_IT_COM: Commutation interrupt 1237 * @arg TIM_IT_TRIGGER: Trigger interrupt 1238 * @arg TIM_IT_BREAK: Break interrupt 1239 * @retval None 1240 */ 1241 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1242 1243 /** @brief Disable the specified TIM interrupt. 1244 * @param __HANDLE__ specifies the TIM Handle. 1245 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1246 * This parameter can be one of the following values: 1247 * @arg TIM_IT_UPDATE: Update interrupt 1248 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1249 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1250 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1251 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1252 * @arg TIM_IT_COM: Commutation interrupt 1253 * @arg TIM_IT_TRIGGER: Trigger interrupt 1254 * @arg TIM_IT_BREAK: Break interrupt 1255 * @retval None 1256 */ 1257 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1258 1259 /** @brief Enable the specified DMA request. 1260 * @param __HANDLE__ specifies the TIM Handle. 1261 * @param __DMA__ specifies the TIM DMA request to enable. 1262 * This parameter can be one of the following values: 1263 * @arg TIM_DMA_UPDATE: Update DMA request 1264 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1265 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1266 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1267 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1268 * @arg TIM_DMA_COM: Commutation DMA request 1269 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1270 * @retval None 1271 */ 1272 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1273 1274 /** @brief Disable the specified DMA request. 1275 * @param __HANDLE__ specifies the TIM Handle. 1276 * @param __DMA__ specifies the TIM DMA request to disable. 1277 * This parameter can be one of the following values: 1278 * @arg TIM_DMA_UPDATE: Update DMA request 1279 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1280 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1281 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1282 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1283 * @arg TIM_DMA_COM: Commutation DMA request 1284 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1285 * @retval None 1286 */ 1287 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1288 1289 /** @brief Check whether the specified TIM interrupt flag is set or not. 1290 * @param __HANDLE__ specifies the TIM Handle. 1291 * @param __FLAG__ specifies the TIM interrupt flag to check. 1292 * This parameter can be one of the following values: 1293 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1294 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1295 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1296 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1297 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1298 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1299 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1300 * @arg TIM_FLAG_COM: Commutation interrupt flag 1301 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1302 * @arg TIM_FLAG_BREAK: Break interrupt flag 1303 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1304 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1305 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1306 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1307 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1308 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1309 * @retval The new state of __FLAG__ (TRUE or FALSE). 1310 */ 1311 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1312 1313 /** @brief Clear the specified TIM interrupt flag. 1314 * @param __HANDLE__ specifies the TIM Handle. 1315 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1316 * This parameter can be one of the following values: 1317 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1318 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1319 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1320 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1321 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1322 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1323 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1324 * @arg TIM_FLAG_COM: Commutation interrupt flag 1325 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1326 * @arg TIM_FLAG_BREAK: Break interrupt flag 1327 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1328 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1329 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1330 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1331 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1332 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1333 * @retval The new state of __FLAG__ (TRUE or FALSE). 1334 */ 1335 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1336 1337 /** 1338 * @brief Check whether the specified TIM interrupt source is enabled or not. 1339 * @param __HANDLE__ TIM handle 1340 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1341 * This parameter can be one of the following values: 1342 * @arg TIM_IT_UPDATE: Update interrupt 1343 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1344 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1345 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1346 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1347 * @arg TIM_IT_COM: Commutation interrupt 1348 * @arg TIM_IT_TRIGGER: Trigger interrupt 1349 * @arg TIM_IT_BREAK: Break interrupt 1350 * @retval The state of TIM_IT (SET or RESET). 1351 */ 1352 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1353 == (__INTERRUPT__)) ? SET : RESET) 1354 1355 /** @brief Clear the TIM interrupt pending bits. 1356 * @param __HANDLE__ TIM handle 1357 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1358 * This parameter can be one of the following values: 1359 * @arg TIM_IT_UPDATE: Update interrupt 1360 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1361 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1362 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1363 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1364 * @arg TIM_IT_COM: Commutation interrupt 1365 * @arg TIM_IT_TRIGGER: Trigger interrupt 1366 * @arg TIM_IT_BREAK: Break interrupt 1367 * @retval None 1368 */ 1369 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1370 1371 /** 1372 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1373 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. 1374 * @param __HANDLE__ TIM handle. 1375 * @retval None 1376 mode. 1377 */ 1378 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1379 1380 /** 1381 * @brief Disable update interrupt flag (UIF) remapping. 1382 * @param __HANDLE__ TIM handle. 1383 * @retval None 1384 mode. 1385 */ 1386 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1387 1388 /** 1389 * @brief Get update interrupt flag (UIF) copy status. 1390 * @param __COUNTER__ Counter value. 1391 * @retval The state of UIFCPY (TRUE or FALSE). 1392 mode. 1393 */ 1394 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1395 1396 /** 1397 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1398 * @param __HANDLE__ TIM handle. 1399 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1400 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1401 mode. 1402 */ 1403 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1404 1405 /** 1406 * @brief Set the TIM Prescaler on runtime. 1407 * @param __HANDLE__ TIM handle. 1408 * @param __PRESC__ specifies the Prescaler new value. 1409 * @retval None 1410 */ 1411 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1412 1413 /** 1414 * @brief Set the TIM Counter Register value on runtime. 1415 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. 1416 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1417 * @param __HANDLE__ TIM handle. 1418 * @param __COUNTER__ specifies the Counter register new value. 1419 * @retval None 1420 */ 1421 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1422 1423 /** 1424 * @brief Get the TIM Counter Register value on runtime. 1425 * @param __HANDLE__ TIM handle. 1426 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1427 */ 1428 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1429 1430 /** 1431 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1432 * @param __HANDLE__ TIM handle. 1433 * @param __AUTORELOAD__ specifies the Counter register new value. 1434 * @retval None 1435 */ 1436 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1437 do{ \ 1438 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1439 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1440 } while(0) 1441 1442 /** 1443 * @brief Get the TIM Autoreload Register value on runtime. 1444 * @param __HANDLE__ TIM handle. 1445 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1446 */ 1447 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1448 1449 /** 1450 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1451 * @param __HANDLE__ TIM handle. 1452 * @param __CKD__ specifies the clock division value. 1453 * This parameter can be one of the following value: 1454 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1455 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1456 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1457 * @retval None 1458 */ 1459 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1460 do{ \ 1461 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1462 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1463 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1464 } while(0) 1465 1466 /** 1467 * @brief Get the TIM Clock Division value on runtime. 1468 * @param __HANDLE__ TIM handle. 1469 * @retval The clock division can be one of the following values: 1470 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1471 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1472 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1473 */ 1474 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1475 1476 /** 1477 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1478 * @param __HANDLE__ TIM handle. 1479 * @param __CHANNEL__ TIM Channels to be configured. 1480 * This parameter can be one of the following values: 1481 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1482 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1483 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1484 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1485 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1486 * This parameter can be one of the following values: 1487 * @arg TIM_ICPSC_DIV1: no prescaler 1488 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1489 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1490 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1491 * @retval None 1492 */ 1493 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1494 do{ \ 1495 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1496 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1497 } while(0) 1498 1499 /** 1500 * @brief Get the TIM Input Capture prescaler on runtime. 1501 * @param __HANDLE__ TIM handle. 1502 * @param __CHANNEL__ TIM Channels to be configured. 1503 * This parameter can be one of the following values: 1504 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1505 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1506 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1507 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1508 * @retval The input capture prescaler can be one of the following values: 1509 * @arg TIM_ICPSC_DIV1: no prescaler 1510 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1511 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1512 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1513 */ 1514 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1515 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1516 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1517 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1518 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1519 1520 /** 1521 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1522 * @param __HANDLE__ TIM handle. 1523 * @param __CHANNEL__ TIM Channels to be configured. 1524 * This parameter can be one of the following values: 1525 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1526 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1527 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1528 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1529 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1530 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1531 * @param __COMPARE__ specifies the Capture Compare register new value. 1532 * @retval None 1533 */ 1534 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1535 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1536 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1537 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1538 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1539 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1540 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1541 1542 /** 1543 * @brief Get the TIM Capture Compare Register value on runtime. 1544 * @param __HANDLE__ TIM handle. 1545 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1546 * This parameter can be one of the following values: 1547 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1548 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1549 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1550 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1551 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1552 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1553 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1554 */ 1555 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1556 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1557 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1558 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1559 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1560 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1561 ((__HANDLE__)->Instance->CCR6)) 1562 1563 /** 1564 * @brief Set the TIM Output compare preload. 1565 * @param __HANDLE__ TIM handle. 1566 * @param __CHANNEL__ TIM Channels to be configured. 1567 * This parameter can be one of the following values: 1568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1572 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1573 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1574 * @retval None 1575 */ 1576 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1577 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1578 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1579 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1580 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1581 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1582 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1583 1584 /** 1585 * @brief Reset the TIM Output compare preload. 1586 * @param __HANDLE__ TIM handle. 1587 * @param __CHANNEL__ TIM Channels to be configured. 1588 * This parameter can be one of the following values: 1589 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1590 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1591 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1592 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1593 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1594 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1595 * @retval None 1596 */ 1597 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1598 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1599 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1600 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1601 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1602 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1603 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1604 1605 /** 1606 * @brief Enable fast mode for a given channel. 1607 * @param __HANDLE__ TIM handle. 1608 * @param __CHANNEL__ TIM Channels to be configured. 1609 * This parameter can be one of the following values: 1610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1614 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1615 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1616 * @note When fast mode is enabled an active edge on the trigger input acts 1617 * like a compare match on CCx output. Delay to sample the trigger 1618 * input and to activate CCx output is reduced to 3 clock cycles. 1619 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1620 * @retval None 1621 */ 1622 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1623 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1624 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1625 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1626 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1627 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1628 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1629 1630 /** 1631 * @brief Disable fast mode for a given channel. 1632 * @param __HANDLE__ TIM handle. 1633 * @param __CHANNEL__ TIM Channels to be configured. 1634 * This parameter can be one of the following values: 1635 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1636 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1637 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1638 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1639 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1640 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1641 * @note When fast mode is disabled CCx output behaves normally depending 1642 * on counter and CCRx values even when the trigger is ON. The minimum 1643 * delay to activate CCx output when an active edge occurs on the 1644 * trigger input is 5 clock cycles. 1645 * @retval None 1646 */ 1647 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1648 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1649 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1650 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1651 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1652 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1653 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1654 1655 /** 1656 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1657 * @param __HANDLE__ TIM handle. 1658 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1659 * overflow/underflow generates an update interrupt or DMA request (if 1660 * enabled) 1661 * @retval None 1662 */ 1663 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1664 1665 /** 1666 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1667 * @param __HANDLE__ TIM handle. 1668 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1669 * following events generate an update interrupt or DMA request (if 1670 * enabled): 1671 * _ Counter overflow underflow 1672 * _ Setting the UG bit 1673 * _ Update generation through the slave mode controller 1674 * @retval None 1675 */ 1676 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1677 1678 /** 1679 * @brief Set the TIM Capture x input polarity on runtime. 1680 * @param __HANDLE__ TIM handle. 1681 * @param __CHANNEL__ TIM Channels to be configured. 1682 * This parameter can be one of the following values: 1683 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1684 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1685 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1686 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1687 * @param __POLARITY__ Polarity for TIx source 1688 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1689 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1690 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1691 * @retval None 1692 */ 1693 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1694 do{ \ 1695 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1696 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1697 }while(0) 1698 1699 /** 1700 * @} 1701 */ 1702 /* End of exported macros ----------------------------------------------------*/ 1703 1704 /* Private constants ---------------------------------------------------------*/ 1705 /** @defgroup TIM_Private_Constants TIM Private Constants 1706 * @{ 1707 */ 1708 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1709 channels have been disabled */ 1710 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1711 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1712 /** 1713 * @} 1714 */ 1715 /* End of private constants --------------------------------------------------*/ 1716 1717 /* Private macros ------------------------------------------------------------*/ 1718 /** @defgroup TIM_Private_Macros TIM Private Macros 1719 * @{ 1720 */ 1721 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1722 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1723 1724 #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) 1725 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1726 ((__BASE__) == TIM_DMABASE_CR2) || \ 1727 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1728 ((__BASE__) == TIM_DMABASE_DIER) || \ 1729 ((__BASE__) == TIM_DMABASE_SR) || \ 1730 ((__BASE__) == TIM_DMABASE_EGR) || \ 1731 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1732 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1733 ((__BASE__) == TIM_DMABASE_CCER) || \ 1734 ((__BASE__) == TIM_DMABASE_CNT) || \ 1735 ((__BASE__) == TIM_DMABASE_PSC) || \ 1736 ((__BASE__) == TIM_DMABASE_ARR) || \ 1737 ((__BASE__) == TIM_DMABASE_RCR) || \ 1738 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1739 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1740 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1741 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1742 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1743 ((__BASE__) == TIM_DMABASE_OR) || \ 1744 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1745 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1746 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1747 ((__BASE__) == TIM_DMABASE_AF1) || \ 1748 ((__BASE__) == TIM_DMABASE_AF2)) 1749 #else 1750 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1751 ((__BASE__) == TIM_DMABASE_CR2) || \ 1752 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1753 ((__BASE__) == TIM_DMABASE_DIER) || \ 1754 ((__BASE__) == TIM_DMABASE_SR) || \ 1755 ((__BASE__) == TIM_DMABASE_EGR) || \ 1756 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1757 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1758 ((__BASE__) == TIM_DMABASE_CCER) || \ 1759 ((__BASE__) == TIM_DMABASE_CNT) || \ 1760 ((__BASE__) == TIM_DMABASE_PSC) || \ 1761 ((__BASE__) == TIM_DMABASE_ARR) || \ 1762 ((__BASE__) == TIM_DMABASE_RCR) || \ 1763 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1764 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1765 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1766 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1767 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1768 ((__BASE__) == TIM_DMABASE_OR) || \ 1769 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1770 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1771 ((__BASE__) == TIM_DMABASE_CCR6)) 1772 #endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ 1773 1774 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1775 1776 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1777 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1778 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1779 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1780 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1781 1782 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1783 ((__MODE__) == TIM_UIFREMAP_ENALE)) 1784 1785 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1786 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1787 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1788 1789 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1790 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1791 1792 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1793 ((__STATE__) == TIM_OCFAST_ENABLE)) 1794 1795 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1796 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1797 1798 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1799 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1800 1801 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1802 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1803 1804 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1805 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1806 1807 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1808 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1809 1810 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1811 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1812 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1813 1814 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1815 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1816 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1817 1818 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1819 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1820 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1821 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1822 1823 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1824 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1825 1826 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1827 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1828 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1829 1830 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1831 1832 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1833 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1834 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1835 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1836 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1837 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1838 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1839 1840 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1841 ((__CHANNEL__) == TIM_CHANNEL_2)) 1842 1843 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1844 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1845 ((__CHANNEL__) == TIM_CHANNEL_3)) 1846 1847 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1848 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1849 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1850 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1851 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1852 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1853 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1854 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1855 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1856 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1857 1858 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1859 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1860 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1861 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1862 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1863 1864 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1865 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1866 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1867 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1868 1869 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1870 1871 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1872 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1873 1874 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1875 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1876 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1877 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1878 1879 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1880 1881 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1882 ((__STATE__) == TIM_OSSR_DISABLE)) 1883 1884 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1885 ((__STATE__) == TIM_OSSI_DISABLE)) 1886 1887 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1888 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1889 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1890 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1891 1892 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1893 1894 1895 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1896 ((__STATE__) == TIM_BREAK_DISABLE)) 1897 1898 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1899 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1900 1901 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1902 ((__STATE__) == TIM_BREAK2_DISABLE)) 1903 1904 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1905 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1906 1907 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1908 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1909 1910 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1911 1912 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1913 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1914 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1915 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1916 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1917 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1918 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1919 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1920 1921 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1922 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1923 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1924 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1925 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1926 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1927 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1928 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1929 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1930 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1931 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1932 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1933 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1934 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1935 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1936 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1937 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1938 1939 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1940 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1941 1942 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1943 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1944 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1945 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1946 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1947 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1948 1949 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1950 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1951 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1952 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1953 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1954 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1955 1956 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1957 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1958 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1959 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1960 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1961 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1962 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1963 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1964 1965 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1966 ((__SELECTION__) == TIM_TS_ITR1) || \ 1967 ((__SELECTION__) == TIM_TS_ITR2) || \ 1968 ((__SELECTION__) == TIM_TS_ITR3) || \ 1969 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1970 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1971 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1972 ((__SELECTION__) == TIM_TS_ETRF)) 1973 1974 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1975 ((__SELECTION__) == TIM_TS_ITR1) || \ 1976 ((__SELECTION__) == TIM_TS_ITR2) || \ 1977 ((__SELECTION__) == TIM_TS_ITR3) || \ 1978 ((__SELECTION__) == TIM_TS_NONE)) 1979 1980 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1981 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1982 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1983 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1984 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1985 1986 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1987 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1988 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1989 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1990 1991 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1992 1993 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1994 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1995 1996 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1997 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1998 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1999 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2000 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2001 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2002 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2003 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2004 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2005 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2006 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2007 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2008 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2009 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2010 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2011 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2012 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2013 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 2014 2015 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2016 2017 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2018 2019 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2020 2021 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2022 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2023 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2024 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2025 2026 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2027 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2028 2029 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2030 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2031 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2032 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2033 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2034 2035 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2036 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2037 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2038 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2039 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2040 2041 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2042 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2043 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2044 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2045 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2046 2047 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2048 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2049 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2050 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2051 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2052 2053 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2054 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2055 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2056 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2057 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2058 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2059 (__HANDLE__)->ChannelState[5]) 2060 2061 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2062 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2063 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2064 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2065 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2066 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2067 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2068 2069 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2070 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 2071 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 2072 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 2073 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 2074 (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ 2075 (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ 2076 } while(0) 2077 2078 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2079 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2080 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2081 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2082 (__HANDLE__)->ChannelNState[3]) 2083 2084 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2085 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2086 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2087 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2088 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2089 2090 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2091 (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ 2092 (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ 2093 (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ 2094 (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ 2095 } while(0) 2096 2097 /** 2098 * @} 2099 */ 2100 /* End of private macros -----------------------------------------------------*/ 2101 2102 /* Include TIM HAL Extended module */ 2103 #include "stm32f7xx_hal_tim_ex.h" 2104 2105 /* Exported functions --------------------------------------------------------*/ 2106 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2107 * @{ 2108 */ 2109 2110 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2111 * @brief Time Base functions 2112 * @{ 2113 */ 2114 /* Time Base functions ********************************************************/ 2115 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2116 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2117 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2118 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2119 /* Blocking mode: Polling */ 2120 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2121 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2122 /* Non-Blocking mode: Interrupt */ 2123 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2124 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2125 /* Non-Blocking mode: DMA */ 2126 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 2127 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2128 /** 2129 * @} 2130 */ 2131 2132 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2133 * @brief TIM Output Compare functions 2134 * @{ 2135 */ 2136 /* Timer Output Compare functions *********************************************/ 2137 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2138 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2139 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2140 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2141 /* Blocking mode: Polling */ 2142 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2143 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2144 /* Non-Blocking mode: Interrupt */ 2145 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2146 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2147 /* Non-Blocking mode: DMA */ 2148 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2149 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2150 /** 2151 * @} 2152 */ 2153 2154 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2155 * @brief TIM PWM functions 2156 * @{ 2157 */ 2158 /* Timer PWM functions ********************************************************/ 2159 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2160 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2161 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2162 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2163 /* Blocking mode: Polling */ 2164 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2165 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2166 /* Non-Blocking mode: Interrupt */ 2167 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2168 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2169 /* Non-Blocking mode: DMA */ 2170 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2171 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2172 /** 2173 * @} 2174 */ 2175 2176 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2177 * @brief TIM Input Capture functions 2178 * @{ 2179 */ 2180 /* Timer Input Capture functions **********************************************/ 2181 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2182 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2183 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2184 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2185 /* Blocking mode: Polling */ 2186 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2187 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2188 /* Non-Blocking mode: Interrupt */ 2189 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2190 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2191 /* Non-Blocking mode: DMA */ 2192 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2193 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2194 /** 2195 * @} 2196 */ 2197 2198 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2199 * @brief TIM One Pulse functions 2200 * @{ 2201 */ 2202 /* Timer One Pulse functions **************************************************/ 2203 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2204 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2205 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2206 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2207 /* Blocking mode: Polling */ 2208 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2209 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2210 /* Non-Blocking mode: Interrupt */ 2211 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2212 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2213 /** 2214 * @} 2215 */ 2216 2217 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2218 * @brief TIM Encoder functions 2219 * @{ 2220 */ 2221 /* Timer Encoder functions ****************************************************/ 2222 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2223 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2224 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2225 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2226 /* Blocking mode: Polling */ 2227 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2228 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2229 /* Non-Blocking mode: Interrupt */ 2230 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2231 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2232 /* Non-Blocking mode: DMA */ 2233 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2234 uint32_t *pData2, uint16_t Length); 2235 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2236 /** 2237 * @} 2238 */ 2239 2240 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2241 * @brief IRQ handler management 2242 * @{ 2243 */ 2244 /* Interrupt Handler functions ***********************************************/ 2245 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2246 /** 2247 * @} 2248 */ 2249 2250 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2251 * @brief Peripheral Control functions 2252 * @{ 2253 */ 2254 /* Control functions *********************************************************/ 2255 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2256 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2257 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2258 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2259 uint32_t OutputChannel, uint32_t InputChannel); 2260 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2261 uint32_t Channel); 2262 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2263 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2264 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2265 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2266 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2267 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2268 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2269 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, 2270 uint32_t DataLength); 2271 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2272 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2273 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2274 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2275 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, 2276 uint32_t DataLength); 2277 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2278 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2279 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2280 /** 2281 * @} 2282 */ 2283 2284 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2285 * @brief TIM Callbacks functions 2286 * @{ 2287 */ 2288 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2289 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2290 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2291 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2292 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2293 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2294 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2295 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2296 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2297 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2298 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2299 2300 /* Callbacks Register/UnRegister functions ***********************************/ 2301 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2302 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2303 pTIM_CallbackTypeDef pCallback); 2304 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2305 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2306 2307 /** 2308 * @} 2309 */ 2310 2311 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2312 * @brief Peripheral State functions 2313 * @{ 2314 */ 2315 /* Peripheral State functions ************************************************/ 2316 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2317 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2318 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2319 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2320 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2321 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2322 2323 /* Peripheral Channel state functions ************************************************/ 2324 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 2325 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 2326 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 2327 /** 2328 * @} 2329 */ 2330 2331 /** 2332 * @} 2333 */ 2334 /* End of exported functions -------------------------------------------------*/ 2335 2336 /* Private functions----------------------------------------------------------*/ 2337 /** @defgroup TIM_Private_Functions TIM Private Functions 2338 * @{ 2339 */ 2340 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2341 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2342 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2343 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2344 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2345 2346 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2347 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2348 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2349 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2350 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2351 2352 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2353 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2355 2356 /** 2357 * @} 2358 */ 2359 /* End of private functions --------------------------------------------------*/ 2360 2361 /** 2362 * @} 2363 */ 2364 2365 /** 2366 * @} 2367 */ 2368 2369 #ifdef __cplusplus 2370 } 2371 #endif 2372 2373 #endif /* STM32F7xx_HAL_TIM_H */ 2374 2375 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2376
