1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f3xx_ll_rcc.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28 /** @addtogroup STM32F3xx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @defgroup RCC_LL RCC
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /** @addtogroup RCC_LL_Private_Variables
41 * @{
42 */
43 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
44 const uint16_t aADCPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
45 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
46 #if defined(RCC_CFGR_SDPRE)
47 const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
48 #endif /* RCC_CFGR_SDPRE */
49 /**
50 * @}
51 */
52
53
54 /* Private constants ---------------------------------------------------------*/
55 /* Private macros ------------------------------------------------------------*/
56 /** @addtogroup RCC_LL_Private_Macros
57 * @{
58 */
59 #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
60 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
63 #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
64 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
65 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
66 #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
67 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
69 #else
70 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
71 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
72
73 #if defined(UART4) && defined(UART5)
74 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
76 #elif defined(UART4)
77 #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
78 #elif defined(UART5)
79 #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
80 #endif /* UART4 && UART5*/
81
82 #if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
83 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
84 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
85 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
86
87 #elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
88 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
89 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
90
91 #elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
92 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
93 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
94
95 #else
96 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
97 #endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
98
99 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
100
101 #if defined(USB)
102 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
103 #endif /* USB */
104
105 #if defined(RCC_CFGR_ADCPRE)
106 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
107 #else
108 #if defined(RCC_CFGR2_ADC1PRES)
109 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
110 #elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
111 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
112 || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
113 #else /* RCC_CFGR2_ADCPRE12 */
114 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
115 #endif /* RCC_CFGR2_ADC1PRES */
116 #endif /* RCC_CFGR_ADCPRE */
117
118 #if defined(RCC_CFGR_SDPRE)
119 #define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
120 #endif /* RCC_CFGR_SDPRE */
121
122 #if defined(CEC)
123 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
124 #endif /* CEC */
125
126 #if defined(RCC_CFGR3_TIMSW)
127 #if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
128 && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
129 && defined(RCC_CFGR3_TIM34SW)
130
131 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
132 || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
133 || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
134 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
135 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
136 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
137 || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
138 || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
139
140 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
141 && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
142 && defined(RCC_CFGR3_TIM34SW)
143
144 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
145 || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
146 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
147 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
148 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
149 || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
150
151 #elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
152 && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
153 && !defined(RCC_CFGR3_TIM34SW)
154
155 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
156 || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
157
158 #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
159 && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
160 && !defined(RCC_CFGR3_TIM34SW)
161
162 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
163 || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
164 || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
165 || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
166
167 #elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
168 && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
169 && !defined(RCC_CFGR3_TIM34SW)
170
171 #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
172
173 #else
174 #error "Miss macro"
175 #endif /* RCC_CFGR3_TIMxSW */
176 #endif /* RCC_CFGR3_TIMSW */
177
178 #if defined(HRTIM1)
179 #define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
180 #endif /* HRTIM1 */
181
182 /**
183 * @}
184 */
185
186 /* Private function prototypes -----------------------------------------------*/
187 /** @defgroup RCC_LL_Private_Functions RCC Private functions
188 * @{
189 */
190 uint32_t RCC_GetSystemClockFreq(void);
191 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
192 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
193 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
194 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
195 /**
196 * @}
197 */
198
199
200 /* Exported functions --------------------------------------------------------*/
201 /** @addtogroup RCC_LL_Exported_Functions
202 * @{
203 */
204
205 /** @addtogroup RCC_LL_EF_Init
206 * @{
207 */
208
209 /**
210 * @brief Reset the RCC clock configuration to the default reset state.
211 * @note The default reset state of the clock configuration is given below:
212 * - HSI ON and used as system clock source
213 * - HSE and PLL OFF
214 * - AHB, APB1 and APB2 prescaler set to 1.
215 * - CSS, MCO OFF
216 * - All interrupts disabled
217 * @note This function doesn't modify the configuration of the
218 * - Peripheral clocks
219 * - LSI, LSE and RTC clocks
220 * @retval An ErrorStatus enumeration value:
221 * - SUCCESS: RCC registers are de-initialized
222 * - ERROR: not applicable
223 */
LL_RCC_DeInit(void)224 ErrorStatus LL_RCC_DeInit(void)
225 {
226 __IO uint32_t vl_mask;
227
228 /* Set HSION bit */
229 LL_RCC_HSI_Enable();
230
231 /* Wait for HSI READY bit */
232 while(LL_RCC_HSI_IsReady() != 1U)
233 {}
234
235 /* Set HSITRIM bits to the reset value*/
236 LL_RCC_HSI_SetCalibTrimming(0x10U);
237
238 /* Reset SW, HPRE, PPRE and MCOSEL bits */
239 vl_mask = 0xFFFFFFFFU;
240 CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 |\
241 RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
242
243 /* Write new value in CFGR register */
244 LL_RCC_WriteReg(CFGR, vl_mask);
245
246 /* Wait till system clock source is ready */
247 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
248 {}
249
250 /* Read CR register */
251 vl_mask = LL_RCC_ReadReg(CR);
252
253 /* Reset HSEON, CSSON, PLLON bits */
254 CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
255
256 /* Write new value in CR register */
257 LL_RCC_WriteReg(CR, vl_mask);
258
259 /* Wait for PLL READY bit to be reset */
260 while(LL_RCC_PLL_IsReady() != 0U)
261 {}
262
263 /* Reset HSEBYP bit */
264 LL_RCC_HSE_DisableBypass();
265
266 /* Reset CFGR register */
267 LL_RCC_WriteReg(CFGR, 0x00000000U);
268
269 /* Reset CFGR2 register */
270 LL_RCC_WriteReg(CFGR2, 0x00000000U);
271
272 /* Reset CFGR3 register */
273 LL_RCC_WriteReg(CFGR3, 0x00000000U);
274
275 /* Clear pending flags */
276 vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC |\
277 LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
278
279 /* Write new value in CIR register */
280 LL_RCC_WriteReg(CIR, vl_mask);
281
282 /* Disable all interrupts */
283 LL_RCC_WriteReg(CIR, 0x00000000U);
284
285 /* Clear reset flags */
286 LL_RCC_ClearResetFlags();
287
288 return SUCCESS;
289 }
290
291 /**
292 * @}
293 */
294
295 /** @addtogroup RCC_LL_EF_Get_Freq
296 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
297 * and different peripheral clocks available on the device.
298 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
299 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
300 * @note If SYSCLK source is PLL, function returns values based on
301 * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
302 * @note (**) HSI_VALUE is a defined constant but the real value may vary
303 * depending on the variations in voltage and temperature.
304 * @note (***) HSE_VALUE is a defined constant, user has to ensure that
305 * HSE_VALUE is same as the real frequency of the crystal used.
306 * Otherwise, this function may have wrong result.
307 * @note The result of this function could be incorrect when using fractional
308 * value for HSE crystal.
309 * @note This function can be used by the user application to compute the
310 * baud-rate for the communication peripherals or configure other parameters.
311 * @{
312 */
313
314 /**
315 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
316 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
317 * must be called to update structure fields. Otherwise, any
318 * configuration based on this function will be incorrect.
319 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
320 * @retval None
321 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)322 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
323 {
324 /* Get SYSCLK frequency */
325 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
326
327 /* HCLK clock frequency */
328 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
329
330 /* PCLK1 clock frequency */
331 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
332
333 /* PCLK2 clock frequency */
334 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
335 }
336
337 /**
338 * @brief Return USARTx clock frequency
339 * @param USARTxSource This parameter can be one of the following values:
340 * @arg @ref LL_RCC_USART1_CLKSOURCE
341 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
342 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
343 *
344 * (*) value not defined in all devices.
345 * @retval USART clock frequency (in Hz)
346 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
347 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)348 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
349 {
350 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
351
352 /* Check parameter */
353 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
354 #if defined(RCC_CFGR3_USART1SW)
355 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
356 {
357 /* USART1CLK clock frequency */
358 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
359 {
360 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
361 usart_frequency = RCC_GetSystemClockFreq();
362 break;
363
364 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
365 if (LL_RCC_HSI_IsReady())
366 {
367 usart_frequency = HSI_VALUE;
368 }
369 break;
370
371 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
372 if (LL_RCC_LSE_IsReady())
373 {
374 usart_frequency = LSE_VALUE;
375 }
376 break;
377
378 #if defined(RCC_CFGR3_USART1SW_PCLK1)
379 case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
380 default:
381 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
382 #else
383 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
384 default:
385 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
386 #endif /* RCC_CFGR3_USART1SW_PCLK1 */
387 break;
388 }
389 }
390 #endif /* RCC_CFGR3_USART1SW */
391
392 #if defined(RCC_CFGR3_USART2SW)
393 if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
394 {
395 /* USART2CLK clock frequency */
396 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
397 {
398 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
399 usart_frequency = RCC_GetSystemClockFreq();
400 break;
401
402 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
403 if (LL_RCC_HSI_IsReady())
404 {
405 usart_frequency = HSI_VALUE;
406 }
407 break;
408
409 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
410 if (LL_RCC_LSE_IsReady())
411 {
412 usart_frequency = LSE_VALUE;
413 }
414 break;
415
416 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
417 default:
418 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
419 break;
420 }
421 }
422 #endif /* RCC_CFGR3_USART2SW */
423
424 #if defined(RCC_CFGR3_USART3SW)
425 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
426 {
427 /* USART3CLK clock frequency */
428 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
429 {
430 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
431 usart_frequency = RCC_GetSystemClockFreq();
432 break;
433
434 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
435 if (LL_RCC_HSI_IsReady())
436 {
437 usart_frequency = HSI_VALUE;
438 }
439 break;
440
441 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
442 if (LL_RCC_LSE_IsReady())
443 {
444 usart_frequency = LSE_VALUE;
445 }
446 break;
447
448 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
449 default:
450 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
451 break;
452 }
453 }
454
455 #endif /* RCC_CFGR3_USART3SW */
456 return usart_frequency;
457 }
458
459 #if defined(UART4) || defined(UART5)
460 /**
461 * @brief Return UARTx clock frequency
462 * @param UARTxSource This parameter can be one of the following values:
463 * @arg @ref LL_RCC_UART4_CLKSOURCE
464 * @arg @ref LL_RCC_UART5_CLKSOURCE
465 * @retval UART clock frequency (in Hz)
466 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
467 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)468 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
469 {
470 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
471
472 /* Check parameter */
473 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
474
475 #if defined(UART4)
476 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
477 {
478 /* UART4CLK clock frequency */
479 switch (LL_RCC_GetUARTClockSource(UARTxSource))
480 {
481 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
482 uart_frequency = RCC_GetSystemClockFreq();
483 break;
484
485 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
486 if (LL_RCC_HSI_IsReady())
487 {
488 uart_frequency = HSI_VALUE;
489 }
490 break;
491
492 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
493 if (LL_RCC_LSE_IsReady())
494 {
495 uart_frequency = LSE_VALUE;
496 }
497 break;
498
499 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
500 default:
501 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
502 break;
503 }
504 }
505 #endif /* UART4 */
506
507 #if defined(UART5)
508 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
509 {
510 /* UART5CLK clock frequency */
511 switch (LL_RCC_GetUARTClockSource(UARTxSource))
512 {
513 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
514 uart_frequency = RCC_GetSystemClockFreq();
515 break;
516
517 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
518 if (LL_RCC_HSI_IsReady())
519 {
520 uart_frequency = HSI_VALUE;
521 }
522 break;
523
524 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
525 if (LL_RCC_LSE_IsReady())
526 {
527 uart_frequency = LSE_VALUE;
528 }
529 break;
530
531 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
532 default:
533 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
534 break;
535 }
536 }
537 #endif /* UART5 */
538
539 return uart_frequency;
540 }
541 #endif /* UART4 || UART5 */
542
543 /**
544 * @brief Return I2Cx clock frequency
545 * @param I2CxSource This parameter can be one of the following values:
546 * @arg @ref LL_RCC_I2C1_CLKSOURCE
547 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
548 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
549 *
550 * (*) value not defined in all devices
551 * @retval I2C clock frequency (in Hz)
552 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
553 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)554 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
555 {
556 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
557
558 /* Check parameter */
559 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
560
561 /* I2C1 CLK clock frequency */
562 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
563 {
564 switch (LL_RCC_GetI2CClockSource(I2CxSource))
565 {
566 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
567 i2c_frequency = RCC_GetSystemClockFreq();
568 break;
569
570 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
571 default:
572 if (LL_RCC_HSI_IsReady())
573 {
574 i2c_frequency = HSI_VALUE;
575 }
576 break;
577 }
578 }
579
580 #if defined(RCC_CFGR3_I2C2SW)
581 /* I2C2 CLK clock frequency */
582 if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
583 {
584 switch (LL_RCC_GetI2CClockSource(I2CxSource))
585 {
586 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
587 i2c_frequency = RCC_GetSystemClockFreq();
588 break;
589
590 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
591 default:
592 if (LL_RCC_HSI_IsReady())
593 {
594 i2c_frequency = HSI_VALUE;
595 }
596 break;
597 }
598 }
599 #endif /*RCC_CFGR3_I2C2SW*/
600
601 #if defined(RCC_CFGR3_I2C3SW)
602 /* I2C3 CLK clock frequency */
603 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
604 {
605 switch (LL_RCC_GetI2CClockSource(I2CxSource))
606 {
607 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
608 i2c_frequency = RCC_GetSystemClockFreq();
609 break;
610
611 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
612 default:
613 if (LL_RCC_HSI_IsReady())
614 {
615 i2c_frequency = HSI_VALUE;
616 }
617 break;
618 }
619 }
620 #endif /*RCC_CFGR3_I2C3SW*/
621
622 return i2c_frequency;
623 }
624
625 #if defined(RCC_CFGR_I2SSRC)
626 /**
627 * @brief Return I2Sx clock frequency
628 * @param I2SxSource This parameter can be one of the following values:
629 * @arg @ref LL_RCC_I2S_CLKSOURCE
630 * @retval I2S clock frequency (in Hz)
631 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)632 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
633 {
634 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
635
636 /* Check parameter */
637 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
638
639 /* I2S1CLK clock frequency */
640 switch (LL_RCC_GetI2SClockSource(I2SxSource))
641 {
642 case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
643 i2s_frequency = RCC_GetSystemClockFreq();
644 break;
645
646 /* If an external I2S clock has to be used, LL_RCC_SetI2SClockSource(LL_RCC_I2S_CLKSOURCE_PIN)
647 have to be called in the main after calling SystemClock_Config() */
648 case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
649 i2s_frequency = EXTERNAL_CLOCK_VALUE;
650 break;
651 default:
652 i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
653 break;
654 }
655
656 return i2s_frequency;
657 }
658 #endif /* RCC_CFGR_I2SSRC */
659 #if defined(USB)
660 /**
661 * @brief Return USBx clock frequency
662 * @param USBxSource This parameter can be one of the following values:
663 * @arg @ref LL_RCC_USB_CLKSOURCE
664 * @retval USB clock frequency (in Hz)
665 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
666 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
667 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)668 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
669 {
670 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
671
672 /* Check parameter */
673 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
674
675 /* USBCLK clock frequency */
676 switch (LL_RCC_GetUSBClockSource(USBxSource))
677 {
678 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
679 if (LL_RCC_PLL_IsReady())
680 {
681 usb_frequency = RCC_PLL_GetFreqDomain_SYS();
682 }
683 break;
684
685 case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
686 default:
687 if (LL_RCC_PLL_IsReady())
688 {
689 usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
690 }
691 break;
692 }
693
694 return usb_frequency;
695 }
696 #endif /* USB */
697
698 #if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
699 /**
700 * @brief Return ADCx clock frequency
701 * @param ADCxSource This parameter can be one of the following values:
702 * @arg @ref LL_RCC_ADC_CLKSOURCE (*)
703 * @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
704 * @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
705 * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
706 *
707 * (*) value not defined in all devices
708 * @retval ADC clock frequency (in Hz)
709 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)710 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
711 {
712 uint32_t adc_prescaler = 0U;
713 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
714
715 /* Check parameter */
716 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
717
718 /* Get ADC prescaler */
719 adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
720
721 #if defined(RCC_CFGR_ADCPRE)
722 /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
723 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
724 / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
725 #else
726 if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
727 {
728 /* ADC frequency = HCLK frequency */
729 adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
730 }
731 else
732 {
733 /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
734 adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
735 / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
736 }
737 #endif /* RCC_CFGR_ADCPRE */
738
739 return adc_frequency;
740 }
741 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
742
743 #if defined(RCC_CFGR_SDPRE)
744 /**
745 * @brief Return SDADCx clock frequency
746 * @param SDADCxSource This parameter can be one of the following values:
747 * @arg @ref LL_RCC_SDADC_CLKSOURCE
748 * @retval SDADC clock frequency (in Hz)
749 */
LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)750 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
751 {
752 uint32_t sdadc_prescaler = 0U;
753 uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
754
755 /* Check parameter */
756 assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
757
758 /* Get SDADC prescaler */
759 sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
760
761 /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
762 sdadc_frequency = RCC_GetSystemClockFreq()
763 / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
764
765 return sdadc_frequency;
766 }
767 #endif /*RCC_CFGR_SDPRE */
768
769 #if defined(CEC)
770 /**
771 * @brief Return CECx clock frequency
772 * @param CECxSource This parameter can be one of the following values:
773 * @arg @ref LL_RCC_CEC_CLKSOURCE
774 * @retval CEC clock frequency (in Hz)
775 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
776 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)777 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
778 {
779 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
780
781 /* Check parameter */
782 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
783
784 /* CECCLK clock frequency */
785 switch (LL_RCC_GetCECClockSource(CECxSource))
786 {
787 case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
788 if (LL_RCC_HSI_IsReady())
789 {
790 cec_frequency = HSI_VALUE / 244U;
791 }
792 break;
793
794 case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
795 default:
796 if (LL_RCC_LSE_IsReady())
797 {
798 cec_frequency = LSE_VALUE;
799 }
800 break;
801 }
802
803 return cec_frequency;
804 }
805 #endif /* CEC */
806
807 #if defined(RCC_CFGR3_TIMSW)
808 /**
809 * @brief Return TIMx clock frequency
810 * @param TIMxSource This parameter can be one of the following values:
811 * @arg @ref LL_RCC_TIM1_CLKSOURCE
812 * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
813 * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
814 * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
815 * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
816 * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
817 * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
818 * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
819 *
820 * (*) value not defined in all devices
821 * @retval TIM clock frequency (in Hz)
822 */
LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)823 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
824 {
825 uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
826
827 /* Check parameter */
828 assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
829
830 if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
831 {
832 /* TIM1CLK clock frequency */
833 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
834 {
835 /* PCLK2 used as TIM1 clock source */
836 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
837 }
838 else /* LL_RCC_TIM1_CLKSOURCE_PLL */
839 {
840 /* PLL clock used as TIM1 clock source */
841 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
842 }
843 }
844
845 #if defined(RCC_CFGR3_TIM8SW)
846 if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
847 {
848 /* TIM8CLK clock frequency */
849 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
850 {
851 /* PCLK2 used as TIM8 clock source */
852 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
853 }
854 else /* LL_RCC_TIM8_CLKSOURCE_PLL */
855 {
856 /* PLL clock used as TIM8 clock source */
857 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
858 }
859 }
860 #endif /*RCC_CFGR3_TIM8SW*/
861
862 #if defined(RCC_CFGR3_TIM15SW)
863 if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
864 {
865 /* TIM15CLK clock frequency */
866 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
867 {
868 /* PCLK2 used as TIM15 clock source */
869 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
870 }
871 else /* LL_RCC_TIM15_CLKSOURCE_PLL */
872 {
873 /* PLL clock used as TIM15 clock source */
874 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
875 }
876 }
877 #endif /*RCC_CFGR3_TIM15SW*/
878
879 #if defined(RCC_CFGR3_TIM16SW)
880 if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
881 {
882 /* TIM16CLK clock frequency */
883 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
884 {
885 /* PCLK2 used as TIM16 clock source */
886 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
887 }
888 else /* LL_RCC_TIM16_CLKSOURCE_PLL */
889 {
890 /* PLL clock used as TIM16 clock source */
891 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
892 }
893 }
894 #endif /*RCC_CFGR3_TIM16SW*/
895
896 #if defined(RCC_CFGR3_TIM17SW)
897 if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
898 {
899 /* TIM17CLK clock frequency */
900 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
901 {
902 /* PCLK2 used as TIM17 clock source */
903 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
904 }
905 else /* LL_RCC_TIM17_CLKSOURCE_PLL */
906 {
907 /* PLL clock used as TIM17 clock source */
908 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
909 }
910 }
911 #endif /*RCC_CFGR3_TIM17SW*/
912
913 #if defined(RCC_CFGR3_TIM20SW)
914 if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
915 {
916 /* TIM20CLK clock frequency */
917 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
918 {
919 /* PCLK2 used as TIM20 clock source */
920 tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
921 }
922 else /* LL_RCC_TIM20_CLKSOURCE_PLL */
923 {
924 /* PLL clock used as TIM20 clock source */
925 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
926 }
927 }
928 #endif /*RCC_CFGR3_TIM20SW*/
929
930 #if defined(RCC_CFGR3_TIM2SW)
931 if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
932 {
933 /* TIM2CLK clock frequency */
934 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
935 {
936 /* PCLK1 used as TIM2 clock source */
937 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
938 }
939 else /* LL_RCC_TIM2_CLKSOURCE_PLL */
940 {
941 /* PLL clock used as TIM2 clock source */
942 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
943 }
944 }
945 #endif /*RCC_CFGR3_TIM2SW*/
946
947 #if defined(RCC_CFGR3_TIM34SW)
948 if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
949 {
950 /* TIM3/4 CLK clock frequency */
951 if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
952 {
953 /* PCLK1 used as TIM3/4 clock source */
954 tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
955 }
956 else /* LL_RCC_TIM34_CLKSOURCE_PLL */
957 {
958 /* PLL clock used as TIM3/4 clock source */
959 tim_frequency = RCC_PLL_GetFreqDomain_SYS();
960 }
961 }
962 #endif /*RCC_CFGR3_TIM34SW*/
963
964 return tim_frequency;
965 }
966 #endif /*RCC_CFGR3_TIMSW*/
967
968 #if defined(HRTIM1)
969 /**
970 * @brief Return HRTIMx clock frequency
971 * @param HRTIMxSource This parameter can be one of the following values:
972 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
973 * @retval HRTIM clock frequency (in Hz)
974 */
LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)975 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
976 {
977 uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
978
979 /* Check parameter */
980 assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
981
982 /* HRTIM1CLK clock frequency */
983 if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
984 {
985 /* PCLK2 used as HRTIM1 clock source */
986 hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
987 }
988 else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
989 {
990 /* PLL clock used as HRTIM1 clock source */
991 hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
992 }
993
994 return hrtim_frequency;
995 }
996 #endif /* HRTIM1 */
997
998 /**
999 * @}
1000 */
1001
1002 /**
1003 * @}
1004 */
1005
1006 /** @addtogroup RCC_LL_Private_Functions
1007 * @{
1008 */
1009
1010 /**
1011 * @brief Return SYSTEM clock frequency
1012 * @retval SYSTEM clock frequency (in Hz)
1013 */
RCC_GetSystemClockFreq(void)1014 uint32_t RCC_GetSystemClockFreq(void)
1015 {
1016 uint32_t frequency = 0U;
1017
1018 /* Get SYSCLK source -------------------------------------------------------*/
1019 switch (LL_RCC_GetSysClkSource())
1020 {
1021 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1022 frequency = HSI_VALUE;
1023 break;
1024
1025 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1026 frequency = HSE_VALUE;
1027 break;
1028
1029 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1030 frequency = RCC_PLL_GetFreqDomain_SYS();
1031 break;
1032
1033 default:
1034 frequency = HSI_VALUE;
1035 break;
1036 }
1037
1038 return frequency;
1039 }
1040
1041 /**
1042 * @brief Return HCLK clock frequency
1043 * @param SYSCLK_Frequency SYSCLK clock frequency
1044 * @retval HCLK clock frequency (in Hz)
1045 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1046 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1047 {
1048 /* HCLK clock frequency */
1049 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1050 }
1051
1052 /**
1053 * @brief Return PCLK1 clock frequency
1054 * @param HCLK_Frequency HCLK clock frequency
1055 * @retval PCLK1 clock frequency (in Hz)
1056 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1057 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1058 {
1059 /* PCLK1 clock frequency */
1060 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1061 }
1062
1063 /**
1064 * @brief Return PCLK2 clock frequency
1065 * @param HCLK_Frequency HCLK clock frequency
1066 * @retval PCLK2 clock frequency (in Hz)
1067 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1068 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1069 {
1070 /* PCLK2 clock frequency */
1071 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1072 }
1073
1074 /**
1075 * @brief Return PLL clock frequency used for system domain
1076 * @retval PLL clock frequency (in Hz)
1077 */
RCC_PLL_GetFreqDomain_SYS(void)1078 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1079 {
1080 uint32_t pllinputfreq = 0U, pllsource = 0U;
1081
1082 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
1083
1084 /* Get PLL source */
1085 pllsource = LL_RCC_PLL_GetMainSource();
1086
1087 switch (pllsource)
1088 {
1089 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1090 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1091 pllinputfreq = HSI_VALUE;
1092 #else
1093 case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
1094 pllinputfreq = HSI_VALUE / 2U;
1095 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1096 break;
1097
1098 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1099 pllinputfreq = HSE_VALUE;
1100 break;
1101
1102 default:
1103 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1104 pllinputfreq = HSI_VALUE;
1105 #else
1106 pllinputfreq = HSI_VALUE / 2U;
1107 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1108 break;
1109 }
1110 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
1111 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
1112 #else
1113 return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
1114 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
1115 }
1116 /**
1117 * @}
1118 */
1119
1120 /**
1121 * @}
1122 */
1123
1124 #endif /* defined(RCC) */
1125
1126 /**
1127 * @}
1128 */
1129
1130 #endif /* USE_FULL_LL_DRIVER */
1131
1132 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1133
