1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) MPU API to configure and enable regions
17 (MPU services provided only on some devices)
18 (+) API to access to MCU info (CPUID register)
19 (+) API to enable fault handler (SHCSR accesses)
20
21 @endverbatim
22 ******************************************************************************
23 * @attention
24 *
25 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
26 * All rights reserved.</center></h2>
27 *
28 * This software component is licensed by ST under BSD 3-Clause license,
29 * the "License"; You may not use this file except in compliance with the
30 * License. You may obtain a copy of the License at:
31 * opensource.org/licenses/BSD-3-Clause
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F2xx_LL_CORTEX_H
38 #define __STM32F2xx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f2xx.h"
46
47 /** @addtogroup STM32F2xx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
65 * @{
66 */
67
68 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
69 * @{
70 */
71 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
72 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
73 /**
74 * @}
75 */
76
77 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
78 * @{
79 */
80 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
81 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
82 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
83 /**
84 * @}
85 */
86
87 #if __MPU_PRESENT
88
89 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
90 * @{
91 */
92 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
93 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
94 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
95 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
96 /**
97 * @}
98 */
99
100 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
101 * @{
102 */
103 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
104 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
105 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
106 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
107 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
108 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
109 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
110 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
111 /**
112 * @}
113 */
114
115 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
116 * @{
117 */
118 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
119 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
120 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
146 /**
147 * @}
148 */
149
150 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
151 * @{
152 */
153 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
154 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
155 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
156 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
157 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
158 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
159 /**
160 * @}
161 */
162
163 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
164 * @{
165 */
166 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
167 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
168 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
169 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
175 * @{
176 */
177 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
178 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
179 /**
180 * @}
181 */
182
183 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
184 * @{
185 */
186 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
187 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
188 /**
189 * @}
190 */
191
192 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
193 * @{
194 */
195 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
196 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
197 /**
198 * @}
199 */
200
201 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
202 * @{
203 */
204 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
205 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
206 /**
207 * @}
208 */
209 #endif /* __MPU_PRESENT */
210 /**
211 * @}
212 */
213
214 /* Exported macro ------------------------------------------------------------*/
215
216 /* Exported functions --------------------------------------------------------*/
217 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
218 * @{
219 */
220
221 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
222 * @{
223 */
224
225 /**
226 * @brief This function checks if the Systick counter flag is active or not.
227 * @note It can be used in timeout function on application side.
228 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
229 * @retval State of bit (1 or 0).
230 */
LL_SYSTICK_IsActiveCounterFlag(void)231 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
232 {
233 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
234 }
235
236 /**
237 * @brief Configures the SysTick clock source
238 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
239 * @param Source This parameter can be one of the following values:
240 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
241 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
242 * @retval None
243 */
LL_SYSTICK_SetClkSource(uint32_t Source)244 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
245 {
246 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
247 {
248 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
249 }
250 else
251 {
252 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
253 }
254 }
255
256 /**
257 * @brief Get the SysTick clock source
258 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
259 * @retval Returned value can be one of the following values:
260 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
261 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
262 */
LL_SYSTICK_GetClkSource(void)263 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
264 {
265 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
266 }
267
268 /**
269 * @brief Enable SysTick exception request
270 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
271 * @retval None
272 */
LL_SYSTICK_EnableIT(void)273 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
274 {
275 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
276 }
277
278 /**
279 * @brief Disable SysTick exception request
280 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
281 * @retval None
282 */
LL_SYSTICK_DisableIT(void)283 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
284 {
285 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
286 }
287
288 /**
289 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
290 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
291 * @retval State of bit (1 or 0).
292 */
LL_SYSTICK_IsEnabledIT(void)293 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
294 {
295 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
296 }
297
298 /**
299 * @}
300 */
301
302 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
303 * @{
304 */
305
306 /**
307 * @brief Processor uses sleep as its low power mode
308 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
309 * @retval None
310 */
LL_LPM_EnableSleep(void)311 __STATIC_INLINE void LL_LPM_EnableSleep(void)
312 {
313 /* Clear SLEEPDEEP bit of Cortex System Control Register */
314 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
315 }
316
317 /**
318 * @brief Processor uses deep sleep as its low power mode
319 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
320 * @retval None
321 */
LL_LPM_EnableDeepSleep(void)322 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
323 {
324 /* Set SLEEPDEEP bit of Cortex System Control Register */
325 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
326 }
327
328 /**
329 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
330 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
331 * empty main application.
332 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
333 * @retval None
334 */
LL_LPM_EnableSleepOnExit(void)335 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
336 {
337 /* Set SLEEPONEXIT bit of Cortex System Control Register */
338 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
339 }
340
341 /**
342 * @brief Do not sleep when returning to Thread mode.
343 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
344 * @retval None
345 */
LL_LPM_DisableSleepOnExit(void)346 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
347 {
348 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
349 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
350 }
351
352 /**
353 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
354 * processor.
355 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
356 * @retval None
357 */
LL_LPM_EnableEventOnPend(void)358 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
359 {
360 /* Set SEVEONPEND bit of Cortex System Control Register */
361 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
362 }
363
364 /**
365 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
366 * excluded
367 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
368 * @retval None
369 */
LL_LPM_DisableEventOnPend(void)370 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
371 {
372 /* Clear SEVEONPEND bit of Cortex System Control Register */
373 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
374 }
375
376 /**
377 * @}
378 */
379
380 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
381 * @{
382 */
383
384 /**
385 * @brief Enable a fault in System handler control register (SHCSR)
386 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
387 * @param Fault This parameter can be a combination of the following values:
388 * @arg @ref LL_HANDLER_FAULT_USG
389 * @arg @ref LL_HANDLER_FAULT_BUS
390 * @arg @ref LL_HANDLER_FAULT_MEM
391 * @retval None
392 */
LL_HANDLER_EnableFault(uint32_t Fault)393 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
394 {
395 /* Enable the system handler fault */
396 SET_BIT(SCB->SHCSR, Fault);
397 }
398
399 /**
400 * @brief Disable a fault in System handler control register (SHCSR)
401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
402 * @param Fault This parameter can be a combination of the following values:
403 * @arg @ref LL_HANDLER_FAULT_USG
404 * @arg @ref LL_HANDLER_FAULT_BUS
405 * @arg @ref LL_HANDLER_FAULT_MEM
406 * @retval None
407 */
LL_HANDLER_DisableFault(uint32_t Fault)408 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
409 {
410 /* Disable the system handler fault */
411 CLEAR_BIT(SCB->SHCSR, Fault);
412 }
413
414 /**
415 * @}
416 */
417
418 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
419 * @{
420 */
421
422 /**
423 * @brief Get Implementer code
424 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
425 * @retval Value should be equal to 0x41 for ARM
426 */
LL_CPUID_GetImplementer(void)427 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
428 {
429 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
430 }
431
432 /**
433 * @brief Get Variant number (The r value in the rnpn product revision identifier)
434 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
435 * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
436 */
LL_CPUID_GetVariant(void)437 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
438 {
439 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
440 }
441
442 /**
443 * @brief Get Constant number
444 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
445 * @retval Value should be equal to 0xF for Cortex-M3 devices
446 */
LL_CPUID_GetConstant(void)447 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
448 {
449 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
450 }
451
452 /**
453 * @brief Get Part number
454 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
455 * @retval Value should be equal to 0xC23 for Cortex-M3
456 */
LL_CPUID_GetParNo(void)457 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
458 {
459 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
460 }
461
462 /**
463 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
464 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
465 * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
466 */
LL_CPUID_GetRevision(void)467 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
468 {
469 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
470 }
471
472 /**
473 * @}
474 */
475
476 #if __MPU_PRESENT
477 /** @defgroup CORTEX_LL_EF_MPU MPU
478 * @{
479 */
480
481 /**
482 * @brief Enable MPU with input options
483 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
484 * @param Options This parameter can be one of the following values:
485 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
486 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
487 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
488 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
489 * @retval None
490 */
LL_MPU_Enable(uint32_t Options)491 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
492 {
493 /* Enable the MPU*/
494 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
495 /* Ensure MPU settings take effects */
496 __DSB();
497 /* Sequence instruction fetches using update settings */
498 __ISB();
499 }
500
501 /**
502 * @brief Disable MPU
503 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
504 * @retval None
505 */
LL_MPU_Disable(void)506 __STATIC_INLINE void LL_MPU_Disable(void)
507 {
508 /* Make sure outstanding transfers are done */
509 __DMB();
510 /* Disable MPU*/
511 WRITE_REG(MPU->CTRL, 0U);
512 }
513
514 /**
515 * @brief Check if MPU is enabled or not
516 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
517 * @retval State of bit (1 or 0).
518 */
LL_MPU_IsEnabled(void)519 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
520 {
521 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
522 }
523
524 /**
525 * @brief Enable a MPU region
526 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
527 * @param Region This parameter can be one of the following values:
528 * @arg @ref LL_MPU_REGION_NUMBER0
529 * @arg @ref LL_MPU_REGION_NUMBER1
530 * @arg @ref LL_MPU_REGION_NUMBER2
531 * @arg @ref LL_MPU_REGION_NUMBER3
532 * @arg @ref LL_MPU_REGION_NUMBER4
533 * @arg @ref LL_MPU_REGION_NUMBER5
534 * @arg @ref LL_MPU_REGION_NUMBER6
535 * @arg @ref LL_MPU_REGION_NUMBER7
536 * @retval None
537 */
LL_MPU_EnableRegion(uint32_t Region)538 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
539 {
540 /* Set Region number */
541 WRITE_REG(MPU->RNR, Region);
542 /* Enable the MPU region */
543 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
544 }
545
546 /**
547 * @brief Configure and enable a region
548 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
549 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
550 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
551 * MPU_RASR XN LL_MPU_ConfigRegion\n
552 * MPU_RASR AP LL_MPU_ConfigRegion\n
553 * MPU_RASR S LL_MPU_ConfigRegion\n
554 * MPU_RASR C LL_MPU_ConfigRegion\n
555 * MPU_RASR B LL_MPU_ConfigRegion\n
556 * MPU_RASR SIZE LL_MPU_ConfigRegion
557 * @param Region This parameter can be one of the following values:
558 * @arg @ref LL_MPU_REGION_NUMBER0
559 * @arg @ref LL_MPU_REGION_NUMBER1
560 * @arg @ref LL_MPU_REGION_NUMBER2
561 * @arg @ref LL_MPU_REGION_NUMBER3
562 * @arg @ref LL_MPU_REGION_NUMBER4
563 * @arg @ref LL_MPU_REGION_NUMBER5
564 * @arg @ref LL_MPU_REGION_NUMBER6
565 * @arg @ref LL_MPU_REGION_NUMBER7
566 * @param Address Value of region base address
567 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
568 * @param Attributes This parameter can be a combination of the following values:
569 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
570 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
571 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
572 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
573 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
574 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
575 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
576 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
577 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
578 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
579 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
580 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
581 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
582 * @retval None
583 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)584 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
585 {
586 /* Set Region number */
587 WRITE_REG(MPU->RNR, Region);
588 /* Set base address */
589 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
590 /* Configure MPU */
591 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
592 }
593
594 /**
595 * @brief Disable a region
596 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
597 * MPU_RASR ENABLE LL_MPU_DisableRegion
598 * @param Region This parameter can be one of the following values:
599 * @arg @ref LL_MPU_REGION_NUMBER0
600 * @arg @ref LL_MPU_REGION_NUMBER1
601 * @arg @ref LL_MPU_REGION_NUMBER2
602 * @arg @ref LL_MPU_REGION_NUMBER3
603 * @arg @ref LL_MPU_REGION_NUMBER4
604 * @arg @ref LL_MPU_REGION_NUMBER5
605 * @arg @ref LL_MPU_REGION_NUMBER6
606 * @arg @ref LL_MPU_REGION_NUMBER7
607 * @retval None
608 */
LL_MPU_DisableRegion(uint32_t Region)609 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
610 {
611 /* Set Region number */
612 WRITE_REG(MPU->RNR, Region);
613 /* Disable the MPU region */
614 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
615 }
616
617 /**
618 * @}
619 */
620
621 #endif /* __MPU_PRESENT */
622 /**
623 * @}
624 */
625
626 /**
627 * @}
628 */
629
630 /**
631 * @}
632 */
633
634 #ifdef __cplusplus
635 }
636 #endif
637
638 #endif /* __STM32F2xx_LL_CORTEX_H */
639
640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
641
