1 /** 2 ****************************************************************************** 3 * @file stm32f100xe.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral�s registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 29 /** @addtogroup CMSIS 30 * @{ 31 */ 32 33 /** @addtogroup stm32f100xe 34 * @{ 35 */ 36 37 #ifndef __STM32F100xE_H 38 #define __STM32F100xE_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /** @addtogroup Configuration_section_for_CMSIS 45 * @{ 46 */ 47 /** 48 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 49 */ 50 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ 51 #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ 52 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief STM32F10x Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 74 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 75 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 76 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 77 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 78 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 79 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 80 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 81 82 /****** STM32 specific Interrupt Numbers *********************************************************/ 83 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 84 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 85 TAMPER_IRQn = 2, /*!< Tamper Interrupt */ 86 RTC_IRQn = 3, /*!< RTC global Interrupt */ 87 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 88 RCC_IRQn = 5, /*!< RCC global Interrupt */ 89 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 90 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 91 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 92 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 93 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 94 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 95 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 96 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 97 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 98 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 99 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 100 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 101 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 103 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 104 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 105 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 121 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ 122 TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ 123 TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ 124 TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ 125 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ 126 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 127 UART4_IRQn = 52, /*!< UART4 global Interrupt */ 128 UART5_IRQn = 53, /*!< UART5 global Interrupt */ 129 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ 130 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ 131 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ 132 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ 133 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ 134 DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ 135 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ 136 DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is 137 mapped at position 60 only if the MISC_REMAP bit in 138 the AFIO_MAPR2 register is set) */ 139 } IRQn_Type; 140 141 /** 142 * @} 143 */ 144 145 #include "core_cm3.h" 146 #include "system_stm32f1xx.h" 147 #include <stdint.h> 148 149 /** @addtogroup Peripheral_registers_structures 150 * @{ 151 */ 152 153 /** 154 * @brief Analog to Digital Converter 155 */ 156 157 typedef struct 158 { 159 __IO uint32_t SR; 160 __IO uint32_t CR1; 161 __IO uint32_t CR2; 162 __IO uint32_t SMPR1; 163 __IO uint32_t SMPR2; 164 __IO uint32_t JOFR1; 165 __IO uint32_t JOFR2; 166 __IO uint32_t JOFR3; 167 __IO uint32_t JOFR4; 168 __IO uint32_t HTR; 169 __IO uint32_t LTR; 170 __IO uint32_t SQR1; 171 __IO uint32_t SQR2; 172 __IO uint32_t SQR3; 173 __IO uint32_t JSQR; 174 __IO uint32_t JDR1; 175 __IO uint32_t JDR2; 176 __IO uint32_t JDR3; 177 __IO uint32_t JDR4; 178 __IO uint32_t DR; 179 } ADC_TypeDef; 180 181 typedef struct 182 { 183 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ 184 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ 185 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ 186 uint32_t RESERVED[16]; 187 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ 188 } ADC_Common_TypeDef; 189 190 /** 191 * @brief Backup Registers 192 */ 193 194 typedef struct 195 { 196 uint32_t RESERVED0; 197 __IO uint32_t DR1; 198 __IO uint32_t DR2; 199 __IO uint32_t DR3; 200 __IO uint32_t DR4; 201 __IO uint32_t DR5; 202 __IO uint32_t DR6; 203 __IO uint32_t DR7; 204 __IO uint32_t DR8; 205 __IO uint32_t DR9; 206 __IO uint32_t DR10; 207 __IO uint32_t RTCCR; 208 __IO uint32_t CR; 209 __IO uint32_t CSR; 210 uint32_t RESERVED13[2]; 211 __IO uint32_t DR11; 212 __IO uint32_t DR12; 213 __IO uint32_t DR13; 214 __IO uint32_t DR14; 215 __IO uint32_t DR15; 216 __IO uint32_t DR16; 217 __IO uint32_t DR17; 218 __IO uint32_t DR18; 219 __IO uint32_t DR19; 220 __IO uint32_t DR20; 221 __IO uint32_t DR21; 222 __IO uint32_t DR22; 223 __IO uint32_t DR23; 224 __IO uint32_t DR24; 225 __IO uint32_t DR25; 226 __IO uint32_t DR26; 227 __IO uint32_t DR27; 228 __IO uint32_t DR28; 229 __IO uint32_t DR29; 230 __IO uint32_t DR30; 231 __IO uint32_t DR31; 232 __IO uint32_t DR32; 233 __IO uint32_t DR33; 234 __IO uint32_t DR34; 235 __IO uint32_t DR35; 236 __IO uint32_t DR36; 237 __IO uint32_t DR37; 238 __IO uint32_t DR38; 239 __IO uint32_t DR39; 240 __IO uint32_t DR40; 241 __IO uint32_t DR41; 242 __IO uint32_t DR42; 243 } BKP_TypeDef; 244 245 246 /** 247 * @brief Consumer Electronics Control (CEC) 248 */ 249 typedef struct 250 { 251 __IO uint32_t CFGR; 252 __IO uint32_t OAR; 253 __IO uint32_t PRES; 254 __IO uint32_t ESR; 255 __IO uint32_t CSR; 256 __IO uint32_t TXD; 257 __IO uint32_t RXD; 258 } CEC_TypeDef; 259 260 /** 261 * @brief CRC calculation unit 262 */ 263 264 typedef struct 265 { 266 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 267 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 268 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 269 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 270 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 271 } CRC_TypeDef; 272 273 /** 274 * @brief Digital to Analog Converter 275 */ 276 277 typedef struct 278 { 279 __IO uint32_t CR; 280 __IO uint32_t SWTRIGR; 281 __IO uint32_t DHR12R1; 282 __IO uint32_t DHR12L1; 283 __IO uint32_t DHR8R1; 284 __IO uint32_t DHR12R2; 285 __IO uint32_t DHR12L2; 286 __IO uint32_t DHR8R2; 287 __IO uint32_t DHR12RD; 288 __IO uint32_t DHR12LD; 289 __IO uint32_t DHR8RD; 290 __IO uint32_t DOR1; 291 __IO uint32_t DOR2; 292 __IO uint32_t SR; 293 } DAC_TypeDef; 294 295 /** 296 * @brief Debug MCU 297 */ 298 299 typedef struct 300 { 301 __IO uint32_t IDCODE; 302 __IO uint32_t CR; 303 }DBGMCU_TypeDef; 304 305 /** 306 * @brief DMA Controller 307 */ 308 309 typedef struct 310 { 311 __IO uint32_t CCR; 312 __IO uint32_t CNDTR; 313 __IO uint32_t CPAR; 314 __IO uint32_t CMAR; 315 } DMA_Channel_TypeDef; 316 317 typedef struct 318 { 319 __IO uint32_t ISR; 320 __IO uint32_t IFCR; 321 } DMA_TypeDef; 322 323 324 325 /** 326 * @brief External Interrupt/Event Controller 327 */ 328 329 typedef struct 330 { 331 __IO uint32_t IMR; 332 __IO uint32_t EMR; 333 __IO uint32_t RTSR; 334 __IO uint32_t FTSR; 335 __IO uint32_t SWIER; 336 __IO uint32_t PR; 337 } EXTI_TypeDef; 338 339 /** 340 * @brief FLASH Registers 341 */ 342 343 typedef struct 344 { 345 __IO uint32_t ACR; 346 __IO uint32_t KEYR; 347 __IO uint32_t OPTKEYR; 348 __IO uint32_t SR; 349 __IO uint32_t CR; 350 __IO uint32_t AR; 351 __IO uint32_t RESERVED; 352 __IO uint32_t OBR; 353 __IO uint32_t WRPR; 354 } FLASH_TypeDef; 355 356 /** 357 * @brief Option Bytes Registers 358 */ 359 360 typedef struct 361 { 362 __IO uint16_t RDP; 363 __IO uint16_t USER; 364 __IO uint16_t Data0; 365 __IO uint16_t Data1; 366 __IO uint16_t WRP0; 367 __IO uint16_t WRP1; 368 __IO uint16_t WRP2; 369 __IO uint16_t WRP3; 370 } OB_TypeDef; 371 372 /** 373 * @brief Flexible Static Memory Controller 374 */ 375 376 typedef struct 377 { 378 __IO uint32_t BTCR[8]; 379 } FSMC_Bank1_TypeDef; 380 381 /** 382 * @brief Flexible Static Memory Controller Bank1E 383 */ 384 385 typedef struct 386 { 387 __IO uint32_t BWTR[7]; 388 } FSMC_Bank1E_TypeDef; 389 390 /** 391 * @brief General Purpose I/O 392 */ 393 394 typedef struct 395 { 396 __IO uint32_t CRL; 397 __IO uint32_t CRH; 398 __IO uint32_t IDR; 399 __IO uint32_t ODR; 400 __IO uint32_t BSRR; 401 __IO uint32_t BRR; 402 __IO uint32_t LCKR; 403 } GPIO_TypeDef; 404 405 /** 406 * @brief Alternate Function I/O 407 */ 408 409 typedef struct 410 { 411 __IO uint32_t EVCR; 412 __IO uint32_t MAPR; 413 __IO uint32_t EXTICR[4]; 414 uint32_t RESERVED0; 415 __IO uint32_t MAPR2; 416 } AFIO_TypeDef; 417 /** 418 * @brief Inter Integrated Circuit Interface 419 */ 420 421 typedef struct 422 { 423 __IO uint32_t CR1; 424 __IO uint32_t CR2; 425 __IO uint32_t OAR1; 426 __IO uint32_t OAR2; 427 __IO uint32_t DR; 428 __IO uint32_t SR1; 429 __IO uint32_t SR2; 430 __IO uint32_t CCR; 431 __IO uint32_t TRISE; 432 } I2C_TypeDef; 433 434 /** 435 * @brief Independent WATCHDOG 436 */ 437 438 typedef struct 439 { 440 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 441 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 442 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 443 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 444 } IWDG_TypeDef; 445 446 /** 447 * @brief Power Control 448 */ 449 450 typedef struct 451 { 452 __IO uint32_t CR; 453 __IO uint32_t CSR; 454 } PWR_TypeDef; 455 456 /** 457 * @brief Reset and Clock Control 458 */ 459 460 typedef struct 461 { 462 __IO uint32_t CR; 463 __IO uint32_t CFGR; 464 __IO uint32_t CIR; 465 __IO uint32_t APB2RSTR; 466 __IO uint32_t APB1RSTR; 467 __IO uint32_t AHBENR; 468 __IO uint32_t APB2ENR; 469 __IO uint32_t APB1ENR; 470 __IO uint32_t BDCR; 471 __IO uint32_t CSR; 472 473 474 uint32_t RESERVED0; 475 __IO uint32_t CFGR2; 476 } RCC_TypeDef; 477 478 /** 479 * @brief Real-Time Clock 480 */ 481 482 typedef struct 483 { 484 __IO uint32_t CRH; 485 __IO uint32_t CRL; 486 __IO uint32_t PRLH; 487 __IO uint32_t PRLL; 488 __IO uint32_t DIVH; 489 __IO uint32_t DIVL; 490 __IO uint32_t CNTH; 491 __IO uint32_t CNTL; 492 __IO uint32_t ALRH; 493 __IO uint32_t ALRL; 494 } RTC_TypeDef; 495 496 /** 497 * @brief Serial Peripheral Interface 498 */ 499 500 typedef struct 501 { 502 __IO uint32_t CR1; 503 __IO uint32_t CR2; 504 __IO uint32_t SR; 505 __IO uint32_t DR; 506 __IO uint32_t CRCPR; 507 __IO uint32_t RXCRCR; 508 __IO uint32_t TXCRCR; 509 } SPI_TypeDef; 510 511 /** 512 * @brief TIM Timers 513 */ 514 typedef struct 515 { 516 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 517 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 518 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 519 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 520 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 521 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 522 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 523 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 524 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 525 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 526 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 527 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 528 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 529 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 530 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 531 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 532 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 533 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 534 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 535 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 536 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 537 }TIM_TypeDef; 538 539 540 /** 541 * @brief Universal Synchronous Asynchronous Receiver Transmitter 542 */ 543 544 typedef struct 545 { 546 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 547 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 548 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 549 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 550 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 551 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 552 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 553 } USART_TypeDef; 554 555 556 557 /** 558 * @brief Window WATCHDOG 559 */ 560 561 typedef struct 562 { 563 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 564 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 565 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 566 } WWDG_TypeDef; 567 568 /** 569 * @} 570 */ 571 572 /** @addtogroup Peripheral_memory_map 573 * @{ 574 */ 575 576 577 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 578 #define FLASH_BANK1_END 0x0807FFFFUL /*!< FLASH END address of bank1 */ 579 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 580 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 581 582 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ 583 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 584 585 #define FSMC_BASE 0x60000000UL /*!< FSMC base address */ 586 #define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */ 587 588 /*!< Peripheral memory map */ 589 #define APB1PERIPH_BASE PERIPH_BASE 590 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 591 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 592 593 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 594 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 595 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 596 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) 597 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 598 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 599 #define TIM12_BASE (APB1PERIPH_BASE + 0x00001800UL) 600 #define TIM13_BASE (APB1PERIPH_BASE + 0x00001C00UL) 601 #define TIM14_BASE (APB1PERIPH_BASE + 0x00002000UL) 602 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 603 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 604 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 605 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 606 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) 607 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 608 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 609 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) 610 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) 611 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 612 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 613 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) 614 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 615 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 616 #define CEC_BASE (APB1PERIPH_BASE + 0x00007800UL) 617 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) 618 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 619 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) 620 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) 621 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) 622 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) 623 #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) 624 #define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL) 625 #define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL) 626 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 627 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 628 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 629 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 630 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) 631 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 632 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 633 634 635 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 636 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) 637 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) 638 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) 639 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) 640 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) 641 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) 642 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) 643 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) 644 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) 645 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) 646 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) 647 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) 648 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) 649 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 650 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 651 652 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ 653 #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ 654 #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ 655 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ 656 657 658 #define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ 659 #define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ 660 #define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */ 661 #define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */ 662 #define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */ 663 664 665 #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL) /*!< FSMC Bank1 registers base address */ 666 #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL) /*!< FSMC Bank1E registers base address */ 667 668 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ 669 670 671 672 /** 673 * @} 674 */ 675 676 /** @addtogroup Peripheral_declaration 677 * @{ 678 */ 679 680 #define TIM2 ((TIM_TypeDef *)TIM2_BASE) 681 #define TIM3 ((TIM_TypeDef *)TIM3_BASE) 682 #define TIM4 ((TIM_TypeDef *)TIM4_BASE) 683 #define TIM5 ((TIM_TypeDef *)TIM5_BASE) 684 #define TIM6 ((TIM_TypeDef *)TIM6_BASE) 685 #define TIM7 ((TIM_TypeDef *)TIM7_BASE) 686 #define TIM12 ((TIM_TypeDef *)TIM12_BASE) 687 #define TIM13 ((TIM_TypeDef *)TIM13_BASE) 688 #define TIM14 ((TIM_TypeDef *)TIM14_BASE) 689 #define RTC ((RTC_TypeDef *)RTC_BASE) 690 #define WWDG ((WWDG_TypeDef *)WWDG_BASE) 691 #define IWDG ((IWDG_TypeDef *)IWDG_BASE) 692 #define SPI2 ((SPI_TypeDef *)SPI2_BASE) 693 #define SPI3 ((SPI_TypeDef *)SPI3_BASE) 694 #define USART2 ((USART_TypeDef *)USART2_BASE) 695 #define USART3 ((USART_TypeDef *)USART3_BASE) 696 #define UART4 ((USART_TypeDef *)UART4_BASE) 697 #define UART5 ((USART_TypeDef *)UART5_BASE) 698 #define I2C1 ((I2C_TypeDef *)I2C1_BASE) 699 #define I2C2 ((I2C_TypeDef *)I2C2_BASE) 700 #define BKP ((BKP_TypeDef *)BKP_BASE) 701 #define PWR ((PWR_TypeDef *)PWR_BASE) 702 #define DAC1 ((DAC_TypeDef *)DAC_BASE) 703 #define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ 704 #define CEC ((CEC_TypeDef *)CEC_BASE) 705 #define AFIO ((AFIO_TypeDef *)AFIO_BASE) 706 #define EXTI ((EXTI_TypeDef *)EXTI_BASE) 707 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) 708 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) 709 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) 710 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) 711 #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) 712 #define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) 713 #define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) 714 #define ADC1 ((ADC_TypeDef *)ADC1_BASE) 715 #define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) 716 #define TIM1 ((TIM_TypeDef *)TIM1_BASE) 717 #define SPI1 ((SPI_TypeDef *)SPI1_BASE) 718 #define USART1 ((USART_TypeDef *)USART1_BASE) 719 #define TIM15 ((TIM_TypeDef *)TIM15_BASE) 720 #define TIM16 ((TIM_TypeDef *)TIM16_BASE) 721 #define TIM17 ((TIM_TypeDef *)TIM17_BASE) 722 #define DMA1 ((DMA_TypeDef *)DMA1_BASE) 723 #define DMA2 ((DMA_TypeDef *)DMA2_BASE) 724 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) 725 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) 726 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) 727 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) 728 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) 729 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) 730 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) 731 #define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) 732 #define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) 733 #define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) 734 #define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) 735 #define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) 736 #define RCC ((RCC_TypeDef *)RCC_BASE) 737 #define CRC ((CRC_TypeDef *)CRC_BASE) 738 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) 739 #define OB ((OB_TypeDef *)OB_BASE) 740 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE) 741 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE) 742 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) 743 744 745 /** 746 * @} 747 */ 748 749 /** @addtogroup Exported_constants 750 * @{ 751 */ 752 753 /** @addtogroup Hardware_Constant_Definition 754 * @{ 755 */ 756 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 757 /** 758 * @} 759 */ 760 761 /** @addtogroup Peripheral_Registers_Bits_Definition 762 * @{ 763 */ 764 765 /******************************************************************************/ 766 /* Peripheral Registers_Bits_Definition */ 767 /******************************************************************************/ 768 769 /******************************************************************************/ 770 /* */ 771 /* CRC calculation unit (CRC) */ 772 /* */ 773 /******************************************************************************/ 774 775 /******************* Bit definition for CRC_DR register *********************/ 776 #define CRC_DR_DR_Pos (0U) 777 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 778 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 779 780 /******************* Bit definition for CRC_IDR register ********************/ 781 #define CRC_IDR_IDR_Pos (0U) 782 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 783 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 784 785 /******************** Bit definition for CRC_CR register ********************/ 786 #define CRC_CR_RESET_Pos (0U) 787 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 788 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 789 790 /******************************************************************************/ 791 /* */ 792 /* Power Control */ 793 /* */ 794 /******************************************************************************/ 795 796 /******************** Bit definition for PWR_CR register ********************/ 797 #define PWR_CR_LPDS_Pos (0U) 798 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 799 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ 800 #define PWR_CR_PDDS_Pos (1U) 801 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 802 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 803 #define PWR_CR_CWUF_Pos (2U) 804 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 805 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 806 #define PWR_CR_CSBF_Pos (3U) 807 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 808 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 809 #define PWR_CR_PVDE_Pos (4U) 810 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 811 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 812 813 #define PWR_CR_PLS_Pos (5U) 814 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 815 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 816 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 817 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 818 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 819 820 /*!< PVD level configuration */ 821 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ 822 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ 823 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ 824 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ 825 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ 826 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ 827 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ 828 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ 829 830 /* Legacy defines */ 831 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 832 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 833 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 834 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 835 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 836 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 837 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 838 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 839 840 #define PWR_CR_DBP_Pos (8U) 841 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 842 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 843 844 845 /******************* Bit definition for PWR_CSR register ********************/ 846 #define PWR_CSR_WUF_Pos (0U) 847 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 848 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 849 #define PWR_CSR_SBF_Pos (1U) 850 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 851 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 852 #define PWR_CSR_PVDO_Pos (2U) 853 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 854 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 855 #define PWR_CSR_EWUP_Pos (8U) 856 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ 857 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ 858 859 /******************************************************************************/ 860 /* */ 861 /* Backup registers */ 862 /* */ 863 /******************************************************************************/ 864 865 /******************* Bit definition for BKP_DR1 register ********************/ 866 #define BKP_DR1_D_Pos (0U) 867 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ 868 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ 869 870 /******************* Bit definition for BKP_DR2 register ********************/ 871 #define BKP_DR2_D_Pos (0U) 872 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ 873 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ 874 875 /******************* Bit definition for BKP_DR3 register ********************/ 876 #define BKP_DR3_D_Pos (0U) 877 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ 878 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ 879 880 /******************* Bit definition for BKP_DR4 register ********************/ 881 #define BKP_DR4_D_Pos (0U) 882 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ 883 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ 884 885 /******************* Bit definition for BKP_DR5 register ********************/ 886 #define BKP_DR5_D_Pos (0U) 887 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ 888 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ 889 890 /******************* Bit definition for BKP_DR6 register ********************/ 891 #define BKP_DR6_D_Pos (0U) 892 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ 893 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ 894 895 /******************* Bit definition for BKP_DR7 register ********************/ 896 #define BKP_DR7_D_Pos (0U) 897 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ 898 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ 899 900 /******************* Bit definition for BKP_DR8 register ********************/ 901 #define BKP_DR8_D_Pos (0U) 902 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ 903 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ 904 905 /******************* Bit definition for BKP_DR9 register ********************/ 906 #define BKP_DR9_D_Pos (0U) 907 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ 908 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ 909 910 /******************* Bit definition for BKP_DR10 register *******************/ 911 #define BKP_DR10_D_Pos (0U) 912 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ 913 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ 914 915 /******************* Bit definition for BKP_DR11 register *******************/ 916 #define BKP_DR11_D_Pos (0U) 917 #define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ 918 #define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ 919 920 /******************* Bit definition for BKP_DR12 register *******************/ 921 #define BKP_DR12_D_Pos (0U) 922 #define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ 923 #define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ 924 925 /******************* Bit definition for BKP_DR13 register *******************/ 926 #define BKP_DR13_D_Pos (0U) 927 #define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ 928 #define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ 929 930 /******************* Bit definition for BKP_DR14 register *******************/ 931 #define BKP_DR14_D_Pos (0U) 932 #define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ 933 #define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ 934 935 /******************* Bit definition for BKP_DR15 register *******************/ 936 #define BKP_DR15_D_Pos (0U) 937 #define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ 938 #define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ 939 940 /******************* Bit definition for BKP_DR16 register *******************/ 941 #define BKP_DR16_D_Pos (0U) 942 #define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ 943 #define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ 944 945 /******************* Bit definition for BKP_DR17 register *******************/ 946 #define BKP_DR17_D_Pos (0U) 947 #define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ 948 #define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ 949 950 /****************** Bit definition for BKP_DR18 register ********************/ 951 #define BKP_DR18_D_Pos (0U) 952 #define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ 953 #define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ 954 955 /******************* Bit definition for BKP_DR19 register *******************/ 956 #define BKP_DR19_D_Pos (0U) 957 #define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ 958 #define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ 959 960 /******************* Bit definition for BKP_DR20 register *******************/ 961 #define BKP_DR20_D_Pos (0U) 962 #define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ 963 #define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ 964 965 /******************* Bit definition for BKP_DR21 register *******************/ 966 #define BKP_DR21_D_Pos (0U) 967 #define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ 968 #define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ 969 970 /******************* Bit definition for BKP_DR22 register *******************/ 971 #define BKP_DR22_D_Pos (0U) 972 #define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ 973 #define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ 974 975 /******************* Bit definition for BKP_DR23 register *******************/ 976 #define BKP_DR23_D_Pos (0U) 977 #define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ 978 #define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ 979 980 /******************* Bit definition for BKP_DR24 register *******************/ 981 #define BKP_DR24_D_Pos (0U) 982 #define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ 983 #define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ 984 985 /******************* Bit definition for BKP_DR25 register *******************/ 986 #define BKP_DR25_D_Pos (0U) 987 #define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ 988 #define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ 989 990 /******************* Bit definition for BKP_DR26 register *******************/ 991 #define BKP_DR26_D_Pos (0U) 992 #define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ 993 #define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ 994 995 /******************* Bit definition for BKP_DR27 register *******************/ 996 #define BKP_DR27_D_Pos (0U) 997 #define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ 998 #define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ 999 1000 /******************* Bit definition for BKP_DR28 register *******************/ 1001 #define BKP_DR28_D_Pos (0U) 1002 #define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ 1003 #define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ 1004 1005 /******************* Bit definition for BKP_DR29 register *******************/ 1006 #define BKP_DR29_D_Pos (0U) 1007 #define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ 1008 #define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ 1009 1010 /******************* Bit definition for BKP_DR30 register *******************/ 1011 #define BKP_DR30_D_Pos (0U) 1012 #define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ 1013 #define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ 1014 1015 /******************* Bit definition for BKP_DR31 register *******************/ 1016 #define BKP_DR31_D_Pos (0U) 1017 #define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ 1018 #define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ 1019 1020 /******************* Bit definition for BKP_DR32 register *******************/ 1021 #define BKP_DR32_D_Pos (0U) 1022 #define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ 1023 #define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ 1024 1025 /******************* Bit definition for BKP_DR33 register *******************/ 1026 #define BKP_DR33_D_Pos (0U) 1027 #define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ 1028 #define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ 1029 1030 /******************* Bit definition for BKP_DR34 register *******************/ 1031 #define BKP_DR34_D_Pos (0U) 1032 #define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ 1033 #define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ 1034 1035 /******************* Bit definition for BKP_DR35 register *******************/ 1036 #define BKP_DR35_D_Pos (0U) 1037 #define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ 1038 #define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ 1039 1040 /******************* Bit definition for BKP_DR36 register *******************/ 1041 #define BKP_DR36_D_Pos (0U) 1042 #define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ 1043 #define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ 1044 1045 /******************* Bit definition for BKP_DR37 register *******************/ 1046 #define BKP_DR37_D_Pos (0U) 1047 #define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ 1048 #define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ 1049 1050 /******************* Bit definition for BKP_DR38 register *******************/ 1051 #define BKP_DR38_D_Pos (0U) 1052 #define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ 1053 #define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ 1054 1055 /******************* Bit definition for BKP_DR39 register *******************/ 1056 #define BKP_DR39_D_Pos (0U) 1057 #define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ 1058 #define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ 1059 1060 /******************* Bit definition for BKP_DR40 register *******************/ 1061 #define BKP_DR40_D_Pos (0U) 1062 #define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ 1063 #define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ 1064 1065 /******************* Bit definition for BKP_DR41 register *******************/ 1066 #define BKP_DR41_D_Pos (0U) 1067 #define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ 1068 #define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ 1069 1070 /******************* Bit definition for BKP_DR42 register *******************/ 1071 #define BKP_DR42_D_Pos (0U) 1072 #define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ 1073 #define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ 1074 1075 #define RTC_BKP_NUMBER 42 1076 1077 /****************** Bit definition for BKP_RTCCR register *******************/ 1078 #define BKP_RTCCR_CAL_Pos (0U) 1079 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ 1080 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ 1081 #define BKP_RTCCR_CCO_Pos (7U) 1082 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ 1083 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ 1084 #define BKP_RTCCR_ASOE_Pos (8U) 1085 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ 1086 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ 1087 #define BKP_RTCCR_ASOS_Pos (9U) 1088 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ 1089 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ 1090 1091 /******************** Bit definition for BKP_CR register ********************/ 1092 #define BKP_CR_TPE_Pos (0U) 1093 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ 1094 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ 1095 #define BKP_CR_TPAL_Pos (1U) 1096 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ 1097 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ 1098 1099 /******************* Bit definition for BKP_CSR register ********************/ 1100 #define BKP_CSR_CTE_Pos (0U) 1101 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ 1102 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ 1103 #define BKP_CSR_CTI_Pos (1U) 1104 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ 1105 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ 1106 #define BKP_CSR_TPIE_Pos (2U) 1107 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ 1108 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ 1109 #define BKP_CSR_TEF_Pos (8U) 1110 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ 1111 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ 1112 #define BKP_CSR_TIF_Pos (9U) 1113 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ 1114 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ 1115 1116 /******************************************************************************/ 1117 /* */ 1118 /* Reset and Clock Control */ 1119 /* */ 1120 /******************************************************************************/ 1121 1122 /******************** Bit definition for RCC_CR register ********************/ 1123 #define RCC_CR_HSION_Pos (0U) 1124 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 1125 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 1126 #define RCC_CR_HSIRDY_Pos (1U) 1127 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 1128 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 1129 #define RCC_CR_HSITRIM_Pos (3U) 1130 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 1131 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 1132 #define RCC_CR_HSICAL_Pos (8U) 1133 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 1134 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 1135 #define RCC_CR_HSEON_Pos (16U) 1136 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 1137 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 1138 #define RCC_CR_HSERDY_Pos (17U) 1139 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 1140 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 1141 #define RCC_CR_HSEBYP_Pos (18U) 1142 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 1143 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 1144 #define RCC_CR_CSSON_Pos (19U) 1145 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 1146 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 1147 #define RCC_CR_PLLON_Pos (24U) 1148 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 1149 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 1150 #define RCC_CR_PLLRDY_Pos (25U) 1151 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 1152 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 1153 1154 1155 /******************* Bit definition for RCC_CFGR register *******************/ 1156 /*!< SW configuration */ 1157 #define RCC_CFGR_SW_Pos (0U) 1158 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 1159 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 1160 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 1161 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 1162 1163 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ 1164 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ 1165 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ 1166 1167 /*!< SWS configuration */ 1168 #define RCC_CFGR_SWS_Pos (2U) 1169 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 1170 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 1171 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 1172 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 1173 1174 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ 1175 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ 1176 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ 1177 1178 /*!< HPRE configuration */ 1179 #define RCC_CFGR_HPRE_Pos (4U) 1180 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 1181 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 1182 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 1183 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 1184 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 1185 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 1186 1187 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ 1188 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ 1189 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ 1190 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ 1191 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ 1192 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ 1193 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ 1194 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ 1195 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ 1196 1197 /*!< PPRE1 configuration */ 1198 #define RCC_CFGR_PPRE1_Pos (8U) 1199 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 1200 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 1201 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 1202 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 1203 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 1204 1205 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ 1206 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ 1207 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ 1208 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ 1209 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ 1210 1211 /*!< PPRE2 configuration */ 1212 #define RCC_CFGR_PPRE2_Pos (11U) 1213 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 1214 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 1215 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 1216 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 1217 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 1218 1219 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ 1220 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ 1221 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ 1222 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ 1223 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ 1224 1225 /*!< ADCPPRE configuration */ 1226 #define RCC_CFGR_ADCPRE_Pos (14U) 1227 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ 1228 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ 1229 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 1230 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ 1231 1232 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ 1233 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ 1234 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ 1235 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ 1236 1237 #define RCC_CFGR_PLLSRC_Pos (16U) 1238 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 1239 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 1240 1241 #define RCC_CFGR_PLLXTPRE_Pos (17U) 1242 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 1243 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 1244 1245 /*!< PLLMUL configuration */ 1246 #define RCC_CFGR_PLLMULL_Pos (18U) 1247 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ 1248 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 1249 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ 1250 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ 1251 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ 1252 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ 1253 1254 #define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ 1255 #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ 1256 1257 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ 1258 #define RCC_CFGR_PLLMULL3_Pos (18U) 1259 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ 1260 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ 1261 #define RCC_CFGR_PLLMULL4_Pos (19U) 1262 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ 1263 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ 1264 #define RCC_CFGR_PLLMULL5_Pos (18U) 1265 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ 1266 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ 1267 #define RCC_CFGR_PLLMULL6_Pos (20U) 1268 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ 1269 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ 1270 #define RCC_CFGR_PLLMULL7_Pos (18U) 1271 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ 1272 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ 1273 #define RCC_CFGR_PLLMULL8_Pos (19U) 1274 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ 1275 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ 1276 #define RCC_CFGR_PLLMULL9_Pos (18U) 1277 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ 1278 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ 1279 #define RCC_CFGR_PLLMULL10_Pos (21U) 1280 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ 1281 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ 1282 #define RCC_CFGR_PLLMULL11_Pos (18U) 1283 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ 1284 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ 1285 #define RCC_CFGR_PLLMULL12_Pos (19U) 1286 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ 1287 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ 1288 #define RCC_CFGR_PLLMULL13_Pos (18U) 1289 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ 1290 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ 1291 #define RCC_CFGR_PLLMULL14_Pos (20U) 1292 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ 1293 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ 1294 #define RCC_CFGR_PLLMULL15_Pos (18U) 1295 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ 1296 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ 1297 #define RCC_CFGR_PLLMULL16_Pos (19U) 1298 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ 1299 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ 1300 1301 /*!< MCO configuration */ 1302 #define RCC_CFGR_MCO_Pos (24U) 1303 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 1304 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 1305 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 1306 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 1307 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 1308 1309 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ 1310 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ 1311 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ 1312 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ 1313 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ 1314 1315 /* Reference defines */ 1316 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 1317 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 1318 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 1319 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 1320 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 1321 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 1322 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 1323 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 1324 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 1325 1326 /*!<****************** Bit definition for RCC_CIR register ********************/ 1327 #define RCC_CIR_LSIRDYF_Pos (0U) 1328 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 1329 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 1330 #define RCC_CIR_LSERDYF_Pos (1U) 1331 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 1332 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 1333 #define RCC_CIR_HSIRDYF_Pos (2U) 1334 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 1335 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 1336 #define RCC_CIR_HSERDYF_Pos (3U) 1337 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 1338 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 1339 #define RCC_CIR_PLLRDYF_Pos (4U) 1340 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 1341 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 1342 #define RCC_CIR_CSSF_Pos (7U) 1343 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 1344 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 1345 #define RCC_CIR_LSIRDYIE_Pos (8U) 1346 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 1347 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 1348 #define RCC_CIR_LSERDYIE_Pos (9U) 1349 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 1350 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 1351 #define RCC_CIR_HSIRDYIE_Pos (10U) 1352 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 1353 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 1354 #define RCC_CIR_HSERDYIE_Pos (11U) 1355 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 1356 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 1357 #define RCC_CIR_PLLRDYIE_Pos (12U) 1358 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 1359 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 1360 #define RCC_CIR_LSIRDYC_Pos (16U) 1361 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 1362 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 1363 #define RCC_CIR_LSERDYC_Pos (17U) 1364 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 1365 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 1366 #define RCC_CIR_HSIRDYC_Pos (18U) 1367 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 1368 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 1369 #define RCC_CIR_HSERDYC_Pos (19U) 1370 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 1371 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 1372 #define RCC_CIR_PLLRDYC_Pos (20U) 1373 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 1374 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 1375 #define RCC_CIR_CSSC_Pos (23U) 1376 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 1377 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 1378 1379 1380 /***************** Bit definition for RCC_APB2RSTR register *****************/ 1381 #define RCC_APB2RSTR_AFIORST_Pos (0U) 1382 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ 1383 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ 1384 #define RCC_APB2RSTR_IOPARST_Pos (2U) 1385 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ 1386 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ 1387 #define RCC_APB2RSTR_IOPBRST_Pos (3U) 1388 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ 1389 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ 1390 #define RCC_APB2RSTR_IOPCRST_Pos (4U) 1391 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ 1392 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ 1393 #define RCC_APB2RSTR_IOPDRST_Pos (5U) 1394 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ 1395 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ 1396 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 1397 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 1398 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ 1399 1400 1401 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 1402 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 1403 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ 1404 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 1405 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 1406 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ 1407 #define RCC_APB2RSTR_USART1RST_Pos (14U) 1408 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 1409 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 1410 1411 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 1412 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 1413 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 Timer reset */ 1414 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 1415 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 1416 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 Timer reset */ 1417 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 1418 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 1419 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 Timer reset */ 1420 1421 #define RCC_APB2RSTR_IOPERST_Pos (6U) 1422 #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ 1423 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ 1424 1425 1426 #define RCC_APB2RSTR_IOPFRST_Pos (7U) 1427 #define RCC_APB2RSTR_IOPFRST_Msk (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */ 1428 #define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */ 1429 #define RCC_APB2RSTR_IOPGRST_Pos (8U) 1430 #define RCC_APB2RSTR_IOPGRST_Msk (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */ 1431 #define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */ 1432 1433 1434 /***************** Bit definition for RCC_APB1RSTR register *****************/ 1435 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 1436 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 1437 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 1438 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 1439 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 1440 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 1441 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 1442 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 1443 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 1444 #define RCC_APB1RSTR_USART2RST_Pos (17U) 1445 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 1446 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 1447 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 1448 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 1449 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 1450 1451 1452 #define RCC_APB1RSTR_BKPRST_Pos (27U) 1453 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ 1454 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ 1455 #define RCC_APB1RSTR_PWRRST_Pos (28U) 1456 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 1457 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 1458 1459 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 1460 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 1461 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 1462 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 1463 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 1464 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 1465 #define RCC_APB1RSTR_USART3RST_Pos (18U) 1466 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 1467 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 1468 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 1469 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 1470 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 1471 1472 1473 1474 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 1475 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 1476 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 1477 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 1478 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 1479 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 1480 #define RCC_APB1RSTR_CECRST_Pos (30U) 1481 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ 1482 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC interface reset */ 1483 1484 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 1485 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ 1486 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ 1487 #define RCC_APB1RSTR_TIM12RST_Pos (6U) 1488 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */ 1489 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /*!< TIM12 Timer reset */ 1490 #define RCC_APB1RSTR_TIM13RST_Pos (7U) 1491 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */ 1492 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /*!< TIM13 Timer reset */ 1493 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 1494 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 1495 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< TIM14 Timer reset */ 1496 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 1497 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 1498 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ 1499 #define RCC_APB1RSTR_UART4RST_Pos (19U) 1500 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ 1501 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ 1502 #define RCC_APB1RSTR_UART5RST_Pos (20U) 1503 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ 1504 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ 1505 1506 1507 #define RCC_APB1RSTR_DACRST_Pos (29U) 1508 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 1509 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 1510 1511 /****************** Bit definition for RCC_AHBENR register ******************/ 1512 #define RCC_AHBENR_DMA1EN_Pos (0U) 1513 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 1514 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 1515 #define RCC_AHBENR_SRAMEN_Pos (2U) 1516 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 1517 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 1518 #define RCC_AHBENR_FLITFEN_Pos (4U) 1519 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 1520 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 1521 #define RCC_AHBENR_CRCEN_Pos (6U) 1522 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 1523 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 1524 1525 #define RCC_AHBENR_DMA2EN_Pos (1U) 1526 #define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ 1527 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ 1528 1529 #define RCC_AHBENR_FSMCEN_Pos (8U) 1530 #define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */ 1531 #define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */ 1532 1533 1534 /****************** Bit definition for RCC_APB2ENR register *****************/ 1535 #define RCC_APB2ENR_AFIOEN_Pos (0U) 1536 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ 1537 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ 1538 #define RCC_APB2ENR_IOPAEN_Pos (2U) 1539 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ 1540 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ 1541 #define RCC_APB2ENR_IOPBEN_Pos (3U) 1542 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ 1543 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ 1544 #define RCC_APB2ENR_IOPCEN_Pos (4U) 1545 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ 1546 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ 1547 #define RCC_APB2ENR_IOPDEN_Pos (5U) 1548 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ 1549 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ 1550 #define RCC_APB2ENR_ADC1EN_Pos (9U) 1551 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 1552 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ 1553 1554 1555 #define RCC_APB2ENR_TIM1EN_Pos (11U) 1556 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 1557 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ 1558 #define RCC_APB2ENR_SPI1EN_Pos (12U) 1559 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 1560 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ 1561 #define RCC_APB2ENR_USART1EN_Pos (14U) 1562 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 1563 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 1564 1565 #define RCC_APB2ENR_TIM15EN_Pos (16U) 1566 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 1567 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 Timer clock enable */ 1568 #define RCC_APB2ENR_TIM16EN_Pos (17U) 1569 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 1570 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 Timer clock enable */ 1571 #define RCC_APB2ENR_TIM17EN_Pos (18U) 1572 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 1573 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 Timer clock enable */ 1574 1575 #define RCC_APB2ENR_IOPEEN_Pos (6U) 1576 #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ 1577 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ 1578 1579 1580 #define RCC_APB2ENR_IOPFEN_Pos (7U) 1581 #define RCC_APB2ENR_IOPFEN_Msk (0x1UL << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */ 1582 #define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */ 1583 #define RCC_APB2ENR_IOPGEN_Pos (8U) 1584 #define RCC_APB2ENR_IOPGEN_Msk (0x1UL << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */ 1585 #define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */ 1586 1587 1588 /***************** Bit definition for RCC_APB1ENR register ******************/ 1589 #define RCC_APB1ENR_TIM2EN_Pos (0U) 1590 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 1591 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 1592 #define RCC_APB1ENR_TIM3EN_Pos (1U) 1593 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 1594 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 1595 #define RCC_APB1ENR_WWDGEN_Pos (11U) 1596 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 1597 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 1598 #define RCC_APB1ENR_USART2EN_Pos (17U) 1599 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 1600 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 1601 #define RCC_APB1ENR_I2C1EN_Pos (21U) 1602 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 1603 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 1604 1605 1606 #define RCC_APB1ENR_BKPEN_Pos (27U) 1607 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ 1608 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ 1609 #define RCC_APB1ENR_PWREN_Pos (28U) 1610 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 1611 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 1612 1613 #define RCC_APB1ENR_TIM4EN_Pos (2U) 1614 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 1615 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 1616 #define RCC_APB1ENR_SPI2EN_Pos (14U) 1617 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 1618 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 1619 #define RCC_APB1ENR_USART3EN_Pos (18U) 1620 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 1621 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 1622 #define RCC_APB1ENR_I2C2EN_Pos (22U) 1623 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 1624 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 1625 1626 1627 1628 #define RCC_APB1ENR_TIM6EN_Pos (4U) 1629 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 1630 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 1631 #define RCC_APB1ENR_TIM7EN_Pos (5U) 1632 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 1633 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 1634 #define RCC_APB1ENR_CECEN_Pos (30U) 1635 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */ 1636 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface clock enable */ 1637 1638 #define RCC_APB1ENR_TIM5EN_Pos (3U) 1639 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ 1640 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ 1641 #define RCC_APB1ENR_TIM12EN_Pos (6U) 1642 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */ 1643 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /*!< TIM12 Timer clock enable */ 1644 #define RCC_APB1ENR_TIM13EN_Pos (7U) 1645 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */ 1646 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /*!< TIM13 Timer clock enable */ 1647 #define RCC_APB1ENR_TIM14EN_Pos (8U) 1648 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 1649 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< TIM14 Timer clock enable */ 1650 #define RCC_APB1ENR_SPI3EN_Pos (15U) 1651 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 1652 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ 1653 #define RCC_APB1ENR_UART4EN_Pos (19U) 1654 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ 1655 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ 1656 #define RCC_APB1ENR_UART5EN_Pos (20U) 1657 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ 1658 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ 1659 1660 1661 #define RCC_APB1ENR_DACEN_Pos (29U) 1662 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 1663 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 1664 1665 /******************* Bit definition for RCC_BDCR register *******************/ 1666 #define RCC_BDCR_LSEON_Pos (0U) 1667 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 1668 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 1669 #define RCC_BDCR_LSERDY_Pos (1U) 1670 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 1671 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 1672 #define RCC_BDCR_LSEBYP_Pos (2U) 1673 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 1674 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 1675 1676 #define RCC_BDCR_RTCSEL_Pos (8U) 1677 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 1678 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 1679 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 1680 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 1681 1682 /*!< RTC congiguration */ 1683 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ 1684 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ 1685 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ 1686 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ 1687 1688 #define RCC_BDCR_RTCEN_Pos (15U) 1689 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 1690 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 1691 #define RCC_BDCR_BDRST_Pos (16U) 1692 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 1693 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 1694 1695 /******************* Bit definition for RCC_CSR register ********************/ 1696 #define RCC_CSR_LSION_Pos (0U) 1697 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 1698 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 1699 #define RCC_CSR_LSIRDY_Pos (1U) 1700 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 1701 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 1702 #define RCC_CSR_RMVF_Pos (24U) 1703 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 1704 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 1705 #define RCC_CSR_PINRSTF_Pos (26U) 1706 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 1707 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 1708 #define RCC_CSR_PORRSTF_Pos (27U) 1709 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 1710 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 1711 #define RCC_CSR_SFTRSTF_Pos (28U) 1712 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 1713 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 1714 #define RCC_CSR_IWDGRSTF_Pos (29U) 1715 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 1716 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 1717 #define RCC_CSR_WWDGRSTF_Pos (30U) 1718 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 1719 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 1720 #define RCC_CSR_LPWRRSTF_Pos (31U) 1721 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 1722 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 1723 1724 1725 /******************* Bit definition for RCC_CFGR2 register ******************/ 1726 /*!< PREDIV1 configuration */ 1727 #define RCC_CFGR2_PREDIV1_Pos (0U) 1728 #define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ 1729 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ 1730 #define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ 1731 #define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ 1732 #define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ 1733 #define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ 1734 1735 #define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ 1736 #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) 1737 #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ 1738 #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ 1739 #define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) 1740 #define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ 1741 #define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ 1742 #define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) 1743 #define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ 1744 #define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ 1745 #define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) 1746 #define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ 1747 #define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ 1748 #define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) 1749 #define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ 1750 #define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ 1751 #define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) 1752 #define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ 1753 #define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ 1754 #define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) 1755 #define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ 1756 #define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ 1757 #define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) 1758 #define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ 1759 #define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ 1760 #define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) 1761 #define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ 1762 #define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ 1763 #define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) 1764 #define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ 1765 #define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ 1766 #define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) 1767 #define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ 1768 #define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ 1769 #define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) 1770 #define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ 1771 #define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ 1772 #define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) 1773 #define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ 1774 #define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ 1775 #define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) 1776 #define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ 1777 #define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ 1778 #define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) 1779 #define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ 1780 #define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ 1781 1782 /******************************************************************************/ 1783 /* */ 1784 /* General Purpose and Alternate Function I/O */ 1785 /* */ 1786 /******************************************************************************/ 1787 1788 /******************* Bit definition for GPIO_CRL register *******************/ 1789 #define GPIO_CRL_MODE_Pos (0U) 1790 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ 1791 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ 1792 1793 #define GPIO_CRL_MODE0_Pos (0U) 1794 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ 1795 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ 1796 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ 1797 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ 1798 1799 #define GPIO_CRL_MODE1_Pos (4U) 1800 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ 1801 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ 1802 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ 1803 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ 1804 1805 #define GPIO_CRL_MODE2_Pos (8U) 1806 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ 1807 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ 1808 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ 1809 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ 1810 1811 #define GPIO_CRL_MODE3_Pos (12U) 1812 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ 1813 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ 1814 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ 1815 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ 1816 1817 #define GPIO_CRL_MODE4_Pos (16U) 1818 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ 1819 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ 1820 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ 1821 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ 1822 1823 #define GPIO_CRL_MODE5_Pos (20U) 1824 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ 1825 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ 1826 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ 1827 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ 1828 1829 #define GPIO_CRL_MODE6_Pos (24U) 1830 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ 1831 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ 1832 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ 1833 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ 1834 1835 #define GPIO_CRL_MODE7_Pos (28U) 1836 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ 1837 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ 1838 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ 1839 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ 1840 1841 #define GPIO_CRL_CNF_Pos (2U) 1842 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ 1843 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ 1844 1845 #define GPIO_CRL_CNF0_Pos (2U) 1846 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ 1847 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ 1848 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ 1849 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ 1850 1851 #define GPIO_CRL_CNF1_Pos (6U) 1852 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ 1853 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ 1854 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ 1855 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ 1856 1857 #define GPIO_CRL_CNF2_Pos (10U) 1858 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ 1859 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ 1860 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ 1861 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ 1862 1863 #define GPIO_CRL_CNF3_Pos (14U) 1864 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ 1865 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ 1866 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ 1867 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ 1868 1869 #define GPIO_CRL_CNF4_Pos (18U) 1870 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ 1871 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ 1872 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ 1873 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ 1874 1875 #define GPIO_CRL_CNF5_Pos (22U) 1876 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ 1877 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ 1878 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ 1879 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ 1880 1881 #define GPIO_CRL_CNF6_Pos (26U) 1882 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ 1883 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ 1884 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ 1885 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ 1886 1887 #define GPIO_CRL_CNF7_Pos (30U) 1888 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ 1889 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ 1890 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ 1891 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ 1892 1893 /******************* Bit definition for GPIO_CRH register *******************/ 1894 #define GPIO_CRH_MODE_Pos (0U) 1895 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ 1896 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ 1897 1898 #define GPIO_CRH_MODE8_Pos (0U) 1899 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ 1900 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ 1901 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ 1902 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ 1903 1904 #define GPIO_CRH_MODE9_Pos (4U) 1905 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ 1906 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ 1907 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ 1908 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ 1909 1910 #define GPIO_CRH_MODE10_Pos (8U) 1911 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ 1912 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ 1913 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ 1914 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ 1915 1916 #define GPIO_CRH_MODE11_Pos (12U) 1917 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ 1918 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ 1919 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ 1920 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ 1921 1922 #define GPIO_CRH_MODE12_Pos (16U) 1923 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ 1924 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ 1925 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ 1926 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ 1927 1928 #define GPIO_CRH_MODE13_Pos (20U) 1929 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ 1930 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ 1931 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ 1932 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ 1933 1934 #define GPIO_CRH_MODE14_Pos (24U) 1935 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ 1936 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ 1937 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ 1938 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ 1939 1940 #define GPIO_CRH_MODE15_Pos (28U) 1941 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ 1942 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ 1943 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ 1944 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ 1945 1946 #define GPIO_CRH_CNF_Pos (2U) 1947 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ 1948 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ 1949 1950 #define GPIO_CRH_CNF8_Pos (2U) 1951 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ 1952 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ 1953 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ 1954 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ 1955 1956 #define GPIO_CRH_CNF9_Pos (6U) 1957 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ 1958 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ 1959 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ 1960 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ 1961 1962 #define GPIO_CRH_CNF10_Pos (10U) 1963 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ 1964 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ 1965 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ 1966 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ 1967 1968 #define GPIO_CRH_CNF11_Pos (14U) 1969 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ 1970 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ 1971 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ 1972 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ 1973 1974 #define GPIO_CRH_CNF12_Pos (18U) 1975 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ 1976 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ 1977 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ 1978 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ 1979 1980 #define GPIO_CRH_CNF13_Pos (22U) 1981 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ 1982 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ 1983 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ 1984 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ 1985 1986 #define GPIO_CRH_CNF14_Pos (26U) 1987 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ 1988 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ 1989 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ 1990 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ 1991 1992 #define GPIO_CRH_CNF15_Pos (30U) 1993 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ 1994 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ 1995 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ 1996 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ 1997 1998 /*!<****************** Bit definition for GPIO_IDR register *******************/ 1999 #define GPIO_IDR_IDR0_Pos (0U) 2000 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ 2001 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ 2002 #define GPIO_IDR_IDR1_Pos (1U) 2003 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ 2004 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ 2005 #define GPIO_IDR_IDR2_Pos (2U) 2006 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ 2007 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ 2008 #define GPIO_IDR_IDR3_Pos (3U) 2009 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ 2010 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ 2011 #define GPIO_IDR_IDR4_Pos (4U) 2012 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ 2013 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ 2014 #define GPIO_IDR_IDR5_Pos (5U) 2015 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ 2016 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ 2017 #define GPIO_IDR_IDR6_Pos (6U) 2018 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ 2019 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ 2020 #define GPIO_IDR_IDR7_Pos (7U) 2021 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ 2022 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ 2023 #define GPIO_IDR_IDR8_Pos (8U) 2024 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ 2025 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ 2026 #define GPIO_IDR_IDR9_Pos (9U) 2027 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ 2028 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ 2029 #define GPIO_IDR_IDR10_Pos (10U) 2030 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ 2031 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ 2032 #define GPIO_IDR_IDR11_Pos (11U) 2033 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ 2034 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ 2035 #define GPIO_IDR_IDR12_Pos (12U) 2036 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ 2037 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ 2038 #define GPIO_IDR_IDR13_Pos (13U) 2039 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ 2040 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ 2041 #define GPIO_IDR_IDR14_Pos (14U) 2042 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ 2043 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ 2044 #define GPIO_IDR_IDR15_Pos (15U) 2045 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ 2046 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ 2047 2048 /******************* Bit definition for GPIO_ODR register *******************/ 2049 #define GPIO_ODR_ODR0_Pos (0U) 2050 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ 2051 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ 2052 #define GPIO_ODR_ODR1_Pos (1U) 2053 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ 2054 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ 2055 #define GPIO_ODR_ODR2_Pos (2U) 2056 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ 2057 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ 2058 #define GPIO_ODR_ODR3_Pos (3U) 2059 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ 2060 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ 2061 #define GPIO_ODR_ODR4_Pos (4U) 2062 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ 2063 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ 2064 #define GPIO_ODR_ODR5_Pos (5U) 2065 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ 2066 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ 2067 #define GPIO_ODR_ODR6_Pos (6U) 2068 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ 2069 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ 2070 #define GPIO_ODR_ODR7_Pos (7U) 2071 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ 2072 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ 2073 #define GPIO_ODR_ODR8_Pos (8U) 2074 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ 2075 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ 2076 #define GPIO_ODR_ODR9_Pos (9U) 2077 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ 2078 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ 2079 #define GPIO_ODR_ODR10_Pos (10U) 2080 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ 2081 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ 2082 #define GPIO_ODR_ODR11_Pos (11U) 2083 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ 2084 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ 2085 #define GPIO_ODR_ODR12_Pos (12U) 2086 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ 2087 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ 2088 #define GPIO_ODR_ODR13_Pos (13U) 2089 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ 2090 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ 2091 #define GPIO_ODR_ODR14_Pos (14U) 2092 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ 2093 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ 2094 #define GPIO_ODR_ODR15_Pos (15U) 2095 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ 2096 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ 2097 2098 /****************** Bit definition for GPIO_BSRR register *******************/ 2099 #define GPIO_BSRR_BS0_Pos (0U) 2100 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 2101 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ 2102 #define GPIO_BSRR_BS1_Pos (1U) 2103 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 2104 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ 2105 #define GPIO_BSRR_BS2_Pos (2U) 2106 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 2107 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ 2108 #define GPIO_BSRR_BS3_Pos (3U) 2109 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 2110 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ 2111 #define GPIO_BSRR_BS4_Pos (4U) 2112 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 2113 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ 2114 #define GPIO_BSRR_BS5_Pos (5U) 2115 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 2116 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ 2117 #define GPIO_BSRR_BS6_Pos (6U) 2118 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 2119 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ 2120 #define GPIO_BSRR_BS7_Pos (7U) 2121 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 2122 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ 2123 #define GPIO_BSRR_BS8_Pos (8U) 2124 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 2125 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ 2126 #define GPIO_BSRR_BS9_Pos (9U) 2127 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 2128 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ 2129 #define GPIO_BSRR_BS10_Pos (10U) 2130 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 2131 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ 2132 #define GPIO_BSRR_BS11_Pos (11U) 2133 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 2134 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ 2135 #define GPIO_BSRR_BS12_Pos (12U) 2136 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 2137 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ 2138 #define GPIO_BSRR_BS13_Pos (13U) 2139 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 2140 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ 2141 #define GPIO_BSRR_BS14_Pos (14U) 2142 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 2143 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ 2144 #define GPIO_BSRR_BS15_Pos (15U) 2145 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 2146 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ 2147 2148 #define GPIO_BSRR_BR0_Pos (16U) 2149 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 2150 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ 2151 #define GPIO_BSRR_BR1_Pos (17U) 2152 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 2153 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ 2154 #define GPIO_BSRR_BR2_Pos (18U) 2155 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 2156 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ 2157 #define GPIO_BSRR_BR3_Pos (19U) 2158 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 2159 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ 2160 #define GPIO_BSRR_BR4_Pos (20U) 2161 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 2162 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ 2163 #define GPIO_BSRR_BR5_Pos (21U) 2164 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 2165 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ 2166 #define GPIO_BSRR_BR6_Pos (22U) 2167 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 2168 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ 2169 #define GPIO_BSRR_BR7_Pos (23U) 2170 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 2171 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ 2172 #define GPIO_BSRR_BR8_Pos (24U) 2173 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 2174 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ 2175 #define GPIO_BSRR_BR9_Pos (25U) 2176 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 2177 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ 2178 #define GPIO_BSRR_BR10_Pos (26U) 2179 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 2180 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ 2181 #define GPIO_BSRR_BR11_Pos (27U) 2182 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 2183 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ 2184 #define GPIO_BSRR_BR12_Pos (28U) 2185 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 2186 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ 2187 #define GPIO_BSRR_BR13_Pos (29U) 2188 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 2189 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ 2190 #define GPIO_BSRR_BR14_Pos (30U) 2191 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 2192 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ 2193 #define GPIO_BSRR_BR15_Pos (31U) 2194 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 2195 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ 2196 2197 /******************* Bit definition for GPIO_BRR register *******************/ 2198 #define GPIO_BRR_BR0_Pos (0U) 2199 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 2200 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ 2201 #define GPIO_BRR_BR1_Pos (1U) 2202 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 2203 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ 2204 #define GPIO_BRR_BR2_Pos (2U) 2205 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 2206 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ 2207 #define GPIO_BRR_BR3_Pos (3U) 2208 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 2209 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ 2210 #define GPIO_BRR_BR4_Pos (4U) 2211 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 2212 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ 2213 #define GPIO_BRR_BR5_Pos (5U) 2214 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 2215 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ 2216 #define GPIO_BRR_BR6_Pos (6U) 2217 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 2218 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ 2219 #define GPIO_BRR_BR7_Pos (7U) 2220 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 2221 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ 2222 #define GPIO_BRR_BR8_Pos (8U) 2223 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 2224 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ 2225 #define GPIO_BRR_BR9_Pos (9U) 2226 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 2227 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ 2228 #define GPIO_BRR_BR10_Pos (10U) 2229 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 2230 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ 2231 #define GPIO_BRR_BR11_Pos (11U) 2232 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 2233 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ 2234 #define GPIO_BRR_BR12_Pos (12U) 2235 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 2236 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ 2237 #define GPIO_BRR_BR13_Pos (13U) 2238 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 2239 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ 2240 #define GPIO_BRR_BR14_Pos (14U) 2241 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 2242 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ 2243 #define GPIO_BRR_BR15_Pos (15U) 2244 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 2245 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ 2246 2247 /****************** Bit definition for GPIO_LCKR register *******************/ 2248 #define GPIO_LCKR_LCK0_Pos (0U) 2249 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2250 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ 2251 #define GPIO_LCKR_LCK1_Pos (1U) 2252 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2253 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ 2254 #define GPIO_LCKR_LCK2_Pos (2U) 2255 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2256 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ 2257 #define GPIO_LCKR_LCK3_Pos (3U) 2258 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2259 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ 2260 #define GPIO_LCKR_LCK4_Pos (4U) 2261 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2262 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ 2263 #define GPIO_LCKR_LCK5_Pos (5U) 2264 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2265 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ 2266 #define GPIO_LCKR_LCK6_Pos (6U) 2267 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2268 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ 2269 #define GPIO_LCKR_LCK7_Pos (7U) 2270 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2271 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ 2272 #define GPIO_LCKR_LCK8_Pos (8U) 2273 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2274 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ 2275 #define GPIO_LCKR_LCK9_Pos (9U) 2276 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2277 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ 2278 #define GPIO_LCKR_LCK10_Pos (10U) 2279 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2280 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ 2281 #define GPIO_LCKR_LCK11_Pos (11U) 2282 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2283 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ 2284 #define GPIO_LCKR_LCK12_Pos (12U) 2285 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2286 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ 2287 #define GPIO_LCKR_LCK13_Pos (13U) 2288 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2289 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ 2290 #define GPIO_LCKR_LCK14_Pos (14U) 2291 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2292 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ 2293 #define GPIO_LCKR_LCK15_Pos (15U) 2294 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2295 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ 2296 #define GPIO_LCKR_LCKK_Pos (16U) 2297 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2298 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ 2299 2300 /*----------------------------------------------------------------------------*/ 2301 2302 /****************** Bit definition for AFIO_EVCR register *******************/ 2303 #define AFIO_EVCR_PIN_Pos (0U) 2304 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ 2305 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ 2306 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ 2307 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ 2308 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ 2309 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ 2310 2311 /*!< PIN configuration */ 2312 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ 2313 #define AFIO_EVCR_PIN_PX1_Pos (0U) 2314 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ 2315 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ 2316 #define AFIO_EVCR_PIN_PX2_Pos (1U) 2317 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ 2318 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ 2319 #define AFIO_EVCR_PIN_PX3_Pos (0U) 2320 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ 2321 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ 2322 #define AFIO_EVCR_PIN_PX4_Pos (2U) 2323 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ 2324 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ 2325 #define AFIO_EVCR_PIN_PX5_Pos (0U) 2326 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ 2327 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ 2328 #define AFIO_EVCR_PIN_PX6_Pos (1U) 2329 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ 2330 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ 2331 #define AFIO_EVCR_PIN_PX7_Pos (0U) 2332 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ 2333 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ 2334 #define AFIO_EVCR_PIN_PX8_Pos (3U) 2335 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ 2336 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ 2337 #define AFIO_EVCR_PIN_PX9_Pos (0U) 2338 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ 2339 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ 2340 #define AFIO_EVCR_PIN_PX10_Pos (1U) 2341 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ 2342 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ 2343 #define AFIO_EVCR_PIN_PX11_Pos (0U) 2344 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ 2345 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ 2346 #define AFIO_EVCR_PIN_PX12_Pos (2U) 2347 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ 2348 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ 2349 #define AFIO_EVCR_PIN_PX13_Pos (0U) 2350 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ 2351 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ 2352 #define AFIO_EVCR_PIN_PX14_Pos (1U) 2353 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ 2354 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ 2355 #define AFIO_EVCR_PIN_PX15_Pos (0U) 2356 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ 2357 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ 2358 2359 #define AFIO_EVCR_PORT_Pos (4U) 2360 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ 2361 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ 2362 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ 2363 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ 2364 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ 2365 2366 /*!< PORT configuration */ 2367 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ 2368 #define AFIO_EVCR_PORT_PB_Pos (4U) 2369 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ 2370 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ 2371 #define AFIO_EVCR_PORT_PC_Pos (5U) 2372 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ 2373 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ 2374 #define AFIO_EVCR_PORT_PD_Pos (4U) 2375 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ 2376 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ 2377 #define AFIO_EVCR_PORT_PE_Pos (6U) 2378 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ 2379 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ 2380 2381 #define AFIO_EVCR_EVOE_Pos (7U) 2382 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ 2383 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ 2384 2385 /****************** Bit definition for AFIO_MAPR register *******************/ 2386 #define AFIO_MAPR_SPI1_REMAP_Pos (0U) 2387 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ 2388 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ 2389 #define AFIO_MAPR_I2C1_REMAP_Pos (1U) 2390 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ 2391 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ 2392 #define AFIO_MAPR_USART1_REMAP_Pos (2U) 2393 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ 2394 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ 2395 #define AFIO_MAPR_USART2_REMAP_Pos (3U) 2396 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ 2397 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ 2398 2399 #define AFIO_MAPR_USART3_REMAP_Pos (4U) 2400 #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ 2401 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ 2402 #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ 2403 #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ 2404 2405 /* USART3_REMAP configuration */ 2406 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ 2407 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) 2408 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ 2409 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ 2410 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) 2411 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ 2412 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ 2413 2414 #define AFIO_MAPR_TIM1_REMAP_Pos (6U) 2415 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ 2416 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ 2417 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ 2418 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ 2419 2420 /*!< TIM1_REMAP configuration */ 2421 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ 2422 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) 2423 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ 2424 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ 2425 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) 2426 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ 2427 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ 2428 2429 #define AFIO_MAPR_TIM2_REMAP_Pos (8U) 2430 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ 2431 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ 2432 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ 2433 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ 2434 2435 /*!< TIM2_REMAP configuration */ 2436 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ 2437 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) 2438 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ 2439 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ 2440 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) 2441 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ 2442 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ 2443 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) 2444 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ 2445 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ 2446 2447 #define AFIO_MAPR_TIM3_REMAP_Pos (10U) 2448 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ 2449 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ 2450 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ 2451 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ 2452 2453 /*!< TIM3_REMAP configuration */ 2454 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ 2455 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) 2456 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ 2457 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ 2458 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) 2459 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ 2460 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ 2461 2462 #define AFIO_MAPR_TIM4_REMAP_Pos (12U) 2463 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ 2464 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ 2465 2466 2467 #define AFIO_MAPR_PD01_REMAP_Pos (15U) 2468 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ 2469 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ 2470 #define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) 2471 #define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ 2472 #define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ 2473 2474 /*!< SWJ_CFG configuration */ 2475 #define AFIO_MAPR_SWJ_CFG_Pos (24U) 2476 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ 2477 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ 2478 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ 2479 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ 2480 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ 2481 2482 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ 2483 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) 2484 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ 2485 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ 2486 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) 2487 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ 2488 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ 2489 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) 2490 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ 2491 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ 2492 2493 2494 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 2495 #define AFIO_EXTICR1_EXTI0_Pos (0U) 2496 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 2497 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 2498 #define AFIO_EXTICR1_EXTI1_Pos (4U) 2499 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 2500 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 2501 #define AFIO_EXTICR1_EXTI2_Pos (8U) 2502 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 2503 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 2504 #define AFIO_EXTICR1_EXTI3_Pos (12U) 2505 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 2506 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 2507 2508 /*!< EXTI0 configuration */ 2509 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ 2510 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) 2511 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ 2512 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ 2513 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) 2514 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ 2515 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ 2516 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) 2517 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ 2518 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ 2519 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) 2520 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ 2521 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ 2522 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) 2523 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ 2524 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ 2525 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) 2526 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ 2527 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ 2528 2529 /*!< EXTI1 configuration */ 2530 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ 2531 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) 2532 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ 2533 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ 2534 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) 2535 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ 2536 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ 2537 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) 2538 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ 2539 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ 2540 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) 2541 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ 2542 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ 2543 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) 2544 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ 2545 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ 2546 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) 2547 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ 2548 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ 2549 2550 /*!< EXTI2 configuration */ 2551 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ 2552 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) 2553 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ 2554 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ 2555 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) 2556 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ 2557 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ 2558 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) 2559 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ 2560 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ 2561 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) 2562 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ 2563 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ 2564 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) 2565 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ 2566 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ 2567 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) 2568 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ 2569 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ 2570 2571 /*!< EXTI3 configuration */ 2572 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ 2573 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) 2574 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ 2575 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ 2576 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) 2577 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ 2578 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ 2579 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) 2580 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ 2581 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ 2582 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) 2583 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ 2584 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ 2585 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) 2586 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ 2587 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ 2588 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) 2589 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ 2590 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ 2591 2592 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 2593 #define AFIO_EXTICR2_EXTI4_Pos (0U) 2594 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 2595 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 2596 #define AFIO_EXTICR2_EXTI5_Pos (4U) 2597 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 2598 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 2599 #define AFIO_EXTICR2_EXTI6_Pos (8U) 2600 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 2601 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 2602 #define AFIO_EXTICR2_EXTI7_Pos (12U) 2603 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 2604 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 2605 2606 /*!< EXTI4 configuration */ 2607 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ 2608 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) 2609 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ 2610 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ 2611 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) 2612 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ 2613 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ 2614 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) 2615 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ 2616 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ 2617 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) 2618 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ 2619 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ 2620 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) 2621 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ 2622 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ 2623 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) 2624 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ 2625 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ 2626 2627 /* EXTI5 configuration */ 2628 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ 2629 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) 2630 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ 2631 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ 2632 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) 2633 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ 2634 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ 2635 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) 2636 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ 2637 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ 2638 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) 2639 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ 2640 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ 2641 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) 2642 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ 2643 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ 2644 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) 2645 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ 2646 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ 2647 2648 /*!< EXTI6 configuration */ 2649 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ 2650 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) 2651 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ 2652 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ 2653 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) 2654 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ 2655 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ 2656 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) 2657 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ 2658 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ 2659 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) 2660 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ 2661 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ 2662 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) 2663 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ 2664 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ 2665 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) 2666 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ 2667 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ 2668 2669 /*!< EXTI7 configuration */ 2670 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ 2671 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) 2672 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ 2673 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ 2674 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) 2675 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ 2676 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ 2677 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) 2678 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ 2679 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ 2680 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) 2681 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ 2682 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ 2683 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) 2684 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ 2685 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ 2686 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) 2687 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ 2688 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ 2689 2690 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 2691 #define AFIO_EXTICR3_EXTI8_Pos (0U) 2692 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 2693 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 2694 #define AFIO_EXTICR3_EXTI9_Pos (4U) 2695 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 2696 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 2697 #define AFIO_EXTICR3_EXTI10_Pos (8U) 2698 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 2699 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 2700 #define AFIO_EXTICR3_EXTI11_Pos (12U) 2701 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 2702 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 2703 2704 /*!< EXTI8 configuration */ 2705 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ 2706 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) 2707 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ 2708 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ 2709 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) 2710 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ 2711 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ 2712 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) 2713 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ 2714 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ 2715 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) 2716 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ 2717 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ 2718 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) 2719 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ 2720 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ 2721 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) 2722 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ 2723 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ 2724 2725 /*!< EXTI9 configuration */ 2726 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ 2727 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) 2728 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ 2729 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ 2730 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) 2731 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ 2732 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ 2733 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) 2734 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ 2735 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ 2736 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) 2737 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ 2738 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ 2739 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) 2740 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ 2741 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ 2742 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) 2743 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ 2744 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ 2745 2746 /*!< EXTI10 configuration */ 2747 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ 2748 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) 2749 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ 2750 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ 2751 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) 2752 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ 2753 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ 2754 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) 2755 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ 2756 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ 2757 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) 2758 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ 2759 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ 2760 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) 2761 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ 2762 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ 2763 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) 2764 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ 2765 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ 2766 2767 /*!< EXTI11 configuration */ 2768 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ 2769 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) 2770 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ 2771 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ 2772 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) 2773 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ 2774 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ 2775 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) 2776 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ 2777 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ 2778 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) 2779 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ 2780 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ 2781 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) 2782 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ 2783 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ 2784 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) 2785 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ 2786 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ 2787 2788 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 2789 #define AFIO_EXTICR4_EXTI12_Pos (0U) 2790 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 2791 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 2792 #define AFIO_EXTICR4_EXTI13_Pos (4U) 2793 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 2794 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 2795 #define AFIO_EXTICR4_EXTI14_Pos (8U) 2796 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 2797 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 2798 #define AFIO_EXTICR4_EXTI15_Pos (12U) 2799 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 2800 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 2801 2802 /* EXTI12 configuration */ 2803 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ 2804 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) 2805 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ 2806 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ 2807 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) 2808 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ 2809 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ 2810 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) 2811 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ 2812 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ 2813 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) 2814 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ 2815 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ 2816 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) 2817 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ 2818 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ 2819 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) 2820 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ 2821 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ 2822 2823 /* EXTI13 configuration */ 2824 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ 2825 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) 2826 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ 2827 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ 2828 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) 2829 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ 2830 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ 2831 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) 2832 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ 2833 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ 2834 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) 2835 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ 2836 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ 2837 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) 2838 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ 2839 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ 2840 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) 2841 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ 2842 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ 2843 2844 /*!< EXTI14 configuration */ 2845 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ 2846 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) 2847 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ 2848 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ 2849 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) 2850 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ 2851 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ 2852 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) 2853 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ 2854 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ 2855 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) 2856 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ 2857 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ 2858 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) 2859 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ 2860 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ 2861 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) 2862 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ 2863 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ 2864 2865 /*!< EXTI15 configuration */ 2866 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ 2867 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) 2868 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ 2869 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ 2870 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) 2871 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ 2872 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ 2873 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) 2874 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ 2875 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ 2876 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) 2877 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ 2878 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ 2879 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) 2880 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ 2881 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ 2882 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) 2883 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ 2884 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ 2885 2886 /****************** Bit definition for AFIO_MAPR2 register ******************/ 2887 #define AFIO_MAPR2_TIM15_REMAP_Pos (0U) 2888 #define AFIO_MAPR2_TIM15_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM15_REMAP_Pos) /*!< 0x00000001 */ 2889 #define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /*!< TIM15 remapping */ 2890 #define AFIO_MAPR2_TIM16_REMAP_Pos (1U) 2891 #define AFIO_MAPR2_TIM16_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM16_REMAP_Pos) /*!< 0x00000002 */ 2892 #define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /*!< TIM16 remapping */ 2893 #define AFIO_MAPR2_TIM17_REMAP_Pos (2U) 2894 #define AFIO_MAPR2_TIM17_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM17_REMAP_Pos) /*!< 0x00000004 */ 2895 #define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /*!< TIM17 remapping */ 2896 #define AFIO_MAPR2_CEC_REMAP_Pos (3U) 2897 #define AFIO_MAPR2_CEC_REMAP_Msk (0x1UL << AFIO_MAPR2_CEC_REMAP_Pos) /*!< 0x00000008 */ 2898 #define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /*!< CEC remapping */ 2899 #define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U) 2900 #define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /*!< 0x00000010 */ 2901 #define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /*!< TIM1_DMA remapping */ 2902 2903 #define AFIO_MAPR2_TIM13_REMAP_Pos (8U) 2904 #define AFIO_MAPR2_TIM13_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */ 2905 #define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /*!< TIM13 remapping */ 2906 #define AFIO_MAPR2_TIM14_REMAP_Pos (9U) 2907 #define AFIO_MAPR2_TIM14_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */ 2908 #define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /*!< TIM14 remapping */ 2909 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U) 2910 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /*!< 0x00000800 */ 2911 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */ 2912 #define AFIO_MAPR2_TIM12_REMAP_Pos (12U) 2913 #define AFIO_MAPR2_TIM12_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM12_REMAP_Pos) /*!< 0x00001000 */ 2914 #define AFIO_MAPR2_TIM12_REMAP AFIO_MAPR2_TIM12_REMAP_Msk /*!< TIM12 remapping */ 2915 #define AFIO_MAPR2_MISC_REMAP_Pos (13U) 2916 #define AFIO_MAPR2_MISC_REMAP_Msk (0x1UL << AFIO_MAPR2_MISC_REMAP_Pos) /*!< 0x00002000 */ 2917 #define AFIO_MAPR2_MISC_REMAP AFIO_MAPR2_MISC_REMAP_Msk /*!< Miscellaneous remapping */ 2918 2919 #define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U) 2920 #define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */ 2921 #define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */ 2922 2923 /******************************************************************************/ 2924 /* */ 2925 /* External Interrupt/Event Controller */ 2926 /* */ 2927 /******************************************************************************/ 2928 2929 /******************* Bit definition for EXTI_IMR register *******************/ 2930 #define EXTI_IMR_MR0_Pos (0U) 2931 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2932 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2933 #define EXTI_IMR_MR1_Pos (1U) 2934 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2935 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2936 #define EXTI_IMR_MR2_Pos (2U) 2937 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2938 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2939 #define EXTI_IMR_MR3_Pos (3U) 2940 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2941 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2942 #define EXTI_IMR_MR4_Pos (4U) 2943 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2944 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2945 #define EXTI_IMR_MR5_Pos (5U) 2946 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2947 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2948 #define EXTI_IMR_MR6_Pos (6U) 2949 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2950 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2951 #define EXTI_IMR_MR7_Pos (7U) 2952 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2953 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2954 #define EXTI_IMR_MR8_Pos (8U) 2955 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2956 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2957 #define EXTI_IMR_MR9_Pos (9U) 2958 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2959 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2960 #define EXTI_IMR_MR10_Pos (10U) 2961 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2962 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2963 #define EXTI_IMR_MR11_Pos (11U) 2964 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2965 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2966 #define EXTI_IMR_MR12_Pos (12U) 2967 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2968 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2969 #define EXTI_IMR_MR13_Pos (13U) 2970 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2971 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2972 #define EXTI_IMR_MR14_Pos (14U) 2973 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2974 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2975 #define EXTI_IMR_MR15_Pos (15U) 2976 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2977 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2978 #define EXTI_IMR_MR16_Pos (16U) 2979 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2980 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2981 #define EXTI_IMR_MR17_Pos (17U) 2982 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2983 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2984 2985 /* References Defines */ 2986 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2987 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2988 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2989 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2990 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2991 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2992 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2993 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2994 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2995 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2996 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2997 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2998 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2999 #define EXTI_IMR_IM13 EXTI_IMR_MR13 3000 #define EXTI_IMR_IM14 EXTI_IMR_MR14 3001 #define EXTI_IMR_IM15 EXTI_IMR_MR15 3002 #define EXTI_IMR_IM16 EXTI_IMR_MR16 3003 #define EXTI_IMR_IM17 EXTI_IMR_MR17 3004 #define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */ 3005 3006 /******************* Bit definition for EXTI_EMR register *******************/ 3007 #define EXTI_EMR_MR0_Pos (0U) 3008 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 3009 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 3010 #define EXTI_EMR_MR1_Pos (1U) 3011 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 3012 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 3013 #define EXTI_EMR_MR2_Pos (2U) 3014 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 3015 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 3016 #define EXTI_EMR_MR3_Pos (3U) 3017 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 3018 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 3019 #define EXTI_EMR_MR4_Pos (4U) 3020 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 3021 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 3022 #define EXTI_EMR_MR5_Pos (5U) 3023 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 3024 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 3025 #define EXTI_EMR_MR6_Pos (6U) 3026 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 3027 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 3028 #define EXTI_EMR_MR7_Pos (7U) 3029 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 3030 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 3031 #define EXTI_EMR_MR8_Pos (8U) 3032 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 3033 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 3034 #define EXTI_EMR_MR9_Pos (9U) 3035 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 3036 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 3037 #define EXTI_EMR_MR10_Pos (10U) 3038 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 3039 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 3040 #define EXTI_EMR_MR11_Pos (11U) 3041 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 3042 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 3043 #define EXTI_EMR_MR12_Pos (12U) 3044 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 3045 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 3046 #define EXTI_EMR_MR13_Pos (13U) 3047 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 3048 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 3049 #define EXTI_EMR_MR14_Pos (14U) 3050 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 3051 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 3052 #define EXTI_EMR_MR15_Pos (15U) 3053 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 3054 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 3055 #define EXTI_EMR_MR16_Pos (16U) 3056 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 3057 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 3058 #define EXTI_EMR_MR17_Pos (17U) 3059 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 3060 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 3061 3062 /* References Defines */ 3063 #define EXTI_EMR_EM0 EXTI_EMR_MR0 3064 #define EXTI_EMR_EM1 EXTI_EMR_MR1 3065 #define EXTI_EMR_EM2 EXTI_EMR_MR2 3066 #define EXTI_EMR_EM3 EXTI_EMR_MR3 3067 #define EXTI_EMR_EM4 EXTI_EMR_MR4 3068 #define EXTI_EMR_EM5 EXTI_EMR_MR5 3069 #define EXTI_EMR_EM6 EXTI_EMR_MR6 3070 #define EXTI_EMR_EM7 EXTI_EMR_MR7 3071 #define EXTI_EMR_EM8 EXTI_EMR_MR8 3072 #define EXTI_EMR_EM9 EXTI_EMR_MR9 3073 #define EXTI_EMR_EM10 EXTI_EMR_MR10 3074 #define EXTI_EMR_EM11 EXTI_EMR_MR11 3075 #define EXTI_EMR_EM12 EXTI_EMR_MR12 3076 #define EXTI_EMR_EM13 EXTI_EMR_MR13 3077 #define EXTI_EMR_EM14 EXTI_EMR_MR14 3078 #define EXTI_EMR_EM15 EXTI_EMR_MR15 3079 #define EXTI_EMR_EM16 EXTI_EMR_MR16 3080 #define EXTI_EMR_EM17 EXTI_EMR_MR17 3081 3082 /****************** Bit definition for EXTI_RTSR register *******************/ 3083 #define EXTI_RTSR_TR0_Pos (0U) 3084 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 3085 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 3086 #define EXTI_RTSR_TR1_Pos (1U) 3087 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 3088 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 3089 #define EXTI_RTSR_TR2_Pos (2U) 3090 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 3091 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 3092 #define EXTI_RTSR_TR3_Pos (3U) 3093 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 3094 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 3095 #define EXTI_RTSR_TR4_Pos (4U) 3096 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 3097 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 3098 #define EXTI_RTSR_TR5_Pos (5U) 3099 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 3100 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 3101 #define EXTI_RTSR_TR6_Pos (6U) 3102 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 3103 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 3104 #define EXTI_RTSR_TR7_Pos (7U) 3105 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 3106 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 3107 #define EXTI_RTSR_TR8_Pos (8U) 3108 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 3109 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 3110 #define EXTI_RTSR_TR9_Pos (9U) 3111 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 3112 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 3113 #define EXTI_RTSR_TR10_Pos (10U) 3114 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 3115 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 3116 #define EXTI_RTSR_TR11_Pos (11U) 3117 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 3118 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 3119 #define EXTI_RTSR_TR12_Pos (12U) 3120 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 3121 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 3122 #define EXTI_RTSR_TR13_Pos (13U) 3123 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 3124 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 3125 #define EXTI_RTSR_TR14_Pos (14U) 3126 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 3127 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 3128 #define EXTI_RTSR_TR15_Pos (15U) 3129 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 3130 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 3131 #define EXTI_RTSR_TR16_Pos (16U) 3132 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 3133 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 3134 #define EXTI_RTSR_TR17_Pos (17U) 3135 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 3136 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 3137 3138 /* References Defines */ 3139 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 3140 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 3141 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 3142 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 3143 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 3144 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 3145 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 3146 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 3147 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 3148 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 3149 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 3150 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 3151 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 3152 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 3153 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 3154 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 3155 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 3156 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 3157 3158 /****************** Bit definition for EXTI_FTSR register *******************/ 3159 #define EXTI_FTSR_TR0_Pos (0U) 3160 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 3161 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 3162 #define EXTI_FTSR_TR1_Pos (1U) 3163 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 3164 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 3165 #define EXTI_FTSR_TR2_Pos (2U) 3166 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 3167 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 3168 #define EXTI_FTSR_TR3_Pos (3U) 3169 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 3170 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 3171 #define EXTI_FTSR_TR4_Pos (4U) 3172 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 3173 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 3174 #define EXTI_FTSR_TR5_Pos (5U) 3175 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 3176 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 3177 #define EXTI_FTSR_TR6_Pos (6U) 3178 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 3179 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 3180 #define EXTI_FTSR_TR7_Pos (7U) 3181 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 3182 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 3183 #define EXTI_FTSR_TR8_Pos (8U) 3184 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 3185 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 3186 #define EXTI_FTSR_TR9_Pos (9U) 3187 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 3188 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 3189 #define EXTI_FTSR_TR10_Pos (10U) 3190 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 3191 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 3192 #define EXTI_FTSR_TR11_Pos (11U) 3193 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 3194 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 3195 #define EXTI_FTSR_TR12_Pos (12U) 3196 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 3197 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 3198 #define EXTI_FTSR_TR13_Pos (13U) 3199 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 3200 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 3201 #define EXTI_FTSR_TR14_Pos (14U) 3202 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 3203 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 3204 #define EXTI_FTSR_TR15_Pos (15U) 3205 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 3206 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 3207 #define EXTI_FTSR_TR16_Pos (16U) 3208 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 3209 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 3210 #define EXTI_FTSR_TR17_Pos (17U) 3211 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 3212 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 3213 3214 /* References Defines */ 3215 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 3216 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 3217 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 3218 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 3219 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 3220 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 3221 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 3222 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 3223 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 3224 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 3225 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 3226 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 3227 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 3228 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 3229 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 3230 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 3231 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 3232 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 3233 3234 /****************** Bit definition for EXTI_SWIER register ******************/ 3235 #define EXTI_SWIER_SWIER0_Pos (0U) 3236 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 3237 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 3238 #define EXTI_SWIER_SWIER1_Pos (1U) 3239 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 3240 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 3241 #define EXTI_SWIER_SWIER2_Pos (2U) 3242 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 3243 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 3244 #define EXTI_SWIER_SWIER3_Pos (3U) 3245 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 3246 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 3247 #define EXTI_SWIER_SWIER4_Pos (4U) 3248 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 3249 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 3250 #define EXTI_SWIER_SWIER5_Pos (5U) 3251 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 3252 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 3253 #define EXTI_SWIER_SWIER6_Pos (6U) 3254 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 3255 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 3256 #define EXTI_SWIER_SWIER7_Pos (7U) 3257 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 3258 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 3259 #define EXTI_SWIER_SWIER8_Pos (8U) 3260 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 3261 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 3262 #define EXTI_SWIER_SWIER9_Pos (9U) 3263 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 3264 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 3265 #define EXTI_SWIER_SWIER10_Pos (10U) 3266 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 3267 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 3268 #define EXTI_SWIER_SWIER11_Pos (11U) 3269 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 3270 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 3271 #define EXTI_SWIER_SWIER12_Pos (12U) 3272 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 3273 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 3274 #define EXTI_SWIER_SWIER13_Pos (13U) 3275 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 3276 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 3277 #define EXTI_SWIER_SWIER14_Pos (14U) 3278 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 3279 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 3280 #define EXTI_SWIER_SWIER15_Pos (15U) 3281 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 3282 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 3283 #define EXTI_SWIER_SWIER16_Pos (16U) 3284 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 3285 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 3286 #define EXTI_SWIER_SWIER17_Pos (17U) 3287 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 3288 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 3289 3290 /* References Defines */ 3291 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 3292 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 3293 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 3294 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 3295 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 3296 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 3297 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 3298 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 3299 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 3300 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 3301 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 3302 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 3303 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 3304 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 3305 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 3306 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 3307 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 3308 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 3309 3310 /******************* Bit definition for EXTI_PR register ********************/ 3311 #define EXTI_PR_PR0_Pos (0U) 3312 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 3313 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 3314 #define EXTI_PR_PR1_Pos (1U) 3315 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 3316 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 3317 #define EXTI_PR_PR2_Pos (2U) 3318 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 3319 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 3320 #define EXTI_PR_PR3_Pos (3U) 3321 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 3322 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 3323 #define EXTI_PR_PR4_Pos (4U) 3324 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 3325 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 3326 #define EXTI_PR_PR5_Pos (5U) 3327 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 3328 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 3329 #define EXTI_PR_PR6_Pos (6U) 3330 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 3331 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 3332 #define EXTI_PR_PR7_Pos (7U) 3333 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 3334 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 3335 #define EXTI_PR_PR8_Pos (8U) 3336 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 3337 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 3338 #define EXTI_PR_PR9_Pos (9U) 3339 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 3340 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 3341 #define EXTI_PR_PR10_Pos (10U) 3342 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 3343 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 3344 #define EXTI_PR_PR11_Pos (11U) 3345 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 3346 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 3347 #define EXTI_PR_PR12_Pos (12U) 3348 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3349 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3350 #define EXTI_PR_PR13_Pos (13U) 3351 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3352 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3353 #define EXTI_PR_PR14_Pos (14U) 3354 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3355 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3356 #define EXTI_PR_PR15_Pos (15U) 3357 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3358 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3359 #define EXTI_PR_PR16_Pos (16U) 3360 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3361 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3362 #define EXTI_PR_PR17_Pos (17U) 3363 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3364 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3365 3366 /* References Defines */ 3367 #define EXTI_PR_PIF0 EXTI_PR_PR0 3368 #define EXTI_PR_PIF1 EXTI_PR_PR1 3369 #define EXTI_PR_PIF2 EXTI_PR_PR2 3370 #define EXTI_PR_PIF3 EXTI_PR_PR3 3371 #define EXTI_PR_PIF4 EXTI_PR_PR4 3372 #define EXTI_PR_PIF5 EXTI_PR_PR5 3373 #define EXTI_PR_PIF6 EXTI_PR_PR6 3374 #define EXTI_PR_PIF7 EXTI_PR_PR7 3375 #define EXTI_PR_PIF8 EXTI_PR_PR8 3376 #define EXTI_PR_PIF9 EXTI_PR_PR9 3377 #define EXTI_PR_PIF10 EXTI_PR_PR10 3378 #define EXTI_PR_PIF11 EXTI_PR_PR11 3379 #define EXTI_PR_PIF12 EXTI_PR_PR12 3380 #define EXTI_PR_PIF13 EXTI_PR_PR13 3381 #define EXTI_PR_PIF14 EXTI_PR_PR14 3382 #define EXTI_PR_PIF15 EXTI_PR_PR15 3383 #define EXTI_PR_PIF16 EXTI_PR_PR16 3384 #define EXTI_PR_PIF17 EXTI_PR_PR17 3385 3386 /******************************************************************************/ 3387 /* */ 3388 /* DMA Controller */ 3389 /* */ 3390 /******************************************************************************/ 3391 3392 /******************* Bit definition for DMA_ISR register ********************/ 3393 #define DMA_ISR_GIF1_Pos (0U) 3394 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 3395 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 3396 #define DMA_ISR_TCIF1_Pos (1U) 3397 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 3398 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 3399 #define DMA_ISR_HTIF1_Pos (2U) 3400 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 3401 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 3402 #define DMA_ISR_TEIF1_Pos (3U) 3403 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 3404 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 3405 #define DMA_ISR_GIF2_Pos (4U) 3406 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 3407 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 3408 #define DMA_ISR_TCIF2_Pos (5U) 3409 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 3410 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 3411 #define DMA_ISR_HTIF2_Pos (6U) 3412 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 3413 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 3414 #define DMA_ISR_TEIF2_Pos (7U) 3415 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 3416 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 3417 #define DMA_ISR_GIF3_Pos (8U) 3418 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 3419 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 3420 #define DMA_ISR_TCIF3_Pos (9U) 3421 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 3422 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 3423 #define DMA_ISR_HTIF3_Pos (10U) 3424 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 3425 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 3426 #define DMA_ISR_TEIF3_Pos (11U) 3427 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 3428 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 3429 #define DMA_ISR_GIF4_Pos (12U) 3430 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 3431 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 3432 #define DMA_ISR_TCIF4_Pos (13U) 3433 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 3434 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 3435 #define DMA_ISR_HTIF4_Pos (14U) 3436 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 3437 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 3438 #define DMA_ISR_TEIF4_Pos (15U) 3439 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 3440 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 3441 #define DMA_ISR_GIF5_Pos (16U) 3442 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 3443 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 3444 #define DMA_ISR_TCIF5_Pos (17U) 3445 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 3446 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 3447 #define DMA_ISR_HTIF5_Pos (18U) 3448 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 3449 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 3450 #define DMA_ISR_TEIF5_Pos (19U) 3451 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 3452 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 3453 #define DMA_ISR_GIF6_Pos (20U) 3454 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 3455 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 3456 #define DMA_ISR_TCIF6_Pos (21U) 3457 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 3458 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 3459 #define DMA_ISR_HTIF6_Pos (22U) 3460 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 3461 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 3462 #define DMA_ISR_TEIF6_Pos (23U) 3463 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 3464 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 3465 #define DMA_ISR_GIF7_Pos (24U) 3466 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 3467 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 3468 #define DMA_ISR_TCIF7_Pos (25U) 3469 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 3470 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 3471 #define DMA_ISR_HTIF7_Pos (26U) 3472 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 3473 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 3474 #define DMA_ISR_TEIF7_Pos (27U) 3475 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 3476 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 3477 3478 /******************* Bit definition for DMA_IFCR register *******************/ 3479 #define DMA_IFCR_CGIF1_Pos (0U) 3480 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 3481 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 3482 #define DMA_IFCR_CTCIF1_Pos (1U) 3483 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 3484 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 3485 #define DMA_IFCR_CHTIF1_Pos (2U) 3486 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 3487 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 3488 #define DMA_IFCR_CTEIF1_Pos (3U) 3489 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 3490 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 3491 #define DMA_IFCR_CGIF2_Pos (4U) 3492 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 3493 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 3494 #define DMA_IFCR_CTCIF2_Pos (5U) 3495 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 3496 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 3497 #define DMA_IFCR_CHTIF2_Pos (6U) 3498 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 3499 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 3500 #define DMA_IFCR_CTEIF2_Pos (7U) 3501 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 3502 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 3503 #define DMA_IFCR_CGIF3_Pos (8U) 3504 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 3505 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 3506 #define DMA_IFCR_CTCIF3_Pos (9U) 3507 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 3508 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 3509 #define DMA_IFCR_CHTIF3_Pos (10U) 3510 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 3511 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 3512 #define DMA_IFCR_CTEIF3_Pos (11U) 3513 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 3514 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 3515 #define DMA_IFCR_CGIF4_Pos (12U) 3516 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 3517 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 3518 #define DMA_IFCR_CTCIF4_Pos (13U) 3519 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 3520 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 3521 #define DMA_IFCR_CHTIF4_Pos (14U) 3522 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 3523 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 3524 #define DMA_IFCR_CTEIF4_Pos (15U) 3525 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 3526 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 3527 #define DMA_IFCR_CGIF5_Pos (16U) 3528 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 3529 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 3530 #define DMA_IFCR_CTCIF5_Pos (17U) 3531 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 3532 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 3533 #define DMA_IFCR_CHTIF5_Pos (18U) 3534 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 3535 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 3536 #define DMA_IFCR_CTEIF5_Pos (19U) 3537 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 3538 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 3539 #define DMA_IFCR_CGIF6_Pos (20U) 3540 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 3541 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 3542 #define DMA_IFCR_CTCIF6_Pos (21U) 3543 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 3544 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 3545 #define DMA_IFCR_CHTIF6_Pos (22U) 3546 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 3547 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 3548 #define DMA_IFCR_CTEIF6_Pos (23U) 3549 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 3550 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 3551 #define DMA_IFCR_CGIF7_Pos (24U) 3552 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 3553 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 3554 #define DMA_IFCR_CTCIF7_Pos (25U) 3555 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 3556 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 3557 #define DMA_IFCR_CHTIF7_Pos (26U) 3558 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 3559 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 3560 #define DMA_IFCR_CTEIF7_Pos (27U) 3561 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 3562 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 3563 3564 /******************* Bit definition for DMA_CCR register *******************/ 3565 #define DMA_CCR_EN_Pos (0U) 3566 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 3567 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 3568 #define DMA_CCR_TCIE_Pos (1U) 3569 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 3570 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 3571 #define DMA_CCR_HTIE_Pos (2U) 3572 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 3573 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 3574 #define DMA_CCR_TEIE_Pos (3U) 3575 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 3576 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 3577 #define DMA_CCR_DIR_Pos (4U) 3578 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 3579 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 3580 #define DMA_CCR_CIRC_Pos (5U) 3581 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 3582 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 3583 #define DMA_CCR_PINC_Pos (6U) 3584 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 3585 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 3586 #define DMA_CCR_MINC_Pos (7U) 3587 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 3588 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 3589 3590 #define DMA_CCR_PSIZE_Pos (8U) 3591 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 3592 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 3593 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 3594 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 3595 3596 #define DMA_CCR_MSIZE_Pos (10U) 3597 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 3598 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 3599 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 3600 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 3601 3602 #define DMA_CCR_PL_Pos (12U) 3603 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 3604 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 3605 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 3606 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 3607 3608 #define DMA_CCR_MEM2MEM_Pos (14U) 3609 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 3610 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 3611 3612 /****************** Bit definition for DMA_CNDTR register ******************/ 3613 #define DMA_CNDTR_NDT_Pos (0U) 3614 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 3615 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 3616 3617 /****************** Bit definition for DMA_CPAR register *******************/ 3618 #define DMA_CPAR_PA_Pos (0U) 3619 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 3620 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 3621 3622 /****************** Bit definition for DMA_CMAR register *******************/ 3623 #define DMA_CMAR_MA_Pos (0U) 3624 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 3625 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 3626 3627 /******************************************************************************/ 3628 /* */ 3629 /* Analog to Digital Converter (ADC) */ 3630 /* */ 3631 /******************************************************************************/ 3632 3633 /* 3634 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) 3635 */ 3636 /* Note: No specific macro feature on this device */ 3637 3638 /******************** Bit definition for ADC_SR register ********************/ 3639 #define ADC_SR_AWD_Pos (0U) 3640 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 3641 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 3642 #define ADC_SR_EOS_Pos (1U) 3643 #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ 3644 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 3645 #define ADC_SR_JEOS_Pos (2U) 3646 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 3647 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 3648 #define ADC_SR_JSTRT_Pos (3U) 3649 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 3650 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 3651 #define ADC_SR_STRT_Pos (4U) 3652 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 3653 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 3654 3655 /* Legacy defines */ 3656 #define ADC_SR_EOC (ADC_SR_EOS) 3657 #define ADC_SR_JEOC (ADC_SR_JEOS) 3658 3659 /******************* Bit definition for ADC_CR1 register ********************/ 3660 #define ADC_CR1_AWDCH_Pos (0U) 3661 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 3662 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 3663 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 3664 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 3665 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 3666 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 3667 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 3668 3669 #define ADC_CR1_EOSIE_Pos (5U) 3670 #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ 3671 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 3672 #define ADC_CR1_AWDIE_Pos (6U) 3673 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 3674 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 3675 #define ADC_CR1_JEOSIE_Pos (7U) 3676 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 3677 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 3678 #define ADC_CR1_SCAN_Pos (8U) 3679 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 3680 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 3681 #define ADC_CR1_AWDSGL_Pos (9U) 3682 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 3683 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 3684 #define ADC_CR1_JAUTO_Pos (10U) 3685 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 3686 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 3687 #define ADC_CR1_DISCEN_Pos (11U) 3688 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 3689 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 3690 #define ADC_CR1_JDISCEN_Pos (12U) 3691 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 3692 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 3693 3694 #define ADC_CR1_DISCNUM_Pos (13U) 3695 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 3696 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 3697 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 3698 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 3699 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 3700 3701 #define ADC_CR1_JAWDEN_Pos (22U) 3702 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 3703 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 3704 #define ADC_CR1_AWDEN_Pos (23U) 3705 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 3706 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 3707 3708 /* Legacy defines */ 3709 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) 3710 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 3711 3712 /******************* Bit definition for ADC_CR2 register ********************/ 3713 #define ADC_CR2_ADON_Pos (0U) 3714 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 3715 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 3716 #define ADC_CR2_CONT_Pos (1U) 3717 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 3718 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 3719 #define ADC_CR2_CAL_Pos (2U) 3720 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ 3721 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ 3722 #define ADC_CR2_RSTCAL_Pos (3U) 3723 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ 3724 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ 3725 #define ADC_CR2_DMA_Pos (8U) 3726 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 3727 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 3728 #define ADC_CR2_ALIGN_Pos (11U) 3729 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 3730 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 3731 3732 #define ADC_CR2_JEXTSEL_Pos (12U) 3733 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ 3734 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 3735 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ 3736 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ 3737 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ 3738 3739 #define ADC_CR2_JEXTTRIG_Pos (15U) 3740 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ 3741 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ 3742 3743 #define ADC_CR2_EXTSEL_Pos (17U) 3744 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ 3745 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 3746 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ 3747 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ 3748 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ 3749 3750 #define ADC_CR2_EXTTRIG_Pos (20U) 3751 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ 3752 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ 3753 #define ADC_CR2_JSWSTART_Pos (21U) 3754 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ 3755 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 3756 #define ADC_CR2_SWSTART_Pos (22U) 3757 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ 3758 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 3759 #define ADC_CR2_TSVREFE_Pos (23U) 3760 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ 3761 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 3762 3763 /****************** Bit definition for ADC_SMPR1 register *******************/ 3764 #define ADC_SMPR1_SMP10_Pos (0U) 3765 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ 3766 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 3767 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ 3768 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ 3769 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ 3770 3771 #define ADC_SMPR1_SMP11_Pos (3U) 3772 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ 3773 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 3774 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ 3775 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ 3776 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ 3777 3778 #define ADC_SMPR1_SMP12_Pos (6U) 3779 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ 3780 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 3781 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ 3782 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ 3783 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ 3784 3785 #define ADC_SMPR1_SMP13_Pos (9U) 3786 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ 3787 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 3788 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ 3789 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ 3790 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ 3791 3792 #define ADC_SMPR1_SMP14_Pos (12U) 3793 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ 3794 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 3795 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ 3796 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ 3797 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ 3798 3799 #define ADC_SMPR1_SMP15_Pos (15U) 3800 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ 3801 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 3802 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ 3803 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ 3804 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ 3805 3806 #define ADC_SMPR1_SMP16_Pos (18U) 3807 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ 3808 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 3809 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ 3810 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ 3811 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ 3812 3813 #define ADC_SMPR1_SMP17_Pos (21U) 3814 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ 3815 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 3816 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ 3817 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ 3818 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ 3819 3820 /****************** Bit definition for ADC_SMPR2 register *******************/ 3821 #define ADC_SMPR2_SMP0_Pos (0U) 3822 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ 3823 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 3824 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ 3825 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ 3826 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ 3827 3828 #define ADC_SMPR2_SMP1_Pos (3U) 3829 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ 3830 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 3831 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ 3832 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ 3833 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ 3834 3835 #define ADC_SMPR2_SMP2_Pos (6U) 3836 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ 3837 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 3838 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ 3839 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ 3840 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ 3841 3842 #define ADC_SMPR2_SMP3_Pos (9U) 3843 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ 3844 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 3845 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ 3846 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ 3847 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ 3848 3849 #define ADC_SMPR2_SMP4_Pos (12U) 3850 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ 3851 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 3852 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ 3853 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ 3854 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ 3855 3856 #define ADC_SMPR2_SMP5_Pos (15U) 3857 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ 3858 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 3859 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ 3860 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ 3861 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ 3862 3863 #define ADC_SMPR2_SMP6_Pos (18U) 3864 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ 3865 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 3866 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ 3867 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ 3868 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ 3869 3870 #define ADC_SMPR2_SMP7_Pos (21U) 3871 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ 3872 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 3873 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ 3874 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ 3875 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ 3876 3877 #define ADC_SMPR2_SMP8_Pos (24U) 3878 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ 3879 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 3880 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ 3881 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ 3882 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ 3883 3884 #define ADC_SMPR2_SMP9_Pos (27U) 3885 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ 3886 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 3887 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ 3888 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ 3889 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ 3890 3891 /****************** Bit definition for ADC_JOFR1 register *******************/ 3892 #define ADC_JOFR1_JOFFSET1_Pos (0U) 3893 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 3894 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 3895 3896 /****************** Bit definition for ADC_JOFR2 register *******************/ 3897 #define ADC_JOFR2_JOFFSET2_Pos (0U) 3898 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 3899 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 3900 3901 /****************** Bit definition for ADC_JOFR3 register *******************/ 3902 #define ADC_JOFR3_JOFFSET3_Pos (0U) 3903 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 3904 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 3905 3906 /****************** Bit definition for ADC_JOFR4 register *******************/ 3907 #define ADC_JOFR4_JOFFSET4_Pos (0U) 3908 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 3909 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 3910 3911 /******************* Bit definition for ADC_HTR register ********************/ 3912 #define ADC_HTR_HT_Pos (0U) 3913 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 3914 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 3915 3916 /******************* Bit definition for ADC_LTR register ********************/ 3917 #define ADC_LTR_LT_Pos (0U) 3918 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 3919 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 3920 3921 /******************* Bit definition for ADC_SQR1 register *******************/ 3922 #define ADC_SQR1_SQ13_Pos (0U) 3923 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ 3924 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 3925 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ 3926 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ 3927 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ 3928 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ 3929 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ 3930 3931 #define ADC_SQR1_SQ14_Pos (5U) 3932 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ 3933 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 3934 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ 3935 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ 3936 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ 3937 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ 3938 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ 3939 3940 #define ADC_SQR1_SQ15_Pos (10U) 3941 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ 3942 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 3943 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ 3944 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ 3945 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ 3946 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ 3947 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ 3948 3949 #define ADC_SQR1_SQ16_Pos (15U) 3950 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ 3951 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 3952 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ 3953 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ 3954 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ 3955 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ 3956 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ 3957 3958 #define ADC_SQR1_L_Pos (20U) 3959 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ 3960 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 3961 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 3962 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 3963 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 3964 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 3965 3966 /******************* Bit definition for ADC_SQR2 register *******************/ 3967 #define ADC_SQR2_SQ7_Pos (0U) 3968 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ 3969 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 3970 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ 3971 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ 3972 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ 3973 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ 3974 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ 3975 3976 #define ADC_SQR2_SQ8_Pos (5U) 3977 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ 3978 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 3979 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ 3980 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ 3981 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ 3982 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ 3983 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ 3984 3985 #define ADC_SQR2_SQ9_Pos (10U) 3986 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ 3987 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 3988 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ 3989 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ 3990 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ 3991 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ 3992 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ 3993 3994 #define ADC_SQR2_SQ10_Pos (15U) 3995 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ 3996 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 3997 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ 3998 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ 3999 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ 4000 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ 4001 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ 4002 4003 #define ADC_SQR2_SQ11_Pos (20U) 4004 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ 4005 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ 4006 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ 4007 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ 4008 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ 4009 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ 4010 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ 4011 4012 #define ADC_SQR2_SQ12_Pos (25U) 4013 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ 4014 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 4015 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ 4016 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ 4017 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ 4018 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ 4019 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ 4020 4021 /******************* Bit definition for ADC_SQR3 register *******************/ 4022 #define ADC_SQR3_SQ1_Pos (0U) 4023 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ 4024 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 4025 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ 4026 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ 4027 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ 4028 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ 4029 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ 4030 4031 #define ADC_SQR3_SQ2_Pos (5U) 4032 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ 4033 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 4034 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ 4035 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ 4036 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ 4037 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ 4038 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ 4039 4040 #define ADC_SQR3_SQ3_Pos (10U) 4041 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ 4042 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 4043 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ 4044 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ 4045 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ 4046 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ 4047 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ 4048 4049 #define ADC_SQR3_SQ4_Pos (15U) 4050 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ 4051 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 4052 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ 4053 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ 4054 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ 4055 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ 4056 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ 4057 4058 #define ADC_SQR3_SQ5_Pos (20U) 4059 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ 4060 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 4061 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ 4062 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ 4063 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ 4064 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ 4065 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ 4066 4067 #define ADC_SQR3_SQ6_Pos (25U) 4068 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ 4069 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 4070 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ 4071 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ 4072 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ 4073 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ 4074 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ 4075 4076 /******************* Bit definition for ADC_JSQR register *******************/ 4077 #define ADC_JSQR_JSQ1_Pos (0U) 4078 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 4079 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 4080 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 4081 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 4082 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 4083 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 4084 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 4085 4086 #define ADC_JSQR_JSQ2_Pos (5U) 4087 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 4088 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 4089 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 4090 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 4091 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 4092 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 4093 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 4094 4095 #define ADC_JSQR_JSQ3_Pos (10U) 4096 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 4097 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 4098 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 4099 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 4100 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 4101 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 4102 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 4103 4104 #define ADC_JSQR_JSQ4_Pos (15U) 4105 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 4106 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 4107 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 4108 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 4109 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 4110 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 4111 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 4112 4113 #define ADC_JSQR_JL_Pos (20U) 4114 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 4115 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 4116 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 4117 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 4118 4119 /******************* Bit definition for ADC_JDR1 register *******************/ 4120 #define ADC_JDR1_JDATA_Pos (0U) 4121 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 4122 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 4123 4124 /******************* Bit definition for ADC_JDR2 register *******************/ 4125 #define ADC_JDR2_JDATA_Pos (0U) 4126 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 4127 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 4128 4129 /******************* Bit definition for ADC_JDR3 register *******************/ 4130 #define ADC_JDR3_JDATA_Pos (0U) 4131 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 4132 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 4133 4134 /******************* Bit definition for ADC_JDR4 register *******************/ 4135 #define ADC_JDR4_JDATA_Pos (0U) 4136 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 4137 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 4138 4139 /******************** Bit definition for ADC_DR register ********************/ 4140 #define ADC_DR_DATA_Pos (0U) 4141 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 4142 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 4143 /******************************************************************************/ 4144 /* */ 4145 /* Digital to Analog Converter */ 4146 /* */ 4147 /******************************************************************************/ 4148 4149 /******************** Bit definition for DAC_CR register ********************/ 4150 #define DAC_CR_EN1_Pos (0U) 4151 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 4152 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ 4153 #define DAC_CR_BOFF1_Pos (1U) 4154 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 4155 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ 4156 #define DAC_CR_TEN1_Pos (2U) 4157 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 4158 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ 4159 4160 #define DAC_CR_TSEL1_Pos (3U) 4161 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 4162 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 4163 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 4164 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 4165 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 4166 4167 #define DAC_CR_WAVE1_Pos (6U) 4168 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 4169 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 4170 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 4171 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 4172 4173 #define DAC_CR_MAMP1_Pos (8U) 4174 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 4175 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 4176 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 4177 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 4178 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 4179 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 4180 4181 #define DAC_CR_DMAEN1_Pos (12U) 4182 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 4183 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ 4184 #define DAC_CR_EN2_Pos (16U) 4185 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 4186 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ 4187 #define DAC_CR_BOFF2_Pos (17U) 4188 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 4189 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ 4190 #define DAC_CR_TEN2_Pos (18U) 4191 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 4192 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ 4193 4194 #define DAC_CR_TSEL2_Pos (19U) 4195 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 4196 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ 4197 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 4198 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 4199 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 4200 4201 #define DAC_CR_WAVE2_Pos (22U) 4202 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 4203 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 4204 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 4205 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 4206 4207 #define DAC_CR_MAMP2_Pos (24U) 4208 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 4209 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 4210 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 4211 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 4212 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 4213 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 4214 4215 #define DAC_CR_DMAEN2_Pos (28U) 4216 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 4217 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ 4218 4219 #define DAC_CR_DMAUDRIE1_Pos (13U) 4220 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 4221 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun interrupt enable */ 4222 #define DAC_CR_DMAUDRIE2_Pos (29U) 4223 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 4224 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun interrupt enable */ 4225 4226 /***************** Bit definition for DAC_SWTRIGR register ******************/ 4227 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 4228 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 4229 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ 4230 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 4231 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 4232 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ 4233 4234 /***************** Bit definition for DAC_DHR12R1 register ******************/ 4235 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 4236 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 4237 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 4238 4239 /***************** Bit definition for DAC_DHR12L1 register ******************/ 4240 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 4241 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 4242 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 4243 4244 /****************** Bit definition for DAC_DHR8R1 register ******************/ 4245 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 4246 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 4247 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 4248 4249 /***************** Bit definition for DAC_DHR12R2 register ******************/ 4250 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 4251 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 4252 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 4253 4254 /***************** Bit definition for DAC_DHR12L2 register ******************/ 4255 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 4256 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 4257 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 4258 4259 /****************** Bit definition for DAC_DHR8R2 register ******************/ 4260 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 4261 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 4262 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 4263 4264 /***************** Bit definition for DAC_DHR12RD register ******************/ 4265 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 4266 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 4267 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 4268 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 4269 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 4270 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 4271 4272 /***************** Bit definition for DAC_DHR12LD register ******************/ 4273 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 4274 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 4275 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 4276 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 4277 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 4278 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 4279 4280 /****************** Bit definition for DAC_DHR8RD register ******************/ 4281 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 4282 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 4283 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 4284 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 4285 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 4286 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 4287 4288 /******************* Bit definition for DAC_DOR1 register *******************/ 4289 #define DAC_DOR1_DACC1DOR_Pos (0U) 4290 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 4291 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ 4292 4293 /******************* Bit definition for DAC_DOR2 register *******************/ 4294 #define DAC_DOR2_DACC2DOR_Pos (0U) 4295 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 4296 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ 4297 4298 /******************** Bit definition for DAC_SR register ********************/ 4299 #define DAC_SR_DMAUDR1_Pos (13U) 4300 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 4301 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ 4302 #define DAC_SR_DMAUDR2_Pos (29U) 4303 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 4304 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ 4305 4306 /******************************************************************************/ 4307 /* */ 4308 /* CEC */ 4309 /* */ 4310 /******************************************************************************/ 4311 /******************** Bit definition for CEC_CFGR register ******************/ 4312 #define CEC_CFGR_PE_Pos (0U) 4313 #define CEC_CFGR_PE_Msk (0x1UL << CEC_CFGR_PE_Pos) /*!< 0x00000001 */ 4314 #define CEC_CFGR_PE CEC_CFGR_PE_Msk /*!< Peripheral Enable */ 4315 #define CEC_CFGR_IE_Pos (1U) 4316 #define CEC_CFGR_IE_Msk (0x1UL << CEC_CFGR_IE_Pos) /*!< 0x00000002 */ 4317 #define CEC_CFGR_IE CEC_CFGR_IE_Msk /*!< Interrupt Enable */ 4318 #define CEC_CFGR_BTEM_Pos (2U) 4319 #define CEC_CFGR_BTEM_Msk (0x1UL << CEC_CFGR_BTEM_Pos) /*!< 0x00000004 */ 4320 #define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /*!< Bit Timing Error Mode */ 4321 #define CEC_CFGR_BPEM_Pos (3U) 4322 #define CEC_CFGR_BPEM_Msk (0x1UL << CEC_CFGR_BPEM_Pos) /*!< 0x00000008 */ 4323 #define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /*!< Bit Period Error Mode */ 4324 4325 /******************** Bit definition for CEC_OAR register ******************/ 4326 #define CEC_OAR_OA_Pos (0U) 4327 #define CEC_OAR_OA_Msk (0xFUL << CEC_OAR_OA_Pos) /*!< 0x0000000F */ 4328 #define CEC_OAR_OA CEC_OAR_OA_Msk /*!< OA[3:0]: Own Address */ 4329 #define CEC_OAR_OA_0 (0x1UL << CEC_OAR_OA_Pos) /*!< 0x00000001 */ 4330 #define CEC_OAR_OA_1 (0x2UL << CEC_OAR_OA_Pos) /*!< 0x00000002 */ 4331 #define CEC_OAR_OA_2 (0x4UL << CEC_OAR_OA_Pos) /*!< 0x00000004 */ 4332 #define CEC_OAR_OA_3 (0x8UL << CEC_OAR_OA_Pos) /*!< 0x00000008 */ 4333 4334 /******************** Bit definition for CEC_PRES register ******************/ 4335 #define CEC_PRES_PRES_Pos (0U) 4336 #define CEC_PRES_PRES_Msk (0x3FFFUL << CEC_PRES_PRES_Pos) /*!< 0x00003FFF */ 4337 #define CEC_PRES_PRES CEC_PRES_PRES_Msk /*!< Prescaler Counter Value */ 4338 4339 /******************** Bit definition for CEC_ESR register ******************/ 4340 #define CEC_ESR_BTE_Pos (0U) 4341 #define CEC_ESR_BTE_Msk (0x1UL << CEC_ESR_BTE_Pos) /*!< 0x00000001 */ 4342 #define CEC_ESR_BTE CEC_ESR_BTE_Msk /*!< Bit Timing Error */ 4343 #define CEC_ESR_BPE_Pos (1U) 4344 #define CEC_ESR_BPE_Msk (0x1UL << CEC_ESR_BPE_Pos) /*!< 0x00000002 */ 4345 #define CEC_ESR_BPE CEC_ESR_BPE_Msk /*!< Bit Period Error */ 4346 #define CEC_ESR_RBTFE_Pos (2U) 4347 #define CEC_ESR_RBTFE_Msk (0x1UL << CEC_ESR_RBTFE_Pos) /*!< 0x00000004 */ 4348 #define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /*!< Rx Block Transfer Finished Error */ 4349 #define CEC_ESR_SBE_Pos (3U) 4350 #define CEC_ESR_SBE_Msk (0x1UL << CEC_ESR_SBE_Pos) /*!< 0x00000008 */ 4351 #define CEC_ESR_SBE CEC_ESR_SBE_Msk /*!< Start Bit Error */ 4352 #define CEC_ESR_ACKE_Pos (4U) 4353 #define CEC_ESR_ACKE_Msk (0x1UL << CEC_ESR_ACKE_Pos) /*!< 0x00000010 */ 4354 #define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /*!< Block Acknowledge Error */ 4355 #define CEC_ESR_LINE_Pos (5U) 4356 #define CEC_ESR_LINE_Msk (0x1UL << CEC_ESR_LINE_Pos) /*!< 0x00000020 */ 4357 #define CEC_ESR_LINE CEC_ESR_LINE_Msk /*!< Line Error */ 4358 #define CEC_ESR_TBTFE_Pos (6U) 4359 #define CEC_ESR_TBTFE_Msk (0x1UL << CEC_ESR_TBTFE_Pos) /*!< 0x00000040 */ 4360 #define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /*!< Tx Block Transfer Finished Error */ 4361 4362 /******************** Bit definition for CEC_CSR register ******************/ 4363 #define CEC_CSR_TSOM_Pos (0U) 4364 #define CEC_CSR_TSOM_Msk (0x1UL << CEC_CSR_TSOM_Pos) /*!< 0x00000001 */ 4365 #define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /*!< Tx Start Of Message */ 4366 #define CEC_CSR_TEOM_Pos (1U) 4367 #define CEC_CSR_TEOM_Msk (0x1UL << CEC_CSR_TEOM_Pos) /*!< 0x00000002 */ 4368 #define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /*!< Tx End Of Message */ 4369 #define CEC_CSR_TERR_Pos (2U) 4370 #define CEC_CSR_TERR_Msk (0x1UL << CEC_CSR_TERR_Pos) /*!< 0x00000004 */ 4371 #define CEC_CSR_TERR CEC_CSR_TERR_Msk /*!< Tx Error */ 4372 #define CEC_CSR_TBTRF_Pos (3U) 4373 #define CEC_CSR_TBTRF_Msk (0x1UL << CEC_CSR_TBTRF_Pos) /*!< 0x00000008 */ 4374 #define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /*!< Tx Byte Transfer Request or Block Transfer Finished */ 4375 #define CEC_CSR_RSOM_Pos (4U) 4376 #define CEC_CSR_RSOM_Msk (0x1UL << CEC_CSR_RSOM_Pos) /*!< 0x00000010 */ 4377 #define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /*!< Rx Start Of Message */ 4378 #define CEC_CSR_REOM_Pos (5U) 4379 #define CEC_CSR_REOM_Msk (0x1UL << CEC_CSR_REOM_Pos) /*!< 0x00000020 */ 4380 #define CEC_CSR_REOM CEC_CSR_REOM_Msk /*!< Rx End Of Message */ 4381 #define CEC_CSR_RERR_Pos (6U) 4382 #define CEC_CSR_RERR_Msk (0x1UL << CEC_CSR_RERR_Pos) /*!< 0x00000040 */ 4383 #define CEC_CSR_RERR CEC_CSR_RERR_Msk /*!< Rx Error */ 4384 #define CEC_CSR_RBTF_Pos (7U) 4385 #define CEC_CSR_RBTF_Msk (0x1UL << CEC_CSR_RBTF_Pos) /*!< 0x00000080 */ 4386 #define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /*!< Rx Block Transfer Finished */ 4387 4388 /******************** Bit definition for CEC_TXD register ******************/ 4389 #define CEC_TXD_TXD_Pos (0U) 4390 #define CEC_TXD_TXD_Msk (0xFFUL << CEC_TXD_TXD_Pos) /*!< 0x000000FF */ 4391 #define CEC_TXD_TXD CEC_TXD_TXD_Msk /*!< Tx Data register */ 4392 4393 /******************** Bit definition for CEC_RXD register ******************/ 4394 #define CEC_RXD_RXD_Pos (0U) 4395 #define CEC_RXD_RXD_Msk (0xFFUL << CEC_RXD_RXD_Pos) /*!< 0x000000FF */ 4396 #define CEC_RXD_RXD CEC_RXD_RXD_Msk /*!< Rx Data register */ 4397 4398 /*****************************************************************************/ 4399 /* */ 4400 /* Timers (TIM) */ 4401 /* */ 4402 /*****************************************************************************/ 4403 /******************* Bit definition for TIM_CR1 register *******************/ 4404 #define TIM_CR1_CEN_Pos (0U) 4405 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4406 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4407 #define TIM_CR1_UDIS_Pos (1U) 4408 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4409 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4410 #define TIM_CR1_URS_Pos (2U) 4411 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4412 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4413 #define TIM_CR1_OPM_Pos (3U) 4414 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4415 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4416 #define TIM_CR1_DIR_Pos (4U) 4417 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4418 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4419 4420 #define TIM_CR1_CMS_Pos (5U) 4421 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4422 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4423 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4424 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4425 4426 #define TIM_CR1_ARPE_Pos (7U) 4427 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4428 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4429 4430 #define TIM_CR1_CKD_Pos (8U) 4431 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4432 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4433 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4434 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4435 4436 /******************* Bit definition for TIM_CR2 register *******************/ 4437 #define TIM_CR2_CCPC_Pos (0U) 4438 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 4439 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 4440 #define TIM_CR2_CCUS_Pos (2U) 4441 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 4442 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 4443 #define TIM_CR2_CCDS_Pos (3U) 4444 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4445 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4446 4447 #define TIM_CR2_MMS_Pos (4U) 4448 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4449 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4450 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4451 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4452 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4453 4454 #define TIM_CR2_TI1S_Pos (7U) 4455 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4456 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4457 #define TIM_CR2_OIS1_Pos (8U) 4458 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 4459 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 4460 #define TIM_CR2_OIS1N_Pos (9U) 4461 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 4462 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 4463 #define TIM_CR2_OIS2_Pos (10U) 4464 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 4465 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 4466 #define TIM_CR2_OIS2N_Pos (11U) 4467 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 4468 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 4469 #define TIM_CR2_OIS3_Pos (12U) 4470 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 4471 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 4472 #define TIM_CR2_OIS3N_Pos (13U) 4473 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 4474 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 4475 #define TIM_CR2_OIS4_Pos (14U) 4476 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 4477 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 4478 4479 /******************* Bit definition for TIM_SMCR register ******************/ 4480 #define TIM_SMCR_SMS_Pos (0U) 4481 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4482 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4483 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4484 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4485 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4486 4487 #define TIM_SMCR_TS_Pos (4U) 4488 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4489 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4490 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4491 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4492 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4493 4494 #define TIM_SMCR_MSM_Pos (7U) 4495 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4496 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4497 4498 #define TIM_SMCR_ETF_Pos (8U) 4499 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4500 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4501 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4502 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4503 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4504 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 4505 4506 #define TIM_SMCR_ETPS_Pos (12U) 4507 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 4508 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 4509 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 4510 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 4511 4512 #define TIM_SMCR_ECE_Pos (14U) 4513 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 4514 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 4515 #define TIM_SMCR_ETP_Pos (15U) 4516 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 4517 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 4518 4519 /******************* Bit definition for TIM_DIER register ******************/ 4520 #define TIM_DIER_UIE_Pos (0U) 4521 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 4522 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 4523 #define TIM_DIER_CC1IE_Pos (1U) 4524 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 4525 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 4526 #define TIM_DIER_CC2IE_Pos (2U) 4527 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 4528 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 4529 #define TIM_DIER_CC3IE_Pos (3U) 4530 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 4531 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 4532 #define TIM_DIER_CC4IE_Pos (4U) 4533 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 4534 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 4535 #define TIM_DIER_COMIE_Pos (5U) 4536 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 4537 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 4538 #define TIM_DIER_TIE_Pos (6U) 4539 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 4540 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 4541 #define TIM_DIER_BIE_Pos (7U) 4542 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 4543 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 4544 #define TIM_DIER_UDE_Pos (8U) 4545 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 4546 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 4547 #define TIM_DIER_CC1DE_Pos (9U) 4548 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 4549 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 4550 #define TIM_DIER_CC2DE_Pos (10U) 4551 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 4552 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 4553 #define TIM_DIER_CC3DE_Pos (11U) 4554 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 4555 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 4556 #define TIM_DIER_CC4DE_Pos (12U) 4557 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 4558 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 4559 #define TIM_DIER_COMDE_Pos (13U) 4560 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 4561 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 4562 #define TIM_DIER_TDE_Pos (14U) 4563 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 4564 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 4565 4566 /******************** Bit definition for TIM_SR register *******************/ 4567 #define TIM_SR_UIF_Pos (0U) 4568 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 4569 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 4570 #define TIM_SR_CC1IF_Pos (1U) 4571 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 4572 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 4573 #define TIM_SR_CC2IF_Pos (2U) 4574 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 4575 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 4576 #define TIM_SR_CC3IF_Pos (3U) 4577 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 4578 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 4579 #define TIM_SR_CC4IF_Pos (4U) 4580 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 4581 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 4582 #define TIM_SR_COMIF_Pos (5U) 4583 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 4584 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 4585 #define TIM_SR_TIF_Pos (6U) 4586 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 4587 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 4588 #define TIM_SR_BIF_Pos (7U) 4589 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 4590 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 4591 #define TIM_SR_CC1OF_Pos (9U) 4592 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 4593 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 4594 #define TIM_SR_CC2OF_Pos (10U) 4595 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 4596 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 4597 #define TIM_SR_CC3OF_Pos (11U) 4598 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 4599 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 4600 #define TIM_SR_CC4OF_Pos (12U) 4601 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 4602 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 4603 4604 /******************* Bit definition for TIM_EGR register *******************/ 4605 #define TIM_EGR_UG_Pos (0U) 4606 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 4607 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 4608 #define TIM_EGR_CC1G_Pos (1U) 4609 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 4610 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 4611 #define TIM_EGR_CC2G_Pos (2U) 4612 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 4613 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 4614 #define TIM_EGR_CC3G_Pos (3U) 4615 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 4616 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 4617 #define TIM_EGR_CC4G_Pos (4U) 4618 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 4619 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 4620 #define TIM_EGR_COMG_Pos (5U) 4621 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 4622 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 4623 #define TIM_EGR_TG_Pos (6U) 4624 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 4625 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 4626 #define TIM_EGR_BG_Pos (7U) 4627 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 4628 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 4629 4630 /****************** Bit definition for TIM_CCMR1 register ******************/ 4631 #define TIM_CCMR1_CC1S_Pos (0U) 4632 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 4633 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 4634 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 4635 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 4636 4637 #define TIM_CCMR1_OC1FE_Pos (2U) 4638 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 4639 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 4640 #define TIM_CCMR1_OC1PE_Pos (3U) 4641 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 4642 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 4643 4644 #define TIM_CCMR1_OC1M_Pos (4U) 4645 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 4646 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 4647 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 4648 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 4649 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 4650 4651 #define TIM_CCMR1_OC1CE_Pos (7U) 4652 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 4653 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 4654 4655 #define TIM_CCMR1_CC2S_Pos (8U) 4656 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 4657 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 4658 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 4659 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 4660 4661 #define TIM_CCMR1_OC2FE_Pos (10U) 4662 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 4663 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 4664 #define TIM_CCMR1_OC2PE_Pos (11U) 4665 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 4666 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 4667 4668 #define TIM_CCMR1_OC2M_Pos (12U) 4669 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 4670 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 4671 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 4672 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 4673 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 4674 4675 #define TIM_CCMR1_OC2CE_Pos (15U) 4676 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 4677 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 4678 4679 /*---------------------------------------------------------------------------*/ 4680 4681 #define TIM_CCMR1_IC1PSC_Pos (2U) 4682 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 4683 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 4684 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 4685 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 4686 4687 #define TIM_CCMR1_IC1F_Pos (4U) 4688 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 4689 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 4690 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 4691 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 4692 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 4693 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 4694 4695 #define TIM_CCMR1_IC2PSC_Pos (10U) 4696 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 4697 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 4698 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 4699 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 4700 4701 #define TIM_CCMR1_IC2F_Pos (12U) 4702 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 4703 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 4704 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 4705 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 4706 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 4707 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 4708 4709 /****************** Bit definition for TIM_CCMR2 register ******************/ 4710 #define TIM_CCMR2_CC3S_Pos (0U) 4711 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 4712 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 4713 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 4714 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 4715 4716 #define TIM_CCMR2_OC3FE_Pos (2U) 4717 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 4718 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 4719 #define TIM_CCMR2_OC3PE_Pos (3U) 4720 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 4721 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 4722 4723 #define TIM_CCMR2_OC3M_Pos (4U) 4724 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 4725 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 4726 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 4727 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 4728 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 4729 4730 #define TIM_CCMR2_OC3CE_Pos (7U) 4731 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 4732 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 4733 4734 #define TIM_CCMR2_CC4S_Pos (8U) 4735 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 4736 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 4737 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 4738 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 4739 4740 #define TIM_CCMR2_OC4FE_Pos (10U) 4741 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 4742 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 4743 #define TIM_CCMR2_OC4PE_Pos (11U) 4744 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 4745 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 4746 4747 #define TIM_CCMR2_OC4M_Pos (12U) 4748 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 4749 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 4750 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 4751 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 4752 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 4753 4754 #define TIM_CCMR2_OC4CE_Pos (15U) 4755 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 4756 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 4757 4758 /*---------------------------------------------------------------------------*/ 4759 4760 #define TIM_CCMR2_IC3PSC_Pos (2U) 4761 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 4762 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 4763 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 4764 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 4765 4766 #define TIM_CCMR2_IC3F_Pos (4U) 4767 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 4768 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 4769 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 4770 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 4771 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 4772 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 4773 4774 #define TIM_CCMR2_IC4PSC_Pos (10U) 4775 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 4776 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 4777 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 4778 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 4779 4780 #define TIM_CCMR2_IC4F_Pos (12U) 4781 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 4782 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 4783 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 4784 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 4785 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 4786 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 4787 4788 /******************* Bit definition for TIM_CCER register ******************/ 4789 #define TIM_CCER_CC1E_Pos (0U) 4790 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 4791 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 4792 #define TIM_CCER_CC1P_Pos (1U) 4793 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 4794 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 4795 #define TIM_CCER_CC1NE_Pos (2U) 4796 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 4797 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 4798 #define TIM_CCER_CC1NP_Pos (3U) 4799 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 4800 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 4801 #define TIM_CCER_CC2E_Pos (4U) 4802 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 4803 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 4804 #define TIM_CCER_CC2P_Pos (5U) 4805 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 4806 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 4807 #define TIM_CCER_CC2NE_Pos (6U) 4808 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 4809 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 4810 #define TIM_CCER_CC2NP_Pos (7U) 4811 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 4812 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 4813 #define TIM_CCER_CC3E_Pos (8U) 4814 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 4815 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 4816 #define TIM_CCER_CC3P_Pos (9U) 4817 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 4818 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 4819 #define TIM_CCER_CC3NE_Pos (10U) 4820 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 4821 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 4822 #define TIM_CCER_CC3NP_Pos (11U) 4823 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 4824 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 4825 #define TIM_CCER_CC4E_Pos (12U) 4826 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 4827 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 4828 #define TIM_CCER_CC4P_Pos (13U) 4829 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 4830 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 4831 4832 /******************* Bit definition for TIM_CNT register *******************/ 4833 #define TIM_CNT_CNT_Pos (0U) 4834 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 4835 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 4836 4837 /******************* Bit definition for TIM_PSC register *******************/ 4838 #define TIM_PSC_PSC_Pos (0U) 4839 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 4840 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 4841 4842 /******************* Bit definition for TIM_ARR register *******************/ 4843 #define TIM_ARR_ARR_Pos (0U) 4844 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 4845 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 4846 4847 /******************* Bit definition for TIM_RCR register *******************/ 4848 #define TIM_RCR_REP_Pos (0U) 4849 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 4850 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 4851 4852 /******************* Bit definition for TIM_CCR1 register ******************/ 4853 #define TIM_CCR1_CCR1_Pos (0U) 4854 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 4855 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 4856 4857 /******************* Bit definition for TIM_CCR2 register ******************/ 4858 #define TIM_CCR2_CCR2_Pos (0U) 4859 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 4860 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 4861 4862 /******************* Bit definition for TIM_CCR3 register ******************/ 4863 #define TIM_CCR3_CCR3_Pos (0U) 4864 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 4865 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 4866 4867 /******************* Bit definition for TIM_CCR4 register ******************/ 4868 #define TIM_CCR4_CCR4_Pos (0U) 4869 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 4870 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 4871 4872 /******************* Bit definition for TIM_BDTR register ******************/ 4873 #define TIM_BDTR_DTG_Pos (0U) 4874 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 4875 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 4876 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 4877 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 4878 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 4879 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 4880 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 4881 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 4882 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 4883 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 4884 4885 #define TIM_BDTR_LOCK_Pos (8U) 4886 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 4887 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 4888 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 4889 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 4890 4891 #define TIM_BDTR_OSSI_Pos (10U) 4892 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 4893 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 4894 #define TIM_BDTR_OSSR_Pos (11U) 4895 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 4896 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 4897 #define TIM_BDTR_BKE_Pos (12U) 4898 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 4899 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 4900 #define TIM_BDTR_BKP_Pos (13U) 4901 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 4902 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 4903 #define TIM_BDTR_AOE_Pos (14U) 4904 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 4905 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 4906 #define TIM_BDTR_MOE_Pos (15U) 4907 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 4908 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 4909 4910 /******************* Bit definition for TIM_DCR register *******************/ 4911 #define TIM_DCR_DBA_Pos (0U) 4912 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 4913 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 4914 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 4915 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 4916 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 4917 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 4918 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 4919 4920 #define TIM_DCR_DBL_Pos (8U) 4921 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 4922 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 4923 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 4924 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 4925 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 4926 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 4927 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 4928 4929 /******************* Bit definition for TIM_DMAR register ******************/ 4930 #define TIM_DMAR_DMAB_Pos (0U) 4931 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 4932 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 4933 4934 /******************************************************************************/ 4935 /* */ 4936 /* Real-Time Clock */ 4937 /* */ 4938 /******************************************************************************/ 4939 4940 /******************* Bit definition for RTC_CRH register ********************/ 4941 #define RTC_CRH_SECIE_Pos (0U) 4942 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ 4943 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ 4944 #define RTC_CRH_ALRIE_Pos (1U) 4945 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ 4946 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ 4947 #define RTC_CRH_OWIE_Pos (2U) 4948 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ 4949 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ 4950 4951 /******************* Bit definition for RTC_CRL register ********************/ 4952 #define RTC_CRL_SECF_Pos (0U) 4953 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ 4954 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ 4955 #define RTC_CRL_ALRF_Pos (1U) 4956 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ 4957 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ 4958 #define RTC_CRL_OWF_Pos (2U) 4959 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ 4960 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ 4961 #define RTC_CRL_RSF_Pos (3U) 4962 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ 4963 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ 4964 #define RTC_CRL_CNF_Pos (4U) 4965 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ 4966 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ 4967 #define RTC_CRL_RTOFF_Pos (5U) 4968 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ 4969 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ 4970 4971 /******************* Bit definition for RTC_PRLH register *******************/ 4972 #define RTC_PRLH_PRL_Pos (0U) 4973 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ 4974 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ 4975 4976 /******************* Bit definition for RTC_PRLL register *******************/ 4977 #define RTC_PRLL_PRL_Pos (0U) 4978 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ 4979 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ 4980 4981 /******************* Bit definition for RTC_DIVH register *******************/ 4982 #define RTC_DIVH_RTC_DIV_Pos (0U) 4983 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ 4984 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ 4985 4986 /******************* Bit definition for RTC_DIVL register *******************/ 4987 #define RTC_DIVL_RTC_DIV_Pos (0U) 4988 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ 4989 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ 4990 4991 /******************* Bit definition for RTC_CNTH register *******************/ 4992 #define RTC_CNTH_RTC_CNT_Pos (0U) 4993 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4994 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ 4995 4996 /******************* Bit definition for RTC_CNTL register *******************/ 4997 #define RTC_CNTL_RTC_CNT_Pos (0U) 4998 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4999 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ 5000 5001 /******************* Bit definition for RTC_ALRH register *******************/ 5002 #define RTC_ALRH_RTC_ALR_Pos (0U) 5003 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ 5004 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ 5005 5006 /******************* Bit definition for RTC_ALRL register *******************/ 5007 #define RTC_ALRL_RTC_ALR_Pos (0U) 5008 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ 5009 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ 5010 5011 /******************************************************************************/ 5012 /* */ 5013 /* Independent WATCHDOG (IWDG) */ 5014 /* */ 5015 /******************************************************************************/ 5016 5017 /******************* Bit definition for IWDG_KR register ********************/ 5018 #define IWDG_KR_KEY_Pos (0U) 5019 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 5020 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 5021 5022 /******************* Bit definition for IWDG_PR register ********************/ 5023 #define IWDG_PR_PR_Pos (0U) 5024 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 5025 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 5026 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 5027 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 5028 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 5029 5030 /******************* Bit definition for IWDG_RLR register *******************/ 5031 #define IWDG_RLR_RL_Pos (0U) 5032 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 5033 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 5034 5035 /******************* Bit definition for IWDG_SR register ********************/ 5036 #define IWDG_SR_PVU_Pos (0U) 5037 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 5038 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 5039 #define IWDG_SR_RVU_Pos (1U) 5040 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 5041 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 5042 5043 /******************************************************************************/ 5044 /* */ 5045 /* Window WATCHDOG (WWDG) */ 5046 /* */ 5047 /******************************************************************************/ 5048 5049 /******************* Bit definition for WWDG_CR register ********************/ 5050 #define WWDG_CR_T_Pos (0U) 5051 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 5052 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 5053 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 5054 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 5055 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 5056 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 5057 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 5058 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 5059 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 5060 5061 /* Legacy defines */ 5062 #define WWDG_CR_T0 WWDG_CR_T_0 5063 #define WWDG_CR_T1 WWDG_CR_T_1 5064 #define WWDG_CR_T2 WWDG_CR_T_2 5065 #define WWDG_CR_T3 WWDG_CR_T_3 5066 #define WWDG_CR_T4 WWDG_CR_T_4 5067 #define WWDG_CR_T5 WWDG_CR_T_5 5068 #define WWDG_CR_T6 WWDG_CR_T_6 5069 5070 #define WWDG_CR_WDGA_Pos (7U) 5071 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 5072 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 5073 5074 /******************* Bit definition for WWDG_CFR register *******************/ 5075 #define WWDG_CFR_W_Pos (0U) 5076 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 5077 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 5078 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 5079 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 5080 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 5081 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 5082 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 5083 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 5084 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 5085 5086 /* Legacy defines */ 5087 #define WWDG_CFR_W0 WWDG_CFR_W_0 5088 #define WWDG_CFR_W1 WWDG_CFR_W_1 5089 #define WWDG_CFR_W2 WWDG_CFR_W_2 5090 #define WWDG_CFR_W3 WWDG_CFR_W_3 5091 #define WWDG_CFR_W4 WWDG_CFR_W_4 5092 #define WWDG_CFR_W5 WWDG_CFR_W_5 5093 #define WWDG_CFR_W6 WWDG_CFR_W_6 5094 5095 #define WWDG_CFR_WDGTB_Pos (7U) 5096 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 5097 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 5098 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 5099 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 5100 5101 /* Legacy defines */ 5102 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 5103 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 5104 5105 #define WWDG_CFR_EWI_Pos (9U) 5106 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 5107 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 5108 5109 /******************* Bit definition for WWDG_SR register ********************/ 5110 #define WWDG_SR_EWIF_Pos (0U) 5111 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 5112 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 5113 5114 /******************************************************************************/ 5115 /* */ 5116 /* Flexible Static Memory Controller */ 5117 /* */ 5118 /******************************************************************************/ 5119 5120 /****************** Bit definition for FSMC_BCRx (x=1..4) register **********/ 5121 #define FSMC_BCRx_MBKEN_Pos (0U) 5122 #define FSMC_BCRx_MBKEN_Msk (0x1UL << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */ 5123 #define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */ 5124 #define FSMC_BCRx_MUXEN_Pos (1U) 5125 #define FSMC_BCRx_MUXEN_Msk (0x1UL << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */ 5126 #define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */ 5127 5128 #define FSMC_BCRx_MTYP_Pos (2U) 5129 #define FSMC_BCRx_MTYP_Msk (0x3UL << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */ 5130 #define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */ 5131 #define FSMC_BCRx_MTYP_0 (0x1UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */ 5132 #define FSMC_BCRx_MTYP_1 (0x2UL << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */ 5133 5134 #define FSMC_BCRx_MWID_Pos (4U) 5135 #define FSMC_BCRx_MWID_Msk (0x3UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */ 5136 #define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */ 5137 #define FSMC_BCRx_MWID_0 (0x1UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */ 5138 #define FSMC_BCRx_MWID_1 (0x2UL << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */ 5139 5140 #define FSMC_BCRx_FACCEN_Pos (6U) 5141 #define FSMC_BCRx_FACCEN_Msk (0x1UL << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */ 5142 #define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */ 5143 #define FSMC_BCRx_BURSTEN_Pos (8U) 5144 #define FSMC_BCRx_BURSTEN_Msk (0x1UL << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */ 5145 #define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */ 5146 #define FSMC_BCRx_WAITPOL_Pos (9U) 5147 #define FSMC_BCRx_WAITPOL_Msk (0x1UL << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */ 5148 #define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */ 5149 #define FSMC_BCRx_WRAPMOD_Pos (10U) 5150 #define FSMC_BCRx_WRAPMOD_Msk (0x1UL << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */ 5151 #define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */ 5152 #define FSMC_BCRx_WAITCFG_Pos (11U) 5153 #define FSMC_BCRx_WAITCFG_Msk (0x1UL << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */ 5154 #define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */ 5155 #define FSMC_BCRx_WREN_Pos (12U) 5156 #define FSMC_BCRx_WREN_Msk (0x1UL << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */ 5157 #define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */ 5158 #define FSMC_BCRx_WAITEN_Pos (13U) 5159 #define FSMC_BCRx_WAITEN_Msk (0x1UL << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */ 5160 #define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */ 5161 #define FSMC_BCRx_EXTMOD_Pos (14U) 5162 #define FSMC_BCRx_EXTMOD_Msk (0x1UL << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ 5163 #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ 5164 #define FSMC_BCRx_ASYNCWAIT_Pos (15U) 5165 #define FSMC_BCRx_ASYNCWAIT_Msk (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ 5166 #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ 5167 #define FSMC_BCRx_CBURSTRW_Pos (19U) 5168 #define FSMC_BCRx_CBURSTRW_Msk (0x1UL << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ 5169 #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ 5170 5171 /****************** Bit definition for FSMC_BTRx (x=1..4) register ******/ 5172 #define FSMC_BTRx_ADDSET_Pos (0U) 5173 #define FSMC_BTRx_ADDSET_Msk (0xFUL << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */ 5174 #define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 5175 #define FSMC_BTRx_ADDSET_0 (0x1UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */ 5176 #define FSMC_BTRx_ADDSET_1 (0x2UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */ 5177 #define FSMC_BTRx_ADDSET_2 (0x4UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */ 5178 #define FSMC_BTRx_ADDSET_3 (0x8UL << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */ 5179 5180 #define FSMC_BTRx_ADDHLD_Pos (4U) 5181 #define FSMC_BTRx_ADDHLD_Msk (0xFUL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 5182 #define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 5183 #define FSMC_BTRx_ADDHLD_0 (0x1UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */ 5184 #define FSMC_BTRx_ADDHLD_1 (0x2UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */ 5185 #define FSMC_BTRx_ADDHLD_2 (0x4UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */ 5186 #define FSMC_BTRx_ADDHLD_3 (0x8UL << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */ 5187 5188 #define FSMC_BTRx_DATAST_Pos (8U) 5189 #define FSMC_BTRx_DATAST_Msk (0xFFUL << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */ 5190 #define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */ 5191 #define FSMC_BTRx_DATAST_0 (0x01UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */ 5192 #define FSMC_BTRx_DATAST_1 (0x02UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */ 5193 #define FSMC_BTRx_DATAST_2 (0x04UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */ 5194 #define FSMC_BTRx_DATAST_3 (0x08UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */ 5195 #define FSMC_BTRx_DATAST_4 (0x10UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */ 5196 #define FSMC_BTRx_DATAST_5 (0x20UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */ 5197 #define FSMC_BTRx_DATAST_6 (0x40UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */ 5198 #define FSMC_BTRx_DATAST_7 (0x80UL << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */ 5199 5200 #define FSMC_BTRx_BUSTURN_Pos (16U) 5201 #define FSMC_BTRx_BUSTURN_Msk (0xFUL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */ 5202 #define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ 5203 #define FSMC_BTRx_BUSTURN_0 (0x1UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */ 5204 #define FSMC_BTRx_BUSTURN_1 (0x2UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */ 5205 #define FSMC_BTRx_BUSTURN_2 (0x4UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */ 5206 #define FSMC_BTRx_BUSTURN_3 (0x8UL << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */ 5207 5208 #define FSMC_BTRx_CLKDIV_Pos (20U) 5209 #define FSMC_BTRx_CLKDIV_Msk (0xFUL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */ 5210 #define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */ 5211 #define FSMC_BTRx_CLKDIV_0 (0x1UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */ 5212 #define FSMC_BTRx_CLKDIV_1 (0x2UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */ 5213 #define FSMC_BTRx_CLKDIV_2 (0x4UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */ 5214 #define FSMC_BTRx_CLKDIV_3 (0x8UL << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */ 5215 5216 #define FSMC_BTRx_DATLAT_Pos (24U) 5217 #define FSMC_BTRx_DATLAT_Msk (0xFUL << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */ 5218 #define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */ 5219 #define FSMC_BTRx_DATLAT_0 (0x1UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */ 5220 #define FSMC_BTRx_DATLAT_1 (0x2UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */ 5221 #define FSMC_BTRx_DATLAT_2 (0x4UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */ 5222 #define FSMC_BTRx_DATLAT_3 (0x8UL << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */ 5223 5224 #define FSMC_BTRx_ACCMOD_Pos (28U) 5225 #define FSMC_BTRx_ACCMOD_Msk (0x3UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */ 5226 #define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 5227 #define FSMC_BTRx_ACCMOD_0 (0x1UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */ 5228 #define FSMC_BTRx_ACCMOD_1 (0x2UL << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */ 5229 5230 /****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/ 5231 #define FSMC_BWTRx_ADDSET_Pos (0U) 5232 #define FSMC_BWTRx_ADDSET_Msk (0xFUL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */ 5233 #define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ 5234 #define FSMC_BWTRx_ADDSET_0 (0x1UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */ 5235 #define FSMC_BWTRx_ADDSET_1 (0x2UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */ 5236 #define FSMC_BWTRx_ADDSET_2 (0x4UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */ 5237 #define FSMC_BWTRx_ADDSET_3 (0x8UL << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */ 5238 5239 #define FSMC_BWTRx_ADDHLD_Pos (4U) 5240 #define FSMC_BWTRx_ADDHLD_Msk (0xFUL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */ 5241 #define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ 5242 #define FSMC_BWTRx_ADDHLD_0 (0x1UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */ 5243 #define FSMC_BWTRx_ADDHLD_1 (0x2UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */ 5244 #define FSMC_BWTRx_ADDHLD_2 (0x4UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */ 5245 #define FSMC_BWTRx_ADDHLD_3 (0x8UL << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */ 5246 5247 #define FSMC_BWTRx_DATAST_Pos (8U) 5248 #define FSMC_BWTRx_DATAST_Msk (0xFFUL << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */ 5249 #define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */ 5250 #define FSMC_BWTRx_DATAST_0 (0x01UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */ 5251 #define FSMC_BWTRx_DATAST_1 (0x02UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */ 5252 #define FSMC_BWTRx_DATAST_2 (0x04UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */ 5253 #define FSMC_BWTRx_DATAST_3 (0x08UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */ 5254 #define FSMC_BWTRx_DATAST_4 (0x10UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */ 5255 #define FSMC_BWTRx_DATAST_5 (0x20UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */ 5256 #define FSMC_BWTRx_DATAST_6 (0x40UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */ 5257 #define FSMC_BWTRx_DATAST_7 (0x80UL << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */ 5258 5259 #define FSMC_BWTRx_CLKDIV_Pos (20U) 5260 #define FSMC_BWTRx_CLKDIV_Msk (0xFUL << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00F00000 */ 5261 #define FSMC_BWTRx_CLKDIV FSMC_BWTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */ 5262 #define FSMC_BWTRx_CLKDIV_0 (0x1UL << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00100000 */ 5263 #define FSMC_BWTRx_CLKDIV_1 (0x2UL << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00200000 */ 5264 #define FSMC_BWTRx_CLKDIV_2 (0x4UL << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00400000 */ 5265 #define FSMC_BWTRx_CLKDIV_3 (0x8UL << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00800000 */ 5266 5267 #define FSMC_BWTRx_DATLAT_Pos (24U) 5268 #define FSMC_BWTRx_DATLAT_Msk (0xFUL << FSMC_BWTRx_DATLAT_Pos) /*!< 0x0F000000 */ 5269 #define FSMC_BWTRx_DATLAT FSMC_BWTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */ 5270 #define FSMC_BWTRx_DATLAT_0 (0x1UL << FSMC_BWTRx_DATLAT_Pos) /*!< 0x01000000 */ 5271 #define FSMC_BWTRx_DATLAT_1 (0x2UL << FSMC_BWTRx_DATLAT_Pos) /*!< 0x02000000 */ 5272 #define FSMC_BWTRx_DATLAT_2 (0x4UL << FSMC_BWTRx_DATLAT_Pos) /*!< 0x04000000 */ 5273 #define FSMC_BWTRx_DATLAT_3 (0x8UL << FSMC_BWTRx_DATLAT_Pos) /*!< 0x08000000 */ 5274 5275 #define FSMC_BWTRx_ACCMOD_Pos (28U) 5276 #define FSMC_BWTRx_ACCMOD_Msk (0x3UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */ 5277 #define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ 5278 #define FSMC_BWTRx_ACCMOD_0 (0x1UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */ 5279 #define FSMC_BWTRx_ACCMOD_1 (0x2UL << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */ 5280 5281 5282 5283 /******************************************************************************/ 5284 /* */ 5285 /* Serial Peripheral Interface */ 5286 /* */ 5287 /******************************************************************************/ 5288 5289 /******************* Bit definition for SPI_CR1 register ********************/ 5290 #define SPI_CR1_CPHA_Pos (0U) 5291 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 5292 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 5293 #define SPI_CR1_CPOL_Pos (1U) 5294 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 5295 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 5296 #define SPI_CR1_MSTR_Pos (2U) 5297 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 5298 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 5299 5300 #define SPI_CR1_BR_Pos (3U) 5301 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 5302 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 5303 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 5304 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 5305 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 5306 5307 #define SPI_CR1_SPE_Pos (6U) 5308 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 5309 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 5310 #define SPI_CR1_LSBFIRST_Pos (7U) 5311 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 5312 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 5313 #define SPI_CR1_SSI_Pos (8U) 5314 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 5315 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 5316 #define SPI_CR1_SSM_Pos (9U) 5317 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 5318 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 5319 #define SPI_CR1_RXONLY_Pos (10U) 5320 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 5321 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 5322 #define SPI_CR1_DFF_Pos (11U) 5323 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 5324 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 5325 #define SPI_CR1_CRCNEXT_Pos (12U) 5326 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 5327 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 5328 #define SPI_CR1_CRCEN_Pos (13U) 5329 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 5330 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 5331 #define SPI_CR1_BIDIOE_Pos (14U) 5332 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 5333 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 5334 #define SPI_CR1_BIDIMODE_Pos (15U) 5335 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 5336 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 5337 5338 /******************* Bit definition for SPI_CR2 register ********************/ 5339 #define SPI_CR2_RXDMAEN_Pos (0U) 5340 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 5341 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 5342 #define SPI_CR2_TXDMAEN_Pos (1U) 5343 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 5344 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 5345 #define SPI_CR2_SSOE_Pos (2U) 5346 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 5347 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 5348 #define SPI_CR2_ERRIE_Pos (5U) 5349 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 5350 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 5351 #define SPI_CR2_RXNEIE_Pos (6U) 5352 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 5353 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 5354 #define SPI_CR2_TXEIE_Pos (7U) 5355 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 5356 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 5357 5358 /******************** Bit definition for SPI_SR register ********************/ 5359 #define SPI_SR_RXNE_Pos (0U) 5360 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 5361 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 5362 #define SPI_SR_TXE_Pos (1U) 5363 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 5364 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 5365 #define SPI_SR_CHSIDE_Pos (2U) 5366 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 5367 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 5368 #define SPI_SR_UDR_Pos (3U) 5369 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 5370 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5371 #define SPI_SR_CRCERR_Pos (4U) 5372 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5373 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5374 #define SPI_SR_MODF_Pos (5U) 5375 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5376 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5377 #define SPI_SR_OVR_Pos (6U) 5378 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5379 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5380 #define SPI_SR_BSY_Pos (7U) 5381 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5382 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5383 5384 /******************** Bit definition for SPI_DR register ********************/ 5385 #define SPI_DR_DR_Pos (0U) 5386 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5387 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 5388 5389 /******************* Bit definition for SPI_CRCPR register ******************/ 5390 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5391 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5392 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 5393 5394 /****************** Bit definition for SPI_RXCRCR register ******************/ 5395 #define SPI_RXCRCR_RXCRC_Pos (0U) 5396 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5397 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 5398 5399 /****************** Bit definition for SPI_TXCRCR register ******************/ 5400 #define SPI_TXCRCR_TXCRC_Pos (0U) 5401 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5402 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 5403 5404 5405 /******************************************************************************/ 5406 /* */ 5407 /* Inter-integrated Circuit Interface */ 5408 /* */ 5409 /******************************************************************************/ 5410 5411 /******************* Bit definition for I2C_CR1 register ********************/ 5412 #define I2C_CR1_PE_Pos (0U) 5413 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 5414 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 5415 #define I2C_CR1_SMBUS_Pos (1U) 5416 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 5417 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 5418 #define I2C_CR1_SMBTYPE_Pos (3U) 5419 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 5420 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 5421 #define I2C_CR1_ENARP_Pos (4U) 5422 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 5423 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 5424 #define I2C_CR1_ENPEC_Pos (5U) 5425 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 5426 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 5427 #define I2C_CR1_ENGC_Pos (6U) 5428 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 5429 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 5430 #define I2C_CR1_NOSTRETCH_Pos (7U) 5431 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 5432 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 5433 #define I2C_CR1_START_Pos (8U) 5434 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 5435 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 5436 #define I2C_CR1_STOP_Pos (9U) 5437 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 5438 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 5439 #define I2C_CR1_ACK_Pos (10U) 5440 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 5441 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 5442 #define I2C_CR1_POS_Pos (11U) 5443 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 5444 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 5445 #define I2C_CR1_PEC_Pos (12U) 5446 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 5447 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 5448 #define I2C_CR1_ALERT_Pos (13U) 5449 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 5450 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 5451 #define I2C_CR1_SWRST_Pos (15U) 5452 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 5453 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 5454 5455 /******************* Bit definition for I2C_CR2 register ********************/ 5456 #define I2C_CR2_FREQ_Pos (0U) 5457 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 5458 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 5459 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 5460 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 5461 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 5462 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 5463 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 5464 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 5465 5466 #define I2C_CR2_ITERREN_Pos (8U) 5467 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 5468 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 5469 #define I2C_CR2_ITEVTEN_Pos (9U) 5470 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 5471 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 5472 #define I2C_CR2_ITBUFEN_Pos (10U) 5473 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 5474 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 5475 #define I2C_CR2_DMAEN_Pos (11U) 5476 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 5477 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 5478 #define I2C_CR2_LAST_Pos (12U) 5479 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 5480 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 5481 5482 /******************* Bit definition for I2C_OAR1 register *******************/ 5483 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ 5484 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ 5485 5486 #define I2C_OAR1_ADD0_Pos (0U) 5487 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 5488 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 5489 #define I2C_OAR1_ADD1_Pos (1U) 5490 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 5491 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 5492 #define I2C_OAR1_ADD2_Pos (2U) 5493 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 5494 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 5495 #define I2C_OAR1_ADD3_Pos (3U) 5496 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 5497 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 5498 #define I2C_OAR1_ADD4_Pos (4U) 5499 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 5500 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 5501 #define I2C_OAR1_ADD5_Pos (5U) 5502 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 5503 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 5504 #define I2C_OAR1_ADD6_Pos (6U) 5505 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 5506 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 5507 #define I2C_OAR1_ADD7_Pos (7U) 5508 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 5509 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 5510 #define I2C_OAR1_ADD8_Pos (8U) 5511 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 5512 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 5513 #define I2C_OAR1_ADD9_Pos (9U) 5514 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 5515 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 5516 5517 #define I2C_OAR1_ADDMODE_Pos (15U) 5518 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 5519 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 5520 5521 /******************* Bit definition for I2C_OAR2 register *******************/ 5522 #define I2C_OAR2_ENDUAL_Pos (0U) 5523 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 5524 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 5525 #define I2C_OAR2_ADD2_Pos (1U) 5526 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 5527 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 5528 5529 /******************** Bit definition for I2C_DR register ********************/ 5530 #define I2C_DR_DR_Pos (0U) 5531 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 5532 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 5533 5534 /******************* Bit definition for I2C_SR1 register ********************/ 5535 #define I2C_SR1_SB_Pos (0U) 5536 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 5537 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 5538 #define I2C_SR1_ADDR_Pos (1U) 5539 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 5540 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 5541 #define I2C_SR1_BTF_Pos (2U) 5542 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 5543 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 5544 #define I2C_SR1_ADD10_Pos (3U) 5545 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 5546 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 5547 #define I2C_SR1_STOPF_Pos (4U) 5548 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 5549 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 5550 #define I2C_SR1_RXNE_Pos (6U) 5551 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 5552 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 5553 #define I2C_SR1_TXE_Pos (7U) 5554 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 5555 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 5556 #define I2C_SR1_BERR_Pos (8U) 5557 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 5558 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 5559 #define I2C_SR1_ARLO_Pos (9U) 5560 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 5561 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 5562 #define I2C_SR1_AF_Pos (10U) 5563 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 5564 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 5565 #define I2C_SR1_OVR_Pos (11U) 5566 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 5567 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 5568 #define I2C_SR1_PECERR_Pos (12U) 5569 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 5570 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 5571 #define I2C_SR1_TIMEOUT_Pos (14U) 5572 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 5573 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 5574 #define I2C_SR1_SMBALERT_Pos (15U) 5575 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 5576 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 5577 5578 /******************* Bit definition for I2C_SR2 register ********************/ 5579 #define I2C_SR2_MSL_Pos (0U) 5580 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 5581 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 5582 #define I2C_SR2_BUSY_Pos (1U) 5583 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 5584 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 5585 #define I2C_SR2_TRA_Pos (2U) 5586 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 5587 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 5588 #define I2C_SR2_GENCALL_Pos (4U) 5589 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 5590 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 5591 #define I2C_SR2_SMBDEFAULT_Pos (5U) 5592 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 5593 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 5594 #define I2C_SR2_SMBHOST_Pos (6U) 5595 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 5596 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 5597 #define I2C_SR2_DUALF_Pos (7U) 5598 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 5599 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 5600 #define I2C_SR2_PEC_Pos (8U) 5601 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 5602 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 5603 5604 /******************* Bit definition for I2C_CCR register ********************/ 5605 #define I2C_CCR_CCR_Pos (0U) 5606 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 5607 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 5608 #define I2C_CCR_DUTY_Pos (14U) 5609 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 5610 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 5611 #define I2C_CCR_FS_Pos (15U) 5612 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 5613 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 5614 5615 /****************** Bit definition for I2C_TRISE register *******************/ 5616 #define I2C_TRISE_TRISE_Pos (0U) 5617 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 5618 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 5619 5620 /******************************************************************************/ 5621 /* */ 5622 /* Universal Synchronous Asynchronous Receiver Transmitter */ 5623 /* */ 5624 /******************************************************************************/ 5625 5626 /******************* Bit definition for USART_SR register *******************/ 5627 #define USART_SR_PE_Pos (0U) 5628 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 5629 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 5630 #define USART_SR_FE_Pos (1U) 5631 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 5632 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 5633 #define USART_SR_NE_Pos (2U) 5634 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 5635 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 5636 #define USART_SR_ORE_Pos (3U) 5637 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 5638 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 5639 #define USART_SR_IDLE_Pos (4U) 5640 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 5641 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 5642 #define USART_SR_RXNE_Pos (5U) 5643 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 5644 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 5645 #define USART_SR_TC_Pos (6U) 5646 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 5647 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 5648 #define USART_SR_TXE_Pos (7U) 5649 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 5650 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 5651 #define USART_SR_LBD_Pos (8U) 5652 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 5653 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 5654 #define USART_SR_CTS_Pos (9U) 5655 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 5656 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 5657 5658 /******************* Bit definition for USART_DR register *******************/ 5659 #define USART_DR_DR_Pos (0U) 5660 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 5661 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 5662 5663 /****************** Bit definition for USART_BRR register *******************/ 5664 #define USART_BRR_DIV_Fraction_Pos (0U) 5665 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 5666 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ 5667 #define USART_BRR_DIV_Mantissa_Pos (4U) 5668 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 5669 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ 5670 5671 /****************** Bit definition for USART_CR1 register *******************/ 5672 #define USART_CR1_SBK_Pos (0U) 5673 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 5674 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 5675 #define USART_CR1_RWU_Pos (1U) 5676 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 5677 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 5678 #define USART_CR1_RE_Pos (2U) 5679 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5680 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5681 #define USART_CR1_TE_Pos (3U) 5682 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5683 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5684 #define USART_CR1_IDLEIE_Pos (4U) 5685 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5686 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5687 #define USART_CR1_RXNEIE_Pos (5U) 5688 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5689 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5690 #define USART_CR1_TCIE_Pos (6U) 5691 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5692 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5693 #define USART_CR1_TXEIE_Pos (7U) 5694 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5695 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 5696 #define USART_CR1_PEIE_Pos (8U) 5697 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5698 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5699 #define USART_CR1_PS_Pos (9U) 5700 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5701 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5702 #define USART_CR1_PCE_Pos (10U) 5703 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5704 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5705 #define USART_CR1_WAKE_Pos (11U) 5706 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5707 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 5708 #define USART_CR1_M_Pos (12U) 5709 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 5710 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 5711 #define USART_CR1_UE_Pos (13U) 5712 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 5713 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5714 #define USART_CR1_OVER8_Pos (15U) 5715 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5716 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< USART Oversmapling 8-bits */ 5717 5718 /****************** Bit definition for USART_CR2 register *******************/ 5719 #define USART_CR2_ADD_Pos (0U) 5720 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 5721 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 5722 #define USART_CR2_LBDL_Pos (5U) 5723 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 5724 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 5725 #define USART_CR2_LBDIE_Pos (6U) 5726 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 5727 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 5728 #define USART_CR2_LBCL_Pos (8U) 5729 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5730 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5731 #define USART_CR2_CPHA_Pos (9U) 5732 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5733 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5734 #define USART_CR2_CPOL_Pos (10U) 5735 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5736 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5737 #define USART_CR2_CLKEN_Pos (11U) 5738 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5739 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5740 5741 #define USART_CR2_STOP_Pos (12U) 5742 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5743 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5744 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5745 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5746 5747 #define USART_CR2_LINEN_Pos (14U) 5748 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 5749 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 5750 5751 /****************** Bit definition for USART_CR3 register *******************/ 5752 #define USART_CR3_EIE_Pos (0U) 5753 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 5754 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 5755 #define USART_CR3_IREN_Pos (1U) 5756 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 5757 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 5758 #define USART_CR3_IRLP_Pos (2U) 5759 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 5760 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 5761 #define USART_CR3_HDSEL_Pos (3U) 5762 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 5763 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 5764 #define USART_CR3_NACK_Pos (4U) 5765 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 5766 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 5767 #define USART_CR3_SCEN_Pos (5U) 5768 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 5769 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 5770 #define USART_CR3_DMAR_Pos (6U) 5771 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 5772 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 5773 #define USART_CR3_DMAT_Pos (7U) 5774 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 5775 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 5776 #define USART_CR3_RTSE_Pos (8U) 5777 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 5778 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 5779 #define USART_CR3_CTSE_Pos (9U) 5780 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 5781 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 5782 #define USART_CR3_CTSIE_Pos (10U) 5783 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 5784 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 5785 #define USART_CR3_ONEBIT_Pos (11U) 5786 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 5787 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One Bit method */ 5788 5789 /****************** Bit definition for USART_GTPR register ******************/ 5790 #define USART_GTPR_PSC_Pos (0U) 5791 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 5792 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 5793 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 5794 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 5795 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 5796 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 5797 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 5798 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 5799 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 5800 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 5801 5802 #define USART_GTPR_GT_Pos (8U) 5803 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 5804 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 5805 5806 /******************************************************************************/ 5807 /* */ 5808 /* Debug MCU */ 5809 /* */ 5810 /******************************************************************************/ 5811 5812 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 5813 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 5814 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 5815 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 5816 5817 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 5818 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 5819 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 5820 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 5821 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 5822 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 5823 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 5824 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 5825 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 5826 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 5827 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 5828 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 5829 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 5830 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 5831 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 5832 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 5833 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 5834 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 5835 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 5836 5837 /****************** Bit definition for DBGMCU_CR register *******************/ 5838 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 5839 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 5840 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 5841 #define DBGMCU_CR_DBG_STOP_Pos (1U) 5842 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 5843 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 5844 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 5845 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 5846 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 5847 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 5848 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 5849 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 5850 5851 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 5852 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 5853 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 5854 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 5855 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 5856 5857 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) 5858 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ 5859 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 5860 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) 5861 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ 5862 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 5863 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) 5864 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ 5865 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 5866 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) 5867 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ 5868 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 5869 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) 5870 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ 5871 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 5872 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) 5873 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ 5874 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 5875 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) 5876 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ 5877 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 5878 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) 5879 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ 5880 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 5881 #define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U) 5882 #define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */ 5883 #define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ 5884 #define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U) 5885 #define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */ 5886 #define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 5887 #define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U) 5888 #define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */ 5889 #define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 5890 #define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U) 5891 #define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM15_STOP_Pos) /*!< 0x00400000 */ 5892 #define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /*!< Debug TIM15 stopped when Core is halted */ 5893 #define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U) 5894 #define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM16_STOP_Pos) /*!< 0x00800000 */ 5895 #define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /*!< Debug TIM16 stopped when Core is halted */ 5896 #define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U) 5897 #define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM17_STOP_Pos) /*!< 0x01000000 */ 5898 #define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /*!< Debug TIM17 stopped when Core is halted */ 5899 #define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U) 5900 #define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */ 5901 #define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /*!< Debug TIM12 stopped when Core is halted */ 5902 #define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U) 5903 #define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */ 5904 #define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /*!< Debug TIM13 stopped when Core is halted */ 5905 #define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U) 5906 #define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */ 5907 #define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /*!< Debug TIM14 stopped when Core is halted */ 5908 5909 /******************************************************************************/ 5910 /* */ 5911 /* FLASH and Option Bytes Registers */ 5912 /* */ 5913 /******************************************************************************/ 5914 /******************* Bit definition for FLASH_ACR register ******************/ 5915 #define FLASH_ACR_HLFCYA_Pos (3U) 5916 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 5917 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 5918 5919 /****************** Bit definition for FLASH_KEYR register ******************/ 5920 #define FLASH_KEYR_FKEYR_Pos (0U) 5921 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 5922 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 5923 5924 #define RDP_KEY_Pos (0U) 5925 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ 5926 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 5927 #define FLASH_KEY1_Pos (0U) 5928 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 5929 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 5930 #define FLASH_KEY2_Pos (0U) 5931 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 5932 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 5933 5934 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 5935 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 5936 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 5937 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 5938 5939 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 5940 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 5941 5942 /****************** Bit definition for FLASH_SR register ********************/ 5943 #define FLASH_SR_BSY_Pos (0U) 5944 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 5945 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 5946 #define FLASH_SR_PGERR_Pos (2U) 5947 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 5948 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 5949 #define FLASH_SR_WRPRTERR_Pos (4U) 5950 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 5951 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 5952 #define FLASH_SR_EOP_Pos (5U) 5953 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 5954 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 5955 5956 /******************* Bit definition for FLASH_CR register *******************/ 5957 #define FLASH_CR_PG_Pos (0U) 5958 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 5959 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 5960 #define FLASH_CR_PER_Pos (1U) 5961 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 5962 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 5963 #define FLASH_CR_MER_Pos (2U) 5964 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 5965 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 5966 #define FLASH_CR_OPTPG_Pos (4U) 5967 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 5968 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 5969 #define FLASH_CR_OPTER_Pos (5U) 5970 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 5971 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 5972 #define FLASH_CR_STRT_Pos (6U) 5973 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 5974 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 5975 #define FLASH_CR_LOCK_Pos (7U) 5976 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 5977 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 5978 #define FLASH_CR_OPTWRE_Pos (9U) 5979 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 5980 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 5981 #define FLASH_CR_ERRIE_Pos (10U) 5982 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 5983 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 5984 #define FLASH_CR_EOPIE_Pos (12U) 5985 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 5986 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 5987 5988 /******************* Bit definition for FLASH_AR register *******************/ 5989 #define FLASH_AR_FAR_Pos (0U) 5990 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 5991 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 5992 5993 /****************** Bit definition for FLASH_OBR register *******************/ 5994 #define FLASH_OBR_OPTERR_Pos (0U) 5995 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 5996 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 5997 #define FLASH_OBR_RDPRT_Pos (1U) 5998 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 5999 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 6000 6001 #define FLASH_OBR_IWDG_SW_Pos (2U) 6002 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ 6003 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 6004 #define FLASH_OBR_nRST_STOP_Pos (3U) 6005 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ 6006 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 6007 #define FLASH_OBR_nRST_STDBY_Pos (4U) 6008 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ 6009 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 6010 #define FLASH_OBR_USER_Pos (2U) 6011 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ 6012 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 6013 #define FLASH_OBR_DATA0_Pos (10U) 6014 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ 6015 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 6016 #define FLASH_OBR_DATA1_Pos (18U) 6017 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ 6018 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 6019 6020 /****************** Bit definition for FLASH_WRPR register ******************/ 6021 #define FLASH_WRPR_WRP_Pos (0U) 6022 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 6023 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 6024 6025 /*----------------------------------------------------------------------------*/ 6026 6027 /****************** Bit definition for FLASH_RDP register *******************/ 6028 #define FLASH_RDP_RDP_Pos (0U) 6029 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ 6030 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ 6031 #define FLASH_RDP_nRDP_Pos (8U) 6032 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 6033 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 6034 6035 /****************** Bit definition for FLASH_USER register ******************/ 6036 #define FLASH_USER_USER_Pos (16U) 6037 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ 6038 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ 6039 #define FLASH_USER_nUSER_Pos (24U) 6040 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ 6041 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ 6042 6043 /****************** Bit definition for FLASH_Data0 register *****************/ 6044 #define FLASH_DATA0_DATA0_Pos (0U) 6045 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ 6046 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ 6047 #define FLASH_DATA0_nDATA0_Pos (8U) 6048 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ 6049 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ 6050 6051 /****************** Bit definition for FLASH_Data1 register *****************/ 6052 #define FLASH_DATA1_DATA1_Pos (16U) 6053 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ 6054 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ 6055 #define FLASH_DATA1_nDATA1_Pos (24U) 6056 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ 6057 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ 6058 6059 /****************** Bit definition for FLASH_WRP0 register ******************/ 6060 #define FLASH_WRP0_WRP0_Pos (0U) 6061 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ 6062 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 6063 #define FLASH_WRP0_nWRP0_Pos (8U) 6064 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 6065 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 6066 6067 /****************** Bit definition for FLASH_WRP1 register ******************/ 6068 #define FLASH_WRP1_WRP1_Pos (16U) 6069 #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 6070 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 6071 #define FLASH_WRP1_nWRP1_Pos (24U) 6072 #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 6073 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 6074 6075 /****************** Bit definition for FLASH_WRP2 register ******************/ 6076 #define FLASH_WRP2_WRP2_Pos (0U) 6077 #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ 6078 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ 6079 #define FLASH_WRP2_nWRP2_Pos (8U) 6080 #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ 6081 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ 6082 6083 /****************** Bit definition for FLASH_WRP3 register ******************/ 6084 #define FLASH_WRP3_WRP3_Pos (16U) 6085 #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ 6086 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ 6087 #define FLASH_WRP3_nWRP3_Pos (24U) 6088 #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ 6089 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ 6090 6091 6092 6093 /** 6094 * @} 6095 */ 6096 6097 /** 6098 * @} 6099 */ 6100 6101 /** @addtogroup Exported_macro 6102 * @{ 6103 */ 6104 6105 /****************************** ADC Instances *********************************/ 6106 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) 6107 6108 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 6109 6110 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 6111 6112 /****************************** CEC Instances *********************************/ 6113 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC) 6114 6115 /****************************** CRC Instances *********************************/ 6116 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 6117 6118 /****************************** DAC Instances *********************************/ 6119 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 6120 6121 /****************************** DMA Instances *********************************/ 6122 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 6123 ((INSTANCE) == DMA1_Channel2) || \ 6124 ((INSTANCE) == DMA1_Channel3) || \ 6125 ((INSTANCE) == DMA1_Channel4) || \ 6126 ((INSTANCE) == DMA1_Channel5) || \ 6127 ((INSTANCE) == DMA1_Channel6) || \ 6128 ((INSTANCE) == DMA1_Channel7) || \ 6129 ((INSTANCE) == DMA2_Channel1) || \ 6130 ((INSTANCE) == DMA2_Channel2) || \ 6131 ((INSTANCE) == DMA2_Channel3) || \ 6132 ((INSTANCE) == DMA2_Channel4) || \ 6133 ((INSTANCE) == DMA2_Channel5)) 6134 6135 /******************************* GPIO Instances *******************************/ 6136 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6137 ((INSTANCE) == GPIOB) || \ 6138 ((INSTANCE) == GPIOC) || \ 6139 ((INSTANCE) == GPIOD) || \ 6140 ((INSTANCE) == GPIOE) || \ 6141 ((INSTANCE) == GPIOF) || \ 6142 ((INSTANCE) == GPIOG)) 6143 6144 /**************************** GPIO Alternate Function Instances ***************/ 6145 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 6146 6147 /**************************** GPIO Lock Instances *****************************/ 6148 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 6149 6150 /******************************** I2C Instances *******************************/ 6151 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6152 ((INSTANCE) == I2C2)) 6153 6154 /******************************* SMBUS Instances ******************************/ 6155 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE 6156 6157 /****************************** IWDG Instances ********************************/ 6158 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6159 6160 /******************************** SPI Instances *******************************/ 6161 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 6162 ((INSTANCE) == SPI2) || \ 6163 ((INSTANCE) == SPI3)) 6164 6165 /****************************** START TIM Instances ***************************/ 6166 /****************************** TIM Instances *********************************/ 6167 #define IS_TIM_INSTANCE(INSTANCE)\ 6168 (((INSTANCE) == TIM1) || \ 6169 ((INSTANCE) == TIM2) || \ 6170 ((INSTANCE) == TIM3) || \ 6171 ((INSTANCE) == TIM4) || \ 6172 ((INSTANCE) == TIM5) || \ 6173 ((INSTANCE) == TIM6) || \ 6174 ((INSTANCE) == TIM7) || \ 6175 ((INSTANCE) == TIM12) || \ 6176 ((INSTANCE) == TIM13) || \ 6177 ((INSTANCE) == TIM14) || \ 6178 ((INSTANCE) == TIM15) || \ 6179 ((INSTANCE) == TIM16) || \ 6180 ((INSTANCE) == TIM17)) 6181 6182 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 6183 6184 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 6185 (((INSTANCE) == TIM1) || \ 6186 ((INSTANCE) == TIM2) || \ 6187 ((INSTANCE) == TIM3) || \ 6188 ((INSTANCE) == TIM4) || \ 6189 ((INSTANCE) == TIM5) || \ 6190 ((INSTANCE) == TIM12) || \ 6191 ((INSTANCE) == TIM13) || \ 6192 ((INSTANCE) == TIM14) || \ 6193 ((INSTANCE) == TIM15) || \ 6194 ((INSTANCE) == TIM16) || \ 6195 ((INSTANCE) == TIM17)) 6196 6197 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 6198 (((INSTANCE) == TIM1) || \ 6199 ((INSTANCE) == TIM2) || \ 6200 ((INSTANCE) == TIM3) || \ 6201 ((INSTANCE) == TIM4) || \ 6202 ((INSTANCE) == TIM5) || \ 6203 ((INSTANCE) == TIM12) || \ 6204 ((INSTANCE) == TIM15)) 6205 6206 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 6207 (((INSTANCE) == TIM1) || \ 6208 ((INSTANCE) == TIM2) || \ 6209 ((INSTANCE) == TIM3) || \ 6210 ((INSTANCE) == TIM4) || \ 6211 ((INSTANCE) == TIM5)) 6212 6213 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 6214 (((INSTANCE) == TIM1) || \ 6215 ((INSTANCE) == TIM2) || \ 6216 ((INSTANCE) == TIM3) || \ 6217 ((INSTANCE) == TIM4) || \ 6218 ((INSTANCE) == TIM5)) 6219 6220 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 6221 (((INSTANCE) == TIM1) || \ 6222 ((INSTANCE) == TIM2) || \ 6223 ((INSTANCE) == TIM3) || \ 6224 ((INSTANCE) == TIM4) || \ 6225 ((INSTANCE) == TIM5)) 6226 6227 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 6228 (((INSTANCE) == TIM1) || \ 6229 ((INSTANCE) == TIM2) || \ 6230 ((INSTANCE) == TIM3) || \ 6231 ((INSTANCE) == TIM4) || \ 6232 ((INSTANCE) == TIM5)) 6233 6234 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 6235 (((INSTANCE) == TIM1) || \ 6236 ((INSTANCE) == TIM2) || \ 6237 ((INSTANCE) == TIM3) || \ 6238 ((INSTANCE) == TIM4) || \ 6239 ((INSTANCE) == TIM5) || \ 6240 ((INSTANCE) == TIM12) || \ 6241 ((INSTANCE) == TIM15)) 6242 6243 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 6244 (((INSTANCE) == TIM1) || \ 6245 ((INSTANCE) == TIM2) || \ 6246 ((INSTANCE) == TIM3) || \ 6247 ((INSTANCE) == TIM4) || \ 6248 ((INSTANCE) == TIM5) || \ 6249 ((INSTANCE) == TIM12) || \ 6250 ((INSTANCE) == TIM15)) 6251 6252 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 6253 (((INSTANCE) == TIM1) || \ 6254 ((INSTANCE) == TIM2) || \ 6255 ((INSTANCE) == TIM3) || \ 6256 ((INSTANCE) == TIM4) || \ 6257 ((INSTANCE) == TIM5)) 6258 6259 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 6260 (((INSTANCE) == TIM1) || \ 6261 ((INSTANCE) == TIM2) || \ 6262 ((INSTANCE) == TIM3) || \ 6263 ((INSTANCE) == TIM4) || \ 6264 ((INSTANCE) == TIM5)) 6265 6266 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 6267 (((INSTANCE) == TIM1) || \ 6268 ((INSTANCE) == TIM2) || \ 6269 ((INSTANCE) == TIM3) || \ 6270 ((INSTANCE) == TIM4) || \ 6271 ((INSTANCE) == TIM5)) 6272 6273 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 6274 (((INSTANCE) == TIM1) || \ 6275 ((INSTANCE) == TIM2) || \ 6276 ((INSTANCE) == TIM3) || \ 6277 ((INSTANCE) == TIM4) || \ 6278 ((INSTANCE) == TIM5) || \ 6279 ((INSTANCE) == TIM6) || \ 6280 ((INSTANCE) == TIM7) || \ 6281 ((INSTANCE) == TIM12) || \ 6282 ((INSTANCE) == TIM15)) 6283 6284 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 6285 (((INSTANCE) == TIM1) || \ 6286 ((INSTANCE) == TIM2) || \ 6287 ((INSTANCE) == TIM3) || \ 6288 ((INSTANCE) == TIM4) || \ 6289 ((INSTANCE) == TIM5) || \ 6290 ((INSTANCE) == TIM12) || \ 6291 ((INSTANCE) == TIM15)) 6292 6293 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 6294 (((INSTANCE) == TIM1) || \ 6295 ((INSTANCE) == TIM2) || \ 6296 ((INSTANCE) == TIM3) || \ 6297 ((INSTANCE) == TIM4) || \ 6298 ((INSTANCE) == TIM5) || \ 6299 ((INSTANCE) == TIM15) || \ 6300 ((INSTANCE) == TIM16) || \ 6301 ((INSTANCE) == TIM17)) 6302 6303 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 6304 (((INSTANCE) == TIM1) || \ 6305 ((INSTANCE) == TIM15) || \ 6306 ((INSTANCE) == TIM16) || \ 6307 ((INSTANCE) == TIM17)) 6308 6309 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 6310 ((((INSTANCE) == TIM1) && \ 6311 (((CHANNEL) == TIM_CHANNEL_1) || \ 6312 ((CHANNEL) == TIM_CHANNEL_2) || \ 6313 ((CHANNEL) == TIM_CHANNEL_3) || \ 6314 ((CHANNEL) == TIM_CHANNEL_4))) \ 6315 || \ 6316 (((INSTANCE) == TIM2) && \ 6317 (((CHANNEL) == TIM_CHANNEL_1) || \ 6318 ((CHANNEL) == TIM_CHANNEL_2) || \ 6319 ((CHANNEL) == TIM_CHANNEL_3) || \ 6320 ((CHANNEL) == TIM_CHANNEL_4))) \ 6321 || \ 6322 (((INSTANCE) == TIM3) && \ 6323 (((CHANNEL) == TIM_CHANNEL_1) || \ 6324 ((CHANNEL) == TIM_CHANNEL_2) || \ 6325 ((CHANNEL) == TIM_CHANNEL_3) || \ 6326 ((CHANNEL) == TIM_CHANNEL_4))) \ 6327 || \ 6328 (((INSTANCE) == TIM4) && \ 6329 (((CHANNEL) == TIM_CHANNEL_1) || \ 6330 ((CHANNEL) == TIM_CHANNEL_2) || \ 6331 ((CHANNEL) == TIM_CHANNEL_3) || \ 6332 ((CHANNEL) == TIM_CHANNEL_4))) \ 6333 || \ 6334 (((INSTANCE) == TIM5) && \ 6335 (((CHANNEL) == TIM_CHANNEL_1) || \ 6336 ((CHANNEL) == TIM_CHANNEL_2) || \ 6337 ((CHANNEL) == TIM_CHANNEL_3) || \ 6338 ((CHANNEL) == TIM_CHANNEL_4))) \ 6339 || \ 6340 (((INSTANCE) == TIM12) && \ 6341 (((CHANNEL) == TIM_CHANNEL_1) || \ 6342 ((CHANNEL) == TIM_CHANNEL_2))) \ 6343 || \ 6344 (((INSTANCE) == TIM13) && \ 6345 (((CHANNEL) == TIM_CHANNEL_1))) \ 6346 || \ 6347 (((INSTANCE) == TIM14) && \ 6348 (((CHANNEL) == TIM_CHANNEL_1))) \ 6349 || \ 6350 (((INSTANCE) == TIM15) && \ 6351 (((CHANNEL) == TIM_CHANNEL_1) || \ 6352 ((CHANNEL) == TIM_CHANNEL_2))) \ 6353 || \ 6354 (((INSTANCE) == TIM16) && \ 6355 (((CHANNEL) == TIM_CHANNEL_1))) \ 6356 || \ 6357 (((INSTANCE) == TIM17) && \ 6358 (((CHANNEL) == TIM_CHANNEL_1)))) 6359 6360 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 6361 ((((INSTANCE) == TIM1) && \ 6362 (((CHANNEL) == TIM_CHANNEL_1) || \ 6363 ((CHANNEL) == TIM_CHANNEL_2) || \ 6364 ((CHANNEL) == TIM_CHANNEL_3))) \ 6365 || \ 6366 (((INSTANCE) == TIM15) && \ 6367 ((CHANNEL) == TIM_CHANNEL_1)) \ 6368 || \ 6369 (((INSTANCE) == TIM16) && \ 6370 ((CHANNEL) == TIM_CHANNEL_1)) \ 6371 || \ 6372 (((INSTANCE) == TIM17) && \ 6373 ((CHANNEL) == TIM_CHANNEL_1))) 6374 6375 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 6376 (((INSTANCE) == TIM1) || \ 6377 ((INSTANCE) == TIM2) || \ 6378 ((INSTANCE) == TIM3) || \ 6379 ((INSTANCE) == TIM4) || \ 6380 ((INSTANCE) == TIM5)) 6381 6382 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 6383 (((INSTANCE) == TIM1) || \ 6384 ((INSTANCE) == TIM15) || \ 6385 ((INSTANCE) == TIM16) || \ 6386 ((INSTANCE) == TIM17)) 6387 6388 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 6389 (((INSTANCE) == TIM1) || \ 6390 ((INSTANCE) == TIM2) || \ 6391 ((INSTANCE) == TIM3) || \ 6392 ((INSTANCE) == TIM4) || \ 6393 ((INSTANCE) == TIM5) || \ 6394 ((INSTANCE) == TIM12) || \ 6395 ((INSTANCE) == TIM13) || \ 6396 ((INSTANCE) == TIM14) || \ 6397 ((INSTANCE) == TIM15) || \ 6398 ((INSTANCE) == TIM16) || \ 6399 ((INSTANCE) == TIM17)) 6400 6401 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 6402 (((INSTANCE) == TIM1) || \ 6403 ((INSTANCE) == TIM2) || \ 6404 ((INSTANCE) == TIM3) || \ 6405 ((INSTANCE) == TIM4) || \ 6406 ((INSTANCE) == TIM5) || \ 6407 ((INSTANCE) == TIM6) || \ 6408 ((INSTANCE) == TIM7) || \ 6409 ((INSTANCE) == TIM15) || \ 6410 ((INSTANCE) == TIM16) || \ 6411 ((INSTANCE) == TIM17)) 6412 6413 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 6414 (((INSTANCE) == TIM1) || \ 6415 ((INSTANCE) == TIM2) || \ 6416 ((INSTANCE) == TIM3) || \ 6417 ((INSTANCE) == TIM4) || \ 6418 ((INSTANCE) == TIM5) || \ 6419 ((INSTANCE) == TIM15) || \ 6420 ((INSTANCE) == TIM16) || \ 6421 ((INSTANCE) == TIM17)) 6422 6423 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 6424 (((INSTANCE) == TIM1) || \ 6425 ((INSTANCE) == TIM15) || \ 6426 ((INSTANCE) == TIM16) || \ 6427 ((INSTANCE) == TIM17)) 6428 6429 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6430 ((INSTANCE) == TIM2) || \ 6431 ((INSTANCE) == TIM3) || \ 6432 ((INSTANCE) == TIM4) || \ 6433 ((INSTANCE) == TIM5)) 6434 6435 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 6436 ((INSTANCE) == TIM2) || \ 6437 ((INSTANCE) == TIM3) || \ 6438 ((INSTANCE) == TIM4) || \ 6439 ((INSTANCE) == TIM5)) 6440 6441 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U 6442 6443 /****************************** END TIM Instances *****************************/ 6444 6445 6446 /******************** USART Instances : Synchronous mode **********************/ 6447 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6448 ((INSTANCE) == USART2) || \ 6449 ((INSTANCE) == USART3)) 6450 6451 /******************** UART Instances : Asynchronous mode **********************/ 6452 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6453 ((INSTANCE) == USART2) || \ 6454 ((INSTANCE) == USART3) || \ 6455 ((INSTANCE) == UART4) || \ 6456 ((INSTANCE) == UART5)) 6457 6458 /******************** UART Instances : Half-Duplex mode **********************/ 6459 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6460 ((INSTANCE) == USART2) || \ 6461 ((INSTANCE) == USART3) || \ 6462 ((INSTANCE) == UART4) || \ 6463 ((INSTANCE) == UART5)) 6464 6465 /******************** UART Instances : LIN mode **********************/ 6466 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6467 ((INSTANCE) == USART2) || \ 6468 ((INSTANCE) == USART3) || \ 6469 ((INSTANCE) == UART4) || \ 6470 ((INSTANCE) == UART5)) 6471 6472 /****************** UART Instances : Hardware Flow control ********************/ 6473 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6474 ((INSTANCE) == USART2) || \ 6475 ((INSTANCE) == USART3)) 6476 6477 /********************* UART Instances : Smard card mode ***********************/ 6478 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6479 ((INSTANCE) == USART2) || \ 6480 ((INSTANCE) == USART3)) 6481 6482 /*********************** UART Instances : IRDA mode ***************************/ 6483 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6484 ((INSTANCE) == USART2) || \ 6485 ((INSTANCE) == USART3) || \ 6486 ((INSTANCE) == UART4) || \ 6487 ((INSTANCE) == UART5)) 6488 6489 /***************** UART Instances : Multi-Processor mode **********************/ 6490 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6491 ((INSTANCE) == USART2) || \ 6492 ((INSTANCE) == USART3) || \ 6493 ((INSTANCE) == UART4) || \ 6494 ((INSTANCE) == UART5)) 6495 6496 /***************** UART Instances : DMA mode available **********************/ 6497 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6498 ((INSTANCE) == USART2) || \ 6499 ((INSTANCE) == USART3) || \ 6500 ((INSTANCE) == UART4) || \ 6501 ((INSTANCE) == UART5)) 6502 6503 /****************************** RTC Instances *********************************/ 6504 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 6505 6506 /**************************** WWDG Instances *****************************/ 6507 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6508 6509 6510 6511 6512 #define RCC_HSE_MIN 4000000U 6513 #define RCC_HSE_MAX 26000000U 6514 6515 #define RCC_MAX_FREQUENCY 24000000U 6516 6517 /** 6518 * @} 6519 */ 6520 /******************************************************************************/ 6521 /* For a painless codes migration between the STM32F1xx device product */ 6522 /* lines, the aliases defined below are put in place to overcome the */ 6523 /* differences in the interrupt handlers and IRQn definitions. */ 6524 /* No need to update developed interrupt code when moving across */ 6525 /* product lines within the same STM32F1 Family */ 6526 /******************************************************************************/ 6527 6528 /* Aliases for __IRQn */ 6529 #define ADC1_2_IRQn ADC1_IRQn 6530 #define OTG_FS_WKUP_IRQn CEC_IRQn 6531 #define USBWakeUp_IRQn CEC_IRQn 6532 #define TIM8_BRK_IRQn TIM12_IRQn 6533 #define TIM8_BRK_TIM12_IRQn TIM12_IRQn 6534 #define TIM8_UP_IRQn TIM13_IRQn 6535 #define TIM8_UP_TIM13_IRQn TIM13_IRQn 6536 #define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn 6537 #define TIM8_TRG_COM_IRQn TIM14_IRQn 6538 #define TIM9_IRQn TIM1_BRK_TIM15_IRQn 6539 #define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn 6540 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn 6541 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn 6542 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn 6543 #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn 6544 #define TIM10_IRQn TIM1_UP_TIM16_IRQn 6545 #define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn 6546 #define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn 6547 #define TIM6_IRQn TIM6_DAC_IRQn 6548 6549 6550 /* Aliases for __IRQHandler */ 6551 #define ADC1_2_IRQHandler ADC1_IRQHandler 6552 #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler 6553 #define USBWakeUp_IRQHandler CEC_IRQHandler 6554 #define TIM8_BRK_IRQHandler TIM12_IRQHandler 6555 #define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler 6556 #define TIM8_UP_IRQHandler TIM13_IRQHandler 6557 #define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler 6558 #define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler 6559 #define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler 6560 #define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler 6561 #define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler 6562 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler 6563 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 6564 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 6565 #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 6566 #define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler 6567 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler 6568 #define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler 6569 #define TIM6_IRQHandler TIM6_DAC_IRQHandler 6570 6571 6572 /** 6573 * @} 6574 */ 6575 6576 /** 6577 * @} 6578 */ 6579 6580 6581 #ifdef __cplusplus 6582 } 6583 #endif /* __cplusplus */ 6584 6585 #endif /* __STM32F100xE_H */ 6586 6587 6588 6589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 6590
