1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F1xx_HAL_RCC_H 22 #define __STM32F1xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f1xx_hal_def.h" 30 31 32 /** @addtogroup STM32F1xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup RCC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup RCC_Exported_Types RCC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief RCC PLL configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 52 This parameter can be a value of @ref RCC_PLL_Config */ 53 54 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 55 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 56 57 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 58 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ 59 } RCC_PLLInitTypeDef; 60 61 /** 62 * @brief RCC System, AHB and APB busses clock configuration structure definition 63 */ 64 typedef struct 65 { 66 uint32_t ClockType; /*!< The clock to be configured. 67 This parameter can be a value of @ref RCC_System_Clock_Type */ 68 69 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 70 This parameter can be a value of @ref RCC_System_Clock_Source */ 71 72 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 73 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 74 75 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 76 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 77 78 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 79 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 80 } RCC_ClkInitTypeDef; 81 82 /** 83 * @} 84 */ 85 86 /* Exported constants --------------------------------------------------------*/ 87 /** @defgroup RCC_Exported_Constants RCC Exported Constants 88 * @{ 89 */ 90 91 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 92 * @{ 93 */ 94 95 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ 96 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup RCC_Oscillator_Type Oscillator Type 103 * @{ 104 */ 105 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 106 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 107 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 108 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 109 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 110 /** 111 * @} 112 */ 113 114 /** @defgroup RCC_HSE_Config HSE Config 115 * @{ 116 */ 117 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 118 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 119 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 120 /** 121 * @} 122 */ 123 124 /** @defgroup RCC_LSE_Config LSE Config 125 * @{ 126 */ 127 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 128 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 129 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 130 131 /** 132 * @} 133 */ 134 135 /** @defgroup RCC_HSI_Config HSI Config 136 * @{ 137 */ 138 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 139 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 140 141 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 142 143 /** 144 * @} 145 */ 146 147 /** @defgroup RCC_LSI_Config LSI Config 148 * @{ 149 */ 150 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 151 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 152 153 /** 154 * @} 155 */ 156 157 /** @defgroup RCC_PLL_Config PLL Config 158 * @{ 159 */ 160 #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ 161 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 162 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 163 164 /** 165 * @} 166 */ 167 168 /** @defgroup RCC_System_Clock_Type System Clock Type 169 * @{ 170 */ 171 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 172 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 173 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 174 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup RCC_System_Clock_Source System Clock Source 181 * @{ 182 */ 183 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 184 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 185 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 186 187 /** 188 * @} 189 */ 190 191 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 192 * @{ 193 */ 194 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 195 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 196 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 197 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 203 * @{ 204 */ 205 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 206 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 207 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 208 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 209 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 210 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 211 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 212 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 213 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 214 215 /** 216 * @} 217 */ 218 219 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 220 * @{ 221 */ 222 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 223 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 224 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 225 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 226 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 227 228 /** 229 * @} 230 */ 231 232 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 233 * @{ 234 */ 235 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ 236 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 237 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 238 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ 239 /** 240 * @} 241 */ 242 243 244 /** @defgroup RCC_MCO_Index MCO Index 245 * @{ 246 */ 247 #define RCC_MCO1 0x00000000U 248 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 249 250 /** 251 * @} 252 */ 253 254 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 255 * @{ 256 */ 257 #define RCC_MCODIV_1 0x00000000U 258 259 /** 260 * @} 261 */ 262 263 /** @defgroup RCC_Interrupt Interrupts 264 * @{ 265 */ 266 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 267 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 268 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 269 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 270 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 271 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup RCC_Flag Flags 277 * Elements values convention: XXXYYYYYb 278 * - YYYYY : Flag position in the register 279 * - XXX : Register index 280 * - 001: CR register 281 * - 010: BDCR register 282 * - 011: CSR register 283 * @{ 284 */ 285 /* Flags in the CR register */ 286 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ 287 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ 288 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ 289 290 /* Flags in the CSR register */ 291 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ 292 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 293 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ 294 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 295 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 296 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 297 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 298 299 /* Flags in the BDCR register */ 300 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ 301 302 /** 303 * @} 304 */ 305 306 /** 307 * @} 308 */ 309 310 /* Exported macro ------------------------------------------------------------*/ 311 312 /** @defgroup RCC_Exported_Macros RCC Exported Macros 313 * @{ 314 */ 315 316 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 317 * @brief Enable or disable the AHB1 peripheral clock. 318 * @note After reset, the peripheral clock (used for registers read/write access) 319 * is disabled and the application software has to enable this clock before 320 * using it. 321 * @{ 322 */ 323 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 324 __IO uint32_t tmpreg; \ 325 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 326 /* Delay after an RCC peripheral clock enabling */\ 327 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 328 UNUSED(tmpreg); \ 329 } while(0U) 330 331 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 332 __IO uint32_t tmpreg; \ 333 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 334 /* Delay after an RCC peripheral clock enabling */\ 335 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 336 UNUSED(tmpreg); \ 337 } while(0U) 338 339 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 340 __IO uint32_t tmpreg; \ 341 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 342 /* Delay after an RCC peripheral clock enabling */\ 343 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 344 UNUSED(tmpreg); \ 345 } while(0U) 346 347 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 348 __IO uint32_t tmpreg; \ 349 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 350 /* Delay after an RCC peripheral clock enabling */\ 351 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 352 UNUSED(tmpreg); \ 353 } while(0U) 354 355 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 356 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 357 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 358 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 359 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 365 * @brief Get the enable or disable status of the AHB peripheral clock. 366 * @note After reset, the peripheral clock (used for registers read/write access) 367 * is disabled and the application software has to enable this clock before 368 * using it. 369 * @{ 370 */ 371 372 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 373 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 374 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 375 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 376 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 377 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 378 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 379 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 380 381 /** 382 * @} 383 */ 384 385 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 386 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 387 * @note After reset, the peripheral clock (used for registers read/write access) 388 * is disabled and the application software has to enable this clock before 389 * using it. 390 * @{ 391 */ 392 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 393 __IO uint32_t tmpreg; \ 394 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 395 /* Delay after an RCC peripheral clock enabling */\ 396 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 397 UNUSED(tmpreg); \ 398 } while(0U) 399 400 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 401 __IO uint32_t tmpreg; \ 402 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 403 /* Delay after an RCC peripheral clock enabling */\ 404 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 405 UNUSED(tmpreg); \ 406 } while(0U) 407 408 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 409 __IO uint32_t tmpreg; \ 410 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 411 /* Delay after an RCC peripheral clock enabling */\ 412 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 413 UNUSED(tmpreg); \ 414 } while(0U) 415 416 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 417 __IO uint32_t tmpreg; \ 418 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 419 /* Delay after an RCC peripheral clock enabling */\ 420 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 421 UNUSED(tmpreg); \ 422 } while(0U) 423 424 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 425 __IO uint32_t tmpreg; \ 426 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 427 /* Delay after an RCC peripheral clock enabling */\ 428 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 429 UNUSED(tmpreg); \ 430 } while(0U) 431 432 #define __HAL_RCC_BKP_CLK_ENABLE() do { \ 433 __IO uint32_t tmpreg; \ 434 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 435 /* Delay after an RCC peripheral clock enabling */\ 436 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 437 UNUSED(tmpreg); \ 438 } while(0U) 439 440 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 441 __IO uint32_t tmpreg; \ 442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 443 /* Delay after an RCC peripheral clock enabling */\ 444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 445 UNUSED(tmpreg); \ 446 } while(0U) 447 448 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 449 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 450 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 451 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 452 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 453 454 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) 455 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 456 457 /** 458 * @} 459 */ 460 461 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 462 * @brief Get the enable or disable status of the APB1 peripheral clock. 463 * @note After reset, the peripheral clock (used for registers read/write access) 464 * is disabled and the application software has to enable this clock before 465 * using it. 466 * @{ 467 */ 468 469 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 470 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 471 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 472 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 473 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 474 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 475 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 476 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 477 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 478 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 479 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) 480 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) 481 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 482 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 483 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 489 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 490 * @note After reset, the peripheral clock (used for registers read/write access) 491 * is disabled and the application software has to enable this clock before 492 * using it. 493 * @{ 494 */ 495 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ 496 __IO uint32_t tmpreg; \ 497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 498 /* Delay after an RCC peripheral clock enabling */\ 499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 500 UNUSED(tmpreg); \ 501 } while(0U) 502 503 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 504 __IO uint32_t tmpreg; \ 505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 506 /* Delay after an RCC peripheral clock enabling */\ 507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 508 UNUSED(tmpreg); \ 509 } while(0U) 510 511 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 512 __IO uint32_t tmpreg; \ 513 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 514 /* Delay after an RCC peripheral clock enabling */\ 515 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 516 UNUSED(tmpreg); \ 517 } while(0U) 518 519 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 520 __IO uint32_t tmpreg; \ 521 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 522 /* Delay after an RCC peripheral clock enabling */\ 523 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 524 UNUSED(tmpreg); \ 525 } while(0U) 526 527 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 528 __IO uint32_t tmpreg; \ 529 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 530 /* Delay after an RCC peripheral clock enabling */\ 531 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 532 UNUSED(tmpreg); \ 533 } while(0U) 534 535 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 536 __IO uint32_t tmpreg; \ 537 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 538 /* Delay after an RCC peripheral clock enabling */\ 539 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 540 UNUSED(tmpreg); \ 541 } while(0U) 542 543 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 544 __IO uint32_t tmpreg; \ 545 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 546 /* Delay after an RCC peripheral clock enabling */\ 547 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 548 UNUSED(tmpreg); \ 549 } while(0U) 550 551 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 552 __IO uint32_t tmpreg; \ 553 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 554 /* Delay after an RCC peripheral clock enabling */\ 555 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 556 UNUSED(tmpreg); \ 557 } while(0U) 558 559 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 560 __IO uint32_t tmpreg; \ 561 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 562 /* Delay after an RCC peripheral clock enabling */\ 563 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 564 UNUSED(tmpreg); \ 565 } while(0U) 566 567 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) 568 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) 569 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) 570 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) 571 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) 572 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 573 574 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 575 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 576 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 577 578 /** 579 * @} 580 */ 581 582 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 583 * @brief Get the enable or disable status of the APB2 peripheral clock. 584 * @note After reset, the peripheral clock (used for registers read/write access) 585 * is disabled and the application software has to enable this clock before 586 * using it. 587 * @{ 588 */ 589 590 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) 591 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) 592 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) 593 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) 594 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) 595 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) 596 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) 597 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) 598 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) 599 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) 600 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 601 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 602 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 603 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 604 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 605 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 606 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 607 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 608 609 /** 610 * @} 611 */ 612 613 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 614 * @brief Force or release APB1 peripheral reset. 615 * @{ 616 */ 617 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 618 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 619 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 620 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 621 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 622 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 623 624 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) 625 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 626 627 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) 628 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 629 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 630 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 631 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 632 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 633 634 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) 635 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 636 637 /** 638 * @} 639 */ 640 641 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 642 * @brief Force or release APB2 peripheral reset. 643 * @{ 644 */ 645 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 646 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) 647 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) 648 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) 649 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) 650 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) 651 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 652 653 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 654 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 655 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 656 657 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) 658 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) 659 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) 660 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) 661 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) 662 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) 663 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 664 665 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 666 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 667 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 668 669 /** 670 * @} 671 */ 672 673 /** @defgroup RCC_HSI_Configuration HSI Configuration 674 * @{ 675 */ 676 677 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 678 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 679 * @note HSI can not be stopped if it is used as system clock source. In this case, 680 * you have to select another source of the system clock then stop the HSI. 681 * @note After enabling the HSI, the application software should wait on HSIRDY 682 * flag to be set indicating that HSI clock is stable and can be used as 683 * system clock source. 684 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 685 * clock cycles. 686 */ 687 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 688 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 689 690 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 691 * @note The calibration is used to compensate for the variations in voltage 692 * and temperature that influence the frequency of the internal HSI RC. 693 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 694 * (default is RCC_HSICALIBRATION_DEFAULT). 695 * This parameter must be a number between 0 and 0x1F. 696 */ 697 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 698 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) 699 700 /** 701 * @} 702 */ 703 704 /** @defgroup RCC_LSI_Configuration LSI Configuration 705 * @{ 706 */ 707 708 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 709 * @note After enabling the LSI, the application software should wait on 710 * LSIRDY flag to be set indicating that LSI clock is stable and can 711 * be used to clock the IWDG and/or the RTC. 712 */ 713 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 714 715 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 716 * @note LSI can not be disabled if the IWDG is running. 717 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 718 * clock cycles. 719 */ 720 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 721 722 /** 723 * @} 724 */ 725 726 /** @defgroup RCC_HSE_Configuration HSE Configuration 727 * @{ 728 */ 729 730 /** 731 * @brief Macro to configure the External High Speed oscillator (HSE). 732 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 733 * supported by this macro. User should request a transition to HSE Off 734 * first and then HSE On or HSE Bypass. 735 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 736 * software should wait on HSERDY flag to be set indicating that HSE clock 737 * is stable and can be used to clock the PLL and/or system clock. 738 * @note HSE state can not be changed if it is used directly or through the 739 * PLL as system clock. In this case, you have to select another source 740 * of the system clock then change the HSE state (ex. disable it). 741 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 742 * @note This function reset the CSSON bit, so if the clock security system(CSS) 743 * was previously enabled you have to enable it again after calling this 744 * function. 745 * @param __STATE__ specifies the new state of the HSE. 746 * This parameter can be one of the following values: 747 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 748 * 6 HSE oscillator clock cycles. 749 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 750 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 751 */ 752 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 753 do{ \ 754 if ((__STATE__) == RCC_HSE_ON) \ 755 { \ 756 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 757 } \ 758 else if ((__STATE__) == RCC_HSE_OFF) \ 759 { \ 760 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 761 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 762 } \ 763 else if ((__STATE__) == RCC_HSE_BYPASS) \ 764 { \ 765 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 766 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 767 } \ 768 else \ 769 { \ 770 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 771 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 772 } \ 773 }while(0U) 774 775 /** 776 * @} 777 */ 778 779 /** @defgroup RCC_LSE_Configuration LSE Configuration 780 * @{ 781 */ 782 783 /** 784 * @brief Macro to configure the External Low Speed oscillator (LSE). 785 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 786 * @note As the LSE is in the Backup domain and write access is denied to 787 * this domain after reset, you have to enable write access using 788 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 789 * (to be done once after reset). 790 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 791 * software should wait on LSERDY flag to be set indicating that LSE clock 792 * is stable and can be used to clock the RTC. 793 * @param __STATE__ specifies the new state of the LSE. 794 * This parameter can be one of the following values: 795 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 796 * 6 LSE oscillator clock cycles. 797 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 798 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 799 */ 800 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 801 do{ \ 802 if ((__STATE__) == RCC_LSE_ON) \ 803 { \ 804 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 805 } \ 806 else if ((__STATE__) == RCC_LSE_OFF) \ 807 { \ 808 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 809 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 810 } \ 811 else if ((__STATE__) == RCC_LSE_BYPASS) \ 812 { \ 813 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 814 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 815 } \ 816 else \ 817 { \ 818 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 819 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 820 } \ 821 }while(0U) 822 823 /** 824 * @} 825 */ 826 827 /** @defgroup RCC_PLL_Configuration PLL Configuration 828 * @{ 829 */ 830 831 /** @brief Macro to enable the main PLL. 832 * @note After enabling the main PLL, the application software should wait on 833 * PLLRDY flag to be set indicating that PLL clock is stable and can 834 * be used as system clock source. 835 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 836 */ 837 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 838 839 /** @brief Macro to disable the main PLL. 840 * @note The main PLL can not be disabled if it is used as system clock source 841 */ 842 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 843 844 /** @brief Macro to configure the main PLL clock source and multiplication factors. 845 * @note This function must be used only when the main PLL is disabled. 846 * 847 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 848 * This parameter can be one of the following values: 849 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry 850 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 851 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 852 * This parameter can be one of the following values: 853 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 854 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 855 @if STM32F105xC 856 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 857 @elseif STM32F107xC 858 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 859 @else 860 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 861 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 862 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 863 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 864 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 865 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 866 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 867 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 868 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 869 @endif 870 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 871 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 872 * 873 */ 874 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ 875 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) 876 877 /** @brief Get oscillator clock selected as PLL input clock 878 * @retval The clock source used for PLL entry. The returned value can be one 879 * of the following: 880 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock 881 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 882 */ 883 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 884 885 /** 886 * @} 887 */ 888 889 /** @defgroup RCC_Get_Clock_source Get Clock source 890 * @{ 891 */ 892 893 /** 894 * @brief Macro to configure the system clock source. 895 * @param __SYSCLKSOURCE__ specifies the system clock source. 896 * This parameter can be one of the following values: 897 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 898 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 899 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 900 */ 901 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 902 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 903 904 /** @brief Macro to get the clock source used as system clock. 905 * @retval The clock source used as system clock. The returned value can be one 906 * of the following: 907 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 908 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 909 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 910 */ 911 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 912 913 /** 914 * @} 915 */ 916 917 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 918 * @{ 919 */ 920 921 #if defined(RCC_CFGR_MCO_3) 922 /** @brief Macro to configure the MCO clock. 923 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 924 * This parameter can be one of the following values: 925 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 926 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 927 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 928 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 929 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 930 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock 931 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock 932 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock 933 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock 934 * @param __MCODIV__ specifies the MCO clock prescaler. 935 * This parameter can be one of the following values: 936 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 937 */ 938 #else 939 /** @brief Macro to configure the MCO clock. 940 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 941 * This parameter can be one of the following values: 942 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 943 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 944 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 945 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 946 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 947 * @param __MCODIV__ specifies the MCO clock prescaler. 948 * This parameter can be one of the following values: 949 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 950 */ 951 #endif 952 953 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 954 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 955 956 957 /** 958 * @} 959 */ 960 961 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 962 * @{ 963 */ 964 965 /** @brief Macro to configure the RTC clock (RTCCLK). 966 * @note As the RTC clock configuration bits are in the Backup domain and write 967 * access is denied to this domain after reset, you have to enable write 968 * access using the Power Backup Access macro before to configure 969 * the RTC clock source (to be done once after reset). 970 * @note Once the RTC clock is configured it can't be changed unless the 971 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 972 * a Power On Reset (POR). 973 * 974 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 975 * This parameter can be one of the following values: 976 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 977 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 978 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 979 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 980 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 981 * work in STOP and STANDBY modes, and can be used as wakeup source. 982 * However, when the HSE clock is used as RTC clock source, the RTC 983 * cannot be used in STOP and STANDBY modes. 984 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 985 * RTC clock source). 986 */ 987 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 988 989 /** @brief Macro to get the RTC clock source. 990 * @retval The clock source can be one of the following values: 991 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 992 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 993 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 994 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 995 */ 996 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 997 998 /** @brief Macro to enable the the RTC clock. 999 * @note These macros must be used only after the RTC clock source was selected. 1000 */ 1001 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 1002 1003 /** @brief Macro to disable the the RTC clock. 1004 * @note These macros must be used only after the RTC clock source was selected. 1005 */ 1006 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 1007 1008 /** @brief Macro to force the Backup domain reset. 1009 * @note This function resets the RTC peripheral (including the backup registers) 1010 * and the RTC clock source selection in RCC_BDCR register. 1011 */ 1012 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 1013 1014 /** @brief Macros to release the Backup domain reset. 1015 */ 1016 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 1017 1018 /** 1019 * @} 1020 */ 1021 1022 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1023 * @brief macros to manage the specified RCC Flags and interrupts. 1024 * @{ 1025 */ 1026 1027 /** @brief Enable RCC interrupt. 1028 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1029 * This parameter can be any combination of the following values: 1030 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1031 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1032 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1033 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1034 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1035 @if STM32F105xx 1036 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1037 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1038 @elsif STM32F107xx 1039 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1040 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1041 @endif 1042 */ 1043 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1044 1045 /** @brief Disable RCC interrupt. 1046 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1047 * This parameter can be any combination of the following values: 1048 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1049 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1050 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1051 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1052 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1053 @if STM32F105xx 1054 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1055 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1056 @elsif STM32F107xx 1057 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1058 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1059 @endif 1060 */ 1061 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1062 1063 /** @brief Clear the RCC's interrupt pending bits. 1064 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1065 * This parameter can be any combination of the following values: 1066 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1067 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1068 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1069 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1070 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1071 @if STM32F105xx 1072 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1073 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1074 @elsif STM32F107xx 1075 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1076 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1077 @endif 1078 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1079 */ 1080 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1081 1082 /** @brief Check the RCC's interrupt has occurred or not. 1083 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1084 * This parameter can be one of the following values: 1085 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1086 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1087 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1088 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1089 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1090 @if STM32F105xx 1091 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1092 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1093 @elsif STM32F107xx 1094 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1095 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1096 @endif 1097 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1098 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1099 */ 1100 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1101 1102 /** @brief Set RMVF bit to clear the reset flags. 1103 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1104 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1105 */ 1106 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) 1107 1108 /** @brief Check RCC flag is set or not. 1109 * @param __FLAG__ specifies the flag to check. 1110 * This parameter can be one of the following values: 1111 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 1112 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 1113 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 1114 @if STM32F105xx 1115 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 1116 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 1117 @elsif STM32F107xx 1118 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 1119 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 1120 @endif 1121 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 1122 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 1123 * @arg @ref RCC_FLAG_PINRST Pin reset. 1124 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 1125 * @arg @ref RCC_FLAG_SFTRST Software reset. 1126 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 1127 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 1128 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 1129 * @retval The new state of __FLAG__ (TRUE or FALSE). 1130 */ 1131 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ 1132 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ 1133 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) 1134 1135 /** 1136 * @} 1137 */ 1138 1139 /** 1140 * @} 1141 */ 1142 1143 /* Include RCC HAL Extension module */ 1144 #include "stm32f1xx_hal_rcc_ex.h" 1145 1146 /* Exported functions --------------------------------------------------------*/ 1147 /** @addtogroup RCC_Exported_Functions 1148 * @{ 1149 */ 1150 1151 /** @addtogroup RCC_Exported_Functions_Group1 1152 * @{ 1153 */ 1154 1155 /* Initialization and de-initialization functions ******************************/ 1156 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1157 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1158 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1159 1160 /** 1161 * @} 1162 */ 1163 1164 /** @addtogroup RCC_Exported_Functions_Group2 1165 * @{ 1166 */ 1167 1168 /* Peripheral Control functions ************************************************/ 1169 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1170 void HAL_RCC_EnableCSS(void); 1171 void HAL_RCC_DisableCSS(void); 1172 uint32_t HAL_RCC_GetSysClockFreq(void); 1173 uint32_t HAL_RCC_GetHCLKFreq(void); 1174 uint32_t HAL_RCC_GetPCLK1Freq(void); 1175 uint32_t HAL_RCC_GetPCLK2Freq(void); 1176 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1177 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1178 1179 /* CSS NMI IRQ handler */ 1180 void HAL_RCC_NMI_IRQHandler(void); 1181 1182 /* User Callbacks in non blocking mode (IT mode) */ 1183 void HAL_RCC_CSSCallback(void); 1184 1185 /** 1186 * @} 1187 */ 1188 1189 /** 1190 * @} 1191 */ 1192 1193 /** @addtogroup RCC_Private_Constants 1194 * @{ 1195 */ 1196 1197 /** @defgroup RCC_Timeout RCC Timeout 1198 * @{ 1199 */ 1200 1201 /* Disable Backup domain write protection state change timeout */ 1202 #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ 1203 /* LSE state change timeout */ 1204 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 1205 #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ 1206 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 1207 #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1208 #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1209 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1210 1211 /** 1212 * @} 1213 */ 1214 1215 /** @defgroup RCC_Register_Offset Register offsets 1216 * @{ 1217 */ 1218 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 1219 #define RCC_CR_OFFSET 0x00U 1220 #define RCC_CFGR_OFFSET 0x04U 1221 #define RCC_CIR_OFFSET 0x08U 1222 #define RCC_BDCR_OFFSET 0x20U 1223 #define RCC_CSR_OFFSET 0x24U 1224 1225 /** 1226 * @} 1227 */ 1228 1229 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 1230 * @brief RCC registers bit address in the alias region 1231 * @{ 1232 */ 1233 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 1234 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 1235 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 1236 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) 1237 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 1238 1239 /* --- CR Register ---*/ 1240 /* Alias word address of HSION bit */ 1241 #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos 1242 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) 1243 /* Alias word address of HSEON bit */ 1244 #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos 1245 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) 1246 /* Alias word address of CSSON bit */ 1247 #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos 1248 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) 1249 /* Alias word address of PLLON bit */ 1250 #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos 1251 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) 1252 1253 /* --- CSR Register ---*/ 1254 /* Alias word address of LSION bit */ 1255 #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos 1256 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) 1257 1258 /* Alias word address of RMVF bit */ 1259 #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos 1260 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) 1261 1262 /* --- BDCR Registers ---*/ 1263 /* Alias word address of LSEON bit */ 1264 #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos 1265 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) 1266 1267 /* Alias word address of LSEON bit */ 1268 #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos 1269 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) 1270 1271 /* Alias word address of RTCEN bit */ 1272 #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos 1273 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) 1274 1275 /* Alias word address of BDRST bit */ 1276 #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos 1277 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) 1278 1279 /** 1280 * @} 1281 */ 1282 1283 /* CR register byte 2 (Bits[23:16]) base address */ 1284 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) 1285 1286 /* CIR register byte 1 (Bits[15:8]) base address */ 1287 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) 1288 1289 /* CIR register byte 2 (Bits[23:16]) base address */ 1290 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) 1291 1292 /* Defines used for Flags */ 1293 #define CR_REG_INDEX ((uint8_t)1) 1294 #define BDCR_REG_INDEX ((uint8_t)2) 1295 #define CSR_REG_INDEX ((uint8_t)3) 1296 1297 #define RCC_FLAG_MASK ((uint8_t)0x1F) 1298 1299 /** 1300 * @} 1301 */ 1302 1303 /** @addtogroup RCC_Private_Macros 1304 * @{ 1305 */ 1306 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy 1307 * @{ 1308 */ 1309 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 1310 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 1311 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 1312 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 1313 /** 1314 * @} 1315 */ 1316 1317 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ 1318 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 1319 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 1320 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 1321 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 1322 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 1323 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 1324 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 1325 ((__HSE__) == RCC_HSE_BYPASS)) 1326 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 1327 ((__LSE__) == RCC_LSE_BYPASS)) 1328 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 1329 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 1330 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 1331 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 1332 ((__PLL__) == RCC_PLL_ON)) 1333 1334 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 1335 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 1336 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 1337 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 1338 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 1339 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 1340 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 1341 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 1342 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 1343 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 1344 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 1345 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 1346 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 1347 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 1348 ((__HCLK__) == RCC_SYSCLK_DIV512)) 1349 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 1350 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 1351 ((__PCLK__) == RCC_HCLK_DIV16)) 1352 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 1353 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) 1354 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 1355 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 1356 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 1357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) 1358 1359 /** 1360 * @} 1361 */ 1362 1363 /** 1364 * @} 1365 */ 1366 1367 /** 1368 * @} 1369 */ 1370 1371 #ifdef __cplusplus 1372 } 1373 #endif 1374 1375 #endif /* __STM32F1xx_HAL_RCC_H */ 1376 1377 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1378 1379
