1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_gpio_ex.h 4 * @author MCD Application Team 5 * @brief Header file of GPIO HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F1xx_HAL_GPIO_EX_H 22 #define STM32F1xx_HAL_GPIO_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f1xx_hal_def.h" 30 31 /** @addtogroup STM32F1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup GPIOEx GPIOEx 36 * @{ 37 */ 38 /* Exported types ------------------------------------------------------------*/ 39 /* Exported constants --------------------------------------------------------*/ 40 41 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants 42 * @{ 43 */ 44 45 /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration 46 * @brief This section propose definition to use the Cortex EVENTOUT signal. 47 * @{ 48 */ 49 50 /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin 51 * @{ 52 */ 53 54 #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ 55 #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ 56 #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ 57 #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ 58 #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ 59 #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ 60 #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ 61 #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ 62 #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ 63 #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ 64 #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ 65 #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ 66 #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ 67 #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ 68 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ 69 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ 70 71 #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ 72 ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ 73 ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ 74 ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ 75 ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ 76 ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ 77 ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ 78 ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ 79 ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ 80 ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ 81 ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ 82 ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ 83 ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ 84 ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ 85 ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ 86 ((__PIN__) == AFIO_EVENTOUT_PIN_15)) 87 /** 88 * @} 89 */ 90 91 /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port 92 * @{ 93 */ 94 95 #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ 96 #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ 97 #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ 98 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ 99 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ 100 101 #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ 102 ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ 103 ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ 104 ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ 105 ((__PORT__) == AFIO_EVENTOUT_PORT_E)) 106 /** 107 * @} 108 */ 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping 115 * @brief This section propose definition to remap the alternate function to some other port/pins. 116 * @{ 117 */ 118 119 /** 120 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 121 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 122 * @retval None 123 */ 124 #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) 125 126 /** 127 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 128 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 129 * @retval None 130 */ 131 #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) 132 133 /** 134 * @brief Enable the remapping of I2C1 alternate function SCL and SDA. 135 * @note ENABLE: Remap (SCL/PB8, SDA/PB9) 136 * @retval None 137 */ 138 #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) 139 140 /** 141 * @brief Disable the remapping of I2C1 alternate function SCL and SDA. 142 * @note DISABLE: No remap (SCL/PB6, SDA/PB7) 143 * @retval None 144 */ 145 #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) 146 147 /** 148 * @brief Enable the remapping of USART1 alternate function TX and RX. 149 * @note ENABLE: Remap (TX/PB6, RX/PB7) 150 * @retval None 151 */ 152 #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) 153 154 /** 155 * @brief Disable the remapping of USART1 alternate function TX and RX. 156 * @note DISABLE: No remap (TX/PA9, RX/PA10) 157 * @retval None 158 */ 159 #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) 160 161 /** 162 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 163 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) 164 * @retval None 165 */ 166 #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) 167 168 /** 169 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 170 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 171 * @retval None 172 */ 173 #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) 174 175 /** 176 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 177 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) 178 * @retval None 179 */ 180 #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) 181 182 /** 183 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 184 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 185 * @retval None 186 */ 187 #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) 188 189 /** 190 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 191 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 192 * @retval None 193 */ 194 #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) 195 196 /** 197 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 198 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) 199 * @retval None 200 */ 201 #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) 202 203 /** 204 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 205 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 206 * @retval None 207 */ 208 #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) 209 210 /** 211 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 212 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 213 * @retval None 214 */ 215 #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) 216 217 /** 218 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 219 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) 220 * @retval None 221 */ 222 #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) 223 224 /** 225 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 226 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 227 * @retval None 228 */ 229 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) 230 231 /** 232 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 233 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 234 * @retval None 235 */ 236 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) 237 238 /** 239 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 240 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 241 * @retval None 242 */ 243 #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) 244 245 /** 246 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 247 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) 248 * @note TIM3_ETR on PE0 is not re-mapped. 249 * @retval None 250 */ 251 #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) 252 253 /** 254 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 255 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 256 * @note TIM3_ETR on PE0 is not re-mapped. 257 * @retval None 258 */ 259 #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) 260 261 /** 262 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 263 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 264 * @note TIM3_ETR on PE0 is not re-mapped. 265 * @retval None 266 */ 267 #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) 268 269 /** 270 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. 271 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) 272 * @note TIM4_ETR on PE0 is not re-mapped. 273 * @retval None 274 */ 275 #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) 276 277 /** 278 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. 279 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 280 * @note TIM4_ETR on PE0 is not re-mapped. 281 * @retval None 282 */ 283 #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) 284 285 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) 286 287 /** 288 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 289 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 290 * @retval None 291 */ 292 #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) 293 294 /** 295 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 296 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 297 * @retval None 298 */ 299 #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) 300 301 /** 302 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 303 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 304 * @retval None 305 */ 306 #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) 307 308 #endif 309 310 /** 311 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used 312 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 313 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 314 * on 100-pin and 144-pin packages, no need for remapping). 315 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. 316 * @retval None 317 */ 318 #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) 319 320 /** 321 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used 322 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 323 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 324 * on 100-pin and 144-pin packages, no need for remapping). 325 * @note DISABLE: No remapping of PD0 and PD1 326 * @retval None 327 */ 328 #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) 329 330 #if defined(AFIO_MAPR_TIM5CH4_IREMAP) 331 /** 332 * @brief Enable the remapping of TIM5CH4. 333 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. 334 * @note This function is available only in high density value line devices. 335 * @retval None 336 */ 337 #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) 338 339 /** 340 * @brief Disable the remapping of TIM5CH4. 341 * @note DISABLE: TIM5_CH4 is connected to PA3 342 * @note This function is available only in high density value line devices. 343 * @retval None 344 */ 345 #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) 346 #endif 347 348 #if defined(AFIO_MAPR_ETH_REMAP) 349 /** 350 * @brief Enable the remapping of Ethernet MAC connections with the PHY. 351 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) 352 * @note This bit is available only in connectivity line devices and is reserved otherwise. 353 * @retval None 354 */ 355 #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) 356 357 /** 358 * @brief Disable the remapping of Ethernet MAC connections with the PHY. 359 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 360 * @note This bit is available only in connectivity line devices and is reserved otherwise. 361 * @retval None 362 */ 363 #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) 364 #endif 365 366 #if defined(AFIO_MAPR_CAN2_REMAP) 367 368 /** 369 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 370 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) 371 * @note This bit is available only in connectivity line devices and is reserved otherwise. 372 * @retval None 373 */ 374 #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) 375 376 /** 377 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 378 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 379 * @note This bit is available only in connectivity line devices and is reserved otherwise. 380 * @retval None 381 */ 382 #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) 383 #endif 384 385 #if defined(AFIO_MAPR_MII_RMII_SEL) 386 /** 387 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 388 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY 389 * @note This bit is available only in connectivity line devices and is reserved otherwise. 390 * @retval None 391 */ 392 #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) 393 394 /** 395 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 396 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY 397 * @note This bit is available only in connectivity line devices and is reserved otherwise. 398 * @retval None 399 */ 400 #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) 401 #endif 402 403 /** 404 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 405 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. 406 * @retval None 407 */ 408 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) 409 410 /** 411 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 412 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 413 * @retval None 414 */ 415 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) 416 417 /** 418 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 419 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. 420 * @retval None 421 */ 422 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) 423 424 /** 425 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 426 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 427 * @retval None 428 */ 429 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) 430 431 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) 432 433 /** 434 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 435 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. 436 * @retval None 437 */ 438 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) 439 440 /** 441 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 442 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 443 * @retval None 444 */ 445 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) 446 #endif 447 448 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) 449 450 /** 451 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 452 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. 453 * @retval None 454 */ 455 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) 456 457 /** 458 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 459 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 460 * @retval None 461 */ 462 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) 463 #endif 464 465 /** 466 * @brief Enable the Serial wire JTAG configuration 467 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State 468 * @retval None 469 */ 470 #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) 471 472 /** 473 * @brief Enable the Serial wire JTAG configuration 474 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 475 * @retval None 476 */ 477 #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) 478 479 /** 480 * @brief Enable the Serial wire JTAG configuration 481 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled 482 * @retval None 483 */ 484 485 #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) 486 487 /** 488 * @brief Disable the Serial wire JTAG configuration 489 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled 490 * @retval None 491 */ 492 #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) 493 494 #if defined(AFIO_MAPR_SPI3_REMAP) 495 496 /** 497 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 498 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) 499 * @note This bit is available only in connectivity line devices and is reserved otherwise. 500 * @retval None 501 */ 502 #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) 503 504 /** 505 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 506 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). 507 * @note This bit is available only in connectivity line devices and is reserved otherwise. 508 * @retval None 509 */ 510 #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) 511 #endif 512 513 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) 514 515 /** 516 * @brief Control of TIM2_ITR1 internal mapping. 517 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. 518 * @note This bit is available only in connectivity line devices and is reserved otherwise. 519 * @retval None 520 */ 521 #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) 522 523 /** 524 * @brief Control of TIM2_ITR1 internal mapping. 525 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 526 * @note This bit is available only in connectivity line devices and is reserved otherwise. 527 * @retval None 528 */ 529 #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) 530 #endif 531 532 #if defined(AFIO_MAPR_PTP_PPS_REMAP) 533 534 /** 535 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 536 * @note ENABLE: PTP_PPS is output on PB5 pin. 537 * @note This bit is available only in connectivity line devices and is reserved otherwise. 538 * @retval None 539 */ 540 #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) 541 542 /** 543 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 544 * @note DISABLE: PTP_PPS not output on PB5 pin. 545 * @note This bit is available only in connectivity line devices and is reserved otherwise. 546 * @retval None 547 */ 548 #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) 549 #endif 550 551 #if defined(AFIO_MAPR2_TIM9_REMAP) 552 553 /** 554 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. 555 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). 556 * @retval None 557 */ 558 #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) 559 560 /** 561 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. 562 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). 563 * @retval None 564 */ 565 #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) 566 #endif 567 568 #if defined(AFIO_MAPR2_TIM10_REMAP) 569 570 /** 571 * @brief Enable the remapping of TIM10_CH1. 572 * @note ENABLE: Remap (TIM10_CH1 on PF6). 573 * @retval None 574 */ 575 #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) 576 577 /** 578 * @brief Disable the remapping of TIM10_CH1. 579 * @note DISABLE: No remap (TIM10_CH1 on PB8). 580 * @retval None 581 */ 582 #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) 583 #endif 584 585 #if defined(AFIO_MAPR2_TIM11_REMAP) 586 /** 587 * @brief Enable the remapping of TIM11_CH1. 588 * @note ENABLE: Remap (TIM11_CH1 on PF7). 589 * @retval None 590 */ 591 #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) 592 593 /** 594 * @brief Disable the remapping of TIM11_CH1. 595 * @note DISABLE: No remap (TIM11_CH1 on PB9). 596 * @retval None 597 */ 598 #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) 599 #endif 600 601 #if defined(AFIO_MAPR2_TIM13_REMAP) 602 603 /** 604 * @brief Enable the remapping of TIM13_CH1. 605 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). 606 * @retval None 607 */ 608 #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) 609 610 /** 611 * @brief Disable the remapping of TIM13_CH1. 612 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). 613 * @retval None 614 */ 615 #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) 616 #endif 617 618 #if defined(AFIO_MAPR2_TIM14_REMAP) 619 620 /** 621 * @brief Enable the remapping of TIM14_CH1. 622 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). 623 * @retval None 624 */ 625 #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) 626 627 /** 628 * @brief Disable the remapping of TIM14_CH1. 629 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). 630 * @retval None 631 */ 632 #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) 633 #endif 634 635 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) 636 637 /** 638 * @brief Controls the use of the optional FSMC_NADV signal. 639 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. 640 * @retval None 641 */ 642 #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) 643 644 /** 645 * @brief Controls the use of the optional FSMC_NADV signal. 646 * @note CONNECTED: The NADV signal is connected to the output (default). 647 * @retval None 648 */ 649 #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) 650 #endif 651 652 #if defined(AFIO_MAPR2_TIM15_REMAP) 653 654 /** 655 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. 656 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). 657 * @retval None 658 */ 659 #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) 660 661 /** 662 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. 663 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). 664 * @retval None 665 */ 666 #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) 667 #endif 668 669 #if defined(AFIO_MAPR2_TIM16_REMAP) 670 671 /** 672 * @brief Enable the remapping of TIM16_CH1. 673 * @note ENABLE: Remap (TIM16_CH1 on PA6). 674 * @retval None 675 */ 676 #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) 677 678 /** 679 * @brief Disable the remapping of TIM16_CH1. 680 * @note DISABLE: No remap (TIM16_CH1 on PB8). 681 * @retval None 682 */ 683 #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) 684 #endif 685 686 #if defined(AFIO_MAPR2_TIM17_REMAP) 687 688 /** 689 * @brief Enable the remapping of TIM17_CH1. 690 * @note ENABLE: Remap (TIM17_CH1 on PA7). 691 * @retval None 692 */ 693 #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) 694 695 /** 696 * @brief Disable the remapping of TIM17_CH1. 697 * @note DISABLE: No remap (TIM17_CH1 on PB9). 698 * @retval None 699 */ 700 #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) 701 #endif 702 703 #if defined(AFIO_MAPR2_CEC_REMAP) 704 705 /** 706 * @brief Enable the remapping of CEC. 707 * @note ENABLE: Remap (CEC on PB10). 708 * @retval None 709 */ 710 #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) 711 712 /** 713 * @brief Disable the remapping of CEC. 714 * @note DISABLE: No remap (CEC on PB8). 715 * @retval None 716 */ 717 #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) 718 #endif 719 720 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) 721 722 /** 723 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 724 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) 725 * @retval None 726 */ 727 #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) 728 729 /** 730 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 731 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). 732 * @retval None 733 */ 734 #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) 735 #endif 736 737 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) 738 739 /** 740 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 741 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) 742 * @retval None 743 */ 744 #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) 745 746 /** 747 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 748 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) 749 * @retval None 750 */ 751 #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) 752 #endif 753 754 #if defined(AFIO_MAPR2_TIM12_REMAP) 755 756 /** 757 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. 758 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). 759 * @note This bit is available only in high density value line devices. 760 * @retval None 761 */ 762 #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) 763 764 /** 765 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. 766 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). 767 * @note This bit is available only in high density value line devices. 768 * @retval None 769 */ 770 #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) 771 #endif 772 773 #if defined(AFIO_MAPR2_MISC_REMAP) 774 775 /** 776 * @brief Miscellaneous features remapping. 777 * This bit is set and cleared by software. It controls miscellaneous features. 778 * The DMA2 channel 5 interrupt position in the vector table. 779 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 780 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is 781 * selected as DAC Trigger 3, TIM15 triggers TIM1/3. 782 * @note This bit is available only in high density value line devices. 783 * @retval None 784 */ 785 #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) 786 787 /** 788 * @brief Miscellaneous features remapping. 789 * This bit is set and cleared by software. It controls miscellaneous features. 790 * The DMA2 channel 5 interrupt position in the vector table. 791 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 792 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO 793 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. 794 * @note This bit is available only in high density value line devices. 795 * @retval None 796 */ 797 #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) 798 #endif 799 800 /** 801 * @} 802 */ 803 804 /** 805 * @} 806 */ 807 808 /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros 809 * @{ 810 */ 811 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) 812 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ 813 ((__GPIOx__) == (GPIOB))? 1uL :\ 814 ((__GPIOx__) == (GPIOC))? 2uL :3uL) 815 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) 816 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ 817 ((__GPIOx__) == (GPIOB))? 1uL :\ 818 ((__GPIOx__) == (GPIOC))? 2uL :\ 819 ((__GPIOx__) == (GPIOD))? 3uL :4uL) 820 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) 821 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ 822 ((__GPIOx__) == (GPIOB))? 1uL :\ 823 ((__GPIOx__) == (GPIOC))? 2uL :\ 824 ((__GPIOx__) == (GPIOD))? 3uL :\ 825 ((__GPIOx__) == (GPIOE))? 4uL :\ 826 ((__GPIOx__) == (GPIOF))? 5uL :6uL) 827 #endif 828 829 #define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ 830 tmpreg |= AFIO_MAPR_SWJ_CFG; \ 831 tmpreg |= REMAP_PIN; \ 832 AFIO->MAPR = tmpreg; \ 833 }while(0u) 834 835 #define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ 836 tmpreg |= AFIO_MAPR_SWJ_CFG; \ 837 tmpreg &= ~REMAP_PIN; \ 838 AFIO->MAPR = tmpreg; \ 839 }while(0u) 840 841 #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ 842 tmpreg &= ~REMAP_PIN_MASK; \ 843 tmpreg |= AFIO_MAPR_SWJ_CFG; \ 844 tmpreg |= REMAP_PIN; \ 845 AFIO->MAPR = tmpreg; \ 846 }while(0u) 847 848 #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ 849 tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ 850 tmpreg |= DBGAFR_SWJCFG; \ 851 AFIO->MAPR = tmpreg; \ 852 }while(0u) 853 854 /** 855 * @} 856 */ 857 858 /* Exported macro ------------------------------------------------------------*/ 859 /* Exported functions --------------------------------------------------------*/ 860 861 /** @addtogroup GPIOEx_Exported_Functions 862 * @{ 863 */ 864 865 /** @addtogroup GPIOEx_Exported_Functions_Group1 866 * @{ 867 */ 868 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); 869 void HAL_GPIOEx_EnableEventout(void); 870 void HAL_GPIOEx_DisableEventout(void); 871 872 /** 873 * @} 874 */ 875 876 /** 877 * @} 878 */ 879 880 /** 881 * @} 882 */ 883 884 /** 885 * @} 886 */ 887 888 #ifdef __cplusplus 889 } 890 #endif 891 892 #endif /* STM32F1xx_HAL_GPIO_EX_H */ 893 894 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 895
