1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F1xx_HAL_DMA_H 22 #define __STM32F1xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f1xx_hal_def.h" 30 31 /** @addtogroup STM32F1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 51 from memory to memory or from peripheral to memory. 52 This parameter can be a value of @ref DMA_Data_transfer_direction */ 53 54 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 55 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 56 57 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 59 60 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 61 This parameter can be a value of @ref DMA_Peripheral_data_size */ 62 63 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 64 This parameter can be a value of @ref DMA_Memory_data_size */ 65 66 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 67 This parameter can be a value of @ref DMA_mode 68 @note The circular buffer mode cannot be used if the memory-to-memory 69 data transfer is configured on the selected Channel */ 70 71 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 72 This parameter can be a value of @ref DMA_Priority_level */ 73 } DMA_InitTypeDef; 74 75 /** 76 * @brief HAL DMA State structures definition 77 */ 78 typedef enum 79 { 80 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 81 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 82 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 83 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ 84 }HAL_DMA_StateTypeDef; 85 86 /** 87 * @brief HAL DMA Error Code structure definition 88 */ 89 typedef enum 90 { 91 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 92 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 93 }HAL_DMA_LevelCompleteTypeDef; 94 95 /** 96 * @brief HAL DMA Callback ID structure definition 97 */ 98 typedef enum 99 { 100 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 101 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 102 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 103 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 104 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 105 106 }HAL_DMA_CallbackIDTypeDef; 107 108 /** 109 * @brief DMA handle Structure definition 110 */ 111 typedef struct __DMA_HandleTypeDef 112 { 113 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 114 115 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 116 117 HAL_LockTypeDef Lock; /*!< DMA locking object */ 118 119 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 120 121 void *Parent; /*!< Parent object state */ 122 123 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 124 125 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 126 127 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 128 129 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 130 131 __IO uint32_t ErrorCode; /*!< DMA Error code */ 132 133 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 134 135 uint32_t ChannelIndex; /*!< DMA Channel Index */ 136 137 } DMA_HandleTypeDef; 138 /** 139 * @} 140 */ 141 142 /* Exported constants --------------------------------------------------------*/ 143 144 /** @defgroup DMA_Exported_Constants DMA Exported Constants 145 * @{ 146 */ 147 148 /** @defgroup DMA_Error_Code DMA Error Code 149 * @{ 150 */ 151 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 152 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 153 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ 154 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 155 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 161 * @{ 162 */ 163 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 164 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 165 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ 166 167 /** 168 * @} 169 */ 170 171 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 172 * @{ 173 */ 174 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 175 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 176 /** 177 * @} 178 */ 179 180 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 181 * @{ 182 */ 183 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 184 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 185 /** 186 * @} 187 */ 188 189 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 190 * @{ 191 */ 192 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 193 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 194 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 195 /** 196 * @} 197 */ 198 199 /** @defgroup DMA_Memory_data_size DMA Memory data size 200 * @{ 201 */ 202 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 203 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 204 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup DMA_mode DMA mode 210 * @{ 211 */ 212 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 213 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Priority_level DMA Priority level 219 * @{ 220 */ 221 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 222 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 223 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 224 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 225 /** 226 * @} 227 */ 228 229 230 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 231 * @{ 232 */ 233 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 234 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 235 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 236 /** 237 * @} 238 */ 239 240 /** @defgroup DMA_flag_definitions DMA flag definitions 241 * @{ 242 */ 243 #define DMA_FLAG_GL1 0x00000001U 244 #define DMA_FLAG_TC1 0x00000002U 245 #define DMA_FLAG_HT1 0x00000004U 246 #define DMA_FLAG_TE1 0x00000008U 247 #define DMA_FLAG_GL2 0x00000010U 248 #define DMA_FLAG_TC2 0x00000020U 249 #define DMA_FLAG_HT2 0x00000040U 250 #define DMA_FLAG_TE2 0x00000080U 251 #define DMA_FLAG_GL3 0x00000100U 252 #define DMA_FLAG_TC3 0x00000200U 253 #define DMA_FLAG_HT3 0x00000400U 254 #define DMA_FLAG_TE3 0x00000800U 255 #define DMA_FLAG_GL4 0x00001000U 256 #define DMA_FLAG_TC4 0x00002000U 257 #define DMA_FLAG_HT4 0x00004000U 258 #define DMA_FLAG_TE4 0x00008000U 259 #define DMA_FLAG_GL5 0x00010000U 260 #define DMA_FLAG_TC5 0x00020000U 261 #define DMA_FLAG_HT5 0x00040000U 262 #define DMA_FLAG_TE5 0x00080000U 263 #define DMA_FLAG_GL6 0x00100000U 264 #define DMA_FLAG_TC6 0x00200000U 265 #define DMA_FLAG_HT6 0x00400000U 266 #define DMA_FLAG_TE6 0x00800000U 267 #define DMA_FLAG_GL7 0x01000000U 268 #define DMA_FLAG_TC7 0x02000000U 269 #define DMA_FLAG_HT7 0x04000000U 270 #define DMA_FLAG_TE7 0x08000000U 271 /** 272 * @} 273 */ 274 275 /** 276 * @} 277 */ 278 279 280 /* Exported macros -----------------------------------------------------------*/ 281 /** @defgroup DMA_Exported_Macros DMA Exported Macros 282 * @{ 283 */ 284 285 /** @brief Reset DMA handle state. 286 * @param __HANDLE__: DMA handle 287 * @retval None 288 */ 289 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 290 291 /** 292 * @brief Enable the specified DMA Channel. 293 * @param __HANDLE__: DMA handle 294 * @retval None 295 */ 296 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 297 298 /** 299 * @brief Disable the specified DMA Channel. 300 * @param __HANDLE__: DMA handle 301 * @retval None 302 */ 303 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 304 305 306 /* Interrupt & Flag management */ 307 308 /** 309 * @brief Enables the specified DMA Channel interrupts. 310 * @param __HANDLE__: DMA handle 311 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 312 * This parameter can be any combination of the following values: 313 * @arg DMA_IT_TC: Transfer complete interrupt mask 314 * @arg DMA_IT_HT: Half transfer complete interrupt mask 315 * @arg DMA_IT_TE: Transfer error interrupt mask 316 * @retval None 317 */ 318 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) 319 320 /** 321 * @brief Disable the specified DMA Channel interrupts. 322 * @param __HANDLE__: DMA handle 323 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 324 * This parameter can be any combination of the following values: 325 * @arg DMA_IT_TC: Transfer complete interrupt mask 326 * @arg DMA_IT_HT: Half transfer complete interrupt mask 327 * @arg DMA_IT_TE: Transfer error interrupt mask 328 * @retval None 329 */ 330 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) 331 332 /** 333 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 334 * @param __HANDLE__: DMA handle 335 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 336 * This parameter can be one of the following values: 337 * @arg DMA_IT_TC: Transfer complete interrupt mask 338 * @arg DMA_IT_HT: Half transfer complete interrupt mask 339 * @arg DMA_IT_TE: Transfer error interrupt mask 340 * @retval The state of DMA_IT (SET or RESET). 341 */ 342 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 343 344 /** 345 * @brief Return the number of remaining data units in the current DMA Channel transfer. 346 * @param __HANDLE__: DMA handle 347 * @retval The number of remaining data units in the current DMA Channel transfer. 348 */ 349 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 350 351 /** 352 * @} 353 */ 354 355 /* Include DMA HAL Extension module */ 356 #include "stm32f1xx_hal_dma_ex.h" 357 358 /* Exported functions --------------------------------------------------------*/ 359 /** @addtogroup DMA_Exported_Functions 360 * @{ 361 */ 362 363 /** @addtogroup DMA_Exported_Functions_Group1 364 * @{ 365 */ 366 /* Initialization and de-initialization functions *****************************/ 367 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 368 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 369 /** 370 * @} 371 */ 372 373 /** @addtogroup DMA_Exported_Functions_Group2 374 * @{ 375 */ 376 /* IO operation functions *****************************************************/ 377 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 378 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 379 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 380 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 381 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 382 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 383 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 384 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 385 386 /** 387 * @} 388 */ 389 390 /** @addtogroup DMA_Exported_Functions_Group3 391 * @{ 392 */ 393 /* Peripheral State and Error functions ***************************************/ 394 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 395 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 396 /** 397 * @} 398 */ 399 400 /** 401 * @} 402 */ 403 404 /* Private macros ------------------------------------------------------------*/ 405 /** @defgroup DMA_Private_Macros DMA Private Macros 406 * @{ 407 */ 408 409 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 410 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 411 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 412 413 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 414 415 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 416 ((STATE) == DMA_PINC_DISABLE)) 417 418 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 419 ((STATE) == DMA_MINC_DISABLE)) 420 421 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 422 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 423 ((SIZE) == DMA_PDATAALIGN_WORD)) 424 425 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 426 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 427 ((SIZE) == DMA_MDATAALIGN_WORD )) 428 429 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 430 ((MODE) == DMA_CIRCULAR)) 431 432 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 433 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 434 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 435 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 436 437 /** 438 * @} 439 */ 440 441 /* Private functions ---------------------------------------------------------*/ 442 443 /** 444 * @} 445 */ 446 447 /** 448 * @} 449 */ 450 451 #ifdef __cplusplus 452 } 453 #endif 454 455 #endif /* __STM32F1xx_HAL_DMA_H */ 456 457 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 458
