1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F0xx_LL_DAC_H
22 #define __STM32F0xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f0xx.h"
30
31 /** @addtogroup STM32F0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DAC1)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into register CR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
60 #if defined(DAC_CHANNEL2_SUPPORT)
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63 #else
64 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
65 #endif /* DAC_CHANNEL2_SUPPORT */
66
67 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
68 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
69 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
70 #if defined(DAC_CHANNEL2_SUPPORT)
71 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
72 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
73 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
74 #endif /* DAC_CHANNEL2_SUPPORT */
75 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
76 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
77 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
78 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
79
80 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
81 #if defined(DAC_CHANNEL2_SUPPORT)
82 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
83 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
84 #else
85 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
86 #endif /* DAC_CHANNEL2_SUPPORT */
87
88 #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
89
90 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
91 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
92 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
93 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
94
95 /* DAC registers bits positions */
96 #if defined(DAC_CHANNEL2_SUPPORT)
97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
100 #endif /* DAC_CHANNEL2_SUPPORT */
101
102 /* Miscellaneous data */
103 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
104
105 /**
106 * @}
107 */
108
109
110 /* Private macros ------------------------------------------------------------*/
111 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
112 * @{
113 */
114
115 /**
116 * @brief Driver macro reserved for internal use: set a pointer to
117 * a register from a register basis from which an offset
118 * is applied.
119 * @param __REG__ Register basis from which the offset is applied.
120 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
121 * @retval Pointer to register address
122 */
123 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
124 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
125
126 /**
127 * @}
128 */
129
130
131 /* Exported types ------------------------------------------------------------*/
132 #if defined(USE_FULL_LL_DRIVER)
133 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
134 * @{
135 */
136
137 /**
138 * @brief Structure definition of some features of DAC instance.
139 */
140 typedef struct
141 {
142 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
143 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
144
145 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
146
147 #if defined(DAC_CR_WAVE1)
148 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
149 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
150
151 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
152
153 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
154 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
155 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
156 @note If waveform automatic generation mode is disabled, this parameter is discarded.
157
158 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
159 #endif
160
161 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
162 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
163
164 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
165
166 } LL_DAC_InitTypeDef;
167
168 /**
169 * @}
170 */
171 #endif /* USE_FULL_LL_DRIVER */
172
173 /* Exported constants --------------------------------------------------------*/
174 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
175 * @{
176 */
177
178 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
179 * @brief Flags defines which can be used with LL_DAC_ReadReg function
180 * @{
181 */
182 /* DAC channel 1 flags */
183 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
184
185 #if defined(DAC_CHANNEL2_SUPPORT)
186 /* DAC channel 2 flags */
187 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
188 #endif /* DAC_CHANNEL2_SUPPORT */
189 /**
190 * @}
191 */
192
193 /** @defgroup DAC_LL_EC_IT DAC interruptions
194 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
195 * @{
196 */
197 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
198 #if defined(DAC_CHANNEL2_SUPPORT)
199 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
200 #endif /* DAC_CHANNEL2_SUPPORT */
201 /**
202 * @}
203 */
204
205 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
206 * @{
207 */
208 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
209 #if defined(DAC_CHANNEL2_SUPPORT)
210 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
211 #endif /* DAC_CHANNEL2_SUPPORT */
212 /**
213 * @}
214 */
215
216 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
217 * @{
218 */
219 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
220 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
221 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
222 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
223 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
224 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
225 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
226 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
227 /**
228 * @}
229 */
230
231 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
232 * @{
233 */
234 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
235 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
236 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
237 /**
238 * @}
239 */
240
241 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
242 * @{
243 */
244 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
245 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
254 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
255 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
256 /**
257 * @}
258 */
259
260 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
261 * @{
262 */
263 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
264 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
265 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
266 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
267 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
268 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
269 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
270 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
271 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
272 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
273 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
274 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
275 /**
276 * @}
277 */
278
279 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
280 * @{
281 */
282 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
283 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
284 /**
285 * @}
286 */
287
288
289 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
290 * @{
291 */
292 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
293 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
294 /**
295 * @}
296 */
297
298 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
299 * @{
300 */
301 /* List of DAC registers intended to be used (most commonly) with */
302 /* DMA transfer. */
303 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
304 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
305 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
306 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
307 /**
308 * @}
309 */
310
311 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
312 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
313 * not timeout values.
314 * For details on delays values, refer to descriptions in source code
315 * above each literal definition.
316 * @{
317 */
318
319 /* Delay for DAC channel voltage settling time from DAC channel startup */
320 /* (transition from disable to enable). */
321 /* Note: DAC channel startup time depends on board application environment: */
322 /* impedance connected to DAC channel output. */
323 /* The delay below is specified under conditions: */
324 /* - voltage maximum transition (lowest to highest value) */
325 /* - until voltage reaches final value +-1LSB */
326 /* - DAC channel output buffer enabled */
327 /* - load impedance of 5kOhm (min), 50pF (max) */
328 /* Literal set to maximum value (refer to device datasheet, */
329 /* parameter "tWAKEUP"). */
330 /* Unit: us */
331 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
332
333 /* Delay for DAC channel voltage settling time. */
334 /* Note: DAC channel startup time depends on board application environment: */
335 /* impedance connected to DAC channel output. */
336 /* The delay below is specified under conditions: */
337 /* - voltage maximum transition (lowest to highest value) */
338 /* - until voltage reaches final value +-1LSB */
339 /* - DAC channel output buffer enabled */
340 /* - load impedance of 5kOhm min, 50pF max */
341 /* Literal set to maximum value (refer to device datasheet, */
342 /* parameter "tSETTLING"). */
343 /* Unit: us */
344 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
345 /**
346 * @}
347 */
348
349 /**
350 * @}
351 */
352
353 /* Exported macro ------------------------------------------------------------*/
354 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
355 * @{
356 */
357
358 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
359 * @{
360 */
361
362 /**
363 * @brief Write a value in DAC register
364 * @param __INSTANCE__ DAC Instance
365 * @param __REG__ Register to be written
366 * @param __VALUE__ Value to be written in the register
367 * @retval None
368 */
369 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
370
371 /**
372 * @brief Read a value in DAC register
373 * @param __INSTANCE__ DAC Instance
374 * @param __REG__ Register to be read
375 * @retval Register value
376 */
377 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
378
379 /**
380 * @}
381 */
382
383 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
384 * @{
385 */
386
387 /**
388 * @brief Helper macro to get DAC channel number in decimal format
389 * from literals LL_DAC_CHANNEL_x.
390 * Example:
391 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
392 * will return decimal number "1".
393 * @note The input can be a value from functions where a channel
394 * number is returned.
395 * @param __CHANNEL__ This parameter can be one of the following values:
396 * @arg @ref LL_DAC_CHANNEL_1
397 * @arg @ref LL_DAC_CHANNEL_2 (1)
398 *
399 * (1) On this STM32 serie, parameter not available on all devices.
400 * Refer to device datasheet for channels availability.
401 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
402 */
403 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
404 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
405
406 /**
407 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
408 * from number in decimal format.
409 * Example:
410 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
411 * will return a data equivalent to "LL_DAC_CHANNEL_1".
412 * @note If the input parameter does not correspond to a DAC channel,
413 * this macro returns value '0'.
414 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
415 * @retval Returned value can be one of the following values:
416 * @arg @ref LL_DAC_CHANNEL_1
417 * @arg @ref LL_DAC_CHANNEL_2 (1)
418 *
419 * (1) On this STM32 serie, parameter not available on all devices.
420 * Refer to device datasheet for channels availability.
421 */
422 #if defined(DAC_CHANNEL2_SUPPORT)
423 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
424 (((__DECIMAL_NB__) == 1U) \
425 ? ( \
426 LL_DAC_CHANNEL_1 \
427 ) \
428 : \
429 (((__DECIMAL_NB__) == 2U) \
430 ? ( \
431 LL_DAC_CHANNEL_2 \
432 ) \
433 : \
434 ( \
435 0 \
436 ) \
437 ) \
438 )
439 #else
440 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
441 (((__DECIMAL_NB__) == 1U) \
442 ? ( \
443 LL_DAC_CHANNEL_1 \
444 ) \
445 : \
446 ( \
447 0 \
448 ) \
449 )
450 #endif /* DAC_CHANNEL2_SUPPORT */
451
452 /**
453 * @brief Helper macro to define the DAC conversion data full-scale digital
454 * value corresponding to the selected DAC resolution.
455 * @note DAC conversion data full-scale corresponds to voltage range
456 * determined by analog voltage references Vref+ and Vref-
457 * (refer to reference manual).
458 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
459 * @arg @ref LL_DAC_RESOLUTION_12B
460 * @arg @ref LL_DAC_RESOLUTION_8B
461 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
462 */
463 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
464 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
465
466 /**
467 * @brief Helper macro to calculate the DAC conversion data (unit: digital
468 * value) corresponding to a voltage (unit: mVolt).
469 * @note This helper macro is intended to provide input data in voltage
470 * rather than digital value,
471 * to be used with LL DAC functions such as
472 * @ref LL_DAC_ConvertData12RightAligned().
473 * @note Analog reference voltage (Vref+) must be either known from
474 * user board environment or can be calculated using ADC measurement
475 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
476 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
477 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
478 * (unit: mVolt).
479 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
480 * @arg @ref LL_DAC_RESOLUTION_12B
481 * @arg @ref LL_DAC_RESOLUTION_8B
482 * @retval DAC conversion data (unit: digital value)
483 */
484 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
485 __DAC_VOLTAGE__,\
486 __DAC_RESOLUTION__) \
487 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
488 / (__VREFANALOG_VOLTAGE__) \
489 )
490
491 /**
492 * @}
493 */
494
495 /**
496 * @}
497 */
498
499
500 /* Exported functions --------------------------------------------------------*/
501 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
502 * @{
503 */
504 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
505 * @{
506 */
507
508 /**
509 * @brief Set the conversion trigger source for the selected DAC channel.
510 * @note For conversion trigger source to be effective, DAC trigger
511 * must be enabled using function @ref LL_DAC_EnableTrigger().
512 * @note To set conversion trigger source, DAC channel must be disabled.
513 * Otherwise, the setting is discarded.
514 * @note Availability of parameters of trigger sources from timer
515 * depends on timers availability on the selected device.
516 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
517 * CR TSEL2 LL_DAC_SetTriggerSource
518 * @param DACx DAC instance
519 * @param DAC_Channel This parameter can be one of the following values:
520 * @arg @ref LL_DAC_CHANNEL_1
521 * @arg @ref LL_DAC_CHANNEL_2 (1)
522 *
523 * (1) On this STM32 serie, parameter not available on all devices.
524 * Refer to device datasheet for channels availability.
525 * @param TriggerSource This parameter can be one of the following values:
526 * @arg @ref LL_DAC_TRIG_SOFTWARE
527 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
528 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
529 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
530 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
531 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
532 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
533 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
534 * @retval None
535 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)536 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
537 {
538 MODIFY_REG(DACx->CR,
539 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
540 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
541 }
542
543 /**
544 * @brief Get the conversion trigger source for the selected DAC channel.
545 * @note For conversion trigger source to be effective, DAC trigger
546 * must be enabled using function @ref LL_DAC_EnableTrigger().
547 * @note Availability of parameters of trigger sources from timer
548 * depends on timers availability on the selected device.
549 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
550 * CR TSEL2 LL_DAC_GetTriggerSource
551 * @param DACx DAC instance
552 * @param DAC_Channel This parameter can be one of the following values:
553 * @arg @ref LL_DAC_CHANNEL_1
554 * @arg @ref LL_DAC_CHANNEL_2 (1)
555 *
556 * (1) On this STM32 serie, parameter not available on all devices.
557 * Refer to device datasheet for channels availability.
558 * @retval Returned value can be one of the following values:
559 * @arg @ref LL_DAC_TRIG_SOFTWARE
560 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
561 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
563 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
564 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
565 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
566 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
567 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)568 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
569 {
570 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
571 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
572 );
573 }
574
575 #if defined(DAC_CR_WAVE1)
576 /**
577 * @brief Set the waveform automatic generation mode
578 * for the selected DAC channel.
579 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
580 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
581 * @param DACx DAC instance
582 * @param DAC_Channel This parameter can be one of the following values:
583 * @arg @ref LL_DAC_CHANNEL_1
584 * @arg @ref LL_DAC_CHANNEL_2 (1)
585 *
586 * (1) On this STM32 serie, parameter not available on all devices.
587 * Refer to device datasheet for channels availability.
588 * @param WaveAutoGeneration This parameter can be one of the following values:
589 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
590 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
591 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
592 * @retval None
593 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)594 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
595 {
596 MODIFY_REG(DACx->CR,
597 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
598 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
599 }
600
601 /**
602 * @brief Get the waveform automatic generation mode
603 * for the selected DAC channel.
604 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
605 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
606 * @param DACx DAC instance
607 * @param DAC_Channel This parameter can be one of the following values:
608 * @arg @ref LL_DAC_CHANNEL_1
609 * @arg @ref LL_DAC_CHANNEL_2 (1)
610 *
611 * (1) On this STM32 serie, parameter not available on all devices.
612 * Refer to device datasheet for channels availability.
613 * @retval Returned value can be one of the following values:
614 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
615 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
616 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
617 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)618 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
619 {
620 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
621 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
622 );
623 }
624
625 /**
626 * @brief Set the noise waveform generation for the selected DAC channel:
627 * Noise mode and parameters LFSR (linear feedback shift register).
628 * @note For wave generation to be effective, DAC channel
629 * wave generation mode must be enabled using
630 * function @ref LL_DAC_SetWaveAutoGeneration().
631 * @note This setting can be set when the selected DAC channel is disabled
632 * (otherwise, the setting operation is ignored).
633 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
634 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
635 * @param DACx DAC instance
636 * @param DAC_Channel This parameter can be one of the following values:
637 * @arg @ref LL_DAC_CHANNEL_1
638 * @arg @ref LL_DAC_CHANNEL_2 (1)
639 *
640 * (1) On this STM32 serie, parameter not available on all devices.
641 * Refer to device datasheet for channels availability.
642 * @param NoiseLFSRMask This parameter can be one of the following values:
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
654 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
655 * @retval None
656 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)657 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
658 {
659 MODIFY_REG(DACx->CR,
660 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
661 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
662 }
663
664 /**
665 * @brief Set the noise waveform generation for the selected DAC channel:
666 * Noise mode and parameters LFSR (linear feedback shift register).
667 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
668 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
669 * @param DACx DAC instance
670 * @param DAC_Channel This parameter can be one of the following values:
671 * @arg @ref LL_DAC_CHANNEL_1
672 * @arg @ref LL_DAC_CHANNEL_2 (1)
673 *
674 * (1) On this STM32 serie, parameter not available on all devices.
675 * Refer to device datasheet for channels availability.
676 * @retval Returned value can be one of the following values:
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
684 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
685 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
686 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
687 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
688 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
689 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)690 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
691 {
692 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
693 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
694 );
695 }
696
697 /**
698 * @brief Set the triangle waveform generation for the selected DAC channel:
699 * triangle mode and amplitude.
700 * @note For wave generation to be effective, DAC channel
701 * wave generation mode must be enabled using
702 * function @ref LL_DAC_SetWaveAutoGeneration().
703 * @note This setting can be set when the selected DAC channel is disabled
704 * (otherwise, the setting operation is ignored).
705 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
706 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
707 * @param DACx DAC instance
708 * @param DAC_Channel This parameter can be one of the following values:
709 * @arg @ref LL_DAC_CHANNEL_1
710 * @arg @ref LL_DAC_CHANNEL_2 (1)
711 *
712 * (1) On this STM32 serie, parameter not available on all devices.
713 * Refer to device datasheet for channels availability.
714 * @param TriangleAmplitude This parameter can be one of the following values:
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
725 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
726 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
727 * @retval None
728 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)729 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
730 {
731 MODIFY_REG(DACx->CR,
732 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
733 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
734 }
735
736 /**
737 * @brief Set the triangle waveform generation for the selected DAC channel:
738 * triangle mode and amplitude.
739 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
740 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
741 * @param DACx DAC instance
742 * @param DAC_Channel This parameter can be one of the following values:
743 * @arg @ref LL_DAC_CHANNEL_1
744 * @arg @ref LL_DAC_CHANNEL_2 (1)
745 *
746 * (1) On this STM32 serie, parameter not available on all devices.
747 * Refer to device datasheet for channels availability.
748 * @retval Returned value can be one of the following values:
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
756 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
757 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
758 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
759 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
760 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
761 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)762 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
763 {
764 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
765 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
766 );
767 }
768 #endif
769
770 /**
771 * @brief Set the output buffer for the selected DAC channel.
772 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
773 * CR BOFF2 LL_DAC_SetOutputBuffer
774 * @param DACx DAC instance
775 * @param DAC_Channel This parameter can be one of the following values:
776 * @arg @ref LL_DAC_CHANNEL_1
777 * @arg @ref LL_DAC_CHANNEL_2 (1)
778 *
779 * (1) On this STM32 serie, parameter not available on all devices.
780 * Refer to device datasheet for channels availability.
781 * @param OutputBuffer This parameter can be one of the following values:
782 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
783 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
784 * @retval None
785 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)786 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
787 {
788 MODIFY_REG(DACx->CR,
789 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
790 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
791 }
792
793 /**
794 * @brief Get the output buffer state for the selected DAC channel.
795 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
796 * CR BOFF2 LL_DAC_GetOutputBuffer
797 * @param DACx DAC instance
798 * @param DAC_Channel This parameter can be one of the following values:
799 * @arg @ref LL_DAC_CHANNEL_1
800 * @arg @ref LL_DAC_CHANNEL_2 (1)
801 *
802 * (1) On this STM32 serie, parameter not available on all devices.
803 * Refer to device datasheet for channels availability.
804 * @retval Returned value can be one of the following values:
805 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
806 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
807 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)808 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
809 {
810 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
811 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
812 );
813 }
814
815 /**
816 * @}
817 */
818
819 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
820 * @{
821 */
822
823 /**
824 * @brief Enable DAC DMA transfer request of the selected channel.
825 * @note To configure DMA source address (peripheral address),
826 * use function @ref LL_DAC_DMA_GetRegAddr().
827 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
828 * CR DMAEN2 LL_DAC_EnableDMAReq
829 * @param DACx DAC instance
830 * @param DAC_Channel This parameter can be one of the following values:
831 * @arg @ref LL_DAC_CHANNEL_1
832 * @arg @ref LL_DAC_CHANNEL_2 (1)
833 *
834 * (1) On this STM32 serie, parameter not available on all devices.
835 * Refer to device datasheet for channels availability.
836 * @retval None
837 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)838 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
839 {
840 SET_BIT(DACx->CR,
841 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
842 }
843
844 /**
845 * @brief Disable DAC DMA transfer request of the selected channel.
846 * @note To configure DMA source address (peripheral address),
847 * use function @ref LL_DAC_DMA_GetRegAddr().
848 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
849 * CR DMAEN2 LL_DAC_DisableDMAReq
850 * @param DACx DAC instance
851 * @param DAC_Channel This parameter can be one of the following values:
852 * @arg @ref LL_DAC_CHANNEL_1
853 * @arg @ref LL_DAC_CHANNEL_2 (1)
854 *
855 * (1) On this STM32 serie, parameter not available on all devices.
856 * Refer to device datasheet for channels availability.
857 * @retval None
858 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)859 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
860 {
861 CLEAR_BIT(DACx->CR,
862 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
863 }
864
865 /**
866 * @brief Get DAC DMA transfer request state of the selected channel.
867 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
868 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
869 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
870 * @param DACx DAC instance
871 * @param DAC_Channel This parameter can be one of the following values:
872 * @arg @ref LL_DAC_CHANNEL_1
873 * @arg @ref LL_DAC_CHANNEL_2 (1)
874 *
875 * (1) On this STM32 serie, parameter not available on all devices.
876 * Refer to device datasheet for channels availability.
877 * @retval State of bit (1 or 0).
878 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)879 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
880 {
881 return (READ_BIT(DACx->CR,
882 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
883 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
884 }
885
886 /**
887 * @brief Function to help to configure DMA transfer to DAC: retrieve the
888 * DAC register address from DAC instance and a list of DAC registers
889 * intended to be used (most commonly) with DMA transfer.
890 * @note These DAC registers are data holding registers:
891 * when DAC conversion is requested, DAC generates a DMA transfer
892 * request to have data available in DAC data holding registers.
893 * @note This macro is intended to be used with LL DMA driver, refer to
894 * function "LL_DMA_ConfigAddresses()".
895 * Example:
896 * LL_DMA_ConfigAddresses(DMA1,
897 * LL_DMA_CHANNEL_1,
898 * (uint32_t)&< array or variable >,
899 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
900 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
901 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
902 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
903 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
904 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
905 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
906 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
907 * @param DACx DAC instance
908 * @param DAC_Channel This parameter can be one of the following values:
909 * @arg @ref LL_DAC_CHANNEL_1
910 * @arg @ref LL_DAC_CHANNEL_2 (1)
911 *
912 * (1) On this STM32 serie, parameter not available on all devices.
913 * Refer to device datasheet for channels availability.
914 * @param Register This parameter can be one of the following values:
915 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
916 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
917 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
918 * @retval DAC register address
919 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)920 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
921 {
922 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
923 /* DAC channel selected. */
924 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
925 }
926 /**
927 * @}
928 */
929
930 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
931 * @{
932 */
933
934 /**
935 * @brief Enable DAC selected channel.
936 * @rmtoll CR EN1 LL_DAC_Enable\n
937 * CR EN2 LL_DAC_Enable
938 * @note After enable from off state, DAC channel requires a delay
939 * for output voltage to reach accuracy +/- 1 LSB.
940 * Refer to device datasheet, parameter "tWAKEUP".
941 * @param DACx DAC instance
942 * @param DAC_Channel This parameter can be one of the following values:
943 * @arg @ref LL_DAC_CHANNEL_1
944 * @arg @ref LL_DAC_CHANNEL_2 (1)
945 *
946 * (1) On this STM32 serie, parameter not available on all devices.
947 * Refer to device datasheet for channels availability.
948 * @retval None
949 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)950 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
951 {
952 SET_BIT(DACx->CR,
953 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
954 }
955
956 /**
957 * @brief Disable DAC selected channel.
958 * @rmtoll CR EN1 LL_DAC_Disable\n
959 * CR EN2 LL_DAC_Disable
960 * @param DACx DAC instance
961 * @param DAC_Channel This parameter can be one of the following values:
962 * @arg @ref LL_DAC_CHANNEL_1
963 * @arg @ref LL_DAC_CHANNEL_2 (1)
964 *
965 * (1) On this STM32 serie, parameter not available on all devices.
966 * Refer to device datasheet for channels availability.
967 * @retval None
968 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)969 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
970 {
971 CLEAR_BIT(DACx->CR,
972 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
973 }
974
975 /**
976 * @brief Get DAC enable state of the selected channel.
977 * (0: DAC channel is disabled, 1: DAC channel is enabled)
978 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
979 * CR EN2 LL_DAC_IsEnabled
980 * @param DACx DAC instance
981 * @param DAC_Channel This parameter can be one of the following values:
982 * @arg @ref LL_DAC_CHANNEL_1
983 * @arg @ref LL_DAC_CHANNEL_2 (1)
984 *
985 * (1) On this STM32 serie, parameter not available on all devices.
986 * Refer to device datasheet for channels availability.
987 * @retval State of bit (1 or 0).
988 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)989 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
990 {
991 return (READ_BIT(DACx->CR,
992 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
993 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
994 }
995
996 /**
997 * @brief Enable DAC trigger of the selected channel.
998 * @note - If DAC trigger is disabled, DAC conversion is performed
999 * automatically once the data holding register is updated,
1000 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1001 * @ref LL_DAC_ConvertData12RightAligned(), ...
1002 * - If DAC trigger is enabled, DAC conversion is performed
1003 * only when a hardware of software trigger event is occurring.
1004 * Select trigger source using
1005 * function @ref LL_DAC_SetTriggerSource().
1006 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1007 * CR TEN2 LL_DAC_EnableTrigger
1008 * @param DACx DAC instance
1009 * @param DAC_Channel This parameter can be one of the following values:
1010 * @arg @ref LL_DAC_CHANNEL_1
1011 * @arg @ref LL_DAC_CHANNEL_2 (1)
1012 *
1013 * (1) On this STM32 serie, parameter not available on all devices.
1014 * Refer to device datasheet for channels availability.
1015 * @retval None
1016 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1017 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1018 {
1019 SET_BIT(DACx->CR,
1020 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1021 }
1022
1023 /**
1024 * @brief Disable DAC trigger of the selected channel.
1025 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1026 * CR TEN2 LL_DAC_DisableTrigger
1027 * @param DACx DAC instance
1028 * @param DAC_Channel This parameter can be one of the following values:
1029 * @arg @ref LL_DAC_CHANNEL_1
1030 * @arg @ref LL_DAC_CHANNEL_2 (1)
1031 *
1032 * (1) On this STM32 serie, parameter not available on all devices.
1033 * Refer to device datasheet for channels availability.
1034 * @retval None
1035 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1036 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1037 {
1038 CLEAR_BIT(DACx->CR,
1039 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1040 }
1041
1042 /**
1043 * @brief Get DAC trigger state of the selected channel.
1044 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1045 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1046 * CR TEN2 LL_DAC_IsTriggerEnabled
1047 * @param DACx DAC instance
1048 * @param DAC_Channel This parameter can be one of the following values:
1049 * @arg @ref LL_DAC_CHANNEL_1
1050 * @arg @ref LL_DAC_CHANNEL_2 (1)
1051 *
1052 * (1) On this STM32 serie, parameter not available on all devices.
1053 * Refer to device datasheet for channels availability.
1054 * @retval State of bit (1 or 0).
1055 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1056 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1057 {
1058 return (READ_BIT(DACx->CR,
1059 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1060 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1061 }
1062
1063 /**
1064 * @brief Trig DAC conversion by software for the selected DAC channel.
1065 * @note Preliminarily, DAC trigger must be set to software trigger
1066 * using function @ref LL_DAC_SetTriggerSource()
1067 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1068 * and DAC trigger must be enabled using
1069 * function @ref LL_DAC_EnableTrigger().
1070 * @note For devices featuring DAC with 2 channels: this function
1071 * can perform a SW start of both DAC channels simultaneously.
1072 * Two channels can be selected as parameter.
1073 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1074 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1075 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1076 * @param DACx DAC instance
1077 * @param DAC_Channel This parameter can a combination of the following values:
1078 * @arg @ref LL_DAC_CHANNEL_1
1079 * @arg @ref LL_DAC_CHANNEL_2 (1)
1080 *
1081 * (1) On this STM32 serie, parameter not available on all devices.
1082 * Refer to device datasheet for channels availability.
1083 * @retval None
1084 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1085 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1086 {
1087 SET_BIT(DACx->SWTRIGR,
1088 (DAC_Channel & DAC_SWTR_CHX_MASK));
1089 }
1090
1091 /**
1092 * @brief Set the data to be loaded in the data holding register
1093 * in format 12 bits left alignment (LSB aligned on bit 0),
1094 * for the selected DAC channel.
1095 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1096 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1097 * @param DACx DAC instance
1098 * @param DAC_Channel This parameter can be one of the following values:
1099 * @arg @ref LL_DAC_CHANNEL_1
1100 * @arg @ref LL_DAC_CHANNEL_2 (1)
1101 *
1102 * (1) On this STM32 serie, parameter not available on all devices.
1103 * Refer to device datasheet for channels availability.
1104 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1105 * @retval None
1106 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1107 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1108 {
1109 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1110
1111 MODIFY_REG(*preg,
1112 DAC_DHR12R1_DACC1DHR,
1113 Data);
1114 }
1115
1116 /**
1117 * @brief Set the data to be loaded in the data holding register
1118 * in format 12 bits left alignment (MSB aligned on bit 15),
1119 * for the selected DAC channel.
1120 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1121 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1122 * @param DACx DAC instance
1123 * @param DAC_Channel This parameter can be one of the following values:
1124 * @arg @ref LL_DAC_CHANNEL_1
1125 * @arg @ref LL_DAC_CHANNEL_2 (1)
1126 *
1127 * (1) On this STM32 serie, parameter not available on all devices.
1128 * Refer to device datasheet for channels availability.
1129 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1130 * @retval None
1131 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1132 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1133 {
1134 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1135
1136 MODIFY_REG(*preg,
1137 DAC_DHR12L1_DACC1DHR,
1138 Data);
1139 }
1140
1141 /**
1142 * @brief Set the data to be loaded in the data holding register
1143 * in format 8 bits left alignment (LSB aligned on bit 0),
1144 * for the selected DAC channel.
1145 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1146 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1147 * @param DACx DAC instance
1148 * @param DAC_Channel This parameter can be one of the following values:
1149 * @arg @ref LL_DAC_CHANNEL_1
1150 * @arg @ref LL_DAC_CHANNEL_2 (1)
1151 *
1152 * (1) On this STM32 serie, parameter not available on all devices.
1153 * Refer to device datasheet for channels availability.
1154 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1155 * @retval None
1156 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1157 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1158 {
1159 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1160
1161 MODIFY_REG(*preg,
1162 DAC_DHR8R1_DACC1DHR,
1163 Data);
1164 }
1165
1166 #if defined(DAC_CHANNEL2_SUPPORT)
1167 /**
1168 * @brief Set the data to be loaded in the data holding register
1169 * in format 12 bits left alignment (LSB aligned on bit 0),
1170 * for both DAC channels.
1171 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1172 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1173 * @param DACx DAC instance
1174 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1175 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1176 * @retval None
1177 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1178 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1179 {
1180 MODIFY_REG(DACx->DHR12RD,
1181 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1182 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1183 }
1184
1185 /**
1186 * @brief Set the data to be loaded in the data holding register
1187 * in format 12 bits left alignment (MSB aligned on bit 15),
1188 * for both DAC channels.
1189 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1190 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1191 * @param DACx DAC instance
1192 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1193 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1194 * @retval None
1195 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1196 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1197 {
1198 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1199 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1200 /* the 4 LSB must be taken into account for the shift value. */
1201 MODIFY_REG(DACx->DHR12LD,
1202 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1203 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1204 }
1205
1206 /**
1207 * @brief Set the data to be loaded in the data holding register
1208 * in format 8 bits left alignment (LSB aligned on bit 0),
1209 * for both DAC channels.
1210 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1211 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1212 * @param DACx DAC instance
1213 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1214 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1215 * @retval None
1216 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1217 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1218 {
1219 MODIFY_REG(DACx->DHR8RD,
1220 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1221 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1222 }
1223
1224 #endif /* DAC_CHANNEL2_SUPPORT */
1225 /**
1226 * @brief Retrieve output data currently generated for the selected DAC channel.
1227 * @note Whatever alignment and resolution settings
1228 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1229 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1230 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1231 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1232 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1233 * @param DACx DAC instance
1234 * @param DAC_Channel This parameter can be one of the following values:
1235 * @arg @ref LL_DAC_CHANNEL_1
1236 * @arg @ref LL_DAC_CHANNEL_2 (1)
1237 *
1238 * (1) On this STM32 serie, parameter not available on all devices.
1239 * Refer to device datasheet for channels availability.
1240 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1241 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1242 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1243 {
1244 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1245
1246 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1247 }
1248
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1254 * @{
1255 */
1256 /**
1257 * @brief Get DAC underrun flag for DAC channel 1
1258 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1259 * @param DACx DAC instance
1260 * @retval State of bit (1 or 0).
1261 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1262 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1263 {
1264 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1265 }
1266
1267 #if defined(DAC_CHANNEL2_SUPPORT)
1268 /**
1269 * @brief Get DAC underrun flag for DAC channel 2
1270 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1271 * @param DACx DAC instance
1272 * @retval State of bit (1 or 0).
1273 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1274 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1275 {
1276 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1277 }
1278 #endif /* DAC_CHANNEL2_SUPPORT */
1279
1280 /**
1281 * @brief Clear DAC underrun flag for DAC channel 1
1282 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1283 * @param DACx DAC instance
1284 * @retval None
1285 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1286 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1287 {
1288 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1289 }
1290
1291 #if defined(DAC_CHANNEL2_SUPPORT)
1292 /**
1293 * @brief Clear DAC underrun flag for DAC channel 2
1294 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1295 * @param DACx DAC instance
1296 * @retval None
1297 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1298 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1299 {
1300 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1301 }
1302 #endif /* DAC_CHANNEL2_SUPPORT */
1303
1304 /**
1305 * @}
1306 */
1307
1308 /** @defgroup DAC_LL_EF_IT_Management IT management
1309 * @{
1310 */
1311
1312 /**
1313 * @brief Enable DMA underrun interrupt for DAC channel 1
1314 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1315 * @param DACx DAC instance
1316 * @retval None
1317 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1318 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1319 {
1320 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1321 }
1322
1323 #if defined(DAC_CHANNEL2_SUPPORT)
1324 /**
1325 * @brief Enable DMA underrun interrupt for DAC channel 2
1326 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1327 * @param DACx DAC instance
1328 * @retval None
1329 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1330 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1331 {
1332 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1333 }
1334 #endif /* DAC_CHANNEL2_SUPPORT */
1335
1336 /**
1337 * @brief Disable DMA underrun interrupt for DAC channel 1
1338 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1339 * @param DACx DAC instance
1340 * @retval None
1341 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1342 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1343 {
1344 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1345 }
1346
1347 #if defined(DAC_CHANNEL2_SUPPORT)
1348 /**
1349 * @brief Disable DMA underrun interrupt for DAC channel 2
1350 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1351 * @param DACx DAC instance
1352 * @retval None
1353 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1354 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1355 {
1356 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1357 }
1358 #endif /* DAC_CHANNEL2_SUPPORT */
1359
1360 /**
1361 * @brief Get DMA underrun interrupt for DAC channel 1
1362 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1363 * @param DACx DAC instance
1364 * @retval State of bit (1 or 0).
1365 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1366 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1367 {
1368 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1369 }
1370
1371 #if defined(DAC_CHANNEL2_SUPPORT)
1372 /**
1373 * @brief Get DMA underrun interrupt for DAC channel 2
1374 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1375 * @param DACx DAC instance
1376 * @retval State of bit (1 or 0).
1377 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1378 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1379 {
1380 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1381 }
1382 #endif /* DAC_CHANNEL2_SUPPORT */
1383
1384 /**
1385 * @}
1386 */
1387
1388 #if defined(USE_FULL_LL_DRIVER)
1389 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1390 * @{
1391 */
1392
1393 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1394 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1395 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1396
1397 /**
1398 * @}
1399 */
1400 #endif /* USE_FULL_LL_DRIVER */
1401
1402 /**
1403 * @}
1404 */
1405
1406 /**
1407 * @}
1408 */
1409
1410 #endif /* DAC1 */
1411
1412 /**
1413 * @}
1414 */
1415
1416 #ifdef __cplusplus
1417 }
1418 #endif
1419
1420 #endif /* __STM32F0xx_LL_DAC_H */
1421
1422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1423
