1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32F0xx_HAL_TSC_H 22 #define STM32F0xx_HAL_TSC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f0xx_hal_def.h" 30 31 #if defined(TSC) 32 33 /** @addtogroup STM32F0xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup TSC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup TSC_Exported_Types TSC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief TSC state structure definition 48 */ 49 typedef enum 50 { 51 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 52 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 53 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 54 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 55 } HAL_TSC_StateTypeDef; 56 57 /** 58 * @brief TSC group status structure definition 59 */ 60 typedef enum 61 { 62 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 63 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 64 } TSC_GroupStatusTypeDef; 65 66 /** 67 * @brief TSC init structure definition 68 */ 69 typedef struct 70 { 71 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 72 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 73 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 74 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 75 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 76 This parameter can be set to ENABLE or DISABLE. */ 77 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 78 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 79 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 80 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 81 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 82 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 83 uint32_t MaxCountValue; /*!< Max count value 84 This parameter can be a value of @ref TSC_MaxCount_Value */ 85 uint32_t IODefaultMode; /*!< IO default mode 86 This parameter can be a value of @ref TSC_IO_Default_Mode */ 87 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 88 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 89 uint32_t AcquisitionMode; /*!< Acquisition mode 90 This parameter can be a value of @ref TSC_Acquisition_Mode */ 91 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 92 This parameter can be set to ENABLE or DISABLE. */ 93 uint32_t ChannelIOs; /*!< Channel IOs mask */ 94 uint32_t ShieldIOs; /*!< Shield IOs mask */ 95 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 96 } TSC_InitTypeDef; 97 98 /** 99 * @brief TSC IOs configuration structure definition 100 */ 101 typedef struct 102 { 103 uint32_t ChannelIOs; /*!< Channel IOs mask */ 104 uint32_t ShieldIOs; /*!< Shield IOs mask */ 105 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 106 } TSC_IOConfigTypeDef; 107 108 /** 109 * @brief TSC handle Structure definition 110 */ 111 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 112 typedef struct __TSC_HandleTypeDef 113 #else 114 typedef struct 115 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 116 { 117 TSC_TypeDef *Instance; /*!< Register base address */ 118 TSC_InitTypeDef Init; /*!< Initialization parameters */ 119 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 120 HAL_LockTypeDef Lock; /*!< Lock feature */ 121 __IO uint32_t ErrorCode; /*!< TSC Error code */ 122 123 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 124 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 125 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 126 127 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 128 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 129 130 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 131 } TSC_HandleTypeDef; 132 133 enum 134 { 135 TSC_GROUP1_IDX = 0x00UL, 136 TSC_GROUP2_IDX, 137 TSC_GROUP3_IDX, 138 TSC_GROUP4_IDX, 139 TSC_GROUP5_IDX, 140 TSC_GROUP6_IDX, 141 TSC_GROUP7_IDX, 142 TSC_GROUP8_IDX, 143 TSC_NB_OF_GROUPS 144 }; 145 146 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 147 /** 148 * @brief HAL TSC Callback ID enumeration definition 149 */ 150 typedef enum 151 { 152 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 153 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 154 155 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 156 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 157 158 } HAL_TSC_CallbackIDTypeDef; 159 160 /** 161 * @brief HAL TSC Callback pointer definition 162 */ 163 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 164 165 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 166 167 /** 168 * @} 169 */ 170 171 /* Exported constants --------------------------------------------------------*/ 172 /** @defgroup TSC_Exported_Constants TSC Exported Constants 173 * @{ 174 */ 175 176 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 177 * @brief TSC Error Code definition 178 * @{ 179 */ 180 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 181 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 182 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 183 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 189 * @{ 190 */ 191 #define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 192 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 193 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 194 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 195 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 196 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 197 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 198 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 199 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 200 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 201 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 202 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 203 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 204 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 205 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 206 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 212 * @{ 213 */ 214 #define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 215 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 216 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 217 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 218 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 219 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 220 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 221 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 222 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 223 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 224 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 225 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 226 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 227 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 228 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 229 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 235 * @{ 236 */ 237 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 238 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 244 * @{ 245 */ 246 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 247 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 248 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 249 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 250 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 251 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 252 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 253 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 254 /** 255 * @} 256 */ 257 258 /** @defgroup TSC_MaxCount_Value Max Count Value 259 * @{ 260 */ 261 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 262 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 263 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 264 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 265 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 266 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 267 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup TSC_IO_Default_Mode IO Default Mode 273 * @{ 274 */ 275 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 276 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 282 * @{ 283 */ 284 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 285 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 291 * @{ 292 */ 293 #define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 294 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup TSC_interrupts_definition Interrupts definition 300 * @{ 301 */ 302 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 303 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 304 /** 305 * @} 306 */ 307 308 /** @defgroup TSC_flags_definition Flags definition 309 * @{ 310 */ 311 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 312 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup TSC_Group_definition Group definition 318 * @{ 319 */ 320 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 321 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 322 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 323 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 324 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 325 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 326 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 327 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 328 329 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 330 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 331 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 332 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 333 334 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 335 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 336 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 337 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 338 339 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 340 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 341 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 342 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 343 344 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 345 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 346 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 347 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 348 349 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 350 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 351 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 352 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 353 354 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 355 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 356 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 357 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 358 359 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 360 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 361 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 362 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 363 364 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 365 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 366 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 367 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 368 /** 369 * @} 370 */ 371 372 /** 373 * @} 374 */ 375 376 /* Exported macros -----------------------------------------------------------*/ 377 378 /** @defgroup TSC_Exported_Macros TSC Exported Macros 379 * @{ 380 */ 381 382 /** @brief Reset TSC handle state. 383 * @param __HANDLE__ TSC handle 384 * @retval None 385 */ 386 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 387 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 388 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 389 (__HANDLE__)->MspInitCallback = NULL; \ 390 (__HANDLE__)->MspDeInitCallback = NULL; \ 391 } while(0) 392 #else 393 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 394 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 395 396 /** 397 * @brief Enable the TSC peripheral. 398 * @param __HANDLE__ TSC handle 399 * @retval None 400 */ 401 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 402 403 /** 404 * @brief Disable the TSC peripheral. 405 * @param __HANDLE__ TSC handle 406 * @retval None 407 */ 408 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 409 410 /** 411 * @brief Start acquisition. 412 * @param __HANDLE__ TSC handle 413 * @retval None 414 */ 415 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 416 417 /** 418 * @brief Stop acquisition. 419 * @param __HANDLE__ TSC handle 420 * @retval None 421 */ 422 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 423 424 /** 425 * @brief Set IO default mode to output push-pull low. 426 * @param __HANDLE__ TSC handle 427 * @retval None 428 */ 429 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 430 431 /** 432 * @brief Set IO default mode to input floating. 433 * @param __HANDLE__ TSC handle 434 * @retval None 435 */ 436 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 437 438 /** 439 * @brief Set synchronization polarity to falling edge. 440 * @param __HANDLE__ TSC handle 441 * @retval None 442 */ 443 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 444 445 /** 446 * @brief Set synchronization polarity to rising edge and high level. 447 * @param __HANDLE__ TSC handle 448 * @retval None 449 */ 450 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 451 452 /** 453 * @brief Enable TSC interrupt. 454 * @param __HANDLE__ TSC handle 455 * @param __INTERRUPT__ TSC interrupt 456 * @retval None 457 */ 458 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 459 460 /** 461 * @brief Disable TSC interrupt. 462 * @param __HANDLE__ TSC handle 463 * @param __INTERRUPT__ TSC interrupt 464 * @retval None 465 */ 466 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 467 468 /** @brief Check whether the specified TSC interrupt source is enabled or not. 469 * @param __HANDLE__ TSC Handle 470 * @param __INTERRUPT__ TSC interrupt 471 * @retval SET or RESET 472 */ 473 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 474 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 475 RESET) 476 477 /** 478 * @brief Check whether the specified TSC flag is set or not. 479 * @param __HANDLE__ TSC handle 480 * @param __FLAG__ TSC flag 481 * @retval SET or RESET 482 */ 483 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 484 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 485 486 /** 487 * @brief Clear the TSC's pending flag. 488 * @param __HANDLE__ TSC handle 489 * @param __FLAG__ TSC flag 490 * @retval None 491 */ 492 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 493 494 /** 495 * @brief Enable schmitt trigger hysteresis on a group of IOs. 496 * @param __HANDLE__ TSC handle 497 * @param __GX_IOY_MASK__ IOs mask 498 * @retval None 499 */ 500 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 501 502 /** 503 * @brief Disable schmitt trigger hysteresis on a group of IOs. 504 * @param __HANDLE__ TSC handle 505 * @param __GX_IOY_MASK__ IOs mask 506 * @retval None 507 */ 508 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 509 &= (~(__GX_IOY_MASK__))) 510 511 /** 512 * @brief Open analog switch on a group of IOs. 513 * @param __HANDLE__ TSC handle 514 * @param __GX_IOY_MASK__ IOs mask 515 * @retval None 516 */ 517 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 518 &= (~(__GX_IOY_MASK__))) 519 520 /** 521 * @brief Close analog switch on a group of IOs. 522 * @param __HANDLE__ TSC handle 523 * @param __GX_IOY_MASK__ IOs mask 524 * @retval None 525 */ 526 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 527 528 /** 529 * @brief Enable a group of IOs in channel mode. 530 * @param __HANDLE__ TSC handle 531 * @param __GX_IOY_MASK__ IOs mask 532 * @retval None 533 */ 534 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 535 536 /** 537 * @brief Disable a group of channel IOs. 538 * @param __HANDLE__ TSC handle 539 * @param __GX_IOY_MASK__ IOs mask 540 * @retval None 541 */ 542 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 543 &= (~(__GX_IOY_MASK__))) 544 545 /** 546 * @brief Enable a group of IOs in sampling mode. 547 * @param __HANDLE__ TSC handle 548 * @param __GX_IOY_MASK__ IOs mask 549 * @retval None 550 */ 551 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 552 553 /** 554 * @brief Disable a group of sampling IOs. 555 * @param __HANDLE__ TSC handle 556 * @param __GX_IOY_MASK__ IOs mask 557 * @retval None 558 */ 559 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 560 561 /** 562 * @brief Enable acquisition groups. 563 * @param __HANDLE__ TSC handle 564 * @param __GX_MASK__ Groups mask 565 * @retval None 566 */ 567 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 568 569 /** 570 * @brief Disable acquisition groups. 571 * @param __HANDLE__ TSC handle 572 * @param __GX_MASK__ Groups mask 573 * @retval None 574 */ 575 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 576 577 /** @brief Gets acquisition group status. 578 * @param __HANDLE__ TSC Handle 579 * @param __GX_INDEX__ Group index 580 * @retval SET or RESET 581 */ 582 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 583 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 584 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 585 586 /** 587 * @} 588 */ 589 590 /* Private macros ------------------------------------------------------------*/ 591 592 /** @defgroup TSC_Private_Macros TSC Private Macros 593 * @{ 594 */ 595 596 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 597 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 598 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 599 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 600 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 601 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 602 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 603 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 604 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 605 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 606 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 607 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 608 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 609 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 610 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 611 ((__VALUE__) == TSC_CTPH_16CYCLES)) 612 613 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 614 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 615 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 616 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 617 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 618 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 619 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 620 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 621 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 622 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 623 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 624 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 625 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 626 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 627 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 628 ((__VALUE__) == TSC_CTPL_16CYCLES)) 629 630 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 631 || ((FunctionalState)(__VALUE__) == ENABLE)) 632 633 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 634 635 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 636 637 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 638 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 639 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 640 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 641 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 642 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 643 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 644 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 645 646 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 647 ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ 648 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 649 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 650 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 651 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 652 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 653 654 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 655 ((__VALUE__) == TSC_MCV_511) || \ 656 ((__VALUE__) == TSC_MCV_1023) || \ 657 ((__VALUE__) == TSC_MCV_2047) || \ 658 ((__VALUE__) == TSC_MCV_4095) || \ 659 ((__VALUE__) == TSC_MCV_8191) || \ 660 ((__VALUE__) == TSC_MCV_16383)) 661 662 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 663 664 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 665 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 666 667 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 668 669 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 670 || ((FunctionalState)(__VALUE__) == ENABLE)) 671 672 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 673 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 674 675 #define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ 676 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 677 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 678 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 679 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 680 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 681 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 682 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 683 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 684 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 685 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 686 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 687 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 688 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 689 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 690 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 691 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 692 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 693 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 694 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 695 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 696 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 697 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 698 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 699 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 700 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 701 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 702 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 703 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 704 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 705 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 706 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 707 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4)) 708 /** 709 * @} 710 */ 711 712 /* Exported functions --------------------------------------------------------*/ 713 /** @addtogroup TSC_Exported_Functions 714 * @{ 715 */ 716 717 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 718 * @{ 719 */ 720 /* Initialization and de-initialization functions *****************************/ 721 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 722 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 723 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 724 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 725 726 /* Callbacks Register/UnRegister functions ***********************************/ 727 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 728 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 729 pTSC_CallbackTypeDef pCallback); 730 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 731 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 732 /** 733 * @} 734 */ 735 736 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 737 * @{ 738 */ 739 /* IO operation functions *****************************************************/ 740 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 741 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 742 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 743 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 744 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 745 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 746 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 747 /** 748 * @} 749 */ 750 751 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 752 * @{ 753 */ 754 /* Peripheral Control functions ***********************************************/ 755 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 756 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 757 /** 758 * @} 759 */ 760 761 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 762 * @{ 763 */ 764 /* Peripheral State and Error functions ***************************************/ 765 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 766 /** 767 * @} 768 */ 769 770 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 771 * @{ 772 */ 773 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 774 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 775 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 776 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 785 /** 786 * @} 787 */ 788 789 /** 790 * @} 791 */ 792 #endif /* TSC */ 793 794 #ifdef __cplusplus 795 } 796 #endif 797 798 #endif /* STM32F0xx_HAL_TSC_H */ 799 800 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 801
