1 /*
2 ******************************************************************************
3 * @file st1vafe3bx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ST1VAFE3BX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "st1vafe3bx_reg.h"
21
22 /**
23 * @defgroup ST1VAFE3BX
24 * @brief This file provides a set of functions needed to drive the
25 * st1vafe3bx sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ST1VAFE3BX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
st1vafe3bx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak st1vafe3bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data, uint16_t len)
51 {
52 if (ctx == NULL)
53 {
54 return -1;
55 }
56
57 return ctx->read_reg(ctx->handle, reg, data, len);
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
st1vafe3bx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak st1vafe3bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data, uint16_t len)
72 {
73 if (ctx == NULL)
74 {
75 return -1;
76 }
77
78 return ctx->write_reg(ctx->handle, reg, data, len);
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup ST1VAFE3BX_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
st1vafe3bx_from_fs2g_to_mg(int16_t lsb)93 float_t st1vafe3bx_from_fs2g_to_mg(int16_t lsb)
94 {
95 return (float_t)lsb * 0.061f;
96 }
97
st1vafe3bx_from_fs4g_to_mg(int16_t lsb)98 float_t st1vafe3bx_from_fs4g_to_mg(int16_t lsb)
99 {
100 return (float_t)lsb * 0.122f;
101 }
102
st1vafe3bx_from_fs8g_to_mg(int16_t lsb)103 float_t st1vafe3bx_from_fs8g_to_mg(int16_t lsb)
104 {
105 return (float_t)lsb * 0.244f;
106 }
107
st1vafe3bx_from_fs16g_to_mg(int16_t lsb)108 float_t st1vafe3bx_from_fs16g_to_mg(int16_t lsb)
109 {
110 return (float_t)lsb * 0.488f;
111 }
112
st1vafe3bx_from_lsb_to_mv(int16_t lsb)113 float_t st1vafe3bx_from_lsb_to_mv(int16_t lsb)
114 {
115 return ((float_t)lsb) / 1311.0f;
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup Common
125 * @brief Common
126 * @{/
127 *
128 */
129 /**
130 * @brief Device ID.[get]
131 *
132 * @param ctx read / write interface definitions
133 * @param val Device ID.
134 * @retval interface status (MANDATORY: return 0 -> no Error)
135 *
136 */
st1vafe3bx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)137 int32_t st1vafe3bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
138 {
139 int32_t ret;
140
141 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WHO_AM_I, val, 1);
142
143 return ret;
144 }
145
146 /**
147 * @brief Configures the bus operating mode.[get]
148 *
149 * @param ctx communication interface handler.(ptr)
150 * @param val configures the bus operating mode.(ptr)
151 * @retval interface status (MANDATORY: return 0 -> no Error)
152 *
153 */
st1vafe3bx_init_set(const stmdev_ctx_t * ctx,st1vafe3bx_init_t val)154 int32_t st1vafe3bx_init_set(const stmdev_ctx_t *ctx, st1vafe3bx_init_t val)
155 {
156 st1vafe3bx_ctrl1_t ctrl1;
157 st1vafe3bx_ctrl4_t ctrl4;
158 st1vafe3bx_status_t status;
159 st1vafe3bx_ctrl3_t ctrl3;
160 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
161 st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3;
162 uint8_t cnt = 0;
163 uint8_t ret;
164
165 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
166 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
167 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
168 (uint8_t *)&ah_bio_cfg2, 1);
169 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
170 (uint8_t *)&ah_bio_cfg3, 1);
171 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
172
173 switch (val)
174 {
175 case ST1VAFE3BX_BOOT:
176 ctrl4.boot = PROPERTY_ENABLE;
177 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
178 if (ret != 0)
179 {
180 break;
181 }
182
183 do
184 {
185 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
186 if (ret != 0)
187 {
188 break;
189 }
190
191 /* boot procedure ended correctly */
192 if (ctrl4.boot == 0U)
193 {
194 break;
195 }
196
197 if (ctx->mdelay != NULL)
198 {
199 ctx->mdelay(25); /* 25 ms of boot time */
200 }
201 } while (cnt++ < 5U);
202
203 if (cnt >= 5U)
204 {
205 ret = -1; /* boot procedure failed */
206 }
207 break;
208 case ST1VAFE3BX_RESET:
209 ctrl1.sw_reset = PROPERTY_ENABLE;
210 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
211 if (ret != 0)
212 {
213 break;
214 }
215
216 do
217 {
218 ret = st1vafe3bx_status_get(ctx, &status);
219 if (ret != 0)
220 {
221 break;
222 }
223
224 /* sw-reset procedure ended correctly */
225 if (status.sw_reset == 0U)
226 {
227 break;
228 }
229
230 if (ctx->mdelay != NULL)
231 {
232 ctx->mdelay(1); /* should be 50 us */
233 }
234 } while (cnt++ < 5U);
235
236 if (cnt >= 5U)
237 {
238 ret = -1; /* sw-reset procedure failed */
239 }
240 break;
241 case ST1VAFE3BX_SENSOR_ONLY_ON:
242 /* no embedded funcs are used */
243 ctrl4.emb_func_en = PROPERTY_DISABLE;
244 ctrl4.bdu = PROPERTY_ENABLE;
245 ctrl1.if_add_inc = PROPERTY_ENABLE;
246 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
247 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
248 break;
249 case ST1VAFE3BX_SENSOR_EMB_FUNC_ON:
250 /* complete configuration is used */
251 ctrl4.emb_func_en = PROPERTY_ENABLE;
252 ctrl4.bdu = PROPERTY_ENABLE;
253 ctrl1.if_add_inc = PROPERTY_ENABLE;
254 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
255 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
256 break;
257 case ST1VAFE3BX_VAFE_ONLY_LP:
258 case ST1VAFE3BX_VAFE_ONLY_HP:
259 /*
260 * when the device is in the AH / vAFE only state, the embedded low power
261 * features are not available
262 */
263 ctrl4.bdu = PROPERTY_ENABLE;
264 ctrl1.if_add_inc = PROPERTY_ENABLE;
265 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
266 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
267
268 ah_bio_cfg2.ah_bio_en = PROPERTY_ENABLE;
269 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
270 (uint8_t *)&ah_bio_cfg2, 1);
271
272 ah_bio_cfg3.ah_bio_active = PROPERTY_ENABLE;
273 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
274 (uint8_t *)&ah_bio_cfg3, 1);
275
276 if (ctx->mdelay != NULL)
277 {
278 ctx->mdelay(10);
279 }
280
281 if (val == ST1VAFE3BX_VAFE_ONLY_HP)
282 {
283 ctrl3.hp_en = PROPERTY_ENABLE;
284 }
285 else
286 {
287 ctrl3.hp_en = PROPERTY_DISABLE;
288 }
289
290 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
291
292 ah_bio_cfg3.ah_bio_active = PROPERTY_DISABLE;
293 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
294 (uint8_t *)&ah_bio_cfg3, 1);
295
296 if (ctx->mdelay != NULL)
297 {
298 ctx->mdelay(10);
299 }
300 break;
301 default:
302 ctrl1.sw_reset = PROPERTY_ENABLE;
303 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
304 break;
305 }
306
307 return ret;
308 }
309
310 /**
311 * @brief Smart mode configuration.[set]
312 *
313 * @param ctx read / write interface definitions
314 * @param val st1vafe3bx_smart_power_t (pwr_en, pwr_win, pwr_dur)
315 * @retval interface status (MANDATORY: return 0 -> no Error)
316 *
317 */
st1vafe3bx_smart_power_set(const stmdev_ctx_t * ctx,st1vafe3bx_smart_power_t val)318 int32_t st1vafe3bx_smart_power_set(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t val)
319 {
320 st1vafe3bx_ctrl1_t ctrl1;
321 st1vafe3bx_smart_power_ctrl_t pwr_ctrl;
322 int32_t ret;
323
324 /* Configure smart power */
325 pwr_ctrl.smart_power_ctrl_win = val.pwr_ctrl_win;
326 pwr_ctrl.smart_power_ctrl_dur = val.pwr_ctrl_dur;
327 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_SMART_POWER_CTRL, (uint8_t *)&pwr_ctrl, 1);
328
329 /* Enable smart power */
330 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
331
332 if (ret == 0)
333 {
334 ctrl1.smart_power_en = val.pwr_en;
335 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
336 }
337
338 return ret;
339 }
340
341 /**
342 * @brief Smart mode configuration.[get]
343 *
344 * @param ctx read / write interface definitions
345 * @param val st1vafe3bx_smart_power_t (pwr_en, pwr_win, pwr_dur)
346 * @retval interface status (MANDATORY: return 0 -> no Error)
347 *
348 */
st1vafe3bx_smart_power_get(const stmdev_ctx_t * ctx,st1vafe3bx_smart_power_t * val)349 int32_t st1vafe3bx_smart_power_get(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t *val)
350 {
351 st1vafe3bx_ctrl1_t ctrl1;
352 st1vafe3bx_smart_power_ctrl_t pwr_ctrl;
353 int32_t ret;
354
355 /* Read smart power configuration */
356 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
357 ret += st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_SMART_POWER_CTRL, (uint8_t *)&pwr_ctrl, 1);
358
359 if (ret == 0)
360 {
361 val->pwr_en = ctrl1.smart_power_en;
362 val->pwr_ctrl_win = pwr_ctrl.smart_power_ctrl_win;
363 val->pwr_ctrl_dur = pwr_ctrl.smart_power_ctrl_dur;
364 }
365
366 return ret;
367 }
368
369 /**
370 * @brief Get the status of the device.[get]
371 *
372 * @param ctx communication interface handler.(ptr)
373 * @param val the status of the device.(ptr)
374 * @retval interface status (MANDATORY: return 0 -> no Error)
375 *
376 */
st1vafe3bx_status_get(const stmdev_ctx_t * ctx,st1vafe3bx_status_t * val)377 int32_t st1vafe3bx_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val)
378 {
379 st1vafe3bx_status_register_t status_register;
380 st1vafe3bx_ctrl1_t ctrl1;
381 st1vafe3bx_ctrl4_t ctrl4;
382 int32_t ret;
383
384 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STATUS,
385 (uint8_t *)&status_register, 1);
386 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
387 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
388
389 val->sw_reset = ctrl1.sw_reset;
390 val->boot = ctrl4.boot;
391 val->drdy = status_register.drdy;
392
393 return ret;
394 }
395
396 /**
397 * @brief Get drdy status flag of the device.[get]
398 *
399 * @param ctx communication interface handler.(ptr)
400 * @param val the drdy status flag of the device .(ptr)
401 * @retval interface status (MANDATORY: return 0 -> no Error)
402 *
403 */
st1vafe3bx_drdy_status_get(const stmdev_ctx_t * ctx,st1vafe3bx_status_t * val)404 int32_t st1vafe3bx_drdy_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val)
405 {
406 st1vafe3bx_status_register_t status_register;
407 int32_t ret;
408
409 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STATUS, (uint8_t *)&status_register, 1);
410 val->drdy = status_register.drdy;
411
412 return ret;
413 }
414
415 /**
416 * @brief Get the status of the embedded funcs.[get]
417 *
418 * @param ctx communication interface handler.(ptr)
419 * @param val the status of the embedded funcs.(ptr)
420 * @retval interface status (MANDATORY: return 0 -> no Error)
421 *
422 */
st1vafe3bx_embedded_status_get(const stmdev_ctx_t * ctx,st1vafe3bx_embedded_status_t * val)423 int32_t st1vafe3bx_embedded_status_get(const stmdev_ctx_t *ctx,
424 st1vafe3bx_embedded_status_t *val)
425 {
426 st1vafe3bx_emb_func_status_t status;
427 int32_t ret;
428
429 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
430 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_STATUS,
431 (uint8_t *)&status, 1);
432 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
433
434 val->is_step_det = status.is_step_det;
435 val->is_tilt = status.is_tilt;
436 val->is_sigmot = status.is_sigmot;
437 val->is_fsm_lc = status.is_fsm_lc;
438
439 return ret;
440 }
441
442 /**
443 * @brief Enables pulsed data-ready mode (~75 us).[set]
444 *
445 * @param ctx read / write interface definitions
446 * @param val DRDY_LATCHED, DRDY_PULSED,
447 * @retval interface status (MANDATORY: return 0 -> no Error)
448 *
449 */
st1vafe3bx_data_ready_mode_set(const stmdev_ctx_t * ctx,st1vafe3bx_data_ready_mode_t val)450 int32_t st1vafe3bx_data_ready_mode_set(const stmdev_ctx_t *ctx,
451 st1vafe3bx_data_ready_mode_t val)
452 {
453 st1vafe3bx_ctrl1_t ctrl1;
454 int32_t ret;
455
456 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
457
458 if (ret == 0)
459 {
460 ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U);
461 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
462 }
463
464 return ret;
465 }
466
467 /**
468 * @brief Enables pulsed data-ready mode (~75 us).[get]
469 *
470 * @param ctx read / write interface definitions
471 * @param val DRDY_LATCHED, DRDY_PULSED,
472 * @retval interface status (MANDATORY: return 0 -> no Error)
473 *
474 */
st1vafe3bx_data_ready_mode_get(const stmdev_ctx_t * ctx,st1vafe3bx_data_ready_mode_t * val)475 int32_t st1vafe3bx_data_ready_mode_get(const stmdev_ctx_t *ctx,
476 st1vafe3bx_data_ready_mode_t *val)
477 {
478 st1vafe3bx_ctrl1_t ctrl1;
479 int32_t ret;
480
481 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
482
483 switch ((ctrl1.drdy_pulsed))
484 {
485 case ST1VAFE3BX_DRDY_LATCHED:
486 *val = ST1VAFE3BX_DRDY_LATCHED;
487 break;
488
489 case ST1VAFE3BX_DRDY_PULSED:
490 *val = ST1VAFE3BX_DRDY_PULSED;
491 break;
492
493 default:
494 *val = ST1VAFE3BX_DRDY_LATCHED;
495 break;
496 }
497 return ret;
498 }
499
500 /**
501 * @brief Sensor mode.[set]
502 *
503 * @param ctx communication interface handler.(ptr)
504 * @param val set the sensor FS and ODR.(ptr)
505 * @retval interface status (MANDATORY: return 0 -> no Error)
506 *
507 */
st1vafe3bx_mode_set(const stmdev_ctx_t * ctx,const st1vafe3bx_md_t * val)508 int32_t st1vafe3bx_mode_set(const stmdev_ctx_t *ctx, const st1vafe3bx_md_t *val)
509 {
510 st1vafe3bx_ctrl3_t ctrl3;
511 st1vafe3bx_ctrl5_t ctrl5;
512 int32_t ret;
513
514 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1);
515 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
516
517 ctrl5.odr = (uint8_t)val->odr & 0xFU;
518 ctrl5.fs = (uint8_t)val->fs;
519
520 /* select high performance mode */
521 switch (val->odr & 0x30U)
522 {
523 case 0x30U:
524 case 0x10U:
525 /* high performance mode */
526 ctrl3.hp_en = 1U;
527 break;
528 case 0x00U:
529 case 0x20U:
530 default:
531 /* low power mode */
532 ctrl3.hp_en = 0U;
533 break;
534 }
535
536 /* set the bandwidth */
537 switch (val->odr)
538 {
539 /* no anti-aliasing filter present */
540 default:
541 case ST1VAFE3BX_OFF:
542 case ST1VAFE3BX_1Hz6_ULP:
543 case ST1VAFE3BX_3Hz_ULP:
544 case ST1VAFE3BX_25Hz_ULP:
545 ctrl5.bw = 0x0;
546 break;
547
548 /* low-power mode with ODR < 50 Hz */
549 case ST1VAFE3BX_6Hz_LP:
550 case ST1VAFE3BX_12Hz5_LP:
551 case ST1VAFE3BX_25Hz_LP:
552 switch (val->bw)
553 {
554 default:
555 /* value not allowed */
556 ret = -1;
557 break;
558 case ST1VAFE3BX_BW_LP_12Hz5:
559 ctrl5.bw = 0x1;
560 break;
561 case ST1VAFE3BX_BW_LP_6Hz:
562 ctrl5.bw = 0x2;
563 break;
564 case ST1VAFE3BX_BW_LP_3Hz:
565 ctrl5.bw = 0x3;
566 break;
567 }
568 break;
569
570 /* High Performance cases */
571 case ST1VAFE3BX_800Hz_VAFE_HP:
572 case ST1VAFE3BX_3200Hz_VAFE_LP:
573 case ST1VAFE3BX_50Hz_LP:
574 case ST1VAFE3BX_100Hz_LP:
575 case ST1VAFE3BX_200Hz_LP:
576 case ST1VAFE3BX_400Hz_LP:
577 case ST1VAFE3BX_800Hz_LP:
578 case ST1VAFE3BX_TRIG_PIN:
579 case ST1VAFE3BX_TRIG_SW:
580 case ST1VAFE3BX_6Hz_HP:
581 case ST1VAFE3BX_12Hz5_HP:
582 case ST1VAFE3BX_25Hz_HP:
583 case ST1VAFE3BX_50Hz_HP:
584 case ST1VAFE3BX_100Hz_HP:
585 case ST1VAFE3BX_200Hz_HP:
586 case ST1VAFE3BX_400Hz_HP:
587 case ST1VAFE3BX_800Hz_HP:
588 ctrl5.bw = (uint8_t)val->bw;
589 break;
590 }
591
592 if (ret == 0)
593 {
594 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1);
595 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
596 }
597
598 return ret;
599 }
600
601 /**
602 * @brief Sensor mode.[get]
603 *
604 * @param ctx communication interface handler.(ptr)
605 * @param val get the sensor FS and ODR.(ptr)
606 * @retval interface status (MANDATORY: return 0 -> no Error)
607 *
608 */
st1vafe3bx_mode_get(const stmdev_ctx_t * ctx,st1vafe3bx_md_t * val)609 int32_t st1vafe3bx_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_md_t *val)
610 {
611 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
612 st1vafe3bx_ctrl3_t ctrl3;
613 st1vafe3bx_ctrl5_t ctrl5;
614 int32_t ret;
615
616 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL5, (uint8_t *)&ctrl5, 1);
617 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
618 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&ah_bio_cfg2, 1);
619
620 val->hp_en = ctrl3.hp_en;
621
622 switch (ctrl5.odr)
623 {
624 case 0x00:
625 val->odr = ST1VAFE3BX_OFF;
626 break;
627 case 0x01:
628 val->odr = ST1VAFE3BX_1Hz6_ULP;
629 break;
630 case 0x02:
631 val->odr = ST1VAFE3BX_3Hz_ULP;
632 break;
633 case 0x03:
634 val->odr = ST1VAFE3BX_25Hz_ULP;
635 break;
636 case 0x04:
637 val->odr = ST1VAFE3BX_6Hz_LP;
638 break;
639 case 0x05:
640 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_12Hz5_HP : ST1VAFE3BX_12Hz5_LP;
641 break;
642 case 0x06:
643 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_25Hz_HP : ST1VAFE3BX_25Hz_LP;
644 break;
645 case 0x07:
646 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_50Hz_HP : ST1VAFE3BX_50Hz_LP;
647 break;
648 case 0x08:
649 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_100Hz_HP : ST1VAFE3BX_100Hz_LP;
650 break;
651 case 0x09:
652 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_200Hz_HP : ST1VAFE3BX_200Hz_LP;
653 break;
654 case 0x0A:
655 val->odr = (ctrl3.hp_en == 0x1U) ? ST1VAFE3BX_400Hz_HP : ST1VAFE3BX_400Hz_LP;
656 break;
657 case 0x0B:
658 if (ah_bio_cfg2.ah_bio_en == 0x1U)
659 {
660 val->odr = (ctrl3.hp_en == 0x1U) ?
661 ST1VAFE3BX_800Hz_VAFE_HP : ST1VAFE3BX_3200Hz_VAFE_LP;
662 }
663 else
664 {
665 val->odr = (ctrl3.hp_en == 0x1U) ?
666 ST1VAFE3BX_800Hz_HP : ST1VAFE3BX_800Hz_LP;
667 }
668 break;
669 case 0xe:
670 val->odr = ST1VAFE3BX_TRIG_PIN;
671 break;
672 case 0xf:
673 val->odr = ST1VAFE3BX_TRIG_SW;
674 break;
675 default:
676 val->odr = ST1VAFE3BX_OFF;
677 break;
678 }
679
680 switch (ctrl5.fs)
681 {
682 case 0:
683 val->fs = ST1VAFE3BX_2g;
684 break;
685 case 1:
686 val->fs = ST1VAFE3BX_4g;
687 break;
688 case 2:
689 val->fs = ST1VAFE3BX_8g;
690 break;
691 case 3:
692 val->fs = ST1VAFE3BX_16g;
693 break;
694 default:
695 val->fs = ST1VAFE3BX_2g;
696 break;
697 }
698
699 if (ah_bio_cfg2.ah_bio_en == 0x1U)
700 {
701 switch (ctrl5.bw)
702 {
703 case 0:
704 val->bw = (ctrl3.hp_en == 0x1U) ?
705 ST1VAFE3BX_BW_VAFE_360Hz : ST1VAFE3BX_BW_VAFE_1600Hz;
706 break;
707 case 1:
708 val->bw = (ctrl3.hp_en == 0x1U) ?
709 ST1VAFE3BX_BW_VAFE_180Hz : ST1VAFE3BX_BW_VAFE_700Hz;
710 break;
711 case 2:
712 val->bw = (ctrl3.hp_en == 0x1U) ?
713 ST1VAFE3BX_BW_VAFE_90Hz : ST1VAFE3BX_BW_VAFE_360Hz;
714 break;
715 case 3:
716 val->bw = (ctrl3.hp_en == 0x1U) ?
717 ST1VAFE3BX_BW_VAFE_45Hz : ST1VAFE3BX_BW_VAFE_180Hz;
718 break;
719 default:
720 val->bw = (ctrl3.hp_en == 0x1U) ?
721 ST1VAFE3BX_BW_VAFE_360Hz : ST1VAFE3BX_BW_VAFE_1600Hz;
722 break;
723 }
724 }
725 else
726 {
727 if (ctrl5.odr == ST1VAFE3BX_6Hz_LP || ctrl5.odr == ST1VAFE3BX_12Hz5_LP
728 || ctrl5.odr == ST1VAFE3BX_25Hz_LP)
729 {
730 switch (ctrl5.bw)
731 {
732 case 1:
733 val->bw = ST1VAFE3BX_BW_LP_12Hz5;
734 break;
735 case 2:
736 val->bw = ST1VAFE3BX_BW_LP_6Hz;
737 break;
738 case 3:
739 val->bw = ST1VAFE3BX_BW_LP_3Hz;
740 break;
741 default:
742 /* value not allowed */
743 ret = -1;
744 break;
745 }
746 }
747 else
748 {
749
750 switch (ctrl5.bw)
751 {
752 case 0:
753 val->bw = ST1VAFE3BX_BW_ODR_div_2;
754 break;
755 case 1:
756 val->bw = ST1VAFE3BX_BW_ODR_div_4;
757 break;
758 case 2:
759 val->bw = ST1VAFE3BX_BW_ODR_div_8;
760 break;
761 case 3:
762 val->bw = ST1VAFE3BX_BW_ODR_div_16;
763 break;
764 default:
765 val->bw = ST1VAFE3BX_BW_ODR_div_2;
766 break;
767 }
768 }
769 }
770
771 return ret;
772 }
773
774 /**
775 * @brief Enter soft power down in SPI case[set]
776 *
777 * @param ctx read / write interface definitions
778 * @param val Enter soft power down in SPI case
779 * @retval interface status (MANDATORY: return 0 -> no Error)
780 *
781 */
st1vafe3bx_exit_deep_power_down(const stmdev_ctx_t * ctx)782 int32_t st1vafe3bx_exit_deep_power_down(const stmdev_ctx_t *ctx)
783 {
784 st1vafe3bx_en_device_config_t en_device_config = {0};
785 int32_t ret;
786
787 en_device_config.en_dev_conf = PROPERTY_ENABLE;
788 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EN_DEVICE_CONFIG,
789 (uint8_t *)&en_device_config, 1);
790
791 if (ctx->mdelay != NULL)
792 {
793 ctx->mdelay(25);
794 }
795
796 return ret;
797 }
798
799 /**
800 * @brief Software trigger for One-Shot.[get]
801 *
802 * @param ctx communication interface handler.(ptr)
803 * @param md the sensor conversion parameters.(ptr)
804 * @retval interface status (MANDATORY: return 0 -> no Error)
805 *
806 */
st1vafe3bx_trigger_sw(const stmdev_ctx_t * ctx,const st1vafe3bx_md_t * md)807 int32_t st1vafe3bx_trigger_sw(const stmdev_ctx_t *ctx,
808 const st1vafe3bx_md_t *md)
809 {
810 st1vafe3bx_ctrl4_t ctrl4;
811 int32_t ret = 0;
812
813 if (md->odr == ST1VAFE3BX_TRIG_SW)
814 {
815 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
816 ctrl4.soc = PROPERTY_ENABLE;
817 if (ret == 0)
818 {
819 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
820 }
821 }
822 return ret;
823 }
824
st1vafe3bx_all_sources_get(const stmdev_ctx_t * ctx,st1vafe3bx_all_sources_t * val)825 int32_t st1vafe3bx_all_sources_get(const stmdev_ctx_t *ctx,
826 st1vafe3bx_all_sources_t *val)
827 {
828 st1vafe3bx_status_register_t status;
829 int32_t ret;
830
831 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STATUS, (uint8_t *)&status, 1);
832 val->drdy = status.drdy;
833
834 if (ret == 0 && status.int_global == 0x1U)
835 {
836 st1vafe3bx_wake_up_src_t wu_src;
837 st1vafe3bx_tap_src_t tap_src;
838 st1vafe3bx_sixd_src_t sixd_src;
839
840 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_SIXD_SRC,
841 (uint8_t *)&sixd_src, 1);
842 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_SRC,
843 (uint8_t *)&wu_src, 1);
844 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_SRC,
845 (uint8_t *)&tap_src, 1);
846
847 val->six_d = sixd_src.d6d_ia;
848 val->six_d_xl = sixd_src.xl;
849 val->six_d_xh = sixd_src.xh;
850 val->six_d_yl = sixd_src.yl;
851 val->six_d_yh = sixd_src.yh;
852 val->six_d_zl = sixd_src.zl;
853 val->six_d_zh = sixd_src.zh;
854
855 val->wake_up = wu_src.wu_ia;
856 val->wake_up_z = wu_src.z_wu;
857 val->wake_up_y = wu_src.y_wu;
858 val->wake_up_x = wu_src.x_wu;
859 val->free_fall = wu_src.ff_ia;
860 val->sleep_change = wu_src.sleep_change_ia;
861 val->sleep_state = wu_src.sleep_state;
862
863 val->single_tap = tap_src.single_tap_ia;
864 val->double_tap = tap_src.double_tap_ia;
865 val->triple_tap = tap_src.triple_tap_ia;
866 }
867
868 return ret;
869 }
870
871 /**
872 * @brief Accelerometer data.[get]
873 *
874 * @param ctx communication interface handler.(ptr)
875 * @param md the sensor conversion parameters.(ptr)
876 * @param data data retrived from the sensor.(ptr)
877 * @retval interface status (MANDATORY: return 0 -> no Error)
878 *
879 */
st1vafe3bx_xl_data_get(const stmdev_ctx_t * ctx,const st1vafe3bx_md_t * md,st1vafe3bx_xl_data_t * data)880 int32_t st1vafe3bx_xl_data_get(const stmdev_ctx_t *ctx,
881 const st1vafe3bx_md_t *md,
882 st1vafe3bx_xl_data_t *data)
883 {
884 uint8_t buff[6];
885 int32_t ret;
886 uint8_t i;
887 uint8_t j;
888
889 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_OUT_X_L, buff, 6);
890
891 /* acceleration conversion */
892 j = 0U;
893 for (i = 0U; i < 3U; i++)
894 {
895 data->raw[i] = (int16_t)buff[j + 1U];
896 data->raw[i] = (data->raw[i] * 256U) + (int16_t) buff[j];
897 j += 2U;
898 switch (md->fs)
899 {
900 case ST1VAFE3BX_2g:
901 data->mg[i] = st1vafe3bx_from_fs2g_to_mg(data->raw[i]);
902 break;
903 case ST1VAFE3BX_4g:
904 data->mg[i] = st1vafe3bx_from_fs4g_to_mg(data->raw[i]);
905 break;
906 case ST1VAFE3BX_8g:
907 data->mg[i] = st1vafe3bx_from_fs8g_to_mg(data->raw[i]);
908 break;
909 case ST1VAFE3BX_16g:
910 data->mg[i] = st1vafe3bx_from_fs16g_to_mg(data->raw[i]);
911 break;
912 default:
913 data->mg[i] = 0.0f;
914 break;
915 }
916 }
917
918 return ret;
919 }
920
921 /**
922 * @brief AH_BIO data.[get]
923 *
924 * @param ctx communication interface handler.(ptr)
925 * @param data data retrived from the sensor.(ptr)
926 * @retval interface status (MANDATORY: return 0 -> no Error)
927 *
928 */
st1vafe3bx_ah_bio_data_get(const stmdev_ctx_t * ctx,st1vafe3bx_ah_bio_data_t * data)929 int32_t st1vafe3bx_ah_bio_data_get(const stmdev_ctx_t *ctx,
930 st1vafe3bx_ah_bio_data_t *data)
931 {
932 uint8_t buff[2];
933 int32_t ret;
934
935 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_OUT_AH_BIO_L, buff, 2);
936
937 data->raw = (int16_t)buff[1];
938 data->raw = (data->raw * 256U) + (int16_t)buff[0];
939
940 data->mv = st1vafe3bx_from_lsb_to_mv(data->raw);
941
942 return ret;
943 }
944
945 /**
946 * @brief Configures the self test.[set]
947 *
948 * @param ctx communication interface handler.(ptr)
949 * @param val self test mode.(ptr)
950 * @retval interface status (MANDATORY: return 0 -> no Error)
951 *
952 */
st1vafe3bx_self_test_sign_set(const stmdev_ctx_t * ctx,st1vafe3bx_xl_self_test_t val)953 int32_t st1vafe3bx_self_test_sign_set(const stmdev_ctx_t *ctx,
954 st1vafe3bx_xl_self_test_t val)
955 {
956 st1vafe3bx_ctrl3_t ctrl3;
957 st1vafe3bx_wake_up_dur_t wkup_dur;
958 int32_t ret;
959
960 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
961 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
962 (uint8_t *)&wkup_dur, 1);
963
964 switch (val)
965 {
966 case ST1VAFE3BX_XL_ST_POSITIVE:
967 ctrl3.st_sign_x = 1;
968 ctrl3.st_sign_y = 1;
969 wkup_dur.st_sign_z = 0;
970 break;
971
972 case ST1VAFE3BX_XL_ST_NEGATIVE:
973 ctrl3.st_sign_x = 0;
974 ctrl3.st_sign_y = 0;
975 wkup_dur.st_sign_z = 1;
976 break;
977
978 case ST1VAFE3BX_XL_ST_DISABLE:
979 default:
980 ret = -1;
981 break;
982 }
983
984
985 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
986 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
987 (uint8_t *)&wkup_dur, 1);
988
989 return ret;
990 }
991
992 /**
993 * @brief Configures the self test.[start]
994 *
995 * @param ctx communication interface handler.(ptr)
996 * @param val valid values 2 (1st step) or 1 (2nd step)
997 * @retval interface status (MANDATORY: return 0 -> no Error)
998 *
999 */
st1vafe3bx_self_test_start(const stmdev_ctx_t * ctx,uint8_t val)1000 int32_t st1vafe3bx_self_test_start(const stmdev_ctx_t *ctx, uint8_t val)
1001 {
1002 st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3;
1003 int32_t ret;
1004
1005 if (val != 1U && val != 2U)
1006 {
1007 return -1;
1008 }
1009
1010 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
1011 (uint8_t *)&ah_bio_cfg3, 1);
1012 if (ret == 0)
1013 {
1014 ah_bio_cfg3.st = (uint8_t)val;
1015 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
1016 (uint8_t *)&ah_bio_cfg3, 1);
1017 }
1018 return ret;
1019 }
1020
1021 /**
1022 * @brief Configures the self test.[stop]
1023 *
1024 * @param ctx communication interface handler.(ptr)
1025 * @retval interface status (MANDATORY: return 0 -> no Error)
1026 *
1027 */
st1vafe3bx_self_test_stop(const stmdev_ctx_t * ctx)1028 int32_t st1vafe3bx_self_test_stop(const stmdev_ctx_t *ctx)
1029 {
1030 st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3;
1031 int32_t ret;
1032
1033 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
1034 (uint8_t *)&ah_bio_cfg3, 1);
1035 if (ret == 0)
1036 {
1037 ah_bio_cfg3.st = 0;
1038 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3,
1039 (uint8_t *)&ah_bio_cfg3, 1);
1040 }
1041 return ret;
1042 }
1043
1044 /**
1045 * @brief Configures I3C bus.[set]
1046 *
1047 * @param ctx communication interface handler.(ptr)
1048 * @param val configuration params
1049 * @retval interface status (MANDATORY: return 0 -> no Error)
1050 *
1051 */
st1vafe3bx_i3c_configure_set(const stmdev_ctx_t * ctx,const st1vafe3bx_i3c_cfg_t * val)1052 int32_t st1vafe3bx_i3c_configure_set(const stmdev_ctx_t *ctx,
1053 const st1vafe3bx_i3c_cfg_t *val)
1054 {
1055 st1vafe3bx_i3c_if_ctrl_t i3c_cfg;
1056 int32_t ret;
1057
1058 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_I3C_IF_CTRL,
1059 (uint8_t *)&i3c_cfg, 1);
1060
1061 if (ret == 0)
1062 {
1063 i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel;
1064 i3c_cfg.dis_drstdaa = val->drstdaa_en;
1065 i3c_cfg.asf_on = val->asf_on;
1066 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_I3C_IF_CTRL,
1067 (uint8_t *)&i3c_cfg, 1);
1068 }
1069
1070 return ret;
1071 }
1072
1073 /**
1074 * @brief Configures I3C bus.[get]
1075 *
1076 * @param ctx communication interface handler.(ptr)
1077 * @param val configuration params
1078 * @retval interface status (MANDATORY: return 0 -> no Error)
1079 *
st1vafe3bx_i3c_configure_get(const stmdev_ctx_t * ctx,st1vafe3bx_i3c_cfg_t * val)1080 */int32_t st1vafe3bx_i3c_configure_get(const stmdev_ctx_t *ctx,
1081 st1vafe3bx_i3c_cfg_t *val)
1082 {
1083 st1vafe3bx_i3c_if_ctrl_t i3c_cfg;
1084 int32_t ret;
1085
1086 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_I3C_IF_CTRL,
1087 (uint8_t *)&i3c_cfg, 1);
1088
1089 val->drstdaa_en = i3c_cfg.dis_drstdaa;
1090 val->asf_on = i3c_cfg.asf_on;
1091
1092 switch (val->bus_act_sel)
1093 {
1094 case ST1VAFE3BX_I3C_BUS_AVAIL_TIME_20US:
1095 val->bus_act_sel = ST1VAFE3BX_I3C_BUS_AVAIL_TIME_20US;
1096 break;
1097
1098 case ST1VAFE3BX_I3C_BUS_AVAIL_TIME_50US:
1099 val->bus_act_sel = ST1VAFE3BX_I3C_BUS_AVAIL_TIME_50US;
1100 break;
1101
1102 case ST1VAFE3BX_I3C_BUS_AVAIL_TIME_1MS:
1103 val->bus_act_sel = ST1VAFE3BX_I3C_BUS_AVAIL_TIME_1MS;
1104 break;
1105
1106 case ST1VAFE3BX_I3C_BUS_AVAIL_TIME_25MS:
1107 default:
1108 val->bus_act_sel = ST1VAFE3BX_I3C_BUS_AVAIL_TIME_25MS;
1109 break;
1110 }
1111
1112 return ret;
1113 }
1114
1115 /**
1116 * @brief Change memory bank.[set]
1117 *
1118 * @param ctx read / write interface definitions
1119 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK,
1120 * STRED_MEM_BANK,
1121 * @retval interface status (MANDATORY: return 0 -> no Error)
1122 *
1123 */
st1vafe3bx_mem_bank_set(const stmdev_ctx_t * ctx,st1vafe3bx_mem_bank_t val)1124 int32_t st1vafe3bx_mem_bank_set(const stmdev_ctx_t *ctx,
1125 st1vafe3bx_mem_bank_t val)
1126 {
1127 st1vafe3bx_func_cfg_access_t func_cfg_access;
1128 int32_t ret;
1129
1130 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FUNC_CFG_ACCESS,
1131 (uint8_t *)&func_cfg_access, 1);
1132
1133 if (ret == 0)
1134 {
1135 func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U);
1136 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FUNC_CFG_ACCESS,
1137 (uint8_t *)&func_cfg_access, 1);
1138 }
1139
1140 return ret;
1141 }
1142
1143 /**
1144 * @brief Change memory bank.[get]
1145 *
1146 * @param ctx read / write interface definitions
1147 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK,
1148 * STRED_MEM_BANK,
1149 * @retval interface status (MANDATORY: return 0 -> no Error)
1150 *
1151 */
st1vafe3bx_mem_bank_get(const stmdev_ctx_t * ctx,st1vafe3bx_mem_bank_t * val)1152 int32_t st1vafe3bx_mem_bank_get(const stmdev_ctx_t *ctx,
1153 st1vafe3bx_mem_bank_t *val)
1154 {
1155 st1vafe3bx_func_cfg_access_t func_cfg_access;
1156 int32_t ret;
1157
1158 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FUNC_CFG_ACCESS,
1159 (uint8_t *)&func_cfg_access, 1);
1160
1161 switch ((func_cfg_access.emb_func_reg_access))
1162 {
1163 case 0x0:
1164 *val = ST1VAFE3BX_MAIN_MEM_BANK;
1165 break;
1166
1167 case 0x1:
1168 *val = ST1VAFE3BX_EMBED_FUNC_MEM_BANK;
1169 break;
1170
1171 default:
1172 *val = ST1VAFE3BX_MAIN_MEM_BANK;
1173 break;
1174 }
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Write buffer in a page.
1180 *
1181 * @param ctx read / write interface definitions
1182 * @param address Address of page register to be written (page number in
1183 * 8-bit msb, register address in 8-bit lsb).
1184 * @param buf Pointer to data buffer.
1185 * @param len Buffer len.
1186 * @retval interface status (MANDATORY: return 0 -> no Error)
1187 *
1188 */
st1vafe3bx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1189 int32_t st1vafe3bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1190 uint8_t *buf, uint8_t len)
1191 {
1192 st1vafe3bx_page_address_t page_address;
1193 st1vafe3bx_page_sel_t page_sel;
1194 st1vafe3bx_page_rw_t page_rw;
1195 uint8_t msb;
1196 uint8_t lsb;
1197 int32_t ret;
1198 uint8_t i ;
1199
1200 msb = ((uint8_t)(address >> 8) & 0x0FU);
1201 lsb = (uint8_t)address & 0xFFU;
1202
1203 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1204
1205 if (ret == 0)
1206 {
1207 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1208 page_rw.page_read = PROPERTY_DISABLE;
1209 page_rw.page_write = PROPERTY_ENABLE;
1210 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW,
1211 (uint8_t *)&page_rw, 1);
1212
1213 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1214 (uint8_t *)&page_sel, 1);
1215 page_sel.page_sel = msb;
1216 page_sel.not_used0 = 1; // Default value
1217 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1218 (uint8_t *)&page_sel, 1);
1219
1220 page_address.page_addr = lsb;
1221 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS,
1222 (uint8_t *)&page_address, 1);
1223
1224 for (i = 0; i < len; i++)
1225 {
1226 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1);
1227 lsb++;
1228
1229 /* Check if page wrap */
1230 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1231 {
1232 msb++;
1233 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1234 (uint8_t *)&page_sel, 1);
1235 page_sel.page_sel = msb;
1236 page_sel.not_used0 = 1; // Default value
1237 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1238 (uint8_t *)&page_sel, 1);
1239 }
1240
1241 if (ret != 0)
1242 {
1243 break;
1244 }
1245 }
1246
1247 page_sel.page_sel = 0;
1248 page_sel.not_used0 = 1;// Default value
1249 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1250 (uint8_t *)&page_sel, 1);
1251
1252 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1253 page_rw.page_read = PROPERTY_DISABLE;
1254 page_rw.page_write = PROPERTY_DISABLE;
1255 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW,
1256 (uint8_t *)&page_rw, 1);
1257 }
1258
1259 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1260
1261 return ret;
1262 }
1263
1264 /**
1265 * @brief Read buffer in a page.
1266 *
1267 * @param ctx read / write interface definitions
1268 * @param address Address of page register to be read (page number in 8-bit
1269 * msb, register address in 8-bit lsb).
1270 * @param buf Pointer to data buffer.
1271 * @param len Buffer len.
1272 * @retval interface status (MANDATORY: return 0 -> no Error)
1273 *
1274 */
st1vafe3bx_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1275 int32_t st1vafe3bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address,
1276 uint8_t *buf, uint8_t len)
1277 {
1278 st1vafe3bx_page_address_t page_address;
1279 st1vafe3bx_page_sel_t page_sel;
1280 st1vafe3bx_page_rw_t page_rw;
1281 uint8_t msb;
1282 uint8_t lsb;
1283 int32_t ret;
1284 uint8_t i ;
1285
1286 msb = ((uint8_t)(address >> 8) & 0x0FU);
1287 lsb = (uint8_t)address & 0xFFU;
1288
1289 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1290
1291 if (ret == 0)
1292 {
1293 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1294 page_rw.page_read = PROPERTY_ENABLE;
1295 page_rw.page_write = PROPERTY_DISABLE;
1296 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW,
1297 (uint8_t *)&page_rw, 1);
1298
1299 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1300 (uint8_t *)&page_sel, 1);
1301 page_sel.page_sel = msb;
1302 page_sel.not_used0 = 1; // Default value
1303 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1304 (uint8_t *)&page_sel, 1);
1305
1306 page_address.page_addr = lsb;
1307 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_ADDRESS,
1308 (uint8_t *)&page_address, 1);
1309
1310 for (i = 0; i < len; i++)
1311 {
1312 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_VALUE, &buf[i], 1);
1313 lsb++;
1314
1315 /* Check if page wrap */
1316 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1317 {
1318 msb++;
1319 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1320 (uint8_t *)&page_sel, 1);
1321 page_sel.page_sel = msb;
1322 page_sel.not_used0 = 1; // Default value
1323 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1324 (uint8_t *)&page_sel, 1);
1325 }
1326
1327 if (ret != 0)
1328 {
1329 break;
1330 }
1331 }
1332
1333 page_sel.page_sel = 0;
1334 page_sel.not_used0 = 1;// Default value
1335 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_SEL,
1336 (uint8_t *)&page_sel, 1);
1337
1338 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1339 page_rw.page_read = PROPERTY_DISABLE;
1340 page_rw.page_write = PROPERTY_DISABLE;
1341 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW,
1342 (uint8_t *)&page_rw, 1);
1343 }
1344
1345 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1346
1347 return ret;
1348 }
1349
1350 /**
1351 * @}
1352 *
1353 */
1354
1355 /**
1356 * @defgroup Interrupt PINs
1357 * @brief Interrupt PINs
1358 * @{/
1359 *
1360 */
1361
1362 /**
1363 * @brief External Clock Enable/Disable on INT pin.[set]
1364 *
1365 * @param ctx read / write interface definitions
1366 * @param val 0: disable ext_clk - 1: enable ext_clk
1367 * @retval interface status (MANDATORY: return 0 -> no Error)
1368 *
1369 */
st1vafe3bx_ext_clk_en_set(const stmdev_ctx_t * ctx,uint8_t val)1370 int32_t st1vafe3bx_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val)
1371 {
1372 st1vafe3bx_ext_clk_cfg_t clk;
1373 int32_t ret;
1374
1375 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1376 clk.ext_clk_en = val;
1377 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief External Clock Enable/Disable on INT pin.[get]
1384 *
1385 * @param ctx read / write interface definitions
1386 * @param val 0: disable ext_clk - 1: enable ext_clk
1387 * @retval interface status (MANDATORY: return 0 -> no Error)
1388 *
1389 */
st1vafe3bx_ext_clk_en_get(const stmdev_ctx_t * ctx,uint8_t * val)1390 int32_t st1vafe3bx_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
1391 {
1392 st1vafe3bx_ext_clk_cfg_t clk;
1393 int32_t ret;
1394
1395 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1396 *val = clk.ext_clk_en;
1397
1398 return ret;
1399 }
1400
1401 /**
1402 * @brief Electrical pin configuration.[set]
1403 *
1404 * @param ctx read / write interface definitions
1405 * @param val the electrical settings for the configurable pins.(ptr)
1406 * @retval interface status (MANDATORY: return 0 -> no Error)
1407 *
1408 */
st1vafe3bx_pin_conf_set(const stmdev_ctx_t * ctx,const st1vafe3bx_pin_conf_t * val)1409 int32_t st1vafe3bx_pin_conf_set(const stmdev_ctx_t *ctx,
1410 const st1vafe3bx_pin_conf_t *val)
1411 {
1412 st1vafe3bx_pin_ctrl_t pin_ctrl;
1413 int32_t ret;
1414
1415 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1416
1417 if (ret == 0)
1418 {
1419 pin_ctrl.cs_pu_dis = ~val->cs_pull_up;
1420 pin_ctrl.sda_pu_en = val->sda_pull_up;
1421 pin_ctrl.sdo_pu_en = val->sdo_pull_up;
1422 pin_ctrl.pp_od = ~val->int_push_pull;
1423
1424 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PIN_CTRL,
1425 (uint8_t *)&pin_ctrl, 1);
1426 }
1427
1428 return ret;
1429 }
1430
1431 /**
1432 * @brief Electrical pin configuration.[get]
1433 *
1434 * @param ctx read / write interface definitions
1435 * @param val the electrical settings for the configurable pins.(ptr)
1436 * @retval interface status (MANDATORY: return 0 -> no Error)
1437 *
1438 */
st1vafe3bx_pin_conf_get(const stmdev_ctx_t * ctx,st1vafe3bx_pin_conf_t * val)1439 int32_t st1vafe3bx_pin_conf_get(const stmdev_ctx_t *ctx,
1440 st1vafe3bx_pin_conf_t *val)
1441 {
1442 st1vafe3bx_pin_ctrl_t pin_ctrl;
1443 int32_t ret;
1444
1445 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1446
1447 val->cs_pull_up = ~pin_ctrl.cs_pu_dis;
1448 val->sda_pull_up = pin_ctrl.sda_pu_en;
1449 val->sdo_pull_up = pin_ctrl.sdo_pu_en;
1450 val->int_push_pull = ~pin_ctrl.pp_od;
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief Interrupt activation level.[set]
1457 *
1458 * @param ctx read / write interface definitions
1459 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1460 * @retval interface status (MANDATORY: return 0 -> no Error)
1461 *
1462 */
st1vafe3bx_int_pin_polarity_set(const stmdev_ctx_t * ctx,st1vafe3bx_int_pin_polarity_t val)1463 int32_t st1vafe3bx_int_pin_polarity_set(const stmdev_ctx_t *ctx,
1464 st1vafe3bx_int_pin_polarity_t val)
1465 {
1466 st1vafe3bx_pin_ctrl_t pin_ctrl;
1467 int32_t ret;
1468
1469 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1470
1471 if (ret == 0)
1472 {
1473 pin_ctrl.h_lactive = (uint8_t)val;
1474 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PIN_CTRL,
1475 (uint8_t *)&pin_ctrl, 1);
1476 }
1477
1478 return ret;
1479 }
1480
1481 /**
1482 * @brief Interrupt activation level.[get]
1483 *
1484 * @param ctx read / write interface definitions
1485 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1486 * @retval interface status (MANDATORY: return 0 -> no Error)
1487 *
1488 */
st1vafe3bx_int_pin_polarity_get(const stmdev_ctx_t * ctx,st1vafe3bx_int_pin_polarity_t * val)1489 int32_t st1vafe3bx_int_pin_polarity_get(const stmdev_ctx_t *ctx,
1490 st1vafe3bx_int_pin_polarity_t *val)
1491 {
1492 st1vafe3bx_pin_ctrl_t pin_ctrl;
1493 int32_t ret;
1494
1495 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1496
1497 switch ((pin_ctrl.h_lactive))
1498 {
1499 case 0x0:
1500 *val = ST1VAFE3BX_ACTIVE_HIGH;
1501 break;
1502
1503 case 0x1:
1504 *val = ST1VAFE3BX_ACTIVE_LOW;
1505 break;
1506
1507 default:
1508 *val = ST1VAFE3BX_ACTIVE_HIGH;
1509 break;
1510 }
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief SPI mode.[set]
1517 *
1518 * @param ctx read / write interface definitions
1519 * @param val SPI_4_WIRE, SPI_3_WIRE,
1520 * @retval interface status (MANDATORY: return 0 -> no Error)
1521 *
1522 */
st1vafe3bx_spi_mode_set(const stmdev_ctx_t * ctx,st1vafe3bx_spi_mode val)1523 int32_t st1vafe3bx_spi_mode_set(const stmdev_ctx_t *ctx,
1524 st1vafe3bx_spi_mode val)
1525 {
1526 st1vafe3bx_pin_ctrl_t pin_ctrl;
1527 int32_t ret;
1528
1529 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1530
1531 if (ret == 0)
1532 {
1533 pin_ctrl.sim = (uint8_t)val;
1534 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PIN_CTRL,
1535 (uint8_t *)&pin_ctrl, 1);
1536 }
1537
1538 return ret;
1539 }
1540
1541 /**
1542 * @brief SPI mode.[get]
1543 *
1544 * @param ctx read / write interface definitions
1545 * @param val SPI_4_WIRE, SPI_3_WIRE,
1546 * @retval interface status (MANDATORY: return 0 -> no Error)
1547 *
1548 */
st1vafe3bx_spi_mode_get(const stmdev_ctx_t * ctx,st1vafe3bx_spi_mode * val)1549 int32_t st1vafe3bx_spi_mode_get(const stmdev_ctx_t *ctx,
1550 st1vafe3bx_spi_mode *val)
1551 {
1552 st1vafe3bx_pin_ctrl_t pin_ctrl;
1553 int32_t ret;
1554
1555 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1556
1557 switch ((pin_ctrl.sim))
1558 {
1559 case 0x0:
1560 *val = ST1VAFE3BX_SPI_4_WIRE;
1561 break;
1562
1563 case 0x1:
1564 *val = ST1VAFE3BX_SPI_3_WIRE;
1565 break;
1566
1567 default:
1568 *val = ST1VAFE3BX_SPI_4_WIRE;
1569 break;
1570 }
1571 return ret;
1572 }
1573
1574 /**
1575 * @brief routes interrupt signals on INT pin.[set]
1576 *
1577 * @param ctx read / write interface definitions
1578 * @param val routes interrupt signals on INT pin.
1579 * @retval interface status (MANDATORY: return 0 -> no Error)
1580 *
1581 */
st1vafe3bx_pin_int_route_set(const stmdev_ctx_t * ctx,const st1vafe3bx_pin_int_route_t * val)1582 int32_t st1vafe3bx_pin_int_route_set(const stmdev_ctx_t *ctx,
1583 const st1vafe3bx_pin_int_route_t *val)
1584 {
1585 st1vafe3bx_ctrl1_t ctrl1;
1586 st1vafe3bx_ctrl2_t ctrl2;
1587 st1vafe3bx_md1_cfg_t md1_cfg;
1588 int32_t ret;
1589
1590 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
1591 ctrl1.int_pin_en = PROPERTY_ENABLE;
1592 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
1593
1594 if (ret == 0)
1595 {
1596 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL2, (uint8_t *)&ctrl2, 1);
1597
1598 if (ret == 0)
1599 {
1600 ctrl2.int_drdy = val->drdy;
1601 ctrl2.int_fifo_ovr = val->fifo_ovr;
1602 ctrl2.int_fifo_th = val->fifo_th;
1603 ctrl2.int_fifo_full = val->fifo_full;
1604 ctrl2.int_boot = val->boot;
1605
1606 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL2, (uint8_t *)&ctrl2, 1);
1607 }
1608 }
1609
1610 if (ret == 0)
1611 {
1612 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1613
1614 if (ret == 0)
1615 {
1616 md1_cfg.int_ff = val->free_fall;
1617 md1_cfg.int_6d = val->six_d;
1618 md1_cfg.int_tap = val->tap;
1619 md1_cfg.int_wu = val->wake_up;
1620 md1_cfg.int_sleep_change = val->sleep_change;
1621 md1_cfg.int_emb_func = val->emb_function;
1622 md1_cfg.int_timestamp = val->timestamp;
1623
1624 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_MD1_CFG,
1625 (uint8_t *)&md1_cfg, 1);
1626 }
1627 }
1628
1629 return ret;
1630 }
1631
1632 /**
1633 * @brief routes interrupt signals on INT pin.[get]
1634 *
1635 * @param ctx read / write interface definitions
1636 * @param val Get interrupt signals routing on INT pin.
1637 * @retval interface status (MANDATORY: return 0 -> no Error)
1638 *
1639 */
st1vafe3bx_pin_int_route_get(const stmdev_ctx_t * ctx,st1vafe3bx_pin_int_route_t * val)1640 int32_t st1vafe3bx_pin_int_route_get(const stmdev_ctx_t *ctx,
1641 st1vafe3bx_pin_int_route_t *val)
1642 {
1643 st1vafe3bx_ctrl2_t ctrl2;
1644 st1vafe3bx_md1_cfg_t md1_cfg;
1645 int32_t ret;
1646
1647 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL2, (uint8_t *)&ctrl2, 1);
1648 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1649
1650 if (ret == 0)
1651 {
1652 val->drdy = ctrl2.int_drdy;
1653 val->fifo_ovr = ctrl2.int_fifo_ovr;
1654 val->fifo_th = ctrl2.int_fifo_th;
1655 val->fifo_full = ctrl2.int_fifo_full;
1656 val->boot = ctrl2.int_boot;
1657
1658 val->free_fall = md1_cfg.int_ff;
1659 val->six_d = md1_cfg.int_6d;
1660 val->tap = md1_cfg.int_tap;
1661 val->wake_up = md1_cfg.int_wu;
1662 val->sleep_change = md1_cfg.int_sleep_change;
1663 val->emb_function = md1_cfg.int_emb_func;
1664 val->timestamp = md1_cfg.int_timestamp;
1665 }
1666
1667 return ret;
1668 }
1669
1670 /**
1671 * @brief routes embedded func interrupt signals on INT pin.[set]
1672 *
1673 * @param ctx read / write interface definitions
1674 * @param val routes embedded func interrupt signals on INT 1 pin.
1675 * @retval interface status (MANDATORY: return 0 -> no Error)
1676 *
1677 */
st1vafe3bx_emb_pin_int_route_set(const stmdev_ctx_t * ctx,const st1vafe3bx_emb_pin_int_route_t * val)1678 int32_t st1vafe3bx_emb_pin_int_route_set(const stmdev_ctx_t *ctx,
1679 const st1vafe3bx_emb_pin_int_route_t *val)
1680 {
1681 st1vafe3bx_emb_func_int_t emb_func_int;
1682 st1vafe3bx_md1_cfg_t md1_cfg;
1683 int32_t ret;
1684
1685 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1686 if (ret == 0)
1687 {
1688 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INT,
1689 (uint8_t *)&emb_func_int, 1);
1690 }
1691
1692 if (ret == 0)
1693 {
1694 emb_func_int.int_tilt = val->tilt;
1695 emb_func_int.int_sig_mot = val->sig_mot;
1696 emb_func_int.int_step_det = val->step_det;
1697 emb_func_int.int_fsm_lc = val->fsm_lc;
1698
1699 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_INT,
1700 (uint8_t *)&emb_func_int, 1);
1701 }
1702 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1703
1704 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1705 if (ret == 0)
1706 {
1707 md1_cfg.int_emb_func = 1;
1708 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1709 }
1710
1711 return ret;
1712 }
1713
1714 /**
1715 * @brief routes embedded func interrupt signals on INT pin.[get]
1716 *
1717 * @param ctx read / write interface definitions
1718 * @param val routes embedded func interrupt signals on INT 1 pin.
1719 * @retval interface status (MANDATORY: return 0 -> no Error)
1720 *
1721 */
st1vafe3bx_emb_pin_int_route_get(const stmdev_ctx_t * ctx,st1vafe3bx_emb_pin_int_route_t * val)1722 int32_t st1vafe3bx_emb_pin_int_route_get(const stmdev_ctx_t *ctx,
1723 st1vafe3bx_emb_pin_int_route_t *val)
1724 {
1725 st1vafe3bx_emb_func_int_t emb_func_int;
1726 int32_t ret;
1727
1728 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1729 if (ret == 0)
1730 {
1731 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INT,
1732 (uint8_t *)&emb_func_int, 1);
1733 }
1734
1735 if (ret == 0)
1736 {
1737 val->tilt = emb_func_int.int_tilt;
1738 val->sig_mot = emb_func_int.int_sig_mot;
1739 val->step_det = emb_func_int.int_step_det;
1740 val->fsm_lc = emb_func_int.int_fsm_lc;
1741 }
1742 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1743
1744 return ret;
1745 }
1746
1747 /**
1748 * @brief Interrupt configuration mode.[set]
1749 *
1750 * @param ctx read / write interface definitions
1751 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1752 * @retval interface status (MANDATORY: return 0 -> no Error)
1753 *
1754 */
st1vafe3bx_int_config_set(const stmdev_ctx_t * ctx,const st1vafe3bx_int_config_t * val)1755 int32_t st1vafe3bx_int_config_set(const stmdev_ctx_t *ctx,
1756 const st1vafe3bx_int_config_t *val)
1757 {
1758 st1vafe3bx_interrupt_cfg_t interrupt_cfg;
1759 int32_t ret;
1760
1761 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
1762 (uint8_t *)&interrupt_cfg, 1);
1763
1764 if (ret == 0)
1765 {
1766 switch (val->int_cfg)
1767 {
1768 case ST1VAFE3BX_INT_DISABLED:
1769 interrupt_cfg.interrupts_enable = 0;
1770 break;
1771
1772 case ST1VAFE3BX_INT_LEVEL:
1773 interrupt_cfg.interrupts_enable = 1;
1774 interrupt_cfg.lir = 0;
1775 break;
1776
1777 case ST1VAFE3BX_INT_LATCHED:
1778 default:
1779 interrupt_cfg.interrupts_enable = 1;
1780 interrupt_cfg.lir = 1;
1781 break;
1782 }
1783
1784 interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int;
1785 interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int;
1786
1787 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
1788 (uint8_t *)&interrupt_cfg, 1);
1789 }
1790
1791 return ret;
1792 }
1793
1794 /**
1795 * @brief Interrupt configuration mode.[get]
1796 *
1797 * @param ctx read / write interface definitions
1798 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1799 * @retval interface status (MANDATORY: return 0 -> no Error)
1800 *
1801 */
st1vafe3bx_int_config_get(const stmdev_ctx_t * ctx,st1vafe3bx_int_config_t * val)1802 int32_t st1vafe3bx_int_config_get(const stmdev_ctx_t *ctx,
1803 st1vafe3bx_int_config_t *val)
1804 {
1805 st1vafe3bx_interrupt_cfg_t interrupt_cfg;
1806 int32_t ret;
1807
1808 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
1809 (uint8_t *)&interrupt_cfg, 1);
1810
1811 if (ret == 0)
1812 {
1813 val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int;
1814 val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int;
1815
1816 if (interrupt_cfg.interrupts_enable == 0U)
1817 {
1818 val->int_cfg = ST1VAFE3BX_INT_DISABLED;
1819 }
1820 else if (interrupt_cfg.lir == 0U)
1821 {
1822 val->int_cfg = ST1VAFE3BX_INT_LEVEL;
1823 }
1824 else
1825 {
1826 val->int_cfg = ST1VAFE3BX_INT_LATCHED;
1827 }
1828 }
1829
1830 return ret;
1831 }
1832
1833 /**
1834 * @brief Embedded Interrupt configuration mode.[set]
1835 *
1836 * @param ctx read / write interface definitions
1837 * @param val INT_PULSED, INT_LATCHED
1838 * @retval interface status (MANDATORY: return 0 -> no Error)
1839 *
1840 */
st1vafe3bx_embedded_int_cfg_set(const stmdev_ctx_t * ctx,st1vafe3bx_embedded_int_config_t val)1841 int32_t st1vafe3bx_embedded_int_cfg_set(const stmdev_ctx_t *ctx,
1842 st1vafe3bx_embedded_int_config_t val)
1843 {
1844 st1vafe3bx_page_rw_t page_rw;
1845 int32_t ret;
1846
1847 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1848 if (ret == 0)
1849 {
1850 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1851
1852 switch (val)
1853 {
1854 case ST1VAFE3BX_EMBEDDED_INT_LEVEL:
1855 page_rw.emb_func_lir = 0;
1856 break;
1857
1858 case ST1VAFE3BX_EMBEDDED_INT_LATCHED:
1859 default:
1860 page_rw.emb_func_lir = 1;
1861 break;
1862 }
1863
1864 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_PAGE_RW,
1865 (uint8_t *)&page_rw, 1);
1866 }
1867
1868 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1869
1870 return ret;
1871 }
1872
1873 /**
1874 * @brief Interrupt configuration mode.[get]
1875 *
1876 * @param ctx read / write interface definitions
1877 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
1878 * @retval interface status (MANDATORY: return 0 -> no Error)
1879 *
1880 */
st1vafe3bx_embedded_int_cfg_get(const stmdev_ctx_t * ctx,st1vafe3bx_embedded_int_config_t * val)1881 int32_t st1vafe3bx_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
1882 st1vafe3bx_embedded_int_config_t *val)
1883 {
1884 st1vafe3bx_page_rw_t page_rw;
1885 int32_t ret;
1886
1887 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
1888 if (ret == 0)
1889 {
1890 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1891
1892 if (page_rw.emb_func_lir == 0U)
1893 {
1894 *val = ST1VAFE3BX_EMBEDDED_INT_LEVEL;
1895 }
1896 else
1897 {
1898 *val = ST1VAFE3BX_EMBEDDED_INT_LATCHED;
1899 }
1900 }
1901
1902 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
1903
1904 return ret;
1905 }
1906
1907 /**
1908 * @}
1909 *
1910 */
1911
1912 /**
1913 * @defgroup FIFO
1914 * @brief FIFO
1915 * @{/
1916 *
1917 */
1918
1919 /**
1920 * @brief FIFO mode selection.[set]
1921 *
1922 * @param ctx read / write interface definitions
1923 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE,
1924 * BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1925 * @retval interface status (MANDATORY: return 0 -> no Error)
1926 *
1927 */
st1vafe3bx_fifo_mode_set(const stmdev_ctx_t * ctx,st1vafe3bx_fifo_mode_t val)1928 int32_t st1vafe3bx_fifo_mode_set(const stmdev_ctx_t *ctx,
1929 st1vafe3bx_fifo_mode_t val)
1930 {
1931 st1vafe3bx_ctrl4_t ctrl4;
1932 st1vafe3bx_fifo_ctrl_t fifo_ctrl;
1933 st1vafe3bx_fifo_wtm_t fifo_wtm;
1934 st1vafe3bx_fifo_batch_dec_t fifo_batch;
1935 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
1936 int32_t ret;
1937
1938 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
1939 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_CTRL,
1940 (uint8_t *)&fifo_ctrl, 1);
1941 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_BATCH_DEC,
1942 (uint8_t *)&fifo_batch, 1);
1943 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1944 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
1945 (uint8_t *)&ah_bio_cfg2, 1);
1946
1947 if (ret == 0)
1948 {
1949 /* set FIFO mode */
1950 if (val.operation != ST1VAFE3BX_FIFO_OFF)
1951 {
1952 ctrl4.fifo_en = 1;
1953 fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U);
1954
1955 /*
1956 * fifo_en_adv must be set to 1 when the embedded function results and/or
1957 * the AH / vAFE data at 3200 Hz ODR are intended to be stored in FIFO.
1958 * It can be set to 0 in the other cases
1959 */
1960 if (ah_bio_cfg2.ah_bio_en == 0x1U)
1961 {
1962 fifo_ctrl.fifo_en_adv = 0x1U;
1963 }
1964 else
1965 {
1966 fifo_ctrl.fifo_en_adv = 0x0U;
1967 }
1968 }
1969 else
1970 {
1971 ctrl4.fifo_en = 0;
1972 }
1973
1974 /* set fifo depth (1X/2X) */
1975 fifo_ctrl.fifo_depth = (uint8_t)val.store;
1976
1977 /* set xl_only_fifo */
1978 fifo_wtm.xl_only_fifo = val.xl_only;
1979
1980 /* set batching info */
1981 if (val.batch.dec_ts != ST1VAFE3BX_DEC_TS_OFF)
1982 {
1983 fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts;
1984 fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl;
1985 }
1986
1987 fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo;
1988
1989 /* set watermark */
1990 if (val.watermark > 0U)
1991 {
1992 fifo_ctrl.stop_on_fth = 1;
1993 fifo_wtm.fth = val.watermark;
1994 }
1995
1996 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FIFO_BATCH_DEC,
1997 (uint8_t *)&fifo_batch, 1);
1998 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FIFO_WTM,
1999 (uint8_t *)&fifo_wtm, 1);
2000 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FIFO_CTRL,
2001 (uint8_t *)&fifo_ctrl, 1);
2002 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
2003 }
2004
2005 return ret;
2006 }
2007
2008 /**
2009 * @brief FIFO mode selection.[get]
2010 *
2011 * @param ctx read / write interface definitions
2012 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE,
2013 * BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
2014 * @retval interface status (MANDATORY: return 0 -> no Error)
2015 *
2016 */
st1vafe3bx_fifo_mode_get(const stmdev_ctx_t * ctx,st1vafe3bx_fifo_mode_t * val)2017 int32_t st1vafe3bx_fifo_mode_get(const stmdev_ctx_t *ctx,
2018 st1vafe3bx_fifo_mode_t *val)
2019 {
2020 st1vafe3bx_ctrl4_t ctrl4;
2021 st1vafe3bx_fifo_ctrl_t fifo_ctrl;
2022 st1vafe3bx_fifo_wtm_t fifo_wtm;
2023 st1vafe3bx_fifo_batch_dec_t fifo_batch;
2024 int32_t ret;
2025
2026 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
2027 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_CTRL,
2028 (uint8_t *)&fifo_ctrl, 1);
2029 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_BATCH_DEC,
2030 (uint8_t *)&fifo_batch, 1);
2031 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
2032
2033 if (ret == 0)
2034 {
2035 /* get FIFO mode */
2036 if (ctrl4.fifo_en == 0U)
2037 {
2038 val->operation = ST1VAFE3BX_FIFO_OFF;
2039 }
2040 else
2041 {
2042 val->operation = (enum st1vafe3bx_operation_t)fifo_ctrl.fifo_mode;
2043 }
2044 val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en;
2045
2046 /* get fifo depth (1X/2X) */
2047 val->store = (enum st1vafe3bx_store_t)fifo_ctrl.fifo_depth;
2048
2049 /* Get xl_only_fifo */
2050 val->xl_only = fifo_wtm.xl_only_fifo;
2051
2052 /* get batching info */
2053 val->batch.dec_ts = (enum st1vafe3bx_dec_ts_t)fifo_batch.dec_ts_batch;
2054 val->batch.bdr_xl = (enum st1vafe3bx_bdr_xl_t)fifo_batch.bdr_xl;
2055
2056 /* get watermark */
2057 val->watermark = fifo_wtm.fth;
2058 }
2059
2060 return ret;
2061 }
2062
2063 /**
2064 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
2065 *
2066 * @param ctx read / write interface definitions
2067 * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO.
2068 * @retval interface status (MANDATORY: return 0 -> no Error)
2069 *
2070 */
st1vafe3bx_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)2071 int32_t st1vafe3bx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
2072 {
2073 uint8_t buff;
2074 int32_t ret;
2075
2076 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_STATUS2, &buff, 1);
2077
2078 *val = buff;
2079
2080 return ret;
2081 }
2082
st1vafe3bx_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2083 int32_t st1vafe3bx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2084 {
2085 st1vafe3bx_fifo_status1_t fifo_status1;
2086 int32_t ret;
2087
2088 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1);
2089
2090 *val = fifo_status1.fifo_wtm_ia;
2091
2092 return ret;
2093 }
2094
st1vafe3bx_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,st1vafe3bx_fifo_sensor_tag_t * val)2095 int32_t st1vafe3bx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
2096 st1vafe3bx_fifo_sensor_tag_t *val)
2097 {
2098 st1vafe3bx_fifo_data_out_tag_t fifo_tag;
2099 int32_t ret;
2100
2101 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_DATA_OUT_TAG,
2102 (uint8_t *)&fifo_tag, 1);
2103
2104 *val = (st1vafe3bx_fifo_sensor_tag_t) fifo_tag.tag_sensor;
2105
2106 return ret;
2107 }
2108
st1vafe3bx_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)2109 int32_t st1vafe3bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2110 {
2111 int32_t ret;
2112
2113 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_DATA_OUT_X_L, buff, 6);
2114
2115 return ret;
2116 }
2117
st1vafe3bx_fifo_data_get(const stmdev_ctx_t * ctx,const st1vafe3bx_md_t * md,const st1vafe3bx_fifo_mode_t * fmd,st1vafe3bx_fifo_data_t * data)2118 int32_t st1vafe3bx_fifo_data_get(const stmdev_ctx_t *ctx,
2119 const st1vafe3bx_md_t *md,
2120 const st1vafe3bx_fifo_mode_t *fmd,
2121 st1vafe3bx_fifo_data_t *data)
2122 {
2123 st1vafe3bx_fifo_data_out_tag_t fifo_tag;
2124 uint8_t fifo_raw[6];
2125 int32_t ret, i;
2126
2127 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FIFO_DATA_OUT_TAG,
2128 (uint8_t *)&fifo_tag, 1);
2129 data->tag = fifo_tag.tag_sensor;
2130
2131 switch (fifo_tag.tag_sensor)
2132 {
2133 case ST1VAFE3BX_TIMESTAMP_CFG_CHG_TAG:
2134 ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw);
2135
2136 data->cfg_chg.cfg_change = fifo_raw[0] >> 7;
2137 data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU;
2138 data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U;
2139 data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U;
2140 data->cfg_chg.ah_en = fifo_raw[1] >> 7;
2141 data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U;
2142 data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U;
2143 data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U;
2144
2145 data->cfg_chg.timestamp = fifo_raw[5];
2146 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4];
2147 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3];
2148 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2];
2149 break;
2150 case ST1VAFE3BX_XL_ONLY_2X_TAG:
2151 /*
2152 * Accelerometer only data (2x depth mode), a FIFO sample consists
2153 * of 2 x 8-bits 3-axis XL at ODR/2
2154 */
2155 ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw);
2156 for (i = 0; i < 3; i++)
2157 {
2158 data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256U;
2159 data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256U;
2160 }
2161 break;
2162 case ST1VAFE3BX_STEP_COUNTER_TAG:
2163 /* step counted + timestamp */
2164 ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw);
2165
2166 data->pedo.steps = fifo_raw[1];
2167 data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0];
2168
2169 data->pedo.timestamp = fifo_raw[5];
2170 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4];
2171 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3];
2172 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2];
2173 break;
2174 case ST1VAFE3BX_AH_VAFE_ONLY_TAG:
2175 /* vAFE data (16 bit) if vafe_only mode is enabled */
2176 ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw);
2177
2178 data->ah_bio.raw = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256U;
2179 data->ah_bio.mv = st1vafe3bx_from_lsb_to_mv(data->ah_bio.raw);
2180 break;
2181 case ST1VAFE3BX_XL_ONLY:
2182 case ST1VAFE3BX_XL_AND_AH_VAFE1_TAG:
2183 ret = st1vafe3bx_fifo_out_raw_get(ctx, fifo_raw);
2184
2185 /*
2186 * XL data(12bit) + vAFE(12bit) if xl_only bit in FIFO WTM
2187 * is set else XL data only(16 bit)
2188 */
2189 if (fmd->xl_only == 0x0U)
2190 {
2191 /*
2192 * data packaging in FIFO when XL and vAFE available:
2193 * ------------- -------------
2194 * | LSB0 | LSN1 | MSN0 |
2195 * ------------- -------------
2196 * | MSB1 | LSB2 |
2197 * ------------- -------------
2198 * | LSN3 | MSN2 | MSB3 |
2199 * ------------- -------------
2200 *
2201 * ------------- ------------- ------------- -------------
2202 * | X | Y | Z | vAFE |
2203 * ------------- ------------- ------------- -------------
2204 * | MSN0 | LSB0 | MSB1 | LSN1 | MSN2 | LSB2 | MSB3 | LSN3 |
2205 * ------ ------ ------ ------ ------ ------ ------ ------
2206 */
2207 data->xl[0].raw[0] = (int16_t)fifo_raw[0];
2208 data->xl[0].raw[0] = (data->xl[0].raw[0] +
2209 ((int16_t)fifo_raw[1] * 256U)) * 16U;
2210
2211 data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16U;
2212 data->xl[0].raw[1] = (data->xl[0].raw[1] +
2213 (int16_t)fifo_raw[2] * 16U) * 16U;
2214
2215 data->xl[0].raw[2] = (int16_t)fifo_raw[3];
2216 data->xl[0].raw[2] = (data->xl[0].raw[2] +
2217 ((int16_t)fifo_raw[4] * 256U)) * 16U;
2218
2219 data->ah_bio.raw = (int16_t)fifo_raw[4] / 16U;
2220 data->ah_bio.raw = (data->ah_bio.raw +
2221 ((int16_t)fifo_raw[5] * 16U)) * 16U;
2222 data->ah_bio.mv = st1vafe3bx_from_lsb_to_mv(data->ah_bio.raw);
2223 }
2224 else
2225 {
2226 data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256U;
2227 data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256U;
2228 data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256U;
2229 }
2230 break;
2231 default:
2232 /* do nothing */
2233 break;
2234 }
2235
2236 for (i = 0; i < 3; i++)
2237 {
2238 switch (md->fs)
2239 {
2240 case ST1VAFE3BX_2g:
2241 data->xl[0].mg[i] = st1vafe3bx_from_fs2g_to_mg(data->xl[0].raw[i]);
2242 data->xl[1].mg[i] = st1vafe3bx_from_fs2g_to_mg(data->xl[1].raw[i]);
2243 break;
2244 case ST1VAFE3BX_4g:
2245 data->xl[0].mg[i] = st1vafe3bx_from_fs4g_to_mg(data->xl[0].raw[i]);
2246 data->xl[1].mg[i] = st1vafe3bx_from_fs4g_to_mg(data->xl[1].raw[i]);
2247 break;
2248 case ST1VAFE3BX_8g:
2249 data->xl[0].mg[i] = st1vafe3bx_from_fs8g_to_mg(data->xl[0].raw[i]);
2250 data->xl[1].mg[i] = st1vafe3bx_from_fs8g_to_mg(data->xl[1].raw[i]);
2251 break;
2252 case ST1VAFE3BX_16g:
2253 data->xl[0].mg[i] = st1vafe3bx_from_fs16g_to_mg(data->xl[0].raw[i]);
2254 data->xl[1].mg[i] = st1vafe3bx_from_fs16g_to_mg(data->xl[1].raw[i]);
2255 break;
2256 default:
2257 data->xl[0].mg[i] = 0.0f;
2258 data->xl[1].mg[i] = 0.0f;
2259 break;
2260 }
2261 }
2262
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief Configures AH_BIO chain.[set]
2268 *
2269 * @param ctx read / write interface definitions
2270 * @param val Configures AH_BIO chain.
2271 * @retval interface status (MANDATORY: return 0 -> no Error)
2272 *
2273 */
st1vafe3bx_ah_bio_config_set(const stmdev_ctx_t * ctx,st1vafe3bx_ah_bio_config_t val)2274 int32_t st1vafe3bx_ah_bio_config_set(const stmdev_ctx_t *ctx,
2275 st1vafe3bx_ah_bio_config_t val)
2276 {
2277 st1vafe3bx_ah_bio_cfg1_t cfg1;
2278 st1vafe3bx_ah_bio_cfg2_t cfg2;
2279 st1vafe3bx_ah_bio_cfg3_t cfg3;
2280 int32_t ret;
2281
2282 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG1, (uint8_t *)&cfg1, 1);
2283 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2284 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2285
2286 if (ret == 0)
2287 {
2288 cfg1.ah_bio_zin_dis_ah2_bio1 = val.ah_bio_zin_dis_1;
2289 cfg1.ah_bio_zin_dis_ah2_bio2 = val.ah_bio_zin_dis_2;
2290
2291 switch (val.mode)
2292 {
2293 case ST1VAFE3BX_DIFFERENTIAL_MODE:
2294 cfg2.ah_bio_mode = 0x0U;
2295 break;
2296 case ST1VAFE3BX_SINGLE_MODE_01:
2297 cfg2.ah_bio_mode = 0x1U;
2298 break;
2299 case ST1VAFE3BX_SINGLE_MODE_10:
2300 cfg2.ah_bio_mode = 0x2U;
2301 break;
2302 case ST1VAFE3BX_FORCED_RESET:
2303 cfg2.ah_bio_mode = 0x3U;
2304 break;
2305 default:
2306 cfg2.ah_bio_mode = 0x0U;
2307 break;
2308 }
2309
2310 switch (val.gain)
2311 {
2312 case ST1VAFE3BX_GAIN_2:
2313 cfg2.ah_bio_gain = 0x0U;
2314 break;
2315 case ST1VAFE3BX_GAIN_4:
2316 cfg2.ah_bio_gain = 0x1U;
2317 break;
2318 case ST1VAFE3BX_GAIN_8:
2319 cfg2.ah_bio_gain = 0x2U;
2320 break;
2321 case ST1VAFE3BX_GAIN_16:
2322 cfg2.ah_bio_gain = 0x3U;
2323 break;
2324 default:
2325 cfg2.ah_bio_gain = 0x0U;
2326 break;
2327 }
2328
2329 switch (val.zin)
2330 {
2331 case ST1VAFE3BX_100MOhm:
2332 cfg2.ah_bio_c_zin = 0x0U;
2333 break;
2334 case ST1VAFE3BX_200MOhm:
2335 cfg2.ah_bio_c_zin = 0x1U;
2336 break;
2337 case ST1VAFE3BX_500MOhm:
2338 cfg2.ah_bio_c_zin = 0x2U;
2339 break;
2340 case ST1VAFE3BX_1GOhm:
2341 cfg2.ah_bio_c_zin = 0x3U;
2342 break;
2343 default:
2344 cfg2.ah_bio_c_zin = 0x0U;
2345 break;
2346 }
2347 }
2348
2349 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG1, (uint8_t *)&cfg1, 1);
2350 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2351 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2352
2353 return ret;
2354 }
2355
2356 /**
2357 * @brief Configures AH_BIO chain.[get]
2358 *
2359 * @param ctx read / write interface definitions
2360 * @param val Configures AH_BIO chain.
2361 * @retval interface status (MANDATORY: return 0 -> no Error)
2362 *
2363 */
st1vafe3bx_ah_bio_config_get(const stmdev_ctx_t * ctx,st1vafe3bx_ah_bio_config_t * val)2364 int32_t st1vafe3bx_ah_bio_config_get(const stmdev_ctx_t *ctx,
2365 st1vafe3bx_ah_bio_config_t *val)
2366 {
2367 st1vafe3bx_ah_bio_cfg1_t cfg1;
2368 st1vafe3bx_ah_bio_cfg2_t cfg2;
2369 st1vafe3bx_ah_bio_cfg3_t cfg3;
2370 int32_t ret;
2371
2372 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG1, (uint8_t *)&cfg1, 1);
2373 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2374 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2375
2376 if (ret == 0)
2377 {
2378
2379 val->ah_bio_zin_dis_1 = cfg1.ah_bio_zin_dis_ah2_bio1;
2380 val->ah_bio_zin_dis_2 = cfg1.ah_bio_zin_dis_ah2_bio2;
2381
2382 switch (cfg2.ah_bio_mode)
2383 {
2384 case 0x0:
2385 val->mode = ST1VAFE3BX_DIFFERENTIAL_MODE;
2386 break;
2387 case 0x1:
2388 val->mode = ST1VAFE3BX_SINGLE_MODE_01;
2389 break;
2390 case 0x2:
2391 val->mode = ST1VAFE3BX_SINGLE_MODE_10;
2392 break;
2393 case 0x3:
2394 val->mode = ST1VAFE3BX_FORCED_RESET;
2395 break;
2396 default:
2397 val->mode = ST1VAFE3BX_DIFFERENTIAL_MODE;
2398 break;
2399 }
2400 }
2401
2402 switch (cfg2.ah_bio_c_zin)
2403 {
2404 case 0x0:
2405 val->zin = ST1VAFE3BX_100MOhm;
2406 break;
2407 case 0x1:
2408 val->zin = ST1VAFE3BX_200MOhm;
2409 break;
2410 case 0x2:
2411 val->zin = ST1VAFE3BX_500MOhm;
2412 break;
2413 case 0x3:
2414 val->zin = ST1VAFE3BX_1GOhm;
2415 break;
2416 default:
2417 val->zin = ST1VAFE3BX_100MOhm;
2418 break;
2419 }
2420
2421 switch (cfg2.ah_bio_gain)
2422 {
2423 case 0x0:
2424 val->gain = ST1VAFE3BX_GAIN_2;
2425 break;
2426 case 0x1:
2427 val->gain = ST1VAFE3BX_GAIN_4;
2428 break;
2429 case 0x2:
2430 val->gain = ST1VAFE3BX_GAIN_8;
2431 break;
2432 case 0x3:
2433 val->gain = ST1VAFE3BX_GAIN_16;
2434 break;
2435 default:
2436 val->gain = ST1VAFE3BX_GAIN_2;
2437 break;
2438 }
2439
2440 return ret;
2441 }
2442
2443 /**
2444 * @brief Enter vafe-only state (must be called in power-down)
2445 *
2446 * @param ctx read / write interface definitions
2447 * @retval interface status (MANDATORY: return 0 -> no Error)
2448 *
2449 */
st1vafe3bx_enter_vafe_only(const stmdev_ctx_t * ctx)2450 int32_t st1vafe3bx_enter_vafe_only(const stmdev_ctx_t *ctx)
2451 {
2452 st1vafe3bx_ah_bio_cfg2_t cfg2;
2453 int32_t ret;
2454
2455 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2456 cfg2.ah_bio_en = 1;
2457 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2458
2459 return ret;
2460 }
2461
2462 /**
2463 * @brief Enter vafe-only state (must be called in power-down)
2464 *
2465 * @param ctx read / write interface definitions
2466 * @retval interface status (MANDATORY: return 0 -> no Error)
2467 *
2468 */
st1vafe3bx_exit_vafe_only(const stmdev_ctx_t * ctx)2469 int32_t st1vafe3bx_exit_vafe_only(const stmdev_ctx_t *ctx)
2470 {
2471 st1vafe3bx_ah_bio_cfg2_t cfg2;
2472 int32_t ret;
2473
2474 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2475 cfg2.ah_bio_en = 0;
2476 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2, (uint8_t *)&cfg2, 1);
2477
2478 return ret;
2479 }
2480
2481 /**
2482 * @brief Device active mode when it is set in the AH / vAFE only state[set]
2483 *
2484 * @param ctx read / write interface definitions
2485 * @param val 1: enable active state - 0: disable active state
2486 * @retval interface status (MANDATORY: return 0 -> no Error)
2487 *
2488 */
st1vafe3bx_ah_bio_active(const stmdev_ctx_t * ctx,uint8_t filter_on)2489 int32_t st1vafe3bx_ah_bio_active(const stmdev_ctx_t *ctx, uint8_t filter_on)
2490 {
2491 st1vafe3bx_ah_bio_cfg3_t cfg3;
2492 st1vafe3bx_ctrl3_t ctrl3;
2493 int32_t ret;
2494
2495 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2496 cfg3.ah_bio_active = 0;
2497 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2498
2499 if (ctx->mdelay != NULL)
2500 {
2501 ctx->mdelay(10);
2502 }
2503
2504 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
2505 ctrl3.hp_en = filter_on;
2506 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL3, (uint8_t *)&ctrl3, 1);
2507
2508 cfg3.ah_bio_active = 0;
2509 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_AH_BIO_CFG3, (uint8_t *)&cfg3, 1);
2510
2511 if (ctx->mdelay != NULL)
2512 {
2513 ctx->mdelay(10);
2514 }
2515
2516 return ret;
2517 }
2518
2519 /**
2520 * @defgroup Step Counter (Pedometer)
2521 * @brief Step Counter (Pedometer)
2522 * @{/
2523 *
2524 */
2525 /**
2526 * @brief Step counter mode[set]
2527 *
2528 * @param ctx read / write interface definitions
2529 * @param val Step counter mode
2530 * @retval interface status (MANDATORY: return 0 -> no Error)
2531 *
2532 */
st1vafe3bx_stpcnt_mode_set(const stmdev_ctx_t * ctx,st1vafe3bx_stpcnt_mode_t val)2533 int32_t st1vafe3bx_stpcnt_mode_set(const stmdev_ctx_t *ctx,
2534 st1vafe3bx_stpcnt_mode_t val)
2535 {
2536 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2537 st1vafe3bx_emb_func_en_b_t emb_func_en_b;
2538 st1vafe3bx_emb_func_fifo_en_t emb_func_fifo_en;
2539 st1vafe3bx_pedo_cmd_reg_t pedo_cmd_reg;
2540 int32_t ret;
2541
2542 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2543 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2544 (uint8_t *)&emb_func_en_a, 1);
2545 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
2546 (uint8_t *)&emb_func_en_b, 1);
2547 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
2548 (uint8_t *)&emb_func_fifo_en, 1);
2549
2550 if ((val.false_step_rej == PROPERTY_ENABLE)
2551 && ((emb_func_en_a.mlc_before_fsm_en &
2552 emb_func_en_b.mlc_en) == PROPERTY_DISABLE))
2553 {
2554 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
2555 }
2556
2557 emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo;
2558 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
2559 (uint8_t *)&emb_func_fifo_en, 1);
2560
2561 emb_func_en_a.pedo_en = val.step_counter_enable;
2562 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2563 (uint8_t *)&emb_func_en_a, 1);
2564
2565 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2566 ret += st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2567 ST1VAFE3BX_PEDO_CMD_REG,
2568 (uint8_t *)&pedo_cmd_reg, 1);
2569
2570 if (ret == 0)
2571 {
2572 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
2573 ret += st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2574 ST1VAFE3BX_PEDO_CMD_REG,
2575 (uint8_t *)&pedo_cmd_reg, 1);
2576 }
2577
2578 return ret;
2579 }
2580
2581 /**
2582 * @brief Step counter mode[get]
2583 *
2584 * @param ctx read / write interface definitions
2585 * @param val Step counter mode
2586 * @retval interface status (MANDATORY: return 0 -> no Error)
2587 *
2588 */
st1vafe3bx_stpcnt_mode_get(const stmdev_ctx_t * ctx,st1vafe3bx_stpcnt_mode_t * val)2589 int32_t st1vafe3bx_stpcnt_mode_get(const stmdev_ctx_t *ctx,
2590 st1vafe3bx_stpcnt_mode_t *val)
2591 {
2592 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2593 st1vafe3bx_pedo_cmd_reg_t pedo_cmd_reg;
2594 int32_t ret;
2595
2596 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2597 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2598 (uint8_t *)&emb_func_en_a, 1);
2599 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2600
2601 ret += st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2602 ST1VAFE3BX_PEDO_CMD_REG,
2603 (uint8_t *)&pedo_cmd_reg, 1);
2604 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
2605 val->step_counter_enable = emb_func_en_a.pedo_en;
2606
2607 return ret;
2608 }
2609
2610 /**
2611 * @brief Step counter output, number of detected steps.[get]
2612 *
2613 * @param ctx read / write interface definitions
2614 * @param val Step counter output, number of detected steps.
2615 * @retval interface status (MANDATORY: return 0 -> no Error)
2616 *
2617 */
st1vafe3bx_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)2618 int32_t st1vafe3bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
2619 {
2620 uint8_t buff[2];
2621 int32_t ret;
2622
2623 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2624 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_STEP_COUNTER_L, &buff[0], 2);
2625 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2626
2627 *val = buff[1];
2628 *val = (*val * 256U) + buff[0];
2629
2630 return ret;
2631 }
2632
2633 /**
2634 * @brief Reset step counter.[set]
2635 *
2636 * @param ctx read / write interface definitions
2637 * @param val Reset step counter.
2638 * @retval interface status (MANDATORY: return 0 -> no Error)
2639 *
2640 */
st1vafe3bx_stpcnt_rst_step_set(const stmdev_ctx_t * ctx)2641 int32_t st1vafe3bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx)
2642 {
2643 st1vafe3bx_emb_func_src_t emb_func_src;
2644 int32_t ret;
2645
2646 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2647 if (ret == 0)
2648 {
2649 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_SRC,
2650 (uint8_t *)&emb_func_src, 1);
2651 emb_func_src.pedo_rst_step = 1;
2652 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_SRC,
2653 (uint8_t *)&emb_func_src, 1);
2654 }
2655
2656 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2657
2658 return ret;
2659 }
2660
2661 /**
2662 * @brief Pedometer debounce configuration.[set]
2663 *
2664 * @param ctx read / write interface definitions
2665 * @param val Pedometer debounce configuration.
2666 * @retval interface status (MANDATORY: return 0 -> no Error)
2667 *
2668 */
st1vafe3bx_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)2669 int32_t st1vafe3bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
2670 {
2671 st1vafe3bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2672 int32_t ret;
2673
2674 pedo_deb_steps_conf.deb_step = val;
2675 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2676 ST1VAFE3BX_PEDO_DEB_STEPS_CONF,
2677 (uint8_t *)&pedo_deb_steps_conf, 1);
2678
2679 return ret;
2680 }
2681
2682 /**
2683 * @brief Pedometer debounce configuration.[get]
2684 *
2685 * @param ctx read / write interface definitions
2686 * @param val Pedometer debounce configuration.
2687 * @retval interface status (MANDATORY: return 0 -> no Error)
2688 *
2689 */
st1vafe3bx_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)2690 int32_t st1vafe3bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
2691 {
2692 st1vafe3bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2693 int32_t ret;
2694
2695 ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2696 ST1VAFE3BX_PEDO_DEB_STEPS_CONF,
2697 (uint8_t *)&pedo_deb_steps_conf, 1);
2698 *val = pedo_deb_steps_conf.deb_step;
2699
2700 return ret;
2701 }
2702
2703 /**
2704 * @brief Time period register for step detection on delta time.[set]
2705 *
2706 * @param ctx read / write interface definitions
2707 * @param val Time period register for step detection on delta time.
2708 * @retval interface status (MANDATORY: return 0 -> no Error)
2709 *
2710 */
st1vafe3bx_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)2711 int32_t st1vafe3bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
2712 {
2713 uint8_t buff[2];
2714 int32_t ret;
2715
2716 buff[1] = (uint8_t)(val / 256U);
2717 buff[0] = (uint8_t)(val - (buff[1] * 256U));
2718
2719 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2720 ST1VAFE3BX_PEDO_SC_DELTAT_L,
2721 (uint8_t *)buff, 2);
2722
2723 return ret;
2724 }
2725
2726 /**
2727 * @brief Time period register for step detection on delta time.[get]
2728 *
2729 * @param ctx read / write interface definitions
2730 * @param val Time period register for step detection on delta time.
2731 * @retval interface status (MANDATORY: return 0 -> no Error)
2732 *
2733 */
st1vafe3bx_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)2734 int32_t st1vafe3bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
2735 {
2736 uint8_t buff[2];
2737 int32_t ret;
2738
2739 ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_EMB_ADV_PG_0 +
2740 ST1VAFE3BX_PEDO_SC_DELTAT_L,
2741 (uint8_t *)buff, 2);
2742 *val = buff[1];
2743 *val = (*val * 256U) + buff[0];
2744
2745 return ret;
2746 }
2747
2748 /**
2749 * @}
2750 *
2751 */
2752
2753 /**
2754 * @defgroup Tilt
2755 * @brief Tilt
2756 * @{/
2757 *
2758 */
2759 /**
2760 * @brief Tilt calculation.[set]
2761 *
2762 * @param ctx read / write interface definitions
2763 * @param val Tilt calculation.
2764 * @retval interface status (MANDATORY: return 0 -> no Error)
2765 *
2766 */
st1vafe3bx_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2767 int32_t st1vafe3bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2768 {
2769 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2770 int32_t ret;
2771
2772 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2773 if (ret == 0)
2774 {
2775 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2776 (uint8_t *)&emb_func_en_a, 1);
2777 emb_func_en_a.tilt_en = val;
2778 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2779 (uint8_t *)&emb_func_en_a, 1);
2780 }
2781
2782 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2783
2784 return ret;
2785 }
2786
2787 /**
2788 * @brief Tilt calculation.[get]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val Tilt calculation.
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
st1vafe3bx_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2795 int32_t st1vafe3bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2796 {
2797 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2798 int32_t ret;
2799
2800 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2801 if (ret == 0)
2802 {
2803 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2804 (uint8_t *)&emb_func_en_a, 1);
2805 *val = emb_func_en_a.tilt_en;
2806 }
2807
2808 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2809
2810 return ret;
2811 }
2812
2813 /**
2814 * @}
2815 *
2816 */
2817
2818 /**
2819 * @defgroup Significant motion detection
2820 * @brief Significant motion detection
2821 * @{/
2822 *
2823 */
2824 /**
2825 * @brief Enables significant motion detection function.[set]
2826 *
2827 * @param ctx read / write interface definitions
2828 * @param val Enables significant motion detection function.
2829 * @retval interface status (MANDATORY: return 0 -> no Error)
2830 *
2831 */
st1vafe3bx_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2832 int32_t st1vafe3bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2833 {
2834 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2835 int32_t ret;
2836
2837 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2838 if (ret == 0)
2839 {
2840 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2841 (uint8_t *)&emb_func_en_a, 1);
2842 emb_func_en_a.sign_motion_en = val;
2843 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2844 (uint8_t *)&emb_func_en_a, 1);
2845 }
2846
2847 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2848
2849 return ret;
2850 }
2851
2852 /**
2853 * @brief Enables significant motion detection function.[get]
2854 *
2855 * @param ctx read / write interface definitions
2856 * @param val Enables significant motion detection function.
2857 * @retval interface status (MANDATORY: return 0 -> no Error)
2858 *
2859 */
st1vafe3bx_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2860 int32_t st1vafe3bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2861 {
2862 st1vafe3bx_emb_func_en_a_t emb_func_en_a;
2863 int32_t ret;
2864
2865 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
2866 if (ret == 0)
2867 {
2868 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
2869 (uint8_t *)&emb_func_en_a, 1);
2870 *val = emb_func_en_a.sign_motion_en;
2871 }
2872
2873 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
2874
2875 return ret;
2876 }
2877
2878 /**
2879 * @}
2880 *
2881 */
2882
2883
2884 /**
2885 * @defgroup Free Fall
2886 * @brief Free Fall
2887 * @{/
2888 *
2889 */
2890 /**
2891 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL
2892 * time[set]
2893 *
2894 * @param ctx read / write interface definitions
2895 * @param val Time windows configuration for Free Fall detection
2896 * 1 LSB = 1/ODR_XL time
2897 * @retval interface status (MANDATORY: return 0 -> no Error)
2898 *
2899 */
st1vafe3bx_ff_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2900 int32_t st1vafe3bx_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
2901 {
2902 st1vafe3bx_wake_up_dur_t wake_up_dur;
2903 st1vafe3bx_free_fall_t free_fall;
2904 int32_t ret;
2905
2906 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
2907 (uint8_t *)&wake_up_dur, 1);
2908
2909 if (ret == 0)
2910 {
2911 wake_up_dur.ff_dur = (val >> 5) & 0x1U;
2912 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
2913 (uint8_t *)&wake_up_dur, 1);
2914 }
2915
2916 if (ret == 0)
2917 {
2918 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL,
2919 (uint8_t *)&free_fall, 1);
2920 free_fall.ff_dur = val & 0x1FU;
2921 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FREE_FALL,
2922 (uint8_t *)&free_fall, 1);
2923 }
2924
2925 return ret;
2926 }
2927
2928 /**
2929 * @brief Time windows configuration for Free Fall detection
2930 * 1 LSB = 1/ODR_XL time[get]
2931 *
2932 * @param ctx read / write interface definitions
2933 * @param val Time windows configuration for Free Fall detection
2934 * 1 LSB = 1/ODR_XL time
2935 * @retval interface status (MANDATORY: return 0 -> no Error)
2936 *
2937 */
st1vafe3bx_ff_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2938 int32_t st1vafe3bx_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
2939 {
2940 st1vafe3bx_wake_up_dur_t wake_up_dur;
2941 st1vafe3bx_free_fall_t free_fall;
2942 int32_t ret;
2943
2944 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
2945 (uint8_t *)&wake_up_dur, 1);
2946 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL,
2947 (uint8_t *)&free_fall, 1);
2948
2949 *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur;
2950
2951 return ret;
2952 }
2953
2954 /**
2955 * @brief Free fall threshold setting.[set]
2956 *
2957 * @param ctx read / write interface definitions
2958 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg,
2959 * 500_mg,
2960 * @retval interface status (MANDATORY: return 0 -> no Error)
2961 *
2962 */
st1vafe3bx_ff_thresholds_set(const stmdev_ctx_t * ctx,st1vafe3bx_ff_thresholds_t val)2963 int32_t st1vafe3bx_ff_thresholds_set(const stmdev_ctx_t *ctx,
2964 st1vafe3bx_ff_thresholds_t val)
2965 {
2966 st1vafe3bx_free_fall_t free_fall;
2967 int32_t ret;
2968
2969 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL,
2970 (uint8_t *)&free_fall, 1);
2971 free_fall.ff_ths = ((uint8_t)val & 0x7U);
2972 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FREE_FALL,
2973 (uint8_t *)&free_fall, 1);
2974
2975 return ret;
2976 }
2977
2978 /**
2979 * @brief Free fall threshold setting.[get]
2980 *
2981 * @param ctx read / write interface definitions
2982 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg,
2983 * 500_mg,
2984 * @retval interface status (MANDATORY: return 0 -> no Error)
2985 *
2986 */
st1vafe3bx_ff_thresholds_get(const stmdev_ctx_t * ctx,st1vafe3bx_ff_thresholds_t * val)2987 int32_t st1vafe3bx_ff_thresholds_get(const stmdev_ctx_t *ctx,
2988 st1vafe3bx_ff_thresholds_t *val)
2989 {
2990 st1vafe3bx_free_fall_t free_fall;
2991 int32_t ret;
2992
2993 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FREE_FALL,
2994 (uint8_t *)&free_fall, 1);
2995
2996 switch (free_fall.ff_ths)
2997 {
2998 case 0x0:
2999 *val = ST1VAFE3BX_156_mg;
3000 break;
3001
3002 case 0x1:
3003 *val = ST1VAFE3BX_219_mg;
3004 break;
3005
3006 case 0x2:
3007 *val = ST1VAFE3BX_250_mg;
3008 break;
3009
3010 case 0x3:
3011 *val = ST1VAFE3BX_312_mg;
3012 break;
3013
3014 case 0x4:
3015 *val = ST1VAFE3BX_344_mg;
3016 break;
3017
3018 case 0x5:
3019 *val = ST1VAFE3BX_406_mg;
3020 break;
3021
3022 case 0x6:
3023 *val = ST1VAFE3BX_469_mg;
3024 break;
3025
3026 case 0x7:
3027 *val = ST1VAFE3BX_500_mg;
3028 break;
3029
3030 default:
3031 *val = ST1VAFE3BX_156_mg;
3032 break;
3033 }
3034
3035 return ret;
3036 }
3037
3038 /**
3039 * @}
3040 *
3041 */
3042
3043
3044 /**
3045 * @defgroup Orientation 6D (and 4D)
3046 * @brief Orientation 6D (and 4D)
3047 * @{/
3048 *
3049 */
3050 /**
3051 * @brief configuration for 4D/6D function.[set]
3052 *
3053 * @param ctx read / write interface definitions
3054 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
3055 * @retval interface status (MANDATORY: return 0 -> no Error)
3056 *
3057 */
st1vafe3bx_sixd_config_set(const stmdev_ctx_t * ctx,st1vafe3bx_sixd_config_t val)3058 int32_t st1vafe3bx_sixd_config_set(const stmdev_ctx_t *ctx,
3059 st1vafe3bx_sixd_config_t val)
3060 {
3061 st1vafe3bx_sixd_t sixd;
3062 int32_t ret;
3063
3064 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_SIXD, (uint8_t *)&sixd, 1);
3065
3066 if (ret == 0)
3067 {
3068 sixd.d4d_en = ((uint8_t)val.mode);
3069 sixd.d6d_ths = ((uint8_t)val.threshold);
3070 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_SIXD, (uint8_t *)&sixd, 1);
3071 }
3072
3073 return ret;
3074 }
3075
3076 /**
3077 * @brief configuration for 4D/6D function.[get]
3078 *
3079 * @param ctx read / write interface definitions
3080 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
3081 * @retval interface status (MANDATORY: return 0 -> no Error)
3082 *
3083 */
st1vafe3bx_sixd_config_get(const stmdev_ctx_t * ctx,st1vafe3bx_sixd_config_t * val)3084 int32_t st1vafe3bx_sixd_config_get(const stmdev_ctx_t *ctx,
3085 st1vafe3bx_sixd_config_t *val)
3086 {
3087 st1vafe3bx_sixd_t sixd;
3088 int32_t ret;
3089
3090 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_SIXD, (uint8_t *)&sixd, 1);
3091
3092 val->mode = (st1vafe3bx_mode_t)sixd.d4d_en;
3093
3094 switch ((sixd.d6d_ths))
3095 {
3096 case 0x0:
3097 val->threshold = ST1VAFE3BX_DEG_80;
3098 break;
3099
3100 case 0x1:
3101 val->threshold = ST1VAFE3BX_DEG_70;
3102 break;
3103
3104 case 0x2:
3105 val->threshold = ST1VAFE3BX_DEG_60;
3106 break;
3107
3108 case 0x3:
3109 val->threshold = ST1VAFE3BX_DEG_50;
3110 break;
3111
3112 default:
3113 val->threshold = ST1VAFE3BX_DEG_80;
3114 break;
3115 }
3116
3117 return ret;
3118 }
3119
3120 /**
3121 * @}
3122 *
3123 */
3124
3125 /**
3126 * @defgroup wakeup configuration
3127 * @brief wakeup configuration
3128 * @{/
3129 *
3130 */
3131
3132 /**
3133 * @brief configuration for wakeup function.[set]
3134 *
3135 * @param ctx read / write interface definitions
3136 * @param val threshold, duration, ...
3137 * @retval interface status (MANDATORY: return 0 -> no Error)
3138 *
3139 */
st1vafe3bx_wakeup_config_set(const stmdev_ctx_t * ctx,st1vafe3bx_wakeup_config_t val)3140 int32_t st1vafe3bx_wakeup_config_set(const stmdev_ctx_t *ctx,
3141 st1vafe3bx_wakeup_config_t val)
3142 {
3143 st1vafe3bx_wake_up_ths_t wup_ths;
3144 st1vafe3bx_wake_up_dur_t wup_dur;
3145 st1vafe3bx_wake_up_dur_ext_t wup_dur_ext;
3146 st1vafe3bx_interrupt_cfg_t int_cfg;
3147 st1vafe3bx_ctrl1_t ctrl1;
3148 st1vafe3bx_ctrl4_t ctrl4;
3149 int32_t ret;
3150
3151 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_THS,
3152 (uint8_t *)&wup_ths, 1);
3153 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
3154 (uint8_t *)&wup_dur, 1);
3155 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR_EXT,
3156 (uint8_t *)&wup_dur_ext, 1);
3157 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3158 (uint8_t *)&int_cfg, 1);
3159 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
3160 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
3161
3162 if (ret == 0)
3163 {
3164 wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U;
3165 wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2;
3166 wup_dur.sleep_dur = val.sleep_dur;
3167
3168 int_cfg.wake_ths_w = val.wake_ths_weight;
3169 wup_ths.wk_ths = val.wake_ths;
3170 wup_ths.sleep_on = (uint8_t)val.wake_enable;
3171 ctrl4.inact_odr = (uint8_t)val.inact_odr;
3172
3173 if (val.wake_enable == ST1VAFE3BX_SLEEP_ON)
3174 {
3175 ctrl1.wu_x_en = 1;
3176 ctrl1.wu_y_en = 1;
3177 ctrl1.wu_z_en = 1;
3178 }
3179 else
3180 {
3181 ctrl1.wu_x_en = 0;
3182 ctrl1.wu_y_en = 0;
3183 ctrl1.wu_z_en = 0;
3184 }
3185
3186 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_THS,
3187 (uint8_t *)&wup_ths, 1);
3188 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
3189 (uint8_t *)&wup_dur, 1);
3190 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR_EXT,
3191 (uint8_t *)&wup_dur_ext, 1);
3192 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3193 (uint8_t *)&int_cfg, 1);
3194 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL1, (uint8_t *)&ctrl1, 1);
3195 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
3196 }
3197
3198 return ret;
3199 }
3200
3201 /**
3202 * @brief configuration for wakeup function.[get]
3203 *
3204 * @param ctx read / write interface definitions
3205 * @param val threshold, duration, ...
3206 * @retval interface status (MANDATORY: return 0 -> no Error)
3207 *
3208 */
st1vafe3bx_wakeup_config_get(const stmdev_ctx_t * ctx,st1vafe3bx_wakeup_config_t * val)3209 int32_t st1vafe3bx_wakeup_config_get(const stmdev_ctx_t *ctx,
3210 st1vafe3bx_wakeup_config_t *val)
3211 {
3212 st1vafe3bx_wake_up_ths_t wup_ths;
3213 st1vafe3bx_wake_up_dur_t wup_dur;
3214 st1vafe3bx_wake_up_dur_ext_t wup_dur_ext;
3215 st1vafe3bx_interrupt_cfg_t int_cfg;
3216 st1vafe3bx_ctrl4_t ctrl4;
3217 int32_t ret;
3218
3219 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_THS,
3220 (uint8_t *)&wup_ths, 1);
3221 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR,
3222 (uint8_t *)&wup_dur, 1);
3223 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_WAKE_UP_DUR_EXT,
3224 (uint8_t *)&wup_dur_ext, 1);
3225 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3226 (uint8_t *)&int_cfg, 1);
3227 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_CTRL4, (uint8_t *)&ctrl4, 1);
3228
3229 if (ret == 0)
3230 {
3231 switch (wup_dur.wake_dur)
3232 {
3233 case 0x0:
3234 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3235 ST1VAFE3BX_3_ODR : ST1VAFE3BX_0_ODR;
3236 break;
3237
3238 case 0x1:
3239 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3240 ST1VAFE3BX_7_ODR : ST1VAFE3BX_1_ODR;
3241 break;
3242
3243 case 0x2:
3244 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
3245 ST1VAFE3BX_11_ODR : ST1VAFE3BX_2_ODR;
3246 break;
3247
3248 case 0x3:
3249 default:
3250 val->wake_dur = ST1VAFE3BX_15_ODR;
3251 break;
3252 }
3253
3254 val->sleep_dur = wup_dur.sleep_dur;
3255
3256 val->wake_ths_weight = int_cfg.wake_ths_w;
3257 val->wake_ths = wup_ths.wk_ths;
3258 val->wake_enable = (st1vafe3bx_wake_enable_t)wup_ths.sleep_on;
3259 val->inact_odr = (st1vafe3bx_inact_odr_t)ctrl4.inact_odr;
3260 }
3261
3262 return ret;
3263 }
3264
3265 /**
3266 * @}
3267 *
3268 */
3269
st1vafe3bx_tap_config_set(const stmdev_ctx_t * ctx,st1vafe3bx_tap_config_t val)3270 int32_t st1vafe3bx_tap_config_set(const stmdev_ctx_t *ctx,
3271 st1vafe3bx_tap_config_t val)
3272 {
3273 st1vafe3bx_tap_cfg0_t tap_cfg0;
3274 st1vafe3bx_tap_cfg1_t tap_cfg1;
3275 st1vafe3bx_tap_cfg2_t tap_cfg2;
3276 st1vafe3bx_tap_cfg3_t tap_cfg3;
3277 st1vafe3bx_tap_cfg4_t tap_cfg4;
3278 st1vafe3bx_tap_cfg5_t tap_cfg5;
3279 st1vafe3bx_tap_cfg6_t tap_cfg6;
3280 int32_t ret;
3281
3282 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3283 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3284 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3285 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3286 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3287 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3288 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3289
3290 if (ret == 0)
3291 {
3292 tap_cfg0.axis = (uint8_t)val.axis;
3293 tap_cfg0.invert_t = val.inverted_peak_time;
3294 tap_cfg1.pre_still_ths = val.pre_still_ths;
3295 tap_cfg3.post_still_ths = val.post_still_ths;
3296 tap_cfg1.post_still_t = val.post_still_time & 0xFU;
3297 tap_cfg2.post_still_t = val.post_still_time >> 4;
3298 tap_cfg2.wait_t = val.shock_wait_time;
3299 tap_cfg3.latency_t = val.latency;
3300 tap_cfg4.wait_end_latency = val.wait_end_latency;
3301 tap_cfg4.peak_ths = val.peak_ths;
3302 tap_cfg5.rebound_t = val.rebound;
3303 tap_cfg5.single_tap_en = val.single_tap_on;
3304 tap_cfg5.double_tap_en = val.double_tap_on;
3305 tap_cfg5.triple_tap_en = val.triple_tap_on;
3306 tap_cfg6.pre_still_st = val.pre_still_start;
3307 tap_cfg6.pre_still_n = val.pre_still_n;
3308
3309 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG0,
3310 (uint8_t *)&tap_cfg0, 1);
3311 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG1,
3312 (uint8_t *)&tap_cfg1, 1);
3313 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG2,
3314 (uint8_t *)&tap_cfg2, 1);
3315 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG3,
3316 (uint8_t *)&tap_cfg3, 1);
3317 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG4,
3318 (uint8_t *)&tap_cfg4, 1);
3319 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG5,
3320 (uint8_t *)&tap_cfg5, 1);
3321 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_TAP_CFG6,
3322 (uint8_t *)&tap_cfg6, 1);
3323 }
3324
3325 return ret;
3326 }
3327
st1vafe3bx_tap_config_get(const stmdev_ctx_t * ctx,st1vafe3bx_tap_config_t * val)3328 int32_t st1vafe3bx_tap_config_get(const stmdev_ctx_t *ctx,
3329 st1vafe3bx_tap_config_t *val)
3330 {
3331 st1vafe3bx_tap_cfg0_t tap_cfg0;
3332 st1vafe3bx_tap_cfg1_t tap_cfg1;
3333 st1vafe3bx_tap_cfg2_t tap_cfg2;
3334 st1vafe3bx_tap_cfg3_t tap_cfg3;
3335 st1vafe3bx_tap_cfg4_t tap_cfg4;
3336 st1vafe3bx_tap_cfg5_t tap_cfg5;
3337 st1vafe3bx_tap_cfg6_t tap_cfg6;
3338 int32_t ret;
3339
3340 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3341 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3342 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3343 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3344 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3345 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3346 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3347
3348 if (ret == 0)
3349 {
3350 val->axis = (st1vafe3bx_axis_t)tap_cfg0.axis;
3351 val->inverted_peak_time = tap_cfg0.invert_t;
3352 val->pre_still_ths = tap_cfg1.pre_still_ths;
3353 val->post_still_ths = tap_cfg3.post_still_ths;
3354 val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t;
3355 val->shock_wait_time = tap_cfg2.wait_t;
3356 val->latency = tap_cfg3.latency_t;
3357 val->wait_end_latency = tap_cfg4.wait_end_latency;
3358 val->peak_ths = tap_cfg4.peak_ths;
3359 val->rebound = tap_cfg5.rebound_t;
3360 val->single_tap_on = tap_cfg5.single_tap_en;
3361 val->double_tap_on = tap_cfg5.double_tap_en;
3362 val->triple_tap_on = tap_cfg5.triple_tap_en;
3363 val->pre_still_start = tap_cfg6.pre_still_st;
3364 val->pre_still_n = tap_cfg6.pre_still_n;
3365 }
3366
3367 return ret;
3368 }
3369
3370 /**
3371 * @}
3372 *
3373 */
3374
3375 /**
3376 * @defgroup st1vafe3bx_Timestamp
3377 * @brief This section groups all the functions that manage the
3378 * timestamp generation.
3379 * @{
3380 *
3381 */
3382
3383 /**
3384 * @brief Enables timestamp counter.[set]
3385 *
3386 * @param ctx Read / write interface definitions.(ptr)
3387 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3388 * @retval Interface status (MANDATORY: return 0 -> no Error).
3389 *
3390 */
st1vafe3bx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)3391 int32_t st1vafe3bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
3392 {
3393 st1vafe3bx_interrupt_cfg_t int_cfg;
3394 int32_t ret;
3395
3396 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3397 (uint8_t *)&int_cfg, 1);
3398
3399 if (ret == 0)
3400 {
3401 int_cfg.timestamp_en = (uint8_t)val;
3402 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3403 (uint8_t *)&int_cfg, 1);
3404 }
3405
3406 return ret;
3407 }
3408
3409 /**
3410 * @brief Enables timestamp counter.[get]
3411 *
3412 * @param ctx Read / write interface definitions.(ptr)
3413 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3414 * @retval Interface status (MANDATORY: return 0 -> no Error).
3415 *
3416 */
st1vafe3bx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)3417 int32_t st1vafe3bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
3418 {
3419 st1vafe3bx_interrupt_cfg_t int_cfg;
3420 int32_t ret;
3421
3422 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_INTERRUPT_CFG,
3423 (uint8_t *)&int_cfg, 1);
3424 *val = int_cfg.timestamp_en;
3425
3426 return ret;
3427 }
3428
3429 /**
3430 * @brief Timestamp first data output register (r).
3431 * The value is expressed as a 32-bit word and the bit resolution
3432 * is 10 us.[get]
3433 *
3434 * @param ctx Read / write interface definitions.(ptr)
3435 * @param buff Buffer that stores data read
3436 * @retval Interface status (MANDATORY: return 0 -> no Error).
3437 *
3438 */
st1vafe3bx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)3439 int32_t st1vafe3bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
3440 {
3441 uint8_t buff[4];
3442 int32_t ret;
3443
3444 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_TIMESTAMP0, buff, 4);
3445 *val = buff[3];
3446 *val = (*val * 256U) + buff[2];
3447 *val = (*val * 256U) + buff[1];
3448 *val = (*val * 256U) + buff[0];
3449
3450 return ret;
3451 }
3452
3453 /**
3454 * @}
3455 *
3456 */
3457
3458 /**
3459 * @defgroup ST1VAFE3BX_finite_state_machine
3460 * @brief This section groups all the functions that manage the
3461 * state_machine.
3462 * @{
3463 *
3464 */
3465
3466 /**
3467 * @brief Interrupt status bit for FSM long counter timeout interrupt
3468 * event.[get]
3469 *
3470 * @param ctx Read / write interface definitions.(ptr)
3471 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
3472 * @retval Interface status (MANDATORY: return 0 -> no Error).
3473 *
3474 */
st1vafe3bx_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3475 int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
3476 uint8_t *val)
3477 {
3478 st1vafe3bx_emb_func_status_t emb_func_status;
3479 int32_t ret;
3480
3481 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3482
3483 if (ret == 0)
3484 {
3485 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_STATUS,
3486 (uint8_t *)&emb_func_status, 1);
3487
3488 *val = emb_func_status.is_fsm_lc;
3489 }
3490
3491 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3492
3493 return ret;
3494 }
3495
3496 /**
3497 * @brief Embedded final state machine functions mode.[set]
3498 *
3499 * @param ctx Read / write interface definitions.(ptr)
3500 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
3501 * @retval Interface status (MANDATORY: return 0 -> no Error).
3502 *
3503 */
st1vafe3bx_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)3504 int32_t st1vafe3bx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3505 {
3506 int32_t ret;
3507
3508 st1vafe3bx_emb_func_en_b_t emb_func_en_b;
3509 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3510
3511 if (ret == 0)
3512 {
3513 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3514 (uint8_t *)&emb_func_en_b, 1);
3515
3516 emb_func_en_b.fsm_en = (uint8_t)val;
3517
3518 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3519 (uint8_t *)&emb_func_en_b, 1);
3520 }
3521
3522 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3523
3524 return ret;
3525 }
3526
3527 /**
3528 * @brief Embedded final state machine functions mode.[get]
3529 *
3530 * @param ctx Read / write interface definitions.(ptr)
3531 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
3532 * @retval Interface status (MANDATORY: return 0 -> no Error).
3533 *
3534 */
st1vafe3bx_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3535 int32_t st1vafe3bx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3536 {
3537 int32_t ret;
3538
3539 st1vafe3bx_emb_func_en_b_t emb_func_en_b;
3540 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3541
3542 if (ret == 0)
3543 {
3544 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3545 (uint8_t *)&emb_func_en_b, 1);
3546
3547 *val = emb_func_en_b.fsm_en;
3548
3549 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3550 (uint8_t *)&emb_func_en_b, 1);
3551 }
3552
3553 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3554
3555 return ret;
3556 }
3557
3558 /**
3559 * @brief Embedded final state machine functions mode.[set]
3560 *
3561 * @param ctx Read / write interface definitions.(ptr)
3562 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3563 * @retval Interface status (MANDATORY: return 0 -> no Error).
3564 *
3565 */
st1vafe3bx_fsm_enable_set(const stmdev_ctx_t * ctx,st1vafe3bx_emb_fsm_enable_t * val)3566 int32_t st1vafe3bx_fsm_enable_set(const stmdev_ctx_t *ctx,
3567 st1vafe3bx_emb_fsm_enable_t *val)
3568 {
3569 st1vafe3bx_emb_func_en_b_t emb_func_en_b;
3570 int32_t ret;
3571
3572 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3573
3574 if (ret == 0)
3575 {
3576 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FSM_ENABLE,
3577 (uint8_t *)&val->fsm_enable, 1);
3578 }
3579
3580 if (ret == 0)
3581 {
3582 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3583 (uint8_t *)&emb_func_en_b, 1);
3584
3585 if ((val->fsm_enable.fsm1_en |
3586 val->fsm_enable.fsm2_en |
3587 val->fsm_enable.fsm3_en |
3588 val->fsm_enable.fsm4_en |
3589 val->fsm_enable.fsm5_en |
3590 val->fsm_enable.fsm6_en |
3591 val->fsm_enable.fsm7_en |
3592 val->fsm_enable.fsm8_en) != PROPERTY_DISABLE)
3593 {
3594 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
3595 }
3596 else
3597 {
3598 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
3599 }
3600
3601 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
3602 (uint8_t *)&emb_func_en_b, 1);
3603 }
3604
3605 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3606
3607 return ret;
3608 }
3609
3610 /**
3611 * @brief Embedded final state machine functions mode.[get]
3612 *
3613 * @param ctx Read / write interface definitions.(ptr)
3614 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3615 * @retval Interface status (MANDATORY: return 0 -> no Error).
3616 *
3617 */
st1vafe3bx_fsm_enable_get(const stmdev_ctx_t * ctx,st1vafe3bx_emb_fsm_enable_t * val)3618 int32_t st1vafe3bx_fsm_enable_get(const stmdev_ctx_t *ctx,
3619 st1vafe3bx_emb_fsm_enable_t *val)
3620 {
3621 int32_t ret;
3622
3623 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3624
3625 if (ret == 0)
3626 {
3627 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ENABLE,
3628 (uint8_t *)&val->fsm_enable, 1);
3629 }
3630
3631 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3632
3633 return ret;
3634 }
3635
3636 /**
3637 * @brief FSM long counter status register. Long counter value is an
3638 * unsigned integer value (16-bit format).[set]
3639 *
3640 * @param ctx Read / write interface definitions.(ptr)
3641 * @param buff Buffer that contains data to write
3642 * @retval Interface status (MANDATORY: return 0 -> no Error).
3643 *
3644 */
st1vafe3bx_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)3645 int32_t st1vafe3bx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
3646 {
3647 uint8_t buff[2];
3648 int32_t ret;
3649
3650 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3651
3652 if (ret == 0)
3653 {
3654 buff[1] = (uint8_t)(val / 256U);
3655 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3656 ret = st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FSM_LONG_COUNTER_L, buff, 2);
3657 }
3658
3659 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3660
3661 return ret;
3662 }
3663
3664 /**
3665 * @brief FSM long counter status register. Long counter value is an
3666 * unsigned integer value (16-bit format).[get]
3667 *
3668 * @param ctx Read / write interface definitions.(ptr)
3669 * @param buff Buffer that stores data read
3670 * @retval Interface status (MANDATORY: return 0 -> no Error).
3671 *
3672 */
st1vafe3bx_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)3673 int32_t st1vafe3bx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
3674 {
3675 uint8_t buff[2];
3676 int32_t ret;
3677
3678 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3679
3680 if (ret == 0)
3681 {
3682 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_LONG_COUNTER_L, buff, 2);
3683 *val = buff[1];
3684 *val = (*val * 256U) + buff[0];
3685 }
3686
3687 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3688
3689 return ret;
3690 }
3691
3692 /**
3693 * @brief FSM status.[get]
3694 *
3695 * @param ctx read / write interface definitions
3696 * @param val register FSM_STATUS_MAINPAGE
3697 *
3698 */
st1vafe3bx_fsm_status_get(const stmdev_ctx_t * ctx,st1vafe3bx_fsm_status_mainpage_t * val)3699 int32_t st1vafe3bx_fsm_status_get(const stmdev_ctx_t *ctx,
3700 st1vafe3bx_fsm_status_mainpage_t *val)
3701 {
3702 return st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_STATUS_MAINPAGE,
3703 (uint8_t *) val, 1);
3704 }
3705
3706 /**
3707 * @brief FSM output registers.[get]
3708 *
3709 * @param ctx Read / write interface definitions.(ptr)
3710 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
3711 * @retval Interface status (MANDATORY: return 0 -> no Error).
3712 *
3713 */
st1vafe3bx_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * val)3714 int32_t st1vafe3bx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
3715 {
3716 int32_t ret;
3717
3718 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3719
3720 if (ret == 0)
3721 {
3722 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_OUTS1, val, 8);
3723 }
3724
3725 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3726
3727 return ret;
3728 }
3729
3730 /**
3731 * @brief Finite State Machine ODR configuration.[set]
3732 *
3733 * @param ctx Read / write interface definitions.(ptr)
3734 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3735 * @retval Interface status (MANDATORY: return 0 -> no Error).
3736 *
3737 */
st1vafe3bx_fsm_data_rate_set(const stmdev_ctx_t * ctx,st1vafe3bx_fsm_val_odr_t val)3738 int32_t st1vafe3bx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
3739 st1vafe3bx_fsm_val_odr_t val)
3740 {
3741 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
3742 st1vafe3bx_fsm_odr_t fsm_odr_reg;
3743 int32_t ret = 0;
3744
3745 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
3746 (uint8_t *)&ah_bio_cfg2, 1);
3747
3748 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3749
3750 if (ret == 0)
3751 {
3752 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ODR,
3753 (uint8_t *)&fsm_odr_reg, 1);
3754
3755 fsm_odr_reg.fsm_odr = (uint8_t)val & 0xfU;
3756 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_FSM_ODR,
3757 (uint8_t *)&fsm_odr_reg, 1);
3758 }
3759
3760 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3761
3762 return ret;
3763 }
3764
3765 /**
3766 * @brief Finite State Machine ODR configuration.[get]
3767 *
3768 * @param ctx Read / write interface definitions.(ptr)
3769 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3770 * @retval Interface status (MANDATORY: return 0 -> no Error).
3771 *
3772 */
st1vafe3bx_fsm_data_rate_get(const stmdev_ctx_t * ctx,st1vafe3bx_fsm_val_odr_t * val)3773 int32_t st1vafe3bx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
3774 st1vafe3bx_fsm_val_odr_t *val)
3775 {
3776 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
3777 st1vafe3bx_fsm_odr_t fsm_odr_reg;
3778 int32_t ret;
3779
3780 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3781 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_FSM_ODR,
3782 (uint8_t *)&fsm_odr_reg, 1);
3783 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3784 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
3785 (uint8_t *)&ah_bio_cfg2, 1);
3786
3787 if (ret != 0)
3788 {
3789 return ret;
3790 }
3791
3792 /* depends on vAFE mode only enabled */
3793 if (ah_bio_cfg2.ah_bio_en == 0x1U)
3794 {
3795 switch (fsm_odr_reg.fsm_odr)
3796 {
3797 case 0:
3798 *val = ST1VAFE3BX_ODR_FSM_VAFE_50Hz;
3799 break;
3800 case 1:
3801 *val = ST1VAFE3BX_ODR_FSM_VAFE_100Hz;
3802 break;
3803 case 2:
3804 *val = ST1VAFE3BX_ODR_FSM_VAFE_200Hz;
3805 break;
3806 case 3:
3807 *val = ST1VAFE3BX_ODR_FSM_VAFE_400Hz;
3808 break;
3809 case 4:
3810 *val = ST1VAFE3BX_ODR_FSM_VAFE_800Hz;
3811 break;
3812 case 5:
3813 *val = ST1VAFE3BX_ODR_FSM_VAFE_1600Hz;
3814 break;
3815 default:
3816 *val = ST1VAFE3BX_ODR_FSM_VAFE_50Hz;
3817 break;
3818 }
3819 }
3820 else
3821 {
3822 switch (fsm_odr_reg.fsm_odr)
3823 {
3824 case 0:
3825 *val = ST1VAFE3BX_ODR_FSM_12Hz5;
3826 break;
3827 case 1:
3828 *val = ST1VAFE3BX_ODR_FSM_25Hz;
3829 break;
3830 case 2:
3831 *val = ST1VAFE3BX_ODR_FSM_50Hz;
3832 break;
3833 case 3:
3834 *val = ST1VAFE3BX_ODR_FSM_100Hz;
3835 break;
3836 case 4:
3837 *val = ST1VAFE3BX_ODR_FSM_200Hz;
3838 break;
3839 case 5:
3840 *val = ST1VAFE3BX_ODR_FSM_400Hz;
3841 break;
3842 case 6:
3843 *val = ST1VAFE3BX_ODR_FSM_800Hz;
3844 break;
3845 default:
3846 *val = ST1VAFE3BX_ODR_FSM_12Hz5;
3847 break;
3848 }
3849 }
3850
3851 return ret;
3852 }
3853
3854 /**
3855 * @brief FSM initialization request.[set]
3856 *
3857 * @param ctx Read / write interface definitions.(ptr)
3858 * @param val Change the values of fsm_init in reg FSM_INIT
3859 * @retval Interface status (MANDATORY: return 0 -> no Error).
3860 *
3861 */
st1vafe3bx_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)3862 int32_t st1vafe3bx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
3863 {
3864 st1vafe3bx_emb_func_init_b_t emb_func_init_b;
3865 int32_t ret;
3866
3867 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3868
3869 if (ret == 0)
3870 {
3871 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B,
3872 (uint8_t *)&emb_func_init_b, 1);
3873
3874 emb_func_init_b.fsm_init = (uint8_t)val;
3875
3876 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B,
3877 (uint8_t *)&emb_func_init_b, 1);
3878 }
3879
3880 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3881
3882 return ret;
3883 }
3884
3885 /**
3886 * @brief FSM initialization request.[get]
3887 *
3888 * @param ctx Read / write interface definitions.(ptr)
3889 * @param val Change the values of fsm_init in reg FSM_INIT
3890 * @retval Interface status (MANDATORY: return 0 -> no Error).
3891 *
3892 */
st1vafe3bx_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)3893 int32_t st1vafe3bx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
3894 {
3895 st1vafe3bx_emb_func_init_b_t emb_func_init_b;
3896 int32_t ret;
3897
3898 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3899
3900 if (ret == 0)
3901 {
3902 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_INIT_B,
3903 (uint8_t *)&emb_func_init_b, 1);
3904
3905 *val = emb_func_init_b.fsm_init;
3906 }
3907
3908 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3909
3910 return ret;
3911 }
3912
3913 /**
3914 * @brief FSM FIFO en bit.[set]
3915 *
3916 * @param ctx Read / write interface definitions.(ptr)
3917 * @param val Change the value of fsm_fifo_en in reg ST1VAFE3BX_EMB_FUNC_FIFO_EN
3918 * @retval Interface status (MANDATORY: return 0 -> no Error).
3919 *
3920 */
st1vafe3bx_fsm_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)3921 int32_t st1vafe3bx_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3922 {
3923 st1vafe3bx_emb_func_fifo_en_t fifo_reg;
3924 int32_t ret;
3925
3926 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3927
3928 if (ret == 0)
3929 {
3930 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
3931 (uint8_t *)&fifo_reg, 1);
3932 fifo_reg.fsm_fifo_en = val;
3933 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
3934 (uint8_t *)&fifo_reg, 1);
3935 }
3936
3937 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3938
3939 return ret;
3940 }
3941
3942 /**
3943 * @brief FSM FIFO en bit.[get]
3944 *
3945 * @param ctx Read / write interface definitions.(ptr)
3946 * @param val Get the value of fsm_fifo_en in reg ST1VAFE3BX_EMB_FUNC_FIFO_EN
3947 * @retval Interface status (MANDATORY: return 0 -> no Error).
3948 *
3949 */
st1vafe3bx_fsm_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3950 int32_t st1vafe3bx_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3951 {
3952 st1vafe3bx_emb_func_fifo_en_t fifo_reg;
3953 int32_t ret;
3954
3955 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
3956
3957 if (ret == 0)
3958 {
3959 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
3960 (uint8_t *)&fifo_reg, 1);
3961 *val = fifo_reg.fsm_fifo_en;
3962 }
3963
3964 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
3965
3966 return ret;
3967 }
3968
3969 /**
3970 * @brief FSM long counter timeout register (r/w). The long counter
3971 * timeout value is an unsigned integer value (16-bit format).
3972 * When the long counter value reached this value, the FSM
3973 * generates an interrupt.[set]
3974 *
3975 * @param ctx Read / write interface definitions.(ptr)
3976 * @param buff Buffer that contains data to write
3977 * @retval Interface status (MANDATORY: return 0 -> no Error).
3978 *
3979 */
st1vafe3bx_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)3980 int32_t st1vafe3bx_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
3981 uint16_t val)
3982 {
3983 uint8_t buff[2];
3984 int32_t ret;
3985
3986 buff[1] = (uint8_t)(val / 256U);
3987 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3988 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_FSM_LC_TIMEOUT_L, buff, 2);
3989
3990 return ret;
3991 }
3992
3993 /**
3994 * @brief FSM long counter timeout register (r/w). The long counter
3995 * timeout value is an unsigned integer value (16-bit format).
3996 * When the long counter value reached this value, the FSM generates
3997 * an interrupt.[get]
3998 *
3999 * @param ctx Read / write interface definitions.(ptr)
4000 * @param buff Buffer that stores data read
4001 * @retval Interface status (MANDATORY: return 0 -> no Error).
4002 *
4003 */
st1vafe3bx_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)4004 int32_t st1vafe3bx_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
4005 uint16_t *val)
4006 {
4007 uint8_t buff[2];
4008 int32_t ret;
4009
4010 ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_FSM_LC_TIMEOUT_L, buff, 2);
4011 *val = buff[1];
4012 *val = (*val * 256U) + buff[0];
4013
4014 return ret;
4015 }
4016
4017 /**
4018 * @brief FSM number of programs register.[set]
4019 *
4020 * @param ctx Read / write interface definitions.(ptr)
4021 * @param val Buffer that contains data to write
4022 * @retval Interface status (MANDATORY: return 0 -> no Error).
4023 *
4024 */
st1vafe3bx_fsm_programs_num_set(const stmdev_ctx_t * ctx,uint8_t val)4025 int32_t st1vafe3bx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val)
4026 {
4027 int32_t ret;
4028
4029 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_FSM_PROGRAMS, &val, 1);
4030
4031 return ret;
4032 }
4033
4034 /**
4035 * @brief FSM number of programs register.[get]
4036 *
4037 * @param ctx Read / write interface definitions.(ptr)
4038 * @param val Buffer that stores data read
4039 * @retval Interface status (MANDATORY: return 0 -> no Error).
4040 *
4041 */
st1vafe3bx_fsm_programs_num_get(const stmdev_ctx_t * ctx,uint8_t * val)4042 int32_t st1vafe3bx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val)
4043 {
4044 int32_t ret;
4045
4046 ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_FSM_PROGRAMS, val, 1);
4047
4048 return ret;
4049 }
4050
4051 /**
4052 * @brief FSM start address register (r/w). First available address is
4053 * 0x033C.[set]
4054 *
4055 * @param ctx Read / write interface definitions.(ptr)
4056 * @param buff Buffer that contains data to write
4057 * @retval Interface status (MANDATORY: return 0 -> no Error).
4058 *
4059 */
st1vafe3bx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)4060 int32_t st1vafe3bx_fsm_start_address_set(const stmdev_ctx_t *ctx,
4061 uint16_t val)
4062 {
4063 uint8_t buff[2];
4064 int32_t ret;
4065
4066 buff[1] = (uint8_t)(val / 256U);
4067 buff[0] = (uint8_t)(val - (buff[1] * 256U));
4068 ret = st1vafe3bx_ln_pg_write(ctx, ST1VAFE3BX_FSM_START_ADD_L, buff, 2);
4069
4070 return ret;
4071 }
4072
4073 /**
4074 * @brief FSM start address register (r/w). First available address
4075 * is 0x033C.[get]
4076 *
4077 * @param ctx Read / write interface definitions.(ptr)
4078 * @param buff Buffer that stores data read
4079 * @retval Interface status (MANDATORY: return 0 -> no Error).
4080 *
4081 */
st1vafe3bx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)4082 int32_t st1vafe3bx_fsm_start_address_get(const stmdev_ctx_t *ctx,
4083 uint16_t *val)
4084 {
4085 uint8_t buff[2];
4086 int32_t ret;
4087
4088 ret = st1vafe3bx_ln_pg_read(ctx, ST1VAFE3BX_FSM_START_ADD_L, buff, 2);
4089 *val = buff[1];
4090 *val = (*val * 256U) + buff[0];
4091
4092 return ret;
4093 }
4094
4095 /**
4096 * @}
4097 *
4098 */
4099
4100 /**
4101 * @addtogroup Machine Learning Core
4102 * @brief This section group all the functions concerning the
4103 * usage of Machine Learning Core
4104 * @{
4105 *
4106 */
4107
4108 /**
4109 * @brief Enable Machine Learning Core.[set]
4110 *
4111 * @param ctx read / write interface definitions
4112 * @param val change the values of mlc_en in
4113 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
4114 * in EMB_FUNC_INIT_A
4115 *
4116 */
st1vafe3bx_mlc_set(const stmdev_ctx_t * ctx,st1vafe3bx_mlc_mode_t val)4117 int32_t st1vafe3bx_mlc_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t val)
4118 {
4119 st1vafe3bx_emb_func_en_a_t emb_en_a;
4120 st1vafe3bx_emb_func_en_b_t emb_en_b;
4121 int32_t ret;
4122
4123 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4124
4125 if (ret == 0)
4126 {
4127 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
4128 (uint8_t *)&emb_en_a, 1);
4129 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
4130 (uint8_t *)&emb_en_b, 1);
4131
4132 switch (val)
4133 {
4134 case ST1VAFE3BX_MLC_OFF:
4135 emb_en_a.mlc_before_fsm_en = 0;
4136 emb_en_b.mlc_en = 0;
4137 break;
4138 case ST1VAFE3BX_MLC_ON:
4139 emb_en_a.mlc_before_fsm_en = 0;
4140 emb_en_b.mlc_en = 1;
4141 break;
4142 case ST1VAFE3BX_MLC_ON_BEFORE_FSM:
4143 emb_en_a.mlc_before_fsm_en = 1;
4144 emb_en_b.mlc_en = 0;
4145 break;
4146 default:
4147 /* do nothing */
4148 break;
4149 }
4150
4151 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
4152 (uint8_t *)&emb_en_a, 1);
4153 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
4154 (uint8_t *)&emb_en_b, 1);
4155 }
4156
4157 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4158
4159 return ret;
4160 }
4161
4162 /**
4163 * @brief Enable Machine Learning Core.[get]
4164 *
4165 * @param ctx read / write interface definitions
4166 * @param val get the values of mlc_en in
4167 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
4168 * in EMB_FUNC_INIT_A
4169 *
4170 */
st1vafe3bx_mlc_get(const stmdev_ctx_t * ctx,st1vafe3bx_mlc_mode_t * val)4171 int32_t st1vafe3bx_mlc_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val)
4172 {
4173 st1vafe3bx_emb_func_en_a_t emb_en_a;
4174 st1vafe3bx_emb_func_en_b_t emb_en_b;
4175 int32_t ret;
4176
4177 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4178
4179 if (ret == 0)
4180 {
4181 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_A,
4182 (uint8_t *)&emb_en_a, 1);
4183 ret += st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_EN_B,
4184 (uint8_t *)&emb_en_b, 1);
4185
4186 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
4187 {
4188 *val = ST1VAFE3BX_MLC_OFF;
4189 }
4190 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
4191 {
4192 *val = ST1VAFE3BX_MLC_ON;
4193 }
4194 else if (emb_en_a.mlc_before_fsm_en == 1U)
4195 {
4196 *val = ST1VAFE3BX_MLC_ON_BEFORE_FSM;
4197 }
4198 else
4199 {
4200 /* Do nothing */
4201 }
4202 }
4203
4204 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4205
4206 return ret;
4207 }
4208
4209 /**
4210 * @brief Machine Learning Core status register[get]
4211 *
4212 * @param ctx read / write interface definitions
4213 * @param val register MLC_STATUS_MAINPAGE
4214 *
4215 */
st1vafe3bx_mlc_status_get(const stmdev_ctx_t * ctx,st1vafe3bx_mlc_status_mainpage_t * val)4216 int32_t st1vafe3bx_mlc_status_get(const stmdev_ctx_t *ctx,
4217 st1vafe3bx_mlc_status_mainpage_t *val)
4218 {
4219 return st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_STATUS_MAINPAGE,
4220 (uint8_t *) val, 1);
4221 }
4222
4223 /**
4224 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
4225 *
4226 * @param ctx_t *ctx: read / write interface definitions
4227 * @param uint8_t * : buffer that stores data read
4228 *
4229 */
st1vafe3bx_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)4230 int32_t st1vafe3bx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
4231 {
4232 int32_t ret;
4233
4234 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4235
4236 if (ret == 0)
4237 {
4238 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC1_SRC, buff, 4);
4239 }
4240
4241 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4242
4243 return ret;
4244 }
4245
4246 /**
4247 * @brief Machine Learning Core data rate selection.[set]
4248 *
4249 * @param ctx read / write interface definitions
4250 * @param val get the values of mlc_odr in
4251 * reg EMB_FUNC_ODR_CFG_C
4252 *
4253 */
st1vafe3bx_mlc_data_rate_set(const stmdev_ctx_t * ctx,st1vafe3bx_mlc_odr_val_t val)4254 int32_t st1vafe3bx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
4255 st1vafe3bx_mlc_odr_val_t val)
4256 {
4257 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
4258 st1vafe3bx_mlc_odr_t reg;
4259 int32_t ret = 0;
4260
4261 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
4262 (uint8_t *)&ah_bio_cfg2, 1);
4263 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4264
4265 if (ret == 0)
4266 {
4267 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1);
4268
4269 reg.mlc_odr = (uint8_t)val & 0xfU;
4270 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1);
4271 }
4272
4273 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4274
4275 return ret;
4276 }
4277
4278 /**
4279 * @brief Machine Learning Core data rate selection.[get]
4280 *
4281 * @param ctx read / write interface definitions
4282 * @param val change the values of mlc_odr in
4283 * reg EMB_FUNC_ODR_CFG_C
4284 *
4285 */
st1vafe3bx_mlc_data_rate_get(const stmdev_ctx_t * ctx,st1vafe3bx_mlc_odr_val_t * val)4286 int32_t st1vafe3bx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
4287 st1vafe3bx_mlc_odr_val_t *val)
4288 {
4289 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2;
4290 st1vafe3bx_mlc_odr_t reg;
4291 int32_t ret = 0;
4292
4293 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_AH_BIO_CFG2,
4294 (uint8_t *)&ah_bio_cfg2, 1);
4295 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4296
4297 if (ret == 0)
4298 {
4299 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_MLC_ODR, (uint8_t *)®, 1);
4300
4301 /* depends on vAFE mode only enabled */
4302 if (ah_bio_cfg2.ah_bio_en == 0x1U)
4303 {
4304 switch (reg.mlc_odr)
4305 {
4306 case 0:
4307 *val = ST1VAFE3BX_ODR_PRGS_VAFE_50Hz;
4308 break;
4309 case 1:
4310 *val = ST1VAFE3BX_ODR_PRGS_VAFE_100Hz;
4311 break;
4312 case 2:
4313 *val = ST1VAFE3BX_ODR_PRGS_VAFE_200Hz;
4314 break;
4315 case 3:
4316 *val = ST1VAFE3BX_ODR_PRGS_VAFE_400Hz;
4317 break;
4318 case 4:
4319 *val = ST1VAFE3BX_ODR_PRGS_VAFE_800Hz;
4320 break;
4321 case 5:
4322 *val = ST1VAFE3BX_ODR_PRGS_VAFE_1600Hz;
4323 break;
4324 default:
4325 *val = ST1VAFE3BX_ODR_PRGS_VAFE_50Hz;
4326 break;
4327 }
4328 }
4329 else
4330 {
4331 switch (reg.mlc_odr)
4332 {
4333 case 0:
4334 *val = ST1VAFE3BX_ODR_PRGS_12Hz5;
4335 break;
4336 case 1:
4337 *val = ST1VAFE3BX_ODR_PRGS_25Hz;
4338 break;
4339 case 2:
4340 *val = ST1VAFE3BX_ODR_PRGS_50Hz;
4341 break;
4342 case 3:
4343 *val = ST1VAFE3BX_ODR_PRGS_100Hz;
4344 break;
4345 case 4:
4346 *val = ST1VAFE3BX_ODR_PRGS_200Hz;
4347 break;
4348 default:
4349 *val = ST1VAFE3BX_ODR_PRGS_12Hz5;
4350 break;
4351 }
4352 }
4353 }
4354
4355 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4356
4357 return ret;
4358 }
4359
4360 /**
4361 * @brief MLC FIFO en bit.[set]
4362 *
4363 * @param ctx Read / write interface definitions.(ptr)
4364 * @param val Change the value of mlc_fifo_en in reg ST1VAFE3BX_EMB_FUNC_FIFO_EN
4365 * @retval Interface status (MANDATORY: return 0 -> no Error).
4366 *
4367 */
st1vafe3bx_mlc_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)4368 int32_t st1vafe3bx_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
4369 {
4370 st1vafe3bx_emb_func_fifo_en_t fifo_reg;
4371 int32_t ret;
4372
4373 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4374
4375 if (ret == 0)
4376 {
4377 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
4378 (uint8_t *)&fifo_reg, 1);
4379 fifo_reg.mlc_fifo_en = val;
4380 ret += st1vafe3bx_write_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
4381 (uint8_t *)&fifo_reg, 1);
4382 }
4383
4384 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4385
4386 return ret;
4387 }
4388
4389 /**
4390 * @brief MLC FIFO en bit.[get]
4391 *
4392 * @param ctx Read / write interface definitions.(ptr)
4393 * @param val Get the value of mlc_fifo_en in reg ST1VAFE3BX_EMB_FUNC_FIFO_EN
4394 * @retval Interface status (MANDATORY: return 0 -> no Error).
4395 *
4396 */
st1vafe3bx_mlc_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)4397 int32_t st1vafe3bx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
4398 {
4399 st1vafe3bx_emb_func_fifo_en_t fifo_reg;
4400 int32_t ret;
4401
4402 ret = st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_EMBED_FUNC_MEM_BANK);
4403
4404 if (ret == 0)
4405 {
4406 ret = st1vafe3bx_read_reg(ctx, ST1VAFE3BX_EMB_FUNC_FIFO_EN,
4407 (uint8_t *)&fifo_reg, 1);
4408 *val = fifo_reg.mlc_fifo_en;
4409 }
4410
4411 ret += st1vafe3bx_mem_bank_set(ctx, ST1VAFE3BX_MAIN_MEM_BANK);
4412
4413 return ret;
4414 }
4415
4416 /**
4417 * @}
4418 *
4419 */
4420
4421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4422
