1 /** 2 ****************************************************************************** 3 * @file lsm9ds1_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm9ds1_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM9DS1_REGS_H 23 #define LSM9DS1_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM9DS1 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM9DS1_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0xD5 if SA0=1 -> 0xD7 **/ 172 #define LSM9DS1_IMU_I2C_ADD_L 0xD5U 173 #define LSM9DS1_IMU_I2C_ADD_H 0xD7U 174 175 /** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x39 **/ 176 #define LSM9DS1_MAG_I2C_ADD_L 0x39U 177 #define LSM9DS1_MAG_I2C_ADD_H 0x3DU 178 179 /** Device Identification (Who am I) **/ 180 #define LSM9DS1_IMU_ID 0x68U 181 182 /** Device Identification (Who am I) **/ 183 #define LSM9DS1_MAG_ID 0x3DU 184 185 /** 186 * @} 187 * 188 */ 189 190 #define LSM9DS1_ACT_THS 0x04U 191 typedef struct 192 { 193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 194 uint8_t act_ths : 7; 195 uint8_t sleep_on_inact_en : 1; 196 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 197 uint8_t sleep_on_inact_en : 1; 198 uint8_t act_ths : 7; 199 #endif /* DRV_BYTE_ORDER */ 200 } lsm9ds1_act_ths_t; 201 202 #define LSM9DS1_ACT_DUR 0x05U 203 #define LSM9DS1_INT_GEN_CFG_XL 0x06U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t xlie_xl : 1; 208 uint8_t xhie_xl : 1; 209 uint8_t ylie_xl : 1; 210 uint8_t yhie_xl : 1; 211 uint8_t zlie_xl : 1; 212 uint8_t zhie_xl : 1; 213 uint8_t _6d : 1; 214 uint8_t aoi_xl : 1; 215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 216 uint8_t aoi_xl : 1; 217 uint8_t _6d : 1; 218 uint8_t zhie_xl : 1; 219 uint8_t zlie_xl : 1; 220 uint8_t yhie_xl : 1; 221 uint8_t ylie_xl : 1; 222 uint8_t xhie_xl : 1; 223 uint8_t xlie_xl : 1; 224 #endif /* DRV_BYTE_ORDER */ 225 } lsm9ds1_int_gen_cfg_xl_t; 226 227 #define LSM9DS1_INT_GEN_THS_X_XL 0x07U 228 #define LSM9DS1_INT_GEN_THS_Y_XL 0x08U 229 #define LSM9DS1_INT_GEN_THS_Z_XL 0x09U 230 #define LSM9DS1_INT_GEN_DUR_XL 0x0AU 231 typedef struct 232 { 233 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 234 uint8_t dur_xl : 7; 235 uint8_t wait_xl : 1; 236 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 237 uint8_t wait_xl : 1; 238 uint8_t dur_xl : 7; 239 #endif /* DRV_BYTE_ORDER */ 240 } lsm9ds1_int_gen_dur_xl_t; 241 242 #define LSM9DS1_REFERENCE_G 0x0BU 243 #define LSM9DS1_INT1_CTRL 0x0CU 244 typedef struct 245 { 246 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 247 uint8_t int1_drdy_xl : 1; 248 uint8_t int1_drdy_g : 1; 249 uint8_t int1_boot : 1; 250 uint8_t int1_fth : 1; 251 uint8_t int1_ovr : 1; 252 uint8_t int1_fss5 : 1; 253 uint8_t int1_ig_xl : 1; 254 uint8_t int1_ig_g : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t int1_ig_g : 1; 257 uint8_t int1_ig_xl : 1; 258 uint8_t int1_fss5 : 1; 259 uint8_t int1_ovr : 1; 260 uint8_t int1_fth : 1; 261 uint8_t int1_boot : 1; 262 uint8_t int1_drdy_g : 1; 263 uint8_t int1_drdy_xl : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } lsm9ds1_int1_ctrl_t; 266 267 #define LSM9DS1_INT2_CTRL 0x0DU 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t int2_drdy_xl : 1; 272 uint8_t int2_drdy_g : 1; 273 uint8_t int2_drdy_temp : 1; 274 uint8_t int2_fth : 1; 275 uint8_t int2_ovr : 1; 276 uint8_t int2_fss5 : 1; 277 uint8_t not_used_01 : 1; 278 uint8_t int2_inact : 1; 279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 280 uint8_t int2_inact : 1; 281 uint8_t not_used_01 : 1; 282 uint8_t int2_fss5 : 1; 283 uint8_t int2_ovr : 1; 284 uint8_t int2_fth : 1; 285 uint8_t int2_drdy_temp : 1; 286 uint8_t int2_drdy_g : 1; 287 uint8_t int2_drdy_xl : 1; 288 #endif /* DRV_BYTE_ORDER */ 289 } lsm9ds1_int2_ctrl_t; 290 291 #define LSM9DS1_WHO_AM_I 0x0FU 292 #define LSM9DS1_CTRL_REG1_G 0x10U 293 typedef struct 294 { 295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 296 uint8_t bw_g : 2; 297 uint8_t not_used_01 : 1; 298 uint8_t fs_g : 2; 299 uint8_t odr_g : 3; 300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 301 uint8_t odr_g : 3; 302 uint8_t fs_g : 2; 303 uint8_t not_used_01 : 1; 304 uint8_t bw_g : 2; 305 #endif /* DRV_BYTE_ORDER */ 306 } lsm9ds1_ctrl_reg1_g_t; 307 308 #define LSM9DS1_CTRL_REG2_G 0x11U 309 typedef struct 310 { 311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 312 uint8_t out_sel : 2; 313 uint8_t int_sel : 2; 314 uint8_t not_used_01 : 4; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t not_used_01 : 4; 317 uint8_t int_sel : 2; 318 uint8_t out_sel : 2; 319 #endif /* DRV_BYTE_ORDER */ 320 } lsm9ds1_ctrl_reg2_g_t; 321 322 #define LSM9DS1_CTRL_REG3_G 0x12U 323 typedef struct 324 { 325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 326 uint8_t hpcf_g : 4; 327 uint8_t not_used_01 : 2; 328 uint8_t hp_en : 1; 329 uint8_t lp_mode : 1; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t lp_mode : 1; 332 uint8_t hp_en : 1; 333 uint8_t not_used_01 : 2; 334 uint8_t hpcf_g : 4; 335 #endif /* DRV_BYTE_ORDER */ 336 } lsm9ds1_ctrl_reg3_g_t; 337 338 #define LSM9DS1_ORIENT_CFG_G 0x13U 339 typedef struct 340 { 341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 342 uint8_t orient : 3; 343 uint8_t signz_g : 1; 344 uint8_t signy_g : 1; 345 uint8_t signx_g : 1; 346 uint8_t not_used_01 : 2; 347 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 348 uint8_t not_used_01 : 2; 349 uint8_t signx_g : 1; 350 uint8_t signy_g : 1; 351 uint8_t signz_g : 1; 352 uint8_t orient : 3; 353 #endif /* DRV_BYTE_ORDER */ 354 } lsm9ds1_orient_cfg_g_t; 355 356 #define LSM9DS1_INT_GEN_SRC_G 0x14U 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t xl_g : 1; 361 uint8_t xh_g : 1; 362 uint8_t yl_g : 1; 363 uint8_t yh_g : 1; 364 uint8_t zl_g : 1; 365 uint8_t zh_g : 1; 366 uint8_t ia_g : 1; 367 uint8_t not_used_01 : 1; 368 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 369 uint8_t not_used_01 : 1; 370 uint8_t ia_g : 1; 371 uint8_t zh_g : 1; 372 uint8_t zl_g : 1; 373 uint8_t yh_g : 1; 374 uint8_t yl_g : 1; 375 uint8_t xh_g : 1; 376 uint8_t xl_g : 1; 377 #endif /* DRV_BYTE_ORDER */ 378 } lsm9ds1_int_gen_src_g_t; 379 380 #define LSM9DS1_OUT_TEMP_L 0x15U 381 #define LSM9DS1_OUT_TEMP_H 0x16U 382 #define LSM9DS1_STATUS_REG 0x17U 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t xlda : 1; 387 uint8_t gda : 1; 388 uint8_t tda : 1; 389 uint8_t boot_status : 1; 390 uint8_t inact : 1; 391 uint8_t ig_g : 1; 392 uint8_t ig_xl : 1; 393 uint8_t not_used_01 : 1; 394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 395 uint8_t not_used_01 : 1; 396 uint8_t ig_xl : 1; 397 uint8_t ig_g : 1; 398 uint8_t inact : 1; 399 uint8_t boot_status : 1; 400 uint8_t tda : 1; 401 uint8_t gda : 1; 402 uint8_t xlda : 1; 403 #endif /* DRV_BYTE_ORDER */ 404 } lsm9ds1_status_reg_t; 405 406 #define LSM9DS1_OUT_X_L_G 0x18U 407 #define LSM9DS1_OUT_X_H_G 0x19U 408 #define LSM9DS1_OUT_Y_L_G 0x1AU 409 #define LSM9DS1_OUT_Y_H_G 0x1BU 410 #define LSM9DS1_OUT_Z_L_G 0x1CU 411 #define LSM9DS1_OUT_Z_H_G 0x1DU 412 #define LSM9DS1_CTRL_REG4 0x1EU 413 typedef struct 414 { 415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 416 uint8_t _4d_xl1 : 1; 417 uint8_t lir_xl1 : 1; 418 uint8_t not_used_01 : 1; 419 uint8_t xen_g : 1; 420 uint8_t yen_g : 1; 421 uint8_t zen_g : 1; 422 uint8_t not_used_02 : 2; 423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 424 uint8_t not_used_02 : 2; 425 uint8_t zen_g : 1; 426 uint8_t yen_g : 1; 427 uint8_t xen_g : 1; 428 uint8_t not_used_01 : 1; 429 uint8_t lir_xl1 : 1; 430 uint8_t _4d_xl1 : 1; 431 #endif /* DRV_BYTE_ORDER */ 432 } lsm9ds1_ctrl_reg4_t; 433 434 #define LSM9DS1_CTRL_REG5_XL 0x1FU 435 typedef struct 436 { 437 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 438 uint8_t not_used_01 : 3; 439 uint8_t xen_xl : 1; 440 uint8_t yen_xl : 1; 441 uint8_t zen_xl : 1; 442 uint8_t dec : 2; 443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 444 uint8_t dec : 2; 445 uint8_t zen_xl : 1; 446 uint8_t yen_xl : 1; 447 uint8_t xen_xl : 1; 448 uint8_t not_used_01 : 3; 449 #endif /* DRV_BYTE_ORDER */ 450 } lsm9ds1_ctrl_reg5_xl_t; 451 452 #define LSM9DS1_CTRL_REG6_XL 0x20U 453 typedef struct 454 { 455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 456 uint8_t bw_xl : 2; 457 uint8_t bw_scal_odr : 1; 458 uint8_t fs_xl : 2; 459 uint8_t odr_xl : 3; 460 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 461 uint8_t odr_xl : 3; 462 uint8_t fs_xl : 2; 463 uint8_t bw_scal_odr : 1; 464 uint8_t bw_xl : 2; 465 #endif /* DRV_BYTE_ORDER */ 466 } lsm9ds1_ctrl_reg6_xl_t; 467 468 #define LSM9DS1_CTRL_REG7_XL 0x21U 469 typedef struct 470 { 471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 472 uint8_t hpis1 : 1; 473 uint8_t not_used_01 : 1; 474 uint8_t fds : 1; 475 uint8_t not_used_02 : 2; 476 uint8_t dcf : 2; 477 uint8_t hr : 1; 478 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 479 uint8_t hr : 1; 480 uint8_t dcf : 2; 481 uint8_t not_used_02 : 2; 482 uint8_t fds : 1; 483 uint8_t not_used_01 : 1; 484 uint8_t hpis1 : 1; 485 #endif /* DRV_BYTE_ORDER */ 486 } lsm9ds1_ctrl_reg7_xl_t; 487 488 #define LSM9DS1_CTRL_REG8 0x22U 489 typedef struct 490 { 491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 492 uint8_t sw_reset : 1; 493 uint8_t ble : 1; 494 uint8_t if_add_inc : 1; 495 uint8_t sim : 1; 496 uint8_t pp_od : 1; 497 uint8_t h_lactive : 1; 498 uint8_t bdu : 1; 499 uint8_t boot : 1; 500 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 501 uint8_t boot : 1; 502 uint8_t bdu : 1; 503 uint8_t h_lactive : 1; 504 uint8_t pp_od : 1; 505 uint8_t sim : 1; 506 uint8_t if_add_inc : 1; 507 uint8_t ble : 1; 508 uint8_t sw_reset : 1; 509 #endif /* DRV_BYTE_ORDER */ 510 } lsm9ds1_ctrl_reg8_t; 511 512 #define LSM9DS1_CTRL_REG9 0x23U 513 typedef struct 514 { 515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 516 uint8_t stop_on_fth : 1; 517 uint8_t fifo_en : 1; 518 uint8_t i2c_disable : 1; 519 uint8_t drdy_mask_bit : 1; 520 uint8_t fifo_temp_en : 1; 521 uint8_t not_used_01 : 1; 522 uint8_t sleep_g : 1; 523 uint8_t not_used_02 : 1; 524 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 525 uint8_t not_used_02 : 1; 526 uint8_t sleep_g : 1; 527 uint8_t not_used_01 : 1; 528 uint8_t fifo_temp_en : 1; 529 uint8_t drdy_mask_bit : 1; 530 uint8_t i2c_disable : 1; 531 uint8_t fifo_en : 1; 532 uint8_t stop_on_fth : 1; 533 #endif /* DRV_BYTE_ORDER */ 534 } lsm9ds1_ctrl_reg9_t; 535 536 #define LSM9DS1_CTRL_REG10 0x24U 537 typedef struct 538 { 539 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 540 uint8_t st_xl : 1; 541 uint8_t not_used_01 : 1; 542 uint8_t st_g : 1; 543 uint8_t not_used_02 : 5; 544 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 545 uint8_t not_used_02 : 5; 546 uint8_t st_g : 1; 547 uint8_t not_used_01 : 1; 548 uint8_t st_xl : 1; 549 #endif /* DRV_BYTE_ORDER */ 550 } lsm9ds1_ctrl_reg10_t; 551 552 #define LSM9DS1_INT_GEN_SRC_XL 0x26U 553 typedef struct 554 { 555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 556 uint8_t xl_xl : 1; 557 uint8_t xh_xl : 1; 558 uint8_t yl_xl : 1; 559 uint8_t yh_xl : 1; 560 uint8_t zl_xl : 1; 561 uint8_t zh_xl : 1; 562 uint8_t ia_xl : 1; 563 uint8_t not_used_01 : 1; 564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 565 uint8_t not_used_01 : 1; 566 uint8_t ia_xl : 1; 567 uint8_t zh_xl : 1; 568 uint8_t zl_xl : 1; 569 uint8_t yh_xl : 1; 570 uint8_t yl_xl : 1; 571 uint8_t xh_xl : 1; 572 uint8_t xl_xl : 1; 573 #endif /* DRV_BYTE_ORDER */ 574 } lsm9ds1_int_gen_src_xl_t; 575 576 #define LSM9DS1_OUT_X_L_XL 0x28U 577 #define LSM9DS1_OUT_X_H_XL 0x29U 578 #define LSM9DS1_OUT_Y_L_XL 0x2AU 579 #define LSM9DS1_OUT_Y_H_XL 0x2BU 580 #define LSM9DS1_OUT_Z_L_XL 0x2CU 581 #define LSM9DS1_OUT_Z_H_XL 0x2DU 582 #define LSM9DS1_FIFO_CTRL 0x2EU 583 typedef struct 584 { 585 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 586 uint8_t fth : 5; 587 uint8_t fmode : 3; 588 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 589 uint8_t fmode : 3; 590 uint8_t fth : 5; 591 #endif /* DRV_BYTE_ORDER */ 592 } lsm9ds1_fifo_ctrl_t; 593 594 #define LSM9DS1_FIFO_SRC 0x2FU 595 typedef struct 596 { 597 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 598 uint8_t fss : 6; 599 uint8_t ovrn : 1; 600 uint8_t fth : 1; 601 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 602 uint8_t fth : 1; 603 uint8_t ovrn : 1; 604 uint8_t fss : 6; 605 #endif /* DRV_BYTE_ORDER */ 606 } lsm9ds1_fifo_src_t; 607 608 #define LSM9DS1_INT_GEN_CFG_G 0x30U 609 typedef struct 610 { 611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 612 uint8_t xlie_g : 1; 613 uint8_t xhie_g : 1; 614 uint8_t ylie_g : 1; 615 uint8_t yhie_g : 1; 616 uint8_t zlie_g : 1; 617 uint8_t zhie_g : 1; 618 uint8_t lir_g : 1; 619 uint8_t aoi_g : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t aoi_g : 1; 622 uint8_t lir_g : 1; 623 uint8_t zhie_g : 1; 624 uint8_t zlie_g : 1; 625 uint8_t yhie_g : 1; 626 uint8_t ylie_g : 1; 627 uint8_t xhie_g : 1; 628 uint8_t xlie_g : 1; 629 #endif /* DRV_BYTE_ORDER */ 630 } lsm9ds1_int_gen_cfg_g_t; 631 632 #define LSM9DS1_INT_GEN_THS_XH_G 0x31U 633 typedef struct 634 { 635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 636 uint8_t ths_g_x : 7; 637 uint8_t dcrm_g : 1; 638 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 639 uint8_t dcrm_g : 1; 640 uint8_t ths_g_x : 7; 641 #endif /* DRV_BYTE_ORDER */ 642 } lsm9ds1_int_gen_ths_xh_g_t; 643 644 #define LSM9DS1_INT_GEN_THS_XL_G 0x32U 645 typedef struct 646 { 647 uint8_t ths_g_x : 8; 648 } lsm9ds1_int_gen_ths_xl_g_t; 649 #define LSM9DS1_INT_GEN_THS_YH_G 0x33U 650 typedef struct 651 { 652 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 653 uint8_t ths_g_y : 7; 654 uint8_t not_used_01 : 1; 655 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 656 uint8_t not_used_01 : 1; 657 uint8_t ths_g_y : 7; 658 #endif /* DRV_BYTE_ORDER */ 659 } lsm9ds1_int_gen_ths_yh_g_t; 660 661 #define LSM9DS1_INT_GEN_THS_YL_G 0x34U 662 typedef struct 663 { 664 uint8_t ths_g_y : 8; 665 } lsm9ds1_int_gen_ths_yl_g_t; 666 #define LSM9DS1_INT_GEN_THS_ZH_G 0x35U 667 typedef struct 668 { 669 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 670 uint8_t ths_g_z : 7; 671 uint8_t not_used_01 : 1; 672 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 673 uint8_t not_used_01 : 1; 674 uint8_t ths_g_z : 7; 675 #endif /* DRV_BYTE_ORDER */ 676 } lsm9ds1_int_gen_ths_zh_g_t; 677 678 #define LSM9DS1_INT_GEN_THS_ZL_G 0x36U 679 typedef struct 680 { 681 uint8_t ths_g_z : 8; 682 } lsm9ds1_int_gen_ths_zl_g_t; 683 #define LSM9DS1_INT_GEN_DUR_G 0x37U 684 typedef struct 685 { 686 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 687 uint8_t dur_g : 7; 688 uint8_t wait_g : 1; 689 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 690 uint8_t wait_g : 1; 691 uint8_t dur_g : 7; 692 #endif /* DRV_BYTE_ORDER */ 693 } lsm9ds1_int_gen_dur_g_t; 694 695 #define LSM9DS1_OFFSET_X_REG_L_M 0x05U 696 #define LSM9DS1_OFFSET_X_REG_H_M 0x06U 697 #define LSM9DS1_OFFSET_Y_REG_L_M 0x07U 698 #define LSM9DS1_OFFSET_Y_REG_H_M 0x08U 699 #define LSM9DS1_OFFSET_Z_REG_L_M 0x09U 700 #define LSM9DS1_OFFSET_Z_REG_H_M 0x0AU 701 702 #define LSM9DS1_WHO_AM_I_M 0x0FU 703 #define LSM9DS1_CTRL_REG1_M 0x20U 704 typedef struct 705 { 706 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 707 uint8_t st : 1; 708 uint8_t fast_odr : 1; 709 uint8_t _do : 3; 710 uint8_t om : 2; 711 uint8_t temp_comp : 1; 712 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 713 uint8_t temp_comp : 1; 714 uint8_t om : 2; 715 uint8_t _do : 3; 716 uint8_t fast_odr : 1; 717 uint8_t st : 1; 718 #endif /* DRV_BYTE_ORDER */ 719 } lsm9ds1_ctrl_reg1_m_t; 720 721 #define LSM9DS1_CTRL_REG2_M 0x21U 722 typedef struct 723 { 724 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 725 uint8_t not_used_01 : 2; 726 uint8_t soft_rst : 1; 727 uint8_t reboot : 1; 728 uint8_t not_used_02 : 1; 729 uint8_t fs : 2; 730 uint8_t not_used_03 : 1; 731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 732 uint8_t not_used_03 : 1; 733 uint8_t fs : 2; 734 uint8_t not_used_02 : 1; 735 uint8_t reboot : 1; 736 uint8_t soft_rst : 1; 737 uint8_t not_used_01 : 2; 738 #endif /* DRV_BYTE_ORDER */ 739 } lsm9ds1_ctrl_reg2_m_t; 740 741 #define LSM9DS1_CTRL_REG3_M 0x22U 742 typedef struct 743 { 744 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 745 uint8_t md : 2; 746 uint8_t sim : 1; 747 uint8_t not_used_01 : 2; 748 uint8_t lp : 1; 749 uint8_t not_used_02 : 1; 750 uint8_t i2c_disable : 1; 751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 752 uint8_t i2c_disable : 1; 753 uint8_t not_used_02 : 1; 754 uint8_t lp : 1; 755 uint8_t not_used_01 : 2; 756 uint8_t sim : 1; 757 uint8_t md : 2; 758 #endif /* DRV_BYTE_ORDER */ 759 } lsm9ds1_ctrl_reg3_m_t; 760 761 #define LSM9DS1_CTRL_REG4_M 0x23U 762 typedef struct 763 { 764 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 765 uint8_t not_used_01 : 1; 766 uint8_t ble : 1; 767 uint8_t omz : 2; 768 uint8_t not_used_02 : 4; 769 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 770 uint8_t not_used_02 : 4; 771 uint8_t omz : 2; 772 uint8_t ble : 1; 773 uint8_t not_used_01 : 1; 774 #endif /* DRV_BYTE_ORDER */ 775 } lsm9ds1_ctrl_reg4_m_t; 776 777 #define LSM9DS1_CTRL_REG5_M 0x24U 778 typedef struct 779 { 780 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 781 uint8_t not_used_01 : 6; 782 uint8_t bdu : 1; 783 uint8_t fast_read : 1; 784 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 785 uint8_t fast_read : 1; 786 uint8_t bdu : 1; 787 uint8_t not_used_01 : 6; 788 #endif /* DRV_BYTE_ORDER */ 789 } lsm9ds1_ctrl_reg5_m_t; 790 791 #define LSM9DS1_STATUS_REG_M 0x27U 792 typedef struct 793 { 794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 795 uint8_t xda : 1; 796 uint8_t yda : 1; 797 uint8_t zda : 1; 798 uint8_t zyxda : 1; 799 uint8_t _xor : 1; 800 uint8_t yor : 1; 801 uint8_t zor : 1; 802 uint8_t zyxor : 1; 803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 804 uint8_t zyxor : 1; 805 uint8_t zor : 1; 806 uint8_t yor : 1; 807 uint8_t _xor : 1; 808 uint8_t zyxda : 1; 809 uint8_t zda : 1; 810 uint8_t yda : 1; 811 uint8_t xda : 1; 812 #endif /* DRV_BYTE_ORDER */ 813 } lsm9ds1_status_reg_m_t; 814 815 #define LSM9DS1_OUT_X_L_M 0x28U 816 #define LSM9DS1_OUT_X_H_M 0x29U 817 #define LSM9DS1_OUT_Y_L_M 0x2AU 818 #define LSM9DS1_OUT_Y_H_M 0x2BU 819 #define LSM9DS1_OUT_Z_L_M 0x2CU 820 #define LSM9DS1_OUT_Z_H_M 0x2DU 821 #define LSM9DS1_INT_CFG_M 0x30U 822 typedef struct 823 { 824 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 825 uint8_t ien : 1; 826 uint8_t iel : 1; 827 uint8_t iea : 1; 828 uint8_t not_used_01 : 2; 829 uint8_t zien : 1; 830 uint8_t yien : 1; 831 uint8_t xien : 1; 832 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 833 uint8_t xien : 1; 834 uint8_t yien : 1; 835 uint8_t zien : 1; 836 uint8_t not_used_01 : 2; 837 uint8_t iea : 1; 838 uint8_t iel : 1; 839 uint8_t ien : 1; 840 #endif /* DRV_BYTE_ORDER */ 841 } lsm9ds1_int_cfg_m_t; 842 843 #define LSM9DS1_INT_SRC_M 0x31U 844 typedef struct 845 { 846 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 847 uint8_t _int : 1; 848 uint8_t mroi : 1; 849 uint8_t nth_z : 1; 850 uint8_t nth_y : 1; 851 uint8_t nth_x : 1; 852 uint8_t pth_z : 1; 853 uint8_t pth_y : 1; 854 uint8_t pth_x : 1; 855 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 856 uint8_t pth_x : 1; 857 uint8_t pth_y : 1; 858 uint8_t pth_z : 1; 859 uint8_t nth_x : 1; 860 uint8_t nth_y : 1; 861 uint8_t nth_z : 1; 862 uint8_t mroi : 1; 863 uint8_t _int : 1; 864 #endif /* DRV_BYTE_ORDER */ 865 } lsm9ds1_int_src_m_t; 866 867 #define LSM9DS1_INT_THS_L_M 0x32U 868 typedef struct 869 { 870 uint8_t ths : 8; 871 } lsm9ds1_int_ths_l_m_t; 872 873 #define LSM9DS1_INT_THS_H_M 0x33U 874 typedef struct 875 { 876 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 877 uint8_t ths : 7; 878 uint8_t not_used_01 : 1; 879 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 880 uint8_t not_used_01 : 1; 881 uint8_t ths : 7; 882 #endif /* DRV_BYTE_ORDER */ 883 } lsm9ds1_int_ths_h_m_t; 884 885 /** 886 * @defgroup LSM9DS1_Register_Union 887 * @brief This union group all the registers having a bit-field 888 * description. 889 * This union is useful but it's not needed by the driver. 890 * 891 * REMOVING this union you are compliant with: 892 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 893 * 894 * @{ 895 * 896 */ 897 typedef union 898 { 899 lsm9ds1_act_ths_t act_ths; 900 lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; 901 lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl; 902 lsm9ds1_int1_ctrl_t int1_ctrl; 903 lsm9ds1_int2_ctrl_t int2_ctrl; 904 lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; 905 lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g; 906 lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g; 907 lsm9ds1_orient_cfg_g_t orient_cfg_g; 908 lsm9ds1_int_gen_src_g_t int_gen_src_g; 909 lsm9ds1_status_reg_t status_reg; 910 lsm9ds1_ctrl_reg4_t ctrl_reg4; 911 lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl; 912 lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl; 913 lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; 914 lsm9ds1_ctrl_reg8_t ctrl_reg8; 915 lsm9ds1_ctrl_reg9_t ctrl_reg9; 916 lsm9ds1_ctrl_reg10_t ctrl_reg10; 917 lsm9ds1_int_gen_src_xl_t int_gen_src_xl; 918 lsm9ds1_fifo_ctrl_t fifo_ctrl; 919 lsm9ds1_fifo_src_t fifo_src; 920 lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g; 921 lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g; 922 lsm9ds1_int_gen_ths_xl_g_t int_gen_ths_xl_g; 923 lsm9ds1_int_gen_ths_yh_g_t int_gen_ths_yh_g; 924 lsm9ds1_int_gen_ths_yl_g_t int_gen_ths_yl_g; 925 lsm9ds1_int_gen_ths_zh_g_t int_gen_ths_zh_g; 926 lsm9ds1_int_gen_ths_zl_g_t int_gen_ths_zl_g; 927 lsm9ds1_int_gen_dur_g_t int_gen_dur_g; 928 lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m; 929 lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m; 930 lsm9ds1_ctrl_reg3_m_t ctrl_reg3_m; 931 lsm9ds1_ctrl_reg4_m_t ctrl_reg4_m; 932 lsm9ds1_ctrl_reg5_m_t ctrl_reg5_m; 933 lsm9ds1_status_reg_m_t status_reg_m; 934 lsm9ds1_int_cfg_m_t int_cfg_m; 935 lsm9ds1_int_src_m_t int_src_m; 936 lsm9ds1_int_ths_l_m_t int_ths_l_m; 937 lsm9ds1_int_ths_h_m_t int_ths_h_m; 938 bitwise_t bitwise; 939 uint8_t byte; 940 } lsm9ds1_reg_t; 941 942 /** 943 * @} 944 * 945 */ 946 947 #ifndef __weak 948 #define __weak __attribute__((weak)) 949 #endif /* __weak */ 950 951 /* 952 * These are the basic platform dependent I/O routines to read 953 * and write device registers connected on a standard bus. 954 * The driver keeps offering a default implementation based on function 955 * pointers to read/write routines for backward compatibility. 956 * The __weak directive allows the final application to overwrite 957 * them with a custom implementation. 958 */ 959 960 int32_t lsm9ds1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 961 uint8_t *data, 962 uint16_t len); 963 int32_t lsm9ds1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 964 uint8_t *data, 965 uint16_t len); 966 967 float_t lsm9ds1_from_fs2g_to_mg(int16_t lsb); 968 float_t lsm9ds1_from_fs4g_to_mg(int16_t lsb); 969 float_t lsm9ds1_from_fs8g_to_mg(int16_t lsb); 970 float_t lsm9ds1_from_fs16g_to_mg(int16_t lsb); 971 972 float_t lsm9ds1_from_fs245dps_to_mdps(int16_t lsb); 973 float_t lsm9ds1_from_fs500dps_to_mdps(int16_t lsb); 974 float_t lsm9ds1_from_fs2000dps_to_mdps(int16_t lsb); 975 976 float_t lsm9ds1_from_fs4gauss_to_mG(int16_t lsb); 977 float_t lsm9ds1_from_fs8gauss_to_mG(int16_t lsb); 978 float_t lsm9ds1_from_fs12gauss_to_mG(int16_t lsb); 979 float_t lsm9ds1_from_fs16gauss_to_mG(int16_t lsb); 980 981 float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb); 982 983 typedef enum 984 { 985 LSM9DS1_245dps = 0, 986 LSM9DS1_500dps = 1, 987 LSM9DS1_2000dps = 3, 988 } lsm9ds1_gy_fs_t; 989 int32_t lsm9ds1_gy_full_scale_set(const stmdev_ctx_t *ctx, 990 lsm9ds1_gy_fs_t val); 991 int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx, 992 lsm9ds1_gy_fs_t *val); 993 994 typedef enum 995 { 996 LSM9DS1_IMU_OFF = 0x00, 997 LSM9DS1_GY_OFF_XL_10Hz = 0x10, 998 LSM9DS1_GY_OFF_XL_50Hz = 0x20, 999 LSM9DS1_GY_OFF_XL_119Hz = 0x30, 1000 LSM9DS1_GY_OFF_XL_238Hz = 0x40, 1001 LSM9DS1_GY_OFF_XL_476Hz = 0x50, 1002 LSM9DS1_GY_OFF_XL_952Hz = 0x60, 1003 LSM9DS1_XL_OFF_GY_14Hz9 = 0x01, 1004 LSM9DS1_XL_OFF_GY_59Hz5 = 0x02, 1005 LSM9DS1_XL_OFF_GY_119Hz = 0x03, 1006 LSM9DS1_XL_OFF_GY_238Hz = 0x04, 1007 LSM9DS1_XL_OFF_GY_476Hz = 0x05, 1008 LSM9DS1_XL_OFF_GY_952Hz = 0x06, 1009 LSM9DS1_IMU_14Hz9 = 0x11, 1010 LSM9DS1_IMU_59Hz5 = 0x22, 1011 LSM9DS1_IMU_119Hz = 0x33, 1012 LSM9DS1_IMU_238Hz = 0x44, 1013 LSM9DS1_IMU_476Hz = 0x55, 1014 LSM9DS1_IMU_952Hz = 0x66, 1015 LSM9DS1_XL_OFF_GY_14Hz9_LP = 0x81, 1016 LSM9DS1_XL_OFF_GY_59Hz5_LP = 0x82, 1017 LSM9DS1_XL_OFF_GY_119Hz_LP = 0x83, 1018 LSM9DS1_IMU_14Hz9_LP = 0x91, 1019 LSM9DS1_IMU_59Hz5_LP = 0xA2, 1020 LSM9DS1_IMU_119Hz_LP = 0xB3, 1021 } lsm9ds1_imu_odr_t; 1022 int32_t lsm9ds1_imu_data_rate_set(const stmdev_ctx_t *ctx, 1023 lsm9ds1_imu_odr_t val); 1024 int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx, 1025 lsm9ds1_imu_odr_t *val); 1026 1027 typedef struct 1028 { 1029 uint8_t orient : 3; 1030 uint8_t signz_g : 1; /*(0: positive; 1: negative)*/ 1031 uint8_t signy_g : 1; /*(0: positive; 1: negative)*/ 1032 uint8_t signx_g : 1; /*(0: positive; 1: negative)*/ 1033 } lsm9ds1_gy_orient_t; 1034 int32_t lsm9ds1_gy_orient_set(const stmdev_ctx_t *ctx, 1035 lsm9ds1_gy_orient_t val); 1036 int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx, 1037 lsm9ds1_gy_orient_t *val); 1038 1039 int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 1040 uint8_t *val); 1041 1042 int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 1043 uint8_t *val); 1044 1045 int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 1046 uint8_t *val); 1047 1048 typedef struct 1049 { 1050 uint8_t xen_g : 1; 1051 uint8_t yen_g : 1; 1052 uint8_t zen_g : 1; 1053 } lsm9ds1_gy_axis_t; 1054 int32_t lsm9ds1_gy_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val); 1055 int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, 1056 lsm9ds1_gy_axis_t *val); 1057 1058 typedef struct 1059 { 1060 uint8_t xen_xl : 1; 1061 uint8_t yen_xl : 1; 1062 uint8_t zen_xl : 1; 1063 } lsm9ds1_xl_axis_t; 1064 int32_t lsm9ds1_xl_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val); 1065 int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, 1066 lsm9ds1_xl_axis_t *val); 1067 1068 typedef enum 1069 { 1070 LSM9DS1_NO_DECIMATION = 0, 1071 LSM9DS1_EVERY_2_SAMPLES = 1, 1072 LSM9DS1_EVERY_4_SAMPLES = 2, 1073 LSM9DS1_EVERY_8_SAMPLES = 3, 1074 } lsm9ds1_dec_t; 1075 int32_t lsm9ds1_xl_decimation_set(const stmdev_ctx_t *ctx, 1076 lsm9ds1_dec_t val); 1077 int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx, 1078 lsm9ds1_dec_t *val); 1079 1080 typedef enum 1081 { 1082 LSM9DS1_2g = 0, 1083 LSM9DS1_16g = 1, 1084 LSM9DS1_4g = 2, 1085 LSM9DS1_8g = 3, 1086 } lsm9ds1_xl_fs_t; 1087 int32_t lsm9ds1_xl_full_scale_set(const stmdev_ctx_t *ctx, 1088 lsm9ds1_xl_fs_t val); 1089 int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx, 1090 lsm9ds1_xl_fs_t *val); 1091 1092 int32_t lsm9ds1_block_data_update_set(const stmdev_ctx_t *ctx_mag, 1093 stmdev_ctx_t *ctx_imu, uint8_t val); 1094 int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, 1095 stmdev_ctx_t *ctx_imu, uint8_t *val); 1096 1097 int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 1098 int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 1099 1100 typedef enum 1101 { 1102 LSM9DS1_MAG_POWER_DOWN = 0xC0, 1103 LSM9DS1_MAG_LP_0Hz625 = 0x00, 1104 LSM9DS1_MAG_LP_1Hz25 = 0x01, 1105 LSM9DS1_MAG_LP_2Hz5 = 0x02, 1106 LSM9DS1_MAG_LP_5Hz = 0x03, 1107 LSM9DS1_MAG_LP_10Hz = 0x04, 1108 LSM9DS1_MAG_LP_20Hz = 0x05, 1109 LSM9DS1_MAG_LP_40Hz = 0x06, 1110 LSM9DS1_MAG_LP_80Hz = 0x07, 1111 LSM9DS1_MAG_MP_0Hz625 = 0x10, 1112 LSM9DS1_MAG_MP_1Hz25 = 0x11, 1113 LSM9DS1_MAG_MP_2Hz5 = 0x12, 1114 LSM9DS1_MAG_MP_5Hz = 0x13, 1115 LSM9DS1_MAG_MP_10Hz = 0x14, 1116 LSM9DS1_MAG_MP_20Hz = 0x15, 1117 LSM9DS1_MAG_MP_40Hz = 0x16, 1118 LSM9DS1_MAG_MP_80Hz = 0x17, 1119 LSM9DS1_MAG_HP_0Hz625 = 0x20, 1120 LSM9DS1_MAG_HP_1Hz25 = 0x21, 1121 LSM9DS1_MAG_HP_2Hz5 = 0x22, 1122 LSM9DS1_MAG_HP_5Hz = 0x23, 1123 LSM9DS1_MAG_HP_10Hz = 0x24, 1124 LSM9DS1_MAG_HP_20Hz = 0x25, 1125 LSM9DS1_MAG_HP_40Hz = 0x26, 1126 LSM9DS1_MAG_HP_80Hz = 0x27, 1127 LSM9DS1_MAG_UHP_0Hz625 = 0x30, 1128 LSM9DS1_MAG_UHP_1Hz25 = 0x31, 1129 LSM9DS1_MAG_UHP_2Hz5 = 0x32, 1130 LSM9DS1_MAG_UHP_5Hz = 0x33, 1131 LSM9DS1_MAG_UHP_10Hz = 0x34, 1132 LSM9DS1_MAG_UHP_20Hz = 0x35, 1133 LSM9DS1_MAG_UHP_40Hz = 0x36, 1134 LSM9DS1_MAG_UHP_80Hz = 0x37, 1135 LSM9DS1_MAG_UHP_155Hz = 0x38, 1136 LSM9DS1_MAG_HP_300Hz = 0x28, 1137 LSM9DS1_MAG_MP_560Hz = 0x18, 1138 LSM9DS1_MAG_LP_1000Hz = 0x08, 1139 LSM9DS1_MAG_ONE_SHOT = 0x70, 1140 } lsm9ds1_mag_data_rate_t; 1141 int32_t lsm9ds1_mag_data_rate_set(const stmdev_ctx_t *ctx, 1142 lsm9ds1_mag_data_rate_t val); 1143 int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx, 1144 lsm9ds1_mag_data_rate_t *val); 1145 1146 typedef enum 1147 { 1148 LSM9DS1_4Ga = 0, 1149 LSM9DS1_8Ga = 1, 1150 LSM9DS1_12Ga = 2, 1151 LSM9DS1_16Ga = 3, 1152 } lsm9ds1_mag_fs_t; 1153 int32_t lsm9ds1_mag_full_scale_set(const stmdev_ctx_t *ctx, 1154 lsm9ds1_mag_fs_t val); 1155 int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx, 1156 lsm9ds1_mag_fs_t *val); 1157 1158 int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, 1159 uint8_t *val); 1160 1161 int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1162 1163 int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1164 1165 int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1166 1167 int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1168 1169 int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, 1170 uint8_t *val); 1171 1172 typedef struct 1173 { 1174 uint8_t imu; 1175 uint8_t mag; 1176 } lsm9ds1_id_t; 1177 int32_t lsm9ds1_dev_id_get(const stmdev_ctx_t *ctx_mag, 1178 stmdev_ctx_t *ctx_imu, 1179 lsm9ds1_id_t *buff); 1180 1181 typedef struct 1182 { 1183 lsm9ds1_status_reg_m_t status_mag; 1184 lsm9ds1_status_reg_t status_imu; 1185 } lsm9ds1_status_t; 1186 int32_t lsm9ds1_dev_status_get(const stmdev_ctx_t *ctx_mag, 1187 stmdev_ctx_t *ctx_imu, 1188 lsm9ds1_status_t *val); 1189 1190 int32_t lsm9ds1_dev_reset_set(const stmdev_ctx_t *ctx_mag, 1191 stmdev_ctx_t *ctx_imu, 1192 uint8_t val); 1193 int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag, 1194 stmdev_ctx_t *ctx_imu, 1195 uint8_t *val); 1196 1197 typedef enum 1198 { 1199 LSM9DS1_LSB_LOW_ADDRESS = 0, 1200 LSM9DS1_MSB_LOW_ADDRESS = 1, 1201 } lsm9ds1_ble_t; 1202 int32_t lsm9ds1_dev_data_format_set(const stmdev_ctx_t *ctx_mag, 1203 stmdev_ctx_t *ctx_imu, 1204 lsm9ds1_ble_t val); 1205 int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag, 1206 stmdev_ctx_t *ctx_imu, 1207 lsm9ds1_ble_t *val); 1208 1209 int32_t lsm9ds1_dev_boot_set(const stmdev_ctx_t *ctx_mag, 1210 stmdev_ctx_t *ctx_imu, 1211 uint8_t val); 1212 int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag, 1213 stmdev_ctx_t *ctx_imu, 1214 uint8_t *val); 1215 1216 int32_t lsm9ds1_gy_filter_reference_set(const stmdev_ctx_t *ctx, 1217 uint8_t *buff); 1218 int32_t lsm9ds1_gy_filter_reference_get(const stmdev_ctx_t *ctx, 1219 uint8_t *buff); 1220 1221 typedef enum 1222 { 1223 LSM9DS1_LP_STRONG = 0, 1224 LSM9DS1_LP_MEDIUM = 1, 1225 LSM9DS1_LP_LIGHT = 2, 1226 LSM9DS1_LP_ULTRA_LIGHT = 3, 1227 } lsm9ds1_gy_lp_bw_t; 1228 int32_t lsm9ds1_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, 1229 lsm9ds1_gy_lp_bw_t val); 1230 int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, 1231 lsm9ds1_gy_lp_bw_t *val); 1232 1233 typedef enum 1234 { 1235 LSM9DS1_LPF1_OUT = 0x00, 1236 LSM9DS1_LPF1_HPF_OUT = 0x01, 1237 LSM9DS1_LPF1_LPF2_OUT = 0x02, 1238 LSM9DS1_LPF1_HPF_LPF2_OUT = 0x12, 1239 } lsm9ds1_gy_out_path_t; 1240 int32_t lsm9ds1_gy_filter_out_path_set(const stmdev_ctx_t *ctx, 1241 lsm9ds1_gy_out_path_t val); 1242 int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx, 1243 lsm9ds1_gy_out_path_t *val); 1244 1245 typedef enum 1246 { 1247 LSM9DS1_LPF1_INT = 0x00, 1248 LSM9DS1_LPF1_HPF_INT = 0x01, 1249 LSM9DS1_LPF1_LPF2_INT = 0x02, 1250 LSM9DS1_LPF1_HPF_LPF2_INT = 0x12, 1251 } lsm9ds1_gy_int_path_t; 1252 int32_t lsm9ds1_gy_filter_int_path_set(const stmdev_ctx_t *ctx, 1253 lsm9ds1_gy_int_path_t val); 1254 int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx, 1255 lsm9ds1_gy_int_path_t *val); 1256 1257 typedef enum 1258 { 1259 LSM9DS1_HP_EXTREME = 0, 1260 LSM9DS1_HP_ULTRA_STRONG = 1, 1261 LSM9DS1_HP_STRONG = 2, 1262 LSM9DS1_HP_ULTRA_HIGH = 3, 1263 LSM9DS1_HP_HIGH = 4, 1264 LSM9DS1_HP_MEDIUM = 5, 1265 LSM9DS1_HP_LOW = 6, 1266 LSM9DS1_HP_ULTRA_LOW = 7, 1267 LSM9DS1_HP_LIGHT = 8, 1268 LSM9DS1_HP_ULTRA_LIGHT = 9, 1269 } lsm9ds1_gy_hp_bw_t; 1270 int32_t lsm9ds1_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, 1271 lsm9ds1_gy_hp_bw_t val); 1272 int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, 1273 lsm9ds1_gy_hp_bw_t *val); 1274 1275 typedef enum 1276 { 1277 LSM9DS1_AUTO = 0x00, 1278 LSM9DS1_408Hz = 0x10, 1279 LSM9DS1_211Hz = 0x11, 1280 LSM9DS1_105Hz = 0x12, 1281 LSM9DS1_50Hz = 0x13, 1282 } lsm9ds1_xl_aa_bw_t; 1283 int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, 1284 lsm9ds1_xl_aa_bw_t val); 1285 int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, 1286 lsm9ds1_xl_aa_bw_t *val); 1287 typedef enum 1288 { 1289 LSM9DS1_HP_DIS = 0, 1290 LSM9DS1_HP_EN = 1, 1291 } lsm9ds1_xl_hp_path_t; 1292 int32_t lsm9ds1_xl_filter_int_path_set(const stmdev_ctx_t *ctx, 1293 lsm9ds1_xl_hp_path_t val); 1294 int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx, 1295 lsm9ds1_xl_hp_path_t *val); 1296 1297 typedef enum 1298 { 1299 LSM9DS1_LP_OUT = 0, 1300 LSM9DS1_HP_OUT = 1, 1301 } lsm9ds1_xl_out_path_t; 1302 int32_t lsm9ds1_xl_filter_out_path_set(const stmdev_ctx_t *ctx, 1303 lsm9ds1_xl_out_path_t val); 1304 int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx, 1305 lsm9ds1_xl_out_path_t *val); 1306 1307 typedef enum 1308 { 1309 LSM9DS1_LP_DISABLE = 0x00, 1310 LSM9DS1_LP_ODR_DIV_50 = 0x10, 1311 LSM9DS1_LP_ODR_DIV_100 = 0x11, 1312 LSM9DS1_LP_ODR_DIV_9 = 0x12, 1313 LSM9DS1_LP_ODR_DIV_400 = 0x13, 1314 } lsm9ds1_xl_lp_bw_t; 1315 int32_t lsm9ds1_xl_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, 1316 lsm9ds1_xl_lp_bw_t val); 1317 int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, 1318 lsm9ds1_xl_lp_bw_t *val); 1319 1320 typedef enum 1321 { 1322 LSM9DS1_HP_ODR_DIV_50 = 0, 1323 LSM9DS1_HP_ODR_DIV_100 = 1, 1324 LSM9DS1_HP_ODR_DIV_9 = 2, 1325 LSM9DS1_HP_ODR_DIV_400 = 3, 1326 } lsm9ds1_xl_hp_bw_t; 1327 int32_t lsm9ds1_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, 1328 lsm9ds1_xl_hp_bw_t val); 1329 int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, 1330 lsm9ds1_xl_hp_bw_t *val); 1331 1332 int32_t lsm9ds1_filter_settling_mask_set(const stmdev_ctx_t *ctx, 1333 uint8_t val); 1334 int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx, 1335 uint8_t *val); 1336 1337 int32_t lsm9ds1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 1338 int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 1339 1340 typedef enum 1341 { 1342 LSM9DS1_SPI_4_WIRE = 0, 1343 LSM9DS1_SPI_3_WIRE = 1, 1344 } lsm9ds1_sim_t; 1345 int32_t lsm9ds1_spi_mode_set(const stmdev_ctx_t *ctx_mag, 1346 stmdev_ctx_t *ctx_imu, 1347 lsm9ds1_sim_t val); 1348 int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag, 1349 stmdev_ctx_t *ctx_imu, 1350 lsm9ds1_sim_t *val); 1351 1352 typedef enum 1353 { 1354 LSM9DS1_I2C_ENABLE = 0, 1355 LSM9DS1_I2C_DISABLE = 1, 1356 } lsm9ds1_i2c_dis_t; 1357 int32_t lsm9ds1_i2c_interface_set(const stmdev_ctx_t *ctx_mag, 1358 stmdev_ctx_t *ctx_imu, 1359 lsm9ds1_i2c_dis_t val); 1360 int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag, 1361 stmdev_ctx_t *ctx_imu, 1362 lsm9ds1_i2c_dis_t *val); 1363 1364 typedef enum 1365 { 1366 LSM9DS1_LOGIC_OR = 0, 1367 LSM9DS1_LOGIC_AND = 1, 1368 } lsm9ds1_pin_logic_t; 1369 int32_t lsm9ds1_pin_logic_set(const stmdev_ctx_t *ctx, 1370 lsm9ds1_pin_logic_t val); 1371 int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx, 1372 lsm9ds1_pin_logic_t *val); 1373 1374 typedef struct 1375 { 1376 uint8_t int1_drdy_xl : 1; 1377 uint8_t int1_drdy_g : 1; 1378 uint8_t int1_boot : 1; 1379 uint8_t int1_fth : 1; 1380 uint8_t int1_ovr : 1; 1381 uint8_t int1_fss5 : 1; 1382 uint8_t int1_ig_xl : 1; 1383 uint8_t int1_ig_g : 1; 1384 } lsm9ds1_pin_int1_route_t; 1385 int32_t lsm9ds1_pin_int1_route_set(const stmdev_ctx_t *ctx, 1386 lsm9ds1_pin_int1_route_t val); 1387 int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx, 1388 lsm9ds1_pin_int1_route_t *val); 1389 typedef struct 1390 { 1391 uint8_t int2_drdy_xl : 1; 1392 uint8_t int2_drdy_g : 1; 1393 uint8_t int2_drdy_temp : 1; 1394 uint8_t int2_fth : 1; 1395 uint8_t int2_ovr : 1; 1396 uint8_t int2_fss5 : 1; 1397 uint8_t int2_inact : 1; 1398 } lsm9ds1_pin_int2_route_t; 1399 int32_t lsm9ds1_pin_int2_route_set(const stmdev_ctx_t *ctx, 1400 lsm9ds1_pin_int2_route_t val); 1401 int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx, 1402 lsm9ds1_pin_int2_route_t *val); 1403 1404 typedef enum 1405 { 1406 LSM9DS1_INT_PULSED = 0, 1407 LSM9DS1_INT_LATCHED = 1, 1408 } lsm9ds1_lir_t; 1409 int32_t lsm9ds1_pin_notification_set(const stmdev_ctx_t *ctx_mag, 1410 stmdev_ctx_t *ctx_imu, 1411 lsm9ds1_lir_t val); 1412 int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag, 1413 stmdev_ctx_t *ctx_imu, 1414 lsm9ds1_lir_t *val); 1415 1416 typedef enum 1417 { 1418 LSM9DS1_PUSH_PULL = 0, 1419 LSM9DS1_OPEN_DRAIN = 1, 1420 } lsm9ds1_pp_od_t; 1421 int32_t lsm9ds1_pin_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val); 1422 int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val); 1423 1424 typedef struct 1425 { 1426 uint8_t ien : 1; 1427 } lsm9ds1_pin_m_route_t; 1428 int32_t lsm9ds1_pin_int_m_route_set(const stmdev_ctx_t *ctx, 1429 lsm9ds1_pin_m_route_t val); 1430 int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx, 1431 lsm9ds1_pin_m_route_t *val); 1432 typedef enum 1433 { 1434 LSM9DS1_ACTIVE_LOW = 0, 1435 LSM9DS1_ACTIVE_HIGH = 1, 1436 } lsm9ds1_polarity_t; 1437 int32_t lsm9ds1_pin_polarity_set(const stmdev_ctx_t *ctx_mag, 1438 stmdev_ctx_t *ctx_imu, 1439 lsm9ds1_polarity_t val); 1440 int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag, 1441 stmdev_ctx_t *ctx_imu, 1442 lsm9ds1_polarity_t *val); 1443 1444 typedef struct 1445 { 1446 uint8_t xlie_xl : 1; 1447 uint8_t xhie_xl : 1; 1448 uint8_t ylie_xl : 1; 1449 uint8_t yhie_xl : 1; 1450 uint8_t zlie_xl : 1; 1451 uint8_t zhie_xl : 1; 1452 } lsm9ds1_xl_trshld_en_t; 1453 int32_t lsm9ds1_xl_trshld_axis_set(const stmdev_ctx_t *ctx, 1454 lsm9ds1_xl_trshld_en_t val); 1455 int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx, 1456 lsm9ds1_xl_trshld_en_t *val); 1457 1458 int32_t lsm9ds1_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1459 int32_t lsm9ds1_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1460 1461 int32_t lsm9ds1_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, 1462 uint8_t val); 1463 int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, 1464 uint8_t *val); 1465 1466 typedef struct 1467 { 1468 uint8_t xl_g : 1; 1469 uint8_t xh_g : 1; 1470 uint8_t yl_g : 1; 1471 uint8_t yh_g : 1; 1472 uint8_t zl_g : 1; 1473 uint8_t zh_g : 1; 1474 uint8_t ia_g : 1; 1475 } lsm9ds1_gy_trshld_src_t; 1476 int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx, 1477 lsm9ds1_gy_trshld_src_t *val); 1478 1479 typedef struct 1480 { 1481 uint8_t xl_xl : 1; 1482 uint8_t xh_xl : 1; 1483 uint8_t yl_xl : 1; 1484 uint8_t yh_xl : 1; 1485 uint8_t zl_xl : 1; 1486 uint8_t zh_xl : 1; 1487 uint8_t ia_xl : 1; 1488 } lsm9ds1_xl_trshld_src_t; 1489 int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx, 1490 lsm9ds1_xl_trshld_src_t *val); 1491 1492 typedef struct 1493 { 1494 uint8_t xlie_g : 1; 1495 uint8_t xhie_g : 1; 1496 uint8_t ylie_g : 1; 1497 uint8_t yhie_g : 1; 1498 uint8_t zlie_g : 1; 1499 uint8_t zhie_g : 1; 1500 } lsm9ds1_gy_trshld_en_t; 1501 int32_t lsm9ds1_gy_trshld_axis_set(const stmdev_ctx_t *ctx, 1502 lsm9ds1_gy_trshld_en_t val); 1503 int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx, 1504 lsm9ds1_gy_trshld_en_t *val); 1505 1506 typedef enum 1507 { 1508 LSM9DS1_RESET_MODE = 0, 1509 LSM9DS1_DECREMENT_MODE = 1, 1510 } lsm9ds1_dcrm_g_t; 1511 int32_t lsm9ds1_gy_trshld_mode_set(const stmdev_ctx_t *ctx, 1512 lsm9ds1_dcrm_g_t val); 1513 int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx, 1514 lsm9ds1_dcrm_g_t *val); 1515 1516 int32_t lsm9ds1_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val); 1517 int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val); 1518 1519 int32_t lsm9ds1_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val); 1520 int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val); 1521 1522 int32_t lsm9ds1_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val); 1523 int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val); 1524 1525 int32_t lsm9ds1_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, 1526 uint8_t val); 1527 int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, 1528 uint8_t *val); 1529 1530 typedef struct 1531 { 1532 uint8_t zien : 1; 1533 uint8_t yien : 1; 1534 uint8_t xien : 1; 1535 } lsm9ds1_mag_trshld_axis_t; 1536 int32_t lsm9ds1_mag_trshld_axis_set(const stmdev_ctx_t *ctx, 1537 lsm9ds1_mag_trshld_axis_t val); 1538 int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx, 1539 lsm9ds1_mag_trshld_axis_t *val); 1540 typedef struct 1541 { 1542 uint8_t _int : 1; 1543 uint8_t nth_z : 1; 1544 uint8_t nth_y : 1; 1545 uint8_t nth_x : 1; 1546 uint8_t pth_z : 1; 1547 uint8_t pth_y : 1; 1548 uint8_t pth_x : 1; 1549 } lsm9ds1_mag_trshld_src_t; 1550 int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx, 1551 lsm9ds1_mag_trshld_src_t *val); 1552 1553 int32_t lsm9ds1_mag_trshld_set(const stmdev_ctx_t *ctx, uint8_t *val); 1554 int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val); 1555 1556 int32_t lsm9ds1_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1557 int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1558 1559 typedef enum 1560 { 1561 LSM9DS1_GYRO_POWER_DOWN = 0, 1562 LSM9DS1_GYRO_SLEEP = 1, 1563 } lsm9ds1_act_mode_t; 1564 int32_t lsm9ds1_act_mode_set(const stmdev_ctx_t *ctx, 1565 lsm9ds1_act_mode_t val); 1566 int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx, 1567 lsm9ds1_act_mode_t *val); 1568 1569 int32_t lsm9ds1_act_duration_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1570 int32_t lsm9ds1_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1571 1572 typedef enum 1573 { 1574 LSM9DS1_ACTIVITY = 0, 1575 LSM9DS1_INACTIVITY = 1, 1576 } lsm9ds1_inact_t; 1577 int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val); 1578 1579 typedef enum 1580 { 1581 LSM9DS1_POS_MOVE_RECO_DISABLE = 0x00, 1582 LSM9DS1_6D_MOVE_RECO = 0x01, 1583 LSM9DS1_4D_MOVE_RECO = 0x05, 1584 LSM9DS1_6D_POS_RECO = 0x03, 1585 LSM9DS1_4D_POS_RECO = 0x07, 1586 } lsm9ds1_6d_mode_t; 1587 int32_t lsm9ds1_6d_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val); 1588 int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, 1589 lsm9ds1_6d_mode_t *val); 1590 1591 int32_t lsm9ds1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1592 int32_t lsm9ds1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1593 1594 typedef struct 1595 { 1596 uint8_t xl_xl : 1; 1597 uint8_t xh_xl : 1; 1598 uint8_t yl_xl : 1; 1599 uint8_t yh_xl : 1; 1600 uint8_t zl_xl : 1; 1601 uint8_t zh_xl : 1; 1602 uint8_t ia_xl : 1; 1603 } lsm9ds1_6d_src_t; 1604 int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val); 1605 1606 int32_t lsm9ds1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 1607 int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 1608 1609 typedef enum 1610 { 1611 LSM9DS1_FIFO_OFF = 0x00, 1612 LSM9DS1_BYPASS_MODE = 0x10, 1613 LSM9DS1_FIFO_MODE = 0x11, 1614 LSM9DS1_STREAM_TO_FIFO_MODE = 0x13, 1615 LSM9DS1_BYPASS_TO_STREAM_MODE = 0x14, 1616 LSM9DS1_STREAM_MODE = 0x16, 1617 } lsm9ds1_fifo_md_t; 1618 int32_t lsm9ds1_fifo_mode_set(const stmdev_ctx_t *ctx, 1619 lsm9ds1_fifo_md_t val); 1620 int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx, 1621 lsm9ds1_fifo_md_t *val); 1622 1623 int32_t lsm9ds1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 1624 int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 1625 1626 int32_t lsm9ds1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 1627 int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 1628 1629 int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1630 1631 int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 1632 1633 int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1634 1635 int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1636 1637 int32_t lsm9ds1_xl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 1638 int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 1639 1640 int32_t lsm9ds1_gy_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 1641 int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 1642 1643 int32_t lsm9ds1_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 1644 int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 1645 /** 1646 *@} 1647 * 1648 */ 1649 1650 #ifdef __cplusplus 1651 } 1652 #endif 1653 1654 #endif /* LSM9DS1_REGS_H */ 1655 1656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1657
