1 /** 2 ****************************************************************************** 3 * @file lsm6dsr_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsr_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSR_REGS_H 23 #define LSM6DSR_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSR 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 /* #define DRV_BYTE_ORDER DRV_BIG_ENDIAN */ 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSR Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSR_I2C_ADD_L 0xD5U 173 #define LSM6DSR_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSR_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSR_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 191 uint8_t not_used_01 : 6; 192 #endif /* DRV_BYTE_ORDER */ 193 } lsm6dsr_func_cfg_access_t; 194 195 #define LSM6DSR_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t ois_pu_dis : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t ois_pu_dis : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } lsm6dsr_pin_ctrl_t; 208 209 #define LSM6DSR_S4S_TPH_L 0x04U 210 typedef struct 211 { 212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 213 uint8_t tph_l : 7; 214 uint8_t tph_h_sel : 1; 215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 216 uint8_t tph_h_sel : 1; 217 uint8_t tph_l : 7; 218 #endif /* DRV_BYTE_ORDER */ 219 } lsm6dsr_s4s_tph_l_t; 220 221 #define LSM6DSR_S4S_TPH_H 0x05U 222 typedef struct 223 { 224 uint8_t tph_h : 8; 225 } lsm6dsr_s4s_tph_h_t; 226 227 #define LSM6DSR_S4S_RR 0x06U 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t rr : 2; 232 uint8_t not_used_01 : 6; 233 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 234 uint8_t not_used_01 : 6; 235 uint8_t rr : 2; 236 #endif /* DRV_BYTE_ORDER */ 237 } lsm6dsr_s4s_rr_t; 238 239 #define LSM6DSR_FIFO_CTRL1 0x07U 240 typedef struct 241 { 242 uint8_t wtm : 8; 243 } lsm6dsr_fifo_ctrl1_t; 244 245 #define LSM6DSR_FIFO_CTRL2 0x08U 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t wtm : 1; 250 uint8_t uncoptr_rate : 2; 251 uint8_t not_used_01 : 1; 252 uint8_t odrchg_en : 1; 253 uint8_t not_used_02 : 1; 254 uint8_t fifo_compr_rt_en : 1; 255 uint8_t stop_on_wtm : 1; 256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 257 uint8_t stop_on_wtm : 1; 258 uint8_t fifo_compr_rt_en : 1; 259 uint8_t not_used_02 : 1; 260 uint8_t odrchg_en : 1; 261 uint8_t not_used_01 : 1; 262 uint8_t uncoptr_rate : 2; 263 uint8_t wtm : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } lsm6dsr_fifo_ctrl2_t; 266 267 #define LSM6DSR_FIFO_CTRL3 0x09U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t bdr_xl : 4; 272 uint8_t bdr_gy : 4; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t bdr_gy : 4; 275 uint8_t bdr_xl : 4; 276 #endif /* DRV_BYTE_ORDER */ 277 } lsm6dsr_fifo_ctrl3_t; 278 279 #define LSM6DSR_FIFO_CTRL4 0x0AU 280 typedef struct 281 { 282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 283 uint8_t fifo_mode : 3; 284 uint8_t not_used_01 : 1; 285 uint8_t odr_t_batch : 2; 286 uint8_t odr_ts_batch : 2; 287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 288 uint8_t odr_ts_batch : 2; 289 uint8_t odr_t_batch : 2; 290 uint8_t not_used_01 : 1; 291 uint8_t fifo_mode : 3; 292 #endif /* DRV_BYTE_ORDER */ 293 } lsm6dsr_fifo_ctrl4_t; 294 295 #define LSM6DSR_COUNTER_BDR_REG1 0x0BU 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t cnt_bdr_th : 3; 300 uint8_t not_used_01 : 2; 301 uint8_t trig_counter_bdr : 1; 302 uint8_t rst_counter_bdr : 1; 303 uint8_t dataready_pulsed : 1; 304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 305 uint8_t dataready_pulsed : 1; 306 uint8_t rst_counter_bdr : 1; 307 uint8_t trig_counter_bdr : 1; 308 uint8_t not_used_01 : 2; 309 uint8_t cnt_bdr_th : 3; 310 #endif /* DRV_BYTE_ORDER */ 311 } lsm6dsr_counter_bdr_reg1_t; 312 313 #define LSM6DSR_COUNTER_BDR_REG2 0x0CU 314 typedef struct 315 { 316 uint8_t cnt_bdr_th : 8; 317 } lsm6dsr_counter_bdr_reg2_t; 318 319 #define LSM6DSR_INT1_CTRL 0x0DU 320 typedef struct 321 { 322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 323 uint8_t int1_drdy_xl : 1; 324 uint8_t int1_drdy_g : 1; 325 uint8_t int1_boot : 1; 326 uint8_t int1_fifo_th : 1; 327 uint8_t int1_fifo_ovr : 1; 328 uint8_t int1_fifo_full : 1; 329 uint8_t int1_cnt_bdr : 1; 330 uint8_t den_drdy_flag : 1; 331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 332 uint8_t den_drdy_flag : 1; 333 uint8_t int1_cnt_bdr : 1; 334 uint8_t int1_fifo_full : 1; 335 uint8_t int1_fifo_ovr : 1; 336 uint8_t int1_fifo_th : 1; 337 uint8_t int1_boot : 1; 338 uint8_t int1_drdy_g : 1; 339 uint8_t int1_drdy_xl : 1; 340 #endif /* DRV_BYTE_ORDER */ 341 } lsm6dsr_int1_ctrl_t; 342 343 #define LSM6DSR_INT2_CTRL 0x0EU 344 typedef struct 345 { 346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 347 uint8_t int2_drdy_xl : 1; 348 uint8_t int2_drdy_g : 1; 349 uint8_t int2_drdy_temp : 1; 350 uint8_t int2_fifo_th : 1; 351 uint8_t int2_fifo_ovr : 1; 352 uint8_t int2_fifo_full : 1; 353 uint8_t int2_cnt_bdr : 1; 354 uint8_t not_used_01 : 1; 355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 356 uint8_t not_used_01 : 1; 357 uint8_t int2_cnt_bdr : 1; 358 uint8_t int2_fifo_full : 1; 359 uint8_t int2_fifo_ovr : 1; 360 uint8_t int2_fifo_th : 1; 361 uint8_t int2_drdy_temp : 1; 362 uint8_t int2_drdy_g : 1; 363 uint8_t int2_drdy_xl : 1; 364 #endif /* DRV_BYTE_ORDER */ 365 } lsm6dsr_int2_ctrl_t; 366 367 #define LSM6DSR_WHO_AM_I 0x0FU 368 #define LSM6DSR_CTRL1_XL 0x10U 369 typedef struct 370 { 371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 372 uint8_t not_used_01 : 1; 373 uint8_t lpf2_xl_en : 1; 374 uint8_t fs_xl : 2; 375 uint8_t odr_xl : 4; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t odr_xl : 4; 378 uint8_t fs_xl : 2; 379 uint8_t lpf2_xl_en : 1; 380 uint8_t not_used_01 : 1; 381 #endif /* DRV_BYTE_ORDER */ 382 } lsm6dsr_ctrl1_xl_t; 383 384 #define LSM6DSR_CTRL2_G 0x11U 385 typedef struct 386 { 387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 388 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 389 uint8_t odr_g : 4; 390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 uint8_t odr_g : 4; 392 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 393 #endif /* DRV_BYTE_ORDER */ 394 } lsm6dsr_ctrl2_g_t; 395 396 #define LSM6DSR_CTRL3_C 0x12U 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t sw_reset : 1; 401 uint8_t not_used_01 : 1; 402 uint8_t if_inc : 1; 403 uint8_t sim : 1; 404 uint8_t pp_od : 1; 405 uint8_t h_lactive : 1; 406 uint8_t bdu : 1; 407 uint8_t boot : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t boot : 1; 410 uint8_t bdu : 1; 411 uint8_t h_lactive : 1; 412 uint8_t pp_od : 1; 413 uint8_t sim : 1; 414 uint8_t if_inc : 1; 415 uint8_t not_used_01 : 1; 416 uint8_t sw_reset : 1; 417 #endif /* DRV_BYTE_ORDER */ 418 } lsm6dsr_ctrl3_c_t; 419 420 #define LSM6DSR_CTRL4_C 0x13U 421 typedef struct 422 { 423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 424 uint8_t not_used_01 : 1; 425 uint8_t lpf1_sel_g : 1; 426 uint8_t i2c_disable : 1; 427 uint8_t drdy_mask : 1; 428 uint8_t not_used_02 : 1; 429 uint8_t int2_on_int1 : 1; 430 uint8_t sleep_g : 1; 431 uint8_t not_used_03 : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t not_used_03 : 1; 434 uint8_t sleep_g : 1; 435 uint8_t int2_on_int1 : 1; 436 uint8_t not_used_02 : 1; 437 uint8_t drdy_mask : 1; 438 uint8_t i2c_disable : 1; 439 uint8_t lpf1_sel_g : 1; 440 uint8_t not_used_01 : 1; 441 #endif /* DRV_BYTE_ORDER */ 442 } lsm6dsr_ctrl4_c_t; 443 444 #define LSM6DSR_CTRL5_C 0x14U 445 typedef struct 446 { 447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 448 uint8_t st_xl : 2; 449 uint8_t st_g : 2; 450 uint8_t not_used_01 : 1; 451 uint8_t rounding : 2; 452 uint8_t not_used_02 : 1; 453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 454 uint8_t not_used_02 : 1; 455 uint8_t rounding : 2; 456 uint8_t not_used_01 : 1; 457 uint8_t st_g : 2; 458 uint8_t st_xl : 2; 459 #endif /* DRV_BYTE_ORDER */ 460 } lsm6dsr_ctrl5_c_t; 461 462 #define LSM6DSR_CTRL6_C 0x15U 463 typedef struct 464 { 465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 466 uint8_t ftype : 3; 467 uint8_t usr_off_w : 1; 468 uint8_t xl_hm_mode : 1; 469 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 471 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 472 uint8_t xl_hm_mode : 1; 473 uint8_t usr_off_w : 1; 474 uint8_t ftype : 3; 475 #endif /* DRV_BYTE_ORDER */ 476 } lsm6dsr_ctrl6_c_t; 477 478 #define LSM6DSR_CTRL7_G 0x16U 479 typedef struct 480 { 481 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 482 uint8_t ois_on : 1; 483 uint8_t usr_off_on_out : 1; 484 uint8_t ois_on_en : 1; 485 uint8_t not_used_01 : 1; 486 uint8_t hpm_g : 2; 487 uint8_t hp_en_g : 1; 488 uint8_t g_hm_mode : 1; 489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 490 uint8_t g_hm_mode : 1; 491 uint8_t hp_en_g : 1; 492 uint8_t hpm_g : 2; 493 uint8_t not_used_01 : 1; 494 uint8_t ois_on_en : 1; 495 uint8_t usr_off_on_out : 1; 496 uint8_t ois_on : 1; 497 #endif /* DRV_BYTE_ORDER */ 498 } lsm6dsr_ctrl7_g_t; 499 500 #define LSM6DSR_CTRL8_XL 0x17U 501 typedef struct 502 { 503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 504 uint8_t low_pass_on_6d : 1; 505 uint8_t not_used_01 : 1; 506 uint8_t hp_slope_xl_en : 1; 507 uint8_t fastsettl_mode_xl : 1; 508 uint8_t hp_ref_mode_xl : 1; 509 uint8_t hpcf_xl : 3; 510 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 511 uint8_t hpcf_xl : 3; 512 uint8_t hp_ref_mode_xl : 1; 513 uint8_t fastsettl_mode_xl : 1; 514 uint8_t hp_slope_xl_en : 1; 515 uint8_t not_used_01 : 1; 516 uint8_t low_pass_on_6d : 1; 517 #endif /* DRV_BYTE_ORDER */ 518 } lsm6dsr_ctrl8_xl_t; 519 520 #define LSM6DSR_CTRL9_XL 0x18U 521 typedef struct 522 { 523 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 524 uint8_t not_used_01 : 1; 525 uint8_t i3c_disable : 1; 526 uint8_t den_lh : 1; 527 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 528 uint8_t den_z : 1; 529 uint8_t den_y : 1; 530 uint8_t den_x : 1; 531 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 532 uint8_t den_x : 1; 533 uint8_t den_y : 1; 534 uint8_t den_z : 1; 535 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 536 uint8_t den_lh : 1; 537 uint8_t i3c_disable : 1; 538 uint8_t not_used_01 : 1; 539 #endif /* DRV_BYTE_ORDER */ 540 } lsm6dsr_ctrl9_xl_t; 541 542 #define LSM6DSR_CTRL10_C 0x19U 543 typedef struct 544 { 545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 546 uint8_t not_used_01 : 5; 547 uint8_t timestamp_en : 1; 548 uint8_t not_used_02 : 2; 549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 550 uint8_t not_used_02 : 2; 551 uint8_t timestamp_en : 1; 552 uint8_t not_used_01 : 5; 553 #endif /* DRV_BYTE_ORDER */ 554 } lsm6dsr_ctrl10_c_t; 555 556 #define LSM6DSR_ALL_INT_SRC 0x1AU 557 typedef struct 558 { 559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 560 uint8_t ff_ia : 1; 561 uint8_t wu_ia : 1; 562 uint8_t single_tap : 1; 563 uint8_t double_tap : 1; 564 uint8_t d6d_ia : 1; 565 uint8_t sleep_change_ia : 1; 566 uint8_t not_used_01 : 1; 567 uint8_t timestamp_endcount : 1; 568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 uint8_t timestamp_endcount : 1; 570 uint8_t not_used_01 : 1; 571 uint8_t sleep_change_ia : 1; 572 uint8_t d6d_ia : 1; 573 uint8_t double_tap : 1; 574 uint8_t single_tap : 1; 575 uint8_t wu_ia : 1; 576 uint8_t ff_ia : 1; 577 #endif /* DRV_BYTE_ORDER */ 578 } lsm6dsr_all_int_src_t; 579 580 #define LSM6DSR_WAKE_UP_SRC 0x1BU 581 typedef struct 582 { 583 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 584 uint8_t z_wu : 1; 585 uint8_t y_wu : 1; 586 uint8_t x_wu : 1; 587 uint8_t wu_ia : 1; 588 uint8_t sleep_state : 1; 589 uint8_t ff_ia : 1; 590 uint8_t sleep_change_ia : 1; 591 uint8_t not_used_01 : 1; 592 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 593 uint8_t not_used_01 : 1; 594 uint8_t sleep_change_ia : 1; 595 uint8_t ff_ia : 1; 596 uint8_t sleep_state : 1; 597 uint8_t wu_ia : 1; 598 uint8_t x_wu : 1; 599 uint8_t y_wu : 1; 600 uint8_t z_wu : 1; 601 #endif /* DRV_BYTE_ORDER */ 602 } lsm6dsr_wake_up_src_t; 603 604 #define LSM6DSR_TAP_SRC 0x1CU 605 typedef struct 606 { 607 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 608 uint8_t z_tap : 1; 609 uint8_t y_tap : 1; 610 uint8_t x_tap : 1; 611 uint8_t tap_sign : 1; 612 uint8_t double_tap : 1; 613 uint8_t single_tap : 1; 614 uint8_t tap_ia : 1; 615 uint8_t not_used_01 : 1; 616 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 617 uint8_t not_used_01 : 1; 618 uint8_t tap_ia : 1; 619 uint8_t single_tap : 1; 620 uint8_t double_tap : 1; 621 uint8_t tap_sign : 1; 622 uint8_t x_tap : 1; 623 uint8_t y_tap : 1; 624 uint8_t z_tap : 1; 625 #endif /* DRV_BYTE_ORDER */ 626 } lsm6dsr_tap_src_t; 627 628 #define LSM6DSR_D6D_SRC 0x1DU 629 typedef struct 630 { 631 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 632 uint8_t xl : 1; 633 uint8_t xh : 1; 634 uint8_t yl : 1; 635 uint8_t yh : 1; 636 uint8_t zl : 1; 637 uint8_t zh : 1; 638 uint8_t d6d_ia : 1; 639 uint8_t den_drdy : 1; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t den_drdy : 1; 642 uint8_t d6d_ia : 1; 643 uint8_t zh : 1; 644 uint8_t zl : 1; 645 uint8_t yh : 1; 646 uint8_t yl : 1; 647 uint8_t xh : 1; 648 uint8_t xl : 1; 649 #endif /* DRV_BYTE_ORDER */ 650 } lsm6dsr_d6d_src_t; 651 652 #define LSM6DSR_STATUS_REG 0x1EU 653 typedef struct 654 { 655 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 656 uint8_t xlda : 1; 657 uint8_t gda : 1; 658 uint8_t tda : 1; 659 uint8_t not_used_01 : 5; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t not_used_01 : 5; 662 uint8_t tda : 1; 663 uint8_t gda : 1; 664 uint8_t xlda : 1; 665 #endif /* DRV_BYTE_ORDER */ 666 } lsm6dsr_status_reg_t; 667 668 #define LSM6DSR_STATUS_SPIAUX 0x1EU 669 typedef struct 670 { 671 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 672 uint8_t xlda : 1; 673 uint8_t gda : 1; 674 uint8_t gyro_settling : 1; 675 uint8_t not_used_01 : 5; 676 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 677 uint8_t not_used_01 : 5; 678 uint8_t gyro_settling : 1; 679 uint8_t gda : 1; 680 uint8_t xlda : 1; 681 #endif /* DRV_BYTE_ORDER */ 682 } lsm6dsr_status_spiaux_t; 683 684 #define LSM6DSR_OUT_TEMP_L 0x20U 685 #define LSM6DSR_OUT_TEMP_H 0x21U 686 #define LSM6DSR_OUTX_L_G 0x22U 687 #define LSM6DSR_OUTX_H_G 0x23U 688 #define LSM6DSR_OUTY_L_G 0x24U 689 #define LSM6DSR_OUTY_H_G 0x25U 690 #define LSM6DSR_OUTZ_L_G 0x26U 691 #define LSM6DSR_OUTZ_H_G 0x27U 692 #define LSM6DSR_OUTX_L_A 0x28U 693 #define LSM6DSR_OUTX_H_A 0x29U 694 #define LSM6DSR_OUTY_L_A 0x2AU 695 #define LSM6DSR_OUTY_H_A 0x2BU 696 #define LSM6DSR_OUTZ_L_A 0x2CU 697 #define LSM6DSR_OUTZ_H_A 0x2DU 698 699 #define LSM6DSR_EMB_FUNC_STATUS_MAINPAGE 0x35U 700 typedef struct 701 { 702 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 703 uint8_t not_used_01 : 3; 704 uint8_t is_step_det : 1; 705 uint8_t is_tilt : 1; 706 uint8_t is_sigmot : 1; 707 uint8_t not_used_02 : 1; 708 uint8_t is_fsm_lc : 1; 709 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 710 uint8_t is_fsm_lc : 1; 711 uint8_t not_used_02 : 1; 712 uint8_t is_sigmot : 1; 713 uint8_t is_tilt : 1; 714 uint8_t is_step_det : 1; 715 uint8_t not_used_01 : 3; 716 #endif /* DRV_BYTE_ORDER */ 717 } lsm6dsr_emb_func_status_mainpage_t; 718 719 #define LSM6DSR_FSM_STATUS_A_MAINPAGE 0x36U 720 typedef struct 721 { 722 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 723 uint8_t is_fsm1 : 1; 724 uint8_t is_fsm2 : 1; 725 uint8_t is_fsm3 : 1; 726 uint8_t is_fsm4 : 1; 727 uint8_t is_fsm5 : 1; 728 uint8_t is_fsm6 : 1; 729 uint8_t is_fsm7 : 1; 730 uint8_t is_fsm8 : 1; 731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 732 uint8_t is_fsm8 : 1; 733 uint8_t is_fsm7 : 1; 734 uint8_t is_fsm6 : 1; 735 uint8_t is_fsm5 : 1; 736 uint8_t is_fsm4 : 1; 737 uint8_t is_fsm3 : 1; 738 uint8_t is_fsm2 : 1; 739 uint8_t is_fsm1 : 1; 740 #endif /* DRV_BYTE_ORDER */ 741 } lsm6dsr_fsm_status_a_mainpage_t; 742 743 #define LSM6DSR_FSM_STATUS_B_MAINPAGE 0x37U 744 typedef struct 745 { 746 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 747 uint8_t is_fsm9 : 1; 748 uint8_t is_fsm10 : 1; 749 uint8_t is_fsm11 : 1; 750 uint8_t is_fsm12 : 1; 751 uint8_t is_fsm13 : 1; 752 uint8_t is_fsm14 : 1; 753 uint8_t is_fsm15 : 1; 754 uint8_t is_fsm16 : 1; 755 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 756 uint8_t is_fsm16 : 1; 757 uint8_t is_fsm15 : 1; 758 uint8_t is_fsm14 : 1; 759 uint8_t is_fsm13 : 1; 760 uint8_t is_fsm12 : 1; 761 uint8_t is_fsm11 : 1; 762 uint8_t is_fsm10 : 1; 763 uint8_t is_fsm9 : 1; 764 #endif /* DRV_BYTE_ORDER */ 765 } lsm6dsr_fsm_status_b_mainpage_t; 766 767 #define LSM6DSR_STATUS_MASTER_MAINPAGE 0x39U 768 typedef struct 769 { 770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 771 uint8_t sens_hub_endop : 1; 772 uint8_t not_used_01 : 2; 773 uint8_t slave0_nack : 1; 774 uint8_t slave1_nack : 1; 775 uint8_t slave2_nack : 1; 776 uint8_t slave3_nack : 1; 777 uint8_t wr_once_done : 1; 778 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 779 uint8_t wr_once_done : 1; 780 uint8_t slave3_nack : 1; 781 uint8_t slave2_nack : 1; 782 uint8_t slave1_nack : 1; 783 uint8_t slave0_nack : 1; 784 uint8_t not_used_01 : 2; 785 uint8_t sens_hub_endop : 1; 786 #endif /* DRV_BYTE_ORDER */ 787 } lsm6dsr_status_master_mainpage_t; 788 789 #define LSM6DSR_FIFO_STATUS1 0x3AU 790 typedef struct 791 { 792 uint8_t diff_fifo : 8; 793 } lsm6dsr_fifo_status1_t; 794 795 #define LSM6DSR_FIFO_STATUS2 0x3BU 796 typedef struct 797 { 798 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 799 uint8_t diff_fifo : 2; 800 uint8_t not_used_01 : 1; 801 uint8_t over_run_latched : 1; 802 uint8_t counter_bdr_ia : 1; 803 uint8_t fifo_full_ia : 1; 804 uint8_t fifo_ovr_ia : 1; 805 uint8_t fifo_wtm_ia : 1; 806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 807 uint8_t fifo_wtm_ia : 1; 808 uint8_t fifo_ovr_ia : 1; 809 uint8_t fifo_full_ia : 1; 810 uint8_t counter_bdr_ia : 1; 811 uint8_t over_run_latched : 1; 812 uint8_t not_used_01 : 1; 813 uint8_t diff_fifo : 2; 814 #endif /* DRV_BYTE_ORDER */ 815 } lsm6dsr_fifo_status2_t; 816 817 #define LSM6DSR_TIMESTAMP0 0x40U 818 #define LSM6DSR_TIMESTAMP1 0x41U 819 #define LSM6DSR_TIMESTAMP2 0x42U 820 #define LSM6DSR_TIMESTAMP3 0x43U 821 #define LSM6DSR_TAP_CFG0 0x56U 822 typedef struct 823 { 824 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 825 uint8_t lir : 1; 826 uint8_t tap_z_en : 1; 827 uint8_t tap_y_en : 1; 828 uint8_t tap_x_en : 1; 829 uint8_t slope_fds : 1; 830 uint8_t sleep_status_on_int : 1; 831 uint8_t int_clr_on_read : 1; 832 uint8_t not_used_01 : 1; 833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 834 uint8_t not_used_01 : 1; 835 uint8_t int_clr_on_read : 1; 836 uint8_t sleep_status_on_int : 1; 837 uint8_t slope_fds : 1; 838 uint8_t tap_x_en : 1; 839 uint8_t tap_y_en : 1; 840 uint8_t tap_z_en : 1; 841 uint8_t lir : 1; 842 #endif /* DRV_BYTE_ORDER */ 843 } lsm6dsr_tap_cfg0_t; 844 845 #define LSM6DSR_TAP_CFG1 0x57U 846 typedef struct 847 { 848 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 849 uint8_t tap_ths_x : 5; 850 uint8_t tap_priority : 3; 851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 852 uint8_t tap_priority : 3; 853 uint8_t tap_ths_x : 5; 854 #endif /* DRV_BYTE_ORDER */ 855 } lsm6dsr_tap_cfg1_t; 856 857 #define LSM6DSR_TAP_CFG2 0x58U 858 typedef struct 859 { 860 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 861 uint8_t tap_ths_y : 5; 862 uint8_t inact_en : 2; 863 uint8_t interrupts_enable : 1; 864 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 865 uint8_t interrupts_enable : 1; 866 uint8_t inact_en : 2; 867 uint8_t tap_ths_y : 5; 868 #endif /* DRV_BYTE_ORDER */ 869 } lsm6dsr_tap_cfg2_t; 870 871 #define LSM6DSR_TAP_THS_6D 0x59U 872 typedef struct 873 { 874 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 875 uint8_t tap_ths_z : 5; 876 uint8_t sixd_ths : 2; 877 uint8_t d4d_en : 1; 878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 879 uint8_t d4d_en : 1; 880 uint8_t sixd_ths : 2; 881 uint8_t tap_ths_z : 5; 882 #endif /* DRV_BYTE_ORDER */ 883 } lsm6dsr_tap_ths_6d_t; 884 885 #define LSM6DSR_INT_DUR2 0x5AU 886 typedef struct 887 { 888 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 889 uint8_t shock : 2; 890 uint8_t quiet : 2; 891 uint8_t dur : 4; 892 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 893 uint8_t dur : 4; 894 uint8_t quiet : 2; 895 uint8_t shock : 2; 896 #endif /* DRV_BYTE_ORDER */ 897 } lsm6dsr_int_dur2_t; 898 899 #define LSM6DSR_WAKE_UP_THS 0x5BU 900 typedef struct 901 { 902 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 903 uint8_t wk_ths : 6; 904 uint8_t usr_off_on_wu : 1; 905 uint8_t single_double_tap : 1; 906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 907 uint8_t single_double_tap : 1; 908 uint8_t usr_off_on_wu : 1; 909 uint8_t wk_ths : 6; 910 #endif /* DRV_BYTE_ORDER */ 911 } lsm6dsr_wake_up_ths_t; 912 913 #define LSM6DSR_WAKE_UP_DUR 0x5CU 914 typedef struct 915 { 916 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 917 uint8_t sleep_dur : 4; 918 uint8_t wake_ths_w : 1; 919 uint8_t wake_dur : 2; 920 uint8_t ff_dur : 1; 921 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 922 uint8_t ff_dur : 1; 923 uint8_t wake_dur : 2; 924 uint8_t wake_ths_w : 1; 925 uint8_t sleep_dur : 4; 926 #endif /* DRV_BYTE_ORDER */ 927 } lsm6dsr_wake_up_dur_t; 928 929 #define LSM6DSR_FREE_FALL 0x5DU 930 typedef struct 931 { 932 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 933 uint8_t ff_ths : 3; 934 uint8_t ff_dur : 5; 935 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 936 uint8_t ff_dur : 5; 937 uint8_t ff_ths : 3; 938 #endif /* DRV_BYTE_ORDER */ 939 } lsm6dsr_free_fall_t; 940 941 #define LSM6DSR_MD1_CFG 0x5EU 942 typedef struct 943 { 944 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 945 uint8_t int1_shub : 1; 946 uint8_t int1_emb_func : 1; 947 uint8_t int1_6d : 1; 948 uint8_t int1_double_tap : 1; 949 uint8_t int1_ff : 1; 950 uint8_t int1_wu : 1; 951 uint8_t int1_single_tap : 1; 952 uint8_t int1_sleep_change : 1; 953 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 954 uint8_t int1_sleep_change : 1; 955 uint8_t int1_single_tap : 1; 956 uint8_t int1_wu : 1; 957 uint8_t int1_ff : 1; 958 uint8_t int1_double_tap : 1; 959 uint8_t int1_6d : 1; 960 uint8_t int1_emb_func : 1; 961 uint8_t int1_shub : 1; 962 #endif /* DRV_BYTE_ORDER */ 963 } lsm6dsr_md1_cfg_t; 964 965 #define LSM6DSR_MD2_CFG 0x5FU 966 typedef struct 967 { 968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 969 uint8_t int2_timestamp : 1; 970 uint8_t int2_emb_func : 1; 971 uint8_t int2_6d : 1; 972 uint8_t int2_double_tap : 1; 973 uint8_t int2_ff : 1; 974 uint8_t int2_wu : 1; 975 uint8_t int2_single_tap : 1; 976 uint8_t int2_sleep_change : 1; 977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 978 uint8_t int2_sleep_change : 1; 979 uint8_t int2_single_tap : 1; 980 uint8_t int2_wu : 1; 981 uint8_t int2_ff : 1; 982 uint8_t int2_double_tap : 1; 983 uint8_t int2_6d : 1; 984 uint8_t int2_emb_func : 1; 985 uint8_t int2_timestamp : 1; 986 #endif /* DRV_BYTE_ORDER */ 987 } lsm6dsr_md2_cfg_t; 988 989 #define LSM6DSR_S4S_ST_CMD_CODE 0x60U 990 typedef struct 991 { 992 uint8_t s4s_st_cmd_code : 8; 993 } lsm6dsr_s4s_st_cmd_code_t; 994 995 #define LSM6DSR_S4S_DT_REG 0x61U 996 typedef struct 997 { 998 uint8_t dt : 8; 999 } lsm6dsr_s4s_dt_reg_t; 1000 1001 #define LSM6DSR_I3C_BUS_AVB 0x62U 1002 typedef struct 1003 { 1004 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1005 uint8_t pd_dis_int1 : 1; 1006 uint8_t not_used_01 : 2; 1007 uint8_t i3c_bus_avb_sel : 2; 1008 uint8_t not_used_02 : 3; 1009 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1010 uint8_t not_used_02 : 3; 1011 uint8_t i3c_bus_avb_sel : 2; 1012 uint8_t not_used_01 : 2; 1013 uint8_t pd_dis_int1 : 1; 1014 #endif /* DRV_BYTE_ORDER */ 1015 } lsm6dsr_i3c_bus_avb_t; 1016 1017 #define LSM6DSR_INTERNAL_FREQ_FINE 0x63U 1018 typedef struct 1019 { 1020 uint8_t freq_fine : 8; 1021 } lsm6dsr_internal_freq_fine_t; 1022 1023 #define LSM6DSR_INT_OIS 0x6FU 1024 typedef struct 1025 { 1026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1027 uint8_t st_xl_ois : 2; 1028 uint8_t not_used_01 : 3; 1029 uint8_t den_lh_ois : 1; 1030 uint8_t lvl2_ois : 1; 1031 uint8_t int2_drdy_ois : 1; 1032 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1033 uint8_t int2_drdy_ois : 1; 1034 uint8_t lvl2_ois : 1; 1035 uint8_t den_lh_ois : 1; 1036 uint8_t not_used_01 : 3; 1037 uint8_t st_xl_ois : 2; 1038 #endif /* DRV_BYTE_ORDER */ 1039 } lsm6dsr_int_ois_t; 1040 1041 #define LSM6DSR_CTRL1_OIS 0x70U 1042 typedef struct 1043 { 1044 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1045 uint8_t ois_en_spi2 : 1; 1046 uint8_t fs_125_ois : 1; 1047 uint8_t fs_g_ois : 2; 1048 uint8_t mode4_en : 1; 1049 uint8_t sim_ois : 1; 1050 uint8_t lvl1_ois : 1; 1051 uint8_t not_used_01 : 1; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t not_used_01 : 1; 1054 uint8_t lvl1_ois : 1; 1055 uint8_t sim_ois : 1; 1056 uint8_t mode4_en : 1; 1057 uint8_t fs_g_ois : 2; 1058 uint8_t fs_125_ois : 1; 1059 uint8_t ois_en_spi2 : 1; 1060 #endif /* DRV_BYTE_ORDER */ 1061 } lsm6dsr_ctrl1_ois_t; 1062 1063 #define LSM6DSR_CTRL2_OIS 0x71U 1064 typedef struct 1065 { 1066 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1067 uint8_t hp_en_ois : 1; 1068 uint8_t ftype_ois : 2; 1069 uint8_t not_used_01 : 1; 1070 uint8_t hpm_ois : 2; 1071 uint8_t not_used_02 : 2; 1072 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1073 uint8_t not_used_02 : 2; 1074 uint8_t hpm_ois : 2; 1075 uint8_t not_used_01 : 1; 1076 uint8_t ftype_ois : 2; 1077 uint8_t hp_en_ois : 1; 1078 #endif /* DRV_BYTE_ORDER */ 1079 } lsm6dsr_ctrl2_ois_t; 1080 1081 #define LSM6DSR_CTRL3_OIS 0x72U 1082 typedef struct 1083 { 1084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1085 uint8_t st_ois_clampdis : 1; 1086 uint8_t st_ois : 2; 1087 uint8_t filter_xl_conf_ois : 3; 1088 uint8_t fs_xl_ois : 2; 1089 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1090 uint8_t fs_xl_ois : 2; 1091 uint8_t filter_xl_conf_ois : 3; 1092 uint8_t st_ois : 2; 1093 uint8_t st_ois_clampdis : 1; 1094 #endif /* DRV_BYTE_ORDER */ 1095 } lsm6dsr_ctrl3_ois_t; 1096 1097 #define LSM6DSR_X_OFS_USR 0x73U 1098 #define LSM6DSR_Y_OFS_USR 0x74U 1099 #define LSM6DSR_Z_OFS_USR 0x75U 1100 #define LSM6DSR_FIFO_DATA_OUT_TAG 0x78U 1101 typedef struct 1102 { 1103 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1104 uint8_t tag_parity : 1; 1105 uint8_t tag_cnt : 2; 1106 uint8_t tag_sensor : 5; 1107 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1108 uint8_t tag_sensor : 5; 1109 uint8_t tag_cnt : 2; 1110 uint8_t tag_parity : 1; 1111 #endif /* DRV_BYTE_ORDER */ 1112 } lsm6dsr_fifo_data_out_tag_t; 1113 1114 #define LSM6DSR_FIFO_DATA_OUT_X_L 0x79U 1115 #define LSM6DSR_FIFO_DATA_OUT_X_H 0x7AU 1116 #define LSM6DSR_FIFO_DATA_OUT_Y_L 0x7BU 1117 #define LSM6DSR_FIFO_DATA_OUT_Y_H 0x7CU 1118 #define LSM6DSR_FIFO_DATA_OUT_Z_L 0x7DU 1119 #define LSM6DSR_FIFO_DATA_OUT_Z_H 0x7EU 1120 #define LSM6DSR_PAGE_SEL 0x02U 1121 typedef struct 1122 { 1123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1124 uint8_t not_used_01 : 4; 1125 uint8_t page_sel : 4; 1126 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1127 uint8_t page_sel : 4; 1128 uint8_t not_used_01 : 4; 1129 #endif /* DRV_BYTE_ORDER */ 1130 } lsm6dsr_page_sel_t; 1131 1132 #define LSM6DSR_ADV_PEDO 0x03U 1133 typedef struct 1134 { 1135 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1136 uint8_t not_used_01 : 1; 1137 uint8_t pedo_fpr_adf_dis : 1; 1138 uint8_t not_used_02 : 6; 1139 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1140 uint8_t not_used_02 : 6; 1141 uint8_t pedo_fpr_adf_dis : 1; 1142 uint8_t not_used_01 : 1; 1143 #endif /* DRV_BYTE_ORDER */ 1144 } lsm6dsr_adv_pedo_t; 1145 1146 #define LSM6DSR_EMB_FUNC_EN_A 0x04U 1147 typedef struct 1148 { 1149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1150 uint8_t not_used_01 : 3; 1151 uint8_t pedo_en : 1; 1152 uint8_t tilt_en : 1; 1153 uint8_t sign_motion_en : 1; 1154 uint8_t not_used_02 : 2; 1155 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1156 uint8_t not_used_02 : 2; 1157 uint8_t sign_motion_en : 1; 1158 uint8_t tilt_en : 1; 1159 uint8_t pedo_en : 1; 1160 uint8_t not_used_01 : 3; 1161 #endif /* DRV_BYTE_ORDER */ 1162 } lsm6dsr_emb_func_en_a_t; 1163 1164 #define LSM6DSR_EMB_FUNC_EN_B 0x05U 1165 typedef struct 1166 { 1167 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1168 uint8_t fsm_en : 1; 1169 uint8_t not_used_01 : 2; 1170 uint8_t fifo_compr_en : 1; 1171 uint8_t pedo_adv_en : 1; 1172 uint8_t not_used_02 : 3; 1173 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1174 uint8_t not_used_02 : 3; 1175 uint8_t pedo_adv_en : 1; 1176 uint8_t fifo_compr_en : 1; 1177 uint8_t not_used_01 : 2; 1178 uint8_t fsm_en : 1; 1179 #endif /* DRV_BYTE_ORDER */ 1180 } lsm6dsr_emb_func_en_b_t; 1181 1182 #define LSM6DSR_PAGE_ADDRESS 0x08U 1183 typedef struct 1184 { 1185 uint8_t page_addr : 8; 1186 } lsm6dsr_page_address_t; 1187 1188 #define LSM6DSR_PAGE_VALUE 0x09U 1189 typedef struct 1190 { 1191 uint8_t page_value : 8; 1192 } lsm6dsr_page_value_t; 1193 1194 #define LSM6DSR_EMB_FUNC_INT1 0x0AU 1195 typedef struct 1196 { 1197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1198 uint8_t not_used_01 : 3; 1199 uint8_t int1_step_detector : 1; 1200 uint8_t int1_tilt : 1; 1201 uint8_t int1_sig_mot : 1; 1202 uint8_t not_used_02 : 1; 1203 uint8_t int1_fsm_lc : 1; 1204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1205 uint8_t int1_fsm_lc : 1; 1206 uint8_t not_used_02 : 1; 1207 uint8_t int1_sig_mot : 1; 1208 uint8_t int1_tilt : 1; 1209 uint8_t int1_step_detector : 1; 1210 uint8_t not_used_01 : 3; 1211 #endif /* DRV_BYTE_ORDER */ 1212 } lsm6dsr_emb_func_int1_t; 1213 1214 #define LSM6DSR_FSM_INT1_A 0x0BU 1215 typedef struct 1216 { 1217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1218 uint8_t int1_fsm1 : 1; 1219 uint8_t int1_fsm2 : 1; 1220 uint8_t int1_fsm3 : 1; 1221 uint8_t int1_fsm4 : 1; 1222 uint8_t int1_fsm5 : 1; 1223 uint8_t int1_fsm6 : 1; 1224 uint8_t int1_fsm7 : 1; 1225 uint8_t int1_fsm8 : 1; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t int1_fsm8 : 1; 1228 uint8_t int1_fsm7 : 1; 1229 uint8_t int1_fsm6 : 1; 1230 uint8_t int1_fsm5 : 1; 1231 uint8_t int1_fsm4 : 1; 1232 uint8_t int1_fsm3 : 1; 1233 uint8_t int1_fsm2 : 1; 1234 uint8_t int1_fsm1 : 1; 1235 #endif /* DRV_BYTE_ORDER */ 1236 } lsm6dsr_fsm_int1_a_t; 1237 1238 #define LSM6DSR_FSM_INT1_B 0x0CU 1239 typedef struct 1240 { 1241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1242 uint8_t int1_fsm9 : 1; 1243 uint8_t int1_fsm10 : 1; 1244 uint8_t int1_fsm11 : 1; 1245 uint8_t int1_fsm12 : 1; 1246 uint8_t int1_fsm13 : 1; 1247 uint8_t int1_fsm14 : 1; 1248 uint8_t int1_fsm15 : 1; 1249 uint8_t int1_fsm16 : 1; 1250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1251 uint8_t int1_fsm16 : 1; 1252 uint8_t int1_fsm15 : 1; 1253 uint8_t int1_fsm14 : 1; 1254 uint8_t int1_fsm13 : 1; 1255 uint8_t int1_fsm12 : 1; 1256 uint8_t int1_fsm11 : 1; 1257 uint8_t int1_fsm10 : 1; 1258 uint8_t int1_fsm9 : 1; 1259 #endif /* DRV_BYTE_ORDER */ 1260 } lsm6dsr_fsm_int1_b_t; 1261 1262 #define LSM6DSR_EMB_FUNC_INT2 0x0EU 1263 typedef struct 1264 { 1265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1266 uint8_t not_used_01 : 3; 1267 uint8_t int2_step_detector : 1; 1268 uint8_t int2_tilt : 1; 1269 uint8_t int2_sig_mot : 1; 1270 uint8_t not_used_02 : 1; 1271 uint8_t int2_fsm_lc : 1; 1272 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1273 uint8_t int2_fsm_lc : 1; 1274 uint8_t not_used_02 : 1; 1275 uint8_t int2_sig_mot : 1; 1276 uint8_t int2_tilt : 1; 1277 uint8_t int2_step_detector : 1; 1278 uint8_t not_used_01 : 3; 1279 #endif /* DRV_BYTE_ORDER */ 1280 } lsm6dsr_emb_func_int2_t; 1281 1282 #define LSM6DSR_FSM_INT2_A 0x0FU 1283 typedef struct 1284 { 1285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1286 uint8_t int2_fsm1 : 1; 1287 uint8_t int2_fsm2 : 1; 1288 uint8_t int2_fsm3 : 1; 1289 uint8_t int2_fsm4 : 1; 1290 uint8_t int2_fsm5 : 1; 1291 uint8_t int2_fsm6 : 1; 1292 uint8_t int2_fsm7 : 1; 1293 uint8_t int2_fsm8 : 1; 1294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1295 uint8_t int2_fsm8 : 1; 1296 uint8_t int2_fsm7 : 1; 1297 uint8_t int2_fsm6 : 1; 1298 uint8_t int2_fsm5 : 1; 1299 uint8_t int2_fsm4 : 1; 1300 uint8_t int2_fsm3 : 1; 1301 uint8_t int2_fsm2 : 1; 1302 uint8_t int2_fsm1 : 1; 1303 #endif /* DRV_BYTE_ORDER */ 1304 } lsm6dsr_fsm_int2_a_t; 1305 1306 #define LSM6DSR_FSM_INT2_B 0x10U 1307 typedef struct 1308 { 1309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1310 uint8_t int2_fsm9 : 1; 1311 uint8_t int2_fsm10 : 1; 1312 uint8_t int2_fsm11 : 1; 1313 uint8_t int2_fsm12 : 1; 1314 uint8_t int2_fsm13 : 1; 1315 uint8_t int2_fsm14 : 1; 1316 uint8_t int2_fsm15 : 1; 1317 uint8_t int2_fsm16 : 1; 1318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1319 uint8_t int2_fsm16 : 1; 1320 uint8_t int2_fsm15 : 1; 1321 uint8_t int2_fsm14 : 1; 1322 uint8_t int2_fsm13 : 1; 1323 uint8_t int2_fsm12 : 1; 1324 uint8_t int2_fsm11 : 1; 1325 uint8_t int2_fsm10 : 1; 1326 uint8_t int2_fsm9 : 1; 1327 #endif /* DRV_BYTE_ORDER */ 1328 } lsm6dsr_fsm_int2_b_t; 1329 1330 #define LSM6DSR_EMB_FUNC_STATUS 0x12U 1331 typedef struct 1332 { 1333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1334 uint8_t not_used_01 : 3; 1335 uint8_t is_step_det : 1; 1336 uint8_t is_tilt : 1; 1337 uint8_t is_sigmot : 1; 1338 uint8_t not_used_02 : 1; 1339 uint8_t is_fsm_lc : 1; 1340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1341 uint8_t is_fsm_lc : 1; 1342 uint8_t not_used_02 : 1; 1343 uint8_t is_sigmot : 1; 1344 uint8_t is_tilt : 1; 1345 uint8_t is_step_det : 1; 1346 uint8_t not_used_01 : 3; 1347 #endif /* DRV_BYTE_ORDER */ 1348 } lsm6dsr_emb_func_status_t; 1349 1350 #define LSM6DSR_FSM_STATUS_A 0x13U 1351 typedef struct 1352 { 1353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1354 uint8_t is_fsm1 : 1; 1355 uint8_t is_fsm2 : 1; 1356 uint8_t is_fsm3 : 1; 1357 uint8_t is_fsm4 : 1; 1358 uint8_t is_fsm5 : 1; 1359 uint8_t is_fsm6 : 1; 1360 uint8_t is_fsm7 : 1; 1361 uint8_t is_fsm8 : 1; 1362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1363 uint8_t is_fsm8 : 1; 1364 uint8_t is_fsm7 : 1; 1365 uint8_t is_fsm6 : 1; 1366 uint8_t is_fsm5 : 1; 1367 uint8_t is_fsm4 : 1; 1368 uint8_t is_fsm3 : 1; 1369 uint8_t is_fsm2 : 1; 1370 uint8_t is_fsm1 : 1; 1371 #endif /* DRV_BYTE_ORDER */ 1372 } lsm6dsr_fsm_status_a_t; 1373 1374 #define LSM6DSR_FSM_STATUS_B 0x14U 1375 typedef struct 1376 { 1377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1378 uint8_t is_fsm9 : 1; 1379 uint8_t is_fsm10 : 1; 1380 uint8_t is_fsm11 : 1; 1381 uint8_t is_fsm12 : 1; 1382 uint8_t is_fsm13 : 1; 1383 uint8_t is_fsm14 : 1; 1384 uint8_t is_fsm15 : 1; 1385 uint8_t is_fsm16 : 1; 1386 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1387 uint8_t is_fsm16 : 1; 1388 uint8_t is_fsm15 : 1; 1389 uint8_t is_fsm14 : 1; 1390 uint8_t is_fsm13 : 1; 1391 uint8_t is_fsm12 : 1; 1392 uint8_t is_fsm11 : 1; 1393 uint8_t is_fsm10 : 1; 1394 uint8_t is_fsm9 : 1; 1395 #endif /* DRV_BYTE_ORDER */ 1396 } lsm6dsr_fsm_status_b_t; 1397 1398 #define LSM6DSR_PAGE_RW 0x17U 1399 typedef struct 1400 { 1401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1402 uint8_t not_used_01 : 5; 1403 uint8_t page_rw : 2; /* page_write + page_read */ 1404 uint8_t emb_func_lir : 1; 1405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1406 uint8_t emb_func_lir : 1; 1407 uint8_t page_rw : 2; /* page_write + page_read */ 1408 uint8_t not_used_01 : 5; 1409 #endif /* DRV_BYTE_ORDER */ 1410 } lsm6dsr_page_rw_t; 1411 1412 #define LSM6DSR_EMB_FUNC_FIFO_CFG 0x44U 1413 typedef struct 1414 { 1415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1416 uint8_t not_used_01 : 6; 1417 uint8_t pedo_fifo_en : 1; 1418 uint8_t not_used_02 : 1; 1419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1420 uint8_t not_used_02 : 1; 1421 uint8_t pedo_fifo_en : 1; 1422 uint8_t not_used_01 : 6; 1423 #endif /* DRV_BYTE_ORDER */ 1424 } lsm6dsr_emb_func_fifo_cfg_t; 1425 1426 #define LSM6DSR_FSM_ENABLE_A 0x46U 1427 typedef struct 1428 { 1429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1430 uint8_t fsm1_en : 1; 1431 uint8_t fsm2_en : 1; 1432 uint8_t fsm3_en : 1; 1433 uint8_t fsm4_en : 1; 1434 uint8_t fsm5_en : 1; 1435 uint8_t fsm6_en : 1; 1436 uint8_t fsm7_en : 1; 1437 uint8_t fsm8_en : 1; 1438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1439 uint8_t fsm8_en : 1; 1440 uint8_t fsm7_en : 1; 1441 uint8_t fsm6_en : 1; 1442 uint8_t fsm5_en : 1; 1443 uint8_t fsm4_en : 1; 1444 uint8_t fsm3_en : 1; 1445 uint8_t fsm2_en : 1; 1446 uint8_t fsm1_en : 1; 1447 #endif /* DRV_BYTE_ORDER */ 1448 } lsm6dsr_fsm_enable_a_t; 1449 1450 #define LSM6DSR_FSM_ENABLE_B 0x47U 1451 typedef struct 1452 { 1453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1454 uint8_t fsm9_en : 1; 1455 uint8_t fsm10_en : 1; 1456 uint8_t fsm11_en : 1; 1457 uint8_t fsm12_en : 1; 1458 uint8_t fsm13_en : 1; 1459 uint8_t fsm14_en : 1; 1460 uint8_t fsm15_en : 1; 1461 uint8_t fsm16_en : 1; 1462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1463 uint8_t fsm16_en : 1; 1464 uint8_t fsm15_en : 1; 1465 uint8_t fsm14_en : 1; 1466 uint8_t fsm13_en : 1; 1467 uint8_t fsm12_en : 1; 1468 uint8_t fsm11_en : 1; 1469 uint8_t fsm10_en : 1; 1470 uint8_t fsm9_en : 1; 1471 #endif /* DRV_BYTE_ORDER */ 1472 } lsm6dsr_fsm_enable_b_t; 1473 1474 #define LSM6DSR_FSM_LONG_COUNTER_L 0x48U 1475 #define LSM6DSR_FSM_LONG_COUNTER_H 0x49U 1476 #define LSM6DSR_FSM_LONG_COUNTER_CLEAR 0x4AU 1477 typedef struct 1478 { 1479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1480 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1481 uint8_t not_used_01 : 6; 1482 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1483 uint8_t not_used_01 : 6; 1484 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1485 #endif /* DRV_BYTE_ORDER */ 1486 } lsm6dsr_fsm_long_counter_clear_t; 1487 1488 #define LSM6DSR_FSM_OUTS1 0x4CU 1489 typedef struct 1490 { 1491 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1492 uint8_t n_v : 1; 1493 uint8_t p_v : 1; 1494 uint8_t n_z : 1; 1495 uint8_t p_z : 1; 1496 uint8_t n_y : 1; 1497 uint8_t p_y : 1; 1498 uint8_t n_x : 1; 1499 uint8_t p_x : 1; 1500 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1501 uint8_t p_x : 1; 1502 uint8_t n_x : 1; 1503 uint8_t p_y : 1; 1504 uint8_t n_y : 1; 1505 uint8_t p_z : 1; 1506 uint8_t n_z : 1; 1507 uint8_t p_v : 1; 1508 uint8_t n_v : 1; 1509 #endif /* DRV_BYTE_ORDER */ 1510 } lsm6dsr_fsm_outs1_t; 1511 1512 #define LSM6DSR_FSM_OUTS2 0x4DU 1513 typedef struct 1514 { 1515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1516 uint8_t n_v : 1; 1517 uint8_t p_v : 1; 1518 uint8_t n_z : 1; 1519 uint8_t p_z : 1; 1520 uint8_t n_y : 1; 1521 uint8_t p_y : 1; 1522 uint8_t n_x : 1; 1523 uint8_t p_x : 1; 1524 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1525 uint8_t p_x : 1; 1526 uint8_t n_x : 1; 1527 uint8_t p_y : 1; 1528 uint8_t n_y : 1; 1529 uint8_t p_z : 1; 1530 uint8_t n_z : 1; 1531 uint8_t p_v : 1; 1532 uint8_t n_v : 1; 1533 #endif /* DRV_BYTE_ORDER */ 1534 } lsm6dsr_fsm_outs2_t; 1535 1536 #define LSM6DSR_FSM_OUTS3 0x4EU 1537 typedef struct 1538 { 1539 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1540 uint8_t n_v : 1; 1541 uint8_t p_v : 1; 1542 uint8_t n_z : 1; 1543 uint8_t p_z : 1; 1544 uint8_t n_y : 1; 1545 uint8_t p_y : 1; 1546 uint8_t n_x : 1; 1547 uint8_t p_x : 1; 1548 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1549 uint8_t p_x : 1; 1550 uint8_t n_x : 1; 1551 uint8_t p_y : 1; 1552 uint8_t n_y : 1; 1553 uint8_t p_z : 1; 1554 uint8_t n_z : 1; 1555 uint8_t p_v : 1; 1556 uint8_t n_v : 1; 1557 #endif /* DRV_BYTE_ORDER */ 1558 } lsm6dsr_fsm_outs3_t; 1559 1560 #define LSM6DSR_FSM_OUTS4 0x4FU 1561 typedef struct 1562 { 1563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1564 uint8_t n_v : 1; 1565 uint8_t p_v : 1; 1566 uint8_t n_z : 1; 1567 uint8_t p_z : 1; 1568 uint8_t n_y : 1; 1569 uint8_t p_y : 1; 1570 uint8_t n_x : 1; 1571 uint8_t p_x : 1; 1572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1573 uint8_t p_x : 1; 1574 uint8_t n_x : 1; 1575 uint8_t p_y : 1; 1576 uint8_t n_y : 1; 1577 uint8_t p_z : 1; 1578 uint8_t n_z : 1; 1579 uint8_t p_v : 1; 1580 uint8_t n_v : 1; 1581 #endif /* DRV_BYTE_ORDER */ 1582 } lsm6dsr_fsm_outs4_t; 1583 1584 #define LSM6DSR_FSM_OUTS5 0x50U 1585 typedef struct 1586 { 1587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1588 uint8_t n_v : 1; 1589 uint8_t p_v : 1; 1590 uint8_t n_z : 1; 1591 uint8_t p_z : 1; 1592 uint8_t n_y : 1; 1593 uint8_t p_y : 1; 1594 uint8_t n_x : 1; 1595 uint8_t p_x : 1; 1596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1597 uint8_t p_x : 1; 1598 uint8_t n_x : 1; 1599 uint8_t p_y : 1; 1600 uint8_t n_y : 1; 1601 uint8_t p_z : 1; 1602 uint8_t n_z : 1; 1603 uint8_t p_v : 1; 1604 uint8_t n_v : 1; 1605 #endif /* DRV_BYTE_ORDER */ 1606 } lsm6dsr_fsm_outs5_t; 1607 1608 #define LSM6DSR_FSM_OUTS6 0x51U 1609 typedef struct 1610 { 1611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1612 uint8_t n_v : 1; 1613 uint8_t p_v : 1; 1614 uint8_t n_z : 1; 1615 uint8_t p_z : 1; 1616 uint8_t n_y : 1; 1617 uint8_t p_y : 1; 1618 uint8_t n_x : 1; 1619 uint8_t p_x : 1; 1620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1621 uint8_t p_x : 1; 1622 uint8_t n_x : 1; 1623 uint8_t p_y : 1; 1624 uint8_t n_y : 1; 1625 uint8_t p_z : 1; 1626 uint8_t n_z : 1; 1627 uint8_t p_v : 1; 1628 uint8_t n_v : 1; 1629 #endif /* DRV_BYTE_ORDER */ 1630 } lsm6dsr_fsm_outs6_t; 1631 1632 #define LSM6DSR_FSM_OUTS7 0x52U 1633 typedef struct 1634 { 1635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1636 uint8_t n_v : 1; 1637 uint8_t p_v : 1; 1638 uint8_t n_z : 1; 1639 uint8_t p_z : 1; 1640 uint8_t n_y : 1; 1641 uint8_t p_y : 1; 1642 uint8_t n_x : 1; 1643 uint8_t p_x : 1; 1644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1645 uint8_t p_x : 1; 1646 uint8_t n_x : 1; 1647 uint8_t p_y : 1; 1648 uint8_t n_y : 1; 1649 uint8_t p_z : 1; 1650 uint8_t n_z : 1; 1651 uint8_t p_v : 1; 1652 uint8_t n_v : 1; 1653 #endif /* DRV_BYTE_ORDER */ 1654 } lsm6dsr_fsm_outs7_t; 1655 1656 #define LSM6DSR_FSM_OUTS8 0x53U 1657 typedef struct 1658 { 1659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1660 uint8_t n_v : 1; 1661 uint8_t p_v : 1; 1662 uint8_t n_z : 1; 1663 uint8_t p_z : 1; 1664 uint8_t n_y : 1; 1665 uint8_t p_y : 1; 1666 uint8_t n_x : 1; 1667 uint8_t p_x : 1; 1668 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1669 uint8_t p_x : 1; 1670 uint8_t n_x : 1; 1671 uint8_t p_y : 1; 1672 uint8_t n_y : 1; 1673 uint8_t p_z : 1; 1674 uint8_t n_z : 1; 1675 uint8_t p_v : 1; 1676 uint8_t n_v : 1; 1677 #endif /* DRV_BYTE_ORDER */ 1678 } lsm6dsr_fsm_outs8_t; 1679 1680 #define LSM6DSR_FSM_OUTS9 0x54U 1681 typedef struct 1682 { 1683 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1684 uint8_t n_v : 1; 1685 uint8_t p_v : 1; 1686 uint8_t n_z : 1; 1687 uint8_t p_z : 1; 1688 uint8_t n_y : 1; 1689 uint8_t p_y : 1; 1690 uint8_t n_x : 1; 1691 uint8_t p_x : 1; 1692 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1693 uint8_t p_x : 1; 1694 uint8_t n_x : 1; 1695 uint8_t p_y : 1; 1696 uint8_t n_y : 1; 1697 uint8_t p_z : 1; 1698 uint8_t n_z : 1; 1699 uint8_t p_v : 1; 1700 uint8_t n_v : 1; 1701 #endif /* DRV_BYTE_ORDER */ 1702 } lsm6dsr_fsm_outs9_t; 1703 1704 #define LSM6DSR_FSM_OUTS10 0x55U 1705 typedef struct 1706 { 1707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1708 uint8_t n_v : 1; 1709 uint8_t p_v : 1; 1710 uint8_t n_z : 1; 1711 uint8_t p_z : 1; 1712 uint8_t n_y : 1; 1713 uint8_t p_y : 1; 1714 uint8_t n_x : 1; 1715 uint8_t p_x : 1; 1716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1717 uint8_t p_x : 1; 1718 uint8_t n_x : 1; 1719 uint8_t p_y : 1; 1720 uint8_t n_y : 1; 1721 uint8_t p_z : 1; 1722 uint8_t n_z : 1; 1723 uint8_t p_v : 1; 1724 uint8_t n_v : 1; 1725 #endif /* DRV_BYTE_ORDER */ 1726 } lsm6dsr_fsm_outs10_t; 1727 1728 #define LSM6DSR_FSM_OUTS11 0x56U 1729 typedef struct 1730 { 1731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1732 uint8_t n_v : 1; 1733 uint8_t p_v : 1; 1734 uint8_t n_z : 1; 1735 uint8_t p_z : 1; 1736 uint8_t n_y : 1; 1737 uint8_t p_y : 1; 1738 uint8_t n_x : 1; 1739 uint8_t p_x : 1; 1740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1741 uint8_t p_x : 1; 1742 uint8_t n_x : 1; 1743 uint8_t p_y : 1; 1744 uint8_t n_y : 1; 1745 uint8_t p_z : 1; 1746 uint8_t n_z : 1; 1747 uint8_t p_v : 1; 1748 uint8_t n_v : 1; 1749 #endif /* DRV_BYTE_ORDER */ 1750 } lsm6dsr_fsm_outs11_t; 1751 1752 #define LSM6DSR_FSM_OUTS12 0x57U 1753 typedef struct 1754 { 1755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1756 uint8_t n_v : 1; 1757 uint8_t p_v : 1; 1758 uint8_t n_z : 1; 1759 uint8_t p_z : 1; 1760 uint8_t n_y : 1; 1761 uint8_t p_y : 1; 1762 uint8_t n_x : 1; 1763 uint8_t p_x : 1; 1764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1765 uint8_t p_x : 1; 1766 uint8_t n_x : 1; 1767 uint8_t p_y : 1; 1768 uint8_t n_y : 1; 1769 uint8_t p_z : 1; 1770 uint8_t n_z : 1; 1771 uint8_t p_v : 1; 1772 uint8_t n_v : 1; 1773 #endif /* DRV_BYTE_ORDER */ 1774 } lsm6dsr_fsm_outs12_t; 1775 1776 #define LSM6DSR_FSM_OUTS13 0x58U 1777 typedef struct 1778 { 1779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1780 uint8_t n_v : 1; 1781 uint8_t p_v : 1; 1782 uint8_t n_z : 1; 1783 uint8_t p_z : 1; 1784 uint8_t n_y : 1; 1785 uint8_t p_y : 1; 1786 uint8_t n_x : 1; 1787 uint8_t p_x : 1; 1788 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1789 uint8_t p_x : 1; 1790 uint8_t n_x : 1; 1791 uint8_t p_y : 1; 1792 uint8_t n_y : 1; 1793 uint8_t p_z : 1; 1794 uint8_t n_z : 1; 1795 uint8_t p_v : 1; 1796 uint8_t n_v : 1; 1797 #endif /* DRV_BYTE_ORDER */ 1798 } lsm6dsr_fsm_outs13_t; 1799 1800 #define LSM6DSR_FSM_OUTS14 0x59U 1801 typedef struct 1802 { 1803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1804 uint8_t n_v : 1; 1805 uint8_t p_v : 1; 1806 uint8_t n_z : 1; 1807 uint8_t p_z : 1; 1808 uint8_t n_y : 1; 1809 uint8_t p_y : 1; 1810 uint8_t n_x : 1; 1811 uint8_t p_x : 1; 1812 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1813 uint8_t p_x : 1; 1814 uint8_t n_x : 1; 1815 uint8_t p_y : 1; 1816 uint8_t n_y : 1; 1817 uint8_t p_z : 1; 1818 uint8_t n_z : 1; 1819 uint8_t p_v : 1; 1820 uint8_t n_v : 1; 1821 #endif /* DRV_BYTE_ORDER */ 1822 } lsm6dsr_fsm_outs14_t; 1823 1824 #define LSM6DSR_FSM_OUTS15 0x5AU 1825 typedef struct 1826 { 1827 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1828 uint8_t n_v : 1; 1829 uint8_t p_v : 1; 1830 uint8_t n_z : 1; 1831 uint8_t p_z : 1; 1832 uint8_t n_y : 1; 1833 uint8_t p_y : 1; 1834 uint8_t n_x : 1; 1835 uint8_t p_x : 1; 1836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1837 uint8_t p_x : 1; 1838 uint8_t n_x : 1; 1839 uint8_t p_y : 1; 1840 uint8_t n_y : 1; 1841 uint8_t p_z : 1; 1842 uint8_t n_z : 1; 1843 uint8_t p_v : 1; 1844 uint8_t n_v : 1; 1845 #endif /* DRV_BYTE_ORDER */ 1846 } lsm6dsr_fsm_outs15_t; 1847 1848 #define LSM6DSR_FSM_OUTS16 0x5BU 1849 typedef struct 1850 { 1851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1852 uint8_t n_v : 1; 1853 uint8_t p_v : 1; 1854 uint8_t n_z : 1; 1855 uint8_t p_z : 1; 1856 uint8_t n_y : 1; 1857 uint8_t p_y : 1; 1858 uint8_t n_x : 1; 1859 uint8_t p_x : 1; 1860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1861 uint8_t p_x : 1; 1862 uint8_t n_x : 1; 1863 uint8_t p_y : 1; 1864 uint8_t n_y : 1; 1865 uint8_t p_z : 1; 1866 uint8_t n_z : 1; 1867 uint8_t p_v : 1; 1868 uint8_t n_v : 1; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } lsm6dsr_fsm_outs16_t; 1871 1872 #define LSM6DSR_EMB_FUNC_ODR_CFG_B 0x5FU 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t not_used_01 : 3; 1877 uint8_t fsm_odr : 2; 1878 uint8_t not_used_02 : 3; 1879 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1880 uint8_t not_used_02 : 3; 1881 uint8_t fsm_odr : 2; 1882 uint8_t not_used_01 : 3; 1883 #endif /* DRV_BYTE_ORDER */ 1884 } lsm6dsr_emb_func_odr_cfg_b_t; 1885 1886 #define LSM6DSR_STEP_COUNTER_L 0x62U 1887 #define LSM6DSR_STEP_COUNTER_H 0x63U 1888 #define LSM6DSR_EMB_FUNC_SRC 0x64U 1889 typedef struct 1890 { 1891 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1892 uint8_t not_used_01 : 2; 1893 uint8_t stepcounter_bit_set : 1; 1894 uint8_t step_overflow : 1; 1895 uint8_t step_count_delta_ia : 1; 1896 uint8_t step_detected : 1; 1897 uint8_t not_used_02 : 1; 1898 uint8_t pedo_rst_step : 1; 1899 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1900 uint8_t pedo_rst_step : 1; 1901 uint8_t not_used_02 : 1; 1902 uint8_t step_detected : 1; 1903 uint8_t step_count_delta_ia : 1; 1904 uint8_t step_overflow : 1; 1905 uint8_t stepcounter_bit_set : 1; 1906 uint8_t not_used_01 : 2; 1907 #endif /* DRV_BYTE_ORDER */ 1908 } lsm6dsr_emb_func_src_t; 1909 1910 #define LSM6DSR_EMB_FUNC_INIT_A 0x66U 1911 typedef struct 1912 { 1913 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1914 uint8_t not_used_01 : 3; 1915 uint8_t step_det_init : 1; 1916 uint8_t tilt_init : 1; 1917 uint8_t sig_mot_init : 1; 1918 uint8_t not_used_02 : 2; 1919 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1920 uint8_t not_used_02 : 2; 1921 uint8_t sig_mot_init : 1; 1922 uint8_t tilt_init : 1; 1923 uint8_t step_det_init : 1; 1924 uint8_t not_used_01 : 3; 1925 #endif /* DRV_BYTE_ORDER */ 1926 } lsm6dsr_emb_func_init_a_t; 1927 1928 #define LSM6DSR_EMB_FUNC_INIT_B 0x67U 1929 typedef struct 1930 { 1931 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1932 uint8_t fsm_init : 1; 1933 uint8_t not_used_01 : 2; 1934 uint8_t fifo_compr_init : 1; 1935 uint8_t not_used_02 : 4; 1936 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1937 uint8_t not_used_02 : 4; 1938 uint8_t fifo_compr_init : 1; 1939 uint8_t not_used_01 : 2; 1940 uint8_t fsm_init : 1; 1941 #endif /* DRV_BYTE_ORDER */ 1942 } lsm6dsr_emb_func_init_b_t; 1943 1944 /** @defgroup bitfields page 0 and 1 1945 * @{ 1946 * 1947 */ 1948 #define LSM6DSR_MAG_SENSITIVITY_L 0xBAU 1949 #define LSM6DSR_MAG_SENSITIVITY_H 0xBBU 1950 #define LSM6DSR_MAG_OFFX_L 0xC0U 1951 #define LSM6DSR_MAG_OFFX_H 0xC1U 1952 #define LSM6DSR_MAG_OFFY_L 0xC2U 1953 #define LSM6DSR_MAG_OFFY_H 0xC3U 1954 #define LSM6DSR_MAG_OFFZ_L 0xC4U 1955 #define LSM6DSR_MAG_OFFZ_H 0xC5U 1956 #define LSM6DSR_MAG_SI_XX_L 0xC6U 1957 #define LSM6DSR_MAG_SI_XX_H 0xC7U 1958 #define LSM6DSR_MAG_SI_XY_L 0xC8U 1959 #define LSM6DSR_MAG_SI_XY_H 0xC9U 1960 #define LSM6DSR_MAG_SI_XZ_L 0xCAU 1961 #define LSM6DSR_MAG_SI_XZ_H 0xCBU 1962 #define LSM6DSR_MAG_SI_YY_L 0xCCU 1963 #define LSM6DSR_MAG_SI_YY_H 0xCDU 1964 #define LSM6DSR_MAG_SI_YZ_L 0xCEU 1965 #define LSM6DSR_MAG_SI_YZ_H 0xCFU 1966 #define LSM6DSR_MAG_SI_ZZ_L 0xD0U 1967 #define LSM6DSR_MAG_SI_ZZ_H 0xD1U 1968 #define LSM6DSR_MAG_CFG_A 0xD4U 1969 typedef struct 1970 { 1971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1972 uint8_t mag_z_axis : 3; 1973 uint8_t not_used_01 : 1; 1974 uint8_t mag_y_axis : 3; 1975 uint8_t not_used_02 : 1; 1976 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1977 uint8_t not_used_02 : 1; 1978 uint8_t mag_y_axis : 3; 1979 uint8_t not_used_01 : 1; 1980 uint8_t mag_z_axis : 3; 1981 #endif /* DRV_BYTE_ORDER */ 1982 } lsm6dsr_mag_cfg_a_t; 1983 1984 #define LSM6DSR_MAG_CFG_B 0xD5U 1985 typedef struct 1986 { 1987 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1988 uint8_t mag_x_axis : 3; 1989 uint8_t not_used_01 : 5; 1990 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1991 uint8_t not_used_01 : 5; 1992 uint8_t mag_x_axis : 3; 1993 #endif /* DRV_BYTE_ORDER */ 1994 } lsm6dsr_mag_cfg_b_t; 1995 1996 #define LSM6DSR_FSM_LC_TIMEOUT_L 0x17AU 1997 #define LSM6DSR_FSM_LC_TIMEOUT_H 0x17BU 1998 #define LSM6DSR_FSM_PROGRAMS 0x17CU 1999 #define LSM6DSR_FSM_START_ADD_L 0x17EU 2000 #define LSM6DSR_FSM_START_ADD_H 0x17FU 2001 #define LSM6DSR_PEDO_CMD_REG 0x183U 2002 typedef struct 2003 { 2004 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2005 uint8_t ad_det_en : 1; 2006 uint8_t not_used_01 : 1; 2007 uint8_t fp_rejection_en : 1; 2008 uint8_t carry_count_en : 1; 2009 uint8_t not_used_02 : 4; 2010 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2011 uint8_t not_used_02 : 4; 2012 uint8_t carry_count_en : 1; 2013 uint8_t fp_rejection_en : 1; 2014 uint8_t not_used_01 : 1; 2015 uint8_t ad_det_en : 1; 2016 #endif /* DRV_BYTE_ORDER */ 2017 } lsm6dsr_pedo_cmd_reg_t; 2018 2019 #define LSM6DSR_PEDO_DEB_STEPS_CONF 0x184U 2020 #define LSM6DSR_PEDO_SC_DELTAT_L 0x1D0U 2021 #define LSM6DSR_PEDO_SC_DELTAT_H 0x1D1U 2022 2023 /** 2024 * @} 2025 * 2026 */ 2027 2028 /** @defgroup bitfields page sensor_hub 2029 * @{ 2030 * 2031 */ 2032 2033 #define LSM6DSR_SENSOR_HUB_1 0x02U 2034 typedef struct 2035 { 2036 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2037 uint8_t bit0 : 1; 2038 uint8_t bit1 : 1; 2039 uint8_t bit2 : 1; 2040 uint8_t bit3 : 1; 2041 uint8_t bit4 : 1; 2042 uint8_t bit5 : 1; 2043 uint8_t bit6 : 1; 2044 uint8_t bit7 : 1; 2045 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2046 uint8_t bit7 : 1; 2047 uint8_t bit6 : 1; 2048 uint8_t bit5 : 1; 2049 uint8_t bit4 : 1; 2050 uint8_t bit3 : 1; 2051 uint8_t bit2 : 1; 2052 uint8_t bit1 : 1; 2053 uint8_t bit0 : 1; 2054 #endif /* DRV_BYTE_ORDER */ 2055 } lsm6dsr_sensor_hub_1_t; 2056 2057 #define LSM6DSR_SENSOR_HUB_2 0x03U 2058 typedef struct 2059 { 2060 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2061 uint8_t bit0 : 1; 2062 uint8_t bit1 : 1; 2063 uint8_t bit2 : 1; 2064 uint8_t bit3 : 1; 2065 uint8_t bit4 : 1; 2066 uint8_t bit5 : 1; 2067 uint8_t bit6 : 1; 2068 uint8_t bit7 : 1; 2069 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2070 uint8_t bit7 : 1; 2071 uint8_t bit6 : 1; 2072 uint8_t bit5 : 1; 2073 uint8_t bit4 : 1; 2074 uint8_t bit3 : 1; 2075 uint8_t bit2 : 1; 2076 uint8_t bit1 : 1; 2077 uint8_t bit0 : 1; 2078 #endif /* DRV_BYTE_ORDER */ 2079 } lsm6dsr_sensor_hub_2_t; 2080 2081 #define LSM6DSR_SENSOR_HUB_3 0x04U 2082 typedef struct 2083 { 2084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2085 uint8_t bit0 : 1; 2086 uint8_t bit1 : 1; 2087 uint8_t bit2 : 1; 2088 uint8_t bit3 : 1; 2089 uint8_t bit4 : 1; 2090 uint8_t bit5 : 1; 2091 uint8_t bit6 : 1; 2092 uint8_t bit7 : 1; 2093 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2094 uint8_t bit7 : 1; 2095 uint8_t bit6 : 1; 2096 uint8_t bit5 : 1; 2097 uint8_t bit4 : 1; 2098 uint8_t bit3 : 1; 2099 uint8_t bit2 : 1; 2100 uint8_t bit1 : 1; 2101 uint8_t bit0 : 1; 2102 #endif /* DRV_BYTE_ORDER */ 2103 } lsm6dsr_sensor_hub_3_t; 2104 2105 #define LSM6DSR_SENSOR_HUB_4 0x05U 2106 typedef struct 2107 { 2108 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2109 uint8_t bit0 : 1; 2110 uint8_t bit1 : 1; 2111 uint8_t bit2 : 1; 2112 uint8_t bit3 : 1; 2113 uint8_t bit4 : 1; 2114 uint8_t bit5 : 1; 2115 uint8_t bit6 : 1; 2116 uint8_t bit7 : 1; 2117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2118 uint8_t bit7 : 1; 2119 uint8_t bit6 : 1; 2120 uint8_t bit5 : 1; 2121 uint8_t bit4 : 1; 2122 uint8_t bit3 : 1; 2123 uint8_t bit2 : 1; 2124 uint8_t bit1 : 1; 2125 uint8_t bit0 : 1; 2126 #endif /* DRV_BYTE_ORDER */ 2127 } lsm6dsr_sensor_hub_4_t; 2128 2129 #define LSM6DSR_SENSOR_HUB_5 0x06U 2130 typedef struct 2131 { 2132 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2133 uint8_t bit0 : 1; 2134 uint8_t bit1 : 1; 2135 uint8_t bit2 : 1; 2136 uint8_t bit3 : 1; 2137 uint8_t bit4 : 1; 2138 uint8_t bit5 : 1; 2139 uint8_t bit6 : 1; 2140 uint8_t bit7 : 1; 2141 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2142 uint8_t bit7 : 1; 2143 uint8_t bit6 : 1; 2144 uint8_t bit5 : 1; 2145 uint8_t bit4 : 1; 2146 uint8_t bit3 : 1; 2147 uint8_t bit2 : 1; 2148 uint8_t bit1 : 1; 2149 uint8_t bit0 : 1; 2150 #endif /* DRV_BYTE_ORDER */ 2151 } lsm6dsr_sensor_hub_5_t; 2152 2153 #define LSM6DSR_SENSOR_HUB_6 0x07U 2154 typedef struct 2155 { 2156 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2157 uint8_t bit0 : 1; 2158 uint8_t bit1 : 1; 2159 uint8_t bit2 : 1; 2160 uint8_t bit3 : 1; 2161 uint8_t bit4 : 1; 2162 uint8_t bit5 : 1; 2163 uint8_t bit6 : 1; 2164 uint8_t bit7 : 1; 2165 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2166 uint8_t bit7 : 1; 2167 uint8_t bit6 : 1; 2168 uint8_t bit5 : 1; 2169 uint8_t bit4 : 1; 2170 uint8_t bit3 : 1; 2171 uint8_t bit2 : 1; 2172 uint8_t bit1 : 1; 2173 uint8_t bit0 : 1; 2174 #endif /* DRV_BYTE_ORDER */ 2175 } lsm6dsr_sensor_hub_6_t; 2176 2177 #define LSM6DSR_SENSOR_HUB_7 0x08U 2178 typedef struct 2179 { 2180 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2181 uint8_t bit0 : 1; 2182 uint8_t bit1 : 1; 2183 uint8_t bit2 : 1; 2184 uint8_t bit3 : 1; 2185 uint8_t bit4 : 1; 2186 uint8_t bit5 : 1; 2187 uint8_t bit6 : 1; 2188 uint8_t bit7 : 1; 2189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2190 uint8_t bit7 : 1; 2191 uint8_t bit6 : 1; 2192 uint8_t bit5 : 1; 2193 uint8_t bit4 : 1; 2194 uint8_t bit3 : 1; 2195 uint8_t bit2 : 1; 2196 uint8_t bit1 : 1; 2197 uint8_t bit0 : 1; 2198 #endif /* DRV_BYTE_ORDER */ 2199 } lsm6dsr_sensor_hub_7_t; 2200 2201 #define LSM6DSR_SENSOR_HUB_8 0x09U 2202 typedef struct 2203 { 2204 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2205 uint8_t bit0 : 1; 2206 uint8_t bit1 : 1; 2207 uint8_t bit2 : 1; 2208 uint8_t bit3 : 1; 2209 uint8_t bit4 : 1; 2210 uint8_t bit5 : 1; 2211 uint8_t bit6 : 1; 2212 uint8_t bit7 : 1; 2213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2214 uint8_t bit7 : 1; 2215 uint8_t bit6 : 1; 2216 uint8_t bit5 : 1; 2217 uint8_t bit4 : 1; 2218 uint8_t bit3 : 1; 2219 uint8_t bit2 : 1; 2220 uint8_t bit1 : 1; 2221 uint8_t bit0 : 1; 2222 #endif /* DRV_BYTE_ORDER */ 2223 } lsm6dsr_sensor_hub_8_t; 2224 2225 #define LSM6DSR_SENSOR_HUB_9 0x0AU 2226 typedef struct 2227 { 2228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2229 uint8_t bit0 : 1; 2230 uint8_t bit1 : 1; 2231 uint8_t bit2 : 1; 2232 uint8_t bit3 : 1; 2233 uint8_t bit4 : 1; 2234 uint8_t bit5 : 1; 2235 uint8_t bit6 : 1; 2236 uint8_t bit7 : 1; 2237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2238 uint8_t bit7 : 1; 2239 uint8_t bit6 : 1; 2240 uint8_t bit5 : 1; 2241 uint8_t bit4 : 1; 2242 uint8_t bit3 : 1; 2243 uint8_t bit2 : 1; 2244 uint8_t bit1 : 1; 2245 uint8_t bit0 : 1; 2246 #endif /* DRV_BYTE_ORDER */ 2247 } lsm6dsr_sensor_hub_9_t; 2248 2249 #define LSM6DSR_SENSOR_HUB_10 0x0BU 2250 typedef struct 2251 { 2252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2253 uint8_t bit0 : 1; 2254 uint8_t bit1 : 1; 2255 uint8_t bit2 : 1; 2256 uint8_t bit3 : 1; 2257 uint8_t bit4 : 1; 2258 uint8_t bit5 : 1; 2259 uint8_t bit6 : 1; 2260 uint8_t bit7 : 1; 2261 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2262 uint8_t bit7 : 1; 2263 uint8_t bit6 : 1; 2264 uint8_t bit5 : 1; 2265 uint8_t bit4 : 1; 2266 uint8_t bit3 : 1; 2267 uint8_t bit2 : 1; 2268 uint8_t bit1 : 1; 2269 uint8_t bit0 : 1; 2270 #endif /* DRV_BYTE_ORDER */ 2271 } lsm6dsr_sensor_hub_10_t; 2272 2273 #define LSM6DSR_SENSOR_HUB_11 0x0CU 2274 typedef struct 2275 { 2276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2277 uint8_t bit0 : 1; 2278 uint8_t bit1 : 1; 2279 uint8_t bit2 : 1; 2280 uint8_t bit3 : 1; 2281 uint8_t bit4 : 1; 2282 uint8_t bit5 : 1; 2283 uint8_t bit6 : 1; 2284 uint8_t bit7 : 1; 2285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2286 uint8_t bit7 : 1; 2287 uint8_t bit6 : 1; 2288 uint8_t bit5 : 1; 2289 uint8_t bit4 : 1; 2290 uint8_t bit3 : 1; 2291 uint8_t bit2 : 1; 2292 uint8_t bit1 : 1; 2293 uint8_t bit0 : 1; 2294 #endif /* DRV_BYTE_ORDER */ 2295 } lsm6dsr_sensor_hub_11_t; 2296 2297 #define LSM6DSR_SENSOR_HUB_12 0x0DU 2298 typedef struct 2299 { 2300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2301 uint8_t bit0 : 1; 2302 uint8_t bit1 : 1; 2303 uint8_t bit2 : 1; 2304 uint8_t bit3 : 1; 2305 uint8_t bit4 : 1; 2306 uint8_t bit5 : 1; 2307 uint8_t bit6 : 1; 2308 uint8_t bit7 : 1; 2309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2310 uint8_t bit7 : 1; 2311 uint8_t bit6 : 1; 2312 uint8_t bit5 : 1; 2313 uint8_t bit4 : 1; 2314 uint8_t bit3 : 1; 2315 uint8_t bit2 : 1; 2316 uint8_t bit1 : 1; 2317 uint8_t bit0 : 1; 2318 #endif /* DRV_BYTE_ORDER */ 2319 } lsm6dsr_sensor_hub_12_t; 2320 2321 #define LSM6DSR_SENSOR_HUB_13 0x0EU 2322 typedef struct 2323 { 2324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2325 uint8_t bit0 : 1; 2326 uint8_t bit1 : 1; 2327 uint8_t bit2 : 1; 2328 uint8_t bit3 : 1; 2329 uint8_t bit4 : 1; 2330 uint8_t bit5 : 1; 2331 uint8_t bit6 : 1; 2332 uint8_t bit7 : 1; 2333 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2334 uint8_t bit7 : 1; 2335 uint8_t bit6 : 1; 2336 uint8_t bit5 : 1; 2337 uint8_t bit4 : 1; 2338 uint8_t bit3 : 1; 2339 uint8_t bit2 : 1; 2340 uint8_t bit1 : 1; 2341 uint8_t bit0 : 1; 2342 #endif /* DRV_BYTE_ORDER */ 2343 } lsm6dsr_sensor_hub_13_t; 2344 2345 #define LSM6DSR_SENSOR_HUB_14 0x0FU 2346 typedef struct 2347 { 2348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2349 uint8_t bit0 : 1; 2350 uint8_t bit1 : 1; 2351 uint8_t bit2 : 1; 2352 uint8_t bit3 : 1; 2353 uint8_t bit4 : 1; 2354 uint8_t bit5 : 1; 2355 uint8_t bit6 : 1; 2356 uint8_t bit7 : 1; 2357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2358 uint8_t bit7 : 1; 2359 uint8_t bit6 : 1; 2360 uint8_t bit5 : 1; 2361 uint8_t bit4 : 1; 2362 uint8_t bit3 : 1; 2363 uint8_t bit2 : 1; 2364 uint8_t bit1 : 1; 2365 uint8_t bit0 : 1; 2366 #endif /* DRV_BYTE_ORDER */ 2367 } lsm6dsr_sensor_hub_14_t; 2368 2369 #define LSM6DSR_SENSOR_HUB_15 0x10U 2370 typedef struct 2371 { 2372 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2373 uint8_t bit0 : 1; 2374 uint8_t bit1 : 1; 2375 uint8_t bit2 : 1; 2376 uint8_t bit3 : 1; 2377 uint8_t bit4 : 1; 2378 uint8_t bit5 : 1; 2379 uint8_t bit6 : 1; 2380 uint8_t bit7 : 1; 2381 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2382 uint8_t bit7 : 1; 2383 uint8_t bit6 : 1; 2384 uint8_t bit5 : 1; 2385 uint8_t bit4 : 1; 2386 uint8_t bit3 : 1; 2387 uint8_t bit2 : 1; 2388 uint8_t bit1 : 1; 2389 uint8_t bit0 : 1; 2390 #endif /* DRV_BYTE_ORDER */ 2391 } lsm6dsr_sensor_hub_15_t; 2392 2393 #define LSM6DSR_SENSOR_HUB_16 0x11U 2394 typedef struct 2395 { 2396 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2397 uint8_t bit0 : 1; 2398 uint8_t bit1 : 1; 2399 uint8_t bit2 : 1; 2400 uint8_t bit3 : 1; 2401 uint8_t bit4 : 1; 2402 uint8_t bit5 : 1; 2403 uint8_t bit6 : 1; 2404 uint8_t bit7 : 1; 2405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2406 uint8_t bit7 : 1; 2407 uint8_t bit6 : 1; 2408 uint8_t bit5 : 1; 2409 uint8_t bit4 : 1; 2410 uint8_t bit3 : 1; 2411 uint8_t bit2 : 1; 2412 uint8_t bit1 : 1; 2413 uint8_t bit0 : 1; 2414 #endif /* DRV_BYTE_ORDER */ 2415 } lsm6dsr_sensor_hub_16_t; 2416 2417 #define LSM6DSR_SENSOR_HUB_17 0x12U 2418 typedef struct 2419 { 2420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2421 uint8_t bit0 : 1; 2422 uint8_t bit1 : 1; 2423 uint8_t bit2 : 1; 2424 uint8_t bit3 : 1; 2425 uint8_t bit4 : 1; 2426 uint8_t bit5 : 1; 2427 uint8_t bit6 : 1; 2428 uint8_t bit7 : 1; 2429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2430 uint8_t bit7 : 1; 2431 uint8_t bit6 : 1; 2432 uint8_t bit5 : 1; 2433 uint8_t bit4 : 1; 2434 uint8_t bit3 : 1; 2435 uint8_t bit2 : 1; 2436 uint8_t bit1 : 1; 2437 uint8_t bit0 : 1; 2438 #endif /* DRV_BYTE_ORDER */ 2439 } lsm6dsr_sensor_hub_17_t; 2440 2441 #define LSM6DSR_SENSOR_HUB_18 0x13U 2442 typedef struct 2443 { 2444 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2445 uint8_t bit0 : 1; 2446 uint8_t bit1 : 1; 2447 uint8_t bit2 : 1; 2448 uint8_t bit3 : 1; 2449 uint8_t bit4 : 1; 2450 uint8_t bit5 : 1; 2451 uint8_t bit6 : 1; 2452 uint8_t bit7 : 1; 2453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2454 uint8_t bit7 : 1; 2455 uint8_t bit6 : 1; 2456 uint8_t bit5 : 1; 2457 uint8_t bit4 : 1; 2458 uint8_t bit3 : 1; 2459 uint8_t bit2 : 1; 2460 uint8_t bit1 : 1; 2461 uint8_t bit0 : 1; 2462 #endif /* DRV_BYTE_ORDER */ 2463 } lsm6dsr_sensor_hub_18_t; 2464 2465 #define LSM6DSR_MASTER_CONFIG 0x14U 2466 typedef struct 2467 { 2468 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2469 uint8_t aux_sens_on : 2; 2470 uint8_t master_on : 1; 2471 uint8_t shub_pu_en : 1; 2472 uint8_t pass_through_mode : 1; 2473 uint8_t start_config : 1; 2474 uint8_t write_once : 1; 2475 uint8_t rst_master_regs : 1; 2476 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2477 uint8_t rst_master_regs : 1; 2478 uint8_t write_once : 1; 2479 uint8_t start_config : 1; 2480 uint8_t pass_through_mode : 1; 2481 uint8_t shub_pu_en : 1; 2482 uint8_t master_on : 1; 2483 uint8_t aux_sens_on : 2; 2484 #endif /* DRV_BYTE_ORDER */ 2485 } lsm6dsr_master_config_t; 2486 2487 #define LSM6DSR_SLV0_ADD 0x15U 2488 typedef struct 2489 { 2490 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2491 uint8_t rw_0 : 1; 2492 uint8_t slave0 : 7; 2493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2494 uint8_t slave0 : 7; 2495 uint8_t rw_0 : 1; 2496 #endif /* DRV_BYTE_ORDER */ 2497 } lsm6dsr_slv0_add_t; 2498 2499 #define LSM6DSR_SLV0_SUBADD 0x16U 2500 typedef struct 2501 { 2502 uint8_t slave0_reg : 8; 2503 } lsm6dsr_slv0_subadd_t; 2504 2505 #define LSM6DSR_SLV0_CONFIG 0x17U 2506 typedef struct 2507 { 2508 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2509 uint8_t slave0_numop : 3; 2510 uint8_t batch_ext_sens_0_en : 1; 2511 uint8_t not_used_01 : 2; 2512 uint8_t shub_odr : 2; 2513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2514 uint8_t shub_odr : 2; 2515 uint8_t not_used_01 : 2; 2516 uint8_t batch_ext_sens_0_en : 1; 2517 uint8_t slave0_numop : 3; 2518 #endif /* DRV_BYTE_ORDER */ 2519 } lsm6dsr_slv0_config_t; 2520 2521 #define LSM6DSR_SLV1_ADD 0x18U 2522 typedef struct 2523 { 2524 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2525 uint8_t r_1 : 1; 2526 uint8_t slave1_add : 7; 2527 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2528 uint8_t slave1_add : 7; 2529 uint8_t r_1 : 1; 2530 #endif /* DRV_BYTE_ORDER */ 2531 } lsm6dsr_slv1_add_t; 2532 2533 #define LSM6DSR_SLV1_SUBADD 0x19U 2534 typedef struct 2535 { 2536 uint8_t slave1_reg : 8; 2537 } lsm6dsr_slv1_subadd_t; 2538 2539 #define LSM6DSR_SLV1_CONFIG 0x1AU 2540 typedef struct 2541 { 2542 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2543 uint8_t slave1_numop : 3; 2544 uint8_t batch_ext_sens_1_en : 1; 2545 uint8_t not_used_01 : 4; 2546 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2547 uint8_t not_used_01 : 4; 2548 uint8_t batch_ext_sens_1_en : 1; 2549 uint8_t slave1_numop : 3; 2550 #endif /* DRV_BYTE_ORDER */ 2551 } lsm6dsr_slv1_config_t; 2552 2553 #define LSM6DSR_SLV2_ADD 0x1BU 2554 typedef struct 2555 { 2556 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2557 uint8_t r_2 : 1; 2558 uint8_t slave2_add : 7; 2559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2560 uint8_t slave2_add : 7; 2561 uint8_t r_2 : 1; 2562 #endif /* DRV_BYTE_ORDER */ 2563 } lsm6dsr_slv2_add_t; 2564 2565 #define LSM6DSR_SLV2_SUBADD 0x1CU 2566 typedef struct 2567 { 2568 uint8_t slave2_reg : 8; 2569 } lsm6dsr_slv2_subadd_t; 2570 2571 #define LSM6DSR_SLV2_CONFIG 0x1DU 2572 typedef struct 2573 { 2574 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2575 uint8_t slave2_numop : 3; 2576 uint8_t batch_ext_sens_2_en : 1; 2577 uint8_t not_used_01 : 4; 2578 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2579 uint8_t not_used_01 : 4; 2580 uint8_t batch_ext_sens_2_en : 1; 2581 uint8_t slave2_numop : 3; 2582 #endif /* DRV_BYTE_ORDER */ 2583 } lsm6dsr_slv2_config_t; 2584 2585 #define LSM6DSR_SLV3_ADD 0x1EU 2586 typedef struct 2587 { 2588 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2589 uint8_t r_3 : 1; 2590 uint8_t slave3_add : 7; 2591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2592 uint8_t slave3_add : 7; 2593 uint8_t r_3 : 1; 2594 #endif /* DRV_BYTE_ORDER */ 2595 } lsm6dsr_slv3_add_t; 2596 2597 #define LSM6DSR_SLV3_SUBADD 0x1FU 2598 typedef struct 2599 { 2600 uint8_t slave3_reg : 8; 2601 } lsm6dsr_slv3_subadd_t; 2602 2603 #define LSM6DSR_SLV3_CONFIG 0x20U 2604 typedef struct 2605 { 2606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2607 uint8_t slave3_numop : 3; 2608 uint8_t batch_ext_sens_3_en : 1; 2609 uint8_t not_used_01 : 4; 2610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2611 uint8_t not_used_01 : 4; 2612 uint8_t batch_ext_sens_3_en : 1; 2613 uint8_t slave3_numop : 3; 2614 #endif /* DRV_BYTE_ORDER */ 2615 } lsm6dsr_slv3_config_t; 2616 2617 #define LSM6DSR_DATAWRITE_SLV0 0x21U 2618 typedef struct 2619 { 2620 uint8_t slave0_dataw : 8; 2621 } lsm6dsr_datawrite_slv0_t; 2622 2623 #define LSM6DSR_STATUS_MASTER 0x22U 2624 typedef struct 2625 { 2626 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2627 uint8_t sens_hub_endop : 1; 2628 uint8_t not_used_01 : 2; 2629 uint8_t slave0_nack : 1; 2630 uint8_t slave1_nack : 1; 2631 uint8_t slave2_nack : 1; 2632 uint8_t slave3_nack : 1; 2633 uint8_t wr_once_done : 1; 2634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2635 uint8_t wr_once_done : 1; 2636 uint8_t slave3_nack : 1; 2637 uint8_t slave2_nack : 1; 2638 uint8_t slave1_nack : 1; 2639 uint8_t slave0_nack : 1; 2640 uint8_t not_used_01 : 2; 2641 uint8_t sens_hub_endop : 1; 2642 #endif /* DRV_BYTE_ORDER */ 2643 } lsm6dsr_status_master_t; 2644 2645 /** 2646 * @} 2647 * 2648 */ 2649 2650 /** 2651 * @defgroup LSM6DSR_Register_Union 2652 * @brief This union group all the registers having a bit-field 2653 * description. 2654 * This union is useful but it's not needed by the driver. 2655 * 2656 * REMOVING this union you are compliant with: 2657 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2658 * 2659 * @{ 2660 * 2661 */ 2662 typedef union 2663 { 2664 lsm6dsr_func_cfg_access_t func_cfg_access; 2665 lsm6dsr_pin_ctrl_t pin_ctrl; 2666 lsm6dsr_s4s_tph_l_t s4s_tph_l; 2667 lsm6dsr_s4s_tph_h_t s4s_tph_h; 2668 lsm6dsr_s4s_rr_t s4s_rr; 2669 lsm6dsr_fifo_ctrl1_t fifo_ctrl1; 2670 lsm6dsr_fifo_ctrl2_t fifo_ctrl2; 2671 lsm6dsr_fifo_ctrl3_t fifo_ctrl3; 2672 lsm6dsr_fifo_ctrl4_t fifo_ctrl4; 2673 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; 2674 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2; 2675 lsm6dsr_int1_ctrl_t int1_ctrl; 2676 lsm6dsr_int2_ctrl_t int2_ctrl; 2677 lsm6dsr_ctrl1_xl_t ctrl1_xl; 2678 lsm6dsr_ctrl2_g_t ctrl2_g; 2679 lsm6dsr_ctrl3_c_t ctrl3_c; 2680 lsm6dsr_ctrl4_c_t ctrl4_c; 2681 lsm6dsr_ctrl5_c_t ctrl5_c; 2682 lsm6dsr_ctrl6_c_t ctrl6_c; 2683 lsm6dsr_ctrl7_g_t ctrl7_g; 2684 lsm6dsr_ctrl8_xl_t ctrl8_xl; 2685 lsm6dsr_ctrl9_xl_t ctrl9_xl; 2686 lsm6dsr_ctrl10_c_t ctrl10_c; 2687 lsm6dsr_all_int_src_t all_int_src; 2688 lsm6dsr_wake_up_src_t wake_up_src; 2689 lsm6dsr_tap_src_t tap_src; 2690 lsm6dsr_d6d_src_t d6d_src; 2691 lsm6dsr_status_reg_t status_reg; 2692 lsm6dsr_status_spiaux_t status_spiaux; 2693 lsm6dsr_fifo_status1_t fifo_status1; 2694 lsm6dsr_fifo_status2_t fifo_status2; 2695 lsm6dsr_tap_cfg0_t tap_cfg0; 2696 lsm6dsr_tap_cfg1_t tap_cfg1; 2697 lsm6dsr_tap_cfg2_t tap_cfg2; 2698 lsm6dsr_tap_ths_6d_t tap_ths_6d; 2699 lsm6dsr_int_dur2_t int_dur2; 2700 lsm6dsr_wake_up_ths_t wake_up_ths; 2701 lsm6dsr_wake_up_dur_t wake_up_dur; 2702 lsm6dsr_free_fall_t free_fall; 2703 lsm6dsr_md1_cfg_t md1_cfg; 2704 lsm6dsr_md2_cfg_t md2_cfg; 2705 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code; 2706 lsm6dsr_s4s_dt_reg_t s4s_dt_reg; 2707 lsm6dsr_i3c_bus_avb_t i3c_bus_avb; 2708 lsm6dsr_internal_freq_fine_t internal_freq_fine; 2709 lsm6dsr_int_ois_t int_ois; 2710 lsm6dsr_ctrl1_ois_t ctrl1_ois; 2711 lsm6dsr_ctrl2_ois_t ctrl2_ois; 2712 lsm6dsr_ctrl3_ois_t ctrl3_ois; 2713 lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag; 2714 lsm6dsr_page_sel_t page_sel; 2715 lsm6dsr_emb_func_en_a_t emb_func_en_a; 2716 lsm6dsr_emb_func_en_b_t emb_func_en_b; 2717 lsm6dsr_page_address_t page_address; 2718 lsm6dsr_page_value_t page_value; 2719 lsm6dsr_emb_func_int1_t emb_func_int1; 2720 lsm6dsr_fsm_int1_a_t fsm_int1_a; 2721 lsm6dsr_fsm_int1_b_t fsm_int1_b; 2722 lsm6dsr_emb_func_int2_t emb_func_int2; 2723 lsm6dsr_fsm_int2_a_t fsm_int2_a; 2724 lsm6dsr_fsm_int2_b_t fsm_int2_b; 2725 lsm6dsr_emb_func_status_t emb_func_status; 2726 lsm6dsr_fsm_status_a_t fsm_status_a; 2727 lsm6dsr_fsm_status_b_t fsm_status_b; 2728 lsm6dsr_page_rw_t page_rw; 2729 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2730 lsm6dsr_fsm_enable_a_t fsm_enable_a; 2731 lsm6dsr_fsm_enable_b_t fsm_enable_b; 2732 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear; 2733 lsm6dsr_fsm_outs1_t fsm_outs1; 2734 lsm6dsr_fsm_outs2_t fsm_outs2; 2735 lsm6dsr_fsm_outs3_t fsm_outs3; 2736 lsm6dsr_fsm_outs4_t fsm_outs4; 2737 lsm6dsr_fsm_outs5_t fsm_outs5; 2738 lsm6dsr_fsm_outs6_t fsm_outs6; 2739 lsm6dsr_fsm_outs7_t fsm_outs7; 2740 lsm6dsr_fsm_outs8_t fsm_outs8; 2741 lsm6dsr_fsm_outs9_t fsm_outs9; 2742 lsm6dsr_fsm_outs10_t fsm_outs10; 2743 lsm6dsr_fsm_outs11_t fsm_outs11; 2744 lsm6dsr_fsm_outs12_t fsm_outs12; 2745 lsm6dsr_fsm_outs13_t fsm_outs13; 2746 lsm6dsr_fsm_outs14_t fsm_outs14; 2747 lsm6dsr_fsm_outs15_t fsm_outs15; 2748 lsm6dsr_fsm_outs16_t fsm_outs16; 2749 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2750 lsm6dsr_emb_func_src_t emb_func_src; 2751 lsm6dsr_emb_func_init_a_t emb_func_init_a; 2752 lsm6dsr_emb_func_init_b_t emb_func_init_b; 2753 lsm6dsr_mag_cfg_a_t mag_cfg_a; 2754 lsm6dsr_mag_cfg_b_t mag_cfg_b; 2755 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; 2756 lsm6dsr_sensor_hub_1_t sensor_hub_1; 2757 lsm6dsr_sensor_hub_2_t sensor_hub_2; 2758 lsm6dsr_sensor_hub_3_t sensor_hub_3; 2759 lsm6dsr_sensor_hub_4_t sensor_hub_4; 2760 lsm6dsr_sensor_hub_5_t sensor_hub_5; 2761 lsm6dsr_sensor_hub_6_t sensor_hub_6; 2762 lsm6dsr_sensor_hub_7_t sensor_hub_7; 2763 lsm6dsr_sensor_hub_8_t sensor_hub_8; 2764 lsm6dsr_sensor_hub_9_t sensor_hub_9; 2765 lsm6dsr_sensor_hub_10_t sensor_hub_10; 2766 lsm6dsr_sensor_hub_11_t sensor_hub_11; 2767 lsm6dsr_sensor_hub_12_t sensor_hub_12; 2768 lsm6dsr_sensor_hub_13_t sensor_hub_13; 2769 lsm6dsr_sensor_hub_14_t sensor_hub_14; 2770 lsm6dsr_sensor_hub_15_t sensor_hub_15; 2771 lsm6dsr_sensor_hub_16_t sensor_hub_16; 2772 lsm6dsr_sensor_hub_17_t sensor_hub_17; 2773 lsm6dsr_sensor_hub_18_t sensor_hub_18; 2774 lsm6dsr_master_config_t master_config; 2775 lsm6dsr_slv0_add_t slv0_add; 2776 lsm6dsr_slv0_subadd_t slv0_subadd; 2777 lsm6dsr_slv0_config_t slv0_config; 2778 lsm6dsr_slv1_add_t slv1_add; 2779 lsm6dsr_slv1_subadd_t slv1_subadd; 2780 lsm6dsr_slv1_config_t slv1_config; 2781 lsm6dsr_slv2_add_t slv2_add; 2782 lsm6dsr_slv2_subadd_t slv2_subadd; 2783 lsm6dsr_slv2_config_t slv2_config; 2784 lsm6dsr_slv3_add_t slv3_add; 2785 lsm6dsr_slv3_subadd_t slv3_subadd; 2786 lsm6dsr_slv3_config_t slv3_config; 2787 lsm6dsr_datawrite_slv0_t datawrite_slv0; 2788 lsm6dsr_status_master_t status_master; 2789 bitwise_t bitwise; 2790 uint8_t byte; 2791 } lsm6dsr_reg_t; 2792 2793 /** 2794 * @} 2795 * 2796 */ 2797 2798 #ifndef __weak 2799 #define __weak __attribute__((weak)) 2800 #endif /* __weak */ 2801 2802 /* 2803 * These are the basic platform dependent I/O routines to read 2804 * and write device registers connected on a standard bus. 2805 * The driver keeps offering a default implementation based on function 2806 * pointers to read/write routines for backward compatibility. 2807 * The __weak directive allows the final application to overwrite 2808 * them with a custom implementation. 2809 */ 2810 int32_t lsm6dsr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2811 uint8_t *data, 2812 uint16_t len); 2813 int32_t lsm6dsr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2814 uint8_t *data, 2815 uint16_t len); 2816 2817 float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb); 2818 float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb); 2819 float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb); 2820 float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb); 2821 2822 float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb); 2823 float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb); 2824 float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb); 2825 float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb); 2826 float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb); 2827 float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb); 2828 2829 float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb); 2830 2831 uint64_t lsm6dsr_from_lsb_to_nsec(uint32_t lsb); 2832 2833 typedef enum 2834 { 2835 LSM6DSR_2g = 0, 2836 LSM6DSR_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSR_2g */ 2837 LSM6DSR_4g = 2, 2838 LSM6DSR_8g = 3, 2839 } lsm6dsr_fs_xl_t; 2840 int32_t lsm6dsr_xl_full_scale_set(const stmdev_ctx_t *ctx, 2841 lsm6dsr_fs_xl_t val); 2842 int32_t lsm6dsr_xl_full_scale_get(const stmdev_ctx_t *ctx, 2843 lsm6dsr_fs_xl_t *val); 2844 2845 typedef enum 2846 { 2847 LSM6DSR_XL_ODR_OFF = 0, 2848 LSM6DSR_XL_ODR_12Hz5 = 1, 2849 LSM6DSR_XL_ODR_26Hz = 2, 2850 LSM6DSR_XL_ODR_52Hz = 3, 2851 LSM6DSR_XL_ODR_104Hz = 4, 2852 LSM6DSR_XL_ODR_208Hz = 5, 2853 LSM6DSR_XL_ODR_416Hz = 6, 2854 LSM6DSR_XL_ODR_833Hz = 7, 2855 LSM6DSR_XL_ODR_1666Hz = 8, 2856 LSM6DSR_XL_ODR_3332Hz = 9, 2857 LSM6DSR_XL_ODR_6667Hz = 10, 2858 LSM6DSR_XL_ODR_1Hz6 = 11, /* (low power only) */ 2859 } lsm6dsr_odr_xl_t; 2860 int32_t lsm6dsr_xl_data_rate_set(const stmdev_ctx_t *ctx, 2861 lsm6dsr_odr_xl_t val); 2862 int32_t lsm6dsr_xl_data_rate_get(const stmdev_ctx_t *ctx, 2863 lsm6dsr_odr_xl_t *val); 2864 2865 typedef enum 2866 { 2867 LSM6DSR_125dps = 2, 2868 LSM6DSR_250dps = 0, 2869 LSM6DSR_500dps = 4, 2870 LSM6DSR_1000dps = 8, 2871 LSM6DSR_2000dps = 12, 2872 LSM6DSR_4000dps = 1, 2873 } lsm6dsr_fs_g_t; 2874 int32_t lsm6dsr_gy_full_scale_set(const stmdev_ctx_t *ctx, 2875 lsm6dsr_fs_g_t val); 2876 int32_t lsm6dsr_gy_full_scale_get(const stmdev_ctx_t *ctx, 2877 lsm6dsr_fs_g_t *val); 2878 2879 typedef enum 2880 { 2881 LSM6DSR_GY_ODR_OFF = 0, 2882 LSM6DSR_GY_ODR_12Hz5 = 1, 2883 LSM6DSR_GY_ODR_26Hz = 2, 2884 LSM6DSR_GY_ODR_52Hz = 3, 2885 LSM6DSR_GY_ODR_104Hz = 4, 2886 LSM6DSR_GY_ODR_208Hz = 5, 2887 LSM6DSR_GY_ODR_416Hz = 6, 2888 LSM6DSR_GY_ODR_833Hz = 7, 2889 LSM6DSR_GY_ODR_1666Hz = 8, 2890 LSM6DSR_GY_ODR_3332Hz = 9, 2891 LSM6DSR_GY_ODR_6667Hz = 10, 2892 } lsm6dsr_odr_g_t; 2893 int32_t lsm6dsr_gy_data_rate_set(const stmdev_ctx_t *ctx, 2894 lsm6dsr_odr_g_t val); 2895 int32_t lsm6dsr_gy_data_rate_get(const stmdev_ctx_t *ctx, 2896 lsm6dsr_odr_g_t *val); 2897 2898 int32_t lsm6dsr_block_data_update_set(const stmdev_ctx_t *ctx, 2899 uint8_t val); 2900 int32_t lsm6dsr_block_data_update_get(const stmdev_ctx_t *ctx, 2901 uint8_t *val); 2902 2903 typedef enum 2904 { 2905 LSM6DSR_LSb_1mg = 0, 2906 LSM6DSR_LSb_16mg = 1, 2907 } lsm6dsr_usr_off_w_t; 2908 int32_t lsm6dsr_xl_offset_weight_set(const stmdev_ctx_t *ctx, 2909 lsm6dsr_usr_off_w_t val); 2910 int32_t lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t *ctx, 2911 lsm6dsr_usr_off_w_t *val); 2912 2913 typedef enum 2914 { 2915 LSM6DSR_HIGH_PERFORMANCE_MD = 0, 2916 LSM6DSR_LOW_NORMAL_POWER_MD = 1, 2917 } lsm6dsr_xl_hm_mode_t; 2918 int32_t lsm6dsr_xl_power_mode_set(const stmdev_ctx_t *ctx, 2919 lsm6dsr_xl_hm_mode_t val); 2920 int32_t lsm6dsr_xl_power_mode_get(const stmdev_ctx_t *ctx, 2921 lsm6dsr_xl_hm_mode_t *val); 2922 2923 typedef enum 2924 { 2925 LSM6DSR_GY_HIGH_PERFORMANCE = 0, 2926 LSM6DSR_GY_NORMAL = 1, 2927 } lsm6dsr_g_hm_mode_t; 2928 int32_t lsm6dsr_gy_power_mode_set(const stmdev_ctx_t *ctx, 2929 lsm6dsr_g_hm_mode_t val); 2930 int32_t lsm6dsr_gy_power_mode_get(const stmdev_ctx_t *ctx, 2931 lsm6dsr_g_hm_mode_t *val); 2932 2933 typedef struct 2934 { 2935 lsm6dsr_all_int_src_t all_int_src; 2936 lsm6dsr_wake_up_src_t wake_up_src; 2937 lsm6dsr_tap_src_t tap_src; 2938 lsm6dsr_d6d_src_t d6d_src; 2939 lsm6dsr_status_reg_t status_reg; 2940 lsm6dsr_emb_func_status_t emb_func_status; 2941 lsm6dsr_fsm_status_a_t fsm_status_a; 2942 lsm6dsr_fsm_status_b_t fsm_status_b; 2943 } lsm6dsr_all_sources_t; 2944 int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx, 2945 lsm6dsr_all_sources_t *val); 2946 2947 int32_t lsm6dsr_status_reg_get(const stmdev_ctx_t *ctx, 2948 lsm6dsr_status_reg_t *val); 2949 2950 int32_t lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 2951 uint8_t *val); 2952 2953 int32_t lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 2954 uint8_t *val); 2955 2956 int32_t lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 2957 uint8_t *val); 2958 2959 int32_t lsm6dsr_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, 2960 uint8_t *val); 2961 int32_t lsm6dsr_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, 2962 uint8_t *val); 2963 2964 int32_t lsm6dsr_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, 2965 uint8_t *val); 2966 int32_t lsm6dsr_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, 2967 uint8_t *val); 2968 2969 int32_t lsm6dsr_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, 2970 uint8_t *val); 2971 int32_t lsm6dsr_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, 2972 uint8_t *val); 2973 2974 int32_t lsm6dsr_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 2975 int32_t lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2976 2977 int32_t lsm6dsr_timestamp_rst(const stmdev_ctx_t *ctx); 2978 2979 int32_t lsm6dsr_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2980 int32_t lsm6dsr_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2981 2982 int32_t lsm6dsr_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2983 2984 typedef enum 2985 { 2986 LSM6DSR_NO_ROUND = 0, 2987 LSM6DSR_ROUND_XL = 1, 2988 LSM6DSR_ROUND_GY = 2, 2989 LSM6DSR_ROUND_GY_XL = 3, 2990 } lsm6dsr_rounding_t; 2991 int32_t lsm6dsr_rounding_mode_set(const stmdev_ctx_t *ctx, 2992 lsm6dsr_rounding_t val); 2993 int32_t lsm6dsr_rounding_mode_get(const stmdev_ctx_t *ctx, 2994 lsm6dsr_rounding_t *val); 2995 2996 int32_t lsm6dsr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2997 2998 int32_t lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2999 3000 int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3001 3002 int32_t lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 3003 3004 int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 3005 int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 3006 3007 int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 3008 3009 int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx); 3010 3011 typedef enum 3012 { 3013 LSM6DSR_USER_BANK = 0, 3014 LSM6DSR_SENSOR_HUB_BANK = 1, 3015 LSM6DSR_EMBEDDED_FUNC_BANK = 2, 3016 } lsm6dsr_reg_access_t; 3017 int32_t lsm6dsr_mem_bank_set(const stmdev_ctx_t *ctx, 3018 lsm6dsr_reg_access_t val); 3019 int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx, 3020 lsm6dsr_reg_access_t *val); 3021 3022 int32_t lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 3023 uint8_t *val); 3024 int32_t lsm6dsr_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 3025 uint8_t *buf, uint8_t len); 3026 int32_t lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, 3027 uint8_t *val); 3028 int32_t lsm6dsr_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 3029 uint8_t *val); 3030 3031 typedef enum 3032 { 3033 LSM6DSR_DRDY_LATCHED = 0, 3034 LSM6DSR_DRDY_PULSED = 1, 3035 } lsm6dsr_dataready_pulsed_t; 3036 int32_t lsm6dsr_data_ready_mode_set(const stmdev_ctx_t *ctx, 3037 lsm6dsr_dataready_pulsed_t val); 3038 int32_t lsm6dsr_data_ready_mode_get(const stmdev_ctx_t *ctx, 3039 lsm6dsr_dataready_pulsed_t *val); 3040 3041 int32_t lsm6dsr_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 3042 3043 int32_t lsm6dsr_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 3044 int32_t lsm6dsr_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3045 3046 int32_t lsm6dsr_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 3047 int32_t lsm6dsr_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 3048 3049 int32_t lsm6dsr_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 3050 int32_t lsm6dsr_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 3051 3052 typedef enum 3053 { 3054 LSM6DSR_XL_ST_DISABLE = 0, 3055 LSM6DSR_XL_ST_POSITIVE = 1, 3056 LSM6DSR_XL_ST_NEGATIVE = 2, 3057 } lsm6dsr_st_xl_t; 3058 int32_t lsm6dsr_xl_self_test_set(const stmdev_ctx_t *ctx, 3059 lsm6dsr_st_xl_t val); 3060 int32_t lsm6dsr_xl_self_test_get(const stmdev_ctx_t *ctx, 3061 lsm6dsr_st_xl_t *val); 3062 3063 typedef enum 3064 { 3065 LSM6DSR_GY_ST_DISABLE = 0, 3066 LSM6DSR_GY_ST_POSITIVE = 1, 3067 LSM6DSR_GY_ST_NEGATIVE = 3, 3068 } lsm6dsr_st_g_t; 3069 int32_t lsm6dsr_gy_self_test_set(const stmdev_ctx_t *ctx, 3070 lsm6dsr_st_g_t val); 3071 int32_t lsm6dsr_gy_self_test_get(const stmdev_ctx_t *ctx, 3072 lsm6dsr_st_g_t *val); 3073 3074 int32_t lsm6dsr_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 3075 int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3076 3077 int32_t lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 3078 int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3079 3080 int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 3081 int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 3082 3083 typedef enum 3084 { 3085 LSM6DSR_ULTRA_LIGHT = 0, 3086 LSM6DSR_VERY_LIGHT = 1, 3087 LSM6DSR_LIGHT = 2, 3088 LSM6DSR_MEDIUM = 3, 3089 LSM6DSR_STRONG = 4, 3090 LSM6DSR_VERY_STRONG = 5, 3091 LSM6DSR_AGGRESSIVE = 6, 3092 LSM6DSR_XTREME = 7, 3093 } lsm6dsr_ftype_t; 3094 int32_t lsm6dsr_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3095 lsm6dsr_ftype_t val); 3096 int32_t lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3097 lsm6dsr_ftype_t *val); 3098 3099 int32_t lsm6dsr_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 3100 int32_t lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 3101 3102 typedef enum 3103 { 3104 LSM6DSR_HP_PATH_DISABLE_ON_OUT = 0x00, 3105 LSM6DSR_SLOPE_ODR_DIV_4 = 0x10, 3106 LSM6DSR_HP_ODR_DIV_10 = 0x11, 3107 LSM6DSR_HP_ODR_DIV_20 = 0x12, 3108 LSM6DSR_HP_ODR_DIV_45 = 0x13, 3109 LSM6DSR_HP_ODR_DIV_100 = 0x14, 3110 LSM6DSR_HP_ODR_DIV_200 = 0x15, 3111 LSM6DSR_HP_ODR_DIV_400 = 0x16, 3112 LSM6DSR_HP_ODR_DIV_800 = 0x17, 3113 LSM6DSR_HP_REF_MD_ODR_DIV_10 = 0x31, 3114 LSM6DSR_HP_REF_MD_ODR_DIV_20 = 0x32, 3115 LSM6DSR_HP_REF_MD_ODR_DIV_45 = 0x33, 3116 LSM6DSR_HP_REF_MD_ODR_DIV_100 = 0x34, 3117 LSM6DSR_HP_REF_MD_ODR_DIV_200 = 0x35, 3118 LSM6DSR_HP_REF_MD_ODR_DIV_400 = 0x36, 3119 LSM6DSR_HP_REF_MD_ODR_DIV_800 = 0x37, 3120 LSM6DSR_LP_ODR_DIV_10 = 0x01, 3121 LSM6DSR_LP_ODR_DIV_20 = 0x02, 3122 LSM6DSR_LP_ODR_DIV_45 = 0x03, 3123 LSM6DSR_LP_ODR_DIV_100 = 0x04, 3124 LSM6DSR_LP_ODR_DIV_200 = 0x05, 3125 LSM6DSR_LP_ODR_DIV_400 = 0x06, 3126 LSM6DSR_LP_ODR_DIV_800 = 0x07, 3127 } lsm6dsr_hp_slope_xl_en_t; 3128 int32_t lsm6dsr_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 3129 lsm6dsr_hp_slope_xl_en_t val); 3130 int32_t lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 3131 lsm6dsr_hp_slope_xl_en_t *val); 3132 3133 int32_t lsm6dsr_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 3134 int32_t lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 3135 3136 typedef enum 3137 { 3138 LSM6DSR_USE_SLOPE = 0, 3139 LSM6DSR_USE_HPF = 1, 3140 } lsm6dsr_slope_fds_t; 3141 int32_t lsm6dsr_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 3142 lsm6dsr_slope_fds_t val); 3143 int32_t lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 3144 lsm6dsr_slope_fds_t *val); 3145 3146 typedef enum 3147 { 3148 LSM6DSR_HP_FILTER_NONE = 0x00, 3149 LSM6DSR_HP_FILTER_16mHz = 0x80, 3150 LSM6DSR_HP_FILTER_65mHz = 0x81, 3151 LSM6DSR_HP_FILTER_260mHz = 0x82, 3152 LSM6DSR_HP_FILTER_1Hz04 = 0x83, 3153 } lsm6dsr_hpm_g_t; 3154 int32_t lsm6dsr_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 3155 lsm6dsr_hpm_g_t val); 3156 int32_t lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 3157 lsm6dsr_hpm_g_t *val); 3158 3159 typedef enum 3160 { 3161 LSM6DSR_AUX_PULL_UP_DISC = 0, 3162 LSM6DSR_AUX_PULL_UP_CONNECT = 1, 3163 } lsm6dsr_ois_pu_dis_t; 3164 int32_t lsm6dsr_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, 3165 lsm6dsr_ois_pu_dis_t val); 3166 int32_t lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, 3167 lsm6dsr_ois_pu_dis_t *val); 3168 3169 typedef enum 3170 { 3171 LSM6DSR_AUX_ON = 1, 3172 LSM6DSR_AUX_ON_BY_AUX_INTERFACE = 0, 3173 } lsm6dsr_ois_on_t; 3174 int32_t lsm6dsr_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, 3175 lsm6dsr_ois_on_t val); 3176 int32_t lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, 3177 lsm6dsr_ois_on_t *val); 3178 3179 int32_t lsm6dsr_aux_status_reg_get(const stmdev_ctx_t *ctx, 3180 lsm6dsr_status_spiaux_t *val); 3181 3182 int32_t lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3183 uint8_t *val); 3184 3185 int32_t lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3186 uint8_t *val); 3187 3188 int32_t lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 3189 uint8_t *val); 3190 3191 typedef enum 3192 { 3193 LSM6DSR_AUX_XL_DISABLE = 0, 3194 LSM6DSR_AUX_XL_POS = 1, 3195 LSM6DSR_AUX_XL_NEG = 2, 3196 } lsm6dsr_st_xl_ois_t; 3197 int32_t lsm6dsr_aux_xl_self_test_set(const stmdev_ctx_t *ctx, 3198 lsm6dsr_st_xl_ois_t val); 3199 int32_t lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t *ctx, 3200 lsm6dsr_st_xl_ois_t *val); 3201 3202 typedef enum 3203 { 3204 LSM6DSR_AUX_DEN_ACTIVE_LOW = 0, 3205 LSM6DSR_AUX_DEN_ACTIVE_HIGH = 1, 3206 } lsm6dsr_den_lh_ois_t; 3207 int32_t lsm6dsr_aux_den_polarity_set(const stmdev_ctx_t *ctx, 3208 lsm6dsr_den_lh_ois_t val); 3209 int32_t lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t *ctx, 3210 lsm6dsr_den_lh_ois_t *val); 3211 3212 typedef enum 3213 { 3214 LSM6DSR_AUX_DEN_DISABLE = 0, 3215 LSM6DSR_AUX_DEN_LEVEL_LATCH = 3, 3216 LSM6DSR_AUX_DEN_LEVEL_TRIG = 2, 3217 } lsm6dsr_lvl2_ois_t; 3218 int32_t lsm6dsr_aux_den_mode_set(const stmdev_ctx_t *ctx, 3219 lsm6dsr_lvl2_ois_t val); 3220 int32_t lsm6dsr_aux_den_mode_get(const stmdev_ctx_t *ctx, 3221 lsm6dsr_lvl2_ois_t *val); 3222 3223 int32_t lsm6dsr_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 3224 int32_t lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3225 3226 typedef enum 3227 { 3228 LSM6DSR_AUX_DISABLE = 0, 3229 LSM6DSR_MODE_3_GY = 1, 3230 LSM6DSR_MODE_4_GY_XL = 3, 3231 } lsm6dsr_ois_en_spi2_t; 3232 int32_t lsm6dsr_aux_mode_set(const stmdev_ctx_t *ctx, 3233 lsm6dsr_ois_en_spi2_t val); 3234 int32_t lsm6dsr_aux_mode_get(const stmdev_ctx_t *ctx, 3235 lsm6dsr_ois_en_spi2_t *val); 3236 3237 typedef enum 3238 { 3239 LSM6DSR_125dps_AUX = 0x04, 3240 LSM6DSR_250dps_AUX = 0x00, 3241 LSM6DSR_500dps_AUX = 0x01, 3242 LSM6DSR_1000dps_AUX = 0x02, 3243 LSM6DSR_2000dps_AUX = 0x03, 3244 } lsm6dsr_fs_g_ois_t; 3245 int32_t lsm6dsr_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 3246 lsm6dsr_fs_g_ois_t val); 3247 int32_t lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 3248 lsm6dsr_fs_g_ois_t *val); 3249 3250 typedef enum 3251 { 3252 LSM6DSR_AUX_SPI_4_WIRE = 0, 3253 LSM6DSR_AUX_SPI_3_WIRE = 1, 3254 } lsm6dsr_sim_ois_t; 3255 int32_t lsm6dsr_aux_spi_mode_set(const stmdev_ctx_t *ctx, 3256 lsm6dsr_sim_ois_t val); 3257 int32_t lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t *ctx, 3258 lsm6dsr_sim_ois_t *val); 3259 3260 typedef enum 3261 { 3262 LSM6DSR_351Hz39 = 0, 3263 LSM6DSR_236Hz63 = 1, 3264 LSM6DSR_172Hz70 = 2, 3265 LSM6DSR_937Hz91 = 3, 3266 } lsm6dsr_ftype_ois_t; 3267 int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3268 lsm6dsr_ftype_ois_t val); 3269 int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3270 lsm6dsr_ftype_ois_t *val); 3271 3272 typedef enum 3273 { 3274 LSM6DSR_AUX_HP_DISABLE = 0x00, 3275 LSM6DSR_AUX_HP_Hz016 = 0x10, 3276 LSM6DSR_AUX_HP_Hz065 = 0x11, 3277 LSM6DSR_AUX_HP_Hz260 = 0x12, 3278 LSM6DSR_AUX_HP_1Hz040 = 0x13, 3279 } lsm6dsr_hpm_ois_t; 3280 int32_t lsm6dsr_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, 3281 lsm6dsr_hpm_ois_t val); 3282 int32_t lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, 3283 lsm6dsr_hpm_ois_t *val); 3284 3285 typedef enum 3286 { 3287 LSM6DSR_ENABLE_CLAMP = 0, 3288 LSM6DSR_DISABLE_CLAMP = 1, 3289 } lsm6dsr_st_ois_clampdis_t; 3290 int32_t lsm6dsr_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 3291 lsm6dsr_st_ois_clampdis_t val); 3292 int32_t lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 3293 lsm6dsr_st_ois_clampdis_t *val); 3294 3295 typedef enum 3296 { 3297 LSM6DSR_AUX_GY_DISABLE = 0, 3298 LSM6DSR_AUX_GY_POS = 1, 3299 LSM6DSR_AUX_GY_NEG = 3, 3300 } lsm6dsr_st_ois_t; 3301 int32_t lsm6dsr_aux_gy_self_test_set(const stmdev_ctx_t *ctx, 3302 lsm6dsr_st_ois_t val); 3303 int32_t lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t *ctx, 3304 lsm6dsr_st_ois_t *val); 3305 3306 typedef enum 3307 { 3308 LSM6DSR_631Hz = 0, 3309 LSM6DSR_295Hz = 1, 3310 LSM6DSR_140Hz = 2, 3311 LSM6DSR_68Hz2 = 3, 3312 LSM6DSR_33Hz6 = 4, 3313 LSM6DSR_16Hz7 = 5, 3314 LSM6DSR_8Hz3 = 6, 3315 LSM6DSR_4Hz11 = 7, 3316 } lsm6dsr_filter_xl_conf_ois_t; 3317 int32_t lsm6dsr_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, 3318 lsm6dsr_filter_xl_conf_ois_t val); 3319 int32_t lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, 3320 lsm6dsr_filter_xl_conf_ois_t *val); 3321 3322 typedef enum 3323 { 3324 LSM6DSR_AUX_2g = 0, 3325 LSM6DSR_AUX_16g = 1, 3326 LSM6DSR_AUX_4g = 2, 3327 LSM6DSR_AUX_8g = 3, 3328 } lsm6dsr_fs_xl_ois_t; 3329 int32_t lsm6dsr_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 3330 lsm6dsr_fs_xl_ois_t val); 3331 int32_t lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 3332 lsm6dsr_fs_xl_ois_t *val); 3333 3334 typedef enum 3335 { 3336 LSM6DSR_PULL_UP_DISC = 0, 3337 LSM6DSR_PULL_UP_CONNECT = 1, 3338 } lsm6dsr_sdo_pu_en_t; 3339 int32_t lsm6dsr_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 3340 lsm6dsr_sdo_pu_en_t val); 3341 int32_t lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 3342 lsm6dsr_sdo_pu_en_t *val); 3343 3344 typedef enum 3345 { 3346 LSM6DSR_PULL_DOWN_CONNECT = 0, 3347 LSM6DSR_PULL_DOWN_DISC = 1, 3348 } lsm6dsr_pd_dis_int1_t; 3349 int32_t lsm6dsr_int1_mode_set(const stmdev_ctx_t *ctx, 3350 lsm6dsr_pd_dis_int1_t val); 3351 int32_t lsm6dsr_int1_mode_get(const stmdev_ctx_t *ctx, 3352 lsm6dsr_pd_dis_int1_t *val); 3353 3354 typedef enum 3355 { 3356 LSM6DSR_SPI_4_WIRE = 0, 3357 LSM6DSR_SPI_3_WIRE = 1, 3358 } lsm6dsr_sim_t; 3359 int32_t lsm6dsr_spi_mode_set(const stmdev_ctx_t *ctx, 3360 lsm6dsr_sim_t val); 3361 int32_t lsm6dsr_spi_mode_get(const stmdev_ctx_t *ctx, 3362 lsm6dsr_sim_t *val); 3363 3364 typedef enum 3365 { 3366 LSM6DSR_I2C_ENABLE = 0, 3367 LSM6DSR_I2C_DISABLE = 1, 3368 } lsm6dsr_i2c_disable_t; 3369 int32_t lsm6dsr_i2c_interface_set(const stmdev_ctx_t *ctx, 3370 lsm6dsr_i2c_disable_t val); 3371 int32_t lsm6dsr_i2c_interface_get(const stmdev_ctx_t *ctx, 3372 lsm6dsr_i2c_disable_t *val); 3373 3374 typedef enum 3375 { 3376 LSM6DSR_I3C_DISABLE = 0x80, 3377 LSM6DSR_I3C_ENABLE_T_50us = 0x00, 3378 LSM6DSR_I3C_ENABLE_T_2us = 0x01, 3379 LSM6DSR_I3C_ENABLE_T_1ms = 0x02, 3380 LSM6DSR_I3C_ENABLE_T_25ms = 0x03, 3381 } lsm6dsr_i3c_disable_t; 3382 int32_t lsm6dsr_i3c_disable_set(const stmdev_ctx_t *ctx, 3383 lsm6dsr_i3c_disable_t val); 3384 int32_t lsm6dsr_i3c_disable_get(const stmdev_ctx_t *ctx, 3385 lsm6dsr_i3c_disable_t *val); 3386 3387 typedef struct 3388 { 3389 lsm6dsr_int1_ctrl_t int1_ctrl; 3390 lsm6dsr_md1_cfg_t md1_cfg; 3391 lsm6dsr_emb_func_int1_t emb_func_int1; 3392 lsm6dsr_fsm_int1_a_t fsm_int1_a; 3393 lsm6dsr_fsm_int1_b_t fsm_int1_b; 3394 } lsm6dsr_pin_int1_route_t; 3395 int32_t lsm6dsr_pin_int1_route_set(const stmdev_ctx_t *ctx, 3396 lsm6dsr_pin_int1_route_t *val); 3397 int32_t lsm6dsr_pin_int1_route_get(const stmdev_ctx_t *ctx, 3398 lsm6dsr_pin_int1_route_t *val); 3399 3400 typedef struct 3401 { 3402 lsm6dsr_int2_ctrl_t int2_ctrl; 3403 lsm6dsr_md2_cfg_t md2_cfg; 3404 lsm6dsr_emb_func_int2_t emb_func_int2; 3405 lsm6dsr_fsm_int2_a_t fsm_int2_a; 3406 lsm6dsr_fsm_int2_b_t fsm_int2_b; 3407 } lsm6dsr_pin_int2_route_t; 3408 int32_t lsm6dsr_pin_int2_route_set(const stmdev_ctx_t *ctx, 3409 lsm6dsr_pin_int2_route_t *val); 3410 int32_t lsm6dsr_pin_int2_route_get(const stmdev_ctx_t *ctx, 3411 lsm6dsr_pin_int2_route_t *val); 3412 3413 typedef enum 3414 { 3415 LSM6DSR_PUSH_PULL = 0, 3416 LSM6DSR_OPEN_DRAIN = 1, 3417 } lsm6dsr_pp_od_t; 3418 int32_t lsm6dsr_pin_mode_set(const stmdev_ctx_t *ctx, 3419 lsm6dsr_pp_od_t val); 3420 int32_t lsm6dsr_pin_mode_get(const stmdev_ctx_t *ctx, 3421 lsm6dsr_pp_od_t *val); 3422 3423 typedef enum 3424 { 3425 LSM6DSR_ACTIVE_HIGH = 0, 3426 LSM6DSR_ACTIVE_LOW = 1, 3427 } lsm6dsr_h_lactive_t; 3428 int32_t lsm6dsr_pin_polarity_set(const stmdev_ctx_t *ctx, 3429 lsm6dsr_h_lactive_t val); 3430 int32_t lsm6dsr_pin_polarity_get(const stmdev_ctx_t *ctx, 3431 lsm6dsr_h_lactive_t *val); 3432 3433 int32_t lsm6dsr_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 3434 int32_t lsm6dsr_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3435 3436 typedef enum 3437 { 3438 LSM6DSR_ALL_INT_PULSED = 0, 3439 LSM6DSR_BASE_LATCHED_EMB_PULSED = 1, 3440 LSM6DSR_BASE_PULSED_EMB_LATCHED = 2, 3441 LSM6DSR_ALL_INT_LATCHED = 3, 3442 } lsm6dsr_lir_t; 3443 int32_t lsm6dsr_int_notification_set(const stmdev_ctx_t *ctx, 3444 lsm6dsr_lir_t val); 3445 int32_t lsm6dsr_int_notification_get(const stmdev_ctx_t *ctx, 3446 lsm6dsr_lir_t *val); 3447 3448 typedef enum 3449 { 3450 LSM6DSR_LSb_FS_DIV_64 = 0, 3451 LSM6DSR_LSb_FS_DIV_256 = 1, 3452 } lsm6dsr_wake_ths_w_t; 3453 int32_t lsm6dsr_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3454 lsm6dsr_wake_ths_w_t val); 3455 int32_t lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3456 lsm6dsr_wake_ths_w_t *val); 3457 3458 int32_t lsm6dsr_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3459 int32_t lsm6dsr_wkup_threshold_get(const stmdev_ctx_t *ctx, 3460 uint8_t *val); 3461 3462 int32_t lsm6dsr_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3463 uint8_t val); 3464 int32_t lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3465 uint8_t *val); 3466 3467 int32_t lsm6dsr_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3468 int32_t lsm6dsr_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3469 3470 int32_t lsm6dsr_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3471 int32_t lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3472 3473 typedef enum 3474 { 3475 LSM6DSR_DRIVE_SLEEP_CHG_EVENT = 0, 3476 LSM6DSR_DRIVE_SLEEP_STATUS = 1, 3477 } lsm6dsr_sleep_status_on_int_t; 3478 int32_t lsm6dsr_act_pin_notification_set(const stmdev_ctx_t *ctx, 3479 lsm6dsr_sleep_status_on_int_t val); 3480 int32_t lsm6dsr_act_pin_notification_get(const stmdev_ctx_t *ctx, 3481 lsm6dsr_sleep_status_on_int_t *val); 3482 3483 typedef enum 3484 { 3485 LSM6DSR_XL_AND_GY_NOT_AFFECTED = 0, 3486 LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED = 1, 3487 LSM6DSR_XL_12Hz5_GY_SLEEP = 2, 3488 LSM6DSR_XL_12Hz5_GY_PD = 3, 3489 } lsm6dsr_inact_en_t; 3490 int32_t lsm6dsr_act_mode_set(const stmdev_ctx_t *ctx, 3491 lsm6dsr_inact_en_t val); 3492 int32_t lsm6dsr_act_mode_get(const stmdev_ctx_t *ctx, 3493 lsm6dsr_inact_en_t *val); 3494 3495 int32_t lsm6dsr_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3496 int32_t lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3497 3498 int32_t lsm6dsr_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 3499 uint8_t val); 3500 int32_t lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 3501 uint8_t *val); 3502 3503 int32_t lsm6dsr_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 3504 uint8_t val); 3505 int32_t lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 3506 uint8_t *val); 3507 3508 int32_t lsm6dsr_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 3509 uint8_t val); 3510 int32_t lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 3511 uint8_t *val); 3512 3513 int32_t lsm6dsr_tap_threshold_x_set(const stmdev_ctx_t *ctx, 3514 uint8_t val); 3515 int32_t lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t *ctx, 3516 uint8_t *val); 3517 3518 typedef enum 3519 { 3520 LSM6DSR_XYZ = 0, 3521 LSM6DSR_YXZ = 1, 3522 LSM6DSR_XZY = 2, 3523 LSM6DSR_ZYX = 3, 3524 LSM6DSR_YZX = 5, 3525 LSM6DSR_ZXY = 6, 3526 } lsm6dsr_tap_priority_t; 3527 int32_t lsm6dsr_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3528 lsm6dsr_tap_priority_t val); 3529 int32_t lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3530 lsm6dsr_tap_priority_t *val); 3531 3532 int32_t lsm6dsr_tap_threshold_y_set(const stmdev_ctx_t *ctx, 3533 uint8_t val); 3534 int32_t lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t *ctx, 3535 uint8_t *val); 3536 3537 int32_t lsm6dsr_tap_threshold_z_set(const stmdev_ctx_t *ctx, 3538 uint8_t val); 3539 int32_t lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t *ctx, 3540 uint8_t *val); 3541 3542 int32_t lsm6dsr_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 3543 int32_t lsm6dsr_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 3544 3545 int32_t lsm6dsr_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 3546 int32_t lsm6dsr_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 3547 3548 int32_t lsm6dsr_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3549 int32_t lsm6dsr_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3550 3551 typedef enum 3552 { 3553 LSM6DSR_ONLY_SINGLE = 0, 3554 LSM6DSR_BOTH_SINGLE_DOUBLE = 1, 3555 } lsm6dsr_single_double_tap_t; 3556 int32_t lsm6dsr_tap_mode_set(const stmdev_ctx_t *ctx, 3557 lsm6dsr_single_double_tap_t val); 3558 int32_t lsm6dsr_tap_mode_get(const stmdev_ctx_t *ctx, 3559 lsm6dsr_single_double_tap_t *val); 3560 3561 typedef enum 3562 { 3563 LSM6DSR_DEG_80 = 0, 3564 LSM6DSR_DEG_70 = 1, 3565 LSM6DSR_DEG_60 = 2, 3566 LSM6DSR_DEG_50 = 3, 3567 } lsm6dsr_sixd_ths_t; 3568 int32_t lsm6dsr_6d_threshold_set(const stmdev_ctx_t *ctx, 3569 lsm6dsr_sixd_ths_t val); 3570 int32_t lsm6dsr_6d_threshold_get(const stmdev_ctx_t *ctx, 3571 lsm6dsr_sixd_ths_t *val); 3572 3573 int32_t lsm6dsr_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3574 int32_t lsm6dsr_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3575 3576 typedef enum 3577 { 3578 LSM6DSR_FF_TSH_156mg = 0, 3579 LSM6DSR_FF_TSH_219mg = 1, 3580 LSM6DSR_FF_TSH_250mg = 2, 3581 LSM6DSR_FF_TSH_312mg = 3, 3582 LSM6DSR_FF_TSH_344mg = 4, 3583 LSM6DSR_FF_TSH_406mg = 5, 3584 LSM6DSR_FF_TSH_469mg = 6, 3585 LSM6DSR_FF_TSH_500mg = 7, 3586 } lsm6dsr_ff_ths_t; 3587 int32_t lsm6dsr_ff_threshold_set(const stmdev_ctx_t *ctx, 3588 lsm6dsr_ff_ths_t val); 3589 int32_t lsm6dsr_ff_threshold_get(const stmdev_ctx_t *ctx, 3590 lsm6dsr_ff_ths_t *val); 3591 3592 int32_t lsm6dsr_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3593 int32_t lsm6dsr_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3594 3595 int32_t lsm6dsr_fifo_watermark_set(const stmdev_ctx_t *ctx, 3596 uint16_t val); 3597 int32_t lsm6dsr_fifo_watermark_get(const stmdev_ctx_t *ctx, 3598 uint16_t *val); 3599 3600 int32_t lsm6dsr_compression_algo_init_set(const stmdev_ctx_t *ctx, 3601 uint8_t val); 3602 int32_t lsm6dsr_compression_algo_init_get(const stmdev_ctx_t *ctx, 3603 uint8_t *val); 3604 3605 typedef enum 3606 { 3607 LSM6DSR_CMP_DISABLE = 0x00, 3608 LSM6DSR_CMP_ALWAYS = 0x04, 3609 LSM6DSR_CMP_8_TO_1 = 0x05, 3610 LSM6DSR_CMP_16_TO_1 = 0x06, 3611 LSM6DSR_CMP_32_TO_1 = 0x07, 3612 } lsm6dsr_uncoptr_rate_t; 3613 int32_t lsm6dsr_compression_algo_set(const stmdev_ctx_t *ctx, 3614 lsm6dsr_uncoptr_rate_t val); 3615 int32_t lsm6dsr_compression_algo_get(const stmdev_ctx_t *ctx, 3616 lsm6dsr_uncoptr_rate_t *val); 3617 3618 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3619 uint8_t val); 3620 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3621 uint8_t *val); 3622 3623 int32_t lsm6dsr_compression_algo_real_time_set(const stmdev_ctx_t *ctx, 3624 uint8_t val); 3625 int32_t lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t *ctx, 3626 uint8_t *val); 3627 3628 int32_t lsm6dsr_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 3629 uint8_t val); 3630 int32_t lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 3631 uint8_t *val); 3632 3633 typedef enum 3634 { 3635 LSM6DSR_XL_NOT_BATCHED = 0, 3636 LSM6DSR_XL_BATCHED_AT_12Hz5 = 1, 3637 LSM6DSR_XL_BATCHED_AT_26Hz = 2, 3638 LSM6DSR_XL_BATCHED_AT_52Hz = 3, 3639 LSM6DSR_XL_BATCHED_AT_104Hz = 4, 3640 LSM6DSR_XL_BATCHED_AT_208Hz = 5, 3641 LSM6DSR_XL_BATCHED_AT_417Hz = 6, 3642 LSM6DSR_XL_BATCHED_AT_833Hz = 7, 3643 LSM6DSR_XL_BATCHED_AT_1667Hz = 8, 3644 LSM6DSR_XL_BATCHED_AT_3333Hz = 9, 3645 LSM6DSR_XL_BATCHED_AT_6667Hz = 10, 3646 LSM6DSR_XL_BATCHED_AT_6Hz5 = 11, 3647 } lsm6dsr_bdr_xl_t; 3648 int32_t lsm6dsr_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3649 lsm6dsr_bdr_xl_t val); 3650 int32_t lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3651 lsm6dsr_bdr_xl_t *val); 3652 3653 typedef enum 3654 { 3655 LSM6DSR_GY_NOT_BATCHED = 0, 3656 LSM6DSR_GY_BATCHED_AT_12Hz5 = 1, 3657 LSM6DSR_GY_BATCHED_AT_26Hz = 2, 3658 LSM6DSR_GY_BATCHED_AT_52Hz = 3, 3659 LSM6DSR_GY_BATCHED_AT_104Hz = 4, 3660 LSM6DSR_GY_BATCHED_AT_208Hz = 5, 3661 LSM6DSR_GY_BATCHED_AT_417Hz = 6, 3662 LSM6DSR_GY_BATCHED_AT_833Hz = 7, 3663 LSM6DSR_GY_BATCHED_AT_1667Hz = 8, 3664 LSM6DSR_GY_BATCHED_AT_3333Hz = 9, 3665 LSM6DSR_GY_BATCHED_AT_6667Hz = 10, 3666 LSM6DSR_GY_BATCHED_6Hz5 = 11, 3667 } lsm6dsr_bdr_gy_t; 3668 int32_t lsm6dsr_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3669 lsm6dsr_bdr_gy_t val); 3670 int32_t lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3671 lsm6dsr_bdr_gy_t *val); 3672 3673 typedef enum 3674 { 3675 LSM6DSR_BYPASS_MODE = 0, 3676 LSM6DSR_FIFO_MODE = 1, 3677 LSM6DSR_STREAM_TO_FIFO_MODE = 3, 3678 LSM6DSR_BYPASS_TO_STREAM_MODE = 4, 3679 LSM6DSR_STREAM_MODE = 6, 3680 LSM6DSR_BYPASS_TO_FIFO_MODE = 7, 3681 } lsm6dsr_fifo_mode_t; 3682 int32_t lsm6dsr_fifo_mode_set(const stmdev_ctx_t *ctx, 3683 lsm6dsr_fifo_mode_t val); 3684 int32_t lsm6dsr_fifo_mode_get(const stmdev_ctx_t *ctx, 3685 lsm6dsr_fifo_mode_t *val); 3686 3687 typedef enum 3688 { 3689 LSM6DSR_TEMP_NOT_BATCHED = 0, 3690 LSM6DSR_TEMP_BATCHED_AT_52Hz = 1, 3691 LSM6DSR_TEMP_BATCHED_AT_12Hz5 = 2, 3692 LSM6DSR_TEMP_BATCHED_AT_1Hz6 = 3, 3693 } lsm6dsr_odr_t_batch_t; 3694 int32_t lsm6dsr_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3695 lsm6dsr_odr_t_batch_t val); 3696 int32_t lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3697 lsm6dsr_odr_t_batch_t *val); 3698 3699 typedef enum 3700 { 3701 LSM6DSR_NO_DECIMATION = 0, 3702 LSM6DSR_DEC_1 = 1, 3703 LSM6DSR_DEC_8 = 2, 3704 LSM6DSR_DEC_32 = 3, 3705 } lsm6dsr_odr_ts_batch_t; 3706 int32_t lsm6dsr_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3707 lsm6dsr_odr_ts_batch_t val); 3708 int32_t lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3709 lsm6dsr_odr_ts_batch_t *val); 3710 3711 typedef enum 3712 { 3713 LSM6DSR_XL_BATCH_EVENT = 0, 3714 LSM6DSR_GYRO_BATCH_EVENT = 1, 3715 } lsm6dsr_trig_counter_bdr_t; 3716 int32_t lsm6dsr_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3717 lsm6dsr_trig_counter_bdr_t val); 3718 int32_t lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3719 lsm6dsr_trig_counter_bdr_t *val); 3720 3721 int32_t lsm6dsr_rst_batch_counter_set(const stmdev_ctx_t *ctx, 3722 uint8_t val); 3723 int32_t lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t *ctx, 3724 uint8_t *val); 3725 3726 int32_t lsm6dsr_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3727 uint16_t val); 3728 int32_t lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3729 uint16_t *val); 3730 3731 int32_t lsm6dsr_fifo_data_level_get(const stmdev_ctx_t *ctx, 3732 uint16_t *val); 3733 3734 int32_t lsm6dsr_fifo_status_get(const stmdev_ctx_t *ctx, 3735 lsm6dsr_fifo_status2_t *val); 3736 3737 int32_t lsm6dsr_fifo_full_flag_get(const stmdev_ctx_t *ctx, 3738 uint8_t *val); 3739 3740 int32_t lsm6dsr_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3741 3742 int32_t lsm6dsr_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3743 3744 typedef enum 3745 { 3746 LSM6DSR_GYRO_NC_TAG = 1, 3747 LSM6DSR_XL_NC_TAG, 3748 LSM6DSR_TEMPERATURE_TAG, 3749 LSM6DSR_TIMESTAMP_TAG, 3750 LSM6DSR_CFG_CHANGE_TAG, 3751 LSM6DSR_XL_NC_T_2_TAG, 3752 LSM6DSR_XL_NC_T_1_TAG, 3753 LSM6DSR_XL_2XC_TAG, 3754 LSM6DSR_XL_3XC_TAG, 3755 LSM6DSR_GYRO_NC_T_2_TAG, 3756 LSM6DSR_GYRO_NC_T_1_TAG, 3757 LSM6DSR_GYRO_2XC_TAG, 3758 LSM6DSR_GYRO_3XC_TAG, 3759 LSM6DSR_SENSORHUB_SLAVE0_TAG, 3760 LSM6DSR_SENSORHUB_SLAVE1_TAG, 3761 LSM6DSR_SENSORHUB_SLAVE2_TAG, 3762 LSM6DSR_SENSORHUB_SLAVE3_TAG, 3763 LSM6DSR_STEP_CPUNTER_TAG, 3764 LSM6DSR_GAME_ROTATION_TAG, 3765 LSM6DSR_GEOMAG_ROTATION_TAG, 3766 LSM6DSR_ROTATION_TAG, 3767 LSM6DSR_SENSORHUB_NACK_TAG = 0x19, 3768 } lsm6dsr_fifo_tag_t; 3769 int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3770 lsm6dsr_fifo_tag_t *val); 3771 3772 int32_t lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, 3773 uint8_t val); 3774 int32_t lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, 3775 uint8_t *val); 3776 3777 int32_t lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, 3778 uint8_t val); 3779 int32_t lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, 3780 uint8_t *val); 3781 3782 int32_t lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, 3783 uint8_t val); 3784 int32_t lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, 3785 uint8_t *val); 3786 3787 int32_t lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, 3788 uint8_t val); 3789 int32_t lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, 3790 uint8_t *val); 3791 3792 int32_t lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, 3793 uint8_t val); 3794 int32_t lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, 3795 uint8_t *val); 3796 3797 typedef enum 3798 { 3799 LSM6DSR_DEN_DISABLE = 0, 3800 LSM6DSR_LEVEL_FIFO = 6, 3801 LSM6DSR_LEVEL_LETCHED = 3, 3802 LSM6DSR_LEVEL_TRIGGER = 2, 3803 LSM6DSR_EDGE_TRIGGER = 4, 3804 } lsm6dsr_den_mode_t; 3805 int32_t lsm6dsr_den_mode_set(const stmdev_ctx_t *ctx, 3806 lsm6dsr_den_mode_t val); 3807 int32_t lsm6dsr_den_mode_get(const stmdev_ctx_t *ctx, 3808 lsm6dsr_den_mode_t *val); 3809 3810 typedef enum 3811 { 3812 LSM6DSR_DEN_ACT_LOW = 0, 3813 LSM6DSR_DEN_ACT_HIGH = 1, 3814 } lsm6dsr_den_lh_t; 3815 int32_t lsm6dsr_den_polarity_set(const stmdev_ctx_t *ctx, 3816 lsm6dsr_den_lh_t val); 3817 int32_t lsm6dsr_den_polarity_get(const stmdev_ctx_t *ctx, 3818 lsm6dsr_den_lh_t *val); 3819 3820 typedef enum 3821 { 3822 LSM6DSR_STAMP_IN_GY_DATA = 0, 3823 LSM6DSR_STAMP_IN_XL_DATA = 1, 3824 LSM6DSR_STAMP_IN_GY_XL_DATA = 2, 3825 } lsm6dsr_den_xl_g_t; 3826 int32_t lsm6dsr_den_enable_set(const stmdev_ctx_t *ctx, 3827 lsm6dsr_den_xl_g_t val); 3828 int32_t lsm6dsr_den_enable_get(const stmdev_ctx_t *ctx, 3829 lsm6dsr_den_xl_g_t *val); 3830 3831 int32_t lsm6dsr_den_mark_axis_x_set(const stmdev_ctx_t *ctx, 3832 uint8_t val); 3833 int32_t lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 3834 uint8_t *val); 3835 3836 int32_t lsm6dsr_den_mark_axis_y_set(const stmdev_ctx_t *ctx, 3837 uint8_t val); 3838 int32_t lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 3839 uint8_t *val); 3840 3841 int32_t lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t *ctx, 3842 uint8_t val); 3843 int32_t lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 3844 uint8_t *val); 3845 3846 int32_t lsm6dsr_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3847 int32_t lsm6dsr_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3848 3849 typedef enum 3850 { 3851 LSM6DSR_PEDO_BASE = 0x00, 3852 LSM6DSR_PEDO_BASE_FALSE_STEP_REJ = 0x01, 3853 LSM6DSR_PEDO_ADV_FALSE_STEP_REJ = 0x03, 3854 } lsm6dsr_pedo_mode_t; 3855 int32_t lsm6dsr_pedo_mode_set(const stmdev_ctx_t *ctx, 3856 lsm6dsr_pedo_mode_t val); 3857 int32_t lsm6dsr_pedo_mode_get(const stmdev_ctx_t *ctx, 3858 lsm6dsr_pedo_mode_t *val); 3859 3860 int32_t lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t *ctx, 3861 uint8_t *val); 3862 3863 int32_t lsm6dsr_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 3864 uint8_t *val); 3865 int32_t lsm6dsr_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 3866 uint8_t *val); 3867 3868 int32_t lsm6dsr_pedo_steps_period_set(const stmdev_ctx_t *ctx, 3869 uint16_t val); 3870 int32_t lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t *ctx, 3871 uint16_t *val); 3872 3873 int32_t lsm6dsr_pedo_adv_detection_set(const stmdev_ctx_t *ctx, 3874 uint8_t val); 3875 int32_t lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t *ctx, 3876 uint8_t *val); 3877 3878 int32_t lsm6dsr_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, 3879 uint8_t val); 3880 int32_t lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, 3881 uint8_t *val); 3882 3883 typedef enum 3884 { 3885 LSM6DSR_EVERY_STEP = 0, 3886 LSM6DSR_COUNT_OVERFLOW = 1, 3887 } lsm6dsr_carry_count_en_t; 3888 int32_t lsm6dsr_pedo_int_mode_set(const stmdev_ctx_t *ctx, 3889 lsm6dsr_carry_count_en_t val); 3890 int32_t lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t *ctx, 3891 lsm6dsr_carry_count_en_t *val); 3892 3893 int32_t lsm6dsr_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3894 int32_t lsm6dsr_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3895 3896 int32_t lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, 3897 uint8_t *val); 3898 3899 int32_t lsm6dsr_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 3900 int32_t lsm6dsr_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 3901 3902 int32_t lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3903 uint8_t *val); 3904 3905 int32_t lsm6dsr_mag_sensitivity_set(const stmdev_ctx_t *ctx, 3906 uint16_t val); 3907 int32_t lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t *ctx, 3908 uint16_t *val); 3909 3910 int32_t lsm6dsr_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 3911 int32_t lsm6dsr_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 3912 3913 int32_t lsm6dsr_mag_soft_iron_set(const stmdev_ctx_t *ctx, 3914 uint16_t *val); 3915 int32_t lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t *ctx, 3916 uint16_t *val); 3917 3918 typedef enum 3919 { 3920 LSM6DSR_Z_EQ_Y = 0, 3921 LSM6DSR_Z_EQ_MIN_Y = 1, 3922 LSM6DSR_Z_EQ_X = 2, 3923 LSM6DSR_Z_EQ_MIN_X = 3, 3924 LSM6DSR_Z_EQ_MIN_Z = 4, 3925 LSM6DSR_Z_EQ_Z = 5, 3926 } lsm6dsr_mag_z_axis_t; 3927 int32_t lsm6dsr_mag_z_orient_set(const stmdev_ctx_t *ctx, 3928 lsm6dsr_mag_z_axis_t val); 3929 int32_t lsm6dsr_mag_z_orient_get(const stmdev_ctx_t *ctx, 3930 lsm6dsr_mag_z_axis_t *val); 3931 3932 typedef enum 3933 { 3934 LSM6DSR_Y_EQ_Y = 0, 3935 LSM6DSR_Y_EQ_MIN_Y = 1, 3936 LSM6DSR_Y_EQ_X = 2, 3937 LSM6DSR_Y_EQ_MIN_X = 3, 3938 LSM6DSR_Y_EQ_MIN_Z = 4, 3939 LSM6DSR_Y_EQ_Z = 5, 3940 } lsm6dsr_mag_y_axis_t; 3941 int32_t lsm6dsr_mag_y_orient_set(const stmdev_ctx_t *ctx, 3942 lsm6dsr_mag_y_axis_t val); 3943 int32_t lsm6dsr_mag_y_orient_get(const stmdev_ctx_t *ctx, 3944 lsm6dsr_mag_y_axis_t *val); 3945 3946 typedef enum 3947 { 3948 LSM6DSR_X_EQ_Y = 0, 3949 LSM6DSR_X_EQ_MIN_Y = 1, 3950 LSM6DSR_X_EQ_X = 2, 3951 LSM6DSR_X_EQ_MIN_X = 3, 3952 LSM6DSR_X_EQ_MIN_Z = 4, 3953 LSM6DSR_X_EQ_Z = 5, 3954 } lsm6dsr_mag_x_axis_t; 3955 int32_t lsm6dsr_mag_x_orient_set(const stmdev_ctx_t *ctx, 3956 lsm6dsr_mag_x_axis_t val); 3957 int32_t lsm6dsr_mag_x_orient_get(const stmdev_ctx_t *ctx, 3958 lsm6dsr_mag_x_axis_t *val); 3959 3960 int32_t lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3961 uint8_t *val); 3962 3963 int32_t lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 3964 int32_t lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 3965 3966 typedef struct 3967 { 3968 lsm6dsr_fsm_enable_a_t fsm_enable_a; 3969 lsm6dsr_fsm_enable_b_t fsm_enable_b; 3970 } lsm6dsr_emb_fsm_enable_t; 3971 int32_t lsm6dsr_fsm_enable_set(const stmdev_ctx_t *ctx, 3972 lsm6dsr_emb_fsm_enable_t *val); 3973 int32_t lsm6dsr_fsm_enable_get(const stmdev_ctx_t *ctx, 3974 lsm6dsr_emb_fsm_enable_t *val); 3975 3976 int32_t lsm6dsr_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3977 int32_t lsm6dsr_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3978 3979 typedef enum 3980 { 3981 LSM6DSR_LC_NORMAL = 0, 3982 LSM6DSR_LC_CLEAR = 1, 3983 LSM6DSR_LC_CLEAR_DONE = 2, 3984 } lsm6dsr_fsm_lc_clr_t; 3985 int32_t lsm6dsr_long_clr_set(const stmdev_ctx_t *ctx, 3986 lsm6dsr_fsm_lc_clr_t val); 3987 int32_t lsm6dsr_long_clr_get(const stmdev_ctx_t *ctx, 3988 lsm6dsr_fsm_lc_clr_t *val); 3989 3990 typedef struct 3991 { 3992 lsm6dsr_fsm_outs1_t fsm_outs1; 3993 lsm6dsr_fsm_outs2_t fsm_outs2; 3994 lsm6dsr_fsm_outs3_t fsm_outs3; 3995 lsm6dsr_fsm_outs4_t fsm_outs4; 3996 lsm6dsr_fsm_outs5_t fsm_outs5; 3997 lsm6dsr_fsm_outs6_t fsm_outs6; 3998 lsm6dsr_fsm_outs7_t fsm_outs7; 3999 lsm6dsr_fsm_outs8_t fsm_outs8; 4000 lsm6dsr_fsm_outs9_t fsm_outs9; 4001 lsm6dsr_fsm_outs10_t fsm_outs10; 4002 lsm6dsr_fsm_outs11_t fsm_outs11; 4003 lsm6dsr_fsm_outs12_t fsm_outs12; 4004 lsm6dsr_fsm_outs13_t fsm_outs13; 4005 lsm6dsr_fsm_outs14_t fsm_outs14; 4006 lsm6dsr_fsm_outs15_t fsm_outs15; 4007 lsm6dsr_fsm_outs16_t fsm_outs16; 4008 } lsm6dsr_fsm_out_t; 4009 int32_t lsm6dsr_fsm_out_get(const stmdev_ctx_t *ctx, 4010 lsm6dsr_fsm_out_t *val); 4011 4012 typedef enum 4013 { 4014 LSM6DSR_ODR_FSM_12Hz5 = 0, 4015 LSM6DSR_ODR_FSM_26Hz = 1, 4016 LSM6DSR_ODR_FSM_52Hz = 2, 4017 LSM6DSR_ODR_FSM_104Hz = 3, 4018 } lsm6dsr_fsm_odr_t; 4019 int32_t lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t *ctx, 4020 lsm6dsr_fsm_odr_t val); 4021 int32_t lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t *ctx, 4022 lsm6dsr_fsm_odr_t *val); 4023 4024 int32_t lsm6dsr_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 4025 int32_t lsm6dsr_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 4026 4027 int32_t lsm6dsr_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 4028 uint16_t val); 4029 int32_t lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 4030 uint16_t *val); 4031 4032 int32_t lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 4033 uint8_t *val); 4034 int32_t lsm6dsr_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 4035 uint8_t *val); 4036 4037 int32_t lsm6dsr_fsm_start_address_set(const stmdev_ctx_t *ctx, 4038 uint16_t val); 4039 int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, 4040 uint16_t *val); 4041 4042 typedef struct 4043 { 4044 lsm6dsr_sensor_hub_1_t sh_byte_1; 4045 lsm6dsr_sensor_hub_2_t sh_byte_2; 4046 lsm6dsr_sensor_hub_3_t sh_byte_3; 4047 lsm6dsr_sensor_hub_4_t sh_byte_4; 4048 lsm6dsr_sensor_hub_5_t sh_byte_5; 4049 lsm6dsr_sensor_hub_6_t sh_byte_6; 4050 lsm6dsr_sensor_hub_7_t sh_byte_7; 4051 lsm6dsr_sensor_hub_8_t sh_byte_8; 4052 lsm6dsr_sensor_hub_9_t sh_byte_9; 4053 lsm6dsr_sensor_hub_10_t sh_byte_10; 4054 lsm6dsr_sensor_hub_11_t sh_byte_11; 4055 lsm6dsr_sensor_hub_12_t sh_byte_12; 4056 lsm6dsr_sensor_hub_13_t sh_byte_13; 4057 lsm6dsr_sensor_hub_14_t sh_byte_14; 4058 lsm6dsr_sensor_hub_15_t sh_byte_15; 4059 lsm6dsr_sensor_hub_16_t sh_byte_16; 4060 lsm6dsr_sensor_hub_17_t sh_byte_17; 4061 lsm6dsr_sensor_hub_18_t sh_byte_18; 4062 } lsm6dsr_emb_sh_read_t; 4063 int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 4064 lsm6dsr_emb_sh_read_t *val, 4065 uint8_t len); 4066 4067 typedef enum 4068 { 4069 LSM6DSR_SLV_0 = 0, 4070 LSM6DSR_SLV_0_1 = 1, 4071 LSM6DSR_SLV_0_1_2 = 2, 4072 LSM6DSR_SLV_0_1_2_3 = 3, 4073 } lsm6dsr_aux_sens_on_t; 4074 int32_t lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t *ctx, 4075 lsm6dsr_aux_sens_on_t val); 4076 int32_t lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t *ctx, 4077 lsm6dsr_aux_sens_on_t *val); 4078 4079 int32_t lsm6dsr_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 4080 int32_t lsm6dsr_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 4081 4082 typedef enum 4083 { 4084 LSM6DSR_EXT_PULL_UP = 0, 4085 LSM6DSR_INTERNAL_PULL_UP = 1, 4086 } lsm6dsr_shub_pu_en_t; 4087 int32_t lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t *ctx, 4088 lsm6dsr_shub_pu_en_t val); 4089 int32_t lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t *ctx, 4090 lsm6dsr_shub_pu_en_t *val); 4091 4092 int32_t lsm6dsr_sh_pass_through_set(const stmdev_ctx_t *ctx, 4093 uint8_t val); 4094 int32_t lsm6dsr_sh_pass_through_get(const stmdev_ctx_t *ctx, 4095 uint8_t *val); 4096 4097 typedef enum 4098 { 4099 LSM6DSR_EXT_ON_INT2_PIN = 1, 4100 LSM6DSR_XL_GY_DRDY = 0, 4101 } lsm6dsr_start_config_t; 4102 int32_t lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 4103 lsm6dsr_start_config_t val); 4104 int32_t lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 4105 lsm6dsr_start_config_t *val); 4106 4107 typedef enum 4108 { 4109 LSM6DSR_EACH_SH_CYCLE = 0, 4110 LSM6DSR_ONLY_FIRST_CYCLE = 1, 4111 } lsm6dsr_write_once_t; 4112 int32_t lsm6dsr_sh_write_mode_set(const stmdev_ctx_t *ctx, 4113 lsm6dsr_write_once_t val); 4114 int32_t lsm6dsr_sh_write_mode_get(const stmdev_ctx_t *ctx, 4115 lsm6dsr_write_once_t *val); 4116 4117 int32_t lsm6dsr_sh_reset_set(const stmdev_ctx_t *ctx); 4118 int32_t lsm6dsr_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 4119 4120 typedef enum 4121 { 4122 LSM6DSR_SH_ODR_104Hz = 0, 4123 LSM6DSR_SH_ODR_52Hz = 1, 4124 LSM6DSR_SH_ODR_26Hz = 2, 4125 LSM6DSR_SH_ODR_13Hz = 3, 4126 } lsm6dsr_shub_odr_t; 4127 int32_t lsm6dsr_sh_data_rate_set(const stmdev_ctx_t *ctx, 4128 lsm6dsr_shub_odr_t val); 4129 int32_t lsm6dsr_sh_data_rate_get(const stmdev_ctx_t *ctx, 4130 lsm6dsr_shub_odr_t *val); 4131 4132 typedef struct 4133 { 4134 uint8_t slv0_add; 4135 uint8_t slv0_subadd; 4136 uint8_t slv0_data; 4137 } lsm6dsr_sh_cfg_write_t; 4138 int32_t lsm6dsr_sh_cfg_write(const stmdev_ctx_t *ctx, 4139 lsm6dsr_sh_cfg_write_t *val); 4140 4141 typedef struct 4142 { 4143 uint8_t slv_add; 4144 uint8_t slv_subadd; 4145 uint8_t slv_len; 4146 } lsm6dsr_sh_cfg_read_t; 4147 int32_t lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 4148 lsm6dsr_sh_cfg_read_t *val); 4149 int32_t lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 4150 lsm6dsr_sh_cfg_read_t *val); 4151 int32_t lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 4152 lsm6dsr_sh_cfg_read_t *val); 4153 int32_t lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 4154 lsm6dsr_sh_cfg_read_t *val); 4155 4156 int32_t lsm6dsr_sh_status_get(const stmdev_ctx_t *ctx, 4157 lsm6dsr_status_master_t *val); 4158 4159 typedef enum 4160 { 4161 LSM6DSR_S4S_TPH_7bit = 0, 4162 LSM6DSR_S4S_TPH_15bit = 1, 4163 } lsm6dsr_s4s_tph_res_t; 4164 int32_t lsm6dsr_s4s_tph_res_set(const stmdev_ctx_t *ctx, 4165 lsm6dsr_s4s_tph_res_t val); 4166 int32_t lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t *ctx, 4167 lsm6dsr_s4s_tph_res_t *val); 4168 4169 int32_t lsm6dsr_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); 4170 int32_t lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); 4171 4172 typedef enum 4173 { 4174 LSM6DSR_S4S_DT_RES_11 = 0, 4175 LSM6DSR_S4S_DT_RES_12 = 1, 4176 LSM6DSR_S4S_DT_RES_13 = 2, 4177 LSM6DSR_S4S_DT_RES_14 = 3, 4178 } lsm6dsr_s4s_res_ratio_t; 4179 int32_t lsm6dsr_s4s_res_ratio_set(const stmdev_ctx_t *ctx, 4180 lsm6dsr_s4s_res_ratio_t val); 4181 int32_t lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t *ctx, 4182 lsm6dsr_s4s_res_ratio_t *val); 4183 4184 int32_t lsm6dsr_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); 4185 int32_t lsm6dsr_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); 4186 4187 int32_t lsm6dsr_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); 4188 int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); 4189 4190 /** 4191 *@} 4192 * 4193 */ 4194 4195 #ifdef __cplusplus 4196 } 4197 #endif 4198 4199 #endif /* LSM6DSR_REGS_H */ 4200 4201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4202
