1 /**
2 ******************************************************************************
3 * @file lsm6dsr_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSR driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsr_reg.h"
21
22 /**
23 * @defgroup LSM6DSR
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsr enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSR_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsr_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsr_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSR_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm6dsr_from_fs2g_to_mg(int16_t lsb)103 float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
lsm6dsr_from_fs4g_to_mg(int16_t lsb)108 float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
lsm6dsr_from_fs8g_to_mg(int16_t lsb)113 float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
lsm6dsr_from_fs16g_to_mg(int16_t lsb)118 float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
lsm6dsr_from_fs125dps_to_mdps(int16_t lsb)123 float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
lsm6dsr_from_fs250dps_to_mdps(int16_t lsb)128 float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.75f);
131 }
132
lsm6dsr_from_fs500dps_to_mdps(int16_t lsb)133 float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb)138 float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb)143 float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb)148 float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb)
149 {
150 return ((float_t)lsb * 140.0f);
151 }
152
lsm6dsr_from_lsb_to_celsius(int16_t lsb)153 float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb)
154 {
155 return (((float_t)lsb / 256.0f) + 25.0f);
156 }
157
lsm6dsr_from_lsb_to_nsec(uint32_t lsb)158 uint64_t lsm6dsr_from_lsb_to_nsec(uint32_t lsb)
159 {
160 return ((uint64_t)lsb * 25000ULL);
161 }
162
163 /**
164 * @}
165 *
166 */
167
168 /**
169 * @defgroup LSM9DS1_Data_generation
170 * @brief This section groups all the functions concerning data
171 * generation
172 * @{
173 *
174 */
175
176 /**
177 * @brief Accelerometer full-scale selection[set]
178 *
179 * @param ctx Read / write interface definitions.(ptr)
180 * @param val Change the values of fs_xl in reg CTRL1_XL
181 * @retval Interface status (MANDATORY: return 0 -> no Error).
182 *
183 */
lsm6dsr_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsr_fs_xl_t val)184 int32_t lsm6dsr_xl_full_scale_set(const stmdev_ctx_t *ctx,
185 lsm6dsr_fs_xl_t val)
186 {
187 lsm6dsr_ctrl1_xl_t ctrl1_xl;
188 int32_t ret;
189 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
190 (uint8_t *)&ctrl1_xl, 1);
191
192 if (ret == 0)
193 {
194 ctrl1_xl.fs_xl = (uint8_t)val;
195 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
196 (uint8_t *)&ctrl1_xl, 1);
197 }
198
199 return ret;
200 }
201
202 /**
203 * @brief Accelerometer full-scale selection.[get]
204 *
205 * @param ctx Read / write interface definitions.(ptr)
206 * @param val Get the values of fs_xl in reg CTRL1_XL
207 * @retval Interface status (MANDATORY: return 0 -> no Error).
208 *
209 */
lsm6dsr_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsr_fs_xl_t * val)210 int32_t lsm6dsr_xl_full_scale_get(const stmdev_ctx_t *ctx,
211 lsm6dsr_fs_xl_t *val)
212 {
213 lsm6dsr_ctrl1_xl_t ctrl1_xl;
214 int32_t ret;
215 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
216 (uint8_t *)&ctrl1_xl, 1);
217
218 switch (ctrl1_xl.fs_xl)
219 {
220 case LSM6DSR_2g:
221 *val = LSM6DSR_2g;
222 break;
223
224 case LSM6DSR_16g:
225 *val = LSM6DSR_16g;
226 break;
227
228 case LSM6DSR_4g:
229 *val = LSM6DSR_4g;
230 break;
231
232 case LSM6DSR_8g:
233 *val = LSM6DSR_8g;
234 break;
235
236 default:
237 *val = LSM6DSR_2g;
238 break;
239 }
240
241 return ret;
242 }
243
244 /**
245 * @brief Accelerometer UI data rate selection.[set]
246 *
247 * @param ctx Read / write interface definitions.(ptr)
248 * @param val Change the values of odr_xl in reg CTRL1_XL
249 * @retval Interface status (MANDATORY: return 0 -> no Error).
250 *
251 */
lsm6dsr_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsr_odr_xl_t val)252 int32_t lsm6dsr_xl_data_rate_set(const stmdev_ctx_t *ctx,
253 lsm6dsr_odr_xl_t val)
254 {
255 lsm6dsr_odr_xl_t odr_xl = val;
256 lsm6dsr_emb_fsm_enable_t fsm_enable;
257 lsm6dsr_fsm_odr_t fsm_odr;
258 lsm6dsr_ctrl1_xl_t ctrl1_xl;
259 int32_t ret;
260
261 /* Check the Finite State Machine data rate constraints */
262 ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
263
264 if (ret == 0)
265 {
266 if ((fsm_enable.fsm_enable_a.fsm1_en |
267 fsm_enable.fsm_enable_a.fsm2_en |
268 fsm_enable.fsm_enable_a.fsm3_en |
269 fsm_enable.fsm_enable_a.fsm4_en |
270 fsm_enable.fsm_enable_a.fsm5_en |
271 fsm_enable.fsm_enable_a.fsm6_en |
272 fsm_enable.fsm_enable_a.fsm7_en |
273 fsm_enable.fsm_enable_a.fsm8_en |
274 fsm_enable.fsm_enable_b.fsm9_en |
275 fsm_enable.fsm_enable_b.fsm10_en |
276 fsm_enable.fsm_enable_b.fsm11_en |
277 fsm_enable.fsm_enable_b.fsm12_en |
278 fsm_enable.fsm_enable_b.fsm13_en |
279 fsm_enable.fsm_enable_b.fsm14_en |
280 fsm_enable.fsm_enable_b.fsm15_en |
281 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
282 {
283 ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
284
285 if (ret == 0)
286 {
287 switch (fsm_odr)
288 {
289 case LSM6DSR_ODR_FSM_12Hz5:
290 if (val == LSM6DSR_XL_ODR_OFF)
291 {
292 odr_xl = LSM6DSR_XL_ODR_12Hz5;
293 }
294
295 else
296 {
297 odr_xl = val;
298 }
299
300 break;
301
302 case LSM6DSR_ODR_FSM_26Hz:
303 if (val == LSM6DSR_XL_ODR_OFF)
304 {
305 odr_xl = LSM6DSR_XL_ODR_26Hz;
306 }
307
308 else if (val == LSM6DSR_XL_ODR_12Hz5)
309 {
310 odr_xl = LSM6DSR_XL_ODR_26Hz;
311 }
312
313 else
314 {
315 odr_xl = val;
316 }
317
318 break;
319
320 case LSM6DSR_ODR_FSM_52Hz:
321 if (val == LSM6DSR_XL_ODR_OFF)
322 {
323 odr_xl = LSM6DSR_XL_ODR_52Hz;
324 }
325
326 else if (val == LSM6DSR_XL_ODR_12Hz5)
327 {
328 odr_xl = LSM6DSR_XL_ODR_52Hz;
329 }
330
331 else if (val == LSM6DSR_XL_ODR_26Hz)
332 {
333 odr_xl = LSM6DSR_XL_ODR_52Hz;
334 }
335
336 else
337 {
338 odr_xl = val;
339 }
340
341 break;
342
343 case LSM6DSR_ODR_FSM_104Hz:
344 if (val == LSM6DSR_XL_ODR_OFF)
345 {
346 odr_xl = LSM6DSR_XL_ODR_104Hz;
347 }
348
349 else if (val == LSM6DSR_XL_ODR_12Hz5)
350 {
351 odr_xl = LSM6DSR_XL_ODR_104Hz;
352 }
353
354 else if (val == LSM6DSR_XL_ODR_26Hz)
355 {
356 odr_xl = LSM6DSR_XL_ODR_104Hz;
357 }
358
359 else if (val == LSM6DSR_XL_ODR_52Hz)
360 {
361 odr_xl = LSM6DSR_XL_ODR_104Hz;
362 }
363
364 else
365 {
366 odr_xl = val;
367 }
368
369 break;
370
371 default:
372 odr_xl = val;
373 break;
374 }
375 }
376 }
377 }
378
379 if (ret == 0)
380 {
381 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
382 (uint8_t *)&ctrl1_xl, 1);
383 }
384
385 if (ret == 0)
386 {
387 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
388 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
389 (uint8_t *)&ctrl1_xl, 1);
390 }
391
392 return ret;
393 }
394
395 /**
396 * @brief Accelerometer UI data rate selection.[get]
397 *
398 * @param ctx Read / write interface definitions.(ptr)
399 * @param val Get the values of odr_xl in reg CTRL1_XL
400 * @retval Interface status (MANDATORY: return 0 -> no Error).
401 *
402 */
lsm6dsr_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsr_odr_xl_t * val)403 int32_t lsm6dsr_xl_data_rate_get(const stmdev_ctx_t *ctx,
404 lsm6dsr_odr_xl_t *val)
405 {
406 lsm6dsr_ctrl1_xl_t ctrl1_xl;
407 int32_t ret;
408 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
409 (uint8_t *)&ctrl1_xl, 1);
410
411 switch (ctrl1_xl.odr_xl)
412 {
413 case LSM6DSR_XL_ODR_OFF:
414 *val = LSM6DSR_XL_ODR_OFF;
415 break;
416
417 case LSM6DSR_XL_ODR_12Hz5:
418 *val = LSM6DSR_XL_ODR_12Hz5;
419 break;
420
421 case LSM6DSR_XL_ODR_26Hz:
422 *val = LSM6DSR_XL_ODR_26Hz;
423 break;
424
425 case LSM6DSR_XL_ODR_52Hz:
426 *val = LSM6DSR_XL_ODR_52Hz;
427 break;
428
429 case LSM6DSR_XL_ODR_104Hz:
430 *val = LSM6DSR_XL_ODR_104Hz;
431 break;
432
433 case LSM6DSR_XL_ODR_208Hz:
434 *val = LSM6DSR_XL_ODR_208Hz;
435 break;
436
437 case LSM6DSR_XL_ODR_416Hz:
438 *val = LSM6DSR_XL_ODR_416Hz;
439 break;
440
441 case LSM6DSR_XL_ODR_833Hz:
442 *val = LSM6DSR_XL_ODR_833Hz;
443 break;
444
445 case LSM6DSR_XL_ODR_1666Hz:
446 *val = LSM6DSR_XL_ODR_1666Hz;
447 break;
448
449 case LSM6DSR_XL_ODR_3332Hz:
450 *val = LSM6DSR_XL_ODR_3332Hz;
451 break;
452
453 case LSM6DSR_XL_ODR_6667Hz:
454 *val = LSM6DSR_XL_ODR_6667Hz;
455 break;
456
457 case LSM6DSR_XL_ODR_1Hz6:
458 *val = LSM6DSR_XL_ODR_1Hz6;
459 break;
460
461 default:
462 *val = LSM6DSR_XL_ODR_OFF;
463 break;
464 }
465
466 return ret;
467 }
468
469 /**
470 * @brief Gyroscope UI chain full-scale selection.[set]
471 *
472 * @param ctx Read / write interface definitions.(ptr)
473 * @param val Change the values of fs_g in reg CTRL2_G
474 * @retval Interface status (MANDATORY: return 0 -> no Error).
475 *
476 */
lsm6dsr_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsr_fs_g_t val)477 int32_t lsm6dsr_gy_full_scale_set(const stmdev_ctx_t *ctx,
478 lsm6dsr_fs_g_t val)
479 {
480 lsm6dsr_ctrl2_g_t ctrl2_g;
481 int32_t ret;
482 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G,
483 (uint8_t *)&ctrl2_g, 1);
484
485 if (ret == 0)
486 {
487 ctrl2_g.fs_g = (uint8_t)val;
488 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G,
489 (uint8_t *)&ctrl2_g, 1);
490 }
491
492 return ret;
493 }
494
495 /**
496 * @brief Gyroscope UI chain full-scale selection.[get]
497 *
498 * @param ctx Read / write interface definitions.(ptr)
499 * @param val Get the values of fs_g in reg CTRL2_G
500 * @retval Interface status (MANDATORY: return 0 -> no Error).
501 *
502 */
lsm6dsr_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsr_fs_g_t * val)503 int32_t lsm6dsr_gy_full_scale_get(const stmdev_ctx_t *ctx,
504 lsm6dsr_fs_g_t *val)
505 {
506 lsm6dsr_ctrl2_g_t ctrl2_g;
507 int32_t ret;
508 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G,
509 (uint8_t *)&ctrl2_g, 1);
510
511 switch (ctrl2_g.fs_g)
512 {
513 case LSM6DSR_125dps:
514 *val = LSM6DSR_125dps;
515 break;
516
517 case LSM6DSR_250dps:
518 *val = LSM6DSR_250dps;
519 break;
520
521 case LSM6DSR_500dps:
522 *val = LSM6DSR_500dps;
523 break;
524
525 case LSM6DSR_1000dps:
526 *val = LSM6DSR_1000dps;
527 break;
528
529 case LSM6DSR_2000dps:
530 *val = LSM6DSR_2000dps;
531 break;
532
533 case LSM6DSR_4000dps:
534 *val = LSM6DSR_4000dps;
535 break;
536
537 default:
538 *val = LSM6DSR_125dps;
539 break;
540 }
541
542 return ret;
543 }
544
545 /**
546 * @brief Gyroscope data rate.[set]
547 *
548 * @param ctx Read / write interface definitions.(ptr)
549 * @param val Change the values of odr_g in reg CTRL2_G
550 * @retval Interface status (MANDATORY: return 0 -> no Error).
551 *
552 */
lsm6dsr_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsr_odr_g_t val)553 int32_t lsm6dsr_gy_data_rate_set(const stmdev_ctx_t *ctx,
554 lsm6dsr_odr_g_t val)
555 {
556 lsm6dsr_odr_g_t odr_gy = val;
557 lsm6dsr_emb_fsm_enable_t fsm_enable;
558 lsm6dsr_fsm_odr_t fsm_odr;
559 lsm6dsr_ctrl2_g_t ctrl2_g;
560 int32_t ret;
561
562 /* Check the Finite State Machine data rate constraints */
563 ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
564
565 if (ret == 0)
566 {
567 if ((fsm_enable.fsm_enable_a.fsm1_en |
568 fsm_enable.fsm_enable_a.fsm2_en |
569 fsm_enable.fsm_enable_a.fsm3_en |
570 fsm_enable.fsm_enable_a.fsm4_en |
571 fsm_enable.fsm_enable_a.fsm5_en |
572 fsm_enable.fsm_enable_a.fsm6_en |
573 fsm_enable.fsm_enable_a.fsm7_en |
574 fsm_enable.fsm_enable_a.fsm8_en |
575 fsm_enable.fsm_enable_b.fsm9_en |
576 fsm_enable.fsm_enable_b.fsm10_en |
577 fsm_enable.fsm_enable_b.fsm11_en |
578 fsm_enable.fsm_enable_b.fsm12_en |
579 fsm_enable.fsm_enable_b.fsm13_en |
580 fsm_enable.fsm_enable_b.fsm14_en |
581 fsm_enable.fsm_enable_b.fsm15_en |
582 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
583 {
584 ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
585
586 if (ret == 0)
587 {
588 switch (fsm_odr)
589 {
590 case LSM6DSR_ODR_FSM_12Hz5:
591 if (val == LSM6DSR_GY_ODR_OFF)
592 {
593 odr_gy = LSM6DSR_GY_ODR_12Hz5;
594 }
595
596 else
597 {
598 odr_gy = val;
599 }
600
601 break;
602
603 case LSM6DSR_ODR_FSM_26Hz:
604 if (val == LSM6DSR_GY_ODR_OFF)
605 {
606 odr_gy = LSM6DSR_GY_ODR_26Hz;
607 }
608
609 else if (val == LSM6DSR_GY_ODR_12Hz5)
610 {
611 odr_gy = LSM6DSR_GY_ODR_26Hz;
612 }
613
614 else
615 {
616 odr_gy = val;
617 }
618
619 break;
620
621 case LSM6DSR_ODR_FSM_52Hz:
622 if (val == LSM6DSR_GY_ODR_OFF)
623 {
624 odr_gy = LSM6DSR_GY_ODR_52Hz;
625 }
626
627 else if (val == LSM6DSR_GY_ODR_12Hz5)
628 {
629 odr_gy = LSM6DSR_GY_ODR_52Hz;
630 }
631
632 else if (val == LSM6DSR_GY_ODR_26Hz)
633 {
634 odr_gy = LSM6DSR_GY_ODR_52Hz;
635 }
636
637 else
638 {
639 odr_gy = val;
640 }
641
642 break;
643
644 case LSM6DSR_ODR_FSM_104Hz:
645 if (val == LSM6DSR_GY_ODR_OFF)
646 {
647 odr_gy = LSM6DSR_GY_ODR_104Hz;
648 }
649
650 else if (val == LSM6DSR_GY_ODR_12Hz5)
651 {
652 odr_gy = LSM6DSR_GY_ODR_104Hz;
653 }
654
655 else if (val == LSM6DSR_GY_ODR_26Hz)
656 {
657 odr_gy = LSM6DSR_GY_ODR_104Hz;
658 }
659
660 else if (val == LSM6DSR_GY_ODR_52Hz)
661 {
662 odr_gy = LSM6DSR_GY_ODR_104Hz;
663 }
664
665 else
666 {
667 odr_gy = val;
668 }
669
670 break;
671
672 default:
673 odr_gy = val;
674 break;
675 }
676 }
677 }
678 }
679
680 if (ret == 0)
681 {
682 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G,
683 (uint8_t *)&ctrl2_g, 1);
684 }
685
686 if (ret == 0)
687 {
688 ctrl2_g.odr_g = (uint8_t)odr_gy;
689 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G,
690 (uint8_t *)&ctrl2_g, 1);
691 }
692
693 return ret;
694 }
695
696 /**
697 * @brief Gyroscope data rate.[get]
698 *
699 * @param ctx Read / write interface definitions.(ptr)
700 * @param val Get the values of odr_g in reg CTRL2_G
701 * @retval Interface status (MANDATORY: return 0 -> no Error).
702 *
703 */
lsm6dsr_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsr_odr_g_t * val)704 int32_t lsm6dsr_gy_data_rate_get(const stmdev_ctx_t *ctx,
705 lsm6dsr_odr_g_t *val)
706 {
707 lsm6dsr_ctrl2_g_t ctrl2_g;
708 int32_t ret;
709 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G,
710 (uint8_t *)&ctrl2_g, 1);
711
712 switch (ctrl2_g.odr_g)
713 {
714 case LSM6DSR_GY_ODR_OFF:
715 *val = LSM6DSR_GY_ODR_OFF;
716 break;
717
718 case LSM6DSR_GY_ODR_12Hz5:
719 *val = LSM6DSR_GY_ODR_12Hz5;
720 break;
721
722 case LSM6DSR_GY_ODR_26Hz:
723 *val = LSM6DSR_GY_ODR_26Hz;
724 break;
725
726 case LSM6DSR_GY_ODR_52Hz:
727 *val = LSM6DSR_GY_ODR_52Hz;
728 break;
729
730 case LSM6DSR_GY_ODR_104Hz:
731 *val = LSM6DSR_GY_ODR_104Hz;
732 break;
733
734 case LSM6DSR_GY_ODR_208Hz:
735 *val = LSM6DSR_GY_ODR_208Hz;
736 break;
737
738 case LSM6DSR_GY_ODR_416Hz:
739 *val = LSM6DSR_GY_ODR_416Hz;
740 break;
741
742 case LSM6DSR_GY_ODR_833Hz:
743 *val = LSM6DSR_GY_ODR_833Hz;
744 break;
745
746 case LSM6DSR_GY_ODR_1666Hz:
747 *val = LSM6DSR_GY_ODR_1666Hz;
748 break;
749
750 case LSM6DSR_GY_ODR_3332Hz:
751 *val = LSM6DSR_GY_ODR_3332Hz;
752 break;
753
754 case LSM6DSR_GY_ODR_6667Hz:
755 *val = LSM6DSR_GY_ODR_6667Hz;
756 break;
757
758 default:
759 *val = LSM6DSR_GY_ODR_OFF;
760 break;
761 }
762
763 return ret;
764 }
765
766 /**
767 * @brief Block data update.[set]
768 *
769 * @param ctx Read / write interface definitions.(ptr)
770 * @param val Change the values of bdu in reg CTRL3_C
771 * @retval Interface status (MANDATORY: return 0 -> no Error).
772 *
773 */
lsm6dsr_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)774 int32_t lsm6dsr_block_data_update_set(const stmdev_ctx_t *ctx,
775 uint8_t val)
776 {
777 lsm6dsr_ctrl3_c_t ctrl3_c;
778 int32_t ret;
779 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
780 (uint8_t *)&ctrl3_c, 1);
781
782 if (ret == 0)
783 {
784 ctrl3_c.bdu = (uint8_t)val;
785 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
786 (uint8_t *)&ctrl3_c, 1);
787 }
788
789 return ret;
790 }
791
792 /**
793 * @brief Block data update.[get]
794 *
795 * @param ctx Read / write interface definitions.(ptr)
796 * @param val Change the values of bdu in reg CTRL3_C
797 * @retval Interface status (MANDATORY: return 0 -> no Error).
798 *
799 */
lsm6dsr_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)800 int32_t lsm6dsr_block_data_update_get(const stmdev_ctx_t *ctx,
801 uint8_t *val)
802 {
803 lsm6dsr_ctrl3_c_t ctrl3_c;
804 int32_t ret;
805 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
806 (uint8_t *)&ctrl3_c, 1);
807 *val = ctrl3_c.bdu;
808
809 return ret;
810 }
811
812 /**
813 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
814 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
815 *
816 * @param ctx Read / write interface definitions.(ptr)
817 * @param val Change the values of usr_off_w in reg CTRL6_C
818 * @retval Interface status (MANDATORY: return 0 -> no Error).
819 *
820 */
lsm6dsr_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dsr_usr_off_w_t val)821 int32_t lsm6dsr_xl_offset_weight_set(const stmdev_ctx_t *ctx,
822 lsm6dsr_usr_off_w_t val)
823 {
824 lsm6dsr_ctrl6_c_t ctrl6_c;
825 int32_t ret;
826 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
827 (uint8_t *)&ctrl6_c, 1);
828
829 if (ret == 0)
830 {
831 ctrl6_c.usr_off_w = (uint8_t)val;
832 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C,
833 (uint8_t *)&ctrl6_c, 1);
834 }
835
836 return ret;
837 }
838
839 /**
840 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
841 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
842 *
843 * @param ctx Read / write interface definitions.(ptr)
844 * @param val Get the values of usr_off_w in reg CTRL6_C
845 * @retval Interface status (MANDATORY: return 0 -> no Error).
846 *
847 */
lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dsr_usr_off_w_t * val)848 int32_t lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t *ctx,
849 lsm6dsr_usr_off_w_t *val)
850 {
851 lsm6dsr_ctrl6_c_t ctrl6_c;
852 int32_t ret;
853 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
854 (uint8_t *)&ctrl6_c, 1);
855
856 switch (ctrl6_c.usr_off_w)
857 {
858 case LSM6DSR_LSb_1mg:
859 *val = LSM6DSR_LSb_1mg;
860 break;
861
862 case LSM6DSR_LSb_16mg:
863 *val = LSM6DSR_LSb_16mg;
864 break;
865
866 default:
867 *val = LSM6DSR_LSb_1mg;
868 break;
869 }
870
871 return ret;
872 }
873
874 /**
875 * @brief Accelerometer power mode.[set]
876 *
877 * @param ctx Read / write interface definitions.(ptr)
878 * @param val Change the values of xl_hm_mode in reg CTRL6_C
879 * @retval Interface status (MANDATORY: return 0 -> no Error).
880 *
881 */
lsm6dsr_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_xl_hm_mode_t val)882 int32_t lsm6dsr_xl_power_mode_set(const stmdev_ctx_t *ctx,
883 lsm6dsr_xl_hm_mode_t val)
884 {
885 lsm6dsr_ctrl6_c_t ctrl6_c;
886 int32_t ret;
887 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
888 (uint8_t *)&ctrl6_c, 1);
889
890 if (ret == 0)
891 {
892 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
893 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C,
894 (uint8_t *)&ctrl6_c, 1);
895 }
896
897 return ret;
898 }
899
900 /**
901 * @brief Accelerometer power mode[get]
902 *
903 * @param ctx Read / write interface definitions.(ptr)
904 * @param val Get the values of xl_hm_mode in reg CTRL6_C
905 * @retval Interface status (MANDATORY: return 0 -> no Error).
906 *
907 */
lsm6dsr_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_xl_hm_mode_t * val)908 int32_t lsm6dsr_xl_power_mode_get(const stmdev_ctx_t *ctx,
909 lsm6dsr_xl_hm_mode_t *val)
910 {
911 lsm6dsr_ctrl6_c_t ctrl6_c;
912 int32_t ret;
913 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
914 (uint8_t *)&ctrl6_c, 1);
915
916 switch (ctrl6_c.xl_hm_mode)
917 {
918 case LSM6DSR_HIGH_PERFORMANCE_MD:
919 *val = LSM6DSR_HIGH_PERFORMANCE_MD;
920 break;
921
922 case LSM6DSR_LOW_NORMAL_POWER_MD:
923 *val = LSM6DSR_LOW_NORMAL_POWER_MD;
924 break;
925
926 default:
927 *val = LSM6DSR_HIGH_PERFORMANCE_MD;
928 break;
929 }
930
931 return ret;
932 }
933
934 /**
935 * @brief Operating mode for gyroscope.[set]
936 *
937 * @param ctx Read / write interface definitions.(ptr)
938 * @param val Change the values of g_hm_mode in reg CTRL7_G
939 * @retval Interface status (MANDATORY: return 0 -> no Error).
940 *
941 */
lsm6dsr_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_g_hm_mode_t val)942 int32_t lsm6dsr_gy_power_mode_set(const stmdev_ctx_t *ctx,
943 lsm6dsr_g_hm_mode_t val)
944 {
945 lsm6dsr_ctrl7_g_t ctrl7_g;
946 int32_t ret;
947 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
948 (uint8_t *)&ctrl7_g, 1);
949
950 if (ret == 0)
951 {
952 ctrl7_g.g_hm_mode = (uint8_t)val;
953 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G,
954 (uint8_t *)&ctrl7_g, 1);
955 }
956
957 return ret;
958 }
959
960 /**
961 * @brief gy_power_mode: [get] Operating mode for gyroscope.
962 *
963 * @param ctx Read / write interface definitions.(ptr)
964 * @param val Get the values of g_hm_mode in reg CTRL7_G
965 * @retval Interface status (MANDATORY: return 0 -> no Error).
966 *
967 */
lsm6dsr_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_g_hm_mode_t * val)968 int32_t lsm6dsr_gy_power_mode_get(const stmdev_ctx_t *ctx,
969 lsm6dsr_g_hm_mode_t *val)
970 {
971 lsm6dsr_ctrl7_g_t ctrl7_g;
972 int32_t ret;
973 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
974 (uint8_t *)&ctrl7_g, 1);
975
976 switch (ctrl7_g.g_hm_mode)
977 {
978 case LSM6DSR_GY_HIGH_PERFORMANCE:
979 *val = LSM6DSR_GY_HIGH_PERFORMANCE;
980 break;
981
982 case LSM6DSR_GY_NORMAL:
983 *val = LSM6DSR_GY_NORMAL;
984 break;
985
986 default:
987 *val = LSM6DSR_GY_HIGH_PERFORMANCE;
988 break;
989 }
990
991 return ret;
992 }
993
994 /**
995 * @brief Read all the interrupt flag of the device.
996 *[get]
997 * @param ctx Read / write interface definitions.(ptr)
998 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
999 * TAP_SRC; D6D_SRC; STATUS_REG;
1000 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1001 * @retval Interface status (MANDATORY: return 0 -> no Error).
1002 *
1003 */
lsm6dsr_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsr_all_sources_t * val)1004 int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx,
1005 lsm6dsr_all_sources_t *val)
1006 {
1007 int32_t ret;
1008
1009 ret = lsm6dsr_read_reg(ctx, LSM6DSR_ALL_INT_SRC,
1010 (uint8_t *)&val->all_int_src, 1);
1011
1012 if (ret == 0)
1013 {
1014 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_SRC,
1015 (uint8_t *)&val->wake_up_src, 1);
1016 }
1017
1018 if (ret == 0)
1019 {
1020 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_SRC,
1021 (uint8_t *)&val->tap_src, 1);
1022 }
1023
1024 if (ret == 0)
1025 {
1026 ret = lsm6dsr_read_reg(ctx, LSM6DSR_D6D_SRC,
1027 (uint8_t *)&val->d6d_src, 1);
1028 }
1029
1030 if (ret == 0)
1031 {
1032 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1033 (uint8_t *)&val->status_reg, 1);
1034 }
1035
1036 if (ret == 0)
1037 {
1038 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1039 }
1040
1041 if (ret == 0)
1042 {
1043 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
1044 (uint8_t *)&val->emb_func_status, 1);
1045 }
1046
1047 if (ret == 0)
1048 {
1049 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_A,
1050 (uint8_t *)&val->fsm_status_a, 1);
1051 }
1052
1053 if (ret == 0)
1054 {
1055 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_B,
1056 (uint8_t *)&val->fsm_status_b, 1);
1057 }
1058
1059 if (ret == 0)
1060 {
1061 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1062 }
1063
1064 return ret;
1065 }
1066
1067 /**
1068 * @brief The STATUS_REG register is read by the primary interface.[get]
1069 *
1070 * @param ctx Read / write interface definitions.(ptr)
1071 * @param val Get register STATUS_REG
1072 * @retval Interface status (MANDATORY: return 0 -> no Error).
1073 *
1074 */
lsm6dsr_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsr_status_reg_t * val)1075 int32_t lsm6dsr_status_reg_get(const stmdev_ctx_t *ctx,
1076 lsm6dsr_status_reg_t *val)
1077 {
1078 int32_t ret;
1079
1080 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *) val, 1);
1081
1082 return ret;
1083 }
1084
1085 /**
1086 * @brief Accelerometer new data available.[get]
1087 *
1088 * @param ctx Read / write interface definitions.(ptr)
1089 * @param val Change the values of xlda in reg STATUS_REG
1090 * @retval Interface status (MANDATORY: return 0 -> no Error).
1091 *
1092 */
lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1093 int32_t lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
1094 uint8_t *val)
1095 {
1096 lsm6dsr_status_reg_t status_reg;
1097 int32_t ret;
1098
1099 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1100 (uint8_t *)&status_reg, 1);
1101 *val = status_reg.xlda;
1102
1103 return ret;
1104 }
1105
1106 /**
1107 * @brief Gyroscope new data available.[get]
1108 *
1109 * @param ctx Read / write interface definitions.(ptr)
1110 * @param val Change the values of gda in reg STATUS_REG
1111 * @retval Interface status (MANDATORY: return 0 -> no Error).
1112 *
1113 */
lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1114 int32_t lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1115 uint8_t *val)
1116 {
1117 lsm6dsr_status_reg_t status_reg;
1118 int32_t ret;
1119
1120 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1121 (uint8_t *)&status_reg, 1);
1122 *val = status_reg.gda;
1123
1124 return ret;
1125 }
1126
1127 /**
1128 * @brief Temperature new data available.[get]
1129 *
1130 * @param ctx Read / write interface definitions.(ptr)
1131 * @param val Change the values of tda in reg STATUS_REG
1132 * @retval Interface status (MANDATORY: return 0 -> no Error).
1133 *
1134 */
lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1135 int32_t lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1136 uint8_t *val)
1137 {
1138 lsm6dsr_status_reg_t status_reg;
1139 int32_t ret;
1140
1141 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1142 (uint8_t *)&status_reg, 1);
1143 *val = status_reg.tda;
1144
1145 return ret;
1146 }
1147
1148 /**
1149 * @brief Accelerometer X-axis user offset correction expressed in two's
1150 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1151 * The value must be in the range [-127 127].[set]
1152 *
1153 * @param ctx Read / write interface definitions.(ptr)
1154 * @param buff Buffer that contains data to write
1155 * @retval Interface status (MANDATORY: return 0 -> no Error).
1156 *
1157 */
lsm6dsr_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1158 int32_t lsm6dsr_xl_usr_offset_x_set(const stmdev_ctx_t *ctx,
1159 uint8_t *buff)
1160 {
1161 int32_t ret;
1162
1163 ret = lsm6dsr_write_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
1164
1165 return ret;
1166 }
1167
1168 /**
1169 * @brief Accelerometer X-axis user offset correction expressed in two's
1170 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1171 * The value must be in the range [-127 127].[get]
1172 *
1173 * @param ctx Read / write interface definitions.(ptr)
1174 * @param buff Buffer that stores data read
1175 * @retval Interface status (MANDATORY: return 0 -> no Error).
1176 *
1177 */
lsm6dsr_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1178 int32_t lsm6dsr_xl_usr_offset_x_get(const stmdev_ctx_t *ctx,
1179 uint8_t *buff)
1180 {
1181 int32_t ret;
1182
1183 ret = lsm6dsr_read_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Accelerometer Y-axis user offset correction expressed in two's
1190 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1191 * The value must be in the range [-127 127].[set]
1192 *
1193 * @param ctx Read / write interface definitions.(ptr)
1194 * @param buff Buffer that contains data to write
1195 * @retval Interface status (MANDATORY: return 0 -> no Error).
1196 *
1197 */
lsm6dsr_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1198 int32_t lsm6dsr_xl_usr_offset_y_set(const stmdev_ctx_t *ctx,
1199 uint8_t *buff)
1200 {
1201 int32_t ret;
1202
1203 ret = lsm6dsr_write_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
1204
1205 return ret;
1206 }
1207
1208 /**
1209 * @brief Accelerometer Y-axis user offset correction expressed in two's
1210 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1211 * The value must be in the range [-127 127].[get]
1212 *
1213 * @param ctx Read / write interface definitions.(ptr)
1214 * @param buff Buffer that stores data read
1215 * @retval Interface status (MANDATORY: return 0 -> no Error).
1216 *
1217 */
lsm6dsr_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1218 int32_t lsm6dsr_xl_usr_offset_y_get(const stmdev_ctx_t *ctx,
1219 uint8_t *buff)
1220 {
1221 int32_t ret;
1222
1223 ret = lsm6dsr_read_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
1224
1225 return ret;
1226 }
1227
1228 /**
1229 * @brief Accelerometer Z-axis user offset correction expressed in two's
1230 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1231 * The value must be in the range [-127 127].[set]
1232 *
1233 * @param ctx Read / write interface definitions.(ptr)
1234 * @param buff Buffer that contains data to write
1235 * @retval Interface status (MANDATORY: return 0 -> no Error).
1236 *
1237 */
lsm6dsr_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1238 int32_t lsm6dsr_xl_usr_offset_z_set(const stmdev_ctx_t *ctx,
1239 uint8_t *buff)
1240 {
1241 int32_t ret;
1242
1243 ret = lsm6dsr_write_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
1244
1245 return ret;
1246 }
1247
1248 /**
1249 * @brief Accelerometer X-axis user offset correction expressed in two's
1250 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1251 * The value must be in the range [-127 127].[get]
1252 *
1253 * @param ctx Read / write interface definitions.(ptr)
1254 * @param buff Buffer that stores data read
1255 * @retval Interface status (MANDATORY: return 0 -> no Error).
1256 *
1257 */
lsm6dsr_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1258 int32_t lsm6dsr_xl_usr_offset_z_get(const stmdev_ctx_t *ctx,
1259 uint8_t *buff)
1260 {
1261 int32_t ret;
1262
1263 ret = lsm6dsr_read_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
1264
1265 return ret;
1266 }
1267
1268 /**
1269 * @brief Enables user offset on out.[set]
1270 *
1271 * @param ctx Read / write interface definitions.(ptr)
1272 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1273 * @retval Interface status (MANDATORY: return 0 -> no Error).
1274 *
1275 */
lsm6dsr_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1276 int32_t lsm6dsr_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1277 {
1278 lsm6dsr_ctrl7_g_t ctrl7_g;
1279 int32_t ret;
1280
1281 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
1282 (uint8_t *)&ctrl7_g, 1);
1283
1284 if (ret == 0)
1285 {
1286 ctrl7_g.usr_off_on_out = (uint8_t)val;
1287 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G,
1288 (uint8_t *)&ctrl7_g, 1);
1289 }
1290
1291 return ret;
1292 }
1293
1294 /**
1295 * @brief Get user offset on out flag.[get]
1296 *
1297 * @param ctx Read / write interface definitions.(ptr)
1298 * @param val Get values of usr_off_on_out in reg CTRL7_G
1299 * @retval Interface status (MANDATORY: return 0 -> no Error).
1300 *
1301 */
lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1302 int32_t lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1303 {
1304 lsm6dsr_ctrl7_g_t ctrl7_g;
1305 int32_t ret;
1306
1307 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
1308 (uint8_t *)&ctrl7_g, 1);
1309 *val = ctrl7_g.usr_off_on_out;
1310
1311 return ret;
1312 }
1313
1314 /**
1315 * @}
1316 *
1317 */
1318
1319 /**
1320 * @defgroup LSM6DSR_Timestamp
1321 * @brief This section groups all the functions that manage the
1322 * timestamp generation.
1323 * @{
1324 *
1325 */
1326
1327 /**
1328 * @brief Reset timestamp counter.[set]
1329 *
1330 * @param ctx Read / write interface definitions.(ptr)
1331 * @retval Interface status (MANDATORY: return 0 -> no Error).
1332 *
1333 */
lsm6dsr_timestamp_rst(const stmdev_ctx_t * ctx)1334 int32_t lsm6dsr_timestamp_rst(const stmdev_ctx_t *ctx)
1335 {
1336 uint8_t rst_val = 0xAA;
1337 return lsm6dsr_write_reg(ctx, LSM6DSR_TIMESTAMP2, &rst_val, 1);
1338 }
1339
1340 /**
1341 * @brief Enables timestamp counter.[set]
1342 *
1343 * @param ctx Read / write interface definitions.(ptr)
1344 * @param val Change the values of timestamp_en in reg CTRL10_C
1345 * @retval Interface status (MANDATORY: return 0 -> no Error).
1346 *
1347 */
lsm6dsr_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1348 int32_t lsm6dsr_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1349 {
1350 lsm6dsr_ctrl10_c_t ctrl10_c;
1351 int32_t ret;
1352
1353 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C,
1354 (uint8_t *)&ctrl10_c, 1);
1355
1356 if (ret == 0)
1357 {
1358 ctrl10_c.timestamp_en = (uint8_t)val;
1359 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL10_C,
1360 (uint8_t *)&ctrl10_c, 1);
1361 }
1362
1363 return ret;
1364 }
1365
1366 /**
1367 * @brief Enables timestamp counter.[get]
1368 *
1369 * @param ctx Read / write interface definitions.(ptr)
1370 * @param val Change the values of timestamp_en in reg CTRL10_C
1371 * @retval Interface status (MANDATORY: return 0 -> no Error).
1372 *
1373 */
lsm6dsr_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1374 int32_t lsm6dsr_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1375 {
1376 lsm6dsr_ctrl10_c_t ctrl10_c;
1377 int32_t ret;
1378
1379 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C,
1380 (uint8_t *)&ctrl10_c, 1);
1381 *val = ctrl10_c.timestamp_en;
1382
1383 return ret;
1384 }
1385
1386 /**
1387 * @brief Timestamp first data output register (r).
1388 * The value is expressed as a 32-bit word and the bit resolution
1389 * is 25 us.[get]
1390 *
1391 * @param ctx Read / write interface definitions.(ptr)
1392 * @param buff Buffer that stores data read
1393 * @retval Interface status (MANDATORY: return 0 -> no Error).
1394 *
1395 */
lsm6dsr_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1396 int32_t lsm6dsr_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1397 {
1398 uint8_t buff[4];
1399 int32_t ret;
1400
1401 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TIMESTAMP0, buff, 4);
1402 *val = buff[3];
1403 *val = (*val * 256U) + buff[2];
1404 *val = (*val * 256U) + buff[1];
1405 *val = (*val * 256U) + buff[0];
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @}
1412 *
1413 */
1414
1415 /**
1416 * @defgroup LSM6DSR_Data output
1417 * @brief This section groups all the data output functions.
1418 * @{
1419 *
1420 */
1421
1422 /**
1423 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1424 *
1425 * @param ctx Read / write interface definitions.(ptr)
1426 * @param val Change the values of rounding in reg CTRL5_C
1427 * @retval Interface status (MANDATORY: return 0 -> no Error).
1428 *
1429 */
lsm6dsr_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_rounding_t val)1430 int32_t lsm6dsr_rounding_mode_set(const stmdev_ctx_t *ctx,
1431 lsm6dsr_rounding_t val)
1432 {
1433 lsm6dsr_ctrl5_c_t ctrl5_c;
1434 int32_t ret;
1435
1436 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
1437 (uint8_t *)&ctrl5_c, 1);
1438
1439 if (ret == 0)
1440 {
1441 ctrl5_c.rounding = (uint8_t)val;
1442 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C,
1443 (uint8_t *)&ctrl5_c, 1);
1444 }
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * @brief Gyroscope UI chain full-scale selection.[get]
1451 *
1452 * @param ctx Read / write interface definitions.(ptr)
1453 * @param val Get the values of rounding in reg CTRL5_C
1454 * @retval Interface status (MANDATORY: return 0 -> no Error).
1455 *
1456 */
lsm6dsr_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_rounding_t * val)1457 int32_t lsm6dsr_rounding_mode_get(const stmdev_ctx_t *ctx,
1458 lsm6dsr_rounding_t *val)
1459 {
1460 lsm6dsr_ctrl5_c_t ctrl5_c;
1461 int32_t ret;
1462
1463 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
1464 (uint8_t *)&ctrl5_c, 1);
1465
1466 switch (ctrl5_c.rounding)
1467 {
1468 case LSM6DSR_NO_ROUND:
1469 *val = LSM6DSR_NO_ROUND;
1470 break;
1471
1472 case LSM6DSR_ROUND_XL:
1473 *val = LSM6DSR_ROUND_XL;
1474 break;
1475
1476 case LSM6DSR_ROUND_GY:
1477 *val = LSM6DSR_ROUND_GY;
1478 break;
1479
1480 case LSM6DSR_ROUND_GY_XL:
1481 *val = LSM6DSR_ROUND_GY_XL;
1482 break;
1483
1484 default:
1485 *val = LSM6DSR_NO_ROUND;
1486 break;
1487 }
1488
1489 return ret;
1490 }
1491
1492 /**
1493 * @brief Temperature data output register (r).
1494 * L and H registers together express a 16-bit word in two's
1495 * complement.[get]
1496 *
1497 * @param ctx Read / write interface definitions.(ptr)
1498 * @param buff Buffer that stores data read
1499 * @retval Interface status (MANDATORY: return 0 -> no Error).
1500 *
1501 */
lsm6dsr_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1502 int32_t lsm6dsr_temperature_raw_get(const stmdev_ctx_t *ctx,
1503 int16_t *val)
1504 {
1505 uint8_t buff[2];
1506 int32_t ret;
1507
1508 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUT_TEMP_L, buff, 2);
1509 *val = (int16_t)buff[1];
1510 *val = (*val * 256) + (int16_t)buff[0];
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief Angular rate sensor. The value is expressed as a 16-bit
1517 * word in two's complement.[get]
1518 *
1519 * @param ctx Read / write interface definitions.(ptr)
1520 * @param buff Buffer that stores data read
1521 * @retval Interface status (MANDATORY: return 0 -> no Error).
1522 *
1523 */
lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1524 int32_t lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1525 int16_t *val)
1526 {
1527 uint8_t buff[6];
1528 int32_t ret;
1529
1530 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_G, buff, 6);
1531 val[0] = (int16_t)buff[1];
1532 val[0] = (val[0] * 256) + (int16_t)buff[0];
1533 val[1] = (int16_t)buff[3];
1534 val[1] = (val[1] * 256) + (int16_t)buff[2];
1535 val[2] = (int16_t)buff[5];
1536 val[2] = (val[2] * 256) + (int16_t)buff[4];
1537
1538 return ret;
1539 }
1540
1541 /**
1542 * @brief Linear acceleration output register. The value is expressed as a
1543 * 16-bit word in two's complement.[get]
1544 *
1545 * @param ctx Read / write interface definitions.(ptr)
1546 * @param buff Buffer that stores data read
1547 * @retval Interface status (MANDATORY: return 0 -> no Error).
1548 *
1549 */
lsm6dsr_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1550 int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx,
1551 int16_t *val)
1552 {
1553 uint8_t buff[6];
1554 int32_t ret;
1555
1556 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_A, buff, 6);
1557 val[0] = (int16_t)buff[1];
1558 val[0] = (val[0] * 256) + (int16_t)buff[0];
1559 val[1] = (int16_t)buff[3];
1560 val[1] = (val[1] * 256) + (int16_t)buff[2];
1561 val[2] = (int16_t)buff[5];
1562 val[2] = (val[2] * 256) + (int16_t)buff[4];
1563
1564 return ret;
1565 }
1566
1567 /**
1568 * @brief FIFO data output.[get]
1569 *
1570 * @param ctx Read / write interface definitions.(ptr)
1571 * @param buff Buffer that stores data read
1572 * @retval Interface status (MANDATORY: return 0 -> no Error).
1573 *
1574 */
lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1575 int32_t lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1576 {
1577 int32_t ret;
1578
1579 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_X_L, buff, 6);
1580
1581 return ret;
1582 }
1583
1584 /**
1585 * @brief Step counter output register.[get]
1586 *
1587 * @param ctx Read / write interface definitions.(ptr)
1588 * @param buff Buffer that stores data read
1589 * @retval Interface status (MANDATORY: return 0 -> no Error).
1590 *
1591 */
lsm6dsr_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1592 int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx,
1593 uint16_t *val)
1594 {
1595 uint8_t buff[2];
1596 int32_t ret;
1597
1598 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1599
1600 if (ret == 0)
1601 {
1602 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STEP_COUNTER_L, buff, 2);
1603 *val = buff[1];
1604 *val = (*val * 256U) + buff[0];
1605 }
1606
1607 if (ret == 0)
1608 {
1609 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1610 }
1611
1612 return ret;
1613 }
1614
1615 /**
1616 * @brief Reset step counter register.[get]
1617 *
1618 * @param ctx Read / write interface definitions.(ptr)
1619 * @retval Interface status (MANDATORY: return 0 -> no Error).
1620 *
1621 */
lsm6dsr_steps_reset(const stmdev_ctx_t * ctx)1622 int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx)
1623 {
1624 lsm6dsr_emb_func_src_t emb_func_src;
1625 int32_t ret;
1626
1627 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1628
1629 if (ret == 0)
1630 {
1631 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
1632 (uint8_t *)&emb_func_src, 1);
1633 }
1634
1635 if (ret == 0)
1636 {
1637 emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
1638 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
1639 (uint8_t *)&emb_func_src, 1);
1640 }
1641
1642 if (ret == 0)
1643 {
1644 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1645 }
1646
1647 return ret;
1648 }
1649
1650 /**
1651 * @}
1652 *
1653 */
1654
1655 /**
1656 * @defgroup LSM6DSR_common
1657 * @brief This section groups common useful functions.
1658 * @{
1659 *
1660 */
1661
1662 /**
1663 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1664 * with respect to the typical.[set]
1665 * Step: 0.15%. 8-bit format, 2's complement.
1666 *
1667 * @param ctx Read / write interface definitions.(ptr)
1668 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1669 * @retval Interface status (MANDATORY: return 0 -> no Error).
1670 *
1671 */
lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1672 int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1673 {
1674 lsm6dsr_internal_freq_fine_t internal_freq_fine;
1675 int32_t ret;
1676
1677 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1678 (uint8_t *)&internal_freq_fine, 1);
1679
1680 if (ret == 0)
1681 {
1682 internal_freq_fine.freq_fine = (uint8_t)val;
1683 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1684 (uint8_t *)&internal_freq_fine, 1);
1685 }
1686
1687 return ret;
1688 }
1689
1690 /**
1691 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1692 * with respect to the typical.[get]
1693 * Step: 0.15%. 8-bit format, 2's complement.
1694 *
1695 * @param ctx Read / write interface definitions.(ptr)
1696 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1697 * @retval Interface status (MANDATORY: return 0 -> no Error).
1698 *
1699 */
lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1700 int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1701 {
1702 lsm6dsr_internal_freq_fine_t internal_freq_fine;
1703 int32_t ret;
1704
1705 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1706 (uint8_t *)&internal_freq_fine, 1);
1707 *val = internal_freq_fine.freq_fine;
1708
1709 return ret;
1710 }
1711
1712 /**
1713 * @brief Enable access to the embedded functions/sensor hub configuration
1714 * registers.[set]
1715 *
1716 * @param ctx Read / write interface definitions.(ptr)
1717 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1718 * @retval Interface status (MANDATORY: return 0 -> no Error).
1719 *
1720 */
lsm6dsr_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsr_reg_access_t val)1721 int32_t lsm6dsr_mem_bank_set(const stmdev_ctx_t *ctx,
1722 lsm6dsr_reg_access_t val)
1723 {
1724 lsm6dsr_func_cfg_access_t func_cfg_access;
1725 int32_t ret;
1726
1727 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1728 (uint8_t *)&func_cfg_access, 1);
1729
1730 if (ret == 0)
1731 {
1732 func_cfg_access.reg_access = (uint8_t)val;
1733 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1734 (uint8_t *)&func_cfg_access, 1);
1735 }
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief Enable access to the embedded functions/sensor hub configuration
1742 * registers.[get]
1743 *
1744 * @param ctx Read / write interface definitions.(ptr)
1745 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1746 * @retval Interface status (MANDATORY: return 0 -> no Error).
1747 *
1748 */
lsm6dsr_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsr_reg_access_t * val)1749 int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx,
1750 lsm6dsr_reg_access_t *val)
1751 {
1752 lsm6dsr_func_cfg_access_t func_cfg_access;
1753 int32_t ret;
1754
1755 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1756 (uint8_t *)&func_cfg_access, 1);
1757
1758 switch (func_cfg_access.reg_access)
1759 {
1760 case LSM6DSR_USER_BANK:
1761 *val = LSM6DSR_USER_BANK;
1762 break;
1763
1764 case LSM6DSR_SENSOR_HUB_BANK:
1765 *val = LSM6DSR_SENSOR_HUB_BANK;
1766 break;
1767
1768 case LSM6DSR_EMBEDDED_FUNC_BANK:
1769 *val = LSM6DSR_EMBEDDED_FUNC_BANK;
1770 break;
1771
1772 default:
1773 *val = LSM6DSR_USER_BANK;
1774 break;
1775 }
1776
1777 return ret;
1778 }
1779
1780 /**
1781 * @brief Write a line(byte) in a page.[set]
1782 *
1783 * @param ctx Read / write interface definitions.(ptr)
1784 * @param add Page line address
1785 * @param val Value to write
1786 * @retval Interface status (MANDATORY: return 0 -> no Error).
1787 *
1788 */
lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1789 int32_t lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
1790 uint8_t *val)
1791 {
1792 lsm6dsr_page_rw_t page_rw;
1793 lsm6dsr_page_sel_t page_sel;
1794 lsm6dsr_page_address_t page_address;
1795 int32_t ret;
1796
1797 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1798
1799 if (ret == 0)
1800 {
1801 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
1802 (uint8_t *)&page_rw, 1);
1803 }
1804
1805 if (ret == 0)
1806 {
1807 page_rw.page_rw = 0x02U; /* page_write enable */
1808 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
1809 (uint8_t *)&page_rw, 1);
1810 }
1811
1812 if (ret == 0)
1813 {
1814 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
1815 (uint8_t *)&page_sel, 1);
1816 }
1817
1818 if (ret == 0)
1819 {
1820 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1821 page_sel.not_used_01 = 1;
1822 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1823 (uint8_t *)&page_sel, 1);
1824 }
1825
1826 if (ret == 0)
1827 {
1828 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1829 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
1830 (uint8_t *)&page_address, 1);
1831 }
1832
1833 if (ret == 0)
1834 {
1835 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, val, 1);
1836 }
1837
1838 if (ret == 0)
1839 {
1840 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
1841 (uint8_t *)&page_rw, 1);
1842 }
1843
1844 if (ret == 0)
1845 {
1846 page_rw.page_rw = 0x00; /* page_write disable */
1847 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
1848 (uint8_t *)&page_rw, 1);
1849 }
1850
1851 if (ret == 0)
1852 {
1853 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1854 }
1855
1856 return ret;
1857 }
1858
1859 /**
1860 * @brief Write buffer in a page.[set]
1861 *
1862 * @param ctx Read / write interface definitions.(ptr)
1863 * @param buf Page line address.(ptr)
1864 * @param val Value to write.
1865 * @param len buffer length.
1866 * @retval Interface status (MANDATORY: return 0 -> no Error).
1867 *
1868 */
lsm6dsr_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1869 int32_t lsm6dsr_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
1870 uint8_t *buf, uint8_t len)
1871 {
1872 lsm6dsr_page_rw_t page_rw;
1873 lsm6dsr_page_sel_t page_sel;
1874 lsm6dsr_page_address_t page_address;
1875 uint8_t msb;
1876 uint8_t lsb;
1877 int32_t ret;
1878 uint8_t i ;
1879
1880 msb = (uint8_t)((add / 256U) & 0x0FU);
1881 lsb = (uint8_t)(add - (msb * 256U));
1882 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1883
1884 if (ret == 0)
1885 {
1886 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
1887 (uint8_t *)&page_rw, 1);
1888 }
1889
1890 if (ret == 0)
1891 {
1892 page_rw.page_rw = 0x02U; /* page_write enable*/
1893 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
1894 (uint8_t *)&page_rw, 1);
1895 }
1896
1897 if (ret == 0)
1898 {
1899 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
1900 (uint8_t *)&page_sel, 1);
1901 }
1902
1903 if (ret == 0)
1904 {
1905 page_sel.page_sel = msb;
1906 page_sel.not_used_01 = 1;
1907 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1908 (uint8_t *)&page_sel, 1);
1909 }
1910
1911 if (ret == 0)
1912 {
1913 page_address.page_addr = lsb;
1914 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
1915 (uint8_t *)&page_address, 1);
1916 }
1917
1918 for (i = 0; i < len; i++)
1919 {
1920 if (ret == 0)
1921 {
1922 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, &buf[i], 1);
1923
1924 if (ret == 0)
1925 {
1926 /* Check if page wrap */
1927 if (lsb == 0x00U)
1928 {
1929 msb++;
1930 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
1931 (uint8_t *)&page_sel, 1);
1932 }
1933
1934 lsb++;
1935 }
1936
1937 if (ret == 0)
1938 {
1939 page_sel.page_sel = msb;
1940 page_sel.not_used_01 = 1;
1941 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1942 (uint8_t *)&page_sel, 1);
1943 }
1944 }
1945 }
1946
1947 if (ret == 0)
1948 {
1949 page_sel.page_sel = 0;
1950 page_sel.not_used_01 = 1;
1951 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1952 (uint8_t *)&page_sel, 1);
1953 }
1954
1955 if (ret == 0)
1956 {
1957 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
1958 (uint8_t *)&page_rw, 1);
1959 }
1960
1961 if (ret == 0)
1962 {
1963 page_rw.page_rw = 0x00U; /* page_write disable */
1964 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
1965 (uint8_t *)&page_rw, 1);
1966 }
1967
1968 if (ret == 0)
1969 {
1970 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1971 }
1972
1973 return ret;
1974 }
1975
1976 /**
1977 * @brief Read a line(byte) in a page.[get]
1978 *
1979 * @param ctx Read / write interface definitions.(ptr)
1980 * @param add Page line address.
1981 * @param val Read value.(ptr)
1982 * @retval Interface status (MANDATORY: return 0 -> no Error).
1983 *
1984 */
lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1985 int32_t lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
1986 uint8_t *val)
1987 {
1988 lsm6dsr_page_rw_t page_rw;
1989 lsm6dsr_page_sel_t page_sel;
1990 lsm6dsr_page_address_t page_address;
1991 int32_t ret;
1992
1993 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1994
1995 if (ret == 0)
1996 {
1997 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
1998 (uint8_t *)&page_rw, 1);
1999 }
2000
2001 if (ret == 0)
2002 {
2003 page_rw.page_rw = 0x01U; /* page_read enable*/
2004 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
2005 (uint8_t *)&page_rw, 1);
2006 }
2007
2008 if (ret == 0)
2009 {
2010 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
2011 (uint8_t *)&page_sel, 1);
2012 }
2013
2014 if (ret == 0)
2015 {
2016 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2017 page_sel.not_used_01 = 1;
2018 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
2019 (uint8_t *)&page_sel, 1);
2020 }
2021
2022 if (ret == 0)
2023 {
2024 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2025 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
2026 (uint8_t *)&page_address, 1);
2027 }
2028
2029 if (ret == 0)
2030 {
2031 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_VALUE, val, 2);
2032 }
2033
2034 if (ret == 0)
2035 {
2036 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
2037 (uint8_t *)&page_rw, 1);
2038 }
2039
2040 if (ret == 0)
2041 {
2042 page_rw.page_rw = 0x00U; /* page_read disable */
2043 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
2044 (uint8_t *)&page_rw, 1);
2045 }
2046
2047 if (ret == 0)
2048 {
2049 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
2050 }
2051
2052 return ret;
2053 }
2054
2055 /**
2056 * @brief Data-ready pulsed / letched mode.[set]
2057 *
2058 * @param ctx Read / write interface definitions.(ptr)
2059 * @param val Change the values of dataready_pulsed in
2060 * reg COUNTER_BDR_REG1
2061 * @retval Interface status (MANDATORY: return 0 -> no Error).
2062 *
2063 */
lsm6dsr_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_dataready_pulsed_t val)2064 int32_t lsm6dsr_data_ready_mode_set(const stmdev_ctx_t *ctx,
2065 lsm6dsr_dataready_pulsed_t val)
2066 {
2067 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
2068 int32_t ret;
2069
2070 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2071 (uint8_t *)&counter_bdr_reg1, 1);
2072
2073 if (ret == 0)
2074 {
2075 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2076 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2077 (uint8_t *)&counter_bdr_reg1, 1);
2078 }
2079
2080 return ret;
2081 }
2082
2083 /**
2084 * @brief Data-ready pulsed / letched mode.[get]
2085 *
2086 * @param ctx Read / write interface definitions.(ptr)
2087 * @param val Get the values of dataready_pulsed in
2088 * reg COUNTER_BDR_REG1
2089 * @retval Interface status (MANDATORY: return 0 -> no Error).
2090 *
2091 */
lsm6dsr_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_dataready_pulsed_t * val)2092 int32_t lsm6dsr_data_ready_mode_get(const stmdev_ctx_t *ctx,
2093 lsm6dsr_dataready_pulsed_t *val)
2094 {
2095 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
2096 int32_t ret;
2097
2098 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2099 (uint8_t *)&counter_bdr_reg1, 1);
2100
2101 switch (counter_bdr_reg1.dataready_pulsed)
2102 {
2103 case LSM6DSR_DRDY_LATCHED:
2104 *val = LSM6DSR_DRDY_LATCHED;
2105 break;
2106
2107 case LSM6DSR_DRDY_PULSED:
2108 *val = LSM6DSR_DRDY_PULSED;
2109 break;
2110
2111 default:
2112 *val = LSM6DSR_DRDY_LATCHED;
2113 break;
2114 }
2115
2116 return ret;
2117 }
2118
2119 /**
2120 * @brief Device Who am I.[get]
2121 *
2122 * @param ctx Read / write interface definitions.(ptr)
2123 * @param buff Buffer that stores data read
2124 * @retval Interface status (MANDATORY: return 0 -> no Error).
2125 *
2126 */
lsm6dsr_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2127 int32_t lsm6dsr_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2128 {
2129 int32_t ret;
2130
2131 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WHO_AM_I, buff, 1);
2132
2133 return ret;
2134 }
2135
2136 /**
2137 * @brief Software reset. Restore the default values in user registers.[set]
2138 *
2139 * @param ctx Read / write interface definitions.(ptr)
2140 * @param val Change the values of sw_reset in reg CTRL3_C
2141 * @retval Interface status (MANDATORY: return 0 -> no Error).
2142 *
2143 */
lsm6dsr_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2144 int32_t lsm6dsr_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2145 {
2146 lsm6dsr_ctrl3_c_t ctrl3_c;
2147 int32_t ret;
2148
2149 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2150 (uint8_t *)&ctrl3_c, 1);
2151
2152 if (ret == 0)
2153 {
2154 ctrl3_c.sw_reset = (uint8_t)val;
2155 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
2156 (uint8_t *)&ctrl3_c, 1);
2157 }
2158
2159 return ret;
2160 }
2161
2162 /**
2163 * @brief Software reset. Restore the default values in user registers.[get]
2164 *
2165 * @param ctx Read / write interface definitions.(ptr)
2166 * @param val Change the values of sw_reset in reg CTRL3_C
2167 * @retval Interface status (MANDATORY: return 0 -> no Error).
2168 *
2169 */
lsm6dsr_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2170 int32_t lsm6dsr_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2171 {
2172 lsm6dsr_ctrl3_c_t ctrl3_c;
2173 int32_t ret;
2174
2175 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2176 (uint8_t *)&ctrl3_c, 1);
2177 *val = ctrl3_c.sw_reset;
2178
2179 return ret;
2180 }
2181
2182 /**
2183 * @brief Register address automatically incremented during a multiple byte
2184 * access with a serial interface.[set]
2185 *
2186 * @param ctx Read / write interface definitions.(ptr)
2187 * @param val Change the values of if_inc in reg CTRL3_C
2188 * @retval Interface status (MANDATORY: return 0 -> no Error).
2189 *
2190 */
lsm6dsr_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2191 int32_t lsm6dsr_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2192 {
2193 lsm6dsr_ctrl3_c_t ctrl3_c;
2194 int32_t ret;
2195
2196 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2197 (uint8_t *)&ctrl3_c, 1);
2198
2199 if (ret == 0)
2200 {
2201 ctrl3_c.if_inc = (uint8_t)val;
2202 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
2203 (uint8_t *)&ctrl3_c, 1);
2204 }
2205
2206 return ret;
2207 }
2208
2209 /**
2210 * @brief Register address automatically incremented during a multiple byte
2211 * access with a serial interface.[get]
2212 *
2213 * @param ctx Read / write interface definitions.(ptr)
2214 * @param val Change the values of if_inc in reg CTRL3_C
2215 * @retval Interface status (MANDATORY: return 0 -> no Error).
2216 *
2217 */
lsm6dsr_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2218 int32_t lsm6dsr_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2219 {
2220 lsm6dsr_ctrl3_c_t ctrl3_c;
2221 int32_t ret;
2222
2223 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2224 (uint8_t *)&ctrl3_c, 1);
2225 *val = ctrl3_c.if_inc;
2226
2227 return ret;
2228 }
2229
2230 /**
2231 * @brief Reboot memory content. Reload the calibration parameters.[set]
2232 *
2233 * @param ctx Read / write interface definitions.(ptr)
2234 * @param val Change the values of boot in reg CTRL3_C
2235 * @retval Interface status (MANDATORY: return 0 -> no Error).
2236 *
2237 */
lsm6dsr_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2238 int32_t lsm6dsr_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2239 {
2240 lsm6dsr_ctrl3_c_t ctrl3_c;
2241 int32_t ret;
2242
2243 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2244 (uint8_t *)&ctrl3_c, 1);
2245
2246 if (ret == 0)
2247 {
2248 ctrl3_c.boot = (uint8_t)val;
2249 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
2250 (uint8_t *)&ctrl3_c, 1);
2251 }
2252
2253 return ret;
2254 }
2255
2256 /**
2257 * @brief Reboot memory content. Reload the calibration parameters.[get]
2258 *
2259 * @param ctx Read / write interface definitions.(ptr)
2260 * @param val Change the values of boot in reg CTRL3_C
2261 * @retval Interface status (MANDATORY: return 0 -> no Error).
2262 *
2263 */
lsm6dsr_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2264 int32_t lsm6dsr_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2265 {
2266 lsm6dsr_ctrl3_c_t ctrl3_c;
2267 int32_t ret;
2268
2269 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
2270 (uint8_t *)&ctrl3_c, 1);
2271 *val = ctrl3_c.boot;
2272
2273 return ret;
2274 }
2275
2276
2277
2278 /**
2279 * @brief Linear acceleration sensor self-test enable.[set]
2280 *
2281 * @param ctx Read / write interface definitions.(ptr)
2282 * @param val Change the values of st_xl in reg CTRL5_C
2283 * @retval Interface status (MANDATORY: return 0 -> no Error).
2284 *
2285 */
lsm6dsr_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsr_st_xl_t val)2286 int32_t lsm6dsr_xl_self_test_set(const stmdev_ctx_t *ctx,
2287 lsm6dsr_st_xl_t val)
2288 {
2289 lsm6dsr_ctrl5_c_t ctrl5_c;
2290 int32_t ret;
2291
2292 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
2293 (uint8_t *)&ctrl5_c, 1);
2294
2295 if (ret == 0)
2296 {
2297 ctrl5_c.st_xl = (uint8_t)val;
2298 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C,
2299 (uint8_t *)&ctrl5_c, 1);
2300 }
2301
2302 return ret;
2303 }
2304
2305 /**
2306 * @brief Linear acceleration sensor self-test enable.[get]
2307 *
2308 * @param ctx Read / write interface definitions.(ptr)
2309 * @param val Get the values of st_xl in reg CTRL5_C
2310 * @retval Interface status (MANDATORY: return 0 -> no Error).
2311 *
2312 */
lsm6dsr_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsr_st_xl_t * val)2313 int32_t lsm6dsr_xl_self_test_get(const stmdev_ctx_t *ctx,
2314 lsm6dsr_st_xl_t *val)
2315 {
2316 lsm6dsr_ctrl5_c_t ctrl5_c;
2317 int32_t ret;
2318
2319 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
2320 (uint8_t *)&ctrl5_c, 1);
2321
2322 switch (ctrl5_c.st_xl)
2323 {
2324 case LSM6DSR_XL_ST_DISABLE:
2325 *val = LSM6DSR_XL_ST_DISABLE;
2326 break;
2327
2328 case LSM6DSR_XL_ST_POSITIVE:
2329 *val = LSM6DSR_XL_ST_POSITIVE;
2330 break;
2331
2332 case LSM6DSR_XL_ST_NEGATIVE:
2333 *val = LSM6DSR_XL_ST_NEGATIVE;
2334 break;
2335
2336 default:
2337 *val = LSM6DSR_XL_ST_DISABLE;
2338 break;
2339 }
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * @brief Angular rate sensor self-test enable.[set]
2346 *
2347 * @param ctx Read / write interface definitions.(ptr)
2348 * @param val Change the values of st_g in reg CTRL5_C
2349 * @retval Interface status (MANDATORY: return 0 -> no Error).
2350 *
2351 */
lsm6dsr_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsr_st_g_t val)2352 int32_t lsm6dsr_gy_self_test_set(const stmdev_ctx_t *ctx,
2353 lsm6dsr_st_g_t val)
2354 {
2355 lsm6dsr_ctrl5_c_t ctrl5_c;
2356 int32_t ret;
2357
2358 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
2359 (uint8_t *)&ctrl5_c, 1);
2360
2361 if (ret == 0)
2362 {
2363 ctrl5_c.st_g = (uint8_t)val;
2364 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C,
2365 (uint8_t *)&ctrl5_c, 1);
2366 }
2367
2368 return ret;
2369 }
2370
2371 /**
2372 * @brief Angular rate sensor self-test enable.[get]
2373 *
2374 * @param ctx Read / write interface definitions.(ptr)
2375 * @param val Get the values of st_g in reg CTRL5_C
2376 * @retval Interface status (MANDATORY: return 0 -> no Error).
2377 *
2378 */
lsm6dsr_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsr_st_g_t * val)2379 int32_t lsm6dsr_gy_self_test_get(const stmdev_ctx_t *ctx,
2380 lsm6dsr_st_g_t *val)
2381 {
2382 lsm6dsr_ctrl5_c_t ctrl5_c;
2383 int32_t ret;
2384
2385 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C,
2386 (uint8_t *)&ctrl5_c, 1);
2387
2388 switch (ctrl5_c.st_g)
2389 {
2390 case LSM6DSR_GY_ST_DISABLE:
2391 *val = LSM6DSR_GY_ST_DISABLE;
2392 break;
2393
2394 case LSM6DSR_GY_ST_POSITIVE:
2395 *val = LSM6DSR_GY_ST_POSITIVE;
2396 break;
2397
2398 case LSM6DSR_GY_ST_NEGATIVE:
2399 *val = LSM6DSR_GY_ST_NEGATIVE;
2400 break;
2401
2402 default:
2403 *val = LSM6DSR_GY_ST_DISABLE;
2404 break;
2405 }
2406
2407 return ret;
2408 }
2409
2410 /**
2411 * @}
2412 *
2413 */
2414
2415 /**
2416 * @defgroup LSM6DSR_filters
2417 * @brief This section group all the functions concerning the
2418 * filters configuration
2419 * @{
2420 *
2421 */
2422
2423 /**
2424 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2425 *
2426 * @param ctx Read / write interface definitions.(ptr)
2427 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2428 * @retval Interface status (MANDATORY: return 0 -> no Error).
2429 *
2430 */
lsm6dsr_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2431 int32_t lsm6dsr_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2432 {
2433 lsm6dsr_ctrl1_xl_t ctrl1_xl;
2434 int32_t ret;
2435
2436 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
2437 (uint8_t *)&ctrl1_xl, 1);
2438
2439 if (ret == 0)
2440 {
2441 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2442 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
2443 (uint8_t *)&ctrl1_xl, 1);
2444 }
2445
2446 return ret;
2447 }
2448
2449 /**
2450 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2451 *
2452 * @param ctx Read / write interface definitions.(ptr)
2453 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2454 * @retval Interface status (MANDATORY: return 0 -> no Error).
2455 *
2456 */
lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2457 int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2458 {
2459 lsm6dsr_ctrl1_xl_t ctrl1_xl;
2460 int32_t ret;
2461
2462 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL,
2463 (uint8_t *)&ctrl1_xl, 1);
2464 *val = ctrl1_xl.lpf2_xl_en;
2465
2466 return ret;
2467 }
2468
2469 /**
2470 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2471 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2472 *
2473 * @param ctx Read / write interface definitions.(ptr)
2474 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2475 * @retval Interface status (MANDATORY: return 0 -> no Error).
2476 *
2477 */
lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2478 int32_t lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2479 {
2480 lsm6dsr_ctrl4_c_t ctrl4_c;
2481 int32_t ret;
2482
2483 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
2484 (uint8_t *)&ctrl4_c, 1);
2485
2486 if (ret == 0)
2487 {
2488 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2489 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C,
2490 (uint8_t *)&ctrl4_c, 1);
2491 }
2492
2493 return ret;
2494 }
2495
2496 /**
2497 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2498 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2499 *
2500 * @param ctx Read / write interface definitions.(ptr)
2501 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2502 * @retval Interface status (MANDATORY: return 0 -> no Error).
2503 *
2504 */
lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2505 int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2506 {
2507 lsm6dsr_ctrl4_c_t ctrl4_c;
2508 int32_t ret;
2509
2510 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
2511 (uint8_t *)&ctrl4_c, 1);
2512 *val = ctrl4_c.lpf1_sel_g;
2513
2514 return ret;
2515 }
2516
2517 /**
2518 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2519 * (XL and Gyro independently masked).[set]
2520 *
2521 * @param ctx Read / write interface definitions.(ptr)
2522 * @param val Change the values of drdy_mask in reg CTRL4_C
2523 * @retval Interface status (MANDATORY: return 0 -> no Error).
2524 *
2525 */
lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2526 int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2527 uint8_t val)
2528 {
2529 lsm6dsr_ctrl4_c_t ctrl4_c;
2530 int32_t ret;
2531
2532 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
2533 (uint8_t *)&ctrl4_c, 1);
2534
2535 if (ret == 0)
2536 {
2537 ctrl4_c.drdy_mask = (uint8_t)val;
2538 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C,
2539 (uint8_t *)&ctrl4_c, 1);
2540 }
2541
2542 return ret;
2543 }
2544
2545 /**
2546 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2547 * (XL and Gyro independently masked).[get]
2548 *
2549 * @param ctx Read / write interface definitions.(ptr)
2550 * @param val Change the values of drdy_mask in reg CTRL4_C
2551 * @retval Interface status (MANDATORY: return 0 -> no Error).
2552 *
2553 */
lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2554 int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2555 uint8_t *val)
2556 {
2557 lsm6dsr_ctrl4_c_t ctrl4_c;
2558 int32_t ret;
2559
2560 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
2561 (uint8_t *)&ctrl4_c, 1);
2562 *val = ctrl4_c.drdy_mask;
2563
2564 return ret;
2565 }
2566
2567 /**
2568 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2569 *
2570 * @param ctx Read / write interface definitions.(ptr)
2571 * @param val Change the values of ftype in reg CTRL6_C
2572 * @retval Interface status (MANDATORY: return 0 -> no Error).
2573 *
2574 */
lsm6dsr_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsr_ftype_t val)2575 int32_t lsm6dsr_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2576 lsm6dsr_ftype_t val)
2577 {
2578 lsm6dsr_ctrl6_c_t ctrl6_c;
2579 int32_t ret;
2580
2581 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
2582 (uint8_t *)&ctrl6_c, 1);
2583
2584 if (ret == 0)
2585 {
2586 ctrl6_c.ftype = (uint8_t)val;
2587 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C,
2588 (uint8_t *)&ctrl6_c, 1);
2589 }
2590
2591 return ret;
2592 }
2593
2594 /**
2595 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2596 *
2597 * @param ctx Read / write interface definitions.(ptr)
2598 * @param val Get the values of ftype in reg CTRL6_C
2599 * @retval Interface status (MANDATORY: return 0 -> no Error).
2600 *
2601 */
lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsr_ftype_t * val)2602 int32_t lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2603 lsm6dsr_ftype_t *val)
2604 {
2605 lsm6dsr_ctrl6_c_t ctrl6_c;
2606 int32_t ret;
2607
2608 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
2609 (uint8_t *)&ctrl6_c, 1);
2610
2611 switch (ctrl6_c.ftype)
2612 {
2613 case LSM6DSR_ULTRA_LIGHT:
2614 *val = LSM6DSR_ULTRA_LIGHT;
2615 break;
2616
2617 case LSM6DSR_VERY_LIGHT:
2618 *val = LSM6DSR_VERY_LIGHT;
2619 break;
2620
2621 case LSM6DSR_LIGHT:
2622 *val = LSM6DSR_LIGHT;
2623 break;
2624
2625 case LSM6DSR_MEDIUM:
2626 *val = LSM6DSR_MEDIUM;
2627 break;
2628
2629 case LSM6DSR_STRONG:
2630 *val = LSM6DSR_STRONG;
2631 break;
2632
2633 case LSM6DSR_VERY_STRONG:
2634 *val = LSM6DSR_VERY_STRONG;
2635 break;
2636
2637 case LSM6DSR_AGGRESSIVE:
2638 *val = LSM6DSR_AGGRESSIVE;
2639 break;
2640
2641 case LSM6DSR_XTREME:
2642 *val = LSM6DSR_XTREME;
2643 break;
2644
2645 default:
2646 *val = LSM6DSR_ULTRA_LIGHT;
2647 break;
2648 }
2649
2650 return ret;
2651 }
2652
2653 /**
2654 * @brief Low pass filter 2 on 6D function selection.[set]
2655 *
2656 * @param ctx Read / write interface definitions.(ptr)
2657 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2658 * @retval Interface status (MANDATORY: return 0 -> no Error).
2659 *
2660 */
lsm6dsr_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2661 int32_t lsm6dsr_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2662 {
2663 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2664 int32_t ret;
2665
2666 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2667 (uint8_t *)&ctrl8_xl, 1);
2668
2669 if (ret == 0)
2670 {
2671 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2672 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2673 (uint8_t *)&ctrl8_xl, 1);
2674 }
2675
2676 return ret;
2677 }
2678
2679 /**
2680 * @brief Low pass filter 2 on 6D function selection.[get]
2681 *
2682 * @param ctx Read / write interface definitions.(ptr)
2683 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2684 * @retval Interface status (MANDATORY: return 0 -> no Error).
2685 *
2686 */
lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2687 int32_t lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2688 {
2689 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2690 int32_t ret;
2691
2692 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2693 (uint8_t *)&ctrl8_xl, 1);
2694 *val = ctrl8_xl.low_pass_on_6d;
2695
2696 return ret;
2697 }
2698
2699 /**
2700 * @brief Accelerometer slope filter / high-pass filter selection
2701 * on output.[set]
2702 *
2703 * @param ctx Read / write interface definitions.(ptr)
2704 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2705 * @retval Interface status (MANDATORY: return 0 -> no Error).
2706 *
2707 */
lsm6dsr_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dsr_hp_slope_xl_en_t val)2708 int32_t lsm6dsr_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2709 lsm6dsr_hp_slope_xl_en_t val)
2710 {
2711 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2712 int32_t ret;
2713
2714 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2715 (uint8_t *)&ctrl8_xl, 1);
2716
2717 if (ret == 0)
2718 {
2719 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2720 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2721 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2722 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2723 (uint8_t *)&ctrl8_xl, 1);
2724 }
2725
2726 return ret;
2727 }
2728
2729 /**
2730 * @brief Accelerometer slope filter / high-pass filter selection on
2731 * output.[get]
2732 *
2733 * @param ctx Read / write interface definitions.(ptr)
2734 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2735 * @retval Interface status (MANDATORY: return 0 -> no Error).
2736 *
2737 */
lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dsr_hp_slope_xl_en_t * val)2738 int32_t lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2739 lsm6dsr_hp_slope_xl_en_t *val)
2740 {
2741 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2742 int32_t ret;
2743
2744 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2745 (uint8_t *)&ctrl8_xl, 1);
2746
2747 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
2748 4) +
2749 ctrl8_xl.hpcf_xl))
2750 {
2751 case LSM6DSR_HP_PATH_DISABLE_ON_OUT:
2752 *val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
2753 break;
2754
2755 case LSM6DSR_SLOPE_ODR_DIV_4:
2756 *val = LSM6DSR_SLOPE_ODR_DIV_4;
2757 break;
2758
2759 case LSM6DSR_HP_ODR_DIV_10:
2760 *val = LSM6DSR_HP_ODR_DIV_10;
2761 break;
2762
2763 case LSM6DSR_HP_ODR_DIV_20:
2764 *val = LSM6DSR_HP_ODR_DIV_20;
2765 break;
2766
2767 case LSM6DSR_HP_ODR_DIV_45:
2768 *val = LSM6DSR_HP_ODR_DIV_45;
2769 break;
2770
2771 case LSM6DSR_HP_ODR_DIV_100:
2772 *val = LSM6DSR_HP_ODR_DIV_100;
2773 break;
2774
2775 case LSM6DSR_HP_ODR_DIV_200:
2776 *val = LSM6DSR_HP_ODR_DIV_200;
2777 break;
2778
2779 case LSM6DSR_HP_ODR_DIV_400:
2780 *val = LSM6DSR_HP_ODR_DIV_400;
2781 break;
2782
2783 case LSM6DSR_HP_ODR_DIV_800:
2784 *val = LSM6DSR_HP_ODR_DIV_800;
2785 break;
2786
2787 case LSM6DSR_HP_REF_MD_ODR_DIV_10:
2788 *val = LSM6DSR_HP_REF_MD_ODR_DIV_10;
2789 break;
2790
2791 case LSM6DSR_HP_REF_MD_ODR_DIV_20:
2792 *val = LSM6DSR_HP_REF_MD_ODR_DIV_20;
2793 break;
2794
2795 case LSM6DSR_HP_REF_MD_ODR_DIV_45:
2796 *val = LSM6DSR_HP_REF_MD_ODR_DIV_45;
2797 break;
2798
2799 case LSM6DSR_HP_REF_MD_ODR_DIV_100:
2800 *val = LSM6DSR_HP_REF_MD_ODR_DIV_100;
2801 break;
2802
2803 case LSM6DSR_HP_REF_MD_ODR_DIV_200:
2804 *val = LSM6DSR_HP_REF_MD_ODR_DIV_200;
2805 break;
2806
2807 case LSM6DSR_HP_REF_MD_ODR_DIV_400:
2808 *val = LSM6DSR_HP_REF_MD_ODR_DIV_400;
2809 break;
2810
2811 case LSM6DSR_HP_REF_MD_ODR_DIV_800:
2812 *val = LSM6DSR_HP_REF_MD_ODR_DIV_800;
2813 break;
2814
2815 case LSM6DSR_LP_ODR_DIV_10:
2816 *val = LSM6DSR_LP_ODR_DIV_10;
2817 break;
2818
2819 case LSM6DSR_LP_ODR_DIV_20:
2820 *val = LSM6DSR_LP_ODR_DIV_20;
2821 break;
2822
2823 case LSM6DSR_LP_ODR_DIV_45:
2824 *val = LSM6DSR_LP_ODR_DIV_45;
2825 break;
2826
2827 case LSM6DSR_LP_ODR_DIV_100:
2828 *val = LSM6DSR_LP_ODR_DIV_100;
2829 break;
2830
2831 case LSM6DSR_LP_ODR_DIV_200:
2832 *val = LSM6DSR_LP_ODR_DIV_200;
2833 break;
2834
2835 case LSM6DSR_LP_ODR_DIV_400:
2836 *val = LSM6DSR_LP_ODR_DIV_400;
2837 break;
2838
2839 case LSM6DSR_LP_ODR_DIV_800:
2840 *val = LSM6DSR_LP_ODR_DIV_800;
2841 break;
2842
2843 default:
2844 *val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
2845 break;
2846 }
2847
2848 return ret;
2849 }
2850
2851 /**
2852 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2853 * The filter sets the second samples after writing this bit.
2854 * Active only during device exit from powerdown mode.[set]
2855 *
2856 * @param ctx Read / write interface definitions.(ptr)
2857 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2858 * @retval Interface status (MANDATORY: return 0 -> no Error).
2859 *
2860 */
lsm6dsr_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2861 int32_t lsm6dsr_xl_fast_settling_set(const stmdev_ctx_t *ctx,
2862 uint8_t val)
2863 {
2864 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2865 int32_t ret;
2866
2867 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2868 (uint8_t *)&ctrl8_xl, 1);
2869
2870 if (ret == 0)
2871 {
2872 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2873 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2874 (uint8_t *)&ctrl8_xl, 1);
2875 }
2876
2877 return ret;
2878 }
2879
2880 /**
2881 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2882 * The filter sets the second samples after writing
2883 * this bit. Active only during device exit from powerdown mode.[get]
2884 *
2885 * @param ctx Read / write interface definitions.(ptr)
2886 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2887 * @retval Interface status (MANDATORY: return 0 -> no Error).
2888 *
2889 */
lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2890 int32_t lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t *ctx,
2891 uint8_t *val)
2892 {
2893 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2894 int32_t ret;
2895
2896 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL,
2897 (uint8_t *)&ctrl8_xl, 1);
2898 *val = ctrl8_xl.fastsettl_mode_xl;
2899
2900 return ret;
2901 }
2902
2903 /**
2904 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2905 * functions.[set]
2906 *
2907 * @param ctx Read / write interface definitions.(ptr)
2908 * @param val Change the values of slope_fds in reg TAP_CFG0
2909 * @retval Interface status (MANDATORY: return 0 -> no Error).
2910 *
2911 */
lsm6dsr_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsr_slope_fds_t val)2912 int32_t lsm6dsr_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2913 lsm6dsr_slope_fds_t val)
2914 {
2915 lsm6dsr_tap_cfg0_t tap_cfg0;
2916 int32_t ret;
2917
2918 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
2919 (uint8_t *)&tap_cfg0, 1);
2920
2921 if (ret == 0)
2922 {
2923 tap_cfg0.slope_fds = (uint8_t)val;
2924 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
2925 (uint8_t *)&tap_cfg0, 1);
2926 }
2927
2928 return ret;
2929 }
2930
2931 /**
2932 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2933 * functions.[get]
2934 *
2935 * @param ctx Read / write interface definitions.(ptr)
2936 * @param val Get the values of slope_fds in reg TAP_CFG0
2937 * @retval Interface status (MANDATORY: return 0 -> no Error).
2938 *
2939 */
lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsr_slope_fds_t * val)2940 int32_t lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2941 lsm6dsr_slope_fds_t *val)
2942 {
2943 lsm6dsr_tap_cfg0_t tap_cfg0;
2944 int32_t ret;
2945
2946 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
2947 (uint8_t *)&tap_cfg0, 1);
2948
2949 switch (tap_cfg0.slope_fds)
2950 {
2951 case LSM6DSR_USE_SLOPE:
2952 *val = LSM6DSR_USE_SLOPE;
2953 break;
2954
2955 case LSM6DSR_USE_HPF:
2956 *val = LSM6DSR_USE_HPF;
2957 break;
2958
2959 default:
2960 *val = LSM6DSR_USE_SLOPE;
2961 break;
2962 }
2963
2964 return ret;
2965 }
2966
2967 /**
2968 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2969 * only if the gyro is in HP mode.[set]
2970 *
2971 * @param ctx Read / write interface definitions.(ptr)
2972 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2973 * @retval Interface status (MANDATORY: return 0 -> no Error).
2974 *
2975 */
lsm6dsr_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsr_hpm_g_t val)2976 int32_t lsm6dsr_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2977 lsm6dsr_hpm_g_t val)
2978 {
2979 lsm6dsr_ctrl7_g_t ctrl7_g;
2980 int32_t ret;
2981
2982 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
2983 (uint8_t *)&ctrl7_g, 1);
2984
2985 if (ret == 0)
2986 {
2987 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2988 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2989 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G,
2990 (uint8_t *)&ctrl7_g, 1);
2991 }
2992
2993 return ret;
2994 }
2995
2996 /**
2997 * @brief Enables gyroscope digital high-pass filter. The filter is
2998 * enabled only if the gyro is in HP mode.[get]
2999 *
3000 * @param ctx Read / write interface definitions.(ptr)
3001 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3002 * @retval Interface status (MANDATORY: return 0 -> no Error).
3003 *
3004 */
lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsr_hpm_g_t * val)3005 int32_t lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
3006 lsm6dsr_hpm_g_t *val)
3007 {
3008 lsm6dsr_ctrl7_g_t ctrl7_g;
3009 int32_t ret;
3010
3011 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
3012 (uint8_t *)&ctrl7_g, 1);
3013
3014 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
3015 {
3016 case LSM6DSR_HP_FILTER_NONE:
3017 *val = LSM6DSR_HP_FILTER_NONE;
3018 break;
3019
3020 case LSM6DSR_HP_FILTER_16mHz:
3021 *val = LSM6DSR_HP_FILTER_16mHz;
3022 break;
3023
3024 case LSM6DSR_HP_FILTER_65mHz:
3025 *val = LSM6DSR_HP_FILTER_65mHz;
3026 break;
3027
3028 case LSM6DSR_HP_FILTER_260mHz:
3029 *val = LSM6DSR_HP_FILTER_260mHz;
3030 break;
3031
3032 case LSM6DSR_HP_FILTER_1Hz04:
3033 *val = LSM6DSR_HP_FILTER_1Hz04;
3034 break;
3035
3036 default:
3037 *val = LSM6DSR_HP_FILTER_NONE;
3038 break;
3039 }
3040
3041 return ret;
3042 }
3043
3044 /**
3045 * @}
3046 *
3047 */
3048
3049 /**
3050 * @defgroup LSM6DSR_ Auxiliary_interface
3051 * @brief This section groups all the functions concerning
3052 * auxiliary interface.
3053 * @{
3054 *
3055 */
3056
3057 /**
3058 * @brief On auxiliary interface connect/disconnect SDO and OCS
3059 * internal pull-up.[set]
3060 *
3061 * @param ctx Read / write interface definitions.(ptr)
3062 * @param val Change the values of ois_pu_dis in reg PIN_CTRL
3063 * @retval Interface status (MANDATORY: return 0 -> no Error).
3064 *
3065 */
lsm6dsr_aux_sdo_ocs_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_ois_pu_dis_t val)3066 int32_t lsm6dsr_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx,
3067 lsm6dsr_ois_pu_dis_t val)
3068 {
3069 lsm6dsr_pin_ctrl_t pin_ctrl;
3070 int32_t ret;
3071
3072 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL,
3073 (uint8_t *)&pin_ctrl, 1);
3074
3075 if (ret == 0)
3076 {
3077 pin_ctrl.ois_pu_dis = (uint8_t)val;
3078 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL,
3079 (uint8_t *)&pin_ctrl, 1);
3080 }
3081
3082 return ret;
3083 }
3084
3085 /**
3086 * @brief On auxiliary interface connect/disconnect SDO and OCS
3087 * internal pull-up.[get]
3088 *
3089 * @param ctx Read / write interface definitions.(ptr)
3090 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
3091 * @retval Interface status (MANDATORY: return 0 -> no Error).
3092 *
3093 */
lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_ois_pu_dis_t * val)3094 int32_t lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx,
3095 lsm6dsr_ois_pu_dis_t *val)
3096 {
3097 lsm6dsr_pin_ctrl_t pin_ctrl;
3098 int32_t ret;
3099
3100 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL,
3101 (uint8_t *)&pin_ctrl, 1);
3102
3103 switch (pin_ctrl.ois_pu_dis)
3104 {
3105 case LSM6DSR_AUX_PULL_UP_DISC:
3106 *val = LSM6DSR_AUX_PULL_UP_DISC;
3107 break;
3108
3109 case LSM6DSR_AUX_PULL_UP_CONNECT:
3110 *val = LSM6DSR_AUX_PULL_UP_CONNECT;
3111 break;
3112
3113 default:
3114 *val = LSM6DSR_AUX_PULL_UP_DISC;
3115 break;
3116 }
3117
3118 return ret;
3119 }
3120
3121 /**
3122 * @brief OIS chain on aux interface power on mode.[set]
3123 *
3124 * @param ctx Read / write interface definitions.(ptr)
3125 * @param val Change the values of ois_on in reg CTRL7_G
3126 * @retval Interface status (MANDATORY: return 0 -> no Error).
3127 *
3128 */
lsm6dsr_aux_pw_on_ctrl_set(const stmdev_ctx_t * ctx,lsm6dsr_ois_on_t val)3129 int32_t lsm6dsr_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx,
3130 lsm6dsr_ois_on_t val)
3131 {
3132 lsm6dsr_ctrl7_g_t ctrl7_g;
3133 int32_t ret;
3134
3135 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
3136 (uint8_t *)&ctrl7_g, 1);
3137
3138 if (ret == 0)
3139 {
3140 ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
3141 ctrl7_g.ois_on = (uint8_t)val & 0x01U;
3142 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G,
3143 (uint8_t *)&ctrl7_g, 1);
3144 }
3145
3146 return ret;
3147 }
3148
3149 /**
3150 * @brief OIS chain on aux interface power on mode[get]
3151 *
3152 * @param ctx Read / write interface definitions.(ptr)
3153 * @param val Get the values of ois_on in reg CTRL7_G
3154 * @retval Interface status (MANDATORY: return 0 -> no Error).
3155 *
3156 */
lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t * ctx,lsm6dsr_ois_on_t * val)3157 int32_t lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx,
3158 lsm6dsr_ois_on_t *val)
3159 {
3160 lsm6dsr_ctrl7_g_t ctrl7_g;
3161 int32_t ret;
3162
3163 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G,
3164 (uint8_t *)&ctrl7_g, 1);
3165
3166 switch (ctrl7_g.ois_on)
3167 {
3168 case LSM6DSR_AUX_ON:
3169 *val = LSM6DSR_AUX_ON;
3170 break;
3171
3172 case LSM6DSR_AUX_ON_BY_AUX_INTERFACE:
3173 *val = LSM6DSR_AUX_ON_BY_AUX_INTERFACE;
3174 break;
3175
3176 default:
3177 *val = LSM6DSR_AUX_ON;
3178 break;
3179 }
3180
3181 return ret;
3182 }
3183
3184 /**
3185 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3186 *
3187 * @param ctx Read / write interface definitions.(ptr)
3188 * @param lsm6dsr_status_spiaux_t: registers STATUS_SPIAUX
3189 * @retval Interface status (MANDATORY: return 0 -> no Error).
3190 *
3191 */
lsm6dsr_aux_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsr_status_spiaux_t * val)3192 int32_t lsm6dsr_aux_status_reg_get(const stmdev_ctx_t *ctx,
3193 lsm6dsr_status_spiaux_t *val)
3194 {
3195 int32_t ret;
3196
3197 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3198 (uint8_t *)val, 1);
3199
3200 return ret;
3201 }
3202
3203 /**
3204 * @brief AUX accelerometer data available.[get]
3205 *
3206 * @param ctx Read / write interface definitions.(ptr)
3207 * @param val Change the values of xlda in reg STATUS_SPIAUX
3208 * @retval Interface status (MANDATORY: return 0 -> no Error).
3209 *
3210 */
lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3211 int32_t lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
3212 uint8_t *val)
3213 {
3214 lsm6dsr_status_spiaux_t status_spiaux;
3215 int32_t ret;
3216
3217 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3218 (uint8_t *)&status_spiaux, 1);
3219 *val = status_spiaux.xlda;
3220
3221 return ret;
3222 }
3223
3224 /**
3225 * @brief AUX gyroscope data available.[get]
3226 *
3227 * @param ctx Read / write interface definitions.(ptr)
3228 * @param val Change the values of gda in reg STATUS_SPIAUX
3229 * @retval Interface status (MANDATORY: return 0 -> no Error).
3230 *
3231 */
lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3232 int32_t lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
3233 uint8_t *val)
3234 {
3235 lsm6dsr_status_spiaux_t status_spiaux;
3236 int32_t ret;
3237
3238 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3239 (uint8_t *)&status_spiaux, 1);
3240 *val = status_spiaux.gda;
3241
3242 return ret;
3243 }
3244
3245 /**
3246 * @brief High when the gyroscope output is in the settling phase.[get]
3247 *
3248 * @param ctx Read / write interface definitions.(ptr)
3249 * @param val Change the values of gyro_settling in reg STATUS_SPIAUX
3250 * @retval Interface status (MANDATORY: return 0 -> no Error).
3251 *
3252 */
lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3253 int32_t lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
3254 uint8_t *val)
3255 {
3256 lsm6dsr_status_spiaux_t status_spiaux;
3257 int32_t ret;
3258
3259 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3260 (uint8_t *)&status_spiaux, 1);
3261 *val = status_spiaux.gyro_settling;
3262
3263 return ret;
3264 }
3265
3266 /**
3267 * @brief Selects accelerometer self-test. Effective only if XL OIS chain is
3268 * enabled.[set]
3269 *
3270 * @param ctx Read / write interface definitions.(ptr)
3271 * @param val Change the values of st_xl_ois in reg INT_OIS
3272 * @retval Interface status (MANDATORY: return 0 -> no Error).
3273 *
3274 */
lsm6dsr_aux_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsr_st_xl_ois_t val)3275 int32_t lsm6dsr_aux_xl_self_test_set(const stmdev_ctx_t *ctx,
3276 lsm6dsr_st_xl_ois_t val)
3277 {
3278 lsm6dsr_int_ois_t int_ois;
3279 int32_t ret;
3280
3281 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3282 (uint8_t *)&int_ois, 1);
3283
3284 if (ret == 0)
3285 {
3286 int_ois.st_xl_ois = (uint8_t)val;
3287 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS,
3288 (uint8_t *)&int_ois, 1);
3289 }
3290
3291 return ret;
3292 }
3293
3294 /**
3295 * @brief Selects accelerometer self-test. Effective only if XL OIS chain
3296 * is enabled.[get]
3297 *
3298 * @param ctx Read / write interface definitions.(ptr)
3299 * @param val Get the values of st_xl_ois in reg INT_OIS
3300 * @retval Interface status (MANDATORY: return 0 -> no Error).
3301 *
3302 */
lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsr_st_xl_ois_t * val)3303 int32_t lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t *ctx,
3304 lsm6dsr_st_xl_ois_t *val)
3305 {
3306 lsm6dsr_int_ois_t int_ois;
3307 int32_t ret;
3308
3309 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3310 (uint8_t *)&int_ois, 1);
3311
3312 switch (int_ois.st_xl_ois)
3313 {
3314 case LSM6DSR_AUX_XL_DISABLE:
3315 *val = LSM6DSR_AUX_XL_DISABLE;
3316 break;
3317
3318 case LSM6DSR_AUX_XL_POS:
3319 *val = LSM6DSR_AUX_XL_POS;
3320 break;
3321
3322 case LSM6DSR_AUX_XL_NEG:
3323 *val = LSM6DSR_AUX_XL_NEG;
3324 break;
3325
3326 default:
3327 *val = LSM6DSR_AUX_XL_DISABLE;
3328 break;
3329 }
3330
3331 return ret;
3332 }
3333
3334 /**
3335 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3336 *
3337 * @param ctx Read / write interface definitions.(ptr)
3338 * @param val Change the values of den_lh_ois in reg INT_OIS
3339 * @retval Interface status (MANDATORY: return 0 -> no Error).
3340 *
3341 */
lsm6dsr_aux_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsr_den_lh_ois_t val)3342 int32_t lsm6dsr_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3343 lsm6dsr_den_lh_ois_t val)
3344 {
3345 lsm6dsr_int_ois_t int_ois;
3346 int32_t ret;
3347
3348 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3349 (uint8_t *)&int_ois, 1);
3350
3351 if (ret == 0)
3352 {
3353 int_ois.den_lh_ois = (uint8_t)val;
3354 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS,
3355 (uint8_t *)&int_ois, 1);
3356 }
3357
3358 return ret;
3359 }
3360
3361 /**
3362 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3363 *
3364 * @param ctx Read / write interface definitions.(ptr)
3365 * @param val Get the values of den_lh_ois in reg INT_OIS
3366 * @retval Interface status (MANDATORY: return 0 -> no Error).
3367 *
3368 */
lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsr_den_lh_ois_t * val)3369 int32_t lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3370 lsm6dsr_den_lh_ois_t *val)
3371 {
3372 lsm6dsr_int_ois_t int_ois;
3373 int32_t ret;
3374
3375 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3376 (uint8_t *)&int_ois, 1);
3377
3378 switch (int_ois.den_lh_ois)
3379 {
3380 case LSM6DSR_AUX_DEN_ACTIVE_LOW:
3381 *val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
3382 break;
3383
3384 case LSM6DSR_AUX_DEN_ACTIVE_HIGH:
3385 *val = LSM6DSR_AUX_DEN_ACTIVE_HIGH;
3386 break;
3387
3388 default:
3389 *val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
3390 break;
3391 }
3392
3393 return ret;
3394 }
3395
3396 /**
3397 * @brief Configure DEN mode on the OIS chain.[set]
3398 *
3399 * @param ctx Read / write interface definitions.(ptr)
3400 * @param val Change the values of lvl2_ois in reg INT_OIS
3401 * @retval Interface status (MANDATORY: return 0 -> no Error).
3402 *
3403 */
lsm6dsr_aux_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_lvl2_ois_t val)3404 int32_t lsm6dsr_aux_den_mode_set(const stmdev_ctx_t *ctx,
3405 lsm6dsr_lvl2_ois_t val)
3406 {
3407 lsm6dsr_int_ois_t int_ois;
3408 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3409 int32_t ret;
3410
3411 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3412 (uint8_t *)&int_ois, 1);
3413
3414 if (ret == 0)
3415 {
3416 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3417 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS,
3418 (uint8_t *)&int_ois, 1);
3419 }
3420
3421 if (ret == 0)
3422 {
3423 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3424 (uint8_t *)&ctrl1_ois, 1);
3425 }
3426
3427 if (ret == 0)
3428 {
3429 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3430 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3431 (uint8_t *)&ctrl1_ois, 1);
3432 }
3433
3434 return ret;
3435 }
3436
3437 /**
3438 * @brief Configure DEN mode on the OIS chain.[get]
3439 *
3440 * @param ctx Read / write interface definitions.(ptr)
3441 * @param val Get the values of lvl2_ois in reg INT_OIS
3442 * @retval Interface status (MANDATORY: return 0 -> no Error).
3443 *
3444 */
lsm6dsr_aux_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_lvl2_ois_t * val)3445 int32_t lsm6dsr_aux_den_mode_get(const stmdev_ctx_t *ctx,
3446 lsm6dsr_lvl2_ois_t *val)
3447 {
3448 lsm6dsr_int_ois_t int_ois;
3449 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3450 int32_t ret;
3451
3452 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3453 (uint8_t *)&int_ois, 1);
3454
3455 if (ret == 0)
3456 {
3457 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3458 (uint8_t *)&ctrl1_ois, 1);
3459 }
3460
3461 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3462 {
3463 case LSM6DSR_AUX_DEN_DISABLE:
3464 *val = LSM6DSR_AUX_DEN_DISABLE;
3465 break;
3466
3467 case LSM6DSR_AUX_DEN_LEVEL_LATCH:
3468 *val = LSM6DSR_AUX_DEN_LEVEL_LATCH;
3469 break;
3470
3471 case LSM6DSR_AUX_DEN_LEVEL_TRIG:
3472 *val = LSM6DSR_AUX_DEN_LEVEL_TRIG;
3473 break;
3474
3475 default:
3476 *val = LSM6DSR_AUX_DEN_DISABLE;
3477 break;
3478 }
3479
3480 return ret;
3481 }
3482
3483 /**
3484 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3485 * priority over all other INT2 settings.[set]
3486 *
3487 * @param ctx Read / write interface definitions.(ptr)
3488 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3489 * @retval Interface status (MANDATORY: return 0 -> no Error).
3490 *
3491 */
lsm6dsr_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3492 int32_t lsm6dsr_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx,
3493 uint8_t val)
3494 {
3495 lsm6dsr_int_ois_t int_ois;
3496 int32_t ret;
3497
3498 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3499 (uint8_t *)&int_ois, 1);
3500
3501 if (ret == 0)
3502 {
3503 int_ois.int2_drdy_ois = (uint8_t)val;
3504 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS,
3505 (uint8_t *)&int_ois, 1);
3506 }
3507
3508 return ret;
3509 }
3510
3511 /**
3512 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3513 * priority over all other INT2 settings.[get]
3514 *
3515 * @param ctx Read / write interface definitions.(ptr)
3516 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3517 * @retval Interface status (MANDATORY: return 0 -> no Error).
3518 *
3519 */
lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3520 int32_t lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx,
3521 uint8_t *val)
3522 {
3523 lsm6dsr_int_ois_t int_ois;
3524 int32_t ret;
3525
3526 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS,
3527 (uint8_t *)&int_ois, 1);
3528 *val = int_ois.int2_drdy_ois;
3529
3530 return ret;
3531 }
3532
3533 /**
3534 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3535 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3536 * When the OIS chain is enabled, the OIS outputs are available
3537 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3538 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3539 * this chain.[set]
3540 *
3541 * @param ctx Read / write interface definitions.(ptr)
3542 * @param val Change the values of ois_en_spi2 in reg CTRL1_OIS
3543 * @retval Interface status (MANDATORY: return 0 -> no Error).
3544 *
3545 */
lsm6dsr_aux_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_ois_en_spi2_t val)3546 int32_t lsm6dsr_aux_mode_set(const stmdev_ctx_t *ctx,
3547 lsm6dsr_ois_en_spi2_t val)
3548 {
3549 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3550 int32_t ret;
3551
3552 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3553 (uint8_t *)&ctrl1_ois, 1);
3554
3555 if (ret == 0)
3556 {
3557 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3558 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3559 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3560 (uint8_t *)&ctrl1_ois, 1);
3561 }
3562
3563 return ret;
3564 }
3565
3566 /**
3567 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3568 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3569 * When the OIS chain is enabled, the OIS outputs are available
3570 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3571 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3572 * this chain.[get]
3573 *
3574 * @param ctx Read / write interface definitions.(ptr)
3575 * @param val Get the values of ois_en_spi2 in
3576 * reg CTRL1_OIS
3577 * @retval Interface status (MANDATORY: return 0 -> no Error).
3578 *
3579 */
lsm6dsr_aux_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_ois_en_spi2_t * val)3580 int32_t lsm6dsr_aux_mode_get(const stmdev_ctx_t *ctx,
3581 lsm6dsr_ois_en_spi2_t *val)
3582 {
3583 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3584 int32_t ret;
3585
3586 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3587 (uint8_t *)&ctrl1_ois, 1);
3588
3589 switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
3590 {
3591 case LSM6DSR_AUX_DISABLE:
3592 *val = LSM6DSR_AUX_DISABLE;
3593 break;
3594
3595 case LSM6DSR_MODE_3_GY:
3596 *val = LSM6DSR_MODE_3_GY;
3597 break;
3598
3599 case LSM6DSR_MODE_4_GY_XL:
3600 *val = LSM6DSR_MODE_4_GY_XL;
3601 break;
3602
3603 default:
3604 *val = LSM6DSR_AUX_DISABLE;
3605 break;
3606 }
3607
3608 return ret;
3609 }
3610
3611 /**
3612 * @brief Selects gyroscope OIS chain full-scale.[set]
3613 *
3614 * @param ctx Read / write interface definitions.(ptr)
3615 * @param val Change the values of fs_g_ois in reg CTRL1_OIS
3616 * @retval Interface status (MANDATORY: return 0 -> no Error).
3617 *
3618 */
lsm6dsr_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsr_fs_g_ois_t val)3619 int32_t lsm6dsr_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3620 lsm6dsr_fs_g_ois_t val)
3621 {
3622 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3623 int32_t ret;
3624
3625 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3626 (uint8_t *)&ctrl1_ois, 1);
3627
3628 if (ret == 0)
3629 {
3630 ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
3631 ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
3632 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3633 (uint8_t *)&ctrl1_ois, 1);
3634 }
3635
3636 return ret;
3637 }
3638
3639 /**
3640 * @brief Selects gyroscope OIS chain full-scale.[get]
3641 *
3642 * @param ctx Read / write interface definitions.(ptr)
3643 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3644 * @retval Interface status (MANDATORY: return 0 -> no Error).
3645 *
3646 */
lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsr_fs_g_ois_t * val)3647 int32_t lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3648 lsm6dsr_fs_g_ois_t *val)
3649 {
3650 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3651 int32_t ret;
3652
3653 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3654 (uint8_t *)&ctrl1_ois, 1);
3655
3656 switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
3657 {
3658 case LSM6DSR_250dps_AUX:
3659 *val = LSM6DSR_250dps_AUX;
3660 break;
3661
3662 case LSM6DSR_125dps_AUX:
3663 *val = LSM6DSR_125dps_AUX;
3664 break;
3665
3666 case LSM6DSR_500dps_AUX:
3667 *val = LSM6DSR_500dps_AUX;
3668 break;
3669
3670 case LSM6DSR_1000dps_AUX:
3671 *val = LSM6DSR_1000dps_AUX;
3672 break;
3673
3674 case LSM6DSR_2000dps_AUX:
3675 *val = LSM6DSR_2000dps_AUX;
3676 break;
3677
3678 default:
3679 *val = LSM6DSR_250dps_AUX;
3680 break;
3681 }
3682
3683 return ret;
3684 }
3685
3686 /**
3687 * @brief SPI2 3- or 4-wire interface.[set]
3688 *
3689 * @param ctx Read / write interface definitions.(ptr)
3690 * @param val Change the values of sim_ois in reg CTRL1_OIS
3691 * @retval Interface status (MANDATORY: return 0 -> no Error).
3692 *
3693 */
lsm6dsr_aux_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_sim_ois_t val)3694 int32_t lsm6dsr_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3695 lsm6dsr_sim_ois_t val)
3696 {
3697 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3698 int32_t ret;
3699
3700 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3701 (uint8_t *)&ctrl1_ois, 1);
3702
3703 if (ret == 0)
3704 {
3705 ctrl1_ois.sim_ois = (uint8_t)val;
3706 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3707 (uint8_t *)&ctrl1_ois, 1);
3708 }
3709
3710 return ret;
3711 }
3712
3713 /**
3714 * @brief SPI2 3- or 4-wire interface.[get]
3715 *
3716 * @param ctx Read / write interface definitions.(ptr)
3717 * @param val Get the values of sim_ois in reg CTRL1_OIS
3718 * @retval Interface status (MANDATORY: return 0 -> no Error).
3719 *
3720 */
lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_sim_ois_t * val)3721 int32_t lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3722 lsm6dsr_sim_ois_t *val)
3723 {
3724 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3725 int32_t ret;
3726
3727 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3728 (uint8_t *)&ctrl1_ois, 1);
3729
3730 switch (ctrl1_ois.sim_ois)
3731 {
3732 case LSM6DSR_AUX_SPI_4_WIRE:
3733 *val = LSM6DSR_AUX_SPI_4_WIRE;
3734 break;
3735
3736 case LSM6DSR_AUX_SPI_3_WIRE:
3737 *val = LSM6DSR_AUX_SPI_3_WIRE;
3738 break;
3739
3740 default:
3741 *val = LSM6DSR_AUX_SPI_4_WIRE;
3742 break;
3743 }
3744
3745 return ret;
3746 }
3747
3748 /**
3749 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3750 *
3751 * @param ctx Read / write interface definitions.(ptr)
3752 * @param val Change the values of ftype_ois in reg CTRL2_OIS
3753 * @retval Interface status (MANDATORY: return 0 -> no Error).
3754 *
3755 */
lsm6dsr_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsr_ftype_ois_t val)3756 int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
3757 lsm6dsr_ftype_ois_t val)
3758 {
3759 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3760 int32_t ret;
3761
3762 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS,
3763 (uint8_t *)&ctrl2_ois, 1);
3764
3765 if (ret == 0)
3766 {
3767 ctrl2_ois.ftype_ois = (uint8_t)val;
3768 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
3769 (uint8_t *)&ctrl2_ois, 1);
3770 }
3771
3772 return ret;
3773 }
3774
3775 /**
3776 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3777 *
3778 * @param ctx Read / write interface definitions.(ptr)
3779 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3780 * @retval Interface status (MANDATORY: return 0 -> no Error).
3781 *
3782 */
lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsr_ftype_ois_t * val)3783 int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
3784 lsm6dsr_ftype_ois_t *val)
3785 {
3786 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3787 int32_t ret;
3788
3789 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS,
3790 (uint8_t *)&ctrl2_ois, 1);
3791
3792 switch (ctrl2_ois.ftype_ois)
3793 {
3794 case LSM6DSR_351Hz39:
3795 *val = LSM6DSR_351Hz39;
3796 break;
3797
3798 case LSM6DSR_236Hz63:
3799 *val = LSM6DSR_236Hz63;
3800 break;
3801
3802 case LSM6DSR_172Hz70:
3803 *val = LSM6DSR_172Hz70;
3804 break;
3805
3806 case LSM6DSR_937Hz91:
3807 *val = LSM6DSR_937Hz91;
3808 break;
3809
3810 default:
3811 *val = LSM6DSR_351Hz39;
3812 break;
3813 }
3814
3815 return ret;
3816 }
3817
3818 /**
3819 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
3820 *
3821 * @param ctx Read / write interface definitions.(ptr)
3822 * @param val Change the values of hpm_ois in reg CTRL2_OIS
3823 * @retval Interface status (MANDATORY: return 0 -> no Error).
3824 *
3825 */
lsm6dsr_aux_gy_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsr_hpm_ois_t val)3826 int32_t lsm6dsr_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx,
3827 lsm6dsr_hpm_ois_t val)
3828 {
3829 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3830 int32_t ret;
3831
3832 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS,
3833 (uint8_t *)&ctrl2_ois, 1);
3834
3835 if (ret == 0)
3836 {
3837 ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
3838 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
3839 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
3840 (uint8_t *)&ctrl2_ois, 1);
3841 }
3842
3843 return ret;
3844 }
3845
3846 /**
3847 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
3848 *
3849 * @param ctx Read / write interface definitions.(ptr)
3850 * @param val Get the values of hpm_ois in reg CTRL2_OIS
3851 * @retval Interface status (MANDATORY: return 0 -> no Error).
3852 *
3853 */
lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsr_hpm_ois_t * val)3854 int32_t lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx,
3855 lsm6dsr_hpm_ois_t *val)
3856 {
3857 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3858 int32_t ret;
3859
3860 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS,
3861 (uint8_t *)&ctrl2_ois, 1);
3862
3863 switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
3864 {
3865 case LSM6DSR_AUX_HP_DISABLE:
3866 *val = LSM6DSR_AUX_HP_DISABLE;
3867 break;
3868
3869 case LSM6DSR_AUX_HP_Hz016:
3870 *val = LSM6DSR_AUX_HP_Hz016;
3871 break;
3872
3873 case LSM6DSR_AUX_HP_Hz065:
3874 *val = LSM6DSR_AUX_HP_Hz065;
3875 break;
3876
3877 case LSM6DSR_AUX_HP_Hz260:
3878 *val = LSM6DSR_AUX_HP_Hz260;
3879 break;
3880
3881 case LSM6DSR_AUX_HP_1Hz040:
3882 *val = LSM6DSR_AUX_HP_1Hz040;
3883 break;
3884
3885 default:
3886 *val = LSM6DSR_AUX_HP_DISABLE;
3887 break;
3888 }
3889
3890 return ret;
3891 }
3892
3893 /**
3894 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3895 * outputs = 8000h during self-test; Disable: OIS chain self-test
3896 * outputs dependent from the aux gyro full scale selected.[set]
3897 *
3898 * @param ctx Read / write interface definitions.(ptr)
3899 * @param val Change the values of st_ois_clampdis in reg CTRL3_OIS
3900 * @retval Interface status (MANDATORY: return 0 -> no Error).
3901 *
3902 */
lsm6dsr_aux_gy_clamp_set(const stmdev_ctx_t * ctx,lsm6dsr_st_ois_clampdis_t val)3903 int32_t lsm6dsr_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
3904 lsm6dsr_st_ois_clampdis_t val)
3905 {
3906 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3907 int32_t ret;
3908
3909 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
3910 (uint8_t *)&ctrl3_ois, 1);
3911
3912 if (ret == 0)
3913 {
3914 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
3915 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
3916 (uint8_t *)&ctrl3_ois, 1);
3917 }
3918
3919 return ret;
3920 }
3921
3922 /**
3923 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3924 * outputs = 8000h during self-test; Disable: OIS chain self-test
3925 * outputs dependent from the aux gyro full scale selected.[get]
3926 *
3927 * @param ctx Read / write interface definitions.(ptr)
3928 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
3929 * @retval Interface status (MANDATORY: return 0 -> no Error).
3930 *
3931 */
lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t * ctx,lsm6dsr_st_ois_clampdis_t * val)3932 int32_t lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
3933 lsm6dsr_st_ois_clampdis_t *val)
3934 {
3935 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3936 int32_t ret;
3937
3938 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
3939 (uint8_t *)&ctrl3_ois, 1);
3940
3941 switch (ctrl3_ois.st_ois_clampdis)
3942 {
3943 case LSM6DSR_ENABLE_CLAMP:
3944 *val = LSM6DSR_ENABLE_CLAMP;
3945 break;
3946
3947 case LSM6DSR_DISABLE_CLAMP:
3948 *val = LSM6DSR_DISABLE_CLAMP;
3949 break;
3950
3951 default:
3952 *val = LSM6DSR_ENABLE_CLAMP;
3953 break;
3954 }
3955
3956 return ret;
3957 }
3958
3959 /**
3960 * @brief Selects gyroscope OIS chain self-test.[set]
3961 *
3962 * @param ctx Read / write interface definitions.(ptr)
3963 * @param val Change the values of st_ois in reg CTRL3_OIS
3964 * @retval Interface status (MANDATORY: return 0 -> no Error).
3965 *
3966 */
lsm6dsr_aux_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsr_st_ois_t val)3967 int32_t lsm6dsr_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
3968 lsm6dsr_st_ois_t val)
3969 {
3970 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3971 int32_t ret;
3972
3973 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
3974 (uint8_t *)&ctrl3_ois, 1);
3975
3976 if (ret == 0)
3977 {
3978 ctrl3_ois.st_ois = (uint8_t)val;
3979 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
3980 (uint8_t *)&ctrl3_ois, 1);
3981 }
3982
3983 return ret;
3984 }
3985
3986 /**
3987 * @brief Selects gyroscope OIS chain self-test.[get]
3988 *
3989 * @param ctx Read / write interface definitions.(ptr)
3990 * @param val Get the values of st_ois in reg CTRL3_OIS
3991 * @retval Interface status (MANDATORY: return 0 -> no Error).
3992 *
3993 */
lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsr_st_ois_t * val)3994 int32_t lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
3995 lsm6dsr_st_ois_t *val)
3996 {
3997 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3998 int32_t ret;
3999
4000 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
4001 (uint8_t *)&ctrl3_ois, 1);
4002
4003 switch (ctrl3_ois.st_ois)
4004 {
4005 case LSM6DSR_AUX_GY_DISABLE:
4006 *val = LSM6DSR_AUX_GY_DISABLE;
4007 break;
4008
4009 case LSM6DSR_AUX_GY_POS:
4010 *val = LSM6DSR_AUX_GY_POS;
4011 break;
4012
4013 case LSM6DSR_AUX_GY_NEG:
4014 *val = LSM6DSR_AUX_GY_NEG;
4015 break;
4016
4017 default:
4018 *val = LSM6DSR_AUX_GY_DISABLE;
4019 break;
4020 }
4021
4022 return ret;
4023 }
4024
4025 /**
4026 * @brief Selects accelerometer OIS channel bandwidth.[set]
4027 *
4028 * @param ctx Read / write interface definitions.(ptr)
4029 * @param val Change the values of filter_xl_conf_ois in reg CTRL3_OIS
4030 * @retval Interface status (MANDATORY: return 0 -> no Error).
4031 *
4032 */
lsm6dsr_aux_xl_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsr_filter_xl_conf_ois_t val)4033 int32_t lsm6dsr_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx,
4034 lsm6dsr_filter_xl_conf_ois_t val)
4035 {
4036 lsm6dsr_ctrl3_ois_t ctrl3_ois;
4037 int32_t ret;
4038
4039 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
4040 (uint8_t *)&ctrl3_ois, 1);
4041
4042 if (ret == 0)
4043 {
4044 ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
4045 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
4046 (uint8_t *)&ctrl3_ois, 1);
4047 }
4048
4049 return ret;
4050 }
4051
4052 /**
4053 * @brief Selects accelerometer OIS channel bandwidth.[get]
4054 *
4055 * @param ctx Read / write interface definitions.(ptr)
4056 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
4057 * @retval Interface status (MANDATORY: return 0 -> no Error).
4058 *
4059 */
lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsr_filter_xl_conf_ois_t * val)4060 int32_t lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx,
4061 lsm6dsr_filter_xl_conf_ois_t *val)
4062 {
4063 lsm6dsr_ctrl3_ois_t ctrl3_ois;
4064 int32_t ret;
4065
4066 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
4067 (uint8_t *)&ctrl3_ois, 1);
4068
4069 switch (ctrl3_ois.filter_xl_conf_ois)
4070 {
4071 case LSM6DSR_631Hz:
4072 *val = LSM6DSR_631Hz;
4073 break;
4074
4075 case LSM6DSR_295Hz:
4076 *val = LSM6DSR_295Hz;
4077 break;
4078
4079 case LSM6DSR_140Hz:
4080 *val = LSM6DSR_140Hz;
4081 break;
4082
4083 case LSM6DSR_68Hz2:
4084 *val = LSM6DSR_68Hz2;
4085 break;
4086
4087 case LSM6DSR_33Hz6:
4088 *val = LSM6DSR_33Hz6;
4089 break;
4090
4091 case LSM6DSR_16Hz7:
4092 *val = LSM6DSR_16Hz7;
4093 break;
4094
4095 case LSM6DSR_8Hz3:
4096 *val = LSM6DSR_8Hz3;
4097 break;
4098
4099 case LSM6DSR_4Hz11:
4100 *val = LSM6DSR_4Hz11;
4101 break;
4102
4103 default:
4104 *val = LSM6DSR_631Hz;
4105 break;
4106 }
4107
4108 return ret;
4109 }
4110
4111 /**
4112 * @brief Selects accelerometer OIS channel full-scale.[set]
4113 *
4114 * @param ctx Read / write interface definitions.(ptr)
4115 * @param val Change the values of fs_xl_ois in reg CTRL3_OIS
4116 * @retval Interface status (MANDATORY: return 0 -> no Error).
4117 *
4118 */
lsm6dsr_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsr_fs_xl_ois_t val)4119 int32_t lsm6dsr_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
4120 lsm6dsr_fs_xl_ois_t val)
4121 {
4122 lsm6dsr_ctrl3_ois_t ctrl3_ois;
4123 int32_t ret;
4124
4125 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
4126 (uint8_t *)&ctrl3_ois, 1);
4127
4128 if (ret == 0)
4129 {
4130 ctrl3_ois.fs_xl_ois = (uint8_t)val;
4131 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
4132 (uint8_t *)&ctrl3_ois, 1);
4133 }
4134
4135 return ret;
4136 }
4137
4138 /**
4139 * @brief Selects accelerometer OIS channel full-scale.[get]
4140 *
4141 * @param ctx Read / write interface definitions.(ptr)
4142 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4143 * @retval Interface status (MANDATORY: return 0 -> no Error).
4144 *
4145 */
lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsr_fs_xl_ois_t * val)4146 int32_t lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
4147 lsm6dsr_fs_xl_ois_t *val)
4148 {
4149 lsm6dsr_ctrl3_ois_t ctrl3_ois;
4150 int32_t ret;
4151
4152 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS,
4153 (uint8_t *)&ctrl3_ois, 1);
4154
4155 switch (ctrl3_ois.fs_xl_ois)
4156 {
4157 case LSM6DSR_AUX_2g:
4158 *val = LSM6DSR_AUX_2g;
4159 break;
4160
4161 case LSM6DSR_AUX_16g:
4162 *val = LSM6DSR_AUX_16g;
4163 break;
4164
4165 case LSM6DSR_AUX_4g:
4166 *val = LSM6DSR_AUX_4g;
4167 break;
4168
4169 case LSM6DSR_AUX_8g:
4170 *val = LSM6DSR_AUX_8g;
4171 break;
4172
4173 default:
4174 *val = LSM6DSR_AUX_2g;
4175 break;
4176 }
4177
4178 return ret;
4179 }
4180
4181 /**
4182 * @}
4183 *
4184 */
4185
4186 /**
4187 * @defgroup LSM6DSR_ main_serial_interface
4188 * @brief This section groups all the functions concerning main
4189 * serial interface management (not auxiliary)
4190 * @{
4191 *
4192 */
4193
4194 /**
4195 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4196 *
4197 * @param ctx Read / write interface definitions.(ptr)
4198 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
4199 * @retval Interface status (MANDATORY: return 0 -> no Error).
4200 *
4201 */
lsm6dsr_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_sdo_pu_en_t val)4202 int32_t lsm6dsr_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
4203 lsm6dsr_sdo_pu_en_t val)
4204 {
4205 lsm6dsr_pin_ctrl_t pin_ctrl;
4206 int32_t ret;
4207
4208 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL,
4209 (uint8_t *)&pin_ctrl, 1);
4210
4211 if (ret == 0)
4212 {
4213 pin_ctrl.sdo_pu_en = (uint8_t)val;
4214 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL,
4215 (uint8_t *)&pin_ctrl, 1);
4216 }
4217
4218 return ret;
4219 }
4220
4221 /**
4222 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4223 *
4224 * @param ctx Read / write interface definitions.(ptr)
4225 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4226 * @retval Interface status (MANDATORY: return 0 -> no Error).
4227 *
4228 */
lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_sdo_pu_en_t * val)4229 int32_t lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
4230 lsm6dsr_sdo_pu_en_t *val)
4231 {
4232 lsm6dsr_pin_ctrl_t pin_ctrl;
4233 int32_t ret;
4234
4235 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL,
4236 (uint8_t *)&pin_ctrl, 1);
4237
4238 switch (pin_ctrl.sdo_pu_en)
4239 {
4240 case LSM6DSR_PULL_UP_DISC:
4241 *val = LSM6DSR_PULL_UP_DISC;
4242 break;
4243
4244 case LSM6DSR_PULL_UP_CONNECT:
4245 *val = LSM6DSR_PULL_UP_CONNECT;
4246 break;
4247
4248 default:
4249 *val = LSM6DSR_PULL_UP_DISC;
4250 break;
4251 }
4252
4253 return ret;
4254 }
4255
4256 /**
4257 * @brief Connect/Disconnect INT1 pull-down.[set]
4258 *
4259 * @param ctx Read / write interface definitions.(ptr)
4260 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
4261 * @retval Interface status (MANDATORY: return 0 -> no Error).
4262 *
4263 */
lsm6dsr_int1_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_pd_dis_int1_t val)4264 int32_t lsm6dsr_int1_mode_set(const stmdev_ctx_t *ctx,
4265 lsm6dsr_pd_dis_int1_t val)
4266 {
4267 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4268 int32_t ret;
4269
4270 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4271 (uint8_t *)&i3c_bus_avb, 1);
4272
4273 if (ret == 0)
4274 {
4275 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
4276 ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4277 (uint8_t *)&i3c_bus_avb, 1);
4278 }
4279
4280 return ret;
4281 }
4282
4283 /**
4284 * @brief Connect/Disconnect INT1 pull-down.[get]
4285 *
4286 * @param ctx Read / write interface definitions.(ptr)
4287 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4288 * @retval Interface status (MANDATORY: return 0 -> no Error).
4289 *
4290 */
lsm6dsr_int1_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_pd_dis_int1_t * val)4291 int32_t lsm6dsr_int1_mode_get(const stmdev_ctx_t *ctx,
4292 lsm6dsr_pd_dis_int1_t *val)
4293 {
4294 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4295 int32_t ret;
4296
4297 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4298 (uint8_t *)&i3c_bus_avb, 1);
4299
4300 switch (i3c_bus_avb.pd_dis_int1)
4301 {
4302 case LSM6DSR_PULL_DOWN_CONNECT:
4303 *val = LSM6DSR_PULL_DOWN_CONNECT;
4304 break;
4305
4306 case LSM6DSR_PULL_DOWN_DISC:
4307 *val = LSM6DSR_PULL_DOWN_DISC;
4308 break;
4309
4310 default:
4311 *val = LSM6DSR_PULL_DOWN_CONNECT;
4312 break;
4313 }
4314
4315 return ret;
4316 }
4317
4318 /**
4319 * @brief SPI Serial Interface Mode selection.[set]
4320 *
4321 * @param ctx Read / write interface definitions.(ptr)
4322 * @param val Change the values of sim in reg CTRL3_C
4323 * @retval Interface status (MANDATORY: return 0 -> no Error).
4324 *
4325 */
lsm6dsr_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_sim_t val)4326 int32_t lsm6dsr_spi_mode_set(const stmdev_ctx_t *ctx,
4327 lsm6dsr_sim_t val)
4328 {
4329 lsm6dsr_ctrl3_c_t ctrl3_c;
4330 int32_t ret;
4331
4332 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4333 (uint8_t *)&ctrl3_c, 1);
4334
4335 if (ret == 0)
4336 {
4337 ctrl3_c.sim = (uint8_t)val;
4338 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
4339 (uint8_t *)&ctrl3_c, 1);
4340 }
4341
4342 return ret;
4343 }
4344
4345 /**
4346 * @brief SPI Serial Interface Mode selection.[get]
4347 *
4348 * @param ctx Read / write interface definitions.(ptr)
4349 * @param val Get the values of sim in reg CTRL3_C
4350 * @retval Interface status (MANDATORY: return 0 -> no Error).
4351 *
4352 */
lsm6dsr_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_sim_t * val)4353 int32_t lsm6dsr_spi_mode_get(const stmdev_ctx_t *ctx,
4354 lsm6dsr_sim_t *val)
4355 {
4356 lsm6dsr_ctrl3_c_t ctrl3_c;
4357 int32_t ret;
4358
4359 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4360 (uint8_t *)&ctrl3_c, 1);
4361
4362 switch (ctrl3_c.sim)
4363 {
4364 case LSM6DSR_SPI_4_WIRE:
4365 *val = LSM6DSR_SPI_4_WIRE;
4366 break;
4367
4368 case LSM6DSR_SPI_3_WIRE:
4369 *val = LSM6DSR_SPI_3_WIRE;
4370 break;
4371
4372 default:
4373 *val = LSM6DSR_SPI_4_WIRE;
4374 break;
4375 }
4376
4377 return ret;
4378 }
4379
4380 /**
4381 * @brief Disable / Enable I2C interface.[set]
4382 *
4383 * @param ctx Read / write interface definitions.(ptr)
4384 * @param val Change the values of i2c_disable in reg CTRL4_C
4385 * @retval Interface status (MANDATORY: return 0 -> no Error).
4386 *
4387 */
lsm6dsr_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dsr_i2c_disable_t val)4388 int32_t lsm6dsr_i2c_interface_set(const stmdev_ctx_t *ctx,
4389 lsm6dsr_i2c_disable_t val)
4390 {
4391 lsm6dsr_ctrl4_c_t ctrl4_c;
4392 int32_t ret;
4393
4394 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
4395 (uint8_t *)&ctrl4_c, 1);
4396
4397 if (ret == 0)
4398 {
4399 ctrl4_c.i2c_disable = (uint8_t)val;
4400 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C,
4401 (uint8_t *)&ctrl4_c, 1);
4402 }
4403
4404 return ret;
4405 }
4406
4407 /**
4408 * @brief Disable / Enable I2C interface.[get]
4409 *
4410 * @param ctx Read / write interface definitions.(ptr)
4411 * @param val Get the values of i2c reg CTRL4_C
4412 * @retval Interface status (MANDATORY: return 0 -> no Error).
4413 *
4414 */
lsm6dsr_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dsr_i2c_disable_t * val)4415 int32_t lsm6dsr_i2c_interface_get(const stmdev_ctx_t *ctx,
4416 lsm6dsr_i2c_disable_t *val)
4417 {
4418 lsm6dsr_ctrl4_c_t ctrl4_c;
4419 int32_t ret;
4420
4421 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
4422 (uint8_t *)&ctrl4_c, 1);
4423
4424 switch (ctrl4_c.i2c_disable)
4425 {
4426 case LSM6DSR_I2C_ENABLE:
4427 *val = LSM6DSR_I2C_ENABLE;
4428 break;
4429
4430 case LSM6DSR_I2C_DISABLE:
4431 *val = LSM6DSR_I2C_DISABLE;
4432 break;
4433
4434 default:
4435 *val = LSM6DSR_I2C_ENABLE;
4436 break;
4437 }
4438
4439 return ret;
4440 }
4441
4442 /**
4443 * @brief I3C Enable/Disable communication protocol.[set]
4444 *
4445 * @param ctx Read / write interface definitions.(ptr)
4446 * @param val Change the values of i3c_disable in reg CTRL9_XL
4447 * @retval Interface status (MANDATORY: return 0 -> no Error).
4448 *
4449 */
lsm6dsr_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dsr_i3c_disable_t val)4450 int32_t lsm6dsr_i3c_disable_set(const stmdev_ctx_t *ctx,
4451 lsm6dsr_i3c_disable_t val)
4452 {
4453 lsm6dsr_ctrl9_xl_t ctrl9_xl;
4454 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4455 int32_t ret;
4456
4457 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4458
4459 if (ret == 0)
4460 {
4461 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4462 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
4463 (uint8_t *)&ctrl9_xl, 1);
4464 }
4465
4466 if (ret == 0)
4467 {
4468 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4469 (uint8_t *)&i3c_bus_avb, 1);
4470 }
4471
4472 if (ret == 0)
4473 {
4474 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4475 ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4476 (uint8_t *)&i3c_bus_avb, 1);
4477 }
4478
4479 return ret;
4480 }
4481
4482 /**
4483 * @brief I3C Enable/Disable communication protocol.[get]
4484 *
4485 * @param ctx Read / write interface definitions.(ptr)
4486 * @param val Change the values of i3c_disable in reg CTRL9_XL
4487 * @retval Interface status (MANDATORY: return 0 -> no Error).
4488 *
4489 */
lsm6dsr_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dsr_i3c_disable_t * val)4490 int32_t lsm6dsr_i3c_disable_get(const stmdev_ctx_t *ctx,
4491 lsm6dsr_i3c_disable_t *val)
4492 {
4493 lsm6dsr_ctrl9_xl_t ctrl9_xl;
4494 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4495 int32_t ret;
4496
4497 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4498
4499 if (ret == 0)
4500 {
4501 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4502 (uint8_t *)&i3c_bus_avb, 1);
4503 }
4504
4505 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
4506 {
4507 case LSM6DSR_I3C_DISABLE:
4508 *val = LSM6DSR_I3C_DISABLE;
4509 break;
4510
4511 case LSM6DSR_I3C_ENABLE_T_50us:
4512 *val = LSM6DSR_I3C_ENABLE_T_50us;
4513 break;
4514
4515 case LSM6DSR_I3C_ENABLE_T_2us:
4516 *val = LSM6DSR_I3C_ENABLE_T_2us;
4517 break;
4518
4519 case LSM6DSR_I3C_ENABLE_T_1ms:
4520 *val = LSM6DSR_I3C_ENABLE_T_1ms;
4521 break;
4522
4523 case LSM6DSR_I3C_ENABLE_T_25ms:
4524 *val = LSM6DSR_I3C_ENABLE_T_25ms;
4525 break;
4526
4527 default:
4528 *val = LSM6DSR_I3C_DISABLE;
4529 break;
4530 }
4531
4532 return ret;
4533 }
4534
4535 /**
4536 * @}
4537 *
4538 */
4539
4540 /**
4541 * @defgroup LSM6DSR_interrupt_pins
4542 * @brief This section groups all the functions that manage
4543 * interrupt pins
4544 * @{
4545 *
4546 */
4547
4548 /**
4549 * @brief Select the signal that need to route on int1 pad[set]
4550 *
4551 * @param ctx Read / write interface definitions.(ptr)
4552 * @param val Structure of registers: INT1_CTRL,MD1_CFG,
4553 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
4554 * @retval Interface status (MANDATORY: return 0 -> no Error).
4555 *
4556 */
lsm6dsr_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsr_pin_int1_route_t * val)4557 int32_t lsm6dsr_pin_int1_route_set(const stmdev_ctx_t *ctx,
4558 lsm6dsr_pin_int1_route_t *val)
4559 {
4560 lsm6dsr_tap_cfg2_t tap_cfg2;
4561 int32_t ret;
4562
4563 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4564
4565 if (ret == 0)
4566 {
4567 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
4568 (uint8_t *)&val->emb_func_int1, 1);
4569 }
4570
4571 if (ret == 0)
4572 {
4573 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_A,
4574 (uint8_t *)&val->fsm_int1_a, 1);
4575 }
4576
4577 if (ret == 0)
4578 {
4579 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_B,
4580 (uint8_t *)&val->fsm_int1_b, 1);
4581 }
4582
4583 if (ret == 0)
4584 {
4585 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4586 }
4587
4588 if (ret == 0)
4589 {
4590 if ((val->emb_func_int1.int1_fsm_lc |
4591 val->emb_func_int1.int1_sig_mot |
4592 val->emb_func_int1.int1_step_detector |
4593 val->emb_func_int1.int1_tilt |
4594 val->fsm_int1_a.int1_fsm1 |
4595 val->fsm_int1_a.int1_fsm2 |
4596 val->fsm_int1_a.int1_fsm3 |
4597 val->fsm_int1_a.int1_fsm4 |
4598 val->fsm_int1_a.int1_fsm5 |
4599 val->fsm_int1_a.int1_fsm6 |
4600 val->fsm_int1_a.int1_fsm7 |
4601 val->fsm_int1_a.int1_fsm8 |
4602 val->fsm_int1_b.int1_fsm9 |
4603 val->fsm_int1_b.int1_fsm10 |
4604 val->fsm_int1_b.int1_fsm11 |
4605 val->fsm_int1_b.int1_fsm12 |
4606 val->fsm_int1_b.int1_fsm13 |
4607 val->fsm_int1_b.int1_fsm14 |
4608 val->fsm_int1_b.int1_fsm15 |
4609 val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
4610 {
4611 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
4612 }
4613 else
4614 {
4615 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
4616 }
4617
4618 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT1_CTRL,
4619 (uint8_t *)&val->int1_ctrl, 1);
4620 }
4621
4622 if (ret == 0)
4623 {
4624 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD1_CFG,
4625 (uint8_t *)&val->md1_cfg, 1);
4626 }
4627
4628 if (ret == 0)
4629 {
4630 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
4631 (uint8_t *)&tap_cfg2, 1);
4632
4633 if ((val->int1_ctrl.den_drdy_flag |
4634 val->int1_ctrl.int1_boot |
4635 val->int1_ctrl.int1_cnt_bdr |
4636 val->int1_ctrl.int1_drdy_g |
4637 val->int1_ctrl.int1_drdy_xl |
4638 val->int1_ctrl.int1_fifo_full |
4639 val->int1_ctrl.int1_fifo_ovr |
4640 val->int1_ctrl.int1_fifo_th |
4641 val->md1_cfg.int1_shub |
4642 val->md1_cfg.int1_6d |
4643 val->md1_cfg.int1_double_tap |
4644 val->md1_cfg.int1_ff |
4645 val->md1_cfg.int1_wu |
4646 val->md1_cfg.int1_single_tap |
4647 val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4648 {
4649 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4650 }
4651
4652 else
4653 {
4654 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4655 }
4656 }
4657
4658 if (ret == 0)
4659 {
4660 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
4661 (uint8_t *)&tap_cfg2, 1);
4662 }
4663
4664 return ret;
4665 }
4666
4667 /**
4668 * @brief Select the signal that need to route on int1 pad.[get]
4669 *
4670 * @param ctx Read / write interface definitions.(ptr)
4671 * @param val Structure of registers: INT1_CTRL, MD1_CFG,
4672 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B.(ptr)
4673 * @retval Interface status (MANDATORY: return 0 -> no Error).
4674 *
4675 */
lsm6dsr_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsr_pin_int1_route_t * val)4676 int32_t lsm6dsr_pin_int1_route_get(const stmdev_ctx_t *ctx,
4677 lsm6dsr_pin_int1_route_t *val)
4678 {
4679 int32_t ret;
4680
4681 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4682
4683 if (ret == 0)
4684 {
4685 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
4686 (uint8_t *)&val->emb_func_int1, 1);
4687 }
4688
4689 if (ret == 0)
4690 {
4691 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_A,
4692 (uint8_t *)&val->fsm_int1_a, 1);
4693 }
4694
4695 if (ret == 0)
4696 {
4697 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_B,
4698 (uint8_t *)&val->fsm_int1_b, 1);
4699 }
4700
4701 if (ret == 0)
4702 {
4703 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4704 }
4705
4706 if (ret == 0)
4707 {
4708 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT1_CTRL,
4709 (uint8_t *)&val->int1_ctrl, 1);
4710 }
4711
4712 if (ret == 0)
4713 {
4714 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD1_CFG,
4715 (uint8_t *)&val->md1_cfg, 1);
4716 }
4717
4718 return ret;
4719 }
4720
4721 /**
4722 * @brief Select the signal that need to route on int2 pad[set]
4723 *
4724 * @param ctx Read / write interface definitions.(ptr)
4725 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4726 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
4727 * @retval Interface status (MANDATORY: return 0 -> no Error).
4728 *
4729 */
lsm6dsr_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsr_pin_int2_route_t * val)4730 int32_t lsm6dsr_pin_int2_route_set(const stmdev_ctx_t *ctx,
4731 lsm6dsr_pin_int2_route_t *val)
4732 {
4733 lsm6dsr_tap_cfg2_t tap_cfg2;
4734 int32_t ret;
4735
4736 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4737
4738 if (ret == 0)
4739 {
4740 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
4741 (uint8_t *)&val->emb_func_int2, 1);
4742 }
4743
4744 if (ret == 0)
4745 {
4746 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_A,
4747 (uint8_t *)&val->fsm_int2_a, 1);
4748 }
4749
4750 if (ret == 0)
4751 {
4752 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_B,
4753 (uint8_t *)&val->fsm_int2_b, 1);
4754 }
4755
4756 if (ret == 0)
4757 {
4758 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4759 }
4760
4761 if (ret == 0)
4762 {
4763 if ((val->emb_func_int2.int2_step_detector |
4764 val->emb_func_int2.int2_tilt |
4765 val->emb_func_int2.int2_sig_mot |
4766 val->emb_func_int2.int2_fsm_lc |
4767 val->fsm_int2_a.int2_fsm1 |
4768 val->fsm_int2_a.int2_fsm2 |
4769 val->fsm_int2_a.int2_fsm3 |
4770 val->fsm_int2_a.int2_fsm4 |
4771 val->fsm_int2_a.int2_fsm5 |
4772 val->fsm_int2_a.int2_fsm6 |
4773 val->fsm_int2_a.int2_fsm7 |
4774 val->fsm_int2_a.int2_fsm8 |
4775 val->fsm_int2_b.int2_fsm9 |
4776 val->fsm_int2_b.int2_fsm10 |
4777 val->fsm_int2_b.int2_fsm11 |
4778 val->fsm_int2_b.int2_fsm12 |
4779 val->fsm_int2_b.int2_fsm13 |
4780 val->fsm_int2_b.int2_fsm14 |
4781 val->fsm_int2_b.int2_fsm15 |
4782 val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
4783 {
4784 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
4785 }
4786 else
4787 {
4788 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
4789 }
4790
4791 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT2_CTRL,
4792 (uint8_t *)&val->int2_ctrl, 1);
4793 }
4794
4795 if (ret == 0)
4796 {
4797 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD2_CFG,
4798 (uint8_t *)&val->md2_cfg, 1);
4799 }
4800
4801 if (ret == 0)
4802 {
4803 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
4804 (uint8_t *)&tap_cfg2, 1);
4805 }
4806
4807 if (ret == 0)
4808 {
4809 if ((val->int2_ctrl.int2_drdy_xl |
4810 val->int2_ctrl.int2_drdy_g |
4811 val->int2_ctrl.int2_drdy_temp |
4812 val->int2_ctrl.int2_fifo_th |
4813 val->int2_ctrl.int2_fifo_ovr |
4814 val->int2_ctrl.int2_fifo_full |
4815 val->int2_ctrl.int2_cnt_bdr |
4816 val->md2_cfg.int2_6d |
4817 val->md2_cfg.int2_double_tap |
4818 val->md2_cfg.int2_ff |
4819 val->md2_cfg.int2_wu |
4820 val->md2_cfg.int2_single_tap |
4821 val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
4822 {
4823 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4824 }
4825
4826 else
4827 {
4828 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4829 }
4830
4831 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
4832 (uint8_t *)&tap_cfg2, 1);
4833 }
4834
4835 return ret;
4836 }
4837
4838 /**
4839 * @brief Select the signal that need to route on int2 pad.[get]
4840 *
4841 * @param ctx Read / write interface definitions.(ptr)
4842 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4843 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B.[get]
4844 * @retval Interface status (MANDATORY: return 0 -> no Error).
4845 *
4846 */
lsm6dsr_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsr_pin_int2_route_t * val)4847 int32_t lsm6dsr_pin_int2_route_get(const stmdev_ctx_t *ctx,
4848 lsm6dsr_pin_int2_route_t *val)
4849 {
4850 int32_t ret;
4851
4852 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4853
4854 if (ret == 0)
4855 {
4856 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
4857 (uint8_t *)&val->emb_func_int2, 1);
4858 }
4859
4860 if (ret == 0)
4861 {
4862 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_A,
4863 (uint8_t *)&val->fsm_int2_a, 1);
4864 }
4865
4866 if (ret == 0)
4867 {
4868 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_B,
4869 (uint8_t *)&val->fsm_int2_b, 1);
4870 }
4871
4872 if (ret == 0)
4873 {
4874 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4875 }
4876
4877 if (ret == 0)
4878 {
4879 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT2_CTRL,
4880 (uint8_t *)&val->int2_ctrl, 1);
4881 }
4882
4883 if (ret == 0)
4884 {
4885 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD2_CFG,
4886 (uint8_t *)&val->md2_cfg, 1);
4887 }
4888
4889 return ret;
4890 }
4891
4892 /**
4893 * @brief Push-pull/open drain selection on interrupt pads.[set]
4894 *
4895 * @param ctx Read / write interface definitions.(ptr)
4896 * @param val Change the values of pp_od in reg CTRL3_C
4897 * @retval Interface status (MANDATORY: return 0 -> no Error).
4898 *
4899 */
lsm6dsr_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_pp_od_t val)4900 int32_t lsm6dsr_pin_mode_set(const stmdev_ctx_t *ctx,
4901 lsm6dsr_pp_od_t val)
4902 {
4903 lsm6dsr_ctrl3_c_t ctrl3_c;
4904 int32_t ret;
4905
4906 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4907 (uint8_t *)&ctrl3_c, 1);
4908
4909 if (ret == 0)
4910 {
4911 ctrl3_c.pp_od = (uint8_t)val;
4912 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
4913 (uint8_t *)&ctrl3_c, 1);
4914 }
4915
4916 return ret;
4917 }
4918
4919 /**
4920 * @brief Push-pull/open drain selection on interrupt pads.[get]
4921 *
4922 * @param ctx Read / write interface definitions.(ptr)
4923 * @param val Get the values of pp_od in reg CTRL3_C
4924 * @retval Interface status (MANDATORY: return 0 -> no Error).
4925 *
4926 */
lsm6dsr_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_pp_od_t * val)4927 int32_t lsm6dsr_pin_mode_get(const stmdev_ctx_t *ctx,
4928 lsm6dsr_pp_od_t *val)
4929 {
4930 lsm6dsr_ctrl3_c_t ctrl3_c;
4931 int32_t ret;
4932
4933 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4934 (uint8_t *)&ctrl3_c, 1);
4935
4936 switch (ctrl3_c.pp_od)
4937 {
4938 case LSM6DSR_PUSH_PULL:
4939 *val = LSM6DSR_PUSH_PULL;
4940 break;
4941
4942 case LSM6DSR_OPEN_DRAIN:
4943 *val = LSM6DSR_OPEN_DRAIN;
4944 break;
4945
4946 default:
4947 *val = LSM6DSR_PUSH_PULL;
4948 break;
4949 }
4950
4951 return ret;
4952 }
4953
4954 /**
4955 * @brief Interrupt active-high/low.[set]
4956 *
4957 * @param ctx Read / write interface definitions.(ptr)
4958 * @param val Change the values of h_lactive in reg CTRL3_C
4959 * @retval Interface status (MANDATORY: return 0 -> no Error).
4960 *
4961 */
lsm6dsr_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsr_h_lactive_t val)4962 int32_t lsm6dsr_pin_polarity_set(const stmdev_ctx_t *ctx,
4963 lsm6dsr_h_lactive_t val)
4964 {
4965 lsm6dsr_ctrl3_c_t ctrl3_c;
4966 int32_t ret;
4967
4968 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4969 (uint8_t *)&ctrl3_c, 1);
4970
4971 if (ret == 0)
4972 {
4973 ctrl3_c.h_lactive = (uint8_t)val;
4974 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C,
4975 (uint8_t *)&ctrl3_c, 1);
4976 }
4977
4978 return ret;
4979 }
4980
4981 /**
4982 * @brief Interrupt active-high/low.[get]
4983 *
4984 * @param ctx Read / write interface definitions.(ptr)
4985 * @param val Get the values of h_lactive in reg CTRL3_C
4986 * @retval Interface status (MANDATORY: return 0 -> no Error).
4987 *
4988 */
lsm6dsr_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsr_h_lactive_t * val)4989 int32_t lsm6dsr_pin_polarity_get(const stmdev_ctx_t *ctx,
4990 lsm6dsr_h_lactive_t *val)
4991 {
4992 lsm6dsr_ctrl3_c_t ctrl3_c;
4993 int32_t ret;
4994
4995 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C,
4996 (uint8_t *)&ctrl3_c, 1);
4997
4998 switch (ctrl3_c.h_lactive)
4999 {
5000 case LSM6DSR_ACTIVE_HIGH:
5001 *val = LSM6DSR_ACTIVE_HIGH;
5002 break;
5003
5004 case LSM6DSR_ACTIVE_LOW:
5005 *val = LSM6DSR_ACTIVE_LOW;
5006 break;
5007
5008 default:
5009 *val = LSM6DSR_ACTIVE_HIGH;
5010 break;
5011 }
5012
5013 return ret;
5014 }
5015
5016 /**
5017 * @brief All interrupt signals become available on INT1 pin.[set]
5018 *
5019 * @param ctx Read / write interface definitions.(ptr)
5020 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5021 * @retval Interface status (MANDATORY: return 0 -> no Error).
5022 *
5023 */
lsm6dsr_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)5024 int32_t lsm6dsr_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
5025 {
5026 lsm6dsr_ctrl4_c_t ctrl4_c;
5027 int32_t ret;
5028
5029 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
5030 (uint8_t *)&ctrl4_c, 1);
5031
5032 if (ret == 0)
5033 {
5034 ctrl4_c.int2_on_int1 = (uint8_t)val;
5035 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C,
5036 (uint8_t *)&ctrl4_c, 1);
5037 }
5038
5039 return ret;
5040 }
5041
5042 /**
5043 * @brief All interrupt signals become available on INT1 pin.[get]
5044 *
5045 * @param ctx Read / write interface definitions.(ptr)
5046 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5047 * @retval Interface status (MANDATORY: return 0 -> no Error).
5048 *
5049 */
lsm6dsr_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)5050 int32_t lsm6dsr_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5051 {
5052 lsm6dsr_ctrl4_c_t ctrl4_c;
5053 int32_t ret;
5054
5055 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
5056 (uint8_t *)&ctrl4_c, 1);
5057 *val = ctrl4_c.int2_on_int1;
5058
5059 return ret;
5060 }
5061
5062 /**
5063 * @brief All interrupt signals notification mode.[set]
5064 *
5065 * @param ctx Read / write interface definitions.(ptr)
5066 * @param val Change the values of lir in reg TAP_CFG0
5067 * @retval Interface status (MANDATORY: return 0 -> no Error).
5068 *
5069 */
lsm6dsr_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsr_lir_t val)5070 int32_t lsm6dsr_int_notification_set(const stmdev_ctx_t *ctx,
5071 lsm6dsr_lir_t val)
5072 {
5073 lsm6dsr_tap_cfg0_t tap_cfg0;
5074 lsm6dsr_page_rw_t page_rw;
5075 int32_t ret;
5076
5077 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5078 (uint8_t *)&tap_cfg0, 1);
5079
5080 if (ret == 0)
5081 {
5082 tap_cfg0.lir = (uint8_t)val & 0x01U;
5083 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
5084 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5085 (uint8_t *)&tap_cfg0, 1);
5086 }
5087
5088 if (ret == 0)
5089 {
5090 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
5091 }
5092
5093 if (ret == 0)
5094 {
5095 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
5096 (uint8_t *)&page_rw, 1);
5097 }
5098
5099 if (ret == 0)
5100 {
5101 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
5102 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW,
5103 (uint8_t *)&page_rw, 1);
5104 }
5105
5106 if (ret == 0)
5107 {
5108 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
5109 }
5110
5111 return ret;
5112 }
5113
5114 /**
5115 * @brief All interrupt signals notification mode.[get]
5116 *
5117 * @param ctx Read / write interface definitions.(ptr)
5118 * @param val Get the values of lir in reg TAP_CFG0
5119 * @retval Interface status (MANDATORY: return 0 -> no Error).
5120 *
5121 */
lsm6dsr_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsr_lir_t * val)5122 int32_t lsm6dsr_int_notification_get(const stmdev_ctx_t *ctx,
5123 lsm6dsr_lir_t *val)
5124 {
5125 lsm6dsr_tap_cfg0_t tap_cfg0;
5126 lsm6dsr_page_rw_t page_rw;
5127 int32_t ret;
5128
5129 *val = LSM6DSR_ALL_INT_PULSED;
5130 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5131 (uint8_t *)&tap_cfg0, 1);
5132
5133 if (ret == 0)
5134 {
5135 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
5136 }
5137
5138 if (ret == 0)
5139 {
5140 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW,
5141 (uint8_t *)&page_rw, 1);
5142 }
5143
5144 if (ret == 0)
5145 {
5146 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
5147 }
5148
5149 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
5150 {
5151 case LSM6DSR_ALL_INT_PULSED:
5152 *val = LSM6DSR_ALL_INT_PULSED;
5153 break;
5154
5155 case LSM6DSR_BASE_LATCHED_EMB_PULSED:
5156 *val = LSM6DSR_BASE_LATCHED_EMB_PULSED;
5157 break;
5158
5159 case LSM6DSR_BASE_PULSED_EMB_LATCHED:
5160 *val = LSM6DSR_BASE_PULSED_EMB_LATCHED;
5161 break;
5162
5163 case LSM6DSR_ALL_INT_LATCHED:
5164 *val = LSM6DSR_ALL_INT_LATCHED;
5165 break;
5166
5167 default:
5168 *val = LSM6DSR_ALL_INT_PULSED;
5169 break;
5170 }
5171
5172 return ret;
5173 }
5174
5175 /**
5176 * @}
5177 *
5178 */
5179
5180 /**
5181 * @defgroup LSM6DSR_Wake_Up_event
5182 * @brief This section groups all the functions that manage the
5183 * Wake Up event generation.
5184 * @{
5185 *
5186 */
5187
5188 /**
5189 * @brief Weight of 1 LSB of wakeup threshold.[set]
5190 * 0: 1 LSB =FS_XL / 64
5191 * 1: 1 LSB = FS_XL / 256
5192 *
5193 * @param ctx Read / write interface definitions.(ptr)
5194 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
5195 * @retval Interface status (MANDATORY: return 0 -> no Error).
5196 *
5197 */
lsm6dsr_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dsr_wake_ths_w_t val)5198 int32_t lsm6dsr_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
5199 lsm6dsr_wake_ths_w_t val)
5200 {
5201 lsm6dsr_wake_up_dur_t wake_up_dur;
5202 int32_t ret;
5203
5204 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5205 (uint8_t *)&wake_up_dur, 1);
5206
5207 if (ret == 0)
5208 {
5209 wake_up_dur.wake_ths_w = (uint8_t)val;
5210 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5211 (uint8_t *)&wake_up_dur, 1);
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief Weight of 1 LSB of wakeup threshold.[get]
5219 * 0: 1 LSB =FS_XL / 64
5220 * 1: 1 LSB = FS_XL / 256
5221 *
5222 * @param ctx Read / write interface definitions.(ptr)
5223 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
5224 * @retval Interface status (MANDATORY: return 0 -> no Error).
5225 *
5226 */
lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dsr_wake_ths_w_t * val)5227 int32_t lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
5228 lsm6dsr_wake_ths_w_t *val)
5229 {
5230 lsm6dsr_wake_up_dur_t wake_up_dur;
5231 int32_t ret;
5232
5233 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5234 (uint8_t *)&wake_up_dur, 1);
5235
5236 switch (wake_up_dur.wake_ths_w)
5237 {
5238 case LSM6DSR_LSb_FS_DIV_64:
5239 *val = LSM6DSR_LSb_FS_DIV_64;
5240 break;
5241
5242 case LSM6DSR_LSb_FS_DIV_256:
5243 *val = LSM6DSR_LSb_FS_DIV_256;
5244 break;
5245
5246 default:
5247 *val = LSM6DSR_LSb_FS_DIV_64;
5248 break;
5249 }
5250
5251 return ret;
5252 }
5253
5254 /**
5255 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5256 * WAKE_UP_DUR.[set]
5257 *
5258 * @param ctx Read / write interface definitions.(ptr)
5259 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5260 * @retval Interface status (MANDATORY: return 0 -> no Error).
5261 *
5262 */
lsm6dsr_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)5263 int32_t lsm6dsr_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
5264 {
5265 lsm6dsr_wake_up_ths_t wake_up_ths;
5266 int32_t ret;
5267
5268 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5269 (uint8_t *)&wake_up_ths, 1);
5270
5271 if (ret == 0)
5272 {
5273 wake_up_ths.wk_ths = (uint8_t)val;
5274 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
5275 (uint8_t *)&wake_up_ths, 1);
5276 }
5277
5278 return ret;
5279 }
5280
5281 /**
5282 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5283 * WAKE_UP_DUR.[get]
5284 *
5285 * @param ctx Read / write interface definitions.(ptr)
5286 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5287 * @retval Interface status (MANDATORY: return 0 -> no Error).
5288 *
5289 */
lsm6dsr_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)5290 int32_t lsm6dsr_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
5291 {
5292 lsm6dsr_wake_up_ths_t wake_up_ths;
5293 int32_t ret;
5294
5295 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5296 (uint8_t *)&wake_up_ths, 1);
5297 *val = wake_up_ths.wk_ths;
5298
5299 return ret;
5300 }
5301
5302 /**
5303 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
5304 *
5305 * @param ctx Read / write interface definitions.(ptr)
5306 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5307 * @retval Interface status (MANDATORY: return 0 -> no Error).
5308 *
5309 */
lsm6dsr_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)5310 int32_t lsm6dsr_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
5311 uint8_t val)
5312 {
5313 lsm6dsr_wake_up_ths_t wake_up_ths;
5314 int32_t ret;
5315
5316 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5317 (uint8_t *)&wake_up_ths, 1);
5318
5319 if (ret == 0)
5320 {
5321 wake_up_ths.usr_off_on_wu = (uint8_t)val;
5322 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
5323 (uint8_t *)&wake_up_ths, 1);
5324 }
5325
5326 return ret;
5327 }
5328
5329 /**
5330 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
5331 *
5332 * @param ctx Read / write interface definitions.(ptr)
5333 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5334 * @retval Interface status (MANDATORY: return 0 -> no Error).
5335 *
5336 */
lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)5337 int32_t lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
5338 uint8_t *val)
5339 {
5340 lsm6dsr_wake_up_ths_t wake_up_ths;
5341 int32_t ret;
5342
5343 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5344 (uint8_t *)&wake_up_ths, 1);
5345 *val = wake_up_ths.usr_off_on_wu;
5346
5347 return ret;
5348 }
5349
5350 /**
5351 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
5352 *
5353 * @param ctx Read / write interface definitions.(ptr)
5354 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5355 * @retval Interface status (MANDATORY: return 0 -> no Error).
5356 *
5357 */
lsm6dsr_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5358 int32_t lsm6dsr_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5359 {
5360 lsm6dsr_wake_up_dur_t wake_up_dur;
5361 int32_t ret;
5362
5363 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5364 (uint8_t *)&wake_up_dur, 1);
5365
5366 if (ret == 0)
5367 {
5368 wake_up_dur.wake_dur = (uint8_t)val;
5369 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5370 (uint8_t *)&wake_up_dur, 1);
5371 }
5372
5373 return ret;
5374 }
5375
5376 /**
5377 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
5378 *
5379 * @param ctx Read / write interface definitions.(ptr)
5380 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5381 * @retval Interface status (MANDATORY: return 0 -> no Error).
5382 *
5383 */
lsm6dsr_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5384 int32_t lsm6dsr_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5385 {
5386 lsm6dsr_wake_up_dur_t wake_up_dur;
5387 int32_t ret;
5388
5389 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5390 (uint8_t *)&wake_up_dur, 1);
5391 *val = wake_up_dur.wake_dur;
5392
5393 return ret;
5394 }
5395
5396 /**
5397 * @}
5398 *
5399 */
5400
5401 /**
5402 * @defgroup LSM6DSR_ Activity/Inactivity_detection
5403 * @brief This section groups all the functions concerning
5404 * activity/inactivity detection.
5405 * @{
5406 *
5407 */
5408
5409 /**
5410 * @brief Enables gyroscope Sleep mode.[set]
5411 *
5412 * @param ctx Read / write interface definitions.(ptr)
5413 * @param val Change the values of sleep_g in reg CTRL4_C
5414 * @retval Interface status (MANDATORY: return 0 -> no Error).
5415 *
5416 */
lsm6dsr_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5417 int32_t lsm6dsr_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5418 {
5419 lsm6dsr_ctrl4_c_t ctrl4_c;
5420 int32_t ret;
5421
5422 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
5423 (uint8_t *)&ctrl4_c, 1);
5424
5425 if (ret == 0)
5426 {
5427 ctrl4_c.sleep_g = (uint8_t)val;
5428 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C,
5429 (uint8_t *)&ctrl4_c, 1);
5430 }
5431
5432 return ret;
5433 }
5434
5435 /**
5436 * @brief Enables gyroscope Sleep mode.[get]
5437 *
5438 * @param ctx Read / write interface definitions.(ptr)
5439 * @param val Change the values of sleep_g in reg CTRL4_C
5440 * @retval Interface status (MANDATORY: return 0 -> no Error).
5441 *
5442 */
lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5443 int32_t lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5444 {
5445 lsm6dsr_ctrl4_c_t ctrl4_c;
5446 int32_t ret;
5447
5448 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C,
5449 (uint8_t *)&ctrl4_c, 1);
5450 *val = ctrl4_c.sleep_g;
5451
5452 return ret;
5453 }
5454
5455 /**
5456 * @brief Drives the sleep status instead of sleep change on INT pins
5457 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5458 * are enabled).[set]
5459 *
5460 * @param ctx Read / write interface definitions.(ptr)
5461 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
5462 * @retval Interface status (MANDATORY: return 0 -> no Error).
5463 *
5464 */
lsm6dsr_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dsr_sleep_status_on_int_t val)5465 int32_t lsm6dsr_act_pin_notification_set(const stmdev_ctx_t *ctx,
5466 lsm6dsr_sleep_status_on_int_t val)
5467 {
5468 lsm6dsr_tap_cfg0_t tap_cfg0;
5469 int32_t ret;
5470
5471 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5472 (uint8_t *)&tap_cfg0, 1);
5473
5474 if (ret == 0)
5475 {
5476 tap_cfg0. sleep_status_on_int = (uint8_t)val;
5477 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5478 (uint8_t *)&tap_cfg0, 1);
5479 }
5480
5481 return ret;
5482 }
5483
5484 /**
5485 * @brief Drives the sleep status instead of sleep change on INT pins
5486 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5487 * are enabled).[get]
5488 *
5489 * @param ctx Read / write interface definitions.(ptr)
5490 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5491 * @retval Interface status (MANDATORY: return 0 -> no Error).
5492 *
5493 */
lsm6dsr_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dsr_sleep_status_on_int_t * val)5494 int32_t lsm6dsr_act_pin_notification_get(const stmdev_ctx_t *ctx,
5495 lsm6dsr_sleep_status_on_int_t *val)
5496 {
5497 lsm6dsr_tap_cfg0_t tap_cfg0;
5498 int32_t ret;
5499
5500 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5501 (uint8_t *)&tap_cfg0, 1);
5502
5503 switch (tap_cfg0. sleep_status_on_int)
5504 {
5505 case LSM6DSR_DRIVE_SLEEP_CHG_EVENT:
5506 *val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
5507 break;
5508
5509 case LSM6DSR_DRIVE_SLEEP_STATUS:
5510 *val = LSM6DSR_DRIVE_SLEEP_STATUS;
5511 break;
5512
5513 default:
5514 *val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
5515 break;
5516 }
5517
5518 return ret;
5519 }
5520
5521 /**
5522 * @brief Enable inactivity function.[set]
5523 *
5524 * @param ctx Read / write interface definitions.(ptr)
5525 * @param val Change the values of inact_en in reg TAP_CFG2
5526 * @retval Interface status (MANDATORY: return 0 -> no Error).
5527 *
5528 */
lsm6dsr_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_inact_en_t val)5529 int32_t lsm6dsr_act_mode_set(const stmdev_ctx_t *ctx,
5530 lsm6dsr_inact_en_t val)
5531 {
5532 lsm6dsr_tap_cfg2_t tap_cfg2;
5533 int32_t ret;
5534
5535 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
5536 (uint8_t *)&tap_cfg2, 1);
5537
5538 if (ret == 0)
5539 {
5540 tap_cfg2.inact_en = (uint8_t)val;
5541 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
5542 (uint8_t *)&tap_cfg2, 1);
5543 }
5544
5545 return ret;
5546 }
5547
5548 /**
5549 * @brief Enable inactivity function.[get]
5550 *
5551 * @param ctx Read / write interface definitions.(ptr)
5552 * @param val Get the values of inact_en in reg TAP_CFG2
5553 * @retval Interface status (MANDATORY: return 0 -> no Error).
5554 *
5555 */
lsm6dsr_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_inact_en_t * val)5556 int32_t lsm6dsr_act_mode_get(const stmdev_ctx_t *ctx,
5557 lsm6dsr_inact_en_t *val)
5558 {
5559 lsm6dsr_tap_cfg2_t tap_cfg2;
5560 int32_t ret;
5561
5562 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
5563 (uint8_t *)&tap_cfg2, 1);
5564
5565 switch (tap_cfg2.inact_en)
5566 {
5567 case LSM6DSR_XL_AND_GY_NOT_AFFECTED:
5568 *val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
5569 break;
5570
5571 case LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED:
5572 *val = LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED;
5573 break;
5574
5575 case LSM6DSR_XL_12Hz5_GY_SLEEP:
5576 *val = LSM6DSR_XL_12Hz5_GY_SLEEP;
5577 break;
5578
5579 case LSM6DSR_XL_12Hz5_GY_PD:
5580 *val = LSM6DSR_XL_12Hz5_GY_PD;
5581 break;
5582
5583 default:
5584 *val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
5585 break;
5586 }
5587
5588 return ret;
5589 }
5590
5591 /**
5592 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
5593 *
5594 * @param ctx Read / write interface definitions.(ptr)
5595 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5596 * @retval Interface status (MANDATORY: return 0 -> no Error).
5597 *
5598 */
lsm6dsr_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5599 int32_t lsm6dsr_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5600 {
5601 lsm6dsr_wake_up_dur_t wake_up_dur;
5602 int32_t ret;
5603
5604 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5605 (uint8_t *)&wake_up_dur, 1);
5606
5607 if (ret == 0)
5608 {
5609 wake_up_dur.sleep_dur = (uint8_t)val;
5610 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5611 (uint8_t *)&wake_up_dur, 1);
5612 }
5613
5614 return ret;
5615 }
5616
5617 /**
5618 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
5619 *
5620 * @param ctx Read / write interface definitions.(ptr)
5621 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5622 * @retval Interface status (MANDATORY: return 0 -> no Error).
5623 *
5624 */
lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5625 int32_t lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5626 {
5627 lsm6dsr_wake_up_dur_t wake_up_dur;
5628 int32_t ret;
5629
5630 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5631 (uint8_t *)&wake_up_dur, 1);
5632 *val = wake_up_dur.sleep_dur;
5633
5634 return ret;
5635 }
5636
5637 /**
5638 * @}
5639 *
5640 */
5641
5642 /**
5643 * @defgroup LSM6DSR_tap_generator
5644 * @brief This section groups all the functions that manage the
5645 * tap and double tap event generation.
5646 * @{
5647 *
5648 */
5649
5650 /**
5651 * @brief Enable Z direction in tap recognition.[set]
5652 *
5653 * @param ctx Read / write interface definitions.(ptr)
5654 * @param val Change the values of tap_z_en in reg TAP_CFG0
5655 * @retval Interface status (MANDATORY: return 0 -> no Error).
5656 *
5657 */
lsm6dsr_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)5658 int32_t lsm6dsr_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
5659 uint8_t val)
5660 {
5661 lsm6dsr_tap_cfg0_t tap_cfg0;
5662 int32_t ret;
5663
5664 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5665 (uint8_t *)&tap_cfg0, 1);
5666
5667 if (ret == 0)
5668 {
5669 tap_cfg0.tap_z_en = (uint8_t)val;
5670 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5671 (uint8_t *)&tap_cfg0, 1);
5672 }
5673
5674 return ret;
5675 }
5676
5677 /**
5678 * @brief Enable Z direction in tap recognition.[get]
5679 *
5680 * @param ctx Read / write interface definitions.(ptr)
5681 * @param val Change the values of tap_z_en in reg TAP_CFG0
5682 * @retval Interface status (MANDATORY: return 0 -> no Error).
5683 *
5684 */
lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5685 int32_t lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
5686 uint8_t *val)
5687 {
5688 lsm6dsr_tap_cfg0_t tap_cfg0;
5689 int32_t ret;
5690
5691 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5692 (uint8_t *)&tap_cfg0, 1);
5693 *val = tap_cfg0.tap_z_en;
5694
5695 return ret;
5696 }
5697
5698 /**
5699 * @brief Enable Y direction in tap recognition.[set]
5700 *
5701 * @param ctx Read / write interface definitions.(ptr)
5702 * @param val Change the values of tap_y_en in reg TAP_CFG0
5703 * @retval Interface status (MANDATORY: return 0 -> no Error).
5704 *
5705 */
lsm6dsr_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)5706 int32_t lsm6dsr_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
5707 uint8_t val)
5708 {
5709 lsm6dsr_tap_cfg0_t tap_cfg0;
5710 int32_t ret;
5711
5712 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5713 (uint8_t *)&tap_cfg0, 1);
5714
5715 if (ret == 0)
5716 {
5717 tap_cfg0.tap_y_en = (uint8_t)val;
5718 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5719 (uint8_t *)&tap_cfg0, 1);
5720 }
5721
5722 return ret;
5723 }
5724
5725 /**
5726 * @brief Enable Y direction in tap recognition.[get]
5727 *
5728 * @param ctx Read / write interface definitions.(ptr)
5729 * @param val Change the values of tap_y_en in reg TAP_CFG0
5730 * @retval Interface status (MANDATORY: return 0 -> no Error).
5731 *
5732 */
lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5733 int32_t lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
5734 uint8_t *val)
5735 {
5736 lsm6dsr_tap_cfg0_t tap_cfg0;
5737 int32_t ret;
5738
5739 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5740 (uint8_t *)&tap_cfg0, 1);
5741 *val = tap_cfg0.tap_y_en;
5742
5743 return ret;
5744 }
5745
5746 /**
5747 * @brief Enable X direction in tap recognition.[set]
5748 *
5749 * @param ctx Read / write interface definitions.(ptr)
5750 * @param val Change the values of tap_x_en in reg TAP_CFG0
5751 * @retval Interface status (MANDATORY: return 0 -> no Error).
5752 *
5753 */
lsm6dsr_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)5754 int32_t lsm6dsr_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
5755 uint8_t val)
5756 {
5757 lsm6dsr_tap_cfg0_t tap_cfg0;
5758 int32_t ret;
5759
5760 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5761 (uint8_t *)&tap_cfg0, 1);
5762
5763 if (ret == 0)
5764 {
5765 tap_cfg0.tap_x_en = (uint8_t)val;
5766 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5767 (uint8_t *)&tap_cfg0, 1);
5768 }
5769
5770 return ret;
5771 }
5772
5773 /**
5774 * @brief Enable X direction in tap recognition.[get]
5775 *
5776 * @param ctx Read / write interface definitions.(ptr)
5777 * @param val Change the values of tap_x_en in reg TAP_CFG0
5778 * @retval Interface status (MANDATORY: return 0 -> no Error).
5779 *
5780 */
lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5781 int32_t lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
5782 uint8_t *val)
5783 {
5784 lsm6dsr_tap_cfg0_t tap_cfg0;
5785 int32_t ret;
5786
5787 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0,
5788 (uint8_t *)&tap_cfg0, 1);
5789 *val = tap_cfg0.tap_x_en;
5790
5791 return ret;
5792 }
5793
5794 /**
5795 * @brief X-axis tap recognition threshold.[set]
5796 *
5797 * @param ctx Read / write interface definitions.(ptr)
5798 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5799 * @retval Interface status (MANDATORY: return 0 -> no Error).
5800 *
5801 */
lsm6dsr_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)5802 int32_t lsm6dsr_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5803 {
5804 lsm6dsr_tap_cfg1_t tap_cfg1;
5805 int32_t ret;
5806
5807 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1,
5808 (uint8_t *)&tap_cfg1, 1);
5809
5810 if (ret == 0)
5811 {
5812 tap_cfg1.tap_ths_x = (uint8_t)val;
5813 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1,
5814 (uint8_t *)&tap_cfg1, 1);
5815 }
5816
5817 return ret;
5818 }
5819
5820 /**
5821 * @brief X-axis tap recognition threshold.[get]
5822 *
5823 * @param ctx Read / write interface definitions.(ptr)
5824 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5825 * @retval Interface status (MANDATORY: return 0 -> no Error).
5826 *
5827 */
lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5828 int32_t lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t *ctx,
5829 uint8_t *val)
5830 {
5831 lsm6dsr_tap_cfg1_t tap_cfg1;
5832 int32_t ret;
5833
5834 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1,
5835 (uint8_t *)&tap_cfg1, 1);
5836 *val = tap_cfg1.tap_ths_x;
5837
5838 return ret;
5839 }
5840
5841 /**
5842 * @brief Selection of axis priority for TAP detection.[set]
5843 *
5844 * @param ctx Read / write interface definitions.(ptr)
5845 * @param val Change the values of tap_priority in reg TAP_CFG1
5846 * @retval Interface status (MANDATORY: return 0 -> no Error).
5847 *
5848 */
lsm6dsr_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsr_tap_priority_t val)5849 int32_t lsm6dsr_tap_axis_priority_set(const stmdev_ctx_t *ctx,
5850 lsm6dsr_tap_priority_t val)
5851 {
5852 lsm6dsr_tap_cfg1_t tap_cfg1;
5853 int32_t ret;
5854
5855 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1,
5856 (uint8_t *)&tap_cfg1, 1);
5857
5858 if (ret == 0)
5859 {
5860 tap_cfg1.tap_priority = (uint8_t)val;
5861 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1,
5862 (uint8_t *)&tap_cfg1, 1);
5863 }
5864
5865 return ret;
5866 }
5867
5868 /**
5869 * @brief Selection of axis priority for TAP detection[get]
5870 *
5871 * @param ctx Read / write interface definitions.(ptr)
5872 * @param val Get the values of tap_priority in reg TAP_CFG1
5873 * @retval Interface status (MANDATORY: return 0 -> no Error).
5874 *
5875 */
lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsr_tap_priority_t * val)5876 int32_t lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t *ctx,
5877 lsm6dsr_tap_priority_t *val)
5878 {
5879 lsm6dsr_tap_cfg1_t tap_cfg1;
5880 int32_t ret;
5881
5882 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1,
5883 (uint8_t *)&tap_cfg1, 1);
5884
5885 switch (tap_cfg1.tap_priority)
5886 {
5887 case LSM6DSR_XYZ:
5888 *val = LSM6DSR_XYZ;
5889 break;
5890
5891 case LSM6DSR_YXZ:
5892 *val = LSM6DSR_YXZ;
5893 break;
5894
5895 case LSM6DSR_XZY:
5896 *val = LSM6DSR_XZY;
5897 break;
5898
5899 case LSM6DSR_ZYX:
5900 *val = LSM6DSR_ZYX;
5901 break;
5902
5903 case LSM6DSR_YZX:
5904 *val = LSM6DSR_YZX;
5905 break;
5906
5907 case LSM6DSR_ZXY:
5908 *val = LSM6DSR_ZXY;
5909 break;
5910
5911 default:
5912 *val = LSM6DSR_XYZ;
5913 break;
5914 }
5915
5916 return ret;
5917 }
5918
5919 /**
5920 * @brief Y-axis tap recognition threshold.[set]
5921 *
5922 * @param ctx Read / write interface definitions.(ptr)
5923 * @param val Change the values of tap_ths_y in reg TAP_CFG2
5924 * @retval Interface status (MANDATORY: return 0 -> no Error).
5925 *
5926 */
lsm6dsr_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)5927 int32_t lsm6dsr_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5928 {
5929 lsm6dsr_tap_cfg2_t tap_cfg2;
5930 int32_t ret;
5931
5932 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
5933 (uint8_t *)&tap_cfg2, 1);
5934
5935 if (ret == 0)
5936 {
5937 tap_cfg2.tap_ths_y = (uint8_t)val;
5938 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
5939 (uint8_t *)&tap_cfg2, 1);
5940 }
5941
5942 return ret;
5943 }
5944
5945 /**
5946 * @brief Y-axis tap recognition threshold.[get]
5947 *
5948 * @param ctx Read / write interface definitions.(ptr)
5949 * @param val Change the values of tap_ths_y in reg TAP_CFG2
5950 * @retval Interface status (MANDATORY: return 0 -> no Error).
5951 *
5952 */
lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5953 int32_t lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t *ctx,
5954 uint8_t *val)
5955 {
5956 lsm6dsr_tap_cfg2_t tap_cfg2;
5957 int32_t ret;
5958
5959 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
5960 (uint8_t *)&tap_cfg2, 1);
5961 *val = tap_cfg2.tap_ths_y;
5962
5963 return ret;
5964 }
5965
5966 /**
5967 * @brief Z-axis recognition threshold.[set]
5968 *
5969 * @param ctx Read / write interface definitions.(ptr)
5970 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
5971 * @retval Interface status (MANDATORY: return 0 -> no Error).
5972 *
5973 */
lsm6dsr_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)5974 int32_t lsm6dsr_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5975 {
5976 lsm6dsr_tap_ths_6d_t tap_ths_6d;
5977 int32_t ret;
5978
5979 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
5980 (uint8_t *)&tap_ths_6d, 1);
5981
5982 if (ret == 0)
5983 {
5984 tap_ths_6d.tap_ths_z = (uint8_t)val;
5985 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
5986 (uint8_t *)&tap_ths_6d, 1);
5987 }
5988
5989 return ret;
5990 }
5991
5992 /**
5993 * @brief Z-axis recognition threshold.[get]
5994 *
5995 * @param ctx Read / write interface definitions.(ptr)
5996 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
5997 * @retval Interface status (MANDATORY: return 0 -> no Error).
5998 *
5999 */
lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6000 int32_t lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t *ctx,
6001 uint8_t *val)
6002 {
6003 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6004 int32_t ret;
6005
6006 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6007 (uint8_t *)&tap_ths_6d, 1);
6008 *val = tap_ths_6d.tap_ths_z;
6009
6010 return ret;
6011 }
6012
6013 /**
6014 * @brief Maximum duration is the maximum time of an overthreshold signal
6015 * detection to be recognized as a tap event. The default value of
6016 * these bits is 00b which corresponds to 4*ODR_XL time.
6017 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6018 * corresponds to 8*ODR_XL time.[set]
6019 *
6020 * @param ctx Read / write interface definitions.(ptr)
6021 * @param val Change the values of shock in reg INT_DUR2
6022 * @retval Interface status (MANDATORY: return 0 -> no Error).
6023 *
6024 */
lsm6dsr_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)6025 int32_t lsm6dsr_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
6026 {
6027 lsm6dsr_int_dur2_t int_dur2;
6028 int32_t ret;
6029
6030 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6031 (uint8_t *)&int_dur2, 1);
6032
6033 if (ret == 0)
6034 {
6035 int_dur2.shock = (uint8_t)val;
6036 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
6037 (uint8_t *)&int_dur2, 1);
6038 }
6039
6040 return ret;
6041 }
6042
6043 /**
6044 * @brief Maximum duration is the maximum time of an overthreshold signal
6045 * detection to be recognized as a tap event. The default value of
6046 * these bits is 00b which corresponds to 4*ODR_XL time.
6047 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6048 * corresponds to 8*ODR_XL time.[get]
6049 *
6050 * @param ctx Read / write interface definitions.(ptr)
6051 * @param val Change the values of shock in reg INT_DUR2
6052 * @retval Interface status (MANDATORY: return 0 -> no Error).
6053 *
6054 */
lsm6dsr_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)6055 int32_t lsm6dsr_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
6056 {
6057 lsm6dsr_int_dur2_t int_dur2;
6058 int32_t ret;
6059
6060 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6061 (uint8_t *)&int_dur2, 1);
6062 *val = int_dur2.shock;
6063
6064 return ret;
6065 }
6066
6067 /**
6068 * @brief Quiet time is the time after the first detected tap in which
6069 * there must not be any overthreshold event.
6070 * The default value of these bits is 00b which corresponds to
6071 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6072 * value, 1LSB corresponds to 4*ODR_XL time.[set]
6073 *
6074 * @param ctx Read / write interface definitions.(ptr)
6075 * @param val Change the values of quiet in reg INT_DUR2
6076 * @retval Interface status (MANDATORY: return 0 -> no Error).
6077 *
6078 */
lsm6dsr_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)6079 int32_t lsm6dsr_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
6080 {
6081 lsm6dsr_int_dur2_t int_dur2;
6082 int32_t ret;
6083
6084 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6085 (uint8_t *)&int_dur2, 1);
6086
6087 if (ret == 0)
6088 {
6089 int_dur2.quiet = (uint8_t)val;
6090 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
6091 (uint8_t *)&int_dur2, 1);
6092 }
6093
6094 return ret;
6095 }
6096
6097 /**
6098 * @brief Quiet time is the time after the first detected tap in which
6099 * there must not be any overthreshold event.
6100 * The default value of these bits is 00b which corresponds to
6101 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6102 * value, 1LSB corresponds to 4*ODR_XL time.[get]
6103 *
6104 * @param ctx Read / write interface definitions.(ptr)
6105 * @param val Change the values of quiet in reg INT_DUR2
6106 * @retval Interface status (MANDATORY: return 0 -> no Error).
6107 *
6108 */
lsm6dsr_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)6109 int32_t lsm6dsr_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
6110 {
6111 lsm6dsr_int_dur2_t int_dur2;
6112 int32_t ret;
6113
6114 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6115 (uint8_t *)&int_dur2, 1);
6116 *val = int_dur2.quiet;
6117
6118 return ret;
6119 }
6120
6121 /**
6122 * @brief When double tap recognition is enabled, this register expresses
6123 * the maximum time between two consecutive detected taps to
6124 * determine a double tap event.
6125 * The default value of these bits is 0000b which corresponds to
6126 * 16*ODR_XL time.
6127 * If the DUR[3:0] bits are set to a different value, 1LSB
6128 * corresponds to 32*ODR_XL time.[set]
6129 *
6130 * @param ctx Read / write interface definitions.(ptr)
6131 * @param val Change the values of dur in reg INT_DUR2
6132 * @retval Interface status (MANDATORY: return 0 -> no Error).
6133 *
6134 */
lsm6dsr_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6135 int32_t lsm6dsr_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6136 {
6137 lsm6dsr_int_dur2_t int_dur2;
6138 int32_t ret;
6139
6140 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6141 (uint8_t *)&int_dur2, 1);
6142
6143 if (ret == 0)
6144 {
6145 int_dur2.dur = (uint8_t)val;
6146 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
6147 (uint8_t *)&int_dur2, 1);
6148 }
6149
6150 return ret;
6151 }
6152
6153 /**
6154 * @brief When double tap recognition is enabled, this register expresses the
6155 * maximum time between two consecutive detected taps to determine
6156 * a double tap event. The default value of these bits is 0000b which
6157 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
6158 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
6159 *
6160 * @param ctx Read / write interface definitions.(ptr)
6161 * @param val Change the values of dur in reg INT_DUR2
6162 * @retval Interface status (MANDATORY: return 0 -> no Error).
6163 *
6164 */
lsm6dsr_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6165 int32_t lsm6dsr_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6166 {
6167 lsm6dsr_int_dur2_t int_dur2;
6168 int32_t ret;
6169
6170 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2,
6171 (uint8_t *)&int_dur2, 1);
6172 *val = int_dur2.dur;
6173
6174 return ret;
6175 }
6176
6177 /**
6178 * @brief Single/double-tap event enable.[set]
6179 *
6180 * @param ctx Read / write interface definitions.(ptr)
6181 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
6182 * @retval Interface status (MANDATORY: return 0 -> no Error).
6183 *
6184 */
lsm6dsr_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_single_double_tap_t val)6185 int32_t lsm6dsr_tap_mode_set(const stmdev_ctx_t *ctx,
6186 lsm6dsr_single_double_tap_t val)
6187 {
6188 lsm6dsr_wake_up_ths_t wake_up_ths;
6189 int32_t ret;
6190
6191 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
6192 (uint8_t *)&wake_up_ths, 1);
6193
6194 if (ret == 0)
6195 {
6196 wake_up_ths.single_double_tap = (uint8_t)val;
6197 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
6198 (uint8_t *)&wake_up_ths, 1);
6199 }
6200
6201 return ret;
6202 }
6203
6204 /**
6205 * @brief Single/double-tap event enable.[get]
6206 *
6207 * @param ctx Read / write interface definitions.(ptr)
6208 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6209 * @retval Interface status (MANDATORY: return 0 -> no Error).
6210 *
6211 */
lsm6dsr_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_single_double_tap_t * val)6212 int32_t lsm6dsr_tap_mode_get(const stmdev_ctx_t *ctx,
6213 lsm6dsr_single_double_tap_t *val)
6214 {
6215 lsm6dsr_wake_up_ths_t wake_up_ths;
6216 int32_t ret;
6217
6218 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
6219 (uint8_t *)&wake_up_ths, 1);
6220
6221 switch (wake_up_ths.single_double_tap)
6222 {
6223 case LSM6DSR_ONLY_SINGLE:
6224 *val = LSM6DSR_ONLY_SINGLE;
6225 break;
6226
6227 case LSM6DSR_BOTH_SINGLE_DOUBLE:
6228 *val = LSM6DSR_BOTH_SINGLE_DOUBLE;
6229 break;
6230
6231 default:
6232 *val = LSM6DSR_ONLY_SINGLE;
6233 break;
6234 }
6235
6236 return ret;
6237 }
6238
6239 /**
6240 * @}
6241 *
6242 */
6243
6244 /**
6245 * @defgroup LSM6DSR_ Six_position_detection(6D/4D)
6246 * @brief This section groups all the functions concerning six
6247 * position detection (6D).
6248 * @{
6249 *
6250 */
6251
6252 /**
6253 * @brief Threshold for 4D/6D function.[set]
6254 *
6255 * @param ctx Read / write interface definitions.(ptr)
6256 * @param val Change the values of sixd_ths in reg TAP_THS_6D
6257 * @retval Interface status (MANDATORY: return 0 -> no Error).
6258 *
6259 */
lsm6dsr_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsr_sixd_ths_t val)6260 int32_t lsm6dsr_6d_threshold_set(const stmdev_ctx_t *ctx,
6261 lsm6dsr_sixd_ths_t val)
6262 {
6263 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6264 int32_t ret;
6265
6266 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6267 (uint8_t *)&tap_ths_6d, 1);
6268
6269 if (ret == 0)
6270 {
6271 tap_ths_6d.sixd_ths = (uint8_t)val;
6272 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
6273 (uint8_t *)&tap_ths_6d, 1);
6274 }
6275
6276 return ret;
6277 }
6278
6279 /**
6280 * @brief Threshold for 4D/6D function.[get]
6281 *
6282 * @param ctx Read / write interface definitions.(ptr)
6283 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6284 * @retval Interface status (MANDATORY: return 0 -> no Error).
6285 *
6286 */
lsm6dsr_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsr_sixd_ths_t * val)6287 int32_t lsm6dsr_6d_threshold_get(const stmdev_ctx_t *ctx,
6288 lsm6dsr_sixd_ths_t *val)
6289 {
6290 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6291 int32_t ret;
6292
6293 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6294 (uint8_t *)&tap_ths_6d, 1);
6295
6296 switch (tap_ths_6d.sixd_ths)
6297 {
6298 case LSM6DSR_DEG_80:
6299 *val = LSM6DSR_DEG_80;
6300 break;
6301
6302 case LSM6DSR_DEG_70:
6303 *val = LSM6DSR_DEG_70;
6304 break;
6305
6306 case LSM6DSR_DEG_60:
6307 *val = LSM6DSR_DEG_60;
6308 break;
6309
6310 case LSM6DSR_DEG_50:
6311 *val = LSM6DSR_DEG_50;
6312 break;
6313
6314 default:
6315 *val = LSM6DSR_DEG_80;
6316 break;
6317 }
6318
6319 return ret;
6320 }
6321
6322 /**
6323 * @brief 4D orientation detection enable.[set]
6324 *
6325 * @param ctx Read / write interface definitions.(ptr)
6326 * @param val Change the values of d4d_en in reg TAP_THS_6D
6327 * @retval Interface status (MANDATORY: return 0 -> no Error).
6328 *
6329 */
lsm6dsr_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6330 int32_t lsm6dsr_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6331 {
6332 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6333 int32_t ret;
6334
6335 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6336 (uint8_t *)&tap_ths_6d, 1);
6337
6338 if (ret == 0)
6339 {
6340 tap_ths_6d.d4d_en = (uint8_t)val;
6341 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
6342 (uint8_t *)&tap_ths_6d, 1);
6343 }
6344
6345 return ret;
6346 }
6347
6348 /**
6349 * @brief 4D orientation detection enable.[get]
6350 *
6351 * @param ctx Read / write interface definitions.(ptr)
6352 * @param val Change the values of d4d_en in reg TAP_THS_6D
6353 * @retval Interface status (MANDATORY: return 0 -> no Error).
6354 *
6355 */
lsm6dsr_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6356 int32_t lsm6dsr_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6357 {
6358 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6359 int32_t ret;
6360
6361 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6362 (uint8_t *)&tap_ths_6d, 1);
6363 *val = tap_ths_6d.d4d_en;
6364
6365 return ret;
6366 }
6367
6368 /**
6369 * @}
6370 *
6371 */
6372
6373 /**
6374 * @defgroup LSM6DSR_free_fall
6375 * @brief This section group all the functions concerning the free
6376 * fall detection.
6377 * @{
6378 *
6379 */
6380
6381 /**
6382 * @brief Free fall threshold setting.[set]
6383 *
6384 * @param ctx Read / write interface definitions.(ptr)
6385 * @param val Change the values of ff_ths in reg FREE_FALL
6386 * @retval Interface status (MANDATORY: return 0 -> no Error).
6387 *
6388 */
lsm6dsr_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dsr_ff_ths_t val)6389 int32_t lsm6dsr_ff_threshold_set(const stmdev_ctx_t *ctx,
6390 lsm6dsr_ff_ths_t val)
6391 {
6392 lsm6dsr_free_fall_t free_fall;
6393 int32_t ret;
6394
6395 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6396 (uint8_t *)&free_fall, 1);
6397
6398 if (ret == 0)
6399 {
6400 free_fall.ff_ths = (uint8_t)val;
6401 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
6402 (uint8_t *)&free_fall, 1);
6403 }
6404
6405 return ret;
6406 }
6407
6408 /**
6409 * @brief Free fall threshold setting.[get]
6410 *
6411 * @param ctx Read / write interface definitions.(ptr)
6412 * @param val Get the values of ff_ths in reg FREE_FALL
6413 * @retval Interface status (MANDATORY: return 0 -> no Error).
6414 *
6415 */
lsm6dsr_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dsr_ff_ths_t * val)6416 int32_t lsm6dsr_ff_threshold_get(const stmdev_ctx_t *ctx,
6417 lsm6dsr_ff_ths_t *val)
6418 {
6419 lsm6dsr_free_fall_t free_fall;
6420 int32_t ret;
6421
6422 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6423 (uint8_t *)&free_fall, 1);
6424
6425 switch (free_fall.ff_ths)
6426 {
6427 case LSM6DSR_FF_TSH_156mg:
6428 *val = LSM6DSR_FF_TSH_156mg;
6429 break;
6430
6431 case LSM6DSR_FF_TSH_219mg:
6432 *val = LSM6DSR_FF_TSH_219mg;
6433 break;
6434
6435 case LSM6DSR_FF_TSH_250mg:
6436 *val = LSM6DSR_FF_TSH_250mg;
6437 break;
6438
6439 case LSM6DSR_FF_TSH_312mg:
6440 *val = LSM6DSR_FF_TSH_312mg;
6441 break;
6442
6443 case LSM6DSR_FF_TSH_344mg:
6444 *val = LSM6DSR_FF_TSH_344mg;
6445 break;
6446
6447 case LSM6DSR_FF_TSH_406mg:
6448 *val = LSM6DSR_FF_TSH_406mg;
6449 break;
6450
6451 case LSM6DSR_FF_TSH_469mg:
6452 *val = LSM6DSR_FF_TSH_469mg;
6453 break;
6454
6455 case LSM6DSR_FF_TSH_500mg:
6456 *val = LSM6DSR_FF_TSH_500mg;
6457 break;
6458
6459 default:
6460 *val = LSM6DSR_FF_TSH_156mg;
6461 break;
6462 }
6463
6464 return ret;
6465 }
6466
6467 /**
6468 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
6469 *
6470 * @param ctx Read / write interface definitions.(ptr)
6471 * @param val Change the values of ff_dur in reg FREE_FALL
6472 * @retval Interface status (MANDATORY: return 0 -> no Error).
6473 *
6474 */
lsm6dsr_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6475 int32_t lsm6dsr_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6476 {
6477 lsm6dsr_wake_up_dur_t wake_up_dur;
6478 lsm6dsr_free_fall_t free_fall;
6479 int32_t ret;
6480
6481 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6482 (uint8_t *)&wake_up_dur, 1);
6483
6484 if (ret == 0)
6485 {
6486 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
6487 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6488 (uint8_t *)&wake_up_dur, 1);
6489 }
6490
6491 if (ret == 0)
6492 {
6493 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6494 (uint8_t *)&free_fall, 1);
6495 }
6496
6497 if (ret == 0)
6498 {
6499 free_fall.ff_dur = val & 0x1FU;
6500 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
6501 (uint8_t *)&free_fall, 1);
6502 }
6503
6504 return ret;
6505 }
6506
6507 /**
6508 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
6509 *
6510 * @param ctx Read / write interface definitions.(ptr)
6511 * @param val Change the values of ff_dur in reg FREE_FALL
6512 * @retval Interface status (MANDATORY: return 0 -> no Error).
6513 *
6514 */
lsm6dsr_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6515 int32_t lsm6dsr_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6516 {
6517 lsm6dsr_wake_up_dur_t wake_up_dur;
6518 lsm6dsr_free_fall_t free_fall;
6519 int32_t ret;
6520
6521 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6522 (uint8_t *)&wake_up_dur, 1);
6523
6524 if (ret == 0)
6525 {
6526 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6527 (uint8_t *)&free_fall, 1);
6528 }
6529
6530 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6531
6532 return ret;
6533 }
6534
6535 /**
6536 * @}
6537 *
6538 */
6539
6540 /**
6541 * @defgroup LSM6DSR_fifo
6542 * @brief This section group all the functions concerning
6543 * the fifo usage
6544 * @{
6545 *
6546 */
6547
6548 /**
6549 * @brief FIFO watermark level selection.[set]
6550 *
6551 * @param ctx Read / write interface definitions.(ptr)
6552 * @param val Change the values of wtm in reg FIFO_CTRL1
6553 * @retval Interface status (MANDATORY: return 0 -> no Error).
6554 *
6555 */
lsm6dsr_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)6556 int32_t lsm6dsr_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
6557 {
6558 lsm6dsr_fifo_ctrl1_t fifo_ctrl1;
6559 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6560 int32_t ret;
6561
6562 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6563 ret += lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6564
6565 if (ret == 0)
6566 {
6567 fifo_ctrl1.wtm = (uint8_t)(val & 0xFFU);
6568 fifo_ctrl2.wtm = (uint8_t)(val / 256U) & 0x01U;
6569
6570 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6571 ret += lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6572 }
6573
6574 return ret;
6575 }
6576
6577 /**
6578 * @brief FIFO watermark level selection.[get]
6579 *
6580 * @param ctx Read / write interface definitions.(ptr)
6581 * @param val Change the values of wtm in reg FIFO_CTRL1
6582 * @retval Interface status (MANDATORY: return 0 -> no Error).
6583 *
6584 */
lsm6dsr_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)6585 int32_t lsm6dsr_fifo_watermark_get(const stmdev_ctx_t *ctx,
6586 uint16_t *val)
6587 {
6588 lsm6dsr_fifo_ctrl1_t fifo_ctrl1;
6589 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6590 int32_t ret;
6591
6592 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6593 ret += lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6594
6595 *val = fifo_ctrl2.wtm;
6596 *val = (*val * 256U) + fifo_ctrl1.wtm;;
6597
6598 return ret;
6599 }
6600
6601 /**
6602 * @brief FIFO compression feature initialization request.[set].
6603 *
6604 * @param ctx Read / write interface definitions.(ptr)
6605 * @param val Change the values of FIFO_COMPR_INIT in reg EMB_FUNC_INIT_B
6606 * @retval Interface status (MANDATORY: return 0 -> no Error).
6607 *
6608 */
lsm6dsr_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)6609 int32_t lsm6dsr_compression_algo_init_set(const stmdev_ctx_t *ctx,
6610 uint8_t val)
6611 {
6612 lsm6dsr_emb_func_init_b_t emb_func_init_b;
6613 int32_t ret;
6614
6615 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6616
6617 if (ret == 0)
6618 {
6619 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6620 (uint8_t *)&emb_func_init_b, 1);
6621 }
6622
6623 if (ret == 0)
6624 {
6625 emb_func_init_b.fifo_compr_init = (uint8_t)val;
6626 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6627 (uint8_t *)&emb_func_init_b, 1);
6628 }
6629
6630 if (ret == 0)
6631 {
6632 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6633 }
6634
6635 return ret;
6636 }
6637
6638 /**
6639 * @brief FIFO compression feature initialization request.[get].
6640 *
6641 * @param ctx Read / write interface definitions.(ptr)
6642 * @param val change the values of FIFO_COMPR_INIT in
6643 * reg EMB_FUNC_INIT_B
6644 * @retval Interface status (MANDATORY: return 0 -> no Error).
6645 *
6646 */
lsm6dsr_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6647 int32_t lsm6dsr_compression_algo_init_get(const stmdev_ctx_t *ctx,
6648 uint8_t *val)
6649 {
6650 lsm6dsr_emb_func_init_b_t emb_func_init_b;
6651 int32_t ret;
6652
6653 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6654
6655 if (ret == 0)
6656 {
6657 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6658 (uint8_t *)&emb_func_init_b, 1);
6659 }
6660
6661 if (ret == 0)
6662 {
6663 *val = emb_func_init_b.fifo_compr_init;
6664 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6665 }
6666
6667 return ret;
6668 }
6669
6670 /**
6671 * @brief Enable and configure compression algo.[set]
6672 *
6673 * @param ctx Read / write interface definitions.(ptr)
6674 * @param val Change the values of uncoptr_rate in reg FIFO_CTRL2
6675 * @retval Interface status (MANDATORY: return 0 -> no Error).
6676 *
6677 */
lsm6dsr_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dsr_uncoptr_rate_t val)6678 int32_t lsm6dsr_compression_algo_set(const stmdev_ctx_t *ctx,
6679 lsm6dsr_uncoptr_rate_t val)
6680 {
6681 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6682 lsm6dsr_emb_func_en_b_t emb_func_en_b;
6683 int32_t ret;
6684
6685 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6686
6687 if (ret == 0)
6688 {
6689 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
6690 (uint8_t *)&emb_func_en_b, 1);
6691 }
6692
6693 if (ret == 0)
6694 {
6695 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
6696 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
6697 (uint8_t *)&emb_func_en_b, 1);
6698 }
6699
6700 if (ret == 0)
6701 {
6702 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6703 }
6704
6705 if (ret == 0)
6706 {
6707 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6708 (uint8_t *)&fifo_ctrl2, 1);
6709 }
6710
6711 if (ret == 0)
6712 {
6713 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6714 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6715 }
6716
6717 if (ret == 0)
6718 {
6719 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6720 (uint8_t *)&fifo_ctrl2, 1);
6721 }
6722
6723 return ret;
6724 }
6725
6726 /**
6727 * @brief Enable and configure compression algo.[get]
6728 *
6729 * @param ctx Read / write interface definitions.(ptr)
6730 * @param val Get the values of uncoptr_rate in reg FIFO_CTRL2
6731 * @retval Interface status (MANDATORY: return 0 -> no Error).
6732 *
6733 */
lsm6dsr_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dsr_uncoptr_rate_t * val)6734 int32_t lsm6dsr_compression_algo_get(const stmdev_ctx_t *ctx,
6735 lsm6dsr_uncoptr_rate_t *val)
6736 {
6737 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6738 int32_t ret;
6739
6740 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6741 (uint8_t *)&fifo_ctrl2, 1);
6742
6743 switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
6744 fifo_ctrl2.uncoptr_rate)
6745 {
6746 case LSM6DSR_CMP_DISABLE:
6747 *val = LSM6DSR_CMP_DISABLE;
6748 break;
6749
6750 case LSM6DSR_CMP_ALWAYS:
6751 *val = LSM6DSR_CMP_ALWAYS;
6752 break;
6753
6754 case LSM6DSR_CMP_8_TO_1:
6755 *val = LSM6DSR_CMP_8_TO_1;
6756 break;
6757
6758 case LSM6DSR_CMP_16_TO_1:
6759 *val = LSM6DSR_CMP_16_TO_1;
6760 break;
6761
6762 case LSM6DSR_CMP_32_TO_1:
6763 *val = LSM6DSR_CMP_32_TO_1;
6764 break;
6765
6766 default:
6767 *val = LSM6DSR_CMP_DISABLE;
6768 break;
6769 }
6770
6771 return ret;
6772 }
6773
6774 /**
6775 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6776 *
6777 * @param ctx Read / write interface definitions.(ptr)
6778 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6779 * @retval Interface status (MANDATORY: return 0 -> no Error).
6780 *
6781 */
lsm6dsr_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)6782 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
6783 uint8_t val)
6784 {
6785 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6786 int32_t ret;
6787
6788 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6789 (uint8_t *)&fifo_ctrl2, 1);
6790
6791 if (ret == 0)
6792 {
6793 fifo_ctrl2.odrchg_en = (uint8_t)val;
6794 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6795 (uint8_t *)&fifo_ctrl2, 1);
6796 }
6797
6798 return ret;
6799 }
6800
6801 /**
6802 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6803 *
6804 * @param ctx Read / write interface definitions.(ptr)
6805 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6806 * @retval Interface status (MANDATORY: return 0 -> no Error).
6807 *
6808 */
lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)6809 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
6810 uint8_t *val)
6811 {
6812 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6813 int32_t ret;
6814
6815 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6816 (uint8_t *)&fifo_ctrl2, 1);
6817 *val = fifo_ctrl2.odrchg_en;
6818
6819 return ret;
6820 }
6821
6822 /**
6823 * @brief Enables/Disables compression algorithm runtime[set]
6824 *
6825 * @param ctx Read / write interface definitions.(ptr)
6826 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6827 * @retval Interface status (MANDATORY: return 0 -> no Error).
6828 *
6829 */
lsm6dsr_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)6830 int32_t lsm6dsr_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
6831 uint8_t val)
6832 {
6833 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6834 int32_t ret;
6835
6836 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6837 (uint8_t *)&fifo_ctrl2, 1);
6838
6839 if (ret == 0)
6840 {
6841 fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
6842 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6843 (uint8_t *)&fifo_ctrl2, 1);
6844 }
6845
6846 return ret;
6847 }
6848
6849 /**
6850 * @brief Enables/Disables compression algorithm runtime.[get]
6851 *
6852 * @param ctx Read / write interface definitions.(ptr)
6853 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6854 * @retval Interface status (MANDATORY: return 0 -> no Error).
6855 *
6856 */
lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)6857 int32_t lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
6858 uint8_t *val)
6859 {
6860 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6861 int32_t ret;
6862
6863 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6864 (uint8_t *)&fifo_ctrl2, 1);
6865 *val = fifo_ctrl2.fifo_compr_rt_en;
6866
6867 return ret;
6868 }
6869
6870 /**
6871 * @brief Sensing chain FIFO stop values memorization at threshold
6872 * level.[set]
6873 *
6874 * @param ctx Read / write interface definitions.(ptr)
6875 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
6876 * @retval Interface status (MANDATORY: return 0 -> no Error).
6877 *
6878 */
lsm6dsr_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)6879 int32_t lsm6dsr_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx,
6880 uint8_t val)
6881 {
6882 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6883 int32_t ret;
6884
6885 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6886 (uint8_t *)&fifo_ctrl2, 1);
6887
6888 if (ret == 0)
6889 {
6890 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
6891 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6892 (uint8_t *)&fifo_ctrl2, 1);
6893 }
6894
6895 return ret;
6896 }
6897
6898 /**
6899 * @brief Sensing chain FIFO stop values memorization at threshold
6900 * level.[get]
6901 *
6902 * @param ctx Read / write interface definitions.(ptr)
6903 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
6904 * @retval Interface status (MANDATORY: return 0 -> no Error).
6905 *
6906 */
lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)6907 int32_t lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
6908 uint8_t *val)
6909 {
6910 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6911 int32_t ret;
6912
6913 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6914 (uint8_t *)&fifo_ctrl2, 1);
6915 *val = fifo_ctrl2.stop_on_wtm;
6916
6917 return ret;
6918 }
6919
6920 /**
6921 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6922 * for accelerometer data.[set]
6923 *
6924 * @param ctx Read / write interface definitions.(ptr)
6925 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
6926 * @retval Interface status (MANDATORY: return 0 -> no Error).
6927 *
6928 */
lsm6dsr_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsr_bdr_xl_t val)6929 int32_t lsm6dsr_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
6930 lsm6dsr_bdr_xl_t val)
6931 {
6932 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6933 int32_t ret;
6934
6935 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6936 (uint8_t *)&fifo_ctrl3, 1);
6937
6938 if (ret == 0)
6939 {
6940 fifo_ctrl3.bdr_xl = (uint8_t)val;
6941 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
6942 (uint8_t *)&fifo_ctrl3, 1);
6943 }
6944
6945 return ret;
6946 }
6947
6948 /**
6949 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6950 * for accelerometer data.[get]
6951 *
6952 * @param ctx Read / write interface definitions.(ptr)
6953 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
6954 * @retval Interface status (MANDATORY: return 0 -> no Error).
6955 *
6956 */
lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsr_bdr_xl_t * val)6957 int32_t lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
6958 lsm6dsr_bdr_xl_t *val)
6959 {
6960 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6961 int32_t ret;
6962
6963 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6964 (uint8_t *)&fifo_ctrl3, 1);
6965
6966 switch (fifo_ctrl3.bdr_xl)
6967 {
6968 case LSM6DSR_XL_NOT_BATCHED:
6969 *val = LSM6DSR_XL_NOT_BATCHED;
6970 break;
6971
6972 case LSM6DSR_XL_BATCHED_AT_12Hz5:
6973 *val = LSM6DSR_XL_BATCHED_AT_12Hz5;
6974 break;
6975
6976 case LSM6DSR_XL_BATCHED_AT_26Hz:
6977 *val = LSM6DSR_XL_BATCHED_AT_26Hz;
6978 break;
6979
6980 case LSM6DSR_XL_BATCHED_AT_52Hz:
6981 *val = LSM6DSR_XL_BATCHED_AT_52Hz;
6982 break;
6983
6984 case LSM6DSR_XL_BATCHED_AT_104Hz:
6985 *val = LSM6DSR_XL_BATCHED_AT_104Hz;
6986 break;
6987
6988 case LSM6DSR_XL_BATCHED_AT_208Hz:
6989 *val = LSM6DSR_XL_BATCHED_AT_208Hz;
6990 break;
6991
6992 case LSM6DSR_XL_BATCHED_AT_417Hz:
6993 *val = LSM6DSR_XL_BATCHED_AT_417Hz;
6994 break;
6995
6996 case LSM6DSR_XL_BATCHED_AT_833Hz:
6997 *val = LSM6DSR_XL_BATCHED_AT_833Hz;
6998 break;
6999
7000 case LSM6DSR_XL_BATCHED_AT_1667Hz:
7001 *val = LSM6DSR_XL_BATCHED_AT_1667Hz;
7002 break;
7003
7004 case LSM6DSR_XL_BATCHED_AT_3333Hz:
7005 *val = LSM6DSR_XL_BATCHED_AT_3333Hz;
7006 break;
7007
7008 case LSM6DSR_XL_BATCHED_AT_6667Hz:
7009 *val = LSM6DSR_XL_BATCHED_AT_6667Hz;
7010 break;
7011
7012 case LSM6DSR_XL_BATCHED_AT_6Hz5:
7013 *val = LSM6DSR_XL_BATCHED_AT_6Hz5;
7014 break;
7015
7016 default:
7017 *val = LSM6DSR_XL_NOT_BATCHED;
7018 break;
7019 }
7020
7021 return ret;
7022 }
7023
7024 /**
7025 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7026 * for gyroscope data.[set]
7027 *
7028 * @param ctx Read / write interface definitions.(ptr)
7029 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
7030 * @retval Interface status (MANDATORY: return 0 -> no Error).
7031 *
7032 */
lsm6dsr_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsr_bdr_gy_t val)7033 int32_t lsm6dsr_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
7034 lsm6dsr_bdr_gy_t val)
7035 {
7036 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
7037 int32_t ret;
7038
7039 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
7040 (uint8_t *)&fifo_ctrl3, 1);
7041
7042 if (ret == 0)
7043 {
7044 fifo_ctrl3.bdr_gy = (uint8_t)val;
7045 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
7046 (uint8_t *)&fifo_ctrl3, 1);
7047 }
7048
7049 return ret;
7050 }
7051
7052 /**
7053 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7054 * for gyroscope data.[get]
7055 *
7056 * @param ctx Read / write interface definitions.(ptr)
7057 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
7058 * @retval Interface status (MANDATORY: return 0 -> no Error).
7059 *
7060 */
lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsr_bdr_gy_t * val)7061 int32_t lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
7062 lsm6dsr_bdr_gy_t *val)
7063 {
7064 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
7065 int32_t ret;
7066
7067 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
7068 (uint8_t *)&fifo_ctrl3, 1);
7069
7070 switch (fifo_ctrl3.bdr_gy)
7071 {
7072 case LSM6DSR_GY_NOT_BATCHED:
7073 *val = LSM6DSR_GY_NOT_BATCHED;
7074 break;
7075
7076 case LSM6DSR_GY_BATCHED_AT_12Hz5:
7077 *val = LSM6DSR_GY_BATCHED_AT_12Hz5;
7078 break;
7079
7080 case LSM6DSR_GY_BATCHED_AT_26Hz:
7081 *val = LSM6DSR_GY_BATCHED_AT_26Hz;
7082 break;
7083
7084 case LSM6DSR_GY_BATCHED_AT_52Hz:
7085 *val = LSM6DSR_GY_BATCHED_AT_52Hz;
7086 break;
7087
7088 case LSM6DSR_GY_BATCHED_AT_104Hz:
7089 *val = LSM6DSR_GY_BATCHED_AT_104Hz;
7090 break;
7091
7092 case LSM6DSR_GY_BATCHED_AT_208Hz:
7093 *val = LSM6DSR_GY_BATCHED_AT_208Hz;
7094 break;
7095
7096 case LSM6DSR_GY_BATCHED_AT_417Hz:
7097 *val = LSM6DSR_GY_BATCHED_AT_417Hz;
7098 break;
7099
7100 case LSM6DSR_GY_BATCHED_AT_833Hz:
7101 *val = LSM6DSR_GY_BATCHED_AT_833Hz;
7102 break;
7103
7104 case LSM6DSR_GY_BATCHED_AT_1667Hz:
7105 *val = LSM6DSR_GY_BATCHED_AT_1667Hz;
7106 break;
7107
7108 case LSM6DSR_GY_BATCHED_AT_3333Hz:
7109 *val = LSM6DSR_GY_BATCHED_AT_3333Hz;
7110 break;
7111
7112 case LSM6DSR_GY_BATCHED_AT_6667Hz:
7113 *val = LSM6DSR_GY_BATCHED_AT_6667Hz;
7114 break;
7115
7116 case LSM6DSR_GY_BATCHED_6Hz5:
7117 *val = LSM6DSR_GY_BATCHED_6Hz5;
7118 break;
7119
7120 default:
7121 *val = LSM6DSR_GY_NOT_BATCHED;
7122 break;
7123 }
7124
7125 return ret;
7126 }
7127
7128 /**
7129 * @brief FIFO mode selection.[set]
7130 *
7131 * @param ctx Read / write interface definitions.(ptr)
7132 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
7133 * @retval Interface status (MANDATORY: return 0 -> no Error).
7134 *
7135 */
lsm6dsr_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_fifo_mode_t val)7136 int32_t lsm6dsr_fifo_mode_set(const stmdev_ctx_t *ctx,
7137 lsm6dsr_fifo_mode_t val)
7138 {
7139 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7140 int32_t ret;
7141
7142 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7143 (uint8_t *)&fifo_ctrl4, 1);
7144
7145 if (ret == 0)
7146 {
7147 fifo_ctrl4.fifo_mode = (uint8_t)val;
7148 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
7149 (uint8_t *)&fifo_ctrl4, 1);
7150 }
7151
7152 return ret;
7153 }
7154
7155 /**
7156 * @brief FIFO mode selection.[get]
7157 *
7158 * @param ctx Read / write interface definitions.(ptr)
7159 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
7160 * @retval Interface status (MANDATORY: return 0 -> no Error).
7161 *
7162 */
lsm6dsr_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_fifo_mode_t * val)7163 int32_t lsm6dsr_fifo_mode_get(const stmdev_ctx_t *ctx,
7164 lsm6dsr_fifo_mode_t *val)
7165 {
7166 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7167 int32_t ret;
7168
7169 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7170 (uint8_t *)&fifo_ctrl4, 1);
7171
7172 switch (fifo_ctrl4.fifo_mode)
7173 {
7174 case LSM6DSR_BYPASS_MODE:
7175 *val = LSM6DSR_BYPASS_MODE;
7176 break;
7177
7178 case LSM6DSR_FIFO_MODE:
7179 *val = LSM6DSR_FIFO_MODE;
7180 break;
7181
7182 case LSM6DSR_STREAM_TO_FIFO_MODE:
7183 *val = LSM6DSR_STREAM_TO_FIFO_MODE;
7184 break;
7185
7186 case LSM6DSR_BYPASS_TO_STREAM_MODE:
7187 *val = LSM6DSR_BYPASS_TO_STREAM_MODE;
7188 break;
7189
7190 case LSM6DSR_STREAM_MODE:
7191 *val = LSM6DSR_STREAM_MODE;
7192 break;
7193
7194 case LSM6DSR_BYPASS_TO_FIFO_MODE:
7195 *val = LSM6DSR_BYPASS_TO_FIFO_MODE;
7196 break;
7197
7198 default:
7199 *val = LSM6DSR_BYPASS_MODE;
7200 break;
7201 }
7202
7203 return ret;
7204 }
7205
7206 /**
7207 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7208 * for temperature data.[set]
7209 *
7210 * @param ctx Read / write interface definitions.(ptr)
7211 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
7212 * @retval Interface status (MANDATORY: return 0 -> no Error).
7213 *
7214 */
lsm6dsr_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsr_odr_t_batch_t val)7215 int32_t lsm6dsr_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
7216 lsm6dsr_odr_t_batch_t val)
7217 {
7218 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7219 int32_t ret;
7220
7221 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7222 (uint8_t *)&fifo_ctrl4, 1);
7223
7224 if (ret == 0)
7225 {
7226 fifo_ctrl4.odr_t_batch = (uint8_t)val;
7227 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
7228 (uint8_t *)&fifo_ctrl4, 1);
7229 }
7230
7231 return ret;
7232 }
7233
7234 /**
7235 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7236 * for temperature data.[get]
7237 *
7238 * @param ctx Read / write interface definitions.(ptr)
7239 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7240 * @retval Interface status (MANDATORY: return 0 -> no Error).
7241 *
7242 */
lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsr_odr_t_batch_t * val)7243 int32_t lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
7244 lsm6dsr_odr_t_batch_t *val)
7245 {
7246 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7247 int32_t ret;
7248
7249 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7250 (uint8_t *)&fifo_ctrl4, 1);
7251
7252 switch (fifo_ctrl4.odr_t_batch)
7253 {
7254 case LSM6DSR_TEMP_NOT_BATCHED:
7255 *val = LSM6DSR_TEMP_NOT_BATCHED;
7256 break;
7257
7258 case LSM6DSR_TEMP_BATCHED_AT_52Hz:
7259 *val = LSM6DSR_TEMP_BATCHED_AT_52Hz;
7260 break;
7261
7262 case LSM6DSR_TEMP_BATCHED_AT_12Hz5:
7263 *val = LSM6DSR_TEMP_BATCHED_AT_12Hz5;
7264 break;
7265
7266 case LSM6DSR_TEMP_BATCHED_AT_1Hz6:
7267 *val = LSM6DSR_TEMP_BATCHED_AT_1Hz6;
7268 break;
7269
7270 default:
7271 *val = LSM6DSR_TEMP_NOT_BATCHED;
7272 break;
7273 }
7274
7275 return ret;
7276 }
7277
7278 /**
7279 * @brief Selects decimation for timestamp batching in FIFO.
7280 * Writing rate will be the maximum rate between XL and
7281 * GYRO BDR divided by decimation decoder.[set]
7282 *
7283 * @param ctx Read / write interface definitions.(ptr)
7284 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
7285 * @retval Interface status (MANDATORY: return 0 -> no Error).
7286 *
7287 */
lsm6dsr_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dsr_odr_ts_batch_t val)7288 int32_t lsm6dsr_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
7289 lsm6dsr_odr_ts_batch_t val)
7290 {
7291 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7292 int32_t ret;
7293
7294 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7295 (uint8_t *)&fifo_ctrl4, 1);
7296
7297 if (ret == 0)
7298 {
7299 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
7300 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
7301 (uint8_t *)&fifo_ctrl4, 1);
7302 }
7303
7304 return ret;
7305 }
7306
7307 /**
7308 * @brief Selects decimation for timestamp batching in FIFO.
7309 * Writing rate will be the maximum rate between XL and
7310 * GYRO BDR divided by decimation decoder.[get]
7311 *
7312 * @param ctx Read / write interface definitions.(ptr)
7313 * @param val Get the values of odr_ts_batch in reg
7314 * FIFO_CTRL4
7315 * @retval Interface status (MANDATORY: return 0 -> no Error).
7316 *
7317 */
lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dsr_odr_ts_batch_t * val)7318 int32_t lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
7319 lsm6dsr_odr_ts_batch_t *val)
7320 {
7321 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7322 int32_t ret;
7323
7324 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7325 (uint8_t *)&fifo_ctrl4, 1);
7326
7327 switch (fifo_ctrl4.odr_ts_batch)
7328 {
7329 case LSM6DSR_NO_DECIMATION:
7330 *val = LSM6DSR_NO_DECIMATION;
7331 break;
7332
7333 case LSM6DSR_DEC_1:
7334 *val = LSM6DSR_DEC_1;
7335 break;
7336
7337 case LSM6DSR_DEC_8:
7338 *val = LSM6DSR_DEC_8;
7339 break;
7340
7341 case LSM6DSR_DEC_32:
7342 *val = LSM6DSR_DEC_32;
7343 break;
7344
7345 default:
7346 *val = LSM6DSR_NO_DECIMATION;
7347 break;
7348 }
7349
7350 return ret;
7351 }
7352
7353 /**
7354 * @brief Selects the trigger for the internal counter of batching events
7355 * between XL and gyro.[set]
7356 *
7357 * @param ctx Read / write interface definitions.(ptr)
7358 * @param val Change the values of trig_counter_bdr in
7359 * reg COUNTER_BDR_REG1
7360 * @retval Interface status (MANDATORY: return 0 -> no Error).
7361 *
7362 */
lsm6dsr_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dsr_trig_counter_bdr_t val)7363 int32_t lsm6dsr_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
7364 lsm6dsr_trig_counter_bdr_t val)
7365 {
7366 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7367 int32_t ret;
7368
7369 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7370 (uint8_t *)&counter_bdr_reg1, 1);
7371
7372 if (ret == 0)
7373 {
7374 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
7375 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7376 (uint8_t *)&counter_bdr_reg1, 1);
7377 }
7378
7379 return ret;
7380 }
7381
7382 /**
7383 * @brief Selects the trigger for the internal counter of batching events
7384 * between XL and gyro.[get]
7385 *
7386 * @param ctx Read / write interface definitions.(ptr)
7387 * @param val Get the values of trig_counter_bdr
7388 * in reg COUNTER_BDR_REG1
7389 * @retval Interface status (MANDATORY: return 0 -> no Error).
7390 *
7391 */
lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dsr_trig_counter_bdr_t * val)7392 int32_t lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
7393 lsm6dsr_trig_counter_bdr_t *val)
7394 {
7395 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7396 int32_t ret;
7397
7398 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7399 (uint8_t *)&counter_bdr_reg1, 1);
7400
7401 switch (counter_bdr_reg1.trig_counter_bdr)
7402 {
7403 case LSM6DSR_XL_BATCH_EVENT:
7404 *val = LSM6DSR_XL_BATCH_EVENT;
7405 break;
7406
7407 case LSM6DSR_GYRO_BATCH_EVENT:
7408 *val = LSM6DSR_GYRO_BATCH_EVENT;
7409 break;
7410
7411 default:
7412 *val = LSM6DSR_XL_BATCH_EVENT;
7413 break;
7414 }
7415
7416 return ret;
7417 }
7418
7419 /**
7420 * @brief Resets the internal counter of batching events for a single sensor.
7421 * This bit is automatically reset to zero if it was set to '1'.[set]
7422 *
7423 * @param ctx Read / write interface definitions.(ptr)
7424 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7425 * @retval Interface status (MANDATORY: return 0 -> no Error).
7426 *
7427 */
lsm6dsr_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)7428 int32_t lsm6dsr_rst_batch_counter_set(const stmdev_ctx_t *ctx,
7429 uint8_t val)
7430 {
7431 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7432 int32_t ret;
7433
7434 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7435 (uint8_t *)&counter_bdr_reg1, 1);
7436
7437 if (ret == 0)
7438 {
7439 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
7440 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7441 (uint8_t *)&counter_bdr_reg1, 1);
7442 }
7443
7444 return ret;
7445 }
7446
7447 /**
7448 * @brief Resets the internal counter of batching events for a single sensor.
7449 * This bit is automatically reset to zero if it was set to '1'.[get]
7450 *
7451 * @param ctx Read / write interface definitions.(ptr)
7452 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7453 * @retval Interface status (MANDATORY: return 0 -> no Error).
7454 *
7455 */
lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)7456 int32_t lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t *ctx,
7457 uint8_t *val)
7458 {
7459 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7460 int32_t ret;
7461
7462 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7463 (uint8_t *)&counter_bdr_reg1, 1);
7464 *val = counter_bdr_reg1.rst_counter_bdr;
7465
7466 return ret;
7467 }
7468
7469 /**
7470 * @brief Batch data rate counter.[set]
7471 *
7472 * @param ctx Read / write interface definitions.(ptr)
7473 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7474 * and COUNTER_BDR_REG1.
7475 * @retval Interface status (MANDATORY: return 0 -> no Error).
7476 *
7477 */
lsm6dsr_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)7478 int32_t lsm6dsr_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
7479 uint16_t val)
7480 {
7481 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg1;
7482 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
7483 int32_t ret;
7484
7485 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7486 (uint8_t *)&counter_bdr_reg1, 1);
7487
7488 if (ret == 0)
7489 {
7490 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
7491 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7492 (uint8_t *)&counter_bdr_reg1, 1);
7493 }
7494
7495 if (ret == 0)
7496 {
7497 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
7498 (counter_bdr_reg1.cnt_bdr_th * 256U));
7499 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
7500 (uint8_t *)&counter_bdr_reg2, 1);
7501 }
7502
7503 return ret;
7504 }
7505
7506 /**
7507 * @brief Batch data rate counter.[get]
7508 *
7509 * @param ctx Read / write interface definitions.(ptr)
7510 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7511 * and COUNTER_BDR_REG1.
7512 * @retval Interface status (MANDATORY: return 0 -> no Error).
7513 *
7514 */
lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)7515 int32_t lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
7516 uint16_t *val)
7517 {
7518 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7519 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
7520 int32_t ret;
7521
7522 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7523 (uint8_t *)&counter_bdr_reg1, 1);
7524
7525 if (ret == 0)
7526 {
7527 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
7528 (uint8_t *)&counter_bdr_reg2, 1);
7529 }
7530
7531 *val = counter_bdr_reg1.cnt_bdr_th;
7532 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
7533
7534 return ret;
7535 }
7536
7537 /**
7538 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7539 *
7540 * @param ctx Read / write interface definitions.(ptr)
7541 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
7542 * @retval Interface status (MANDATORY: return 0 -> no Error).
7543 *
7544 */
lsm6dsr_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)7545 int32_t lsm6dsr_fifo_data_level_get(const stmdev_ctx_t *ctx,
7546 uint16_t *val)
7547 {
7548 uint8_t reg[2];
7549 lsm6dsr_fifo_status1_t *fifo_status1 = (lsm6dsr_fifo_status1_t *)®[0];
7550 lsm6dsr_fifo_status2_t *fifo_status2 = (lsm6dsr_fifo_status2_t *)®[1];
7551 int32_t ret;
7552
7553 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7554 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1, (uint8_t *)reg, 2);
7555 if (ret == 0)
7556 {
7557 *val = fifo_status2->diff_fifo;
7558 *val = (*val * 256U) + fifo_status1->diff_fifo;
7559 }
7560
7561 return ret;
7562 }
7563
7564 /**
7565 * @brief Smart FIFO status.[get]
7566 *
7567 * @param ctx Read / write interface definitions.(ptr)
7568 * @param val Read registers FIFO_STATUS2
7569 * @retval Interface status (MANDATORY: return 0 -> no Error).
7570 *
7571 */
lsm6dsr_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsr_fifo_status2_t * val)7572 int32_t lsm6dsr_fifo_status_get(const stmdev_ctx_t *ctx,
7573 lsm6dsr_fifo_status2_t *val)
7574 {
7575 uint8_t reg[2];
7576 lsm6dsr_fifo_status2_t *fifo_status2 = (lsm6dsr_fifo_status2_t *)®[1];
7577 int32_t ret;
7578
7579 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7580 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1, (uint8_t *)reg, 2);
7581 if (ret == 0)
7582 {
7583 *val = *fifo_status2;
7584 }
7585
7586 return ret;
7587 }
7588
7589 /**
7590 * @brief Smart FIFO full status.[get]
7591 *
7592 * @param ctx Read / write interface definitions.(ptr)
7593 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
7594 * @retval Interface status (MANDATORY: return 0 -> no Error).
7595 *
7596 */
lsm6dsr_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7597 int32_t lsm6dsr_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7598 {
7599 uint8_t reg[2];
7600 lsm6dsr_fifo_status2_t *fifo_status2 = (lsm6dsr_fifo_status2_t *)®[1];
7601 int32_t ret;
7602
7603 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7604 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1, (uint8_t *)reg, 2);
7605 if (ret == 0)
7606 {
7607 *val = fifo_status2->fifo_full_ia;
7608 }
7609
7610 return ret;
7611 }
7612
7613 /**
7614 * @brief FIFO overrun status.[get]
7615 *
7616 * @param ctx Read / write interface definitions.(ptr)
7617 * @param val Read the values of fifo_over_run_latched in
7618 * reg FIFO_STATUS2
7619 * @retval Interface status (MANDATORY: return 0 -> no Error).
7620 *
7621 */
lsm6dsr_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7622 int32_t lsm6dsr_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7623 {
7624 uint8_t reg[2];
7625 lsm6dsr_fifo_status2_t *fifo_status2 = (lsm6dsr_fifo_status2_t *)®[1];
7626 int32_t ret;
7627
7628 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7629 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1, (uint8_t *)reg, 2);
7630 if (ret == 0)
7631 {
7632 *val = fifo_status2->fifo_ovr_ia;
7633 }
7634
7635 return ret;
7636 }
7637
7638 /**
7639 * @brief FIFO watermark status.[get]
7640 *
7641 * @param ctx Read / write interface definitions.(ptr)
7642 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
7643 * @retval Interface status (MANDATORY: return 0 -> no Error).
7644 *
7645 */
lsm6dsr_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7646 int32_t lsm6dsr_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7647 {
7648 uint8_t reg[2];
7649 lsm6dsr_fifo_status2_t *fifo_status2 = (lsm6dsr_fifo_status2_t *)®[1];
7650 int32_t ret;
7651
7652 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7653 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1, (uint8_t *)reg, 2);
7654 if (ret == 0)
7655 {
7656 *val = fifo_status2->fifo_wtm_ia;
7657 }
7658
7659 return ret;
7660 }
7661
7662 /**
7663 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7664 *
7665 * @param ctx Read / write interface definitions.(ptr)
7666 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7667 * @retval Interface status (MANDATORY: return 0 -> no Error).
7668 *
7669 */
lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dsr_fifo_tag_t * val)7670 int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
7671 lsm6dsr_fifo_tag_t *val)
7672 {
7673 lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag;
7674 int32_t ret;
7675
7676 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_TAG,
7677 (uint8_t *)&fifo_data_out_tag, 1);
7678
7679 switch (fifo_data_out_tag.tag_sensor)
7680 {
7681 case LSM6DSR_GYRO_NC_TAG:
7682 *val = LSM6DSR_GYRO_NC_TAG;
7683 break;
7684
7685 case LSM6DSR_XL_NC_TAG:
7686 *val = LSM6DSR_XL_NC_TAG;
7687 break;
7688
7689 case LSM6DSR_TEMPERATURE_TAG:
7690 *val = LSM6DSR_TEMPERATURE_TAG;
7691 break;
7692
7693 case LSM6DSR_TIMESTAMP_TAG:
7694 *val = LSM6DSR_TIMESTAMP_TAG;
7695 break;
7696
7697 case LSM6DSR_CFG_CHANGE_TAG:
7698 *val = LSM6DSR_CFG_CHANGE_TAG;
7699 break;
7700
7701 case LSM6DSR_XL_NC_T_2_TAG:
7702 *val = LSM6DSR_XL_NC_T_2_TAG;
7703 break;
7704
7705 case LSM6DSR_XL_NC_T_1_TAG:
7706 *val = LSM6DSR_XL_NC_T_1_TAG;
7707 break;
7708
7709 case LSM6DSR_XL_2XC_TAG:
7710 *val = LSM6DSR_XL_2XC_TAG;
7711 break;
7712
7713 case LSM6DSR_XL_3XC_TAG:
7714 *val = LSM6DSR_XL_3XC_TAG;
7715 break;
7716
7717 case LSM6DSR_GYRO_NC_T_2_TAG:
7718 *val = LSM6DSR_GYRO_NC_T_2_TAG;
7719 break;
7720
7721 case LSM6DSR_GYRO_NC_T_1_TAG:
7722 *val = LSM6DSR_GYRO_NC_T_1_TAG;
7723 break;
7724
7725 case LSM6DSR_GYRO_2XC_TAG:
7726 *val = LSM6DSR_GYRO_2XC_TAG;
7727 break;
7728
7729 case LSM6DSR_GYRO_3XC_TAG:
7730 *val = LSM6DSR_GYRO_3XC_TAG;
7731 break;
7732
7733 case LSM6DSR_SENSORHUB_SLAVE0_TAG:
7734 *val = LSM6DSR_SENSORHUB_SLAVE0_TAG;
7735 break;
7736
7737 case LSM6DSR_SENSORHUB_SLAVE1_TAG:
7738 *val = LSM6DSR_SENSORHUB_SLAVE1_TAG;
7739 break;
7740
7741 case LSM6DSR_SENSORHUB_SLAVE2_TAG:
7742 *val = LSM6DSR_SENSORHUB_SLAVE2_TAG;
7743 break;
7744
7745 case LSM6DSR_SENSORHUB_SLAVE3_TAG:
7746 *val = LSM6DSR_SENSORHUB_SLAVE3_TAG;
7747 break;
7748
7749 case LSM6DSR_STEP_CPUNTER_TAG:
7750 *val = LSM6DSR_STEP_CPUNTER_TAG;
7751 break;
7752
7753 case LSM6DSR_GAME_ROTATION_TAG:
7754 *val = LSM6DSR_GAME_ROTATION_TAG;
7755 break;
7756
7757 case LSM6DSR_GEOMAG_ROTATION_TAG:
7758 *val = LSM6DSR_GEOMAG_ROTATION_TAG;
7759 break;
7760
7761 case LSM6DSR_ROTATION_TAG:
7762 *val = LSM6DSR_ROTATION_TAG;
7763 break;
7764
7765 case LSM6DSR_SENSORHUB_NACK_TAG:
7766 *val = LSM6DSR_SENSORHUB_NACK_TAG;
7767 break;
7768
7769 default:
7770 *val = LSM6DSR_SENSORHUB_NACK_TAG;
7771 break;
7772 }
7773
7774 return ret;
7775 }
7776
7777 /**
7778 * @brief Enable FIFO batching of pedometer embedded function values.[set]
7779 *
7780 * @param ctx Read / write interface definitions.(ptr)
7781 * @param val Change the values of gbias_fifo_en in
7782 * reg LSM6DSR_EMB_FUNC_FIFO_CFG
7783 * @retval Interface status (MANDATORY: return 0 -> no Error).
7784 *
7785 */
lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)7786 int32_t lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
7787 {
7788 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7789 int32_t ret;
7790
7791 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
7792
7793 if (ret == 0)
7794 {
7795 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7796 (uint8_t *)&emb_func_fifo_cfg, 1);
7797 }
7798
7799 if (ret == 0)
7800 {
7801 emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
7802 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7803 (uint8_t *)&emb_func_fifo_cfg, 1);
7804 }
7805
7806 if (ret == 0)
7807 {
7808 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7809 }
7810
7811 return ret;
7812 }
7813
7814 /**
7815 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7816 *
7817 * @param ctx Read / write interface definitions.(ptr)
7818 * @param val Change the values of pedo_fifo_en in reg
7819 * LSM6DSR_EMB_FUNC_FIFO_CFG
7820 * @retval Interface status (MANDATORY: return 0 -> no Error).
7821 *
7822 */
lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)7823 int32_t lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t *ctx,
7824 uint8_t *val)
7825 {
7826 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7827 int32_t ret;
7828
7829 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
7830
7831 if (ret == 0)
7832 {
7833 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7834 (uint8_t *)&emb_func_fifo_cfg, 1);
7835 *val = emb_func_fifo_cfg.pedo_fifo_en;
7836 }
7837
7838 if (ret == 0)
7839 {
7840 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7841 }
7842
7843 return ret;
7844 }
7845
7846 /**
7847 * @brief Enable FIFO batching data of first slave.[set]
7848 *
7849 * @param ctx Read / write interface definitions.(ptr)
7850 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
7851 * @retval Interface status (MANDATORY: return 0 -> no Error).
7852 *
7853 */
lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)7854 int32_t lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t *ctx,
7855 uint8_t val)
7856 {
7857 lsm6dsr_slv0_config_t slv0_config;
7858 int32_t ret;
7859
7860 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7861
7862 if (ret == 0)
7863 {
7864 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
7865 (uint8_t *)&slv0_config, 1);
7866 }
7867
7868 if (ret == 0)
7869 {
7870 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
7871 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
7872 (uint8_t *)&slv0_config, 1);
7873 }
7874
7875 if (ret == 0)
7876 {
7877 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7878 }
7879
7880 return ret;
7881 }
7882
7883 /**
7884 * @brief Enable FIFO batching data of first slave.[get]
7885 *
7886 * @param ctx Read / write interface definitions.(ptr)
7887 * @param val Change the values of batch_ext_sens_0_en in
7888 * reg SLV0_CONFIG
7889 * @retval Interface status (MANDATORY: return 0 -> no Error).
7890 *
7891 */
lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)7892 int32_t lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t *ctx,
7893 uint8_t *val)
7894 {
7895 lsm6dsr_slv0_config_t slv0_config;
7896 int32_t ret;
7897
7898 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7899
7900 if (ret == 0)
7901 {
7902 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
7903 (uint8_t *)&slv0_config, 1);
7904 }
7905
7906 if (ret == 0)
7907 {
7908 *val = slv0_config. batch_ext_sens_0_en;
7909 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7910 }
7911
7912 return ret;
7913 }
7914
7915 /**
7916 * @brief Enable FIFO batching data of second slave.[set]
7917 *
7918 * @param ctx Read / write interface definitions.(ptr)
7919 * @param val Change the values of batch_ext_sens_1_en in
7920 * reg SLV1_CONFIG
7921 * @retval Interface status (MANDATORY: return 0 -> no Error).
7922 *
7923 */
lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)7924 int32_t lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t *ctx,
7925 uint8_t val)
7926 {
7927 lsm6dsr_slv1_config_t slv1_config;
7928 int32_t ret;
7929
7930 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7931
7932 if (ret == 0)
7933 {
7934 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
7935 (uint8_t *)&slv1_config, 1);
7936 }
7937
7938 if (ret == 0)
7939 {
7940 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
7941 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
7942 (uint8_t *)&slv1_config, 1);
7943 }
7944
7945 if (ret == 0)
7946 {
7947 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7948 }
7949
7950 return ret;
7951 }
7952
7953 /**
7954 * @brief Enable FIFO batching data of second slave.[get]
7955 *
7956 * @param ctx Read / write interface definitions.(ptr)
7957 * @param val Change the values of batch_ext_sens_1_en in
7958 * reg SLV1_CONFIG
7959 * @retval Interface status (MANDATORY: return 0 -> no Error).
7960 *
7961 */
lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)7962 int32_t lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t *ctx,
7963 uint8_t *val)
7964 {
7965 lsm6dsr_slv1_config_t slv1_config;
7966 int32_t ret;
7967
7968 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7969
7970 if (ret == 0)
7971 {
7972 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
7973 (uint8_t *)&slv1_config, 1);
7974 *val = slv1_config. batch_ext_sens_1_en;
7975 }
7976
7977 if (ret == 0)
7978 {
7979 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7980 }
7981
7982 return ret;
7983 }
7984
7985 /**
7986 * @brief Enable FIFO batching data of third slave.[set]
7987 *
7988 * @param ctx Read / write interface definitions.(ptr)
7989 * @param val Change the values of batch_ext_sens_2_en in
7990 * reg SLV2_CONFIG
7991 * @retval Interface status (MANDATORY: return 0 -> no Error).
7992 *
7993 */
lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)7994 int32_t lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t *ctx,
7995 uint8_t val)
7996 {
7997 lsm6dsr_slv2_config_t slv2_config;
7998 int32_t ret;
7999
8000 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
8001
8002 if (ret == 0)
8003 {
8004 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
8005 (uint8_t *)&slv2_config, 1);
8006 }
8007
8008 if (ret == 0)
8009 {
8010 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
8011 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
8012 (uint8_t *)&slv2_config, 1);
8013 }
8014
8015 if (ret == 0)
8016 {
8017 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8018 }
8019
8020 return ret;
8021 }
8022
8023 /**
8024 * @brief Enable FIFO batching data of third slave.[get]
8025 *
8026 * @param ctx Read / write interface definitions.(ptr)
8027 * @param val Change the values of batch_ext_sens_2_en in
8028 * reg SLV2_CONFIG
8029 * @retval Interface status (MANDATORY: return 0 -> no Error).
8030 *
8031 */
lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)8032 int32_t lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t *ctx,
8033 uint8_t *val)
8034 {
8035 lsm6dsr_slv2_config_t slv2_config;
8036 int32_t ret;
8037
8038 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
8039
8040 if (ret == 0)
8041 {
8042 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
8043 (uint8_t *)&slv2_config, 1);
8044 }
8045
8046 if (ret == 0)
8047 {
8048 *val = slv2_config. batch_ext_sens_2_en;
8049 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8050 }
8051
8052 return ret;
8053 }
8054
8055 /**
8056 * @brief Enable FIFO batching data of fourth slave.[set]
8057 *
8058 * @param ctx Read / write interface definitions.(ptr)
8059 * @param val Change the values of batch_ext_sens_3_en in
8060 * reg SLV3_CONFIG
8061 * @retval Interface status (MANDATORY: return 0 -> no Error).
8062 *
8063 */
lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)8064 int32_t lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t *ctx,
8065 uint8_t val)
8066 {
8067 lsm6dsr_slv3_config_t slv3_config;
8068 int32_t ret;
8069
8070 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
8071
8072 if (ret == 0)
8073 {
8074 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
8075 (uint8_t *)&slv3_config, 1);
8076 }
8077
8078 if (ret == 0)
8079 {
8080 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
8081 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
8082 (uint8_t *)&slv3_config, 1);
8083 }
8084
8085 if (ret == 0)
8086 {
8087 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8088 }
8089
8090 return ret;
8091 }
8092
8093 /**
8094 * @brief Enable FIFO batching data of fourth slave.[get]
8095 *
8096 * @param ctx Read / write interface definitions.(ptr)
8097 * @param val Change the values of batch_ext_sens_3_en in
8098 * reg SLV3_CONFIG
8099 * @retval Interface status (MANDATORY: return 0 -> no Error).
8100 *
8101 */
lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)8102 int32_t lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t *ctx,
8103 uint8_t *val)
8104 {
8105 lsm6dsr_slv3_config_t slv3_config;
8106 int32_t ret;
8107
8108 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
8109
8110 if (ret == 0)
8111 {
8112 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
8113 (uint8_t *)&slv3_config, 1);
8114 *val = slv3_config. batch_ext_sens_3_en;
8115 }
8116
8117 if (ret == 0)
8118 {
8119 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8120 }
8121
8122 return ret;
8123 }
8124
8125 /**
8126 * @}
8127 *
8128 */
8129
8130 /**
8131 * @defgroup LSM6DSR_DEN_functionality
8132 * @brief This section groups all the functions concerning
8133 * DEN functionality.
8134 * @{
8135 *
8136 */
8137
8138 /**
8139 * @brief DEN functionality marking mode.[set]
8140 *
8141 * @param ctx Read / write interface definitions.(ptr)
8142 * @param val Change the values of den_mode in reg CTRL6_C
8143 * @retval Interface status (MANDATORY: return 0 -> no Error).
8144 *
8145 */
lsm6dsr_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_den_mode_t val)8146 int32_t lsm6dsr_den_mode_set(const stmdev_ctx_t *ctx,
8147 lsm6dsr_den_mode_t val)
8148 {
8149 lsm6dsr_ctrl6_c_t ctrl6_c;
8150 int32_t ret;
8151
8152 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
8153 (uint8_t *)&ctrl6_c, 1);
8154
8155 if (ret == 0)
8156 {
8157 ctrl6_c.den_mode = (uint8_t)val;
8158 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C,
8159 (uint8_t *)&ctrl6_c, 1);
8160 }
8161
8162 return ret;
8163 }
8164
8165 /**
8166 * @brief DEN functionality marking mode.[get]
8167 *
8168 * @param ctx Read / write interface definitions.(ptr)
8169 * @param val Get the values of den_mode in reg CTRL6_C
8170 * @retval Interface status (MANDATORY: return 0 -> no Error).
8171 *
8172 */
lsm6dsr_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_den_mode_t * val)8173 int32_t lsm6dsr_den_mode_get(const stmdev_ctx_t *ctx,
8174 lsm6dsr_den_mode_t *val)
8175 {
8176 lsm6dsr_ctrl6_c_t ctrl6_c;
8177 int32_t ret;
8178
8179 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C,
8180 (uint8_t *)&ctrl6_c, 1);
8181
8182 switch (ctrl6_c.den_mode)
8183 {
8184 case LSM6DSR_DEN_DISABLE:
8185 *val = LSM6DSR_DEN_DISABLE;
8186 break;
8187
8188 case LSM6DSR_LEVEL_FIFO:
8189 *val = LSM6DSR_LEVEL_FIFO;
8190 break;
8191
8192 case LSM6DSR_LEVEL_LETCHED:
8193 *val = LSM6DSR_LEVEL_LETCHED;
8194 break;
8195
8196 case LSM6DSR_LEVEL_TRIGGER:
8197 *val = LSM6DSR_LEVEL_TRIGGER;
8198 break;
8199
8200 case LSM6DSR_EDGE_TRIGGER:
8201 *val = LSM6DSR_EDGE_TRIGGER;
8202 break;
8203
8204 default:
8205 *val = LSM6DSR_DEN_DISABLE;
8206 break;
8207 }
8208
8209 return ret;
8210 }
8211
8212 /**
8213 * @brief DEN active level configuration.[set]
8214 *
8215 * @param ctx Read / write interface definitions.(ptr)
8216 * @param val Change the values of den_lh in reg CTRL9_XL
8217 * @retval Interface status (MANDATORY: return 0 -> no Error).
8218 *
8219 */
lsm6dsr_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsr_den_lh_t val)8220 int32_t lsm6dsr_den_polarity_set(const stmdev_ctx_t *ctx,
8221 lsm6dsr_den_lh_t val)
8222 {
8223 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8224 int32_t ret;
8225
8226 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8227 (uint8_t *)&ctrl9_xl, 1);
8228
8229 if (ret == 0)
8230 {
8231 ctrl9_xl.den_lh = (uint8_t)val;
8232 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8233 (uint8_t *)&ctrl9_xl, 1);
8234 }
8235
8236 return ret;
8237 }
8238
8239 /**
8240 * @brief DEN active level configuration.[get]
8241 *
8242 * @param ctx Read / write interface definitions.(ptr)
8243 * @param val Get the values of den_lh in reg CTRL9_XL
8244 * @retval Interface status (MANDATORY: return 0 -> no Error).
8245 *
8246 */
lsm6dsr_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsr_den_lh_t * val)8247 int32_t lsm6dsr_den_polarity_get(const stmdev_ctx_t *ctx,
8248 lsm6dsr_den_lh_t *val)
8249 {
8250 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8251 int32_t ret;
8252
8253 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8254 (uint8_t *)&ctrl9_xl, 1);
8255
8256 switch (ctrl9_xl.den_lh)
8257 {
8258 case LSM6DSR_DEN_ACT_LOW:
8259 *val = LSM6DSR_DEN_ACT_LOW;
8260 break;
8261
8262 case LSM6DSR_DEN_ACT_HIGH:
8263 *val = LSM6DSR_DEN_ACT_HIGH;
8264 break;
8265
8266 default:
8267 *val = LSM6DSR_DEN_ACT_LOW;
8268 break;
8269 }
8270
8271 return ret;
8272 }
8273
8274 /**
8275 * @brief DEN configuration.[set]
8276 *
8277 * @param ctx Read / write interface definitions.(ptr)
8278 * @param val Change the values of den_xl_g in reg CTRL9_XL
8279 * @retval Interface status (MANDATORY: return 0 -> no Error).
8280 *
8281 */
lsm6dsr_den_enable_set(const stmdev_ctx_t * ctx,lsm6dsr_den_xl_g_t val)8282 int32_t lsm6dsr_den_enable_set(const stmdev_ctx_t *ctx,
8283 lsm6dsr_den_xl_g_t val)
8284 {
8285 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8286 int32_t ret;
8287
8288 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8289 (uint8_t *)&ctrl9_xl, 1);
8290
8291 if (ret == 0)
8292 {
8293 ctrl9_xl.den_xl_g = (uint8_t)val;
8294 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8295 (uint8_t *)&ctrl9_xl, 1);
8296 }
8297
8298 return ret;
8299 }
8300
8301 /**
8302 * @brief DEN configuration.[get]
8303 *
8304 * @param ctx Read / write interface definitions.(ptr)
8305 * @param val Get the values of den_xl_g in reg CTRL9_XL
8306 * @retval Interface status (MANDATORY: return 0 -> no Error).
8307 *
8308 */
lsm6dsr_den_enable_get(const stmdev_ctx_t * ctx,lsm6dsr_den_xl_g_t * val)8309 int32_t lsm6dsr_den_enable_get(const stmdev_ctx_t *ctx,
8310 lsm6dsr_den_xl_g_t *val)
8311 {
8312 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8313 int32_t ret;
8314
8315 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8316 (uint8_t *)&ctrl9_xl, 1);
8317
8318 switch (ctrl9_xl.den_xl_g)
8319 {
8320 case LSM6DSR_STAMP_IN_GY_DATA:
8321 *val = LSM6DSR_STAMP_IN_GY_DATA;
8322 break;
8323
8324 case LSM6DSR_STAMP_IN_XL_DATA:
8325 *val = LSM6DSR_STAMP_IN_XL_DATA;
8326 break;
8327
8328 case LSM6DSR_STAMP_IN_GY_XL_DATA:
8329 *val = LSM6DSR_STAMP_IN_GY_XL_DATA;
8330 break;
8331
8332 default:
8333 *val = LSM6DSR_STAMP_IN_GY_DATA;
8334 break;
8335 }
8336
8337 return ret;
8338 }
8339
8340 /**
8341 * @brief DEN value stored in LSB of X-axis.[set]
8342 *
8343 * @param ctx Read / write interface definitions.(ptr)
8344 * @param val Change the values of den_z in reg CTRL9_XL
8345 * @retval Interface status (MANDATORY: return 0 -> no Error).
8346 *
8347 */
lsm6dsr_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)8348 int32_t lsm6dsr_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
8349 {
8350 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8351 int32_t ret;
8352
8353 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8354 (uint8_t *)&ctrl9_xl, 1);
8355
8356 if (ret == 0)
8357 {
8358 ctrl9_xl.den_z = (uint8_t)val;
8359 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8360 (uint8_t *)&ctrl9_xl, 1);
8361 }
8362
8363 return ret;
8364 }
8365
8366 /**
8367 * @brief DEN value stored in LSB of X-axis.[get]
8368 *
8369 * @param ctx Read / write interface definitions.(ptr)
8370 * @param val Change the values of den_z in reg CTRL9_XL
8371 * @retval Interface status (MANDATORY: return 0 -> no Error).
8372 *
8373 */
lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)8374 int32_t lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t *ctx,
8375 uint8_t *val)
8376 {
8377 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8378 int32_t ret;
8379
8380 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8381 (uint8_t *)&ctrl9_xl, 1);
8382 *val = ctrl9_xl.den_z;
8383
8384 return ret;
8385 }
8386
8387 /**
8388 * @brief DEN value stored in LSB of Y-axis.[set]
8389 *
8390 * @param ctx Read / write interface definitions.(ptr)
8391 * @param val Change the values of den_y in reg CTRL9_XL
8392 * @retval Interface status (MANDATORY: return 0 -> no Error).
8393 *
8394 */
lsm6dsr_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)8395 int32_t lsm6dsr_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
8396 {
8397 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8398 int32_t ret;
8399
8400 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8401 (uint8_t *)&ctrl9_xl, 1);
8402
8403 if (ret == 0)
8404 {
8405 ctrl9_xl.den_y = (uint8_t)val;
8406 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8407 (uint8_t *)&ctrl9_xl, 1);
8408 }
8409
8410 return ret;
8411 }
8412
8413 /**
8414 * @brief DEN value stored in LSB of Y-axis.[get]
8415 *
8416 * @param ctx Read / write interface definitions.(ptr)
8417 * @param val Change the values of den_y in reg CTRL9_XL
8418 * @retval Interface status (MANDATORY: return 0 -> no Error).
8419 *
8420 */
lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)8421 int32_t lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t *ctx,
8422 uint8_t *val)
8423 {
8424 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8425 int32_t ret;
8426
8427 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8428 (uint8_t *)&ctrl9_xl, 1);
8429 *val = ctrl9_xl.den_y;
8430
8431 return ret;
8432 }
8433
8434 /**
8435 * @brief DEN value stored in LSB of Z-axis.[set]
8436 *
8437 * @param ctx Read / write interface definitions.(ptr)
8438 * @param val Change the values of den_x in reg CTRL9_XL
8439 * @retval Interface status (MANDATORY: return 0 -> no Error).
8440 *
8441 */
lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)8442 int32_t lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
8443 {
8444 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8445 int32_t ret;
8446
8447 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8448 (uint8_t *)&ctrl9_xl, 1);
8449
8450 if (ret == 0)
8451 {
8452 ctrl9_xl.den_x = (uint8_t)val;
8453 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8454 (uint8_t *)&ctrl9_xl, 1);
8455 }
8456
8457 return ret;
8458 }
8459
8460 /**
8461 * @brief DEN value stored in LSB of Z-axis.[get]
8462 *
8463 * @param ctx Read / write interface definitions.(ptr)
8464 * @param val Change the values of den_x in reg CTRL9_XL
8465 * @retval Interface status (MANDATORY: return 0 -> no Error).
8466 *
8467 */
lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)8468 int32_t lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t *ctx,
8469 uint8_t *val)
8470 {
8471 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8472 int32_t ret;
8473
8474 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL,
8475 (uint8_t *)&ctrl9_xl, 1);
8476 *val = ctrl9_xl.den_x;
8477
8478 return ret;
8479 }
8480
8481 /**
8482 * @}
8483 *
8484 */
8485
8486 /**
8487 * @defgroup LSM6DSR_Pedometer
8488 * @brief This section groups all the functions that manage pedometer.
8489 * @{
8490 *
8491 */
8492
8493 /**
8494 * @brief Enable pedometer algorithm.[set]
8495 *
8496 * @param ctx Read / write interface definitions.(ptr)
8497 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8498 * @retval Interface status (MANDATORY: return 0 -> no Error).
8499 *
8500 */
lsm6dsr_pedo_sens_set(const stmdev_ctx_t * ctx,uint8_t val)8501 int32_t lsm6dsr_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
8502 {
8503 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8504 int32_t ret;
8505
8506 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8507
8508 if (ret == 0)
8509 {
8510 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8511 (uint8_t *)&emb_func_en_a, 1);
8512 }
8513
8514 if (ret == 0)
8515 {
8516 emb_func_en_a.pedo_en = (uint8_t)val;
8517 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8518 (uint8_t *)&emb_func_en_a, 1);
8519 }
8520
8521 if (ret == 0)
8522 {
8523 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8524 }
8525
8526 return ret;
8527 }
8528
8529 /**
8530 * @brief Enable pedometer algorithm.[get]
8531 *
8532 * @param ctx Read / write interface definitions.(ptr)
8533 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8534 * @retval Interface status (MANDATORY: return 0 -> no Error).
8535 *
8536 */
lsm6dsr_pedo_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)8537 int32_t lsm6dsr_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
8538 {
8539 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8540 int32_t ret;
8541
8542 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8543
8544 if (ret == 0)
8545 {
8546 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8547 (uint8_t *)&emb_func_en_a, 1);
8548 *val = emb_func_en_a.pedo_en;
8549 }
8550
8551 if (ret == 0)
8552 {
8553 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8554 }
8555
8556 return ret;
8557 }
8558
8559 /**
8560 * @brief Pedometer algorithm working mode.[set]
8561 *
8562 * @param ctx read / write interface definitions
8563 * @param val Change the values of:
8564 * - pedo_fpr_adf_dis in reg ADV_PEDO
8565 * - pedo_adv_en in reg EMB_FUNC_EN_B
8566 * - ad_det_en in reg PEDO_CMD_REG
8567 * @retval Interface status (MANDATORY: return 0 -> no Error).
8568 *
8569 */
lsm6dsr_pedo_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_pedo_mode_t val)8570 int32_t lsm6dsr_pedo_mode_set(const stmdev_ctx_t *ctx,
8571 lsm6dsr_pedo_mode_t val)
8572 {
8573 lsm6dsr_adv_pedo_t adv_pedo;
8574 lsm6dsr_emb_func_en_b_t emb_func_en_b;
8575 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8576 int32_t ret;
8577
8578 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8579
8580 if (ret == 0)
8581 {
8582 ret = lsm6dsr_read_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
8583 }
8584
8585 if (ret == 0)
8586 {
8587 adv_pedo.pedo_fpr_adf_dis = (~((uint8_t)val) & 0x01U);
8588 ret = lsm6dsr_write_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
8589 }
8590
8591 if (ret == 0)
8592 {
8593 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
8594 (uint8_t *)&emb_func_en_b, 1);
8595 }
8596
8597 if (ret == 0)
8598 {
8599 emb_func_en_b.pedo_adv_en = (uint8_t)val & 0x01U;
8600 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
8601 (uint8_t *)&emb_func_en_b, 1);
8602 }
8603
8604 if (ret == 0)
8605 {
8606 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8607 }
8608
8609 if (ret == 0)
8610 {
8611 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8612 (uint8_t *)&pedo_cmd_reg);
8613 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x01U);
8614 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x02U) >> 1;
8615 }
8616
8617 if (ret == 0)
8618 {
8619 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8620 (uint8_t *)&pedo_cmd_reg);
8621 }
8622
8623 return ret;
8624 }
8625
8626 /**
8627 * @brief Pedometer algorithm working mode.[get]
8628 *
8629 * @param ctx read / write interface definitions
8630 * @param val Get the values of:
8631 * - pedo_fpr_adf_dis in reg ADV_PEDO
8632 * - pedo_adv_en in reg EMB_FUNC_EN_B
8633 * - ad_det_en in reg PEDO_CMD_REG
8634 * @retval Interface status (MANDATORY: return 0 -> no Error).
8635 *
8636 */
lsm6dsr_pedo_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_pedo_mode_t * val)8637 int32_t lsm6dsr_pedo_mode_get(const stmdev_ctx_t *ctx,
8638 lsm6dsr_pedo_mode_t *val)
8639 {
8640 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8641 int32_t ret;
8642
8643 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8644 (uint8_t *)&pedo_cmd_reg);
8645
8646 switch ((pedo_cmd_reg.ad_det_en << 1) |
8647 pedo_cmd_reg.fp_rejection_en)
8648 {
8649 case LSM6DSR_PEDO_BASE:
8650 *val = LSM6DSR_PEDO_BASE;
8651 break;
8652
8653 case LSM6DSR_PEDO_BASE_FALSE_STEP_REJ:
8654 *val = LSM6DSR_PEDO_BASE_FALSE_STEP_REJ;
8655 break;
8656
8657 case LSM6DSR_PEDO_ADV_FALSE_STEP_REJ:
8658 *val = LSM6DSR_PEDO_ADV_FALSE_STEP_REJ;
8659 break;
8660
8661 default:
8662 *val = LSM6DSR_PEDO_BASE;
8663 break;
8664 }
8665
8666 return ret;
8667 }
8668
8669 /**
8670 * @brief Interrupt status bit for step detection.[get]
8671 *
8672 * @param ctx Read / write interface definitions.(ptr)
8673 * @param val Change the values of is_step_det in reg EMB_FUNC_STATUS
8674 * @retval Interface status (MANDATORY: return 0 -> no Error).
8675 *
8676 */
lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)8677 int32_t lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t *ctx,
8678 uint8_t *val)
8679 {
8680 lsm6dsr_emb_func_status_t emb_func_status;
8681 int32_t ret;
8682
8683 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8684
8685 if (ret == 0)
8686 {
8687 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
8688 (uint8_t *)&emb_func_status, 1);
8689 *val = emb_func_status.is_step_det;
8690 }
8691
8692 if (ret == 0)
8693 {
8694 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8695 }
8696
8697 return ret;
8698 }
8699
8700 /**
8701 * @brief Pedometer debounce configuration register (r/w).[set]
8702 *
8703 * @param ctx Read / write interface definitions.(ptr)
8704 * @param buff Buffer that contains data to write
8705 * @retval Interface status (MANDATORY: return 0 -> no Error).
8706 *
8707 */
lsm6dsr_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)8708 int32_t lsm6dsr_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
8709 uint8_t *buff)
8710 {
8711 int32_t ret;
8712
8713 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF,
8714 buff);
8715
8716 return ret;
8717 }
8718
8719 /**
8720 * @brief Pedometer debounce configuration register (r/w).[get]
8721 *
8722 * @param ctx Read / write interface definitions.(ptr)
8723 * @param buff Buffer that stores data read
8724 * @retval Interface status (MANDATORY: return 0 -> no Error).
8725 *
8726 */
lsm6dsr_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)8727 int32_t lsm6dsr_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
8728 uint8_t *buff)
8729 {
8730 int32_t ret;
8731
8732 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF,
8733 buff);
8734
8735 return ret;
8736 }
8737
8738 /**
8739 * @brief Time period register for step detection on delta time (r/w).[set]
8740 *
8741 * @param ctx Read / write interface definitions.(ptr)
8742 * @param buff Buffer that contains data to write
8743 * @retval Interface status (MANDATORY: return 0 -> no Error).
8744 *
8745 */
lsm6dsr_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)8746 int32_t lsm6dsr_pedo_steps_period_set(const stmdev_ctx_t *ctx,
8747 uint16_t val)
8748 {
8749 uint8_t buff[2];
8750 int32_t ret;
8751
8752 buff[1] = (uint8_t)(val / 256U);
8753 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8754 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
8755 &buff[0]);
8756
8757 if (ret == 0)
8758 {
8759 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
8760 &buff[1]);
8761 }
8762
8763 return ret;
8764 }
8765
8766 /**
8767 * @brief Time period register for step detection on delta time (r/w).[get]
8768 *
8769 * @param ctx Read / write interface definitions.(ptr)
8770 * @param buff Buffer that stores data read
8771 * @retval Interface status (MANDATORY: return 0 -> no Error).
8772 *
8773 */
lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)8774 int32_t lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t *ctx,
8775 uint16_t *val)
8776 {
8777 uint8_t buff[2];
8778 int32_t ret;
8779
8780 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
8781 &buff[0]);
8782
8783 if (ret == 0)
8784 {
8785 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
8786 &buff[1]);
8787 *val = buff[1];
8788 *val = (*val * 256U) + buff[0];
8789 }
8790
8791 return ret;
8792 }
8793
8794 /**
8795 * @brief Enables the advanced detection feature.[set]
8796 *
8797 * @param ctx Read / write interface definitions.(ptr)
8798 * @param val Change the values of ad_det_en in reg PEDO_CMD_REG
8799 * @retval Interface status (MANDATORY: return 0 -> no Error).
8800 *
8801 */
lsm6dsr_pedo_adv_detection_set(const stmdev_ctx_t * ctx,uint8_t val)8802 int32_t lsm6dsr_pedo_adv_detection_set(const stmdev_ctx_t *ctx, uint8_t val)
8803 {
8804 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8805 int32_t ret;
8806
8807 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8808 (uint8_t *)&pedo_cmd_reg);
8809
8810 if (ret == 0)
8811 {
8812 pedo_cmd_reg.ad_det_en = (uint8_t)val;
8813 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8814 (uint8_t *)&pedo_cmd_reg);
8815 }
8816
8817 return ret;
8818 }
8819
8820 /**
8821 * @brief Enables the advanced detection feature.[get]
8822 *
8823 * @param ctx Read / write interface definitions.(ptr)
8824 * @param val Change the values of ad_det_en in reg PEDO_CMD_REG
8825 * @retval Interface status (MANDATORY: return 0 -> no Error).
8826 *
8827 */
lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t * ctx,uint8_t * val)8828 int32_t lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t *ctx,
8829 uint8_t *val)
8830 {
8831 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8832 int32_t ret;
8833
8834 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8835 (uint8_t *)&pedo_cmd_reg);
8836 *val = pedo_cmd_reg.ad_det_en;
8837
8838 return ret;
8839 }
8840
8841 /**
8842 * @brief Enables the false-positive rejection feature.[set]
8843 *
8844 * @param ctx Read / write interface definitions.(ptr)
8845 * @param val Change the values of fp_rejection_en in reg PEDO_CMD_REG
8846 * @retval Interface status (MANDATORY: return 0 -> no Error).
8847 *
8848 */
lsm6dsr_pedo_false_step_rejection_set(const stmdev_ctx_t * ctx,uint8_t val)8849 int32_t lsm6dsr_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx,
8850 uint8_t val)
8851 {
8852 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8853 int32_t ret;
8854
8855 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8856 (uint8_t *)&pedo_cmd_reg);
8857
8858 if (ret == 0)
8859 {
8860 pedo_cmd_reg.fp_rejection_en = (uint8_t)val;
8861 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8862 (uint8_t *)&pedo_cmd_reg);
8863 }
8864
8865 return ret;
8866 }
8867
8868 /**
8869 * @brief Enables the false-positive rejection feature.[get]
8870 *
8871 * @param ctx Read / write interface definitions.(ptr)
8872 * @param val Change the values of fp_rejection_en in reg PEDO_CMD_REG
8873 * @retval Interface status (MANDATORY: return 0 -> no Error).
8874 *
8875 */
lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t * ctx,uint8_t * val)8876 int32_t lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx,
8877 uint8_t *val)
8878 {
8879 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8880 int32_t ret;
8881
8882 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8883 (uint8_t *)&pedo_cmd_reg);
8884 *val = pedo_cmd_reg.fp_rejection_en;
8885
8886 return ret;
8887 }
8888
8889 /**
8890 * @brief Set when user wants to generate interrupt on count overflow
8891 * event/every step.[set]
8892 *
8893 * @param ctx Read / write interface definitions.(ptr)
8894 * @param val Change the values of carry_count_en in reg PEDO_CMD_REG
8895 * @retval Interface status (MANDATORY: return 0 -> no Error).
8896 *
8897 */
lsm6dsr_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_carry_count_en_t val)8898 int32_t lsm6dsr_pedo_int_mode_set(const stmdev_ctx_t *ctx,
8899 lsm6dsr_carry_count_en_t val)
8900 {
8901 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8902 int32_t ret;
8903
8904 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8905 (uint8_t *)&pedo_cmd_reg);
8906
8907 if (ret == 0)
8908 {
8909 pedo_cmd_reg.carry_count_en = (uint8_t)val;
8910 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8911 (uint8_t *)&pedo_cmd_reg);
8912 }
8913
8914 return ret;
8915 }
8916
8917 /**
8918 * @brief Set when user wants to generate interrupt on count overflow
8919 * event/every step.[get]
8920 *
8921 * @param ctx Read / write interface definitions.(ptr)
8922 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8923 * @retval Interface status (MANDATORY: return 0 -> no Error).
8924 *
8925 */
lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_carry_count_en_t * val)8926 int32_t lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t *ctx,
8927 lsm6dsr_carry_count_en_t *val)
8928 {
8929 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8930 int32_t ret;
8931
8932 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8933 (uint8_t *)&pedo_cmd_reg);
8934
8935 switch (pedo_cmd_reg.carry_count_en)
8936 {
8937 case LSM6DSR_EVERY_STEP:
8938 *val = LSM6DSR_EVERY_STEP;
8939 break;
8940
8941 case LSM6DSR_COUNT_OVERFLOW:
8942 *val = LSM6DSR_COUNT_OVERFLOW;
8943 break;
8944
8945 default:
8946 *val = LSM6DSR_EVERY_STEP;
8947 break;
8948 }
8949
8950 return ret;
8951 }
8952
8953 /**
8954 * @}
8955 *
8956 */
8957
8958 /**
8959 * @defgroup LSM6DSR_significant_motion
8960 * @brief This section groups all the functions that manage the
8961 * significant motion detection.
8962 * @{
8963 *
8964 */
8965
8966 /**
8967 * @brief Enable significant motion detection function.[set]
8968 *
8969 * @param ctx Read / write interface definitions.(ptr)
8970 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8971 * @retval Interface status (MANDATORY: return 0 -> no Error).
8972 *
8973 */
lsm6dsr_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)8974 int32_t lsm6dsr_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
8975 {
8976 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8977 int32_t ret;
8978
8979 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8980
8981 if (ret == 0)
8982 {
8983 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8984 (uint8_t *)&emb_func_en_a, 1);
8985 }
8986
8987 if (ret == 0)
8988 {
8989 emb_func_en_a.sign_motion_en = (uint8_t)val;
8990 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8991 (uint8_t *)&emb_func_en_a, 1);
8992 }
8993
8994 if (ret == 0)
8995 {
8996 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8997 }
8998
8999 return ret;
9000 }
9001
9002 /**
9003 * @brief Enable significant motion detection function.[get]
9004 *
9005 * @param ctx Read / write interface definitions.(ptr)
9006 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
9007 * @retval Interface status (MANDATORY: return 0 -> no Error).
9008 *
9009 */
lsm6dsr_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)9010 int32_t lsm6dsr_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
9011 {
9012 lsm6dsr_emb_func_en_a_t emb_func_en_a;
9013 int32_t ret;
9014
9015 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9016
9017 if (ret == 0)
9018 {
9019 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
9020 (uint8_t *)&emb_func_en_a, 1);
9021 }
9022
9023 if (ret == 0)
9024 {
9025 *val = emb_func_en_a.sign_motion_en;
9026 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9027 }
9028
9029 return ret;
9030 }
9031
9032 /**
9033 * @brief Interrupt status bit for significant motion detection.[get]
9034 *
9035 * @param ctx Read / write interface definitions.(ptr)
9036 * @param val Change the values of is_sigmot in reg EMB_FUNC_STATUS
9037 * @retval Interface status (MANDATORY: return 0 -> no Error).
9038 *
9039 */
lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9040 int32_t lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
9041 uint8_t *val)
9042 {
9043 lsm6dsr_emb_func_status_t emb_func_status;
9044 int32_t ret;
9045
9046 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9047
9048 if (ret == 0)
9049 {
9050 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
9051 (uint8_t *)&emb_func_status, 1);
9052 }
9053
9054 if (ret == 0)
9055 {
9056 *val = emb_func_status.is_sigmot;
9057 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9058 }
9059
9060 return ret;
9061 }
9062
9063 /**
9064 * @}
9065 *
9066 */
9067
9068 /**
9069 * @defgroup LSM6DSR_tilt_detection
9070 * @brief This section groups all the functions that manage the tilt
9071 * event detection.
9072 * @{
9073 *
9074 */
9075
9076 /**
9077 * @brief Enable tilt calculation.[set]
9078 *
9079 * @param ctx Read / write interface definitions.(ptr)
9080 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9081 * @retval Interface status (MANDATORY: return 0 -> no Error).
9082 *
9083 */
lsm6dsr_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)9084 int32_t lsm6dsr_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
9085 {
9086 lsm6dsr_emb_func_en_a_t emb_func_en_a;
9087 int32_t ret;
9088
9089 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9090
9091 if (ret == 0)
9092 {
9093 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
9094 (uint8_t *)&emb_func_en_a, 1);
9095 }
9096
9097 if (ret == 0)
9098 {
9099 emb_func_en_a.tilt_en = (uint8_t)val;
9100 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
9101 (uint8_t *)&emb_func_en_a, 1);
9102 }
9103
9104 if (ret == 0)
9105 {
9106 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9107 }
9108
9109 return ret;
9110 }
9111
9112 /**
9113 * @brief Enable tilt calculation.[get]
9114 *
9115 * @param ctx Read / write interface definitions.(ptr)
9116 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9117 * @retval Interface status (MANDATORY: return 0 -> no Error).
9118 *
9119 */
lsm6dsr_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)9120 int32_t lsm6dsr_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
9121 {
9122 lsm6dsr_emb_func_en_a_t emb_func_en_a;
9123 int32_t ret;
9124
9125 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9126
9127 if (ret == 0)
9128 {
9129 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
9130 (uint8_t *)&emb_func_en_a, 1);
9131 }
9132
9133 if (ret == 0)
9134 {
9135 *val = emb_func_en_a.tilt_en;
9136 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9137 }
9138
9139 return ret;
9140 }
9141
9142 /**
9143 * @brief Interrupt status bit for tilt detection.[get]
9144 *
9145 * @param ctx Read / write interface definitions.(ptr)
9146 * @param val Change the values of is_tilt in reg EMB_FUNC_STATUS
9147 * @retval Interface status (MANDATORY: return 0 -> no Error).
9148 *
9149 */
lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9150 int32_t lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9151 uint8_t *val)
9152 {
9153 lsm6dsr_emb_func_status_t emb_func_status;
9154 int32_t ret;
9155
9156 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9157
9158 if (ret == 0)
9159 {
9160 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
9161 (uint8_t *)&emb_func_status, 1);
9162 }
9163
9164 if (ret == 0)
9165 {
9166 *val = emb_func_status.is_tilt;
9167 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9168 }
9169
9170 return ret;
9171 }
9172
9173 /**
9174 * @}
9175 *
9176 */
9177
9178 /**
9179 * @defgroup LSM6DSR_ magnetometer_sensor
9180 * @brief This section groups all the functions that manage additional
9181 * magnetometer sensor.
9182 * @{
9183 *
9184 */
9185
9186 /**
9187 * @brief External magnetometer sensitivity value register.[set]
9188 *
9189 * @param ctx Read / write interface definitions.(ptr)
9190 * @param buff Buffer that contains data to write
9191 * @retval Interface status (MANDATORY: return 0 -> no Error).
9192 *
9193 */
lsm6dsr_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)9194 int32_t lsm6dsr_mag_sensitivity_set(const stmdev_ctx_t *ctx,
9195 uint16_t val)
9196 {
9197 uint8_t buff[2];
9198 int32_t ret;
9199
9200 buff[1] = (uint8_t)(val / 256U);
9201 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9202 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
9203 &buff[0]);
9204
9205 if (ret == 0)
9206 {
9207 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
9208 &buff[1]);
9209 }
9210
9211 return ret;
9212 }
9213
9214 /**
9215 * @brief External magnetometer sensitivity value register.[get]
9216 *
9217 * @param ctx Read / write interface definitions.(ptr)
9218 * @param buff Buffer that stores data read
9219 * @retval Interface status (MANDATORY: return 0 -> no Error).
9220 *
9221 */
lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)9222 int32_t lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t *ctx,
9223 uint16_t *val)
9224 {
9225 uint8_t buff[2];
9226 int32_t ret;
9227
9228 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
9229 &buff[0]);
9230
9231 if (ret == 0)
9232 {
9233 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
9234 &buff[1]);
9235 *val = buff[1];
9236 *val = (*val * 256U) + buff[0];
9237 }
9238
9239 return ret;
9240 }
9241
9242 /**
9243 * @brief Offset for hard-iron compensation register (r/w).[set]
9244 *
9245 * @param ctx Read / write interface definitions.(ptr)
9246 * @param buff Buffer that contains data to write
9247 * @retval Interface status (MANDATORY: return 0 -> no Error).
9248 *
9249 */
lsm6dsr_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)9250 int32_t lsm6dsr_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
9251 {
9252 uint8_t buff[6];
9253 int32_t ret;
9254 uint8_t i;
9255
9256 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9257 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9258 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9259 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9260 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9261 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9262 i = 0x00U;
9263 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
9264
9265 if (ret == 0)
9266 {
9267 i++;
9268 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
9269 }
9270
9271 if (ret == 0)
9272 {
9273 i++;
9274 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
9275 }
9276
9277 if (ret == 0)
9278 {
9279 i++;
9280 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
9281 }
9282
9283 if (ret == 0)
9284 {
9285 i++;
9286 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
9287 }
9288
9289 if (ret == 0)
9290 {
9291 i++;
9292 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
9293 }
9294
9295 return ret;
9296 }
9297
9298 /**
9299 * @brief Offset for hard-iron compensation register (r/w).[get]
9300 *
9301 * @param ctx Read / write interface definitions.(ptr)
9302 * @param buff Buffer that stores data read
9303 * @retval Interface status (MANDATORY: return 0 -> no Error).
9304 *
9305 */
lsm6dsr_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)9306 int32_t lsm6dsr_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
9307 {
9308 uint8_t buff[6];
9309 int32_t ret;
9310 uint8_t i;
9311
9312 i = 0x00U;
9313 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
9314
9315 if (ret == 0)
9316 {
9317 i++;
9318 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
9319 }
9320
9321 if (ret == 0)
9322 {
9323 i++;
9324 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
9325 }
9326
9327 if (ret == 0)
9328 {
9329 i++;
9330 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
9331 }
9332
9333 if (ret == 0)
9334 {
9335 i++;
9336 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
9337 }
9338
9339 if (ret == 0)
9340 {
9341 i++;
9342 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
9343
9344 val[0] = (int16_t)buff[1];
9345 val[0] = (val[0] * 256) + (int16_t)buff[0];
9346 val[1] = (int16_t)buff[3];
9347 val[1] = (val[1] * 256) + (int16_t)buff[2];
9348 val[2] = (int16_t)buff[5];
9349 val[2] = (val[2] * 256) + (int16_t)buff[4];
9350 }
9351
9352 return ret;
9353 }
9354
9355 /**
9356 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9357 * The value is expressed as half-precision floating-point format:
9358 * SEEEEEFFFFFFFFFF
9359 * S: 1 sign bit;
9360 * E: 5 exponent bits;
9361 * F: 10 fraction bits).[set]
9362 *
9363 * @param ctx Read / write interface definitions.(ptr)
9364 * @param buff Buffer that contains data to write
9365 * @retval Interface status (MANDATORY: return 0 -> no Error).
9366 *
9367 */
lsm6dsr_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)9368 int32_t lsm6dsr_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
9369 {
9370 uint8_t buff[12];
9371 int32_t ret;
9372 uint8_t i;
9373
9374 buff[1] = (uint8_t)(val[0] / 256U);
9375 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
9376 buff[3] = (uint8_t)(val[1] / 256U);
9377 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
9378 buff[5] = (uint8_t)(val[2] / 256U);
9379 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
9380 buff[7] = (uint8_t)(val[3] / 256U);
9381 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
9382 buff[9] = (uint8_t)(val[4] / 256U);
9383 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
9384 buff[11] = (uint8_t)(val[5] / 256U);
9385 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
9386 i = 0x00U;
9387 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_L,
9388 &buff[i]);
9389
9390 if (ret == 0)
9391 {
9392 i++;
9393 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_H,
9394 &buff[i]);
9395 }
9396
9397 if (ret == 0)
9398 {
9399 i++;
9400 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_L,
9401 &buff[i]);
9402 }
9403
9404 if (ret == 0)
9405 {
9406 i++;
9407 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_H,
9408 &buff[i]);
9409 }
9410
9411 if (ret == 0)
9412 {
9413 i++;
9414 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_L,
9415 &buff[i]);
9416 }
9417
9418 if (ret == 0)
9419 {
9420 i++;
9421 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_H,
9422 &buff[i]);
9423 }
9424
9425 if (ret == 0)
9426 {
9427 i++;
9428 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_L,
9429 &buff[i]);
9430 }
9431
9432 if (ret == 0)
9433 {
9434 i++;
9435 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_H,
9436 &buff[i]);
9437 }
9438
9439 if (ret == 0)
9440 {
9441 i++;
9442 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_L,
9443 &buff[i]);
9444 }
9445
9446 if (ret == 0)
9447 {
9448 i++;
9449 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_H,
9450 &buff[i]);
9451 }
9452
9453 if (ret == 0)
9454 {
9455 i++;
9456 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_L,
9457 &buff[i]);
9458 }
9459
9460 if (ret == 0)
9461 {
9462 i++;
9463 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_H,
9464 &buff[i]);
9465 }
9466
9467 return ret;
9468 }
9469
9470 /**
9471 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9472 * The value is expressed as half-precision floating-point format:
9473 * SEEEEEFFFFFFFFFF
9474 * S: 1 sign bit;
9475 * E: 5 exponent bits;
9476 * F: 10 fraction bits).[get]
9477 *
9478 * @param ctx Read / write interface definitions.(ptr)
9479 * @param buff Buffer that stores data read
9480 * @retval Interface status (MANDATORY: return 0 -> no Error).
9481 *
9482 */
lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)9483 int32_t lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
9484 {
9485 uint8_t buff[12];
9486 int32_t ret;
9487 uint8_t i;
9488
9489 i = 0x00U;
9490 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_L,
9491 &buff[i]);
9492
9493 if (ret == 0)
9494 {
9495 i++;
9496 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_H,
9497 &buff[i]);
9498 }
9499
9500 if (ret == 0)
9501 {
9502 i++;
9503 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_L,
9504 &buff[i]);
9505 }
9506
9507 if (ret == 0)
9508 {
9509 i++;
9510 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_H,
9511 &buff[i]);
9512 }
9513
9514 if (ret == 0)
9515 {
9516 i++;
9517 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_L,
9518 &buff[i]);
9519 }
9520
9521 if (ret == 0)
9522 {
9523 i++;
9524 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_H,
9525 &buff[i]);
9526 }
9527
9528 if (ret == 0)
9529 {
9530 i++;
9531 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_L,
9532 &buff[i]);
9533 }
9534
9535 if (ret == 0)
9536 {
9537 i++;
9538 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_H,
9539 &buff[i]);
9540 }
9541
9542 if (ret == 0)
9543 {
9544 i++;
9545 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_L,
9546 &buff[i]);
9547 }
9548
9549 if (ret == 0)
9550 {
9551 i++;
9552 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_H,
9553 &buff[i]);
9554 }
9555
9556 if (ret == 0)
9557 {
9558 i++;
9559 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_L,
9560 &buff[i]);
9561 }
9562
9563 if (ret == 0)
9564 {
9565 i++;
9566 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_H,
9567 &buff[i]);
9568 }
9569
9570 val[0] = buff[1];
9571 val[0] = (val[0] * 256U) + buff[0];
9572 val[1] = buff[3];
9573 val[1] = (val[1] * 256U) + buff[2];
9574 val[2] = buff[5];
9575 val[2] = (val[2] * 256U) + buff[4];
9576 val[3] = buff[7];
9577 val[3] = (val[3] * 256U) + buff[6];
9578 val[4] = buff[9];
9579 val[4] = (val[4] * 256U) + buff[8];
9580 val[5] = buff[11];
9581 val[6] = (val[5] * 256U) + buff[10];
9582
9583 return ret;
9584 }
9585
9586 /**
9587 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9588 * accelerometer/gyroscope axes orientation).[set]
9589 *
9590 * @param ctx Read / write interface definitions.(ptr)
9591 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
9592 * @retval Interface status (MANDATORY: return 0 -> no Error).
9593 *
9594 */
lsm6dsr_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsr_mag_z_axis_t val)9595 int32_t lsm6dsr_mag_z_orient_set(const stmdev_ctx_t *ctx,
9596 lsm6dsr_mag_z_axis_t val)
9597 {
9598 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9599 int32_t ret;
9600
9601 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9602 (uint8_t *)&mag_cfg_a);
9603
9604 if (ret == 0)
9605 {
9606 mag_cfg_a.mag_z_axis = (uint8_t)val;
9607 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
9608 (uint8_t *)&mag_cfg_a);
9609 }
9610
9611 return ret;
9612 }
9613
9614 /**
9615 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9616 * accelerometer/gyroscope axes orientation).[get]
9617 *
9618 * @param ctx Read / write interface definitions.(ptr)
9619 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9620 * @retval Interface status (MANDATORY: return 0 -> no Error).
9621 *
9622 */
lsm6dsr_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsr_mag_z_axis_t * val)9623 int32_t lsm6dsr_mag_z_orient_get(const stmdev_ctx_t *ctx,
9624 lsm6dsr_mag_z_axis_t *val)
9625 {
9626 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9627 int32_t ret;
9628
9629 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9630 (uint8_t *)&mag_cfg_a);
9631
9632 switch (mag_cfg_a.mag_z_axis)
9633 {
9634 case LSM6DSR_Z_EQ_Y:
9635 *val = LSM6DSR_Z_EQ_Y;
9636 break;
9637
9638 case LSM6DSR_Z_EQ_MIN_Y:
9639 *val = LSM6DSR_Z_EQ_MIN_Y;
9640 break;
9641
9642 case LSM6DSR_Z_EQ_X:
9643 *val = LSM6DSR_Z_EQ_X;
9644 break;
9645
9646 case LSM6DSR_Z_EQ_MIN_X:
9647 *val = LSM6DSR_Z_EQ_MIN_X;
9648 break;
9649
9650 case LSM6DSR_Z_EQ_MIN_Z:
9651 *val = LSM6DSR_Z_EQ_MIN_Z;
9652 break;
9653
9654 case LSM6DSR_Z_EQ_Z:
9655 *val = LSM6DSR_Z_EQ_Z;
9656 break;
9657
9658 default:
9659 *val = LSM6DSR_Z_EQ_Y;
9660 break;
9661 }
9662
9663 return ret;
9664 }
9665
9666 /**
9667 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9668 * accelerometer/gyroscope axes orientation).[set]
9669 *
9670 * @param ctx Read / write interface definitions.(ptr)
9671 * @param val Change the values of mag_y_axis in
9672 * reg MAG_CFG_A
9673 * @retval Interface status (MANDATORY: return 0 -> no Error).
9674 *
9675 */
lsm6dsr_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsr_mag_y_axis_t val)9676 int32_t lsm6dsr_mag_y_orient_set(const stmdev_ctx_t *ctx,
9677 lsm6dsr_mag_y_axis_t val)
9678 {
9679 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9680 int32_t ret;
9681
9682 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9683 (uint8_t *)&mag_cfg_a);
9684
9685 if (ret == 0)
9686 {
9687 mag_cfg_a.mag_y_axis = (uint8_t)val;
9688 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
9689 (uint8_t *)&mag_cfg_a);
9690 }
9691
9692 return ret;
9693 }
9694
9695 /**
9696 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9697 * accelerometer/gyroscope axes orientation).[get]
9698 *
9699 * @param ctx Read / write interface definitions.(ptr)
9700 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9701 * @retval Interface status (MANDATORY: return 0 -> no Error).
9702 *
9703 */
lsm6dsr_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsr_mag_y_axis_t * val)9704 int32_t lsm6dsr_mag_y_orient_get(const stmdev_ctx_t *ctx,
9705 lsm6dsr_mag_y_axis_t *val)
9706 {
9707 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9708 int32_t ret;
9709
9710 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9711 (uint8_t *)&mag_cfg_a);
9712
9713 switch (mag_cfg_a.mag_y_axis)
9714 {
9715 case LSM6DSR_Y_EQ_Y:
9716 *val = LSM6DSR_Y_EQ_Y;
9717 break;
9718
9719 case LSM6DSR_Y_EQ_MIN_Y:
9720 *val = LSM6DSR_Y_EQ_MIN_Y;
9721 break;
9722
9723 case LSM6DSR_Y_EQ_X:
9724 *val = LSM6DSR_Y_EQ_X;
9725 break;
9726
9727 case LSM6DSR_Y_EQ_MIN_X:
9728 *val = LSM6DSR_Y_EQ_MIN_X;
9729 break;
9730
9731 case LSM6DSR_Y_EQ_MIN_Z:
9732 *val = LSM6DSR_Y_EQ_MIN_Z;
9733 break;
9734
9735 case LSM6DSR_Y_EQ_Z:
9736 *val = LSM6DSR_Y_EQ_Z;
9737 break;
9738
9739 default:
9740 *val = LSM6DSR_Y_EQ_Y;
9741 break;
9742 }
9743
9744 return ret;
9745 }
9746
9747 /**
9748 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9749 * accelerometer/gyroscope axes orientation).[set]
9750 *
9751 * @param ctx Read / write interface definitions.(ptr)
9752 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
9753 * @retval Interface status (MANDATORY: return 0 -> no Error).
9754 *
9755 */
lsm6dsr_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsr_mag_x_axis_t val)9756 int32_t lsm6dsr_mag_x_orient_set(const stmdev_ctx_t *ctx,
9757 lsm6dsr_mag_x_axis_t val)
9758 {
9759 lsm6dsr_mag_cfg_b_t mag_cfg_b;
9760 int32_t ret;
9761
9762 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
9763 (uint8_t *)&mag_cfg_b);
9764
9765 if (ret == 0)
9766 {
9767 mag_cfg_b.mag_x_axis = (uint8_t)val;
9768 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_B,
9769 (uint8_t *)&mag_cfg_b);
9770 }
9771
9772 return ret;
9773 }
9774
9775 /**
9776 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9777 * accelerometer/gyroscope axes orientation).[get]
9778 *
9779 * @param ctx Read / write interface definitions.(ptr)
9780 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9781 * @retval Interface status (MANDATORY: return 0 -> no Error).
9782 *
9783 */
lsm6dsr_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsr_mag_x_axis_t * val)9784 int32_t lsm6dsr_mag_x_orient_get(const stmdev_ctx_t *ctx,
9785 lsm6dsr_mag_x_axis_t *val)
9786 {
9787 lsm6dsr_mag_cfg_b_t mag_cfg_b;
9788 int32_t ret;
9789
9790 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
9791 (uint8_t *)&mag_cfg_b);
9792
9793 switch (mag_cfg_b.mag_x_axis)
9794 {
9795 case LSM6DSR_X_EQ_Y:
9796 *val = LSM6DSR_X_EQ_Y;
9797 break;
9798
9799 case LSM6DSR_X_EQ_MIN_Y:
9800 *val = LSM6DSR_X_EQ_MIN_Y;
9801 break;
9802
9803 case LSM6DSR_X_EQ_X:
9804 *val = LSM6DSR_X_EQ_X;
9805 break;
9806
9807 case LSM6DSR_X_EQ_MIN_X:
9808 *val = LSM6DSR_X_EQ_MIN_X;
9809 break;
9810
9811 case LSM6DSR_X_EQ_MIN_Z:
9812 *val = LSM6DSR_X_EQ_MIN_Z;
9813 break;
9814
9815 case LSM6DSR_X_EQ_Z:
9816 *val = LSM6DSR_X_EQ_Z;
9817 break;
9818
9819 default:
9820 *val = LSM6DSR_X_EQ_Y;
9821 break;
9822 }
9823
9824 return ret;
9825 }
9826
9827 /**
9828 * @}
9829 *
9830 */
9831
9832 /**
9833 * @defgroup LSM6DSR_finite_state_machine
9834 * @brief This section groups all the functions that manage the
9835 * state_machine.
9836 * @{
9837 *
9838 */
9839
9840 /**
9841 * @brief Interrupt status bit for FSM long counter timeout interrupt
9842 * event.[get]
9843 *
9844 * @param ctx Read / write interface definitions.(ptr)
9845 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9846 * @retval Interface status (MANDATORY: return 0 -> no Error).
9847 *
9848 */
lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9849 int32_t lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9850 uint8_t *val)
9851 {
9852 lsm6dsr_emb_func_status_t emb_func_status;
9853 int32_t ret;
9854
9855 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9856
9857 if (ret == 0)
9858 {
9859 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
9860 (uint8_t *)&emb_func_status, 1);
9861 }
9862
9863 if (ret == 0)
9864 {
9865 *val = emb_func_status.is_fsm_lc;
9866 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9867 }
9868
9869 return ret;
9870 }
9871
9872 /**
9873 * @brief Embedded final state machine functions mode.[set]
9874 *
9875 * @param ctx Read / write interface definitions.(ptr)
9876 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
9877 * @retval Interface status (MANDATORY: return 0 -> no Error).
9878 *
9879 */
lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)9880 int32_t lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
9881 {
9882 int32_t ret;
9883
9884 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9885 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9886
9887 if (ret == 0)
9888 {
9889 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9890 (uint8_t *)&emb_func_en_b, 1);
9891 }
9892
9893 if (ret == 0)
9894 {
9895 emb_func_en_b.fsm_en = (uint8_t)val;
9896 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9897 (uint8_t *)&emb_func_en_b, 1);
9898 }
9899
9900 if (ret == 0)
9901 {
9902 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9903 }
9904
9905 return ret;
9906 }
9907
9908 /**
9909 * @brief Embedded final state machine functions mode.[get]
9910 *
9911 * @param ctx Read / write interface definitions.(ptr)
9912 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
9913 * @retval Interface status (MANDATORY: return 0 -> no Error).
9914 *
9915 */
lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)9916 int32_t lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
9917 {
9918 int32_t ret;
9919 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9920
9921 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9922
9923 if (ret == 0)
9924 {
9925 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9926 (uint8_t *)&emb_func_en_b, 1);
9927 }
9928
9929 if (ret == 0)
9930 {
9931 *val = emb_func_en_b.fsm_en;
9932 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9933 (uint8_t *)&emb_func_en_b, 1);
9934 }
9935
9936 if (ret == 0)
9937 {
9938 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9939 }
9940
9941 return ret;
9942 }
9943
9944 /**
9945 * @brief Embedded final state machine functions mode.[set]
9946 *
9947 * @param ctx Read / write interface definitions.(ptr)
9948 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9949 * @retval Interface status (MANDATORY: return 0 -> no Error).
9950 *
9951 */
lsm6dsr_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dsr_emb_fsm_enable_t * val)9952 int32_t lsm6dsr_fsm_enable_set(const stmdev_ctx_t *ctx,
9953 lsm6dsr_emb_fsm_enable_t *val)
9954 {
9955 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9956 int32_t ret;
9957
9958 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9959
9960 if (ret == 0)
9961 {
9962 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_A,
9963 (uint8_t *)&val->fsm_enable_a, 1);
9964 }
9965
9966 if (ret == 0)
9967 {
9968 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_B,
9969 (uint8_t *)&val->fsm_enable_b, 1);
9970 }
9971
9972 if (ret == 0)
9973 {
9974 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9975 (uint8_t *)&emb_func_en_b, 1);
9976 }
9977
9978 if (ret == 0)
9979 {
9980 if ((val->fsm_enable_a.fsm1_en |
9981 val->fsm_enable_a.fsm2_en |
9982 val->fsm_enable_a.fsm3_en |
9983 val->fsm_enable_a.fsm4_en |
9984 val->fsm_enable_a.fsm5_en |
9985 val->fsm_enable_a.fsm6_en |
9986 val->fsm_enable_a.fsm7_en |
9987 val->fsm_enable_a.fsm8_en |
9988 val->fsm_enable_b.fsm9_en |
9989 val->fsm_enable_b.fsm10_en |
9990 val->fsm_enable_b.fsm11_en |
9991 val->fsm_enable_b.fsm12_en |
9992 val->fsm_enable_b.fsm13_en |
9993 val->fsm_enable_b.fsm14_en |
9994 val->fsm_enable_b.fsm15_en |
9995 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
9996 {
9997 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
9998 }
9999
10000 else
10001 {
10002 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
10003 }
10004 }
10005
10006 if (ret == 0)
10007 {
10008 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
10009 (uint8_t *)&emb_func_en_b, 1);
10010 }
10011
10012 if (ret == 0)
10013 {
10014 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10015 }
10016
10017 return ret;
10018 }
10019
10020 /**
10021 * @brief Embedded final state machine functions mode.[get]
10022 *
10023 * @param ctx Read / write interface definitions.(ptr)
10024 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
10025 * @retval Interface status (MANDATORY: return 0 -> no Error).
10026 *
10027 */
lsm6dsr_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dsr_emb_fsm_enable_t * val)10028 int32_t lsm6dsr_fsm_enable_get(const stmdev_ctx_t *ctx,
10029 lsm6dsr_emb_fsm_enable_t *val)
10030 {
10031 int32_t ret;
10032
10033 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10034
10035 if (ret == 0)
10036 {
10037 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_A,
10038 (uint8_t *)&val->fsm_enable_a, 1);
10039 }
10040
10041 if (ret == 0)
10042 {
10043 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_B,
10044 (uint8_t *)&val->fsm_enable_b, 1);
10045 }
10046
10047 if (ret == 0)
10048 {
10049 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10050 }
10051
10052 return ret;
10053 }
10054
10055 /**
10056 * @brief FSM long counter status register. Long counter value is an
10057 * unsigned integer value (16-bit format).[set]
10058 *
10059 * @param ctx Read / write interface definitions.(ptr)
10060 * @param buff Buffer that contains data to write
10061 * @retval Interface status (MANDATORY: return 0 -> no Error).
10062 *
10063 */
lsm6dsr_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)10064 int32_t lsm6dsr_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
10065 {
10066 uint8_t buff[2];
10067 int32_t ret;
10068
10069 buff[1] = (uint8_t)(val / 256U);
10070 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10071 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10072
10073 if (ret == 0)
10074 {
10075 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff,
10076 2);
10077 }
10078
10079 if (ret == 0)
10080 {
10081 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10082 }
10083
10084 return ret;
10085 }
10086
10087 /**
10088 * @brief FSM long counter status register. Long counter value is an
10089 * unsigned integer value (16-bit format).[get]
10090 *
10091 * @param ctx Read / write interface definitions.(ptr)
10092 * @param buff Buffer that stores data read
10093 * @retval Interface status (MANDATORY: return 0 -> no Error).
10094 *
10095 */
lsm6dsr_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)10096 int32_t lsm6dsr_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
10097 {
10098 uint8_t buff[2];
10099 int32_t ret;
10100
10101 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10102
10103 if (ret == 0)
10104 {
10105 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff,
10106 2);
10107 *val = buff[1];
10108 *val = (*val * 256U) + buff[0];
10109 }
10110
10111 if (ret == 0)
10112 {
10113 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10114 }
10115
10116 return ret;
10117 }
10118
10119 /**
10120 * @brief Clear FSM long counter value.[set]
10121 *
10122 * @param ctx Read / write interface definitions.(ptr)
10123 * @param val Change the values of fsm_lc_clr in reg
10124 * FSM_LONG_COUNTER_CLEAR
10125 * @retval Interface status (MANDATORY: return 0 -> no Error).
10126 *
10127 */
lsm6dsr_long_clr_set(const stmdev_ctx_t * ctx,lsm6dsr_fsm_lc_clr_t val)10128 int32_t lsm6dsr_long_clr_set(const stmdev_ctx_t *ctx,
10129 lsm6dsr_fsm_lc_clr_t val)
10130 {
10131 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
10132 int32_t ret;
10133
10134 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10135
10136 if (ret == 0)
10137 {
10138 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
10139 (uint8_t *)&fsm_long_counter_clear, 1);
10140 }
10141
10142 if (ret == 0)
10143 {
10144 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
10145 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
10146 (uint8_t *)&fsm_long_counter_clear, 1);
10147 }
10148
10149 if (ret == 0)
10150 {
10151 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10152 }
10153
10154 return ret;
10155 }
10156
10157 /**
10158 * @brief Clear FSM long counter value.[get]
10159 *
10160 * @param ctx Read / write interface definitions.(ptr)
10161 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
10162 * @retval Interface status (MANDATORY: return 0 -> no Error).
10163 *
10164 */
lsm6dsr_long_clr_get(const stmdev_ctx_t * ctx,lsm6dsr_fsm_lc_clr_t * val)10165 int32_t lsm6dsr_long_clr_get(const stmdev_ctx_t *ctx,
10166 lsm6dsr_fsm_lc_clr_t *val)
10167 {
10168 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
10169 int32_t ret;
10170
10171 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10172
10173 if (ret == 0)
10174 {
10175 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
10176 (uint8_t *)&fsm_long_counter_clear, 1);
10177 }
10178
10179 if (ret == 0)
10180 {
10181 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10182 }
10183
10184 switch (fsm_long_counter_clear.fsm_lc_clr)
10185 {
10186 case LSM6DSR_LC_NORMAL:
10187 *val = LSM6DSR_LC_NORMAL;
10188 break;
10189
10190 case LSM6DSR_LC_CLEAR:
10191 *val = LSM6DSR_LC_CLEAR;
10192 break;
10193
10194 case LSM6DSR_LC_CLEAR_DONE:
10195 *val = LSM6DSR_LC_CLEAR_DONE;
10196 break;
10197
10198 default:
10199 *val = LSM6DSR_LC_NORMAL;
10200 break;
10201 }
10202
10203 return ret;
10204 }
10205
10206 /**
10207 * @brief FSM output registers.[get]
10208 *
10209 * @param ctx Read / write interface definitions.(ptr)
10210 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
10211 * @retval Interface status (MANDATORY: return 0 -> no Error).
10212 *
10213 */
lsm6dsr_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsr_fsm_out_t * val)10214 int32_t lsm6dsr_fsm_out_get(const stmdev_ctx_t *ctx,
10215 lsm6dsr_fsm_out_t *val)
10216 {
10217 int32_t ret;
10218
10219 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10220
10221 if (ret == 0)
10222 {
10223 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_OUTS1,
10224 (uint8_t *)&val->fsm_outs1, 16);
10225 }
10226
10227 if (ret == 0)
10228 {
10229 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10230 }
10231
10232 return ret;
10233 }
10234
10235 /**
10236 * @brief Finite State Machine ODR configuration.[set]
10237 *
10238 * @param ctx Read / write interface definitions.(ptr)
10239 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10240 * @retval Interface status (MANDATORY: return 0 -> no Error).
10241 *
10242 */
lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsr_fsm_odr_t val)10243 int32_t lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t *ctx,
10244 lsm6dsr_fsm_odr_t val)
10245 {
10246 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10247 int32_t ret;
10248
10249 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10250
10251 if (ret == 0)
10252 {
10253 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
10254 (uint8_t *)&emb_func_odr_cfg_b, 1);
10255 }
10256
10257 if (ret == 0)
10258 {
10259 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
10260 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
10261 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
10262 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
10263 (uint8_t *)&emb_func_odr_cfg_b, 1);
10264 }
10265
10266 if (ret == 0)
10267 {
10268 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10269 }
10270
10271 return ret;
10272 }
10273
10274 /**
10275 * @brief Finite State Machine ODR configuration.[get]
10276 *
10277 * @param ctx Read / write interface definitions.(ptr)
10278 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10279 * @retval Interface status (MANDATORY: return 0 -> no Error).
10280 *
10281 */
lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsr_fsm_odr_t * val)10282 int32_t lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t *ctx,
10283 lsm6dsr_fsm_odr_t *val)
10284 {
10285 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10286 int32_t ret;
10287
10288 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10289
10290 if (ret == 0)
10291 {
10292 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
10293 (uint8_t *)&emb_func_odr_cfg_b, 1);
10294 }
10295
10296 if (ret == 0)
10297 {
10298 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10299 }
10300
10301 switch (emb_func_odr_cfg_b.fsm_odr)
10302 {
10303 case LSM6DSR_ODR_FSM_12Hz5:
10304 *val = LSM6DSR_ODR_FSM_12Hz5;
10305 break;
10306
10307 case LSM6DSR_ODR_FSM_26Hz:
10308 *val = LSM6DSR_ODR_FSM_26Hz;
10309 break;
10310
10311 case LSM6DSR_ODR_FSM_52Hz:
10312 *val = LSM6DSR_ODR_FSM_52Hz;
10313 break;
10314
10315 case LSM6DSR_ODR_FSM_104Hz:
10316 *val = LSM6DSR_ODR_FSM_104Hz;
10317 break;
10318
10319 default:
10320 *val = LSM6DSR_ODR_FSM_12Hz5;
10321 break;
10322 }
10323
10324 return ret;
10325 }
10326
10327 /**
10328 * @brief FSM initialization request.[set]
10329 *
10330 * @param ctx Read / write interface definitions.(ptr)
10331 * @param val Change the values of fsm_init in reg FSM_INIT
10332 * @retval Interface status (MANDATORY: return 0 -> no Error).
10333 *
10334 */
lsm6dsr_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)10335 int32_t lsm6dsr_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
10336 {
10337 lsm6dsr_emb_func_init_b_t emb_func_init_b;
10338 int32_t ret;
10339
10340 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10341
10342 if (ret == 0)
10343 {
10344 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10345 (uint8_t *)&emb_func_init_b, 1);
10346 }
10347
10348 if (ret == 0)
10349 {
10350 emb_func_init_b.fsm_init = (uint8_t)val;
10351 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10352 (uint8_t *)&emb_func_init_b, 1);
10353 }
10354
10355 if (ret == 0)
10356 {
10357 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10358 }
10359
10360 return ret;
10361 }
10362
10363 /**
10364 * @brief FSM initialization request.[get]
10365 *
10366 * @param ctx Read / write interface definitions.(ptr)
10367 * @param val Change the values of fsm_init in reg FSM_INIT
10368 * @retval Interface status (MANDATORY: return 0 -> no Error).
10369 *
10370 */
lsm6dsr_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)10371 int32_t lsm6dsr_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
10372 {
10373 lsm6dsr_emb_func_init_b_t emb_func_init_b;
10374 int32_t ret;
10375
10376 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10377
10378 if (ret == 0)
10379 {
10380 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10381 (uint8_t *)&emb_func_init_b, 1);
10382 }
10383
10384 if (ret == 0)
10385 {
10386 *val = emb_func_init_b.fsm_init;
10387 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10388 }
10389
10390 return ret;
10391 }
10392
10393 /**
10394 * @brief FSM long counter timeout register (r/w). The long counter
10395 * timeout value is an unsigned integer value (16-bit format).
10396 * When the long counter value reached this value, the FSM
10397 * generates an interrupt.[set]
10398 *
10399 * @param ctx Read / write interface definitions.(ptr)
10400 * @param buff Buffer that contains data to write
10401 * @retval Interface status (MANDATORY: return 0 -> no Error).
10402 *
10403 */
lsm6dsr_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)10404 int32_t lsm6dsr_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
10405 uint16_t val)
10406 {
10407 uint8_t buff[2];
10408 int32_t ret;
10409
10410 buff[1] = (uint8_t)(val / 256U);
10411 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10412 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
10413 &buff[0]);
10414
10415 if (ret == 0)
10416 {
10417 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
10418 &buff[1]);
10419 }
10420
10421 return ret;
10422 }
10423
10424 /**
10425 * @brief FSM long counter timeout register (r/w). The long counter
10426 * timeout value is an unsigned integer value (16-bit format).
10427 * When the long counter value reached this value, the FSM generates
10428 * an interrupt.[get]
10429 *
10430 * @param ctx Read / write interface definitions.(ptr)
10431 * @param buff Buffer that stores data read
10432 * @retval Interface status (MANDATORY: return 0 -> no Error).
10433 *
10434 */
lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)10435 int32_t lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
10436 uint16_t *val)
10437 {
10438 uint8_t buff[2];
10439 int32_t ret;
10440
10441 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
10442 &buff[0]);
10443
10444 if (ret == 0)
10445 {
10446 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
10447 &buff[1]);
10448 *val = buff[1];
10449 *val = (*val * 256U) + buff[0];
10450 }
10451
10452 return ret;
10453 }
10454
10455 /**
10456 * @brief FSM number of programs register.[set]
10457 *
10458 * @param ctx Read / write interface definitions.(ptr)
10459 * @param buff Buffer that contains data to write
10460 * @retval Interface status (MANDATORY: return 0 -> no Error).
10461 *
10462 */
lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)10463 int32_t lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
10464 uint8_t *buff)
10465 {
10466 int32_t ret;
10467
10468 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff);
10469
10470 if (ret == 0)
10471 {
10472 ret = lsm6dsr_ln_pg_write_byte(ctx,
10473 LSM6DSR_FSM_PROGRAMS + 0x01U,
10474 buff);
10475 }
10476
10477 return ret;
10478 }
10479
10480 /**
10481 * @brief FSM number of programs register.[get]
10482 *
10483 * @param ctx Read / write interface definitions.(ptr)
10484 * @param buff Buffer that stores data read
10485 * @retval Interface status (MANDATORY: return 0 -> no Error).
10486 *
10487 */
lsm6dsr_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)10488 int32_t lsm6dsr_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
10489 uint8_t *buff)
10490 {
10491 int32_t ret;
10492
10493 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff);
10494
10495 return ret;
10496 }
10497
10498 /**
10499 * @brief FSM start address register (r/w). First available address is
10500 * 0x033C.[set]
10501 *
10502 * @param ctx Read / write interface definitions.(ptr)
10503 * @param buff Buffer that contains data to write
10504 * @retval Interface status (MANDATORY: return 0 -> no Error).
10505 *
10506 */
lsm6dsr_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)10507 int32_t lsm6dsr_fsm_start_address_set(const stmdev_ctx_t *ctx,
10508 uint16_t val)
10509 {
10510 uint8_t buff[2];
10511 int32_t ret;
10512
10513 buff[1] = (uint8_t)(val / 256U);
10514 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10515 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_L,
10516 &buff[0]);
10517
10518 if (ret == 0)
10519 {
10520 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_H,
10521 &buff[1]);
10522 }
10523
10524 return ret;
10525 }
10526
10527 /**
10528 * @brief FSM start address register (r/w). First available address
10529 * is 0x033C.[get]
10530 *
10531 * @param ctx Read / write interface definitions.(ptr)
10532 * @param buff Buffer that stores data read
10533 * @retval Interface status (MANDATORY: return 0 -> no Error).
10534 *
10535 */
lsm6dsr_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)10536 int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx,
10537 uint16_t *val)
10538 {
10539 uint8_t buff[2];
10540 int32_t ret;
10541
10542 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_L,
10543 &buff[0]);
10544
10545 if (ret == 0)
10546 {
10547 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_H,
10548 &buff[1]);
10549 *val = buff[1];
10550 *val = (*val * 256U) + buff[0];
10551 }
10552
10553 return ret;
10554 }
10555
10556 /**
10557 * @}
10558 *
10559 */
10560
10561 /**
10562 * @defgroup LSM6DSR_Sensor_hub
10563 * @brief This section groups all the functions that manage the
10564 * sensor hub.
10565 * @{
10566 *
10567 */
10568
10569 /**
10570 * @brief Sensor hub output registers.[get]
10571 *
10572 * @param ctx Read / write interface definitions.(ptr)
10573 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10574 * @retval Interface status (MANDATORY: return 0 -> no Error).
10575 *
10576 */
lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dsr_emb_sh_read_t * val,uint8_t len)10577 int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
10578 lsm6dsr_emb_sh_read_t *val,
10579 uint8_t len)
10580 {
10581 int32_t ret;
10582
10583 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10584
10585 if (ret == 0)
10586 {
10587 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SENSOR_HUB_1,
10588 (uint8_t *)val, len);
10589 }
10590
10591 if (ret == 0)
10592 {
10593 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10594 }
10595
10596 return ret;
10597 }
10598
10599 /**
10600 * @brief Number of external sensors to be read by the sensor hub.[set]
10601 *
10602 * @param ctx Read / write interface definitions.(ptr)
10603 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
10604 * @retval Interface status (MANDATORY: return 0 -> no Error).
10605 *
10606 */
lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsr_aux_sens_on_t val)10607 int32_t lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t *ctx,
10608 lsm6dsr_aux_sens_on_t val)
10609 {
10610 lsm6dsr_master_config_t master_config;
10611 int32_t ret;
10612
10613 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10614
10615 if (ret == 0)
10616 {
10617 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10618 (uint8_t *)&master_config, 1);
10619 }
10620
10621 if (ret == 0)
10622 {
10623 master_config.aux_sens_on = (uint8_t)val;
10624 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10625 (uint8_t *)&master_config, 1);
10626 }
10627
10628 if (ret == 0)
10629 {
10630 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10631 }
10632
10633 return ret;
10634 }
10635
10636 /**
10637 * @brief Number of external sensors to be read by the sensor hub.[get]
10638 *
10639 * @param ctx Read / write interface definitions.(ptr)
10640 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10641 * @retval Interface status (MANDATORY: return 0 -> no Error).
10642 *
10643 */
lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsr_aux_sens_on_t * val)10644 int32_t lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t *ctx,
10645 lsm6dsr_aux_sens_on_t *val)
10646 {
10647 lsm6dsr_master_config_t master_config;
10648 int32_t ret;
10649
10650 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10651
10652 if (ret == 0)
10653 {
10654 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10655 (uint8_t *)&master_config, 1);
10656 }
10657
10658 if (ret == 0)
10659 {
10660 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10661 }
10662
10663 switch (master_config.aux_sens_on)
10664 {
10665 case LSM6DSR_SLV_0:
10666 *val = LSM6DSR_SLV_0;
10667 break;
10668
10669 case LSM6DSR_SLV_0_1:
10670 *val = LSM6DSR_SLV_0_1;
10671 break;
10672
10673 case LSM6DSR_SLV_0_1_2:
10674 *val = LSM6DSR_SLV_0_1_2;
10675 break;
10676
10677 case LSM6DSR_SLV_0_1_2_3:
10678 *val = LSM6DSR_SLV_0_1_2_3;
10679 break;
10680
10681 default:
10682 *val = LSM6DSR_SLV_0;
10683 break;
10684 }
10685
10686 return ret;
10687 }
10688
10689 /**
10690 * @brief Sensor hub I2C master enable.[set]
10691 *
10692 * @param ctx Read / write interface definitions.(ptr)
10693 * @param val Change the values of master_on in reg MASTER_CONFIG
10694 * @retval Interface status (MANDATORY: return 0 -> no Error).
10695 *
10696 */
lsm6dsr_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)10697 int32_t lsm6dsr_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
10698 {
10699 lsm6dsr_master_config_t master_config;
10700 int32_t ret;
10701
10702 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10703
10704 if (ret == 0)
10705 {
10706 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10707 (uint8_t *)&master_config, 1);
10708 }
10709
10710 if (ret == 0)
10711 {
10712 master_config.master_on = (uint8_t)val;
10713 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10714 (uint8_t *)&master_config, 1);
10715 }
10716
10717 if (ret == 0)
10718 {
10719 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10720 }
10721
10722 return ret;
10723 }
10724
10725 /**
10726 * @brief Sensor hub I2C master enable.[get]
10727 *
10728 * @param ctx Read / write interface definitions.(ptr)
10729 * @param val Change the values of master_on in reg MASTER_CONFIG
10730 * @retval Interface status (MANDATORY: return 0 -> no Error).
10731 *
10732 */
lsm6dsr_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)10733 int32_t lsm6dsr_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
10734 {
10735 lsm6dsr_master_config_t master_config;
10736 int32_t ret;
10737
10738 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10739
10740 if (ret == 0)
10741 {
10742 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10743 (uint8_t *)&master_config, 1);
10744 }
10745
10746 if (ret == 0)
10747 {
10748 *val = master_config.master_on;
10749 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10750 }
10751
10752 return ret;
10753 }
10754
10755 /**
10756 * @brief Master I2C pull-up enable.[set]
10757 *
10758 * @param ctx Read / write interface definitions.(ptr)
10759 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
10760 * @retval Interface status (MANDATORY: return 0 -> no Error).
10761 *
10762 */
lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_shub_pu_en_t val)10763 int32_t lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t *ctx,
10764 lsm6dsr_shub_pu_en_t val)
10765 {
10766 lsm6dsr_master_config_t master_config;
10767 int32_t ret;
10768
10769 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10770
10771 if (ret == 0)
10772 {
10773 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10774 (uint8_t *)&master_config, 1);
10775 }
10776
10777 if (ret == 0)
10778 {
10779 master_config.shub_pu_en = (uint8_t)val;
10780 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10781 (uint8_t *)&master_config, 1);
10782 }
10783
10784 if (ret == 0)
10785 {
10786 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10787 }
10788
10789 return ret;
10790 }
10791
10792 /**
10793 * @brief Master I2C pull-up enable.[get]
10794 *
10795 * @param ctx Read / write interface definitions.(ptr)
10796 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
10797 * @retval Interface status (MANDATORY: return 0 -> no Error).
10798 *
10799 */
lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_shub_pu_en_t * val)10800 int32_t lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t *ctx,
10801 lsm6dsr_shub_pu_en_t *val)
10802 {
10803 lsm6dsr_master_config_t master_config;
10804 int32_t ret;
10805
10806 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10807
10808 if (ret == 0)
10809 {
10810 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10811 (uint8_t *)&master_config, 1);
10812 }
10813
10814 if (ret == 0)
10815 {
10816 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10817 }
10818
10819 switch (master_config.shub_pu_en)
10820 {
10821 case LSM6DSR_EXT_PULL_UP:
10822 *val = LSM6DSR_EXT_PULL_UP;
10823 break;
10824
10825 case LSM6DSR_INTERNAL_PULL_UP:
10826 *val = LSM6DSR_INTERNAL_PULL_UP;
10827 break;
10828
10829 default:
10830 *val = LSM6DSR_EXT_PULL_UP;
10831 break;
10832 }
10833
10834 return ret;
10835 }
10836
10837 /**
10838 * @brief I2C interface pass-through.[set]
10839 *
10840 * @param ctx Read / write interface definitions.(ptr)
10841 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
10842 * @retval Interface status (MANDATORY: return 0 -> no Error).
10843 *
10844 */
lsm6dsr_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)10845 int32_t lsm6dsr_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
10846 {
10847 lsm6dsr_master_config_t master_config;
10848 int32_t ret;
10849
10850 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10851
10852 if (ret == 0)
10853 {
10854 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10855 (uint8_t *)&master_config, 1);
10856 }
10857
10858 if (ret == 0)
10859 {
10860 master_config.pass_through_mode = (uint8_t)val;
10861 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10862 (uint8_t *)&master_config, 1);
10863 }
10864
10865 if (ret == 0)
10866 {
10867 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10868 }
10869
10870 return ret;
10871 }
10872
10873 /**
10874 * @brief I2C interface pass-through.[get]
10875 *
10876 * @param ctx Read / write interface definitions.(ptr)
10877 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
10878 * @retval Interface status (MANDATORY: return 0 -> no Error).
10879 *
10880 */
lsm6dsr_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)10881 int32_t lsm6dsr_sh_pass_through_get(const stmdev_ctx_t *ctx,
10882 uint8_t *val)
10883 {
10884 lsm6dsr_master_config_t master_config;
10885 int32_t ret;
10886
10887 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10888
10889 if (ret == 0)
10890 {
10891 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10892 (uint8_t *)&master_config, 1);
10893 }
10894
10895 if (ret == 0)
10896 {
10897 *val = master_config.pass_through_mode;
10898 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10899 }
10900
10901 return ret;
10902 }
10903
10904 /**
10905 * @brief Sensor hub trigger signal selection.[set]
10906 *
10907 * @param ctx Read / write interface definitions.(ptr)
10908 * @param val Change the values of start_config in reg MASTER_CONFIG
10909 * @retval Interface status (MANDATORY: return 0 -> no Error).
10910 *
10911 */
lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_start_config_t val)10912 int32_t lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
10913 lsm6dsr_start_config_t val)
10914 {
10915 lsm6dsr_master_config_t master_config;
10916 int32_t ret;
10917
10918 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10919
10920 if (ret == 0)
10921 {
10922 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10923 (uint8_t *)&master_config, 1);
10924 }
10925
10926 if (ret == 0)
10927 {
10928 master_config.start_config = (uint8_t)val;
10929 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10930 (uint8_t *)&master_config, 1);
10931 }
10932
10933 if (ret == 0)
10934 {
10935 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10936 }
10937
10938 return ret;
10939 }
10940
10941 /**
10942 * @brief Sensor hub trigger signal selection.[get]
10943 *
10944 * @param ctx Read / write interface definitions.(ptr)
10945 * @param val Get the values of start_config in reg MASTER_CONFIG
10946 * @retval Interface status (MANDATORY: return 0 -> no Error).
10947 *
10948 */
lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_start_config_t * val)10949 int32_t lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
10950 lsm6dsr_start_config_t *val)
10951 {
10952 lsm6dsr_master_config_t master_config;
10953 int32_t ret;
10954
10955 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10956
10957 if (ret == 0)
10958 {
10959 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10960 (uint8_t *)&master_config, 1);
10961 }
10962
10963 if (ret == 0)
10964 {
10965 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10966 }
10967
10968 switch (master_config.start_config)
10969 {
10970 case LSM6DSR_EXT_ON_INT2_PIN:
10971 *val = LSM6DSR_EXT_ON_INT2_PIN;
10972 break;
10973
10974 case LSM6DSR_XL_GY_DRDY:
10975 *val = LSM6DSR_XL_GY_DRDY;
10976 break;
10977
10978 default:
10979 *val = LSM6DSR_EXT_ON_INT2_PIN;
10980 break;
10981 }
10982
10983 return ret;
10984 }
10985
10986 /**
10987 * @brief Slave 0 write operation is performed only at the first sensor
10988 * hub cycle.[set]
10989 *
10990 * @param ctx Read / write interface definitions.(ptr)
10991 * @param val Change the values of write_once in reg MASTER_CONFIG
10992 * @retval Interface status (MANDATORY: return 0 -> no Error).
10993 *
10994 */
lsm6dsr_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsr_write_once_t val)10995 int32_t lsm6dsr_sh_write_mode_set(const stmdev_ctx_t *ctx,
10996 lsm6dsr_write_once_t val)
10997 {
10998 lsm6dsr_master_config_t master_config;
10999 int32_t ret;
11000
11001 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11002
11003 if (ret == 0)
11004 {
11005 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
11006 (uint8_t *)&master_config, 1);
11007 }
11008
11009 if (ret == 0)
11010 {
11011 master_config.write_once = (uint8_t)val;
11012 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
11013 (uint8_t *)&master_config, 1);
11014 }
11015
11016 if (ret == 0)
11017 {
11018 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11019 }
11020
11021 return ret;
11022 }
11023
11024 /**
11025 * @brief Slave 0 write operation is performed only at the first sensor
11026 * hub cycle.[get]
11027 *
11028 * @param ctx Read / write interface definitions.(ptr)
11029 * @param val Get the values of write_once in reg MASTER_CONFIG
11030 * @retval Interface status (MANDATORY: return 0 -> no Error).
11031 *
11032 */
lsm6dsr_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsr_write_once_t * val)11033 int32_t lsm6dsr_sh_write_mode_get(const stmdev_ctx_t *ctx,
11034 lsm6dsr_write_once_t *val)
11035 {
11036 lsm6dsr_master_config_t master_config;
11037 int32_t ret;
11038
11039 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11040
11041 if (ret == 0)
11042 {
11043 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
11044 (uint8_t *)&master_config, 1);
11045 }
11046
11047 if (ret == 0)
11048 {
11049 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11050 }
11051
11052 switch (master_config.write_once)
11053 {
11054 case LSM6DSR_EACH_SH_CYCLE:
11055 *val = LSM6DSR_EACH_SH_CYCLE;
11056 break;
11057
11058 case LSM6DSR_ONLY_FIRST_CYCLE:
11059 *val = LSM6DSR_ONLY_FIRST_CYCLE;
11060 break;
11061
11062 default:
11063 *val = LSM6DSR_EACH_SH_CYCLE;
11064 break;
11065 }
11066
11067 return ret;
11068 }
11069
11070 /**
11071 * @brief Reset Master logic and output registers.[set]
11072 *
11073 * @param ctx Read / write interface definitions.(ptr)
11074 * @retval Interface status (MANDATORY: return 0 -> no Error).
11075 *
11076 */
lsm6dsr_sh_reset_set(const stmdev_ctx_t * ctx)11077 int32_t lsm6dsr_sh_reset_set(const stmdev_ctx_t *ctx)
11078 {
11079 lsm6dsr_master_config_t master_config;
11080 int32_t ret;
11081
11082 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11083
11084 if (ret == 0)
11085 {
11086 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
11087 (uint8_t *)&master_config, 1);
11088 }
11089
11090 if (ret == 0)
11091 {
11092 master_config.rst_master_regs = PROPERTY_ENABLE;
11093 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
11094 (uint8_t *)&master_config, 1);
11095 }
11096
11097 if (ret == 0)
11098 {
11099 master_config.rst_master_regs = PROPERTY_DISABLE;
11100 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
11101 (uint8_t *)&master_config, 1);
11102 }
11103
11104 if (ret == 0)
11105 {
11106 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11107 }
11108
11109 return ret;
11110 }
11111
11112 /**
11113 * @brief Reset Master logic and output registers.[get]
11114 *
11115 * @param ctx Read / write interface definitions.(ptr)
11116 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
11117 * @retval Interface status (MANDATORY: return 0 -> no Error).
11118 *
11119 */
lsm6dsr_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)11120 int32_t lsm6dsr_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
11121 {
11122 lsm6dsr_master_config_t master_config;
11123 int32_t ret;
11124
11125 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11126
11127 if (ret == 0)
11128 {
11129 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
11130 (uint8_t *)&master_config, 1);
11131 *val = master_config.rst_master_regs;
11132 }
11133
11134 if (ret == 0)
11135 {
11136 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11137 }
11138
11139 return ret;
11140 }
11141
11142 /**
11143 * @brief Rate at which the master communicates.[set]
11144 *
11145 * @param ctx Read / write interface definitions.(ptr)
11146 * @param val Change the values of shub_odr in reg SLV0_CONFIG
11147 * @retval Interface status (MANDATORY: return 0 -> no Error).
11148 *
11149 */
lsm6dsr_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsr_shub_odr_t val)11150 int32_t lsm6dsr_sh_data_rate_set(const stmdev_ctx_t *ctx,
11151 lsm6dsr_shub_odr_t val)
11152 {
11153 lsm6dsr_slv0_config_t slv0_config;
11154 int32_t ret;
11155
11156 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11157
11158 if (ret == 0)
11159 {
11160 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
11161 (uint8_t *)&slv0_config, 1);
11162 }
11163
11164 if (ret == 0)
11165 {
11166 slv0_config.shub_odr = (uint8_t)val;
11167 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
11168 (uint8_t *)&slv0_config, 1);
11169 }
11170
11171 if (ret == 0)
11172 {
11173 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11174 }
11175
11176 return ret;
11177 }
11178
11179 /**
11180 * @brief Rate at which the master communicates.[get]
11181 *
11182 * @param ctx Read / write interface definitions.(ptr)
11183 * @param val Get the values of shub_odr in reg slv1_CONFIG
11184 * @retval Interface status (MANDATORY: return 0 -> no Error).
11185 *
11186 */
lsm6dsr_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsr_shub_odr_t * val)11187 int32_t lsm6dsr_sh_data_rate_get(const stmdev_ctx_t *ctx,
11188 lsm6dsr_shub_odr_t *val)
11189 {
11190 lsm6dsr_slv0_config_t slv0_config;
11191 int32_t ret;
11192
11193 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11194
11195 if (ret == 0)
11196 {
11197 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
11198 (uint8_t *)&slv0_config, 1);
11199 }
11200
11201 if (ret == 0)
11202 {
11203 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11204 }
11205
11206 switch (slv0_config.shub_odr)
11207 {
11208 case LSM6DSR_SH_ODR_104Hz:
11209 *val = LSM6DSR_SH_ODR_104Hz;
11210 break;
11211
11212 case LSM6DSR_SH_ODR_52Hz:
11213 *val = LSM6DSR_SH_ODR_52Hz;
11214 break;
11215
11216 case LSM6DSR_SH_ODR_26Hz:
11217 *val = LSM6DSR_SH_ODR_26Hz;
11218 break;
11219
11220 case LSM6DSR_SH_ODR_13Hz:
11221 *val = LSM6DSR_SH_ODR_13Hz;
11222 break;
11223
11224 default:
11225 *val = LSM6DSR_SH_ODR_104Hz;
11226 break;
11227 }
11228
11229 return ret;
11230 }
11231
11232 /**
11233 * @brief Configure slave 0 for perform a write.[set]
11234 *
11235 * @param ctx Read / write interface definitions.(ptr)
11236 * @param val Structure that contain
11237 * - uint8_t slv0_add; 8 bit i2c device address
11238 * - uint8_t slv0_subadd; 8 bit register device address
11239 * - uint8_t slv0_data; 8 bit data to write
11240 * @retval Interface status (MANDATORY: return 0 -> no Error).
11241 *
11242 */
lsm6dsr_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_write_t * val)11243 int32_t lsm6dsr_sh_cfg_write(const stmdev_ctx_t *ctx,
11244 lsm6dsr_sh_cfg_write_t *val)
11245 {
11246 lsm6dsr_slv0_add_t slv0_add;
11247 int32_t ret;
11248
11249 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11250
11251 if (ret == 0)
11252 {
11253 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
11254 slv0_add.rw_0 = 0;
11255 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
11256 (uint8_t *) & (slv0_add), 1);
11257 }
11258
11259 if (ret == 0)
11260 {
11261 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
11262 (uint8_t *) & (val->slv0_subadd), 1);
11263 }
11264
11265 if (ret == 0)
11266 {
11267 ret = lsm6dsr_write_reg(ctx, LSM6DSR_DATAWRITE_SLV0,
11268 (uint8_t *) & (val->slv0_data), 1);
11269 }
11270
11271 if (ret == 0)
11272 {
11273 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11274 }
11275
11276 return ret;
11277 }
11278
11279 /**
11280 * @brief Configure slave 0 for perform a write/read.[get]
11281 *
11282 * @param ctx Read / write interface definitions.(ptr)
11283 * @param val Structure that contain
11284 * - uint8_t slv_add; 8 bit i2c device address
11285 * - uint8_t slv_subadd; 8 bit register device address
11286 * - uint8_t slv_len; num of bit to read
11287 * @retval Interface status (MANDATORY: return 0 -> no Error).
11288 *
11289 */
lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11290 int32_t lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
11291 lsm6dsr_sh_cfg_read_t *val)
11292 {
11293 lsm6dsr_slv0_config_t slv0_config;
11294 lsm6dsr_slv0_add_t slv0_add;
11295 int32_t ret;
11296
11297 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11298
11299 if (ret == 0)
11300 {
11301 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
11302 slv0_add.rw_0 = 1;
11303 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
11304 (uint8_t *) & (slv0_add), 1);
11305 }
11306
11307 if (ret == 0)
11308 {
11309 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
11310 &(val->slv_subadd), 1);
11311 }
11312
11313 if (ret == 0)
11314 {
11315 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
11316 (uint8_t *)&slv0_config, 1);
11317 }
11318
11319 if (ret == 0)
11320 {
11321 slv0_config.slave0_numop = val->slv_len;
11322 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
11323 (uint8_t *)&slv0_config, 1);
11324 }
11325
11326 if (ret == 0)
11327 {
11328 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11329 }
11330
11331 return ret;
11332 }
11333
11334 /**
11335 * @brief Configure slave 0 for perform a write/read.[get]
11336 *
11337 * @param ctx Read / write interface definitions.(ptr)
11338 * @param val Structure that contain
11339 * - uint8_t slv_add; 8 bit i2c device address
11340 * - uint8_t slv_subadd; 8 bit register device address
11341 * - uint8_t slv_len; num of bit to read
11342 * @retval Interface status (MANDATORY: return 0 -> no Error).
11343 *
11344 */
lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11345 int32_t lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
11346 lsm6dsr_sh_cfg_read_t *val)
11347 {
11348 lsm6dsr_slv1_config_t slv1_config;
11349 lsm6dsr_slv1_add_t slv1_add;
11350 int32_t ret;
11351
11352 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11353
11354 if (ret == 0)
11355 {
11356 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
11357 slv1_add.r_1 = 1;
11358 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_ADD,
11359 (uint8_t *)&slv1_add, 1);
11360 }
11361
11362 if (ret == 0)
11363 {
11364 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_SUBADD,
11365 &(val->slv_subadd), 1);
11366 }
11367
11368 if (ret == 0)
11369 {
11370 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
11371 (uint8_t *)&slv1_config, 1);
11372 }
11373
11374 if (ret == 0)
11375 {
11376 slv1_config.slave1_numop = val->slv_len;
11377 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
11378 (uint8_t *)&slv1_config, 1);
11379 }
11380
11381 if (ret == 0)
11382 {
11383 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11384 }
11385
11386 return ret;
11387 }
11388
11389 /**
11390 * @brief Configure slave 2 for perform a write/read.[get]
11391 *
11392 * @param ctx Read / write interface definitions.(ptr)
11393 * @param val Structure that contain
11394 * - uint8_t slv_add; 8 bit i2c device address
11395 * - uint8_t slv_subadd; 8 bit register device address
11396 * - uint8_t slv_len; num of bit to read
11397 * @retval Interface status (MANDATORY: return 0 -> no Error).
11398 *
11399 */
lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11400 int32_t lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
11401 lsm6dsr_sh_cfg_read_t *val)
11402 {
11403 lsm6dsr_slv2_config_t slv2_config;
11404 lsm6dsr_slv2_add_t slv2_add;
11405 int32_t ret;
11406
11407 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11408
11409 if (ret == 0)
11410 {
11411 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
11412 slv2_add.r_2 = 1;
11413 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_ADD,
11414 (uint8_t *)&slv2_add, 1);
11415 }
11416
11417 if (ret == 0)
11418 {
11419 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_SUBADD,
11420 (uint8_t *) & (val->slv_subadd), 1);
11421 }
11422
11423 if (ret == 0)
11424 {
11425 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
11426 (uint8_t *)&slv2_config, 1);
11427 }
11428
11429 if (ret == 0)
11430 {
11431 slv2_config.slave2_numop = val->slv_len;
11432 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
11433 (uint8_t *)&slv2_config, 1);
11434 }
11435
11436 if (ret == 0)
11437 {
11438 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11439 }
11440
11441 return ret;
11442 }
11443
11444 /**
11445 * @brief Configure slave 3 for perform a write/read.[get]
11446 *
11447 * @param ctx Read / write interface definitions.(ptr)
11448 * @param val Structure that contain
11449 * - uint8_t slv_add; 8 bit i2c device address
11450 * - uint8_t slv_subadd; 8 bit register device address
11451 * - uint8_t slv_len; num of bit to read
11452 * @retval Interface status (MANDATORY: return 0 -> no Error).
11453 *
11454 */
lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11455 int32_t lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
11456 lsm6dsr_sh_cfg_read_t *val)
11457 {
11458 lsm6dsr_slv3_config_t slv3_config;
11459 lsm6dsr_slv3_add_t slv3_add;
11460 int32_t ret;
11461
11462 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11463
11464 if (ret == 0)
11465 {
11466 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
11467 slv3_add.r_3 = 1;
11468 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_ADD,
11469 (uint8_t *)&slv3_add, 1);
11470 }
11471
11472 if (ret == 0)
11473 {
11474 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_SUBADD,
11475 &(val->slv_subadd), 1);
11476 }
11477
11478 if (ret == 0)
11479 {
11480 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
11481 (uint8_t *)&slv3_config, 1);
11482 }
11483
11484 if (ret == 0)
11485 {
11486 slv3_config.slave3_numop = val->slv_len;
11487 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
11488 (uint8_t *)&slv3_config, 1);
11489 }
11490
11491 if (ret == 0)
11492 {
11493 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11494 }
11495
11496 return ret;
11497 }
11498
11499 /**
11500 * @brief Sensor hub source register.[get]
11501 *
11502 * @param ctx Read / write interface definitions.(ptr)
11503 * @param val Registers from STATUS_MASTER
11504 * @retval Interface status (MANDATORY: return 0 -> no Error).
11505 *
11506 */
lsm6dsr_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsr_status_master_t * val)11507 int32_t lsm6dsr_sh_status_get(const stmdev_ctx_t *ctx,
11508 lsm6dsr_status_master_t *val)
11509 {
11510 int32_t ret;
11511
11512 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11513
11514 if (ret == 0)
11515 {
11516 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_MASTER,
11517 (uint8_t *)val, 1);
11518 }
11519
11520 if (ret == 0)
11521 {
11522 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11523 }
11524
11525 return ret;
11526 }
11527
11528 /**
11529 * @}
11530 *
11531 */
11532
11533 /**
11534 * @defgroup LSM6DSR_Sensors for Smart Mobile Devices
11535 * @brief This section groups all the functions that manage the
11536 * Sensors for Smart Mobile Devices.
11537 * @{
11538 *
11539 */
11540
11541 /**
11542 * @brief Sensor synchronization time frame resolution[set]
11543 *
11544 * @param ctx Read / write interface definitions.(ptr)
11545 * @param val Change the values of tph_h_sel in LSM6DSR_S4S_TPH_L
11546 * @retval Interface status (MANDATORY: return 0 -> no Error).
11547 *
11548 */
lsm6dsr_s4s_tph_res_set(const stmdev_ctx_t * ctx,lsm6dsr_s4s_tph_res_t val)11549 int32_t lsm6dsr_s4s_tph_res_set(const stmdev_ctx_t *ctx,
11550 lsm6dsr_s4s_tph_res_t val)
11551 {
11552 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11553 int32_t ret;
11554
11555 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11556
11557 if (ret == 0)
11558 {
11559 s4s_tph_l.tph_h_sel = (uint8_t)val;
11560 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
11561 (uint8_t *)&s4s_tph_l, 1);
11562 }
11563
11564 return ret;
11565 }
11566
11567 /**
11568 * @brief Sensor synchronization time frame resolution.[get]
11569 *
11570 * @param ctx Read / write interface definitions.(ptr)
11571 * @param val Get the values of tph_h_sel in LSM6DSR_S4S_TPH_L
11572 * @retval Interface status (MANDATORY: return 0 -> no Error).
11573 *
11574 */
lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t * ctx,lsm6dsr_s4s_tph_res_t * val)11575 int32_t lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t *ctx,
11576 lsm6dsr_s4s_tph_res_t *val)
11577 {
11578 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11579 int32_t ret;
11580
11581 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11582
11583 switch (s4s_tph_l.tph_h_sel)
11584 {
11585 case LSM6DSR_S4S_TPH_7bit:
11586 *val = LSM6DSR_S4S_TPH_7bit;
11587 break;
11588
11589 case LSM6DSR_S4S_TPH_15bit:
11590 *val = LSM6DSR_S4S_TPH_15bit;
11591 break;
11592
11593 default:
11594 *val = LSM6DSR_S4S_TPH_7bit;
11595 break;
11596 }
11597
11598 return ret;
11599 }
11600
11601 /**
11602 * @brief Sensor synchronization time frame.[set]
11603 *
11604 * @param ctx Read / write interface definitions.(ptr)
11605 * @param val Change the values of tph_l in S4S_TPH_L and
11606 * tph_h in S4S_TPH_H
11607 * @retval Interface status (MANDATORY: return 0 -> no Error).
11608 *
11609 */
lsm6dsr_s4s_tph_val_set(const stmdev_ctx_t * ctx,uint16_t val)11610 int32_t lsm6dsr_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val)
11611 {
11612 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11613 lsm6dsr_s4s_tph_h_t s4s_tph_h;
11614 int32_t ret;
11615
11616 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11617
11618 if (ret == 0)
11619 {
11620 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
11621 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
11622 (uint8_t *)&s4s_tph_l, 1);
11623 }
11624
11625 if (ret == 0)
11626 {
11627 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
11628 (uint8_t *)&s4s_tph_h, 1);
11629 }
11630
11631 if (ret == 0)
11632 {
11633 s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
11634 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_H,
11635 (uint8_t *)&s4s_tph_h, 1);
11636 }
11637
11638 return ret;
11639 }
11640
11641 /**
11642 * @brief Sensor synchronization time frame.[get]
11643 *
11644 * @param ctx Read / write interface definitions.(ptr)
11645 * @param val Get the values of tph_l in S4S_TPH_L and tph_h in S4S_TPH_H
11646 * @retval Interface status (MANDATORY: return 0 -> no Error).
11647 *
11648 */
lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t * ctx,uint16_t * val)11649 int32_t lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val)
11650 {
11651 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11652 lsm6dsr_s4s_tph_h_t s4s_tph_h;
11653 int32_t ret;
11654
11655 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11656
11657 if (ret == 0)
11658 {
11659 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
11660 (uint8_t *)&s4s_tph_h, 1);
11661 }
11662
11663 *val = s4s_tph_h.tph_h;
11664 *val = *val << 7;
11665 *val += s4s_tph_l.tph_l;
11666
11667 return ret;
11668 }
11669
11670 /**
11671 * @brief Sensor synchronization resolution ratio register.[set]
11672 *
11673 * @param ctx Read / write interface definitions.(ptr)
11674 * @param val Change the values of rr in S4S_RR.
11675 * @retval Interface status (MANDATORY: return 0 -> no Error).
11676 *
11677 */
lsm6dsr_s4s_res_ratio_set(const stmdev_ctx_t * ctx,lsm6dsr_s4s_res_ratio_t val)11678 int32_t lsm6dsr_s4s_res_ratio_set(const stmdev_ctx_t *ctx,
11679 lsm6dsr_s4s_res_ratio_t val)
11680 {
11681 lsm6dsr_s4s_rr_t s4s_rr;
11682 int32_t ret;
11683
11684 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11685
11686 if (ret == 0)
11687 {
11688 s4s_rr.rr = (uint8_t)val;
11689 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11690 }
11691
11692 return ret;
11693 }
11694
11695 /**
11696 * @brief Sensor synchronization resolution ratio register.[get]
11697 *
11698 * @param ctx Read / write interface definitions.(ptr)
11699 * @param val get the values of rr in S4S_RR
11700 * @retval Interface status (MANDATORY: return 0 -> no Error).
11701 *
11702 */
lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t * ctx,lsm6dsr_s4s_res_ratio_t * val)11703 int32_t lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t *ctx,
11704 lsm6dsr_s4s_res_ratio_t *val)
11705 {
11706 lsm6dsr_s4s_rr_t s4s_rr;
11707 int32_t ret;
11708
11709 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11710
11711 switch (s4s_rr.rr)
11712 {
11713 case LSM6DSR_S4S_DT_RES_11:
11714 *val = LSM6DSR_S4S_DT_RES_11;
11715 break;
11716
11717 case LSM6DSR_S4S_DT_RES_12:
11718 *val = LSM6DSR_S4S_DT_RES_12;
11719 break;
11720
11721 case LSM6DSR_S4S_DT_RES_13:
11722 *val = LSM6DSR_S4S_DT_RES_13;
11723 break;
11724
11725 case LSM6DSR_S4S_DT_RES_14:
11726 *val = LSM6DSR_S4S_DT_RES_14;
11727 break;
11728
11729 default:
11730 *val = LSM6DSR_S4S_DT_RES_11;
11731 break;
11732 }
11733
11734 return ret;
11735 }
11736
11737 /**
11738 * @brief s4s master command.[set]
11739 *
11740 * @param ctx Read / write interface definitions.(ptr)
11741 * @param val Change the values of S4S_ST_CMD_CODE.
11742 * @retval Interface status (MANDATORY: return 0 -> no Error).
11743 *
11744 */
lsm6dsr_s4s_command_set(const stmdev_ctx_t * ctx,uint8_t val)11745 int32_t lsm6dsr_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val)
11746 {
11747 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code;
11748 int32_t ret;
11749
11750 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11751 (uint8_t *)&s4s_st_cmd_code, 1);
11752
11753 if (ret == 0)
11754 {
11755 s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
11756 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11757 (uint8_t *)&s4s_st_cmd_code, 1);
11758 }
11759
11760 return ret;
11761 }
11762
11763 /**
11764 * @brief s4s master command.[get]
11765 *
11766 * @param ctx Read / write interface definitions.(ptr)
11767 * @param val get the values of S4S_ST_CMD_CODE.
11768 * @retval Interface status (MANDATORY: return 0 -> no Error).
11769 *
11770 */
lsm6dsr_s4s_command_get(const stmdev_ctx_t * ctx,uint8_t * val)11771 int32_t lsm6dsr_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val)
11772 {
11773 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code;
11774 int32_t ret;
11775
11776 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11777 (uint8_t *)&s4s_st_cmd_code, 1);
11778 *val = s4s_st_cmd_code.s4s_st_cmd_code;
11779
11780 return ret;
11781 }
11782
11783 /**
11784 * @brief S4S DT register.[set]
11785 *
11786 * @param ctx Read / write interface definitions.(ptr)
11787 * @param val Change the values of S4S_DT_REG.
11788 * @retval Interface status (MANDATORY: return 0 -> no Error).
11789 *
11790 */
lsm6dsr_s4s_dt_set(const stmdev_ctx_t * ctx,uint8_t val)11791 int32_t lsm6dsr_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val)
11792 {
11793 lsm6dsr_s4s_dt_reg_t s4s_dt_reg;
11794 int32_t ret;
11795
11796 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
11797 (uint8_t *)&s4s_dt_reg, 1);
11798
11799 if (ret == 0)
11800 {
11801 s4s_dt_reg.dt = (uint8_t)val;
11802 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_DT_REG,
11803 (uint8_t *)&s4s_dt_reg, 1);
11804 }
11805
11806 return ret;
11807 }
11808
11809 /**
11810 * @brief S4S DT register.[get]
11811 *
11812 * @param ctx Read / write interface definitions.(ptr)
11813 * @param val get the values of S4S_DT_REG.
11814 * @retval Interface status (MANDATORY: return 0 -> no Error).
11815 *
11816 */
lsm6dsr_s4s_dt_get(const stmdev_ctx_t * ctx,uint8_t * val)11817 int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val)
11818 {
11819 lsm6dsr_s4s_dt_reg_t s4s_dt_reg;
11820 int32_t ret;
11821
11822 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
11823 (uint8_t *)&s4s_dt_reg, 1);
11824 *val = s4s_dt_reg.dt;
11825
11826 return ret;
11827 }
11828
11829 /**
11830 * @}
11831 *
11832 */
11833
11834 /**
11835 * @}
11836 *
11837 */
11838
11839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11840
