1 /** 2 ****************************************************************************** 3 * @file lsm6dso32x_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dso32x_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSO32X_REGS_H 23 #define LSM6DSO32X_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSO32X 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSO32X_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSO32X_I2C_ADD_L 0xD5U 173 #define LSM6DSO32X_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSO32X_ID 0x6CU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSO32X_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 191 uint8_t not_used_01 : 6; 192 #endif /* DRV_BYTE_ORDER */ 193 } lsm6dso32x_func_cfg_access_t; 194 195 #define LSM6DSO32X_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t not_used_02 : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t not_used_02 : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } lsm6dso32x_pin_ctrl_t; 208 209 #define LSM6DSO32X_FIFO_CTRL1 0x07U 210 typedef struct 211 { 212 uint8_t wtm : 8; 213 } lsm6dso32x_fifo_ctrl1_t; 214 215 #define LSM6DSO32X_FIFO_CTRL2 0x08U 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t wtm : 1; 220 uint8_t uncoptr_rate : 2; 221 uint8_t not_used_01 : 1; 222 uint8_t odrchg_en : 1; 223 uint8_t not_used_02 : 1; 224 uint8_t fifo_compr_rt_en : 1; 225 uint8_t stop_on_wtm : 1; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t stop_on_wtm : 1; 228 uint8_t fifo_compr_rt_en : 1; 229 uint8_t not_used_02 : 1; 230 uint8_t odrchg_en : 1; 231 uint8_t not_used_01 : 1; 232 uint8_t uncoptr_rate : 2; 233 uint8_t wtm : 1; 234 #endif /* DRV_BYTE_ORDER */ 235 } lsm6dso32x_fifo_ctrl2_t; 236 237 #define LSM6DSO32X_FIFO_CTRL3 0x09U 238 typedef struct 239 { 240 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 241 uint8_t bdr_xl : 4; 242 uint8_t bdr_gy : 4; 243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 244 uint8_t bdr_gy : 4; 245 uint8_t bdr_xl : 4; 246 #endif /* DRV_BYTE_ORDER */ 247 } lsm6dso32x_fifo_ctrl3_t; 248 249 #define LSM6DSO32X_FIFO_CTRL4 0x0AU 250 typedef struct 251 { 252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 253 uint8_t fifo_mode : 3; 254 uint8_t not_used_01 : 1; 255 uint8_t odr_t_batch : 2; 256 uint8_t odr_ts_batch : 2; 257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 258 uint8_t odr_ts_batch : 2; 259 uint8_t odr_t_batch : 2; 260 uint8_t not_used_01 : 1; 261 uint8_t fifo_mode : 3; 262 #endif /* DRV_BYTE_ORDER */ 263 } lsm6dso32x_fifo_ctrl4_t; 264 265 #define LSM6DSO32X_COUNTER_BDR_REG1 0x0BU 266 typedef struct 267 { 268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 269 uint8_t cnt_bdr_th : 3; 270 uint8_t not_used_01 : 2; 271 uint8_t trig_counter_bdr : 1; 272 uint8_t rst_counter_bdr : 1; 273 uint8_t dataready_pulsed : 1; 274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 275 uint8_t dataready_pulsed : 1; 276 uint8_t rst_counter_bdr : 1; 277 uint8_t trig_counter_bdr : 1; 278 uint8_t not_used_01 : 2; 279 uint8_t cnt_bdr_th : 3; 280 #endif /* DRV_BYTE_ORDER */ 281 } lsm6dso32x_counter_bdr_reg1_t; 282 283 #define LSM6DSO32X_COUNTER_BDR_REG2 0x0CU 284 typedef struct 285 { 286 uint8_t cnt_bdr_th : 8; 287 } lsm6dso32x_counter_bdr_reg2_t; 288 289 #define LSM6DSO32X_INT1_CTRL 0x0D 290 typedef struct 291 { 292 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 293 uint8_t int1_drdy_xl : 1; 294 uint8_t int1_drdy_g : 1; 295 uint8_t int1_boot : 1; 296 uint8_t int1_fifo_th : 1; 297 uint8_t int1_fifo_ovr : 1; 298 uint8_t int1_fifo_full : 1; 299 uint8_t int1_cnt_bdr : 1; 300 uint8_t den_drdy_flag : 1; 301 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 302 uint8_t den_drdy_flag : 1; 303 uint8_t int1_cnt_bdr : 1; 304 uint8_t int1_fifo_full : 1; 305 uint8_t int1_fifo_ovr : 1; 306 uint8_t int1_fifo_th : 1; 307 uint8_t int1_boot : 1; 308 uint8_t int1_drdy_g : 1; 309 uint8_t int1_drdy_xl : 1; 310 #endif /* DRV_BYTE_ORDER */ 311 } lsm6dso32x_int1_ctrl_t; 312 313 #define LSM6DSO32X_INT2_CTRL 0x0EU 314 typedef struct 315 { 316 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 317 uint8_t int2_drdy_xl : 1; 318 uint8_t int2_drdy_g : 1; 319 uint8_t int2_drdy_temp : 1; 320 uint8_t int2_fifo_th : 1; 321 uint8_t int2_fifo_ovr : 1; 322 uint8_t int2_fifo_full : 1; 323 uint8_t int2_cnt_bdr : 1; 324 uint8_t not_used_01 : 1; 325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 326 uint8_t not_used_01 : 1; 327 uint8_t int2_cnt_bdr : 1; 328 uint8_t int2_fifo_full : 1; 329 uint8_t int2_fifo_ovr : 1; 330 uint8_t int2_fifo_th : 1; 331 uint8_t int2_drdy_temp : 1; 332 uint8_t int2_drdy_g : 1; 333 uint8_t int2_drdy_xl : 1; 334 #endif /* DRV_BYTE_ORDER */ 335 } lsm6dso32x_int2_ctrl_t; 336 337 #define LSM6DSO32X_WHO_AM_I 0x0FU 338 #define LSM6DSO32X_CTRL1_XL 0x10U 339 typedef struct 340 { 341 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 342 uint8_t not_used_01 : 1; 343 uint8_t lpf2_xl_en : 1; 344 uint8_t fs_xl : 2; 345 uint8_t odr_xl : 4; 346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 347 uint8_t odr_xl : 4; 348 uint8_t fs_xl : 2; 349 uint8_t lpf2_xl_en : 1; 350 uint8_t not_used_01 : 1; 351 #endif /* DRV_BYTE_ORDER */ 352 } lsm6dso32x_ctrl1_xl_t; 353 354 #define LSM6DSO32X_CTRL2_G 0x11U 355 typedef struct 356 { 357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 358 uint8_t not_used_01 : 1; 359 uint8_t fs_g : 3; /* fs_125 + fs_g */ 360 uint8_t odr_g : 4; 361 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 362 uint8_t odr_g : 4; 363 uint8_t fs_g : 3; /* fs_125 + fs_g */ 364 uint8_t not_used_01 : 1; 365 #endif /* DRV_BYTE_ORDER */ 366 } lsm6dso32x_ctrl2_g_t; 367 368 #define LSM6DSO32X_CTRL3_C 0x12U 369 typedef struct 370 { 371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 372 uint8_t sw_reset : 1; 373 uint8_t not_used_01 : 1; 374 uint8_t if_inc : 1; 375 uint8_t sim : 1; 376 uint8_t pp_od : 1; 377 uint8_t h_lactive : 1; 378 uint8_t bdu : 1; 379 uint8_t boot : 1; 380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 381 uint8_t boot : 1; 382 uint8_t bdu : 1; 383 uint8_t h_lactive : 1; 384 uint8_t pp_od : 1; 385 uint8_t sim : 1; 386 uint8_t if_inc : 1; 387 uint8_t not_used_01 : 1; 388 uint8_t sw_reset : 1; 389 #endif /* DRV_BYTE_ORDER */ 390 } lsm6dso32x_ctrl3_c_t; 391 392 #define LSM6DSO32X_CTRL4_C 0x13U 393 typedef struct 394 { 395 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 396 uint8_t not_used_01 : 1; 397 uint8_t lpf1_sel_g : 1; 398 uint8_t i2c_disable : 1; 399 uint8_t drdy_mask : 1; 400 uint8_t not_used_02 : 1; 401 uint8_t int2_on_int1 : 1; 402 uint8_t sleep_g : 1; 403 uint8_t not_used_03 : 1; 404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 405 uint8_t not_used_03 : 1; 406 uint8_t sleep_g : 1; 407 uint8_t int2_on_int1 : 1; 408 uint8_t not_used_02 : 1; 409 uint8_t drdy_mask : 1; 410 uint8_t i2c_disable : 1; 411 uint8_t lpf1_sel_g : 1; 412 uint8_t not_used_01 : 1; 413 #endif /* DRV_BYTE_ORDER */ 414 } lsm6dso32x_ctrl4_c_t; 415 416 #define LSM6DSO32X_CTRL5_C 0x14U 417 typedef struct 418 { 419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 420 uint8_t st_xl : 2; 421 uint8_t st_g : 2; 422 uint8_t not_used_01 : 1; 423 uint8_t rounding : 2; 424 uint8_t xl_ulp_en : 1; 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t xl_ulp_en : 1; 427 uint8_t rounding : 2; 428 uint8_t not_used_01 : 1; 429 uint8_t st_g : 2; 430 uint8_t st_xl : 2; 431 #endif /* DRV_BYTE_ORDER */ 432 } lsm6dso32x_ctrl5_c_t; 433 434 #define LSM6DSO32X_CTRL6_C 0x15U 435 typedef struct 436 { 437 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 438 uint8_t ftype : 3; 439 uint8_t usr_off_w : 1; 440 uint8_t xl_hm_mode : 1; 441 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 443 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 444 uint8_t xl_hm_mode : 1; 445 uint8_t usr_off_w : 1; 446 uint8_t ftype : 3; 447 #endif /* DRV_BYTE_ORDER */ 448 } lsm6dso32x_ctrl6_c_t; 449 450 #define LSM6DSO32X_CTRL7_G 0x16U 451 typedef struct 452 { 453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 454 uint8_t not_used_01 : 1; 455 uint8_t usr_off_on_out : 1; 456 uint8_t not_used_02 : 2; 457 uint8_t hpm_g : 2; 458 uint8_t hp_en_g : 1; 459 uint8_t g_hm_mode : 1; 460 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 461 uint8_t g_hm_mode : 1; 462 uint8_t hp_en_g : 1; 463 uint8_t hpm_g : 2; 464 uint8_t not_used_02 : 2; 465 uint8_t usr_off_on_out : 1; 466 uint8_t not_used_01 : 1; 467 #endif /* DRV_BYTE_ORDER */ 468 } lsm6dso32x_ctrl7_g_t; 469 470 #define LSM6DSO32X_CTRL8_XL 0x17U 471 typedef struct 472 { 473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 474 uint8_t low_pass_on_6d : 1; 475 uint8_t not_used_01 : 1; 476 uint8_t hp_slope_xl_en : 1; 477 uint8_t fastsettl_mode_xl : 1; 478 uint8_t hp_ref_mode_xl : 1; 479 uint8_t hpcf_xl : 3; 480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 481 uint8_t hpcf_xl : 3; 482 uint8_t hp_ref_mode_xl : 1; 483 uint8_t fastsettl_mode_xl : 1; 484 uint8_t hp_slope_xl_en : 1; 485 uint8_t not_used_01 : 1; 486 uint8_t low_pass_on_6d : 1; 487 #endif /* DRV_BYTE_ORDER */ 488 } lsm6dso32x_ctrl8_xl_t; 489 490 #define LSM6DSO32X_CTRL9_XL 0x18U 491 typedef struct 492 { 493 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 494 uint8_t not_used_01 : 1; 495 uint8_t i3c_disable : 1; 496 uint8_t den_lh : 1; 497 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 498 uint8_t den_z : 1; 499 uint8_t den_y : 1; 500 uint8_t den_x : 1; 501 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 502 uint8_t den_x : 1; 503 uint8_t den_y : 1; 504 uint8_t den_z : 1; 505 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 506 uint8_t den_lh : 1; 507 uint8_t i3c_disable : 1; 508 uint8_t not_used_01 : 1; 509 #endif /* DRV_BYTE_ORDER */ 510 } lsm6dso32x_ctrl9_xl_t; 511 512 #define LSM6DSO32X_CTRL10_C 0x19U 513 typedef struct 514 { 515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 516 uint8_t not_used_01 : 5; 517 uint8_t timestamp_en : 1; 518 uint8_t not_used_02 : 2; 519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 520 uint8_t not_used_02 : 2; 521 uint8_t timestamp_en : 1; 522 uint8_t not_used_01 : 5; 523 #endif /* DRV_BYTE_ORDER */ 524 } lsm6dso32x_ctrl10_c_t; 525 526 #define LSM6DSO32X_ALL_INT_SRC 0x1AU 527 typedef struct 528 { 529 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 530 uint8_t ff_ia : 1; 531 uint8_t wu_ia : 1; 532 uint8_t single_tap : 1; 533 uint8_t double_tap : 1; 534 uint8_t d6d_ia : 1; 535 uint8_t sleep_change_ia : 1; 536 uint8_t not_used_01 : 1; 537 uint8_t timestamp_endcount : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t timestamp_endcount : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t sleep_change_ia : 1; 542 uint8_t d6d_ia : 1; 543 uint8_t double_tap : 1; 544 uint8_t single_tap : 1; 545 uint8_t wu_ia : 1; 546 uint8_t ff_ia : 1; 547 #endif /* DRV_BYTE_ORDER */ 548 } lsm6dso32x_all_int_src_t; 549 550 #define LSM6DSO32X_WAKE_UP_SRC 0x1BU 551 typedef struct 552 { 553 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 554 uint8_t z_wu : 1; 555 uint8_t y_wu : 1; 556 uint8_t x_wu : 1; 557 uint8_t wu_ia : 1; 558 uint8_t sleep_state : 1; 559 uint8_t ff_ia : 1; 560 uint8_t sleep_change_ia : 2; 561 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 562 uint8_t sleep_change_ia : 2; 563 uint8_t ff_ia : 1; 564 uint8_t sleep_state : 1; 565 uint8_t wu_ia : 1; 566 uint8_t x_wu : 1; 567 uint8_t y_wu : 1; 568 uint8_t z_wu : 1; 569 #endif /* DRV_BYTE_ORDER */ 570 } lsm6dso32x_wake_up_src_t; 571 572 #define LSM6DSO32X_TAP_SRC 0x1CU 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t z_tap : 1; 577 uint8_t y_tap : 1; 578 uint8_t x_tap : 1; 579 uint8_t tap_sign : 1; 580 uint8_t double_tap : 1; 581 uint8_t single_tap : 1; 582 uint8_t tap_ia : 1; 583 uint8_t not_used_02 : 1; 584 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 585 uint8_t not_used_02 : 1; 586 uint8_t tap_ia : 1; 587 uint8_t single_tap : 1; 588 uint8_t double_tap : 1; 589 uint8_t tap_sign : 1; 590 uint8_t x_tap : 1; 591 uint8_t y_tap : 1; 592 uint8_t z_tap : 1; 593 #endif /* DRV_BYTE_ORDER */ 594 } lsm6dso32x_tap_src_t; 595 596 #define LSM6DSO32X_D6D_SRC 0x1DU 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t xl : 1; 601 uint8_t xh : 1; 602 uint8_t yl : 1; 603 uint8_t yh : 1; 604 uint8_t zl : 1; 605 uint8_t zh : 1; 606 uint8_t d6d_ia : 1; 607 uint8_t den_drdy : 1; 608 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 609 uint8_t den_drdy : 1; 610 uint8_t d6d_ia : 1; 611 uint8_t zh : 1; 612 uint8_t zl : 1; 613 uint8_t yh : 1; 614 uint8_t yl : 1; 615 uint8_t xh : 1; 616 uint8_t xl : 1; 617 #endif /* DRV_BYTE_ORDER */ 618 } lsm6dso32x_d6d_src_t; 619 620 #define LSM6DSO32X_STATUS_REG 0x1EU 621 typedef struct 622 { 623 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 624 uint8_t xlda : 1; 625 uint8_t gda : 1; 626 uint8_t tda : 1; 627 uint8_t not_used_01 : 5; 628 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 629 uint8_t not_used_01 : 5; 630 uint8_t tda : 1; 631 uint8_t gda : 1; 632 uint8_t xlda : 1; 633 #endif /* DRV_BYTE_ORDER */ 634 } lsm6dso32x_status_reg_t; 635 636 #define LSM6DSO32X_OUT_TEMP_L 0x20U 637 #define LSM6DSO32X_OUT_TEMP_H 0x21U 638 #define LSM6DSO32X_OUTX_L_G 0x22U 639 #define LSM6DSO32X_OUTX_H_G 0x23U 640 #define LSM6DSO32X_OUTY_L_G 0x24U 641 #define LSM6DSO32X_OUTY_H_G 0x25U 642 #define LSM6DSO32X_OUTZ_L_G 0x26U 643 #define LSM6DSO32X_OUTZ_H_G 0x27U 644 #define LSM6DSO32X_OUTX_L_A 0x28U 645 #define LSM6DSO32X_OUTX_H_A 0x29U 646 #define LSM6DSO32X_OUTY_L_A 0x2AU 647 #define LSM6DSO32X_OUTY_H_A 0x2BU 648 #define LSM6DSO32X_OUTZ_L_A 0x2CU 649 #define LSM6DSO32X_OUTZ_H_A 0x2DU 650 #define LSM6DSO32X_EMB_FUNC_STATUS_MAINPAGE 0x35U 651 typedef struct 652 { 653 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 654 uint8_t not_used_01 : 3; 655 uint8_t is_step_det : 1; 656 uint8_t is_tilt : 1; 657 uint8_t is_sigmot : 1; 658 uint8_t not_used_02 : 1; 659 uint8_t is_fsm_lc : 1; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t is_fsm_lc : 1; 662 uint8_t not_used_02 : 1; 663 uint8_t is_sigmot : 1; 664 uint8_t is_tilt : 1; 665 uint8_t is_step_det : 1; 666 uint8_t not_used_01 : 3; 667 #endif /* DRV_BYTE_ORDER */ 668 } lsm6dso32x_emb_func_status_mainpage_t; 669 670 #define LSM6DSO32X_FSM_STATUS_A_MAINPAGE 0x36U 671 typedef struct 672 { 673 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 674 uint8_t is_fsm1 : 1; 675 uint8_t is_fsm2 : 1; 676 uint8_t is_fsm3 : 1; 677 uint8_t is_fsm4 : 1; 678 uint8_t is_fsm5 : 1; 679 uint8_t is_fsm6 : 1; 680 uint8_t is_fsm7 : 1; 681 uint8_t is_fsm8 : 1; 682 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 683 uint8_t is_fsm8 : 1; 684 uint8_t is_fsm7 : 1; 685 uint8_t is_fsm6 : 1; 686 uint8_t is_fsm5 : 1; 687 uint8_t is_fsm4 : 1; 688 uint8_t is_fsm3 : 1; 689 uint8_t is_fsm2 : 1; 690 uint8_t is_fsm1 : 1; 691 #endif /* DRV_BYTE_ORDER */ 692 } lsm6dso32x_fsm_status_a_mainpage_t; 693 694 #define LSM6DSO32X_FSM_STATUS_B_MAINPAGE 0x37U 695 typedef struct 696 { 697 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 698 uint8_t is_fsm9 : 1; 699 uint8_t is_fsm10 : 1; 700 uint8_t is_fsm11 : 1; 701 uint8_t is_fsm12 : 1; 702 uint8_t is_fsm13 : 1; 703 uint8_t is_fsm14 : 1; 704 uint8_t is_fsm15 : 1; 705 uint8_t is_fsm16 : 1; 706 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 707 uint8_t is_fsm16 : 1; 708 uint8_t is_fsm15 : 1; 709 uint8_t is_fsm14 : 1; 710 uint8_t is_fsm13 : 1; 711 uint8_t is_fsm12 : 1; 712 uint8_t is_fsm11 : 1; 713 uint8_t is_fsm10 : 1; 714 uint8_t is_fsm9 : 1; 715 #endif /* DRV_BYTE_ORDER */ 716 } lsm6dso32x_fsm_status_b_mainpage_t; 717 718 #define LSM6DSO32X_MLC_STATUS_MAINPAGE 0x38U 719 typedef struct 720 { 721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 722 uint8_t is_mlc1 : 1; 723 uint8_t is_mlc2 : 1; 724 uint8_t is_mlc3 : 1; 725 uint8_t is_mlc4 : 1; 726 uint8_t is_mlc5 : 1; 727 uint8_t is_mlc6 : 1; 728 uint8_t is_mlc7 : 1; 729 uint8_t is_mlc8 : 1; 730 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 731 uint8_t is_mlc8 : 1; 732 uint8_t is_mlc7 : 1; 733 uint8_t is_mlc6 : 1; 734 uint8_t is_mlc5 : 1; 735 uint8_t is_mlc4 : 1; 736 uint8_t is_mlc3 : 1; 737 uint8_t is_mlc2 : 1; 738 uint8_t is_mlc1 : 1; 739 #endif /* DRV_BYTE_ORDER */ 740 } lsm6dso32x_mlc_status_mainpage_t; 741 742 #define LSM6DSO32X_STATUS_MASTER_MAINPAGE 0x39U 743 typedef struct 744 { 745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 746 uint8_t sens_hub_endop : 1; 747 uint8_t not_used_01 : 2; 748 uint8_t slave0_nack : 1; 749 uint8_t slave1_nack : 1; 750 uint8_t slave2_nack : 1; 751 uint8_t slave3_nack : 1; 752 uint8_t wr_once_done : 1; 753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 754 uint8_t wr_once_done : 1; 755 uint8_t slave3_nack : 1; 756 uint8_t slave2_nack : 1; 757 uint8_t slave1_nack : 1; 758 uint8_t slave0_nack : 1; 759 uint8_t not_used_01 : 2; 760 uint8_t sens_hub_endop : 1; 761 #endif /* DRV_BYTE_ORDER */ 762 } lsm6dso32x_status_master_mainpage_t; 763 764 #define LSM6DSO32X_FIFO_STATUS1 0x3AU 765 typedef struct 766 { 767 uint8_t diff_fifo : 8; 768 } lsm6dso32x_fifo_status1_t; 769 770 #define LSM6DSO32X_FIFO_STATUS2 0x3B 771 typedef struct 772 { 773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 774 uint8_t diff_fifo : 2; 775 uint8_t not_used_01 : 1; 776 uint8_t over_run_latched : 1; 777 uint8_t counter_bdr_ia : 1; 778 uint8_t fifo_full_ia : 1; 779 uint8_t fifo_ovr_ia : 1; 780 uint8_t fifo_wtm_ia : 1; 781 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 782 uint8_t fifo_wtm_ia : 1; 783 uint8_t fifo_ovr_ia : 1; 784 uint8_t fifo_full_ia : 1; 785 uint8_t counter_bdr_ia : 1; 786 uint8_t over_run_latched : 1; 787 uint8_t not_used_01 : 1; 788 uint8_t diff_fifo : 2; 789 #endif /* DRV_BYTE_ORDER */ 790 } lsm6dso32x_fifo_status2_t; 791 792 #define LSM6DSO32X_TIMESTAMP0 0x40U 793 #define LSM6DSO32X_TIMESTAMP1 0x41U 794 #define LSM6DSO32X_TIMESTAMP2 0x42U 795 #define LSM6DSO32X_TIMESTAMP3 0x43U 796 797 #define LSM6DSO32X_TAP_CFG0 0x56U 798 typedef struct 799 { 800 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 801 uint8_t lir : 1; 802 uint8_t tap_z_en : 1; 803 uint8_t tap_y_en : 1; 804 uint8_t tap_x_en : 1; 805 uint8_t slope_fds : 1; 806 uint8_t sleep_status_on_int : 1; 807 uint8_t int_clr_on_read : 1; 808 uint8_t not_used_01 : 1; 809 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 810 uint8_t not_used_01 : 1; 811 uint8_t int_clr_on_read : 1; 812 uint8_t sleep_status_on_int : 1; 813 uint8_t slope_fds : 1; 814 uint8_t tap_x_en : 1; 815 uint8_t tap_y_en : 1; 816 uint8_t tap_z_en : 1; 817 uint8_t lir : 1; 818 #endif /* DRV_BYTE_ORDER */ 819 } lsm6dso32x_tap_cfg0_t; 820 821 #define LSM6DSO32X_TAP_CFG1 0x57U 822 typedef struct 823 { 824 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 825 uint8_t tap_ths_x : 5; 826 uint8_t tap_priority : 3; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t tap_priority : 3; 829 uint8_t tap_ths_x : 5; 830 #endif /* DRV_BYTE_ORDER */ 831 } lsm6dso32x_tap_cfg1_t; 832 833 #define LSM6DSO32X_TAP_CFG2 0x58U 834 typedef struct 835 { 836 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 837 uint8_t tap_ths_y : 5; 838 uint8_t inact_en : 2; 839 uint8_t interrupts_enable : 1; 840 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 841 uint8_t interrupts_enable : 1; 842 uint8_t inact_en : 2; 843 uint8_t tap_ths_y : 5; 844 #endif /* DRV_BYTE_ORDER */ 845 } lsm6dso32x_tap_cfg2_t; 846 847 #define LSM6DSO32X_TAP_THS_6D 0x59U 848 typedef struct 849 { 850 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 851 uint8_t tap_ths_z : 5; 852 uint8_t sixd_ths : 2; 853 uint8_t d4d_en : 1; 854 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 855 uint8_t d4d_en : 1; 856 uint8_t sixd_ths : 2; 857 uint8_t tap_ths_z : 5; 858 #endif /* DRV_BYTE_ORDER */ 859 } lsm6dso32x_tap_ths_6d_t; 860 861 #define LSM6DSO32X_INT_DUR2 0x5AU 862 typedef struct 863 { 864 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 865 uint8_t shock : 2; 866 uint8_t quiet : 2; 867 uint8_t dur : 4; 868 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 869 uint8_t dur : 4; 870 uint8_t quiet : 2; 871 uint8_t shock : 2; 872 #endif /* DRV_BYTE_ORDER */ 873 } lsm6dso32x_int_dur2_t; 874 875 #define LSM6DSO32X_WAKE_UP_THS 0x5BU 876 typedef struct 877 { 878 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 879 uint8_t wk_ths : 6; 880 uint8_t usr_off_on_wu : 1; 881 uint8_t single_double_tap : 1; 882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 883 uint8_t single_double_tap : 1; 884 uint8_t usr_off_on_wu : 1; 885 uint8_t wk_ths : 6; 886 #endif /* DRV_BYTE_ORDER */ 887 } lsm6dso32x_wake_up_ths_t; 888 889 #define LSM6DSO32X_WAKE_UP_DUR 0x5CU 890 typedef struct 891 { 892 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 893 uint8_t sleep_dur : 4; 894 uint8_t wake_ths_w : 1; 895 uint8_t wake_dur : 2; 896 uint8_t ff_dur : 1; 897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 898 uint8_t ff_dur : 1; 899 uint8_t wake_dur : 2; 900 uint8_t wake_ths_w : 1; 901 uint8_t sleep_dur : 4; 902 #endif /* DRV_BYTE_ORDER */ 903 } lsm6dso32x_wake_up_dur_t; 904 905 #define LSM6DSO32X_FREE_FALL 0x5DU 906 typedef struct 907 { 908 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 909 uint8_t ff_ths : 3; 910 uint8_t ff_dur : 5; 911 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 912 uint8_t ff_dur : 5; 913 uint8_t ff_ths : 3; 914 #endif /* DRV_BYTE_ORDER */ 915 } lsm6dso32x_free_fall_t; 916 917 #define LSM6DSO32X_MD1_CFG 0x5EU 918 typedef struct 919 { 920 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 921 uint8_t int1_shub : 1; 922 uint8_t int1_emb_func : 1; 923 uint8_t int1_6d : 1; 924 uint8_t int1_double_tap : 1; 925 uint8_t int1_ff : 1; 926 uint8_t int1_wu : 1; 927 uint8_t int1_single_tap : 1; 928 uint8_t int1_sleep_change : 1; 929 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 930 uint8_t int1_sleep_change : 1; 931 uint8_t int1_single_tap : 1; 932 uint8_t int1_wu : 1; 933 uint8_t int1_ff : 1; 934 uint8_t int1_double_tap : 1; 935 uint8_t int1_6d : 1; 936 uint8_t int1_emb_func : 1; 937 uint8_t int1_shub : 1; 938 #endif /* DRV_BYTE_ORDER */ 939 } lsm6dso32x_md1_cfg_t; 940 941 #define LSM6DSO32X_MD2_CFG 0x5FU 942 typedef struct 943 { 944 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 945 uint8_t int2_timestamp : 1; 946 uint8_t int2_emb_func : 1; 947 uint8_t int2_6d : 1; 948 uint8_t int2_double_tap : 1; 949 uint8_t int2_ff : 1; 950 uint8_t int2_wu : 1; 951 uint8_t int2_single_tap : 1; 952 uint8_t int2_sleep_change : 1; 953 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 954 uint8_t int2_sleep_change : 1; 955 uint8_t int2_single_tap : 1; 956 uint8_t int2_wu : 1; 957 uint8_t int2_ff : 1; 958 uint8_t int2_double_tap : 1; 959 uint8_t int2_6d : 1; 960 uint8_t int2_emb_func : 1; 961 uint8_t int2_timestamp : 1; 962 #endif /* DRV_BYTE_ORDER */ 963 } lsm6dso32x_md2_cfg_t; 964 965 #define LSM6DSO32X_I3C_BUS_AVB 0x62U 966 typedef struct 967 { 968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 969 uint8_t pd_dis_int1 : 1; 970 uint8_t not_used_01 : 2; 971 uint8_t i3c_bus_avb_sel : 2; 972 uint8_t not_used_02 : 3; 973 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 974 uint8_t not_used_02 : 3; 975 uint8_t i3c_bus_avb_sel : 2; 976 uint8_t not_used_01 : 2; 977 uint8_t pd_dis_int1 : 1; 978 #endif /* DRV_BYTE_ORDER */ 979 } lsm6dso32x_i3c_bus_avb_t; 980 981 #define LSM6DSO32X_INTERNAL_FREQ_FINE 0x63U 982 typedef struct 983 { 984 uint8_t freq_fine : 8; 985 } lsm6dso32x_internal_freq_fine_t; 986 987 #define LSM6DSO32X_X_OFS_USR 0x73U 988 #define LSM6DSO32X_Y_OFS_USR 0x74U 989 #define LSM6DSO32X_Z_OFS_USR 0x75U 990 #define LSM6DSO32X_FIFO_DATA_OUT_TAG 0x78U 991 typedef struct 992 { 993 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 994 uint8_t tag_parity : 1; 995 uint8_t tag_cnt : 2; 996 uint8_t tag_sensor : 5; 997 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 998 uint8_t tag_sensor : 5; 999 uint8_t tag_cnt : 2; 1000 uint8_t tag_parity : 1; 1001 #endif /* DRV_BYTE_ORDER */ 1002 } lsm6dso32x_fifo_data_out_tag_t; 1003 1004 #define LSM6DSO32X_FIFO_DATA_OUT_X_L 0x79 1005 #define LSM6DSO32X_FIFO_DATA_OUT_X_H 0x7A 1006 #define LSM6DSO32X_FIFO_DATA_OUT_Y_L 0x7B 1007 #define LSM6DSO32X_FIFO_DATA_OUT_Y_H 0x7C 1008 #define LSM6DSO32X_FIFO_DATA_OUT_Z_L 0x7D 1009 #define LSM6DSO32X_FIFO_DATA_OUT_Z_H 0x7E 1010 1011 #define LSM6DSO32X_PAGE_SEL 0x02U 1012 typedef struct 1013 { 1014 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1015 uint8_t not_used_01 : 4; 1016 uint8_t page_sel : 4; 1017 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1018 uint8_t page_sel : 4; 1019 uint8_t not_used_01 : 4; 1020 #endif /* DRV_BYTE_ORDER */ 1021 } lsm6dso32x_page_sel_t; 1022 1023 #define LSM6DSO32X_EMB_FUNC_EN_A 0x04U 1024 typedef struct 1025 { 1026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1027 uint8_t not_used_01 : 3; 1028 uint8_t pedo_en : 1; 1029 uint8_t tilt_en : 1; 1030 uint8_t sign_motion_en : 1; 1031 uint8_t not_used_02 : 2; 1032 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1033 uint8_t not_used_02 : 2; 1034 uint8_t sign_motion_en : 1; 1035 uint8_t tilt_en : 1; 1036 uint8_t pedo_en : 1; 1037 uint8_t not_used_01 : 3; 1038 #endif /* DRV_BYTE_ORDER */ 1039 } lsm6dso32x_emb_func_en_a_t; 1040 1041 #define LSM6DSO32X_EMB_FUNC_EN_B 0x05U 1042 typedef struct 1043 { 1044 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1045 uint8_t fsm_en : 1; 1046 uint8_t not_used_01 : 2; 1047 uint8_t fifo_compr_en : 1; 1048 uint8_t mlc_en : 1; 1049 uint8_t not_used_02 : 3; 1050 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1051 uint8_t not_used_02 : 3; 1052 uint8_t mlc_en : 1; 1053 uint8_t fifo_compr_en : 1; 1054 uint8_t not_used_01 : 2; 1055 uint8_t fsm_en : 1; 1056 #endif /* DRV_BYTE_ORDER */ 1057 } lsm6dso32x_emb_func_en_b_t; 1058 1059 #define LSM6DSO32X_PAGE_ADDRESS 0x08U 1060 typedef struct 1061 { 1062 uint8_t page_addr : 8; 1063 } lsm6dso32x_page_address_t; 1064 1065 #define LSM6DSO32X_PAGE_VALUE 0x09U 1066 typedef struct 1067 { 1068 uint8_t page_value : 8; 1069 } lsm6dso32x_page_value_t; 1070 1071 #define LSM6DSO32X_EMB_FUNC_INT1 0x0AU 1072 typedef struct 1073 { 1074 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1075 uint8_t not_used_01 : 3; 1076 uint8_t int1_step_detector : 1; 1077 uint8_t int1_tilt : 1; 1078 uint8_t int1_sig_mot : 1; 1079 uint8_t not_used_02 : 1; 1080 uint8_t int1_fsm_lc : 1; 1081 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1082 uint8_t int1_fsm_lc : 1; 1083 uint8_t not_used_02 : 1; 1084 uint8_t int1_sig_mot : 1; 1085 uint8_t int1_tilt : 1; 1086 uint8_t int1_step_detector : 1; 1087 uint8_t not_used_01 : 3; 1088 #endif /* DRV_BYTE_ORDER */ 1089 } lsm6dso32x_emb_func_int1_t; 1090 1091 #define LSM6DSO32X_FSM_INT1_A 0x0BU 1092 typedef struct 1093 { 1094 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1095 uint8_t int1_fsm1 : 1; 1096 uint8_t int1_fsm2 : 1; 1097 uint8_t int1_fsm3 : 1; 1098 uint8_t int1_fsm4 : 1; 1099 uint8_t int1_fsm5 : 1; 1100 uint8_t int1_fsm6 : 1; 1101 uint8_t int1_fsm7 : 1; 1102 uint8_t int1_fsm8 : 1; 1103 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1104 uint8_t int1_fsm8 : 1; 1105 uint8_t int1_fsm7 : 1; 1106 uint8_t int1_fsm6 : 1; 1107 uint8_t int1_fsm5 : 1; 1108 uint8_t int1_fsm4 : 1; 1109 uint8_t int1_fsm3 : 1; 1110 uint8_t int1_fsm2 : 1; 1111 uint8_t int1_fsm1 : 1; 1112 #endif /* DRV_BYTE_ORDER */ 1113 } lsm6dso32x_fsm_int1_a_t; 1114 1115 #define LSM6DSO32X_FSM_INT1_B 0x0CU 1116 typedef struct 1117 { 1118 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1119 uint8_t int1_fsm16 : 1; 1120 uint8_t int1_fsm15 : 1; 1121 uint8_t int1_fsm14 : 1; 1122 uint8_t int1_fsm13 : 1; 1123 uint8_t int1_fsm12 : 1; 1124 uint8_t int1_fsm11 : 1; 1125 uint8_t int1_fsm10 : 1; 1126 uint8_t int1_fsm9 : 1; 1127 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1128 #endif /* DRV_BYTE_ORDER */ 1129 } lsm6dso32x_fsm_int1_b_t; 1130 1131 #define LSM6DSO32X_MLC_INT1 0x0DU 1132 typedef struct 1133 { 1134 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1135 uint8_t int1_mlc1 : 1; 1136 uint8_t int1_mlc2 : 1; 1137 uint8_t int1_mlc3 : 1; 1138 uint8_t int1_mlc4 : 1; 1139 uint8_t int1_mlc5 : 1; 1140 uint8_t int1_mlc6 : 1; 1141 uint8_t int1_mlc7 : 1; 1142 uint8_t int1_mlc8 : 1; 1143 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1144 uint8_t int1_mlc8 : 1; 1145 uint8_t int1_mlc7 : 1; 1146 uint8_t int1_mlc6 : 1; 1147 uint8_t int1_mlc5 : 1; 1148 uint8_t int1_mlc4 : 1; 1149 uint8_t int1_mlc3 : 1; 1150 uint8_t int1_mlc2 : 1; 1151 uint8_t int1_mlc1 : 1; 1152 #endif /* DRV_BYTE_ORDER */ 1153 } lsm6dso32x_mlc_int1_t; 1154 1155 #define LSM6DSO32X_EMB_FUNC_INT2 0x0EU 1156 typedef struct 1157 { 1158 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1159 uint8_t not_used_01 : 3; 1160 uint8_t int2_step_detector : 1; 1161 uint8_t int2_tilt : 1; 1162 uint8_t int2_sig_mot : 1; 1163 uint8_t not_used_02 : 1; 1164 uint8_t int2_fsm_lc : 1; 1165 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1166 uint8_t int2_fsm_lc : 1; 1167 uint8_t not_used_02 : 1; 1168 uint8_t int2_sig_mot : 1; 1169 uint8_t int2_tilt : 1; 1170 uint8_t int2_step_detector : 1; 1171 uint8_t not_used_01 : 3; 1172 #endif /* DRV_BYTE_ORDER */ 1173 } lsm6dso32x_emb_func_int2_t; 1174 1175 #define LSM6DSO32X_FSM_INT2_A 0x0FU 1176 typedef struct 1177 { 1178 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1179 uint8_t int2_fsm1 : 1; 1180 uint8_t int2_fsm2 : 1; 1181 uint8_t int2_fsm3 : 1; 1182 uint8_t int2_fsm4 : 1; 1183 uint8_t int2_fsm5 : 1; 1184 uint8_t int2_fsm6 : 1; 1185 uint8_t int2_fsm7 : 1; 1186 uint8_t int2_fsm8 : 1; 1187 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1188 uint8_t int2_fsm8 : 1; 1189 uint8_t int2_fsm7 : 1; 1190 uint8_t int2_fsm6 : 1; 1191 uint8_t int2_fsm5 : 1; 1192 uint8_t int2_fsm4 : 1; 1193 uint8_t int2_fsm3 : 1; 1194 uint8_t int2_fsm2 : 1; 1195 uint8_t int2_fsm1 : 1; 1196 #endif /* DRV_BYTE_ORDER */ 1197 } lsm6dso32x_fsm_int2_a_t; 1198 1199 #define LSM6DSO32X_FSM_INT2_B 0x10U 1200 typedef struct 1201 { 1202 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1203 uint8_t int2_fsm9 : 1; 1204 uint8_t int2_fsm10 : 1; 1205 uint8_t int2_fsm11 : 1; 1206 uint8_t int2_fsm12 : 1; 1207 uint8_t int2_fsm13 : 1; 1208 uint8_t int2_fsm14 : 1; 1209 uint8_t int2_fsm15 : 1; 1210 uint8_t int2_fsm16 : 1; 1211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1212 uint8_t int2_fsm16 : 1; 1213 uint8_t int2_fsm15 : 1; 1214 uint8_t int2_fsm14 : 1; 1215 uint8_t int2_fsm13 : 1; 1216 uint8_t int2_fsm12 : 1; 1217 uint8_t int2_fsm11 : 1; 1218 uint8_t int2_fsm10 : 1; 1219 uint8_t int2_fsm9 : 1; 1220 #endif /* DRV_BYTE_ORDER */ 1221 } lsm6dso32x_fsm_int2_b_t; 1222 1223 #define LSM6DSO32X_MLC_INT2 0x11U 1224 typedef struct 1225 { 1226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1227 uint8_t int2_mlc1 : 1; 1228 uint8_t int2_mlc2 : 1; 1229 uint8_t int2_mlc3 : 1; 1230 uint8_t int2_mlc4 : 1; 1231 uint8_t int2_mlc5 : 1; 1232 uint8_t int2_mlc6 : 1; 1233 uint8_t int2_mlc7 : 1; 1234 uint8_t int2_mlc8 : 1; 1235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1236 uint8_t int2_mlc8 : 1; 1237 uint8_t int2_mlc7 : 1; 1238 uint8_t int2_mlc6 : 1; 1239 uint8_t int2_mlc5 : 1; 1240 uint8_t int2_mlc4 : 1; 1241 uint8_t int2_mlc3 : 1; 1242 uint8_t int2_mlc2 : 1; 1243 uint8_t int2_mlc1 : 1; 1244 #endif /* DRV_BYTE_ORDER */ 1245 } lsm6dso32x_mlc_int2_t; 1246 1247 #define LSM6DSO32X_EMB_FUNC_STATUS 0x12U 1248 typedef struct 1249 { 1250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1251 uint8_t not_used_01 : 3; 1252 uint8_t is_step_det : 1; 1253 uint8_t is_tilt : 1; 1254 uint8_t is_sigmot : 1; 1255 uint8_t not_used_02 : 1; 1256 uint8_t is_fsm_lc : 1; 1257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1258 uint8_t is_fsm_lc : 1; 1259 uint8_t not_used_02 : 1; 1260 uint8_t is_sigmot : 1; 1261 uint8_t is_tilt : 1; 1262 uint8_t is_step_det : 1; 1263 uint8_t not_used_01 : 3; 1264 #endif /* DRV_BYTE_ORDER */ 1265 } lsm6dso32x_emb_func_status_t; 1266 1267 #define LSM6DSO32X_FSM_STATUS_A 0x13U 1268 typedef struct 1269 { 1270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1271 uint8_t is_fsm1 : 1; 1272 uint8_t is_fsm2 : 1; 1273 uint8_t is_fsm3 : 1; 1274 uint8_t is_fsm4 : 1; 1275 uint8_t is_fsm5 : 1; 1276 uint8_t is_fsm6 : 1; 1277 uint8_t is_fsm7 : 1; 1278 uint8_t is_fsm8 : 1; 1279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1280 uint8_t is_fsm8 : 1; 1281 uint8_t is_fsm7 : 1; 1282 uint8_t is_fsm6 : 1; 1283 uint8_t is_fsm5 : 1; 1284 uint8_t is_fsm4 : 1; 1285 uint8_t is_fsm3 : 1; 1286 uint8_t is_fsm2 : 1; 1287 uint8_t is_fsm1 : 1; 1288 #endif /* DRV_BYTE_ORDER */ 1289 } lsm6dso32x_fsm_status_a_t; 1290 1291 #define LSM6DSO32X_FSM_STATUS_B 0x14U 1292 typedef struct 1293 { 1294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1295 uint8_t is_fsm9 : 1; 1296 uint8_t is_fsm10 : 1; 1297 uint8_t is_fsm11 : 1; 1298 uint8_t is_fsm12 : 1; 1299 uint8_t is_fsm13 : 1; 1300 uint8_t is_fsm14 : 1; 1301 uint8_t is_fsm15 : 1; 1302 uint8_t is_fsm16 : 1; 1303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1304 uint8_t is_fsm16 : 1; 1305 uint8_t is_fsm15 : 1; 1306 uint8_t is_fsm14 : 1; 1307 uint8_t is_fsm13 : 1; 1308 uint8_t is_fsm12 : 1; 1309 uint8_t is_fsm11 : 1; 1310 uint8_t is_fsm10 : 1; 1311 uint8_t is_fsm9 : 1; 1312 #endif /* DRV_BYTE_ORDER */ 1313 } lsm6dso32x_fsm_status_b_t; 1314 1315 #define LSM6DSO32X_MLC_STATUS 0x15U 1316 typedef struct 1317 { 1318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1319 uint8_t is_mlc1 : 1; 1320 uint8_t is_mlc2 : 1; 1321 uint8_t is_mlc3 : 1; 1322 uint8_t is_mlc4 : 1; 1323 uint8_t is_mlc5 : 1; 1324 uint8_t is_mlc6 : 1; 1325 uint8_t is_mlc7 : 1; 1326 uint8_t is_mlc8 : 1; 1327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1328 uint8_t is_mlc8 : 1; 1329 uint8_t is_mlc7 : 1; 1330 uint8_t is_mlc6 : 1; 1331 uint8_t is_mlc5 : 1; 1332 uint8_t is_mlc4 : 1; 1333 uint8_t is_mlc3 : 1; 1334 uint8_t is_mlc2 : 1; 1335 uint8_t is_mlc1 : 1; 1336 #endif /* DRV_BYTE_ORDER */ 1337 } lsm6dso32x_mlc_status_t; 1338 1339 #define LSM6DSO32X_PAGE_RW 0x17U 1340 typedef struct 1341 { 1342 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1343 uint8_t not_used_01 : 5; 1344 uint8_t page_rw : 2; /* page_write + page_read */ 1345 uint8_t emb_func_lir : 1; 1346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1347 uint8_t emb_func_lir : 1; 1348 uint8_t page_rw : 2; /* page_write + page_read */ 1349 uint8_t not_used_01 : 5; 1350 #endif /* DRV_BYTE_ORDER */ 1351 } lsm6dso32x_page_rw_t; 1352 1353 #define LSM6DSO32X_EMB_FUNC_FIFO_CFG 0x44U 1354 typedef struct 1355 { 1356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1357 uint8_t not_used_00 : 6; 1358 uint8_t pedo_fifo_en : 1; 1359 uint8_t not_used_01 : 1; 1360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1361 uint8_t not_used_01 : 1; 1362 uint8_t pedo_fifo_en : 1; 1363 uint8_t not_used_00 : 6; 1364 #endif /* DRV_BYTE_ORDER */ 1365 } lsm6dso32x_emb_func_fifo_cfg_t; 1366 1367 #define LSM6DSO32X_FSM_ENABLE_A 0x46U 1368 typedef struct 1369 { 1370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1371 uint8_t fsm1_en : 1; 1372 uint8_t fsm2_en : 1; 1373 uint8_t fsm3_en : 1; 1374 uint8_t fsm4_en : 1; 1375 uint8_t fsm5_en : 1; 1376 uint8_t fsm6_en : 1; 1377 uint8_t fsm7_en : 1; 1378 uint8_t fsm8_en : 1; 1379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1380 uint8_t fsm8_en : 1; 1381 uint8_t fsm7_en : 1; 1382 uint8_t fsm6_en : 1; 1383 uint8_t fsm5_en : 1; 1384 uint8_t fsm4_en : 1; 1385 uint8_t fsm3_en : 1; 1386 uint8_t fsm2_en : 1; 1387 uint8_t fsm1_en : 1; 1388 #endif /* DRV_BYTE_ORDER */ 1389 } lsm6dso32x_fsm_enable_a_t; 1390 1391 #define LSM6DSO32X_FSM_ENABLE_B 0x47U 1392 typedef struct 1393 { 1394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1395 uint8_t fsm9_en : 1; 1396 uint8_t fsm10_en : 1; 1397 uint8_t fsm11_en : 1; 1398 uint8_t fsm12_en : 1; 1399 uint8_t fsm13_en : 1; 1400 uint8_t fsm14_en : 1; 1401 uint8_t fsm15_en : 1; 1402 uint8_t fsm16_en : 1; 1403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1404 uint8_t fsm16_en : 1; 1405 uint8_t fsm15_en : 1; 1406 uint8_t fsm14_en : 1; 1407 uint8_t fsm13_en : 1; 1408 uint8_t fsm12_en : 1; 1409 uint8_t fsm11_en : 1; 1410 uint8_t fsm10_en : 1; 1411 uint8_t fsm9_en : 1; 1412 #endif /* DRV_BYTE_ORDER */ 1413 } lsm6dso32x_fsm_enable_b_t; 1414 1415 #define LSM6DSO32X_FSM_LONG_COUNTER_L 0x48U 1416 #define LSM6DSO32X_FSM_LONG_COUNTER_H 0x49U 1417 #define LSM6DSO32X_FSM_LONG_COUNTER_CLEAR 0x4AU 1418 typedef struct 1419 { 1420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1421 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1422 uint8_t not_used_01 : 6; 1423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1424 uint8_t not_used_01 : 6; 1425 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1426 #endif /* DRV_BYTE_ORDER */ 1427 } lsm6dso32x_fsm_long_counter_clear_t; 1428 1429 #define LSM6DSO32X_FSM_OUTS1 0x4CU 1430 typedef struct 1431 { 1432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1433 uint8_t n_v : 1; 1434 uint8_t p_v : 1; 1435 uint8_t n_z : 1; 1436 uint8_t p_z : 1; 1437 uint8_t n_y : 1; 1438 uint8_t p_y : 1; 1439 uint8_t n_x : 1; 1440 uint8_t p_x : 1; 1441 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1442 uint8_t p_x : 1; 1443 uint8_t n_x : 1; 1444 uint8_t p_y : 1; 1445 uint8_t n_y : 1; 1446 uint8_t p_z : 1; 1447 uint8_t n_z : 1; 1448 uint8_t p_v : 1; 1449 uint8_t n_v : 1; 1450 #endif /* DRV_BYTE_ORDER */ 1451 } lsm6dso32x_fsm_outs1_t; 1452 1453 #define LSM6DSO32X_FSM_OUTS2 0x4DU 1454 typedef struct 1455 { 1456 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1457 uint8_t n_v : 1; 1458 uint8_t p_v : 1; 1459 uint8_t n_z : 1; 1460 uint8_t p_z : 1; 1461 uint8_t n_y : 1; 1462 uint8_t p_y : 1; 1463 uint8_t n_x : 1; 1464 uint8_t p_x : 1; 1465 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1466 uint8_t p_x : 1; 1467 uint8_t n_x : 1; 1468 uint8_t p_y : 1; 1469 uint8_t n_y : 1; 1470 uint8_t p_z : 1; 1471 uint8_t n_z : 1; 1472 uint8_t p_v : 1; 1473 uint8_t n_v : 1; 1474 #endif /* DRV_BYTE_ORDER */ 1475 } lsm6dso32x_fsm_outs2_t; 1476 1477 #define LSM6DSO32X_FSM_OUTS3 0x4EU 1478 typedef struct 1479 { 1480 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1481 uint8_t n_v : 1; 1482 uint8_t p_v : 1; 1483 uint8_t n_z : 1; 1484 uint8_t p_z : 1; 1485 uint8_t n_y : 1; 1486 uint8_t p_y : 1; 1487 uint8_t n_x : 1; 1488 uint8_t p_x : 1; 1489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1490 uint8_t p_x : 1; 1491 uint8_t n_x : 1; 1492 uint8_t p_y : 1; 1493 uint8_t n_y : 1; 1494 uint8_t p_z : 1; 1495 uint8_t n_z : 1; 1496 uint8_t p_v : 1; 1497 uint8_t n_v : 1; 1498 #endif /* DRV_BYTE_ORDER */ 1499 } lsm6dso32x_fsm_outs3_t; 1500 1501 #define LSM6DSO32X_FSM_OUTS4 0x4FU 1502 typedef struct 1503 { 1504 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1505 uint8_t n_v : 1; 1506 uint8_t p_v : 1; 1507 uint8_t n_z : 1; 1508 uint8_t p_z : 1; 1509 uint8_t n_y : 1; 1510 uint8_t p_y : 1; 1511 uint8_t n_x : 1; 1512 uint8_t p_x : 1; 1513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1514 uint8_t p_x : 1; 1515 uint8_t n_x : 1; 1516 uint8_t p_y : 1; 1517 uint8_t n_y : 1; 1518 uint8_t p_z : 1; 1519 uint8_t n_z : 1; 1520 uint8_t p_v : 1; 1521 uint8_t n_v : 1; 1522 #endif /* DRV_BYTE_ORDER */ 1523 } lsm6dso32x_fsm_outs4_t; 1524 1525 #define LSM6DSO32X_FSM_OUTS5 0x50U 1526 typedef struct 1527 { 1528 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1529 uint8_t n_v : 1; 1530 uint8_t p_v : 1; 1531 uint8_t n_z : 1; 1532 uint8_t p_z : 1; 1533 uint8_t n_y : 1; 1534 uint8_t p_y : 1; 1535 uint8_t n_x : 1; 1536 uint8_t p_x : 1; 1537 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1538 uint8_t p_x : 1; 1539 uint8_t n_x : 1; 1540 uint8_t p_y : 1; 1541 uint8_t n_y : 1; 1542 uint8_t p_z : 1; 1543 uint8_t n_z : 1; 1544 uint8_t p_v : 1; 1545 uint8_t n_v : 1; 1546 #endif /* DRV_BYTE_ORDER */ 1547 } lsm6dso32x_fsm_outs5_t; 1548 1549 #define LSM6DSO32X_FSM_OUTS6 0x51U 1550 typedef struct 1551 { 1552 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1553 uint8_t n_v : 1; 1554 uint8_t p_v : 1; 1555 uint8_t n_z : 1; 1556 uint8_t p_z : 1; 1557 uint8_t n_y : 1; 1558 uint8_t p_y : 1; 1559 uint8_t n_x : 1; 1560 uint8_t p_x : 1; 1561 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1562 uint8_t p_x : 1; 1563 uint8_t n_x : 1; 1564 uint8_t p_y : 1; 1565 uint8_t n_y : 1; 1566 uint8_t p_z : 1; 1567 uint8_t n_z : 1; 1568 uint8_t p_v : 1; 1569 uint8_t n_v : 1; 1570 #endif /* DRV_BYTE_ORDER */ 1571 } lsm6dso32x_fsm_outs6_t; 1572 1573 #define LSM6DSO32X_FSM_OUTS7 0x52U 1574 typedef struct 1575 { 1576 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1577 uint8_t n_v : 1; 1578 uint8_t p_v : 1; 1579 uint8_t n_z : 1; 1580 uint8_t p_z : 1; 1581 uint8_t n_y : 1; 1582 uint8_t p_y : 1; 1583 uint8_t n_x : 1; 1584 uint8_t p_x : 1; 1585 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1586 uint8_t p_x : 1; 1587 uint8_t n_x : 1; 1588 uint8_t p_y : 1; 1589 uint8_t n_y : 1; 1590 uint8_t p_z : 1; 1591 uint8_t n_z : 1; 1592 uint8_t p_v : 1; 1593 uint8_t n_v : 1; 1594 #endif /* DRV_BYTE_ORDER */ 1595 } lsm6dso32x_fsm_outs7_t; 1596 1597 #define LSM6DSO32X_FSM_OUTS8 0x53U 1598 typedef struct 1599 { 1600 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1601 uint8_t n_v : 1; 1602 uint8_t p_v : 1; 1603 uint8_t n_z : 1; 1604 uint8_t p_z : 1; 1605 uint8_t n_y : 1; 1606 uint8_t p_y : 1; 1607 uint8_t n_x : 1; 1608 uint8_t p_x : 1; 1609 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1610 uint8_t p_x : 1; 1611 uint8_t n_x : 1; 1612 uint8_t p_y : 1; 1613 uint8_t n_y : 1; 1614 uint8_t p_z : 1; 1615 uint8_t n_z : 1; 1616 uint8_t p_v : 1; 1617 uint8_t n_v : 1; 1618 #endif /* DRV_BYTE_ORDER */ 1619 } lsm6dso32x_fsm_outs8_t; 1620 1621 #define LSM6DSO32X_FSM_OUTS9 0x54U 1622 typedef struct 1623 { 1624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1625 uint8_t n_v : 1; 1626 uint8_t p_v : 1; 1627 uint8_t n_z : 1; 1628 uint8_t p_z : 1; 1629 uint8_t n_y : 1; 1630 uint8_t p_y : 1; 1631 uint8_t n_x : 1; 1632 uint8_t p_x : 1; 1633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1634 uint8_t p_x : 1; 1635 uint8_t n_x : 1; 1636 uint8_t p_y : 1; 1637 uint8_t n_y : 1; 1638 uint8_t p_z : 1; 1639 uint8_t n_z : 1; 1640 uint8_t p_v : 1; 1641 uint8_t n_v : 1; 1642 #endif /* DRV_BYTE_ORDER */ 1643 } lsm6dso32x_fsm_outs9_t; 1644 1645 #define LSM6DSO32X_FSM_OUTS10 0x55U 1646 typedef struct 1647 { 1648 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1649 uint8_t n_v : 1; 1650 uint8_t p_v : 1; 1651 uint8_t n_z : 1; 1652 uint8_t p_z : 1; 1653 uint8_t n_y : 1; 1654 uint8_t p_y : 1; 1655 uint8_t n_x : 1; 1656 uint8_t p_x : 1; 1657 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1658 uint8_t p_x : 1; 1659 uint8_t n_x : 1; 1660 uint8_t p_y : 1; 1661 uint8_t n_y : 1; 1662 uint8_t p_z : 1; 1663 uint8_t n_z : 1; 1664 uint8_t p_v : 1; 1665 uint8_t n_v : 1; 1666 #endif /* DRV_BYTE_ORDER */ 1667 } lsm6dso32x_fsm_outs10_t; 1668 1669 #define LSM6DSO32X_FSM_OUTS11 0x56U 1670 typedef struct 1671 { 1672 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1673 uint8_t n_v : 1; 1674 uint8_t p_v : 1; 1675 uint8_t n_z : 1; 1676 uint8_t p_z : 1; 1677 uint8_t n_y : 1; 1678 uint8_t p_y : 1; 1679 uint8_t n_x : 1; 1680 uint8_t p_x : 1; 1681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1682 uint8_t p_x : 1; 1683 uint8_t n_x : 1; 1684 uint8_t p_y : 1; 1685 uint8_t n_y : 1; 1686 uint8_t p_z : 1; 1687 uint8_t n_z : 1; 1688 uint8_t p_v : 1; 1689 uint8_t n_v : 1; 1690 #endif /* DRV_BYTE_ORDER */ 1691 } lsm6dso32x_fsm_outs11_t; 1692 1693 #define LSM6DSO32X_FSM_OUTS12 0x57U 1694 typedef struct 1695 { 1696 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1697 uint8_t n_v : 1; 1698 uint8_t p_v : 1; 1699 uint8_t n_z : 1; 1700 uint8_t p_z : 1; 1701 uint8_t n_y : 1; 1702 uint8_t p_y : 1; 1703 uint8_t n_x : 1; 1704 uint8_t p_x : 1; 1705 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1706 uint8_t p_x : 1; 1707 uint8_t n_x : 1; 1708 uint8_t p_y : 1; 1709 uint8_t n_y : 1; 1710 uint8_t p_z : 1; 1711 uint8_t n_z : 1; 1712 uint8_t p_v : 1; 1713 uint8_t n_v : 1; 1714 #endif /* DRV_BYTE_ORDER */ 1715 } lsm6dso32x_fsm_outs12_t; 1716 1717 #define LSM6DSO32X_FSM_OUTS13 0x58U 1718 typedef struct 1719 { 1720 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1721 uint8_t n_v : 1; 1722 uint8_t p_v : 1; 1723 uint8_t n_z : 1; 1724 uint8_t p_z : 1; 1725 uint8_t n_y : 1; 1726 uint8_t p_y : 1; 1727 uint8_t n_x : 1; 1728 uint8_t p_x : 1; 1729 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1730 uint8_t p_x : 1; 1731 uint8_t n_x : 1; 1732 uint8_t p_y : 1; 1733 uint8_t n_y : 1; 1734 uint8_t p_z : 1; 1735 uint8_t n_z : 1; 1736 uint8_t p_v : 1; 1737 uint8_t n_v : 1; 1738 #endif /* DRV_BYTE_ORDER */ 1739 } lsm6dso32x_fsm_outs13_t; 1740 1741 #define LSM6DSO32X_FSM_OUTS14 0x59U 1742 typedef struct 1743 { 1744 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1745 uint8_t n_v : 1; 1746 uint8_t p_v : 1; 1747 uint8_t n_z : 1; 1748 uint8_t p_z : 1; 1749 uint8_t n_y : 1; 1750 uint8_t p_y : 1; 1751 uint8_t n_x : 1; 1752 uint8_t p_x : 1; 1753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1754 uint8_t p_x : 1; 1755 uint8_t n_x : 1; 1756 uint8_t p_y : 1; 1757 uint8_t n_y : 1; 1758 uint8_t p_z : 1; 1759 uint8_t n_z : 1; 1760 uint8_t p_v : 1; 1761 uint8_t n_v : 1; 1762 #endif /* DRV_BYTE_ORDER */ 1763 } lsm6dso32x_fsm_outs14_t; 1764 1765 #define LSM6DSO32X_FSM_OUTS15 0x5AU 1766 typedef struct 1767 { 1768 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1769 uint8_t n_v : 1; 1770 uint8_t p_v : 1; 1771 uint8_t n_z : 1; 1772 uint8_t p_z : 1; 1773 uint8_t n_y : 1; 1774 uint8_t p_y : 1; 1775 uint8_t n_x : 1; 1776 uint8_t p_x : 1; 1777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1778 uint8_t p_x : 1; 1779 uint8_t n_x : 1; 1780 uint8_t p_y : 1; 1781 uint8_t n_y : 1; 1782 uint8_t p_z : 1; 1783 uint8_t n_z : 1; 1784 uint8_t p_v : 1; 1785 uint8_t n_v : 1; 1786 #endif /* DRV_BYTE_ORDER */ 1787 } lsm6dso32x_fsm_outs15_t; 1788 1789 #define LSM6DSO32X_FSM_OUTS16 0x5BU 1790 typedef struct 1791 { 1792 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1793 uint8_t n_v : 1; 1794 uint8_t p_v : 1; 1795 uint8_t n_z : 1; 1796 uint8_t p_z : 1; 1797 uint8_t n_y : 1; 1798 uint8_t p_y : 1; 1799 uint8_t n_x : 1; 1800 uint8_t p_x : 1; 1801 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1802 uint8_t p_x : 1; 1803 uint8_t n_x : 1; 1804 uint8_t p_y : 1; 1805 uint8_t n_y : 1; 1806 uint8_t p_z : 1; 1807 uint8_t n_z : 1; 1808 uint8_t p_v : 1; 1809 uint8_t n_v : 1; 1810 #endif /* DRV_BYTE_ORDER */ 1811 } lsm6dso32x_fsm_outs16_t; 1812 1813 #define LSM6DSO32X_EMB_FUNC_ODR_CFG_B 0x5FU 1814 typedef struct 1815 { 1816 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1817 uint8_t not_used_01 : 3; 1818 uint8_t fsm_odr : 2; 1819 uint8_t not_used_02 : 3; 1820 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1821 uint8_t not_used_02 : 3; 1822 uint8_t fsm_odr : 2; 1823 uint8_t not_used_01 : 3; 1824 #endif /* DRV_BYTE_ORDER */ 1825 } lsm6dso32x_emb_func_odr_cfg_b_t; 1826 1827 #define LSM6DSO32X_EMB_FUNC_ODR_CFG_C 0x60U 1828 typedef struct 1829 { 1830 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1831 uint8_t not_used_01 : 4; 1832 uint8_t mlc_odr : 2; 1833 uint8_t not_used_02 : 2; 1834 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1835 uint8_t not_used_02 : 2; 1836 uint8_t mlc_odr : 2; 1837 uint8_t not_used_01 : 4; 1838 #endif /* DRV_BYTE_ORDER */ 1839 } lsm6dso32x_emb_func_odr_cfg_c_t; 1840 1841 #define LSM6DSO32X_STEP_COUNTER_L 0x62U 1842 #define LSM6DSO32X_STEP_COUNTER_H 0x63U 1843 #define LSM6DSO32X_EMB_FUNC_SRC 0x64U 1844 typedef struct 1845 { 1846 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1847 uint8_t not_used_01 : 2; 1848 uint8_t stepcounter_bit_set : 1; 1849 uint8_t step_overflow : 1; 1850 uint8_t step_count_delta_ia : 1; 1851 uint8_t step_detected : 1; 1852 uint8_t not_used_02 : 1; 1853 uint8_t pedo_rst_step : 1; 1854 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1855 uint8_t pedo_rst_step : 1; 1856 uint8_t not_used_02 : 1; 1857 uint8_t step_detected : 1; 1858 uint8_t step_count_delta_ia : 1; 1859 uint8_t step_overflow : 1; 1860 uint8_t stepcounter_bit_set : 1; 1861 uint8_t not_used_01 : 2; 1862 #endif /* DRV_BYTE_ORDER */ 1863 } lsm6dso32x_emb_func_src_t; 1864 1865 #define LSM6DSO32X_EMB_FUNC_INIT_A 0x66U 1866 typedef struct 1867 { 1868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1869 uint8_t not_used_01 : 3; 1870 uint8_t step_det_init : 1; 1871 uint8_t tilt_init : 1; 1872 uint8_t sig_mot_init : 1; 1873 uint8_t not_used_02 : 2; 1874 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1875 uint8_t not_used_02 : 2; 1876 uint8_t sig_mot_init : 1; 1877 uint8_t tilt_init : 1; 1878 uint8_t step_det_init : 1; 1879 uint8_t not_used_01 : 3; 1880 #endif /* DRV_BYTE_ORDER */ 1881 } lsm6dso32x_emb_func_init_a_t; 1882 1883 #define LSM6DSO32X_EMB_FUNC_INIT_B 0x67U 1884 typedef struct 1885 { 1886 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1887 uint8_t fsm_init : 1; 1888 uint8_t not_used_01 : 2; 1889 uint8_t fifo_compr_init : 1; 1890 uint8_t mlc_init : 1; 1891 uint8_t not_used_02 : 3; 1892 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1893 uint8_t not_used_02 : 3; 1894 uint8_t mlc_init : 1; 1895 uint8_t fifo_compr_init : 1; 1896 uint8_t not_used_01 : 2; 1897 uint8_t fsm_init : 1; 1898 #endif /* DRV_BYTE_ORDER */ 1899 } lsm6dso32x_emb_func_init_b_t; 1900 1901 #define LSM6DSO32X_MLC0_SRC 0x70U 1902 #define LSM6DSO32X_MLC1_SRC 0x71U 1903 #define LSM6DSO32X_MLC2_SRC 0x72U 1904 #define LSM6DSO32X_MLC3_SRC 0x73U 1905 #define LSM6DSO32X_MLC4_SRC 0x74U 1906 #define LSM6DSO32X_MLC5_SRC 0x75U 1907 #define LSM6DSO32X_MLC6_SRC 0x76U 1908 #define LSM6DSO32X_MLC7_SRC 0x77U 1909 #define LSM6DSO32X_MAG_SENSITIVITY_L 0xBAU 1910 #define LSM6DSO32X_MAG_SENSITIVITY_H 0xBBU 1911 #define LSM6DSO32X_MAG_OFFX_L 0xC0U 1912 #define LSM6DSO32X_MAG_OFFX_H 0xC1U 1913 #define LSM6DSO32X_MAG_OFFY_L 0xC2U 1914 #define LSM6DSO32X_MAG_OFFY_H 0xC3U 1915 #define LSM6DSO32X_MAG_OFFZ_L 0xC4U 1916 #define LSM6DSO32X_MAG_OFFZ_H 0xC5U 1917 #define LSM6DSO32X_MAG_SI_XX_L 0xC6U 1918 #define LSM6DSO32X_MAG_SI_XX_H 0xC7U 1919 #define LSM6DSO32X_MAG_SI_XY_L 0xC8U 1920 #define LSM6DSO32X_MAG_SI_XY_H 0xC9U 1921 #define LSM6DSO32X_MAG_SI_XZ_L 0xCAU 1922 #define LSM6DSO32X_MAG_SI_XZ_H 0xCBU 1923 #define LSM6DSO32X_MAG_SI_YY_L 0xCCU 1924 #define LSM6DSO32X_MAG_SI_YY_H 0xCDU 1925 #define LSM6DSO32X_MAG_SI_YZ_L 0xCEU 1926 #define LSM6DSO32X_MAG_SI_YZ_H 0xCFU 1927 #define LSM6DSO32X_MAG_SI_ZZ_L 0xD0U 1928 #define LSM6DSO32X_MAG_SI_ZZ_H 0xD1U 1929 #define LSM6DSO32X_MAG_CFG_A 0xD4U 1930 typedef struct 1931 { 1932 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1933 uint8_t mag_z_axis : 3; 1934 uint8_t not_used_01 : 1; 1935 uint8_t mag_y_axis : 3; 1936 uint8_t not_used_02 : 1; 1937 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1938 uint8_t not_used_02 : 1; 1939 uint8_t mag_y_axis : 3; 1940 uint8_t not_used_01 : 1; 1941 uint8_t mag_z_axis : 3; 1942 #endif /* DRV_BYTE_ORDER */ 1943 } lsm6dso32x_mag_cfg_a_t; 1944 1945 #define LSM6DSO32X_MAG_CFG_B 0xD5U 1946 typedef struct 1947 { 1948 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1949 uint8_t mag_x_axis : 3; 1950 uint8_t not_used_01 : 5; 1951 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1952 uint8_t not_used_01 : 5; 1953 uint8_t mag_x_axis : 3; 1954 #endif /* DRV_BYTE_ORDER */ 1955 } lsm6dso32x_mag_cfg_b_t; 1956 1957 #define LSM6DSO32X_FSM_LC_TIMEOUT_L 0x17AU 1958 #define LSM6DSO32X_FSM_LC_TIMEOUT_H 0x17BU 1959 #define LSM6DSO32X_FSM_PROGRAMS 0x17CU 1960 #define LSM6DSO32X_FSM_START_ADD_L 0x17EU 1961 #define LSM6DSO32X_FSM_START_ADD_H 0x17FU 1962 #define LSM6DSO32X_PEDO_CMD_REG 0x183U 1963 typedef struct 1964 { 1965 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1966 uint8_t ad_det_en : 1; 1967 uint8_t not_used_01 : 1; 1968 uint8_t fp_rejection_en : 1; 1969 uint8_t carry_count_en : 1; 1970 uint8_t not_used_02 : 4; 1971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1972 uint8_t not_used_02 : 4; 1973 uint8_t carry_count_en : 1; 1974 uint8_t fp_rejection_en : 1; 1975 uint8_t not_used_01 : 1; 1976 uint8_t ad_det_en : 1; 1977 #endif /* DRV_BYTE_ORDER */ 1978 } lsm6dso32x_pedo_cmd_reg_t; 1979 1980 #define LSM6DSO32X_PEDO_DEB_STEPS_CONF 0x184U 1981 #define LSM6DSO32X_PEDO_SC_DELTAT_L 0x1D0U 1982 #define LSM6DSO32X_PEDO_SC_DELTAT_H 0x1D1U 1983 1984 #define LSM6DSO32X_MLC_MAG_SENSITIVITY_L 0x1E8U 1985 #define LSM6DSO32X_MLC_MAG_SENSITIVITY_H 0x1E9U 1986 1987 #define LSM6DSO32X_SENSOR_HUB_1 0x02U 1988 typedef struct 1989 { 1990 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1991 uint8_t bit0 : 1; 1992 uint8_t bit1 : 1; 1993 uint8_t bit2 : 1; 1994 uint8_t bit3 : 1; 1995 uint8_t bit4 : 1; 1996 uint8_t bit5 : 1; 1997 uint8_t bit6 : 1; 1998 uint8_t bit7 : 1; 1999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2000 uint8_t bit7 : 1; 2001 uint8_t bit6 : 1; 2002 uint8_t bit5 : 1; 2003 uint8_t bit4 : 1; 2004 uint8_t bit3 : 1; 2005 uint8_t bit2 : 1; 2006 uint8_t bit1 : 1; 2007 uint8_t bit0 : 1; 2008 #endif /* DRV_BYTE_ORDER */ 2009 } lsm6dso32x_sensor_hub_1_t; 2010 2011 #define LSM6DSO32X_SENSOR_HUB_2 0x03U 2012 typedef struct 2013 { 2014 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2015 uint8_t bit0 : 1; 2016 uint8_t bit1 : 1; 2017 uint8_t bit2 : 1; 2018 uint8_t bit3 : 1; 2019 uint8_t bit4 : 1; 2020 uint8_t bit5 : 1; 2021 uint8_t bit6 : 1; 2022 uint8_t bit7 : 1; 2023 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2024 uint8_t bit7 : 1; 2025 uint8_t bit6 : 1; 2026 uint8_t bit5 : 1; 2027 uint8_t bit4 : 1; 2028 uint8_t bit3 : 1; 2029 uint8_t bit2 : 1; 2030 uint8_t bit1 : 1; 2031 uint8_t bit0 : 1; 2032 #endif /* DRV_BYTE_ORDER */ 2033 } lsm6dso32x_sensor_hub_2_t; 2034 2035 #define LSM6DSO32X_SENSOR_HUB_3 0x04U 2036 typedef struct 2037 { 2038 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2039 uint8_t bit0 : 1; 2040 uint8_t bit1 : 1; 2041 uint8_t bit2 : 1; 2042 uint8_t bit3 : 1; 2043 uint8_t bit4 : 1; 2044 uint8_t bit5 : 1; 2045 uint8_t bit6 : 1; 2046 uint8_t bit7 : 1; 2047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2048 uint8_t bit7 : 1; 2049 uint8_t bit6 : 1; 2050 uint8_t bit5 : 1; 2051 uint8_t bit4 : 1; 2052 uint8_t bit3 : 1; 2053 uint8_t bit2 : 1; 2054 uint8_t bit1 : 1; 2055 uint8_t bit0 : 1; 2056 #endif /* DRV_BYTE_ORDER */ 2057 } lsm6dso32x_sensor_hub_3_t; 2058 2059 #define LSM6DSO32X_SENSOR_HUB_4 0x05U 2060 typedef struct 2061 { 2062 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2063 uint8_t bit0 : 1; 2064 uint8_t bit1 : 1; 2065 uint8_t bit2 : 1; 2066 uint8_t bit3 : 1; 2067 uint8_t bit4 : 1; 2068 uint8_t bit5 : 1; 2069 uint8_t bit6 : 1; 2070 uint8_t bit7 : 1; 2071 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2072 uint8_t bit7 : 1; 2073 uint8_t bit6 : 1; 2074 uint8_t bit5 : 1; 2075 uint8_t bit4 : 1; 2076 uint8_t bit3 : 1; 2077 uint8_t bit2 : 1; 2078 uint8_t bit1 : 1; 2079 uint8_t bit0 : 1; 2080 #endif /* DRV_BYTE_ORDER */ 2081 } lsm6dso32x_sensor_hub_4_t; 2082 2083 #define LSM6DSO32X_SENSOR_HUB_5 0x06U 2084 typedef struct 2085 { 2086 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2087 uint8_t bit0 : 1; 2088 uint8_t bit1 : 1; 2089 uint8_t bit2 : 1; 2090 uint8_t bit3 : 1; 2091 uint8_t bit4 : 1; 2092 uint8_t bit5 : 1; 2093 uint8_t bit6 : 1; 2094 uint8_t bit7 : 1; 2095 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2096 uint8_t bit7 : 1; 2097 uint8_t bit6 : 1; 2098 uint8_t bit5 : 1; 2099 uint8_t bit4 : 1; 2100 uint8_t bit3 : 1; 2101 uint8_t bit2 : 1; 2102 uint8_t bit1 : 1; 2103 uint8_t bit0 : 1; 2104 #endif /* DRV_BYTE_ORDER */ 2105 } lsm6dso32x_sensor_hub_5_t; 2106 2107 #define LSM6DSO32X_SENSOR_HUB_6 0x07U 2108 typedef struct 2109 { 2110 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2111 uint8_t bit0 : 1; 2112 uint8_t bit1 : 1; 2113 uint8_t bit2 : 1; 2114 uint8_t bit3 : 1; 2115 uint8_t bit4 : 1; 2116 uint8_t bit5 : 1; 2117 uint8_t bit6 : 1; 2118 uint8_t bit7 : 1; 2119 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2120 uint8_t bit7 : 1; 2121 uint8_t bit6 : 1; 2122 uint8_t bit5 : 1; 2123 uint8_t bit4 : 1; 2124 uint8_t bit3 : 1; 2125 uint8_t bit2 : 1; 2126 uint8_t bit1 : 1; 2127 uint8_t bit0 : 1; 2128 #endif /* DRV_BYTE_ORDER */ 2129 } lsm6dso32x_sensor_hub_6_t; 2130 2131 #define LSM6DSO32X_SENSOR_HUB_7 0x08U 2132 typedef struct 2133 { 2134 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2135 uint8_t bit0 : 1; 2136 uint8_t bit1 : 1; 2137 uint8_t bit2 : 1; 2138 uint8_t bit3 : 1; 2139 uint8_t bit4 : 1; 2140 uint8_t bit5 : 1; 2141 uint8_t bit6 : 1; 2142 uint8_t bit7 : 1; 2143 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2144 uint8_t bit7 : 1; 2145 uint8_t bit6 : 1; 2146 uint8_t bit5 : 1; 2147 uint8_t bit4 : 1; 2148 uint8_t bit3 : 1; 2149 uint8_t bit2 : 1; 2150 uint8_t bit1 : 1; 2151 uint8_t bit0 : 1; 2152 #endif /* DRV_BYTE_ORDER */ 2153 } lsm6dso32x_sensor_hub_7_t; 2154 2155 #define LSM6DSO32X_SENSOR_HUB_8 0x09U 2156 typedef struct 2157 { 2158 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2159 uint8_t bit0 : 1; 2160 uint8_t bit1 : 1; 2161 uint8_t bit2 : 1; 2162 uint8_t bit3 : 1; 2163 uint8_t bit4 : 1; 2164 uint8_t bit5 : 1; 2165 uint8_t bit6 : 1; 2166 uint8_t bit7 : 1; 2167 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2168 uint8_t bit7 : 1; 2169 uint8_t bit6 : 1; 2170 uint8_t bit5 : 1; 2171 uint8_t bit4 : 1; 2172 uint8_t bit3 : 1; 2173 uint8_t bit2 : 1; 2174 uint8_t bit1 : 1; 2175 uint8_t bit0 : 1; 2176 #endif /* DRV_BYTE_ORDER */ 2177 } lsm6dso32x_sensor_hub_8_t; 2178 2179 #define LSM6DSO32X_SENSOR_HUB_9 0x0AU 2180 typedef struct 2181 { 2182 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2183 uint8_t bit0 : 1; 2184 uint8_t bit1 : 1; 2185 uint8_t bit2 : 1; 2186 uint8_t bit3 : 1; 2187 uint8_t bit4 : 1; 2188 uint8_t bit5 : 1; 2189 uint8_t bit6 : 1; 2190 uint8_t bit7 : 1; 2191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2192 uint8_t bit7 : 1; 2193 uint8_t bit6 : 1; 2194 uint8_t bit5 : 1; 2195 uint8_t bit4 : 1; 2196 uint8_t bit3 : 1; 2197 uint8_t bit2 : 1; 2198 uint8_t bit1 : 1; 2199 uint8_t bit0 : 1; 2200 #endif /* DRV_BYTE_ORDER */ 2201 } lsm6dso32x_sensor_hub_9_t; 2202 2203 #define LSM6DSO32X_SENSOR_HUB_10 0x0BU 2204 typedef struct 2205 { 2206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2207 uint8_t bit0 : 1; 2208 uint8_t bit1 : 1; 2209 uint8_t bit2 : 1; 2210 uint8_t bit3 : 1; 2211 uint8_t bit4 : 1; 2212 uint8_t bit5 : 1; 2213 uint8_t bit6 : 1; 2214 uint8_t bit7 : 1; 2215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2216 uint8_t bit7 : 1; 2217 uint8_t bit6 : 1; 2218 uint8_t bit5 : 1; 2219 uint8_t bit4 : 1; 2220 uint8_t bit3 : 1; 2221 uint8_t bit2 : 1; 2222 uint8_t bit1 : 1; 2223 uint8_t bit0 : 1; 2224 #endif /* DRV_BYTE_ORDER */ 2225 } lsm6dso32x_sensor_hub_10_t; 2226 2227 #define LSM6DSO32X_SENSOR_HUB_11 0x0CU 2228 typedef struct 2229 { 2230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2231 uint8_t bit0 : 1; 2232 uint8_t bit1 : 1; 2233 uint8_t bit2 : 1; 2234 uint8_t bit3 : 1; 2235 uint8_t bit4 : 1; 2236 uint8_t bit5 : 1; 2237 uint8_t bit6 : 1; 2238 uint8_t bit7 : 1; 2239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2240 uint8_t bit7 : 1; 2241 uint8_t bit6 : 1; 2242 uint8_t bit5 : 1; 2243 uint8_t bit4 : 1; 2244 uint8_t bit3 : 1; 2245 uint8_t bit2 : 1; 2246 uint8_t bit1 : 1; 2247 uint8_t bit0 : 1; 2248 #endif /* DRV_BYTE_ORDER */ 2249 } lsm6dso32x_sensor_hub_11_t; 2250 2251 #define LSM6DSO32X_SENSOR_HUB_12 0x0DU 2252 typedef struct 2253 { 2254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2255 uint8_t bit0 : 1; 2256 uint8_t bit1 : 1; 2257 uint8_t bit2 : 1; 2258 uint8_t bit3 : 1; 2259 uint8_t bit4 : 1; 2260 uint8_t bit5 : 1; 2261 uint8_t bit6 : 1; 2262 uint8_t bit7 : 1; 2263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2264 uint8_t bit7 : 1; 2265 uint8_t bit6 : 1; 2266 uint8_t bit5 : 1; 2267 uint8_t bit4 : 1; 2268 uint8_t bit3 : 1; 2269 uint8_t bit2 : 1; 2270 uint8_t bit1 : 1; 2271 uint8_t bit0 : 1; 2272 #endif /* DRV_BYTE_ORDER */ 2273 } lsm6dso32x_sensor_hub_12_t; 2274 2275 #define LSM6DSO32X_SENSOR_HUB_13 0x0EU 2276 typedef struct 2277 { 2278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2279 uint8_t bit0 : 1; 2280 uint8_t bit1 : 1; 2281 uint8_t bit2 : 1; 2282 uint8_t bit3 : 1; 2283 uint8_t bit4 : 1; 2284 uint8_t bit5 : 1; 2285 uint8_t bit6 : 1; 2286 uint8_t bit7 : 1; 2287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2288 uint8_t bit7 : 1; 2289 uint8_t bit6 : 1; 2290 uint8_t bit5 : 1; 2291 uint8_t bit4 : 1; 2292 uint8_t bit3 : 1; 2293 uint8_t bit2 : 1; 2294 uint8_t bit1 : 1; 2295 uint8_t bit0 : 1; 2296 #endif /* DRV_BYTE_ORDER */ 2297 } lsm6dso32x_sensor_hub_13_t; 2298 2299 #define LSM6DSO32X_SENSOR_HUB_14 0x0FU 2300 typedef struct 2301 { 2302 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2303 uint8_t bit0 : 1; 2304 uint8_t bit1 : 1; 2305 uint8_t bit2 : 1; 2306 uint8_t bit3 : 1; 2307 uint8_t bit4 : 1; 2308 uint8_t bit5 : 1; 2309 uint8_t bit6 : 1; 2310 uint8_t bit7 : 1; 2311 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2312 uint8_t bit7 : 1; 2313 uint8_t bit6 : 1; 2314 uint8_t bit5 : 1; 2315 uint8_t bit4 : 1; 2316 uint8_t bit3 : 1; 2317 uint8_t bit2 : 1; 2318 uint8_t bit1 : 1; 2319 uint8_t bit0 : 1; 2320 #endif /* DRV_BYTE_ORDER */ 2321 } lsm6dso32x_sensor_hub_14_t; 2322 2323 #define LSM6DSO32X_SENSOR_HUB_15 0x10U 2324 typedef struct 2325 { 2326 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2327 uint8_t bit0 : 1; 2328 uint8_t bit1 : 1; 2329 uint8_t bit2 : 1; 2330 uint8_t bit3 : 1; 2331 uint8_t bit4 : 1; 2332 uint8_t bit5 : 1; 2333 uint8_t bit6 : 1; 2334 uint8_t bit7 : 1; 2335 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2336 uint8_t bit7 : 1; 2337 uint8_t bit6 : 1; 2338 uint8_t bit5 : 1; 2339 uint8_t bit4 : 1; 2340 uint8_t bit3 : 1; 2341 uint8_t bit2 : 1; 2342 uint8_t bit1 : 1; 2343 uint8_t bit0 : 1; 2344 #endif /* DRV_BYTE_ORDER */ 2345 } lsm6dso32x_sensor_hub_15_t; 2346 2347 #define LSM6DSO32X_SENSOR_HUB_16 0x11U 2348 typedef struct 2349 { 2350 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2351 uint8_t bit0 : 1; 2352 uint8_t bit1 : 1; 2353 uint8_t bit2 : 1; 2354 uint8_t bit3 : 1; 2355 uint8_t bit4 : 1; 2356 uint8_t bit5 : 1; 2357 uint8_t bit6 : 1; 2358 uint8_t bit7 : 1; 2359 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2360 uint8_t bit7 : 1; 2361 uint8_t bit6 : 1; 2362 uint8_t bit5 : 1; 2363 uint8_t bit4 : 1; 2364 uint8_t bit3 : 1; 2365 uint8_t bit2 : 1; 2366 uint8_t bit1 : 1; 2367 uint8_t bit0 : 1; 2368 #endif /* DRV_BYTE_ORDER */ 2369 } lsm6dso32x_sensor_hub_16_t; 2370 2371 #define LSM6DSO32X_SENSOR_HUB_17 0x12U 2372 typedef struct 2373 { 2374 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2375 uint8_t bit0 : 1; 2376 uint8_t bit1 : 1; 2377 uint8_t bit2 : 1; 2378 uint8_t bit3 : 1; 2379 uint8_t bit4 : 1; 2380 uint8_t bit5 : 1; 2381 uint8_t bit6 : 1; 2382 uint8_t bit7 : 1; 2383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2384 uint8_t bit7 : 1; 2385 uint8_t bit6 : 1; 2386 uint8_t bit5 : 1; 2387 uint8_t bit4 : 1; 2388 uint8_t bit3 : 1; 2389 uint8_t bit2 : 1; 2390 uint8_t bit1 : 1; 2391 uint8_t bit0 : 1; 2392 #endif /* DRV_BYTE_ORDER */ 2393 } lsm6dso32x_sensor_hub_17_t; 2394 2395 #define LSM6DSO32X_SENSOR_HUB_18 0x13U 2396 typedef struct 2397 { 2398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2399 uint8_t bit0 : 1; 2400 uint8_t bit1 : 1; 2401 uint8_t bit2 : 1; 2402 uint8_t bit3 : 1; 2403 uint8_t bit4 : 1; 2404 uint8_t bit5 : 1; 2405 uint8_t bit6 : 1; 2406 uint8_t bit7 : 1; 2407 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2408 uint8_t bit7 : 1; 2409 uint8_t bit6 : 1; 2410 uint8_t bit5 : 1; 2411 uint8_t bit4 : 1; 2412 uint8_t bit3 : 1; 2413 uint8_t bit2 : 1; 2414 uint8_t bit1 : 1; 2415 uint8_t bit0 : 1; 2416 #endif /* DRV_BYTE_ORDER */ 2417 } lsm6dso32x_sensor_hub_18_t; 2418 2419 #define LSM6DSO32X_MASTER_CONFIG 0x14U 2420 typedef struct 2421 { 2422 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2423 uint8_t aux_sens_on : 2; 2424 uint8_t master_on : 1; 2425 uint8_t shub_pu_en : 1; 2426 uint8_t pass_through_mode : 1; 2427 uint8_t start_config : 1; 2428 uint8_t write_once : 1; 2429 uint8_t rst_master_regs : 1; 2430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2431 uint8_t rst_master_regs : 1; 2432 uint8_t write_once : 1; 2433 uint8_t start_config : 1; 2434 uint8_t pass_through_mode : 1; 2435 uint8_t shub_pu_en : 1; 2436 uint8_t master_on : 1; 2437 uint8_t aux_sens_on : 2; 2438 #endif /* DRV_BYTE_ORDER */ 2439 } lsm6dso32x_master_config_t; 2440 2441 #define LSM6DSO32X_SLV0_ADD 0x15U 2442 typedef struct 2443 { 2444 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2445 uint8_t rw_0 : 1; 2446 uint8_t slave0 : 7; 2447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2448 uint8_t slave0 : 7; 2449 uint8_t rw_0 : 1; 2450 #endif /* DRV_BYTE_ORDER */ 2451 } lsm6dso32x_slv0_add_t; 2452 2453 #define LSM6DSO32X_SLV0_SUBADD 0x16U 2454 typedef struct 2455 { 2456 uint8_t slave0_reg : 8; 2457 } lsm6dso32x_slv0_subadd_t; 2458 2459 #define LSM6DSO32X_SLV0_CONFIG 0x17U 2460 typedef struct 2461 { 2462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2463 uint8_t slave0_numop : 3; 2464 uint8_t batch_ext_sens_0_en : 1; 2465 uint8_t not_used_01 : 2; 2466 uint8_t shub_odr : 2; 2467 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2468 uint8_t shub_odr : 2; 2469 uint8_t not_used_01 : 2; 2470 uint8_t batch_ext_sens_0_en : 1; 2471 uint8_t slave0_numop : 3; 2472 #endif /* DRV_BYTE_ORDER */ 2473 } lsm6dso32x_slv0_config_t; 2474 2475 #define LSM6DSO32X_SLV1_ADD 0x18U 2476 typedef struct 2477 { 2478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2479 uint8_t r_1 : 1; 2480 uint8_t slave1_add : 7; 2481 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2482 uint8_t slave1_add : 7; 2483 uint8_t r_1 : 1; 2484 #endif /* DRV_BYTE_ORDER */ 2485 } lsm6dso32x_slv1_add_t; 2486 2487 #define LSM6DSO32X_SLV1_SUBADD 0x19U 2488 typedef struct 2489 { 2490 uint8_t slave1_reg : 8; 2491 } lsm6dso32x_slv1_subadd_t; 2492 2493 #define LSM6DSO32X_SLV1_CONFIG 0x1AU 2494 typedef struct 2495 { 2496 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2497 uint8_t slave1_numop : 3; 2498 uint8_t batch_ext_sens_1_en : 1; 2499 uint8_t not_used_01 : 4; 2500 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2501 uint8_t not_used_01 : 4; 2502 uint8_t batch_ext_sens_1_en : 1; 2503 uint8_t slave1_numop : 3; 2504 #endif /* DRV_BYTE_ORDER */ 2505 } lsm6dso32x_slv1_config_t; 2506 2507 #define LSM6DSO32X_SLV2_ADD 0x1BU 2508 typedef struct 2509 { 2510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2511 uint8_t r_2 : 1; 2512 uint8_t slave2_add : 7; 2513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2514 uint8_t slave2_add : 7; 2515 uint8_t r_2 : 1; 2516 #endif /* DRV_BYTE_ORDER */ 2517 } lsm6dso32x_slv2_add_t; 2518 2519 #define LSM6DSO32X_SLV2_SUBADD 0x1CU 2520 typedef struct 2521 { 2522 uint8_t slave2_reg : 8; 2523 } lsm6dso32x_slv2_subadd_t; 2524 2525 #define LSM6DSO32X_SLV2_CONFIG 0x1DU 2526 typedef struct 2527 { 2528 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2529 uint8_t slave2_numop : 3; 2530 uint8_t batch_ext_sens_2_en : 1; 2531 uint8_t not_used_01 : 4; 2532 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2533 uint8_t not_used_01 : 4; 2534 uint8_t batch_ext_sens_2_en : 1; 2535 uint8_t slave2_numop : 3; 2536 #endif /* DRV_BYTE_ORDER */ 2537 } lsm6dso32x_slv2_config_t; 2538 2539 #define LSM6DSO32X_SLV3_ADD 0x1EU 2540 typedef struct 2541 { 2542 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2543 uint8_t r_3 : 1; 2544 uint8_t slave3_add : 7; 2545 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2546 uint8_t slave3_add : 7; 2547 uint8_t r_3 : 1; 2548 #endif /* DRV_BYTE_ORDER */ 2549 } lsm6dso32x_slv3_add_t; 2550 2551 #define LSM6DSO32X_SLV3_SUBADD 0x1FU 2552 typedef struct 2553 { 2554 uint8_t slave3_reg : 8; 2555 } lsm6dso32x_slv3_subadd_t; 2556 2557 #define LSM6DSO32X_SLV3_CONFIG 0x20U 2558 typedef struct 2559 { 2560 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2561 uint8_t slave3_numop : 3; 2562 uint8_t batch_ext_sens_3_en : 1; 2563 uint8_t not_used_01 : 4; 2564 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2565 uint8_t not_used_01 : 4; 2566 uint8_t batch_ext_sens_3_en : 1; 2567 uint8_t slave3_numop : 3; 2568 #endif /* DRV_BYTE_ORDER */ 2569 } lsm6dso32x_slv3_config_t; 2570 2571 #define LSM6DSO32X_DATAWRITE_SLV0 0x21U 2572 typedef struct 2573 { 2574 uint8_t slave0_dataw : 8; 2575 } lsm6dso32x_datawrite_slv0_t; 2576 2577 #define LSM6DSO32X_STATUS_MASTER 0x22U 2578 typedef struct 2579 { 2580 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2581 uint8_t sens_hub_endop : 1; 2582 uint8_t not_used_01 : 2; 2583 uint8_t slave0_nack : 1; 2584 uint8_t slave1_nack : 1; 2585 uint8_t slave2_nack : 1; 2586 uint8_t slave3_nack : 1; 2587 uint8_t wr_once_done : 1; 2588 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2589 uint8_t wr_once_done : 1; 2590 uint8_t slave3_nack : 1; 2591 uint8_t slave2_nack : 1; 2592 uint8_t slave1_nack : 1; 2593 uint8_t slave0_nack : 1; 2594 uint8_t not_used_01 : 2; 2595 uint8_t sens_hub_endop : 1; 2596 #endif /* DRV_BYTE_ORDER */ 2597 } lsm6dso32x_status_master_t; 2598 2599 #define LSM6DSO32X_START_FSM_ADD 0x0400U 2600 2601 /** 2602 * @defgroup LSM6DSO32X_Register_Union 2603 * @brief This union group all the registers that has a bitfield 2604 * description. 2605 * This union is useful but not need by the driver. 2606 * 2607 * REMOVING this union you are compliant with: 2608 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2609 * 2610 * @{ 2611 * 2612 */ 2613 typedef union 2614 { 2615 lsm6dso32x_func_cfg_access_t func_cfg_access; 2616 lsm6dso32x_pin_ctrl_t pin_ctrl; 2617 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1; 2618 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2; 2619 lsm6dso32x_fifo_ctrl3_t fifo_ctrl3; 2620 lsm6dso32x_fifo_ctrl4_t fifo_ctrl4; 2621 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1; 2622 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2; 2623 lsm6dso32x_int1_ctrl_t int1_ctrl; 2624 lsm6dso32x_int2_ctrl_t int2_ctrl; 2625 lsm6dso32x_ctrl1_xl_t ctrl1_xl; 2626 lsm6dso32x_ctrl2_g_t ctrl2_g; 2627 lsm6dso32x_ctrl3_c_t ctrl3_c; 2628 lsm6dso32x_ctrl4_c_t ctrl4_c; 2629 lsm6dso32x_ctrl5_c_t ctrl5_c; 2630 lsm6dso32x_ctrl6_c_t ctrl6_c; 2631 lsm6dso32x_ctrl7_g_t ctrl7_g; 2632 lsm6dso32x_ctrl8_xl_t ctrl8_xl; 2633 lsm6dso32x_ctrl9_xl_t ctrl9_xl; 2634 lsm6dso32x_ctrl10_c_t ctrl10_c; 2635 lsm6dso32x_all_int_src_t all_int_src; 2636 lsm6dso32x_wake_up_src_t wake_up_src; 2637 lsm6dso32x_tap_src_t tap_src; 2638 lsm6dso32x_d6d_src_t d6d_src; 2639 lsm6dso32x_status_reg_t status_reg; 2640 lsm6dso32x_fifo_status1_t fifo_status1; 2641 lsm6dso32x_fifo_status2_t fifo_status2; 2642 lsm6dso32x_tap_cfg0_t tap_cfg0; 2643 lsm6dso32x_tap_cfg1_t tap_cfg1; 2644 lsm6dso32x_tap_cfg2_t tap_cfg2; 2645 lsm6dso32x_tap_ths_6d_t tap_ths_6d; 2646 lsm6dso32x_int_dur2_t int_dur2; 2647 lsm6dso32x_wake_up_ths_t wake_up_ths; 2648 lsm6dso32x_wake_up_dur_t wake_up_dur; 2649 lsm6dso32x_free_fall_t free_fall; 2650 lsm6dso32x_md1_cfg_t md1_cfg; 2651 lsm6dso32x_md2_cfg_t md2_cfg; 2652 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; 2653 lsm6dso32x_internal_freq_fine_t internal_freq_fine; 2654 lsm6dso32x_fifo_data_out_tag_t fifo_data_out_tag; 2655 lsm6dso32x_page_sel_t page_sel; 2656 lsm6dso32x_emb_func_en_a_t emb_func_en_a; 2657 lsm6dso32x_emb_func_en_b_t emb_func_en_b; 2658 lsm6dso32x_page_address_t page_address; 2659 lsm6dso32x_page_value_t page_value; 2660 lsm6dso32x_emb_func_int1_t emb_func_int1; 2661 lsm6dso32x_fsm_int1_a_t fsm_int1_a; 2662 lsm6dso32x_fsm_int1_b_t fsm_int1_b; 2663 lsm6dso32x_emb_func_int2_t emb_func_int2; 2664 lsm6dso32x_fsm_int2_a_t fsm_int2_a; 2665 lsm6dso32x_fsm_int2_b_t fsm_int2_b; 2666 lsm6dso32x_emb_func_status_t emb_func_status; 2667 lsm6dso32x_fsm_status_a_t fsm_status_a; 2668 lsm6dso32x_fsm_status_b_t fsm_status_b; 2669 lsm6dso32x_page_rw_t page_rw; 2670 lsm6dso32x_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2671 lsm6dso32x_fsm_enable_a_t fsm_enable_a; 2672 lsm6dso32x_fsm_enable_b_t fsm_enable_b; 2673 lsm6dso32x_fsm_long_counter_clear_t fsm_long_counter_clear; 2674 lsm6dso32x_fsm_outs1_t fsm_outs1; 2675 lsm6dso32x_fsm_outs2_t fsm_outs2; 2676 lsm6dso32x_fsm_outs3_t fsm_outs3; 2677 lsm6dso32x_fsm_outs4_t fsm_outs4; 2678 lsm6dso32x_fsm_outs5_t fsm_outs5; 2679 lsm6dso32x_fsm_outs6_t fsm_outs6; 2680 lsm6dso32x_fsm_outs7_t fsm_outs7; 2681 lsm6dso32x_fsm_outs8_t fsm_outs8; 2682 lsm6dso32x_fsm_outs9_t fsm_outs9; 2683 lsm6dso32x_fsm_outs10_t fsm_outs10; 2684 lsm6dso32x_fsm_outs11_t fsm_outs11; 2685 lsm6dso32x_fsm_outs12_t fsm_outs12; 2686 lsm6dso32x_fsm_outs13_t fsm_outs13; 2687 lsm6dso32x_fsm_outs14_t fsm_outs14; 2688 lsm6dso32x_fsm_outs15_t fsm_outs15; 2689 lsm6dso32x_fsm_outs16_t fsm_outs16; 2690 lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2691 lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 2692 lsm6dso32x_emb_func_src_t emb_func_src; 2693 lsm6dso32x_emb_func_init_a_t emb_func_init_a; 2694 lsm6dso32x_emb_func_init_b_t emb_func_init_b; 2695 lsm6dso32x_mag_cfg_a_t mag_cfg_a; 2696 lsm6dso32x_mag_cfg_b_t mag_cfg_b; 2697 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg; 2698 lsm6dso32x_sensor_hub_1_t sensor_hub_1; 2699 lsm6dso32x_sensor_hub_2_t sensor_hub_2; 2700 lsm6dso32x_sensor_hub_3_t sensor_hub_3; 2701 lsm6dso32x_sensor_hub_4_t sensor_hub_4; 2702 lsm6dso32x_sensor_hub_5_t sensor_hub_5; 2703 lsm6dso32x_sensor_hub_6_t sensor_hub_6; 2704 lsm6dso32x_sensor_hub_7_t sensor_hub_7; 2705 lsm6dso32x_sensor_hub_8_t sensor_hub_8; 2706 lsm6dso32x_sensor_hub_9_t sensor_hub_9; 2707 lsm6dso32x_sensor_hub_10_t sensor_hub_10; 2708 lsm6dso32x_sensor_hub_11_t sensor_hub_11; 2709 lsm6dso32x_sensor_hub_12_t sensor_hub_12; 2710 lsm6dso32x_sensor_hub_13_t sensor_hub_13; 2711 lsm6dso32x_sensor_hub_14_t sensor_hub_14; 2712 lsm6dso32x_sensor_hub_15_t sensor_hub_15; 2713 lsm6dso32x_sensor_hub_16_t sensor_hub_16; 2714 lsm6dso32x_sensor_hub_17_t sensor_hub_17; 2715 lsm6dso32x_sensor_hub_18_t sensor_hub_18; 2716 lsm6dso32x_master_config_t master_config; 2717 lsm6dso32x_slv0_add_t slv0_add; 2718 lsm6dso32x_slv0_subadd_t slv0_subadd; 2719 lsm6dso32x_slv0_config_t slv0_config; 2720 lsm6dso32x_slv1_add_t slv1_add; 2721 lsm6dso32x_slv1_subadd_t slv1_subadd; 2722 lsm6dso32x_slv1_config_t slv1_config; 2723 lsm6dso32x_slv2_add_t slv2_add; 2724 lsm6dso32x_slv2_subadd_t slv2_subadd; 2725 lsm6dso32x_slv2_config_t slv2_config; 2726 lsm6dso32x_slv3_add_t slv3_add; 2727 lsm6dso32x_slv3_subadd_t slv3_subadd; 2728 lsm6dso32x_slv3_config_t slv3_config; 2729 lsm6dso32x_datawrite_slv0_t datawrite_slv0; 2730 lsm6dso32x_status_master_t status_master; 2731 bitwise_t bitwise; 2732 uint8_t byte; 2733 } lsm6dso32x_reg_t; 2734 2735 /** 2736 * @} 2737 * 2738 */ 2739 2740 #ifndef __weak 2741 #define __weak __attribute__((weak)) 2742 #endif /* __weak */ 2743 2744 /* 2745 * These are the basic platform dependent I/O routines to read 2746 * and write device registers connected on a standard bus. 2747 * The driver keeps offering a default implementation based on function 2748 * pointers to read/write routines for backward compatibility. 2749 * The __weak directive allows the final application to overwrite 2750 * them with a custom implementation. 2751 */ 2752 2753 int32_t lsm6dso32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2754 uint16_t len); 2755 int32_t lsm6dso32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 2756 uint16_t len); 2757 2758 float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb); 2759 float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb); 2760 float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb); 2761 float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb); 2762 float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb); 2763 float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb); 2764 float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb); 2765 float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb); 2766 float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb); 2767 float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb); 2768 float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb); 2769 2770 typedef enum 2771 { 2772 LSM6DSO32X_4g = 0, 2773 LSM6DSO32X_32g = 1, 2774 LSM6DSO32X_8g = 2, 2775 LSM6DSO32X_16g = 3, 2776 } lsm6dso32x_fs_xl_t; 2777 int32_t lsm6dso32x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val); 2778 int32_t lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t *ctx, 2779 lsm6dso32x_fs_xl_t *val); 2780 2781 typedef enum 2782 { 2783 LSM6DSO32X_XL_ODR_OFF = 0, 2784 LSM6DSO32X_XL_ODR_12Hz5 = 1, 2785 LSM6DSO32X_XL_ODR_26Hz = 2, 2786 LSM6DSO32X_XL_ODR_52Hz = 3, 2787 LSM6DSO32X_XL_ODR_104Hz = 4, 2788 LSM6DSO32X_XL_ODR_208Hz = 5, 2789 LSM6DSO32X_XL_ODR_417Hz = 6, 2790 LSM6DSO32X_XL_ODR_833Hz = 7, 2791 LSM6DSO32X_XL_ODR_1667Hz = 8, 2792 LSM6DSO32X_XL_ODR_3333Hz = 9, 2793 LSM6DSO32X_XL_ODR_6667Hz = 10, 2794 LSM6DSO32X_XL_ODR_1Hz6 = 11, /* (low power only) */ 2795 } lsm6dso32x_odr_xl_t; 2796 int32_t lsm6dso32x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val); 2797 int32_t lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t *ctx, 2798 lsm6dso32x_odr_xl_t *val); 2799 2800 typedef enum 2801 { 2802 LSM6DSO32X_250dps = 0, 2803 LSM6DSO32X_125dps = 1, 2804 LSM6DSO32X_500dps = 2, 2805 LSM6DSO32X_1000dps = 4, 2806 LSM6DSO32X_2000dps = 6, 2807 } lsm6dso32x_fs_g_t; 2808 int32_t lsm6dso32x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val); 2809 int32_t lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val); 2810 2811 typedef enum 2812 { 2813 LSM6DSO32X_GY_ODR_OFF = 0, 2814 LSM6DSO32X_GY_ODR_12Hz5 = 1, 2815 LSM6DSO32X_GY_ODR_26Hz = 2, 2816 LSM6DSO32X_GY_ODR_52Hz = 3, 2817 LSM6DSO32X_GY_ODR_104Hz = 4, 2818 LSM6DSO32X_GY_ODR_208Hz = 5, 2819 LSM6DSO32X_GY_ODR_417Hz = 6, 2820 LSM6DSO32X_GY_ODR_833Hz = 7, 2821 LSM6DSO32X_GY_ODR_1667Hz = 8, 2822 LSM6DSO32X_GY_ODR_3333Hz = 9, 2823 LSM6DSO32X_GY_ODR_6667Hz = 10, 2824 } lsm6dso32x_odr_g_t; 2825 int32_t lsm6dso32x_gy_data_rate_set(const stmdev_ctx_t *ctx, 2826 lsm6dso32x_odr_g_t val); 2827 int32_t lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t *ctx, 2828 lsm6dso32x_odr_g_t *val); 2829 2830 int32_t lsm6dso32x_block_data_update_set(const stmdev_ctx_t *ctx, 2831 uint8_t val); 2832 int32_t lsm6dso32x_block_data_update_get(const stmdev_ctx_t *ctx, 2833 uint8_t *val); 2834 2835 typedef enum 2836 { 2837 LSM6DSO32X_LSb_1mg = 0, 2838 LSM6DSO32X_LSb_16mg = 1, 2839 } lsm6dso32x_usr_off_w_t; 2840 int32_t lsm6dso32x_xl_offset_weight_set(const stmdev_ctx_t *ctx, 2841 lsm6dso32x_usr_off_w_t val); 2842 int32_t lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t *ctx, 2843 lsm6dso32x_usr_off_w_t *val); 2844 2845 typedef enum 2846 { 2847 LSM6DSO32X_HIGH_PERFORMANCE_MD = 0, 2848 LSM6DSO32X_LOW_NORMAL_POWER_MD = 1, 2849 LSM6DSO32X_ULTRA_LOW_POWER_MD = 2, 2850 } lsm6dso32x_xl_hm_mode_t; 2851 int32_t lsm6dso32x_xl_power_mode_set(const stmdev_ctx_t *ctx, 2852 lsm6dso32x_xl_hm_mode_t val); 2853 int32_t lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t *ctx, 2854 lsm6dso32x_xl_hm_mode_t *val); 2855 2856 typedef enum 2857 { 2858 LSM6DSO32X_GY_HIGH_PERFORMANCE = 0, 2859 LSM6DSO32X_GY_NORMAL = 1, 2860 } lsm6dso32x_g_hm_mode_t; 2861 int32_t lsm6dso32x_gy_power_mode_set(const stmdev_ctx_t *ctx, 2862 lsm6dso32x_g_hm_mode_t val); 2863 int32_t lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t *ctx, 2864 lsm6dso32x_g_hm_mode_t *val); 2865 2866 int32_t lsm6dso32x_status_reg_get(const stmdev_ctx_t *ctx, 2867 lsm6dso32x_status_reg_t *val); 2868 2869 int32_t lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 2870 uint8_t *val); 2871 2872 int32_t lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 2873 uint8_t *val); 2874 2875 int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 2876 uint8_t *val); 2877 2878 int32_t lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, 2879 uint8_t *buff); 2880 int32_t lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, 2881 uint8_t *buff); 2882 2883 int32_t lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, 2884 uint8_t *buff); 2885 int32_t lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, 2886 uint8_t *buff); 2887 2888 int32_t lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, 2889 uint8_t *buff); 2890 int32_t lsm6dso32x_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, 2891 uint8_t *buff); 2892 2893 int32_t lsm6dso32x_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 2894 int32_t lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2895 2896 int32_t lsm6dso32x_timestamp_rst(const stmdev_ctx_t *ctx); 2897 2898 int32_t lsm6dso32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2899 int32_t lsm6dso32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2900 2901 int32_t lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t *ctx, 2902 uint32_t *val); 2903 2904 typedef enum 2905 { 2906 LSM6DSO32X_NO_ROUND = 0, 2907 LSM6DSO32X_ROUND_XL = 1, 2908 LSM6DSO32X_ROUND_GY = 2, 2909 LSM6DSO32X_ROUND_GY_XL = 3, 2910 } lsm6dso32x_rounding_t; 2911 int32_t lsm6dso32x_rounding_mode_set(const stmdev_ctx_t *ctx, 2912 lsm6dso32x_rounding_t val); 2913 int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx, 2914 lsm6dso32x_rounding_t *val); 2915 2916 int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx, 2917 int16_t *val); 2918 2919 int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, 2920 int16_t *val); 2921 2922 int32_t lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t *ctx, 2923 int16_t *val); 2924 2925 int32_t lsm6dso32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2926 2927 int32_t lsm6dso32x_number_of_steps_get(const stmdev_ctx_t *ctx, 2928 uint16_t *val); 2929 2930 int32_t lsm6dso32x_steps_reset(const stmdev_ctx_t *ctx); 2931 2932 int32_t lsm6dso32x_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2933 2934 int32_t lsm6dso32x_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 2935 int32_t lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 2936 2937 typedef enum 2938 { 2939 LSM6DSO32X_USER_BANK = 0, 2940 LSM6DSO32X_SENSOR_HUB_BANK = 1, 2941 LSM6DSO32X_EMBEDDED_FUNC_BANK = 2, 2942 } lsm6dso32x_reg_access_t; 2943 int32_t lsm6dso32x_mem_bank_set(const stmdev_ctx_t *ctx, 2944 lsm6dso32x_reg_access_t val); 2945 int32_t lsm6dso32x_mem_bank_get(const stmdev_ctx_t *ctx, 2946 lsm6dso32x_reg_access_t *val); 2947 2948 int32_t lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t *ctx, 2949 uint16_t address, 2950 uint8_t *val); 2951 int32_t lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t *ctx, 2952 uint16_t address, 2953 uint8_t *val); 2954 2955 int32_t lsm6dso32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2956 uint8_t *buf, uint8_t len); 2957 int32_t lsm6dso32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2958 uint8_t *val); 2959 2960 typedef enum 2961 { 2962 LSM6DSO32X_DRDY_LATCHED = 0, 2963 LSM6DSO32X_DRDY_PULSED = 1, 2964 } lsm6dso32x_dataready_pulsed_t; 2965 int32_t lsm6dso32x_data_ready_mode_set(const stmdev_ctx_t *ctx, 2966 lsm6dso32x_dataready_pulsed_t val); 2967 int32_t lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t *ctx, 2968 lsm6dso32x_dataready_pulsed_t *val); 2969 2970 int32_t lsm6dso32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2971 2972 int32_t lsm6dso32x_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 2973 int32_t lsm6dso32x_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2974 2975 int32_t lsm6dso32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2976 int32_t lsm6dso32x_auto_increment_get(const stmdev_ctx_t *ctx, 2977 uint8_t *val); 2978 2979 int32_t lsm6dso32x_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 2980 int32_t lsm6dso32x_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 2981 2982 typedef enum 2983 { 2984 LSM6DSO32X_XL_ST_DISABLE = 0, 2985 LSM6DSO32X_XL_ST_POSITIVE = 1, 2986 LSM6DSO32X_XL_ST_NEGATIVE = 2, 2987 } lsm6dso32x_st_xl_t; 2988 int32_t lsm6dso32x_xl_self_test_set(const stmdev_ctx_t *ctx, 2989 lsm6dso32x_st_xl_t val); 2990 int32_t lsm6dso32x_xl_self_test_get(const stmdev_ctx_t *ctx, 2991 lsm6dso32x_st_xl_t *val); 2992 2993 typedef enum 2994 { 2995 LSM6DSO32X_GY_ST_DISABLE = 0, 2996 LSM6DSO32X_GY_ST_POSITIVE = 1, 2997 LSM6DSO32X_GY_ST_NEGATIVE = 3, 2998 } lsm6dso32x_st_g_t; 2999 int32_t lsm6dso32x_gy_self_test_set(const stmdev_ctx_t *ctx, 3000 lsm6dso32x_st_g_t val); 3001 int32_t lsm6dso32x_gy_self_test_get(const stmdev_ctx_t *ctx, 3002 lsm6dso32x_st_g_t *val); 3003 3004 int32_t lsm6dso32x_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 3005 int32_t lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3006 3007 int32_t lsm6dso32x_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 3008 int32_t lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3009 3010 int32_t lsm6dso32x_filter_settling_mask_set(const stmdev_ctx_t *ctx, 3011 uint8_t val); 3012 int32_t lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t *ctx, 3013 uint8_t *val); 3014 3015 typedef enum 3016 { 3017 LSM6DSO32X_ULTRA_LIGHT = 0, 3018 LSM6DSO32X_VERY_LIGHT = 1, 3019 LSM6DSO32X_LIGHT = 2, 3020 LSM6DSO32X_MEDIUM = 3, 3021 LSM6DSO32X_STRONG = 4, 3022 LSM6DSO32X_VERY_STRONG = 5, 3023 LSM6DSO32X_AGGRESSIVE = 6, 3024 LSM6DSO32X_XTREME = 7, 3025 } lsm6dso32x_ftype_t; 3026 int32_t lsm6dso32x_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3027 lsm6dso32x_ftype_t val); 3028 int32_t lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3029 lsm6dso32x_ftype_t *val); 3030 3031 int32_t lsm6dso32x_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 3032 int32_t lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 3033 3034 typedef enum 3035 { 3036 LSM6DSO32X_HP_PATH_DISABLE_ON_OUT = 0x00, 3037 LSM6DSO32X_SLOPE_ODR_DIV_4 = 0x10, 3038 LSM6DSO32X_HP_ODR_DIV_10 = 0x11, 3039 LSM6DSO32X_HP_ODR_DIV_20 = 0x12, 3040 LSM6DSO32X_HP_ODR_DIV_45 = 0x13, 3041 LSM6DSO32X_HP_ODR_DIV_100 = 0x14, 3042 LSM6DSO32X_HP_ODR_DIV_200 = 0x15, 3043 LSM6DSO32X_HP_ODR_DIV_400 = 0x16, 3044 LSM6DSO32X_HP_ODR_DIV_800 = 0x17, 3045 LSM6DSO32X_HP_REF_MD_ODR_DIV_10 = 0x31, 3046 LSM6DSO32X_HP_REF_MD_ODR_DIV_20 = 0x32, 3047 LSM6DSO32X_HP_REF_MD_ODR_DIV_45 = 0x33, 3048 LSM6DSO32X_HP_REF_MD_ODR_DIV_100 = 0x34, 3049 LSM6DSO32X_HP_REF_MD_ODR_DIV_200 = 0x35, 3050 LSM6DSO32X_HP_REF_MD_ODR_DIV_400 = 0x36, 3051 LSM6DSO32X_HP_REF_MD_ODR_DIV_800 = 0x37, 3052 LSM6DSO32X_LP_ODR_DIV_10 = 0x01, 3053 LSM6DSO32X_LP_ODR_DIV_20 = 0x02, 3054 LSM6DSO32X_LP_ODR_DIV_45 = 0x03, 3055 LSM6DSO32X_LP_ODR_DIV_100 = 0x04, 3056 LSM6DSO32X_LP_ODR_DIV_200 = 0x05, 3057 LSM6DSO32X_LP_ODR_DIV_400 = 0x06, 3058 LSM6DSO32X_LP_ODR_DIV_800 = 0x07, 3059 } lsm6dso32x_hp_slope_xl_en_t; 3060 int32_t lsm6dso32x_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 3061 lsm6dso32x_hp_slope_xl_en_t val); 3062 int32_t lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 3063 lsm6dso32x_hp_slope_xl_en_t *val); 3064 3065 int32_t lsm6dso32x_xl_fast_settling_set(const stmdev_ctx_t *ctx, 3066 uint8_t val); 3067 int32_t lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t *ctx, 3068 uint8_t *val); 3069 3070 typedef enum 3071 { 3072 LSM6DSO32X_USE_SLOPE = 0, 3073 LSM6DSO32X_USE_HPF = 1, 3074 } lsm6dso32x_slope_fds_t; 3075 int32_t lsm6dso32x_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 3076 lsm6dso32x_slope_fds_t val); 3077 int32_t lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 3078 lsm6dso32x_slope_fds_t *val); 3079 3080 typedef enum 3081 { 3082 LSM6DSO32X_HP_FILTER_NONE = 0x00, 3083 LSM6DSO32X_HP_FILTER_16mHz = 0x80, 3084 LSM6DSO32X_HP_FILTER_65mHz = 0x81, 3085 LSM6DSO32X_HP_FILTER_260mHz = 0x82, 3086 LSM6DSO32X_HP_FILTER_1Hz04 = 0x83, 3087 } lsm6dso32x_hpm_g_t; 3088 int32_t lsm6dso32x_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 3089 lsm6dso32x_hpm_g_t val); 3090 int32_t lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 3091 lsm6dso32x_hpm_g_t *val); 3092 3093 typedef enum 3094 { 3095 LSM6DSO32X_PULL_UP_DISC = 0, 3096 LSM6DSO32X_PULL_UP_CONNECT = 1, 3097 } lsm6dso32x_sdo_pu_en_t; 3098 int32_t lsm6dso32x_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 3099 lsm6dso32x_sdo_pu_en_t val); 3100 int32_t lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 3101 lsm6dso32x_sdo_pu_en_t *val); 3102 3103 typedef enum 3104 { 3105 LSM6DSO32X_SPI_4_WIRE = 0, 3106 LSM6DSO32X_SPI_3_WIRE = 1, 3107 } lsm6dso32x_sim_t; 3108 int32_t lsm6dso32x_spi_mode_set(const stmdev_ctx_t *ctx, 3109 lsm6dso32x_sim_t val); 3110 int32_t lsm6dso32x_spi_mode_get(const stmdev_ctx_t *ctx, 3111 lsm6dso32x_sim_t *val); 3112 3113 typedef enum 3114 { 3115 LSM6DSO32X_I2C_ENABLE = 0, 3116 LSM6DSO32X_I2C_DISABLE = 1, 3117 } lsm6dso32x_i2c_disable_t; 3118 int32_t lsm6dso32x_i2c_interface_set(const stmdev_ctx_t *ctx, 3119 lsm6dso32x_i2c_disable_t val); 3120 int32_t lsm6dso32x_i2c_interface_get(const stmdev_ctx_t *ctx, 3121 lsm6dso32x_i2c_disable_t *val); 3122 3123 typedef enum 3124 { 3125 LSM6DSO32X_I3C_DISABLE = 0x80, 3126 LSM6DSO32X_I3C_ENABLE_T_50us = 0x00, 3127 LSM6DSO32X_I3C_ENABLE_T_2us = 0x01, 3128 LSM6DSO32X_I3C_ENABLE_T_1ms = 0x02, 3129 LSM6DSO32X_I3C_ENABLE_T_25ms = 0x03, 3130 } lsm6dso32x_i3c_disable_t; 3131 int32_t lsm6dso32x_i3c_disable_set(const stmdev_ctx_t *ctx, 3132 lsm6dso32x_i3c_disable_t val); 3133 int32_t lsm6dso32x_i3c_disable_get(const stmdev_ctx_t *ctx, 3134 lsm6dso32x_i3c_disable_t *val); 3135 3136 typedef enum 3137 { 3138 LSM6DSO32X_PUSH_PULL = 0x00, 3139 LSM6DSO32X_OPEN_DRAIN = 0x01, 3140 LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, 3141 LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, 3142 } lsm6dso32x_pp_od_t; 3143 int32_t lsm6dso32x_pin_mode_set(const stmdev_ctx_t *ctx, 3144 lsm6dso32x_pp_od_t val); 3145 int32_t lsm6dso32x_pin_mode_get(const stmdev_ctx_t *ctx, 3146 lsm6dso32x_pp_od_t *val); 3147 3148 typedef enum 3149 { 3150 LSM6DSO32X_ACTIVE_HIGH = 0, 3151 LSM6DSO32X_ACTIVE_LOW = 1, 3152 } lsm6dso32x_h_lactive_t; 3153 int32_t lsm6dso32x_pin_polarity_set(const stmdev_ctx_t *ctx, 3154 lsm6dso32x_h_lactive_t val); 3155 int32_t lsm6dso32x_pin_polarity_get(const stmdev_ctx_t *ctx, 3156 lsm6dso32x_h_lactive_t *val); 3157 3158 int32_t lsm6dso32x_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 3159 int32_t lsm6dso32x_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3160 3161 typedef enum 3162 { 3163 LSM6DSO32X_ALL_INT_PULSED = 0, 3164 LSM6DSO32X_BASE_LATCHED_EMB_PULSED = 1, 3165 LSM6DSO32X_BASE_PULSED_EMB_LATCHED = 2, 3166 LSM6DSO32X_ALL_INT_LATCHED = 3, 3167 } lsm6dso32x_lir_t; 3168 int32_t lsm6dso32x_int_notification_set(const stmdev_ctx_t *ctx, 3169 lsm6dso32x_lir_t val); 3170 int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx, 3171 lsm6dso32x_lir_t *val); 3172 3173 typedef enum 3174 { 3175 LSM6DSO32X_LSb_FS_DIV_64 = 0, 3176 LSM6DSO32X_LSb_FS_DIV_256 = 1, 3177 } lsm6dso32x_wake_ths_w_t; 3178 int32_t lsm6dso32x_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3179 lsm6dso32x_wake_ths_w_t val); 3180 int32_t lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3181 lsm6dso32x_wake_ths_w_t *val); 3182 3183 int32_t lsm6dso32x_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3184 int32_t lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t *ctx, 3185 uint8_t *val); 3186 3187 int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3188 uint8_t val); 3189 int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3190 uint8_t *val); 3191 3192 int32_t lsm6dso32x_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3193 int32_t lsm6dso32x_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3194 3195 int32_t lsm6dso32x_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3196 int32_t lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3197 3198 typedef enum 3199 { 3200 LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT = 0, 3201 LSM6DSO32X_DRIVE_SLEEP_STATUS = 1, 3202 } lsm6dso32x_sleep_status_on_int_t; 3203 int32_t lsm6dso32x_act_pin_notification_set(const stmdev_ctx_t *ctx, 3204 lsm6dso32x_sleep_status_on_int_t val); 3205 int32_t lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t *ctx, 3206 lsm6dso32x_sleep_status_on_int_t *val); 3207 3208 typedef enum 3209 { 3210 LSM6DSO32X_XL_AND_GY_NOT_AFFECTED = 0, 3211 LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED = 1, 3212 LSM6DSO32X_XL_12Hz5_GY_SLEEP = 2, 3213 LSM6DSO32X_XL_12Hz5_GY_PD = 3, 3214 } lsm6dso32x_inact_en_t; 3215 int32_t lsm6dso32x_act_mode_set(const stmdev_ctx_t *ctx, 3216 lsm6dso32x_inact_en_t val); 3217 int32_t lsm6dso32x_act_mode_get(const stmdev_ctx_t *ctx, 3218 lsm6dso32x_inact_en_t *val); 3219 3220 int32_t lsm6dso32x_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3221 int32_t lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3222 3223 int32_t lsm6dso32x_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 3224 uint8_t val); 3225 int32_t lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 3226 uint8_t *val); 3227 3228 int32_t lsm6dso32x_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 3229 uint8_t val); 3230 int32_t lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 3231 uint8_t *val); 3232 3233 int32_t lsm6dso32x_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 3234 uint8_t val); 3235 int32_t lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 3236 uint8_t *val); 3237 3238 int32_t lsm6dso32x_tap_threshold_x_set(const stmdev_ctx_t *ctx, 3239 uint8_t val); 3240 int32_t lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t *ctx, 3241 uint8_t *val); 3242 3243 typedef enum 3244 { 3245 LSM6DSO32X_XYZ = 0, 3246 LSM6DSO32X_YXZ = 1, 3247 LSM6DSO32X_XZY = 2, 3248 LSM6DSO32X_ZYX = 3, 3249 LSM6DSO32X_YZX = 5, 3250 LSM6DSO32X_ZXY = 6, 3251 } lsm6dso32x_tap_priority_t; 3252 int32_t lsm6dso32x_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3253 lsm6dso32x_tap_priority_t val); 3254 int32_t lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3255 lsm6dso32x_tap_priority_t *val); 3256 3257 int32_t lsm6dso32x_tap_threshold_y_set(const stmdev_ctx_t *ctx, 3258 uint8_t val); 3259 int32_t lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t *ctx, 3260 uint8_t *val); 3261 3262 int32_t lsm6dso32x_tap_threshold_z_set(const stmdev_ctx_t *ctx, 3263 uint8_t val); 3264 int32_t lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t *ctx, 3265 uint8_t *val); 3266 3267 int32_t lsm6dso32x_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 3268 int32_t lsm6dso32x_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 3269 3270 int32_t lsm6dso32x_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 3271 int32_t lsm6dso32x_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 3272 3273 int32_t lsm6dso32x_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3274 int32_t lsm6dso32x_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3275 3276 typedef enum 3277 { 3278 LSM6DSO32X_ONLY_SINGLE = 0, 3279 LSM6DSO32X_BOTH_SINGLE_DOUBLE = 1, 3280 } lsm6dso32x_single_double_tap_t; 3281 int32_t lsm6dso32x_tap_mode_set(const stmdev_ctx_t *ctx, 3282 lsm6dso32x_single_double_tap_t val); 3283 int32_t lsm6dso32x_tap_mode_get(const stmdev_ctx_t *ctx, 3284 lsm6dso32x_single_double_tap_t *val); 3285 3286 typedef enum 3287 { 3288 LSM6DSO32X_DEG_80 = 0, 3289 LSM6DSO32X_DEG_70 = 1, 3290 LSM6DSO32X_DEG_60 = 2, 3291 LSM6DSO32X_DEG_50 = 3, 3292 } lsm6dso32x_sixd_ths_t; 3293 int32_t lsm6dso32x_6d_threshold_set(const stmdev_ctx_t *ctx, 3294 lsm6dso32x_sixd_ths_t val); 3295 int32_t lsm6dso32x_6d_threshold_get(const stmdev_ctx_t *ctx, 3296 lsm6dso32x_sixd_ths_t *val); 3297 3298 int32_t lsm6dso32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3299 int32_t lsm6dso32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3300 3301 typedef enum 3302 { 3303 LSM6DSO32X_FF_TSH_312mg = 0, 3304 LSM6DSO32X_FF_TSH_438mg = 1, 3305 LSM6DSO32X_FF_TSH_500mg = 2, 3306 } lsm6dso32x_ff_ths_t; 3307 int32_t lsm6dso32x_ff_threshold_set(const stmdev_ctx_t *ctx, 3308 lsm6dso32x_ff_ths_t val); 3309 int32_t lsm6dso32x_ff_threshold_get(const stmdev_ctx_t *ctx, 3310 lsm6dso32x_ff_ths_t *val); 3311 3312 int32_t lsm6dso32x_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3313 int32_t lsm6dso32x_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3314 3315 int32_t lsm6dso32x_fifo_watermark_set(const stmdev_ctx_t *ctx, 3316 uint16_t val); 3317 int32_t lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t *ctx, 3318 uint16_t *val); 3319 3320 int32_t lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t *ctx, 3321 uint8_t val); 3322 int32_t lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t *ctx, 3323 uint8_t *val); 3324 3325 typedef enum 3326 { 3327 LSM6DSO32X_CMP_DISABLE = 0x00, 3328 LSM6DSO32X_CMP_ALWAYS = 0x04, 3329 LSM6DSO32X_CMP_8_TO_1 = 0x05, 3330 LSM6DSO32X_CMP_16_TO_1 = 0x06, 3331 LSM6DSO32X_CMP_32_TO_1 = 0x07, 3332 } lsm6dso32x_uncoptr_rate_t; 3333 int32_t lsm6dso32x_compression_algo_set(const stmdev_ctx_t *ctx, 3334 lsm6dso32x_uncoptr_rate_t val); 3335 int32_t lsm6dso32x_compression_algo_get(const stmdev_ctx_t *ctx, 3336 lsm6dso32x_uncoptr_rate_t *val); 3337 3338 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3339 uint8_t val); 3340 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3341 uint8_t *val); 3342 3343 int32_t lsm6dso32x_compression_algo_real_time_set(const stmdev_ctx_t *ctx, 3344 uint8_t val); 3345 int32_t lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t *ctx, 3346 uint8_t *val); 3347 3348 int32_t lsm6dso32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 3349 uint8_t val); 3350 int32_t lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 3351 uint8_t *val); 3352 3353 typedef enum 3354 { 3355 LSM6DSO32X_XL_NOT_BATCHED = 0, 3356 LSM6DSO32X_XL_BATCHED_AT_12Hz5 = 1, 3357 LSM6DSO32X_XL_BATCHED_AT_26Hz = 2, 3358 LSM6DSO32X_XL_BATCHED_AT_52Hz = 3, 3359 LSM6DSO32X_XL_BATCHED_AT_104Hz = 4, 3360 LSM6DSO32X_XL_BATCHED_AT_208Hz = 5, 3361 LSM6DSO32X_XL_BATCHED_AT_417Hz = 6, 3362 LSM6DSO32X_XL_BATCHED_AT_833Hz = 7, 3363 LSM6DSO32X_XL_BATCHED_AT_1667Hz = 8, 3364 LSM6DSO32X_XL_BATCHED_AT_3333Hz = 9, 3365 LSM6DSO32X_XL_BATCHED_AT_6667Hz = 10, 3366 LSM6DSO32X_XL_BATCHED_AT_6Hz5 = 11, 3367 } lsm6dso32x_bdr_xl_t; 3368 int32_t lsm6dso32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3369 lsm6dso32x_bdr_xl_t val); 3370 int32_t lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3371 lsm6dso32x_bdr_xl_t *val); 3372 3373 typedef enum 3374 { 3375 LSM6DSO32X_GY_NOT_BATCHED = 0, 3376 LSM6DSO32X_GY_BATCHED_AT_12Hz5 = 1, 3377 LSM6DSO32X_GY_BATCHED_AT_26Hz = 2, 3378 LSM6DSO32X_GY_BATCHED_AT_52Hz = 3, 3379 LSM6DSO32X_GY_BATCHED_AT_104Hz = 4, 3380 LSM6DSO32X_GY_BATCHED_AT_208Hz = 5, 3381 LSM6DSO32X_GY_BATCHED_AT_417Hz = 6, 3382 LSM6DSO32X_GY_BATCHED_AT_833Hz = 7, 3383 LSM6DSO32X_GY_BATCHED_AT_1667Hz = 8, 3384 LSM6DSO32X_GY_BATCHED_AT_3333Hz = 9, 3385 LSM6DSO32X_GY_BATCHED_AT_6667Hz = 10, 3386 LSM6DSO32X_GY_BATCHED_AT_6Hz5 = 11, 3387 } lsm6dso32x_bdr_gy_t; 3388 int32_t lsm6dso32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3389 lsm6dso32x_bdr_gy_t val); 3390 int32_t lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3391 lsm6dso32x_bdr_gy_t *val); 3392 3393 typedef enum 3394 { 3395 LSM6DSO32X_BYPASS_MODE = 0, 3396 LSM6DSO32X_FIFO_MODE = 1, 3397 LSM6DSO32X_STREAM_TO_FIFO_MODE = 3, 3398 LSM6DSO32X_BYPASS_TO_STREAM_MODE = 4, 3399 LSM6DSO32X_STREAM_MODE = 6, 3400 LSM6DSO32X_BYPASS_TO_FIFO_MODE = 7, 3401 } lsm6dso32x_fifo_mode_t; 3402 int32_t lsm6dso32x_fifo_mode_set(const stmdev_ctx_t *ctx, 3403 lsm6dso32x_fifo_mode_t val); 3404 int32_t lsm6dso32x_fifo_mode_get(const stmdev_ctx_t *ctx, 3405 lsm6dso32x_fifo_mode_t *val); 3406 3407 typedef enum 3408 { 3409 LSM6DSO32X_TEMP_NOT_BATCHED = 0, 3410 LSM6DSO32X_TEMP_BATCHED_AT_1Hz6 = 1, 3411 LSM6DSO32X_TEMP_BATCHED_AT_12Hz5 = 2, 3412 LSM6DSO32X_TEMP_BATCHED_AT_52Hz = 3, 3413 } lsm6dso32x_odr_t_batch_t; 3414 int32_t lsm6dso32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3415 lsm6dso32x_odr_t_batch_t val); 3416 int32_t lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3417 lsm6dso32x_odr_t_batch_t *val); 3418 3419 typedef enum 3420 { 3421 LSM6DSO32X_NO_DECIMATION = 0, 3422 LSM6DSO32X_DEC_1 = 1, 3423 LSM6DSO32X_DEC_8 = 2, 3424 LSM6DSO32X_DEC_32 = 3, 3425 } lsm6dso32x_odr_ts_batch_t; 3426 int32_t lsm6dso32x_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3427 lsm6dso32x_odr_ts_batch_t val); 3428 int32_t lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3429 lsm6dso32x_odr_ts_batch_t *val); 3430 3431 typedef enum 3432 { 3433 LSM6DSO32X_XL_BATCH_EVENT = 0, 3434 LSM6DSO32X_GYRO_BATCH_EVENT = 1, 3435 } lsm6dso32x_trig_counter_bdr_t; 3436 3437 typedef enum 3438 { 3439 LSM6DSO32X_GYRO_NC_TAG = 1, 3440 LSM6DSO32X_XL_NC_TAG, 3441 LSM6DSO32X_TEMPERATURE_TAG, 3442 LSM6DSO32X_TIMESTAMP_TAG, 3443 LSM6DSO32X_CFG_CHANGE_TAG, 3444 LSM6DSO32X_XL_NC_T_2_TAG, 3445 LSM6DSO32X_XL_NC_T_1_TAG, 3446 LSM6DSO32X_XL_2XC_TAG, 3447 LSM6DSO32X_XL_3XC_TAG, 3448 LSM6DSO32X_GYRO_NC_T_2_TAG, 3449 LSM6DSO32X_GYRO_NC_T_1_TAG, 3450 LSM6DSO32X_GYRO_2XC_TAG, 3451 LSM6DSO32X_GYRO_3XC_TAG, 3452 LSM6DSO32X_SENSORHUB_SLAVE0_TAG, 3453 LSM6DSO32X_SENSORHUB_SLAVE1_TAG, 3454 LSM6DSO32X_SENSORHUB_SLAVE2_TAG, 3455 LSM6DSO32X_SENSORHUB_SLAVE3_TAG, 3456 LSM6DSO32X_STEP_CPUNTER_TAG, 3457 LSM6DSO32X_GAME_ROTATION_TAG, 3458 LSM6DSO32X_GEOMAG_ROTATION_TAG, 3459 LSM6DSO32X_ROTATION_TAG, 3460 LSM6DSO32X_SENSORHUB_NACK_TAG = 0x19, 3461 } lsm6dso32x_fifo_tag_t; 3462 int32_t lsm6dso32x_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3463 lsm6dso32x_trig_counter_bdr_t val); 3464 int32_t lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3465 lsm6dso32x_trig_counter_bdr_t *val); 3466 3467 int32_t lsm6dso32x_rst_batch_counter_set(const stmdev_ctx_t *ctx, 3468 uint8_t val); 3469 int32_t lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t *ctx, 3470 uint8_t *val); 3471 3472 int32_t lsm6dso32x_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3473 uint16_t val); 3474 int32_t lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3475 uint16_t *val); 3476 3477 int32_t lsm6dso32x_fifo_data_level_get(const stmdev_ctx_t *ctx, 3478 uint16_t *val); 3479 3480 int32_t lsm6dso32x_fifo_status_get(const stmdev_ctx_t *ctx, 3481 lsm6dso32x_fifo_status2_t *val); 3482 3483 int32_t lsm6dso32x_fifo_full_flag_get(const stmdev_ctx_t *ctx, 3484 uint8_t *val); 3485 3486 int32_t lsm6dso32x_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3487 3488 int32_t lsm6dso32x_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3489 3490 int32_t lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3491 lsm6dso32x_fifo_tag_t *val); 3492 3493 int32_t lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, 3494 uint8_t val); 3495 int32_t lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, 3496 uint8_t *val); 3497 3498 int32_t lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, 3499 uint8_t val); 3500 int32_t lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, 3501 uint8_t *val); 3502 3503 int32_t lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, 3504 uint8_t val); 3505 int32_t lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, 3506 uint8_t *val); 3507 3508 int32_t lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, 3509 uint8_t val); 3510 int32_t lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, 3511 uint8_t *val); 3512 3513 int32_t lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, 3514 uint8_t val); 3515 int32_t lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, 3516 uint8_t *val); 3517 3518 typedef enum 3519 { 3520 LSM6DSO32X_DEN_DISABLE = 0, 3521 LSM6DSO32X_LEVEL_FIFO = 6, 3522 LSM6DSO32X_LEVEL_LETCHED = 3, 3523 LSM6DSO32X_LEVEL_TRIGGER = 2, 3524 LSM6DSO32X_EDGE_TRIGGER = 4, 3525 } lsm6dso32x_den_mode_t; 3526 int32_t lsm6dso32x_den_mode_set(const stmdev_ctx_t *ctx, 3527 lsm6dso32x_den_mode_t val); 3528 int32_t lsm6dso32x_den_mode_get(const stmdev_ctx_t *ctx, 3529 lsm6dso32x_den_mode_t *val); 3530 3531 typedef enum 3532 { 3533 LSM6DSO32X_DEN_ACT_LOW = 0, 3534 LSM6DSO32X_DEN_ACT_HIGH = 1, 3535 } lsm6dso32x_den_lh_t; 3536 int32_t lsm6dso32x_den_polarity_set(const stmdev_ctx_t *ctx, 3537 lsm6dso32x_den_lh_t val); 3538 int32_t lsm6dso32x_den_polarity_get(const stmdev_ctx_t *ctx, 3539 lsm6dso32x_den_lh_t *val); 3540 3541 typedef enum 3542 { 3543 LSM6DSO32X_STAMP_IN_GY_DATA = 0, 3544 LSM6DSO32X_STAMP_IN_XL_DATA = 1, 3545 LSM6DSO32X_STAMP_IN_GY_XL_DATA = 2, 3546 } lsm6dso32x_den_xl_g_t; 3547 int32_t lsm6dso32x_den_enable_set(const stmdev_ctx_t *ctx, 3548 lsm6dso32x_den_xl_g_t val); 3549 int32_t lsm6dso32x_den_enable_get(const stmdev_ctx_t *ctx, 3550 lsm6dso32x_den_xl_g_t *val); 3551 3552 int32_t lsm6dso32x_den_mark_axis_x_set(const stmdev_ctx_t *ctx, 3553 uint8_t val); 3554 int32_t lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 3555 uint8_t *val); 3556 3557 int32_t lsm6dso32x_den_mark_axis_y_set(const stmdev_ctx_t *ctx, 3558 uint8_t val); 3559 int32_t lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 3560 uint8_t *val); 3561 3562 int32_t lsm6dso32x_den_mark_axis_z_set(const stmdev_ctx_t *ctx, 3563 uint8_t val); 3564 int32_t lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 3565 uint8_t *val); 3566 3567 typedef enum 3568 { 3569 LSM6DSO32X_PEDO_BASE_MODE = 0x00, 3570 LSM6DSO32X_FALSE_STEP_REJ = 0x10, 3571 LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE = 0x30, 3572 } lsm6dso32x_pedo_md_t; 3573 int32_t lsm6dso32x_pedo_sens_set(const stmdev_ctx_t *ctx, 3574 lsm6dso32x_pedo_md_t val); 3575 int32_t lsm6dso32x_pedo_sens_get(const stmdev_ctx_t *ctx, 3576 lsm6dso32x_pedo_md_t *val); 3577 3578 int32_t lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t *ctx, 3579 uint8_t *val); 3580 3581 int32_t lsm6dso32x_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 3582 uint8_t *buff); 3583 int32_t lsm6dso32x_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 3584 uint8_t *buff); 3585 3586 int32_t lsm6dso32x_pedo_steps_period_set(const stmdev_ctx_t *ctx, 3587 uint16_t val); 3588 int32_t lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t *ctx, 3589 uint16_t *val); 3590 3591 int32_t lsm6dso32x_pedo_adv_detection_set(const stmdev_ctx_t *ctx, 3592 uint8_t val); 3593 int32_t lsm6dso32x_pedo_adv_detection_get(const stmdev_ctx_t *ctx, 3594 uint8_t *val); 3595 3596 int32_t lsm6dso32x_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, 3597 uint8_t val); 3598 int32_t lsm6dso32x_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, 3599 uint8_t *val); 3600 3601 typedef enum 3602 { 3603 LSM6DSO32X_EVERY_STEP = 0, 3604 LSM6DSO32X_COUNT_OVERFLOW = 1, 3605 } lsm6dso32x_carry_count_en_t; 3606 int32_t lsm6dso32x_pedo_int_mode_set(const stmdev_ctx_t *ctx, 3607 lsm6dso32x_carry_count_en_t val); 3608 int32_t lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t *ctx, 3609 lsm6dso32x_carry_count_en_t *val); 3610 3611 int32_t lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, 3612 uint8_t *val); 3613 3614 int32_t lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3615 uint8_t *val); 3616 3617 int32_t lsm6dso32x_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, 3618 uint16_t val); 3619 int32_t lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, 3620 uint16_t *val); 3621 3622 int32_t lsm6dso32x_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, 3623 uint16_t val); 3624 int32_t lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, 3625 uint16_t *val); 3626 3627 int32_t lsm6dso32x_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 3628 int32_t lsm6dso32x_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 3629 3630 int32_t lsm6dso32x_mag_soft_iron_set(const stmdev_ctx_t *ctx, 3631 uint16_t *val); 3632 int32_t lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t *ctx, 3633 uint16_t *val); 3634 3635 typedef enum 3636 { 3637 LSM6DSO32X_Z_EQ_Y = 0, 3638 LSM6DSO32X_Z_EQ_MIN_Y = 1, 3639 LSM6DSO32X_Z_EQ_X = 2, 3640 LSM6DSO32X_Z_EQ_MIN_X = 3, 3641 LSM6DSO32X_Z_EQ_MIN_Z = 4, 3642 LSM6DSO32X_Z_EQ_Z = 5, 3643 } lsm6dso32x_mag_z_axis_t; 3644 int32_t lsm6dso32x_mag_z_orient_set(const stmdev_ctx_t *ctx, 3645 lsm6dso32x_mag_z_axis_t val); 3646 int32_t lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t *ctx, 3647 lsm6dso32x_mag_z_axis_t *val); 3648 3649 typedef enum 3650 { 3651 LSM6DSO32X_Y_EQ_Y = 0, 3652 LSM6DSO32X_Y_EQ_MIN_Y = 1, 3653 LSM6DSO32X_Y_EQ_X = 2, 3654 LSM6DSO32X_Y_EQ_MIN_X = 3, 3655 LSM6DSO32X_Y_EQ_MIN_Z = 4, 3656 LSM6DSO32X_Y_EQ_Z = 5, 3657 } lsm6dso32x_mag_y_axis_t; 3658 int32_t lsm6dso32x_mag_y_orient_set(const stmdev_ctx_t *ctx, 3659 lsm6dso32x_mag_y_axis_t val); 3660 int32_t lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t *ctx, 3661 lsm6dso32x_mag_y_axis_t *val); 3662 3663 typedef enum 3664 { 3665 LSM6DSO32X_X_EQ_Y = 0, 3666 LSM6DSO32X_X_EQ_MIN_Y = 1, 3667 LSM6DSO32X_X_EQ_X = 2, 3668 LSM6DSO32X_X_EQ_MIN_X = 3, 3669 LSM6DSO32X_X_EQ_MIN_Z = 4, 3670 LSM6DSO32X_X_EQ_Z = 5, 3671 } lsm6dso32x_mag_x_axis_t; 3672 int32_t lsm6dso32x_mag_x_orient_set(const stmdev_ctx_t *ctx, 3673 lsm6dso32x_mag_x_axis_t val); 3674 int32_t lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t *ctx, 3675 lsm6dso32x_mag_x_axis_t *val); 3676 3677 int32_t lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 3678 uint8_t *val); 3679 3680 typedef struct 3681 { 3682 lsm6dso32x_fsm_enable_a_t fsm_enable_a; 3683 lsm6dso32x_fsm_enable_b_t fsm_enable_b; 3684 } lsm6dso32x_emb_fsm_enable_t; 3685 int32_t lsm6dso32x_fsm_enable_set(const stmdev_ctx_t *ctx, 3686 lsm6dso32x_emb_fsm_enable_t *val); 3687 int32_t lsm6dso32x_fsm_enable_get(const stmdev_ctx_t *ctx, 3688 lsm6dso32x_emb_fsm_enable_t *val); 3689 3690 int32_t lsm6dso32x_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3691 int32_t lsm6dso32x_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3692 3693 typedef enum 3694 { 3695 LSM6DSO32X_LC_NORMAL = 0, 3696 LSM6DSO32X_LC_CLEAR = 1, 3697 LSM6DSO32X_LC_CLEAR_DONE = 2, 3698 } lsm6dso32x_fsm_lc_clr_t; 3699 int32_t lsm6dso32x_long_clr_set(const stmdev_ctx_t *ctx, 3700 lsm6dso32x_fsm_lc_clr_t val); 3701 int32_t lsm6dso32x_long_clr_get(const stmdev_ctx_t *ctx, 3702 lsm6dso32x_fsm_lc_clr_t *val); 3703 3704 typedef struct 3705 { 3706 lsm6dso32x_fsm_outs1_t fsm_outs1; 3707 lsm6dso32x_fsm_outs2_t fsm_outs2; 3708 lsm6dso32x_fsm_outs3_t fsm_outs3; 3709 lsm6dso32x_fsm_outs4_t fsm_outs4; 3710 lsm6dso32x_fsm_outs5_t fsm_outs5; 3711 lsm6dso32x_fsm_outs6_t fsm_outs6; 3712 lsm6dso32x_fsm_outs7_t fsm_outs7; 3713 lsm6dso32x_fsm_outs8_t fsm_outs8; 3714 lsm6dso32x_fsm_outs1_t fsm_outs9; 3715 lsm6dso32x_fsm_outs2_t fsm_outs10; 3716 lsm6dso32x_fsm_outs3_t fsm_outs11; 3717 lsm6dso32x_fsm_outs4_t fsm_outs12; 3718 lsm6dso32x_fsm_outs5_t fsm_outs13; 3719 lsm6dso32x_fsm_outs6_t fsm_outs14; 3720 lsm6dso32x_fsm_outs7_t fsm_outs15; 3721 lsm6dso32x_fsm_outs8_t fsm_outs16; 3722 } lsm6dso32x_fsm_out_t; 3723 int32_t lsm6dso32x_fsm_out_get(const stmdev_ctx_t *ctx, 3724 lsm6dso32x_fsm_out_t *val); 3725 3726 typedef enum 3727 { 3728 LSM6DSO32X_ODR_FSM_12Hz5 = 0, 3729 LSM6DSO32X_ODR_FSM_26Hz = 1, 3730 LSM6DSO32X_ODR_FSM_52Hz = 2, 3731 LSM6DSO32X_ODR_FSM_104Hz = 3, 3732 } lsm6dso32x_fsm_odr_t; 3733 int32_t lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, 3734 lsm6dso32x_fsm_odr_t val); 3735 int32_t lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, 3736 lsm6dso32x_fsm_odr_t *val); 3737 3738 int32_t lsm6dso32x_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 3739 int32_t lsm6dso32x_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 3740 3741 int32_t lsm6dso32x_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 3742 uint16_t val); 3743 int32_t lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 3744 uint16_t *val); 3745 3746 int32_t lsm6dso32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 3747 uint8_t val); 3748 int32_t lsm6dso32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 3749 uint8_t *val); 3750 3751 int32_t lsm6dso32x_fsm_start_address_set(const stmdev_ctx_t *ctx, 3752 uint16_t val); 3753 int32_t lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t *ctx, 3754 uint16_t *val); 3755 3756 int32_t lsm6dso32x_mlc_status_get(const stmdev_ctx_t *ctx, 3757 lsm6dso32x_mlc_status_mainpage_t *val); 3758 3759 typedef enum 3760 { 3761 LSM6DSO32X_ODR_PRGS_12Hz5 = 0, 3762 LSM6DSO32X_ODR_PRGS_26Hz = 1, 3763 LSM6DSO32X_ODR_PRGS_52Hz = 2, 3764 LSM6DSO32X_ODR_PRGS_104Hz = 3, 3765 } lsm6dso32x_mlc_odr_t; 3766 int32_t lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, 3767 lsm6dso32x_mlc_odr_t val); 3768 int32_t lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, 3769 lsm6dso32x_mlc_odr_t *val); 3770 3771 typedef struct 3772 { 3773 lsm6dso32x_sensor_hub_1_t sh_byte_1; 3774 lsm6dso32x_sensor_hub_2_t sh_byte_2; 3775 lsm6dso32x_sensor_hub_3_t sh_byte_3; 3776 lsm6dso32x_sensor_hub_4_t sh_byte_4; 3777 lsm6dso32x_sensor_hub_5_t sh_byte_5; 3778 lsm6dso32x_sensor_hub_6_t sh_byte_6; 3779 lsm6dso32x_sensor_hub_7_t sh_byte_7; 3780 lsm6dso32x_sensor_hub_8_t sh_byte_8; 3781 lsm6dso32x_sensor_hub_9_t sh_byte_9; 3782 lsm6dso32x_sensor_hub_10_t sh_byte_10; 3783 lsm6dso32x_sensor_hub_11_t sh_byte_11; 3784 lsm6dso32x_sensor_hub_12_t sh_byte_12; 3785 lsm6dso32x_sensor_hub_13_t sh_byte_13; 3786 lsm6dso32x_sensor_hub_14_t sh_byte_14; 3787 lsm6dso32x_sensor_hub_15_t sh_byte_15; 3788 lsm6dso32x_sensor_hub_16_t sh_byte_16; 3789 lsm6dso32x_sensor_hub_17_t sh_byte_17; 3790 lsm6dso32x_sensor_hub_18_t sh_byte_18; 3791 } lsm6dso32x_emb_sh_read_t; 3792 int32_t lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 3793 lsm6dso32x_emb_sh_read_t *val, 3794 uint8_t len); 3795 3796 typedef enum 3797 { 3798 LSM6DSO32X_SLV_0 = 0, 3799 LSM6DSO32X_SLV_0_1 = 1, 3800 LSM6DSO32X_SLV_0_1_2 = 2, 3801 LSM6DSO32X_SLV_0_1_2_3 = 3, 3802 } lsm6dso32x_aux_sens_on_t; 3803 int32_t lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, 3804 lsm6dso32x_aux_sens_on_t val); 3805 int32_t lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, 3806 lsm6dso32x_aux_sens_on_t *val); 3807 3808 int32_t lsm6dso32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 3809 int32_t lsm6dso32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 3810 3811 typedef enum 3812 { 3813 LSM6DSO32X_EXT_PULL_UP = 0, 3814 LSM6DSO32X_INTERNAL_PULL_UP = 1, 3815 } lsm6dso32x_shub_pu_en_t; 3816 int32_t lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t *ctx, 3817 lsm6dso32x_shub_pu_en_t val); 3818 int32_t lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t *ctx, 3819 lsm6dso32x_shub_pu_en_t *val); 3820 3821 int32_t lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t *ctx, 3822 uint8_t val); 3823 int32_t lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t *ctx, 3824 uint8_t *val); 3825 3826 typedef enum 3827 { 3828 LSM6DSO32X_EXT_ON_INT2_PIN = 1, 3829 LSM6DSO32X_XL_GY_DRDY = 0, 3830 } lsm6dso32x_start_config_t; 3831 int32_t lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 3832 lsm6dso32x_start_config_t val); 3833 int32_t lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 3834 lsm6dso32x_start_config_t *val); 3835 3836 typedef enum 3837 { 3838 LSM6DSO32X_EACH_SH_CYCLE = 0, 3839 LSM6DSO32X_ONLY_FIRST_CYCLE = 1, 3840 } lsm6dso32x_write_once_t; 3841 int32_t lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t *ctx, 3842 lsm6dso32x_write_once_t val); 3843 int32_t lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t *ctx, 3844 lsm6dso32x_write_once_t *val); 3845 3846 int32_t lsm6dso32x_sh_reset_set(const stmdev_ctx_t *ctx); 3847 int32_t lsm6dso32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3848 3849 typedef enum 3850 { 3851 LSM6DSO32X_SH_ODR_104Hz = 0, 3852 LSM6DSO32X_SH_ODR_52Hz = 1, 3853 LSM6DSO32X_SH_ODR_26Hz = 2, 3854 LSM6DSO32X_SH_ODR_13Hz = 3, 3855 } lsm6dso32x_shub_odr_t; 3856 int32_t lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t *ctx, 3857 lsm6dso32x_shub_odr_t val); 3858 int32_t lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t *ctx, 3859 lsm6dso32x_shub_odr_t *val); 3860 3861 typedef struct 3862 { 3863 uint8_t slv0_add; 3864 uint8_t slv0_subadd; 3865 uint8_t slv0_data; 3866 } lsm6dso32x_sh_cfg_write_t; 3867 int32_t lsm6dso32x_sh_cfg_write(const stmdev_ctx_t *ctx, 3868 lsm6dso32x_sh_cfg_write_t *val); 3869 3870 typedef struct 3871 { 3872 uint8_t slv_add; 3873 uint8_t slv_subadd; 3874 uint8_t slv_len; 3875 } lsm6dso32x_sh_cfg_read_t; 3876 int32_t lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 3877 lsm6dso32x_sh_cfg_read_t *val); 3878 int32_t lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 3879 lsm6dso32x_sh_cfg_read_t *val); 3880 int32_t lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 3881 lsm6dso32x_sh_cfg_read_t *val); 3882 int32_t lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 3883 lsm6dso32x_sh_cfg_read_t *val); 3884 3885 int32_t lsm6dso32x_sh_status_get(const stmdev_ctx_t *ctx, 3886 lsm6dso32x_status_master_t *val); 3887 typedef struct 3888 { 3889 uint8_t ui; 3890 uint8_t aux; 3891 } lsm6dso32x_id_t; 3892 int32_t lsm6dso32x_id_get(const stmdev_ctx_t *ctx, 3893 lsm6dso32x_id_t *val); 3894 3895 typedef enum 3896 { 3897 LSM6DSO32X_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 3898 LSM6DSO32X_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 3899 LSM6DSO32X_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 3900 LSM6DSO32X_I2C = 0x04, /* Only I2C */ 3901 LSM6DSO32X_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 3902 LSM6DSO32X_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 3903 LSM6DSO32X_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 3904 LSM6DSO32X_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 3905 } lsm6dso32x_ui_bus_md_t; 3906 3907 typedef enum 3908 { 3909 LSM6DSO32X_SPI_4W_AUX = 0x00, 3910 LSM6DSO32X_SPI_3W_AUX = 0x01, 3911 } lsm6dso32x_aux_bus_md_t; 3912 3913 typedef struct 3914 { 3915 lsm6dso32x_ui_bus_md_t ui_bus_md; 3916 lsm6dso32x_aux_bus_md_t aux_bus_md; 3917 } lsm6dso32x_bus_mode_t; 3918 int32_t lsm6dso32x_bus_mode_set(const stmdev_ctx_t *ctx, 3919 lsm6dso32x_bus_mode_t val); 3920 int32_t lsm6dso32x_bus_mode_get(const stmdev_ctx_t *ctx, 3921 lsm6dso32x_bus_mode_t *val); 3922 3923 typedef enum 3924 { 3925 LSM6DSO32X_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 3926 LSM6DSO32X_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 3927 LSM6DSO32X_RESET = 0x02, /* Reset configuration registers */ 3928 LSM6DSO32X_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 3929 LSM6DSO32X_FSM = 0x08, /* Finite State Machine initialization request */ 3930 LSM6DSO32X_MLC = 0x10, /* Machine Learning Core initialization request */ 3931 LSM6DSO32X_PEDO = 0x20, /* Pedometer algo initialization request. */ 3932 LSM6DSO32X_TILT = 0x40, /* Tilt algo initialization request */ 3933 LSM6DSO32X_SMOTION = 0x80, /* Significant Motion initialization request */ 3934 } lsm6dso32x_init_t; 3935 int32_t lsm6dso32x_init_set(const stmdev_ctx_t *ctx, lsm6dso32x_init_t val); 3936 3937 typedef struct 3938 { 3939 uint8_t sw_reset : 1; /* Restoring configuration registers */ 3940 uint8_t boot : 1; /* Restoring calibration parameters */ 3941 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 3942 uint8_t drdy_g : 1; /* Gyroscope data ready */ 3943 uint8_t drdy_temp : 1; /* Temperature data ready */ 3944 } lsm6dso32x_status_t; 3945 int32_t lsm6dso32x_status_get(const stmdev_ctx_t *ctx, 3946 lsm6dso32x_status_t *val); 3947 3948 typedef struct 3949 { 3950 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 3951 uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 3952 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 3953 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 3954 } lsm6dso32x_pin_conf_t; 3955 int32_t lsm6dso32x_pin_conf_set(const stmdev_ctx_t *ctx, 3956 lsm6dso32x_pin_conf_t val); 3957 int32_t lsm6dso32x_pin_conf_get(const stmdev_ctx_t *ctx, 3958 lsm6dso32x_pin_conf_t *val); 3959 3960 typedef struct 3961 { 3962 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 3963 uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 3964 uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 3965 } lsm6dso32x_int_mode_t; 3966 int32_t lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t *ctx, 3967 lsm6dso32x_int_mode_t val); 3968 int32_t lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t *ctx, 3969 lsm6dso32x_int_mode_t *val); 3970 3971 typedef struct 3972 { 3973 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 3974 uint8_t drdy_g : 1; /* Gyroscope data ready */ 3975 uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ 3976 uint8_t boot : 1; /* Restoring calibration parameters */ 3977 uint8_t fifo_th : 1; /* FIFO threshold reached */ 3978 uint8_t fifo_ovr : 1; /* FIFO overrun */ 3979 uint8_t fifo_full : 1; /* FIFO full */ 3980 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 3981 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 3982 uint8_t sh_endop : 1; /* sensor hub end operation */ 3983 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 3984 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 3985 uint8_t double_tap : 1; /* double-tap event */ 3986 uint8_t free_fall : 1; /* free fall event */ 3987 uint8_t wake_up : 1; /* wake up event */ 3988 uint8_t single_tap : 1; /* single-tap event */ 3989 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 3990 uint8_t step_detector : 1; /* Step detected */ 3991 uint8_t tilt : 1; /* Relative tilt event detected */ 3992 uint8_t sig_mot : 1; /* "significant motion" event detected */ 3993 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 3994 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 3995 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 3996 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 3997 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 3998 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 3999 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4000 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4001 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4002 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4003 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4004 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4005 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4006 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4007 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4008 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4009 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4010 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4011 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4012 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4013 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4014 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4015 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4016 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4017 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4018 } lsm6dso32x_pin_int1_route_t; 4019 4020 int32_t lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t *ctx, 4021 lsm6dso32x_pin_int1_route_t val); 4022 int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx, 4023 lsm6dso32x_pin_int1_route_t *val); 4024 4025 typedef struct 4026 { 4027 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4028 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4029 uint8_t drdy_temp : 1; /* Temperature data ready */ 4030 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4031 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4032 uint8_t fifo_full : 1; /* FIFO full */ 4033 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4034 uint8_t timestamp : 1; /* timestamp overflow */ 4035 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4036 uint8_t double_tap : 1; /* double-tap event */ 4037 uint8_t free_fall : 1; /* free fall event */ 4038 uint8_t wake_up : 1; /* wake up event */ 4039 uint8_t single_tap : 1; /* single-tap event */ 4040 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 4041 uint8_t step_detector : 1; /* Step detected */ 4042 uint8_t tilt : 1; /* Relative tilt event detected */ 4043 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4044 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 4045 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4046 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4047 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4048 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4049 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4050 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4051 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4052 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4053 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4054 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4055 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4056 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4057 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4058 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4059 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4060 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4061 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4062 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4063 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4064 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4065 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4066 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4067 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4068 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4069 } lsm6dso32x_pin_int2_route_t; 4070 4071 int32_t lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t *ctx, 4072 lsm6dso32x_pin_int2_route_t val); 4073 int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx, 4074 lsm6dso32x_pin_int2_route_t *val); 4075 4076 typedef struct 4077 { 4078 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4079 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4080 uint8_t drdy_temp : 1; /* Temperature data ready */ 4081 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 4082 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 4083 uint8_t free_fall : 1; /* free fall event */ 4084 uint8_t wake_up : 1; /* wake up event */ 4085 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 4086 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 4087 uint8_t wake_up_x : 1; /* wake up on X axis event */ 4088 uint8_t single_tap : 1; /* single-tap event */ 4089 uint8_t double_tap : 1; /* double-tap event */ 4090 uint8_t tap_z : 1; /* single-tap on Z axis event */ 4091 uint8_t tap_y : 1; /* single-tap on Y axis event */ 4092 uint8_t tap_x : 1; /* single-tap on X axis event */ 4093 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 4094 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4095 uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ 4096 uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ 4097 uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ 4098 uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ 4099 uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ 4100 uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ 4101 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 4102 uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 4103 uint8_t step_detector : 1; /* Step detected */ 4104 uint8_t tilt : 1; /* Relative tilt event detected */ 4105 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4106 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 4107 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4108 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4109 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4110 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4111 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4112 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4113 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4114 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4115 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4116 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4117 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4118 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4119 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4120 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4121 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4122 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4123 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4124 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4125 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4126 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4127 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4128 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4129 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4130 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4131 uint8_t sh_endop : 1; /* sensor hub end operation */ 4132 uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ 4133 uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ 4134 uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ 4135 uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ 4136 uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 4137 uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ 4138 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 4139 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4140 uint8_t fifo_full : 1; /* FIFO full */ 4141 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4142 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4143 } lsm6dso32x_all_sources_t; 4144 int32_t lsm6dso32x_all_sources_get(const stmdev_ctx_t *ctx, 4145 lsm6dso32x_all_sources_t *val); 4146 4147 typedef struct 4148 { 4149 uint8_t odr_fine_tune; 4150 } lsm6dso32x_dev_cal_t; 4151 int32_t lsm6dso32x_calibration_get(const stmdev_ctx_t *ctx, 4152 lsm6dso32x_dev_cal_t *val); 4153 4154 typedef enum 4155 { 4156 LSM6DSO32X_XL_UI_OFF = 0x00, /* in power down */ 4157 LSM6DSO32X_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 4158 LSM6DSO32X_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy) */ 4159 LSM6DSO32X_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 4160 LSM6DSO32X_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 4161 LSM6DSO32X_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy) */ 4162 LSM6DSO32X_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 4163 LSM6DSO32X_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 4164 LSM6DSO32X_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy) */ 4165 LSM6DSO32X_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 4166 LSM6DSO32X_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 4167 LSM6DSO32X_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy) */ 4168 LSM6DSO32X_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 4169 LSM6DSO32X_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 4170 LSM6DSO32X_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy) */ 4171 LSM6DSO32X_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 4172 LSM6DSO32X_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 4173 LSM6DSO32X_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy) */ 4174 LSM6DSO32X_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 4175 LSM6DSO32X_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 4176 LSM6DSO32X_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 4177 LSM6DSO32X_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 4178 LSM6DSO32X_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 4179 } lsm6dso32x_ui_xl_odr_t; 4180 4181 typedef enum 4182 { 4183 LSM6DSO32X_XL_UI_4g = 0, 4184 LSM6DSO32X_XL_UI_32g = 1, 4185 LSM6DSO32X_XL_UI_8g = 2, 4186 LSM6DSO32X_XL_UI_16g = 3, 4187 } lsm6dso32x_ui_xl_fs_t; 4188 4189 typedef enum 4190 { 4191 LSM6DSO32X_GY_UI_OFF = 0x00, /* gy in power down */ 4192 LSM6DSO32X_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 4193 LSM6DSO32X_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 4194 LSM6DSO32X_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 4195 LSM6DSO32X_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 4196 LSM6DSO32X_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 4197 LSM6DSO32X_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 4198 LSM6DSO32X_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 4199 LSM6DSO32X_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 4200 LSM6DSO32X_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 4201 LSM6DSO32X_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 4202 LSM6DSO32X_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 4203 LSM6DSO32X_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 4204 LSM6DSO32X_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 4205 LSM6DSO32X_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 4206 LSM6DSO32X_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 4207 } lsm6dso32x_ui_gy_odr_t; 4208 4209 typedef enum 4210 { 4211 LSM6DSO32X_GY_UI_250dps = 0, 4212 LSM6DSO32X_GY_UI_125dps = 1, 4213 LSM6DSO32X_GY_UI_500dps = 2, 4214 LSM6DSO32X_GY_UI_1000dps = 4, 4215 LSM6DSO32X_GY_UI_2000dps = 6, 4216 } lsm6dso32x_ui_gy_fs_t; 4217 4218 typedef enum 4219 { 4220 LSM6DSO32X_FSM_DISABLE = 0x00, 4221 LSM6DSO32X_FSM_XL = 0x01, 4222 LSM6DSO32X_FSM_GY = 0x02, 4223 LSM6DSO32X_FSM_XL_GY = 0x03, 4224 } lsm6dso32x_fsm_sens_t; 4225 4226 typedef enum 4227 { 4228 LSM6DSO32X_MLC_DISABLE = 0x00, 4229 LSM6DSO32X_MLC_XL = 0x01, 4230 LSM6DSO32X_MLC_XL_GY = 0x03, 4231 } lsm6dso32x_mlc_sens_t; 4232 4233 typedef struct 4234 { 4235 struct 4236 { 4237 struct 4238 { 4239 lsm6dso32x_ui_xl_odr_t odr; 4240 lsm6dso32x_ui_xl_fs_t fs; 4241 } xl; 4242 struct 4243 { 4244 lsm6dso32x_ui_gy_odr_t odr; 4245 lsm6dso32x_ui_gy_fs_t fs; 4246 } gy; 4247 } ui; 4248 struct 4249 { 4250 lsm6dso32x_fsm_sens_t sens; 4251 lsm6dso32x_fsm_odr_t odr; 4252 } fsm; 4253 struct 4254 { 4255 lsm6dso32x_mlc_sens_t sens; 4256 lsm6dso32x_mlc_odr_t odr; 4257 } mlc; 4258 } lsm6dso32x_md_t; 4259 int32_t lsm6dso32x_mode_set(const stmdev_ctx_t *ctx, 4260 lsm6dso32x_md_t *val); 4261 int32_t lsm6dso32x_mode_get(const stmdev_ctx_t *ctx, 4262 lsm6dso32x_md_t *val); 4263 4264 typedef struct 4265 { 4266 struct 4267 { 4268 struct 4269 { 4270 float mg[3]; 4271 int16_t raw[3]; 4272 } xl; 4273 struct 4274 { 4275 float mdps[3]; 4276 int16_t raw[3]; 4277 } gy; 4278 struct 4279 { 4280 float deg_c; 4281 int16_t raw; 4282 } heat; 4283 } ui; 4284 } lsm6dso32x_data_t; 4285 int32_t lsm6dso32x_data_get(const stmdev_ctx_t *ctx, 4286 lsm6dso32x_md_t *md, 4287 lsm6dso32x_data_t *data); 4288 4289 typedef struct 4290 { 4291 uint8_t sig_mot : 1; /* significant motion */ 4292 uint8_t tilt : 1; /* tilt detection */ 4293 uint8_t step : 1; /* step counter/detector */ 4294 uint8_t mlc : 1; /* machine learning core */ 4295 uint8_t fsm : 1; /* finite state machine */ 4296 uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ 4297 } lsm6dso32x_emb_sens_t; 4298 int32_t lsm6dso32x_embedded_sens_set(const stmdev_ctx_t *ctx, 4299 lsm6dso32x_emb_sens_t *emb_sens); 4300 int32_t lsm6dso32x_embedded_sens_get(const stmdev_ctx_t *ctx, 4301 lsm6dso32x_emb_sens_t *emb_sens); 4302 int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx); 4303 4304 /** 4305 * @} 4306 * 4307 */ 4308 4309 #ifdef __cplusplus 4310 } 4311 #endif 4312 4313 #endif /*LSM6DSO32X_DRIVER_H */ 4314 4315 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4316
