1 /**
2 ******************************************************************************
3 * @file lsm6dso32x_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO32X driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso32x_reg.h"
21
22 /**
23 * @defgroup LSM6DSO32X
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso32x enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSO32X_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error).
47 *
48 */
lsm6dso32x_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error).
73 *
74 */
lsm6dso32x_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dso32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSO32X_Private_functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup LSM6DSO32X_Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dso32x_from_fs4_to_mg(int16_t lsb)122 float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.122f;
125 }
126
lsm6dso32x_from_fs8_to_mg(int16_t lsb)127 float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.244f;
130 }
131
lsm6dso32x_from_fs16_to_mg(int16_t lsb)132 float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.488f;
135 }
136
lsm6dso32x_from_fs32_to_mg(int16_t lsb)137 float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.976f;
140 }
141
lsm6dso32x_from_fs125_to_mdps(int16_t lsb)142 float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 4.375f;
145 }
146
lsm6dso32x_from_fs500_to_mdps(int16_t lsb)147 float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 17.50f;
150 }
151
lsm6dso32x_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dso32x_from_fs1000_to_mdps(int16_t lsb)157 float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 35.0f;
160 }
161
lsm6dso32x_from_fs2000_to_mdps(int16_t lsb)162 float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 70.0f;
165 }
166
lsm6dso32x_from_lsb_to_celsius(int16_t lsb)167 float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb)
168 {
169 return (((float_t)lsb / 256.0f) + 25.0f);
170 }
171
lsm6dso32x_from_lsb_to_nsec(int16_t lsb)172 float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb)
173 {
174 return ((float_t)lsb * 25000.0f);
175 }
176
177 /**
178 * @}
179 *
180 */
181
182 /**
183 * @defgroup LSM6DSO32X_Data_Generation
184 * @brief This section groups all the functions concerning
185 * data generation.
186 *
187 */
188
189 /**
190 * @brief Accelerometer full-scale selection.[set]
191 *
192 * @param ctx read / write interface definitions
193 * @param val change the values of fs_xl in reg CTRL1_XL
194 * @retval interface status (MANDATORY: return 0 -> no Error).
195 *
196 */
lsm6dso32x_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso32x_fs_xl_t val)197 int32_t lsm6dso32x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val)
198 {
199 lsm6dso32x_ctrl1_xl_t reg;
200 int32_t ret;
201
202 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
203
204 if (ret == 0)
205 {
206 reg.fs_xl = (uint8_t) val;
207 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
208 }
209
210 return ret;
211 }
212
213 /**
214 * @brief Accelerometer full-scale selection.[get]
215 *
216 * @param ctx read / write interface definitions
217 * @param val Get the values of fs_xl in reg CTRL1_XL
218 * @retval interface status (MANDATORY: return 0 -> no Error).
219 *
220 */
lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso32x_fs_xl_t * val)221 int32_t lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t *ctx,
222 lsm6dso32x_fs_xl_t *val)
223 {
224 lsm6dso32x_ctrl1_xl_t reg;
225 int32_t ret;
226
227 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
228
229 switch (reg.fs_xl)
230 {
231 case LSM6DSO32X_16g:
232 *val = LSM6DSO32X_16g;
233 break;
234
235 case LSM6DSO32X_4g:
236 *val = LSM6DSO32X_4g;
237 break;
238
239 case LSM6DSO32X_8g:
240 *val = LSM6DSO32X_8g;
241 break;
242
243 case LSM6DSO32X_32g:
244 *val = LSM6DSO32X_32g;
245 break;
246
247 default:
248 *val = LSM6DSO32X_4g;
249 break;
250 }
251
252 return ret;
253 }
254
255 /**
256 * @brief Accelerometer UI data rate selection.[set]
257 *
258 * @param ctx read / write interface definitions
259 * @param val change the values of odr_xl in reg CTRL1_XL
260 * @retval interface status (MANDATORY: return 0 -> no Error).
261 *
262 */
lsm6dso32x_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32x_odr_xl_t val)263 int32_t lsm6dso32x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val)
264 {
265 lsm6dso32x_odr_xl_t odr_xl = val;
266 lsm6dso32x_emb_fsm_enable_t fsm_enable;
267 lsm6dso32x_fsm_odr_t fsm_odr;
268 lsm6dso32x_emb_sens_t emb_sens;
269 lsm6dso32x_mlc_odr_t mlc_odr;
270 lsm6dso32x_ctrl1_xl_t reg;
271 int32_t ret;
272
273 /* Check the Finite State Machine data rate constraints */
274 ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
275
276 if (ret == 0)
277 {
278 if ((fsm_enable.fsm_enable_a.fsm1_en |
279 fsm_enable.fsm_enable_a.fsm2_en |
280 fsm_enable.fsm_enable_a.fsm3_en |
281 fsm_enable.fsm_enable_a.fsm4_en |
282 fsm_enable.fsm_enable_a.fsm5_en |
283 fsm_enable.fsm_enable_a.fsm6_en |
284 fsm_enable.fsm_enable_a.fsm7_en |
285 fsm_enable.fsm_enable_a.fsm8_en |
286 fsm_enable.fsm_enable_b.fsm9_en |
287 fsm_enable.fsm_enable_b.fsm10_en |
288 fsm_enable.fsm_enable_b.fsm11_en |
289 fsm_enable.fsm_enable_b.fsm12_en |
290 fsm_enable.fsm_enable_b.fsm13_en |
291 fsm_enable.fsm_enable_b.fsm14_en |
292 fsm_enable.fsm_enable_b.fsm15_en |
293 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
294 {
295 ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
296
297 if (ret == 0)
298 {
299 switch (fsm_odr)
300 {
301 case LSM6DSO32X_ODR_FSM_12Hz5:
302 if (val == LSM6DSO32X_XL_ODR_OFF)
303 {
304 odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
305 }
306
307 else
308 {
309 odr_xl = val;
310 }
311
312 break;
313
314 case LSM6DSO32X_ODR_FSM_26Hz:
315 if (val == LSM6DSO32X_XL_ODR_OFF)
316 {
317 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
318 }
319
320 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
321 {
322 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
323 }
324
325 else
326 {
327 odr_xl = val;
328 }
329
330 break;
331
332 case LSM6DSO32X_ODR_FSM_52Hz:
333 if (val == LSM6DSO32X_XL_ODR_OFF)
334 {
335 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
336 }
337
338 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
339 {
340 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
341 }
342
343 else if (val == LSM6DSO32X_XL_ODR_26Hz)
344 {
345 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
346 }
347
348 else
349 {
350 odr_xl = val;
351 }
352
353 break;
354
355 case LSM6DSO32X_ODR_FSM_104Hz:
356 if (val == LSM6DSO32X_XL_ODR_OFF)
357 {
358 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
359 }
360
361 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
362 {
363 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
364 }
365
366 else if (val == LSM6DSO32X_XL_ODR_26Hz)
367 {
368 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
369 }
370
371 else if (val == LSM6DSO32X_XL_ODR_52Hz)
372 {
373 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
374 }
375
376 else
377 {
378 odr_xl = val;
379 }
380
381 break;
382
383 default:
384 odr_xl = val;
385 break;
386 }
387 }
388 }
389 }
390
391 /* Check the Machine Learning Core data rate constraints */
392 emb_sens.mlc = PROPERTY_DISABLE;
393
394 if (ret == 0)
395 {
396 ret = lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
397
398 if ((ret == 0) && (emb_sens.mlc == PROPERTY_ENABLE))
399 {
400 ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
401
402 if (ret == 0)
403 {
404 switch (mlc_odr)
405 {
406 case LSM6DSO32X_ODR_PRGS_12Hz5:
407 if (val == LSM6DSO32X_XL_ODR_OFF)
408 {
409 odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
410 }
411
412 else
413 {
414 odr_xl = val;
415 }
416
417 break;
418
419 case LSM6DSO32X_ODR_PRGS_26Hz:
420 if (val == LSM6DSO32X_XL_ODR_OFF)
421 {
422 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
423 }
424
425 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
426 {
427 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
428 }
429
430 else
431 {
432 odr_xl = val;
433 }
434
435 break;
436
437 case LSM6DSO32X_ODR_PRGS_52Hz:
438 if (val == LSM6DSO32X_XL_ODR_OFF)
439 {
440 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
441 }
442
443 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
444 {
445 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
446 }
447
448 else if (val == LSM6DSO32X_XL_ODR_26Hz)
449 {
450 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
451 }
452
453 else
454 {
455 odr_xl = val;
456 }
457
458 break;
459
460 case LSM6DSO32X_ODR_PRGS_104Hz:
461 if (val == LSM6DSO32X_XL_ODR_OFF)
462 {
463 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
464 }
465
466 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
467 {
468 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
469 }
470
471 else if (val == LSM6DSO32X_XL_ODR_26Hz)
472 {
473 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
474 }
475
476 else if (val == LSM6DSO32X_XL_ODR_52Hz)
477 {
478 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
479 }
480
481 else
482 {
483 odr_xl = val;
484 }
485
486 break;
487
488 default:
489 odr_xl = val;
490 break;
491 }
492 }
493 }
494 }
495
496 if (ret == 0)
497 {
498 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
499 }
500
501 if (ret == 0)
502 {
503 reg.odr_xl = (uint8_t) odr_xl;
504 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
505 }
506
507 return ret;
508 }
509
510 /**
511 * @brief Accelerometer UI data rate selection.[get]
512 *
513 * @param ctx read / write interface definitions
514 * @param val Get the values of odr_xl in reg CTRL1_XL
515 * @retval interface status (MANDATORY: return 0 -> no Error).
516 *
517 */
lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32x_odr_xl_t * val)518 int32_t lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val)
519 {
520 lsm6dso32x_ctrl1_xl_t reg;
521 int32_t ret;
522
523 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
524
525 switch (reg.odr_xl)
526 {
527 case LSM6DSO32X_XL_ODR_OFF:
528 *val = LSM6DSO32X_XL_ODR_OFF;
529 break;
530
531 case LSM6DSO32X_XL_ODR_12Hz5:
532 *val = LSM6DSO32X_XL_ODR_12Hz5;
533 break;
534
535 case LSM6DSO32X_XL_ODR_26Hz:
536 *val = LSM6DSO32X_XL_ODR_26Hz;
537 break;
538
539 case LSM6DSO32X_XL_ODR_52Hz:
540 *val = LSM6DSO32X_XL_ODR_52Hz;
541 break;
542
543 case LSM6DSO32X_XL_ODR_104Hz:
544 *val = LSM6DSO32X_XL_ODR_104Hz;
545 break;
546
547 case LSM6DSO32X_XL_ODR_208Hz:
548 *val = LSM6DSO32X_XL_ODR_208Hz;
549 break;
550
551 case LSM6DSO32X_XL_ODR_417Hz:
552 *val = LSM6DSO32X_XL_ODR_417Hz;
553 break;
554
555 case LSM6DSO32X_XL_ODR_833Hz:
556 *val = LSM6DSO32X_XL_ODR_833Hz;
557 break;
558
559 case LSM6DSO32X_XL_ODR_1667Hz:
560 *val = LSM6DSO32X_XL_ODR_1667Hz;
561 break;
562
563 case LSM6DSO32X_XL_ODR_3333Hz:
564 *val = LSM6DSO32X_XL_ODR_3333Hz;
565 break;
566
567 case LSM6DSO32X_XL_ODR_6667Hz:
568 *val = LSM6DSO32X_XL_ODR_6667Hz;
569 break;
570
571 case LSM6DSO32X_XL_ODR_1Hz6:
572 *val = LSM6DSO32X_XL_ODR_1Hz6;
573 break;
574
575 default:
576 *val = LSM6DSO32X_XL_ODR_OFF;
577 break;
578 }
579
580 return ret;
581 }
582
583 /**
584 * @brief Gyroscope UI chain full-scale selection.[set]
585 *
586 * @param ctx read / write interface definitions
587 * @param val change the values of fs_g in reg CTRL2_G
588 * @retval interface status (MANDATORY: return 0 -> no Error).
589 *
590 */
lsm6dso32x_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso32x_fs_g_t val)591 int32_t lsm6dso32x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val)
592 {
593 lsm6dso32x_ctrl2_g_t reg;
594 int32_t ret;
595
596 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
597
598 if (ret == 0)
599 {
600 reg.fs_g = (uint8_t) val;
601 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
602 }
603
604 return ret;
605 }
606
607 /**
608 * @brief Gyroscope UI chain full-scale selection.[get]
609 *
610 * @param ctx read / write interface definitions
611 * @param val Get the values of fs_g in reg CTRL2_G
612 * @retval interface status (MANDATORY: return 0 -> no Error).
613 *
614 */
lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso32x_fs_g_t * val)615 int32_t lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val)
616 {
617 lsm6dso32x_ctrl2_g_t reg;
618 int32_t ret;
619
620 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
621
622 switch (reg.fs_g)
623 {
624 case LSM6DSO32X_250dps:
625 *val = LSM6DSO32X_250dps;
626 break;
627
628 case LSM6DSO32X_125dps:
629 *val = LSM6DSO32X_125dps;
630 break;
631
632 case LSM6DSO32X_500dps:
633 *val = LSM6DSO32X_500dps;
634 break;
635
636 case LSM6DSO32X_1000dps:
637 *val = LSM6DSO32X_1000dps;
638 break;
639
640 case LSM6DSO32X_2000dps:
641 *val = LSM6DSO32X_2000dps;
642 break;
643
644 default:
645 *val = LSM6DSO32X_250dps;
646 break;
647 }
648
649 return ret;
650 }
651
652 /**
653 * @brief Gyroscope UI data rate selection.[set]
654 *
655 * @param ctx read / write interface definitions
656 * @param val change the values of odr_g in reg CTRL2_G
657 * @retval interface status (MANDATORY: return 0 -> no Error).
658 *
659 */
lsm6dso32x_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32x_odr_g_t val)660 int32_t lsm6dso32x_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val)
661 {
662 lsm6dso32x_odr_g_t odr_gy = val;
663 lsm6dso32x_emb_fsm_enable_t fsm_enable;
664 lsm6dso32x_fsm_odr_t fsm_odr;
665 lsm6dso32x_emb_sens_t emb_sens;
666 lsm6dso32x_mlc_odr_t mlc_odr;
667 lsm6dso32x_ctrl2_g_t reg;
668 int32_t ret;
669
670 /* Check the Finite State Machine data rate constraints */
671 ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
672
673 if (ret == 0)
674 {
675 if ((fsm_enable.fsm_enable_a.fsm1_en |
676 fsm_enable.fsm_enable_a.fsm2_en |
677 fsm_enable.fsm_enable_a.fsm3_en |
678 fsm_enable.fsm_enable_a.fsm4_en |
679 fsm_enable.fsm_enable_a.fsm5_en |
680 fsm_enable.fsm_enable_a.fsm6_en |
681 fsm_enable.fsm_enable_a.fsm7_en |
682 fsm_enable.fsm_enable_a.fsm8_en |
683 fsm_enable.fsm_enable_b.fsm9_en |
684 fsm_enable.fsm_enable_b.fsm10_en |
685 fsm_enable.fsm_enable_b.fsm11_en |
686 fsm_enable.fsm_enable_b.fsm12_en |
687 fsm_enable.fsm_enable_b.fsm13_en |
688 fsm_enable.fsm_enable_b.fsm14_en |
689 fsm_enable.fsm_enable_b.fsm15_en |
690 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
691 {
692 ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
693
694 if (ret == 0)
695 {
696 switch (fsm_odr)
697 {
698 case LSM6DSO32X_ODR_FSM_12Hz5:
699 if (val == LSM6DSO32X_GY_ODR_OFF)
700 {
701 odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
702 }
703
704 else
705 {
706 odr_gy = val;
707 }
708
709 break;
710
711 case LSM6DSO32X_ODR_FSM_26Hz:
712 if (val == LSM6DSO32X_GY_ODR_OFF)
713 {
714 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
715 }
716
717 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
718 {
719 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
720 }
721
722 else
723 {
724 odr_gy = val;
725 }
726
727 break;
728
729 case LSM6DSO32X_ODR_FSM_52Hz:
730 if (val == LSM6DSO32X_GY_ODR_OFF)
731 {
732 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
733 }
734
735 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
736 {
737 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
738 }
739
740 else if (val == LSM6DSO32X_GY_ODR_26Hz)
741 {
742 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
743 }
744
745 else
746 {
747 odr_gy = val;
748 }
749
750 break;
751
752 case LSM6DSO32X_ODR_FSM_104Hz:
753 if (val == LSM6DSO32X_GY_ODR_OFF)
754 {
755 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
756 }
757
758 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
759 {
760 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
761 }
762
763 else if (val == LSM6DSO32X_GY_ODR_26Hz)
764 {
765 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
766 }
767
768 else if (val == LSM6DSO32X_GY_ODR_52Hz)
769 {
770 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
771 }
772
773 else
774 {
775 odr_gy = val;
776 }
777
778 break;
779
780 default:
781 odr_gy = val;
782 break;
783 }
784 }
785 }
786 }
787
788 /* Check the Machine Learning Core data rate constraints */
789 emb_sens.mlc = PROPERTY_DISABLE;
790
791 if (ret == 0)
792 {
793 ret = lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
794
795 if (emb_sens.mlc == PROPERTY_ENABLE)
796 {
797 ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
798
799 if (ret == 0)
800 {
801 switch (mlc_odr)
802 {
803 case LSM6DSO32X_ODR_PRGS_12Hz5:
804 if (val == LSM6DSO32X_GY_ODR_OFF)
805 {
806 odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
807 }
808
809 else
810 {
811 odr_gy = val;
812 }
813
814 break;
815
816 case LSM6DSO32X_ODR_PRGS_26Hz:
817 if (val == LSM6DSO32X_GY_ODR_OFF)
818 {
819 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
820 }
821
822 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
823 {
824 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
825 }
826
827 else
828 {
829 odr_gy = val;
830 }
831
832 break;
833
834 case LSM6DSO32X_ODR_PRGS_52Hz:
835 if (val == LSM6DSO32X_GY_ODR_OFF)
836 {
837 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
838 }
839
840 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
841 {
842 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
843 }
844
845 else if (val == LSM6DSO32X_GY_ODR_26Hz)
846 {
847 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
848 }
849
850 else
851 {
852 odr_gy = val;
853 }
854
855 break;
856
857 case LSM6DSO32X_ODR_PRGS_104Hz:
858 if (val == LSM6DSO32X_GY_ODR_OFF)
859 {
860 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
861 }
862
863 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
864 {
865 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
866 }
867
868 else if (val == LSM6DSO32X_GY_ODR_26Hz)
869 {
870 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
871 }
872
873 else if (val == LSM6DSO32X_GY_ODR_52Hz)
874 {
875 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
876 }
877
878 else
879 {
880 odr_gy = val;
881 }
882
883 break;
884
885 default:
886 odr_gy = val;
887 break;
888 }
889 }
890 }
891 }
892
893 if (ret == 0)
894 {
895 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
896 }
897
898 if (ret == 0)
899 {
900 reg.odr_g = (uint8_t) odr_gy;
901 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
902 }
903
904 return ret;
905 }
906
907 /**
908 * @brief Gyroscope UI data rate selection.[get]
909 *
910 * @param ctx read / write interface definitions
911 * @param val Get the values of odr_g in reg CTRL2_G
912 * @retval interface status (MANDATORY: return 0 -> no Error).
913 *
914 */
lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32x_odr_g_t * val)915 int32_t lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val)
916 {
917 lsm6dso32x_ctrl2_g_t reg;
918 int32_t ret;
919
920 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
921
922 switch (reg.odr_g)
923 {
924 case LSM6DSO32X_GY_ODR_OFF:
925 *val = LSM6DSO32X_GY_ODR_OFF;
926 break;
927
928 case LSM6DSO32X_GY_ODR_12Hz5:
929 *val = LSM6DSO32X_GY_ODR_12Hz5;
930 break;
931
932 case LSM6DSO32X_GY_ODR_26Hz:
933 *val = LSM6DSO32X_GY_ODR_26Hz;
934 break;
935
936 case LSM6DSO32X_GY_ODR_52Hz:
937 *val = LSM6DSO32X_GY_ODR_52Hz;
938 break;
939
940 case LSM6DSO32X_GY_ODR_104Hz:
941 *val = LSM6DSO32X_GY_ODR_104Hz;
942 break;
943
944 case LSM6DSO32X_GY_ODR_208Hz:
945 *val = LSM6DSO32X_GY_ODR_208Hz;
946 break;
947
948 case LSM6DSO32X_GY_ODR_417Hz:
949 *val = LSM6DSO32X_GY_ODR_417Hz;
950 break;
951
952 case LSM6DSO32X_GY_ODR_833Hz:
953 *val = LSM6DSO32X_GY_ODR_833Hz;
954 break;
955
956 case LSM6DSO32X_GY_ODR_1667Hz:
957 *val = LSM6DSO32X_GY_ODR_1667Hz;
958 break;
959
960 case LSM6DSO32X_GY_ODR_3333Hz:
961 *val = LSM6DSO32X_GY_ODR_3333Hz;
962 break;
963
964 case LSM6DSO32X_GY_ODR_6667Hz:
965 *val = LSM6DSO32X_GY_ODR_6667Hz;
966 break;
967
968 default:
969 *val = LSM6DSO32X_GY_ODR_OFF;
970 break;
971 }
972
973 return ret;
974 }
975
976 /**
977 * @brief Block data update.[set]
978 *
979 * @param ctx read / write interface definitions
980 * @param val change the values of bdu in reg CTRL3_C
981 * @retval interface status (MANDATORY: return 0 -> no Error).
982 *
983 */
lsm6dso32x_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)984 int32_t lsm6dso32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
985 {
986 lsm6dso32x_ctrl3_c_t reg;
987 int32_t ret;
988
989 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
990
991 if (ret == 0)
992 {
993 reg.bdu = val;
994 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
995 }
996
997 return ret;
998 }
999
1000 /**
1001 * @brief Block data update.[get]
1002 *
1003 * @param ctx read / write interface definitions
1004 * @param val change the values of bdu in reg CTRL3_C
1005 * @retval interface status (MANDATORY: return 0 -> no Error).
1006 *
1007 */
lsm6dso32x_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1008 int32_t lsm6dso32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
1009 {
1010 lsm6dso32x_ctrl3_c_t reg;
1011 int32_t ret;
1012
1013 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
1014 *val = reg.bdu;
1015
1016 return ret;
1017 }
1018
1019 /**
1020 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1021 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1022 *
1023 * @param ctx read / write interface definitions
1024 * @param val change the values of usr_off_w in reg CTRL6_C
1025 * @retval interface status (MANDATORY: return 0 -> no Error).
1026 *
1027 */
lsm6dso32x_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dso32x_usr_off_w_t val)1028 int32_t lsm6dso32x_xl_offset_weight_set(const stmdev_ctx_t *ctx,
1029 lsm6dso32x_usr_off_w_t val)
1030 {
1031 lsm6dso32x_ctrl6_c_t reg;
1032 int32_t ret;
1033
1034 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1035
1036 if (ret == 0)
1037 {
1038 reg.usr_off_w = (uint8_t)val;
1039 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1040 }
1041
1042 return ret;
1043 }
1044
1045 /**
1046 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1047 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1048 *
1049 * @param ctx read / write interface definitions
1050 * @param val Get the values of usr_off_w in reg CTRL6_C
1051 * @retval interface status (MANDATORY: return 0 -> no Error).
1052 *
1053 */
lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dso32x_usr_off_w_t * val)1054 int32_t lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t *ctx,
1055 lsm6dso32x_usr_off_w_t *val)
1056 {
1057 lsm6dso32x_ctrl6_c_t reg;
1058 int32_t ret;
1059
1060 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1061
1062 switch (reg.usr_off_w)
1063 {
1064 case LSM6DSO32X_LSb_1mg:
1065 *val = LSM6DSO32X_LSb_1mg;
1066 break;
1067
1068 case LSM6DSO32X_LSb_16mg:
1069 *val = LSM6DSO32X_LSb_16mg;
1070 break;
1071
1072 default:
1073 *val = LSM6DSO32X_LSb_1mg;
1074 break;
1075 }
1076
1077 return ret;
1078 }
1079
1080 /**
1081 * @brief Accelerometer power mode.[set]
1082 *
1083 * @param ctx read / write interface definitions
1084 * @param val change the values of xl_hm_mode in
1085 * reg CTRL6_C
1086 * @retval interface status (MANDATORY: return 0 -> no Error).
1087 *
1088 */
lsm6dso32x_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_xl_hm_mode_t val)1089 int32_t lsm6dso32x_xl_power_mode_set(const stmdev_ctx_t *ctx,
1090 lsm6dso32x_xl_hm_mode_t val)
1091 {
1092 lsm6dso32x_ctrl5_c_t ctrl5_c;
1093 lsm6dso32x_ctrl6_c_t ctrl6_c;
1094 int32_t ret;
1095
1096 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
1097 (uint8_t *) &ctrl5_c, 1);
1098
1099 if (ret == 0)
1100 {
1101 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
1102 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
1103 (uint8_t *) &ctrl5_c, 1);
1104 }
1105
1106 if (ret == 0)
1107 {
1108 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
1109 (uint8_t *) &ctrl6_c, 1);
1110 }
1111
1112 if (ret == 0)
1113 {
1114 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1115 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C,
1116 (uint8_t *) &ctrl6_c, 1);
1117 }
1118
1119 return ret;
1120 }
1121
1122 /**
1123 * @brief Accelerometer power mode.[get]
1124 *
1125 * @param ctx read / write interface definitions
1126 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1127 * @retval interface status (MANDATORY: return 0 -> no Error).
1128 *
1129 */
lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_xl_hm_mode_t * val)1130 int32_t lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t *ctx,
1131 lsm6dso32x_xl_hm_mode_t *val)
1132 {
1133 lsm6dso32x_ctrl5_c_t ctrl5_c;
1134 lsm6dso32x_ctrl6_c_t ctrl6_c;
1135 int32_t ret;
1136
1137 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
1138 (uint8_t *) &ctrl5_c, 1);
1139
1140 if (ret == 0)
1141 {
1142 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
1143 (uint8_t *) &ctrl6_c, 1);
1144
1145 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
1146 {
1147 case LSM6DSO32X_HIGH_PERFORMANCE_MD:
1148 *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
1149 break;
1150
1151 case LSM6DSO32X_LOW_NORMAL_POWER_MD:
1152 *val = LSM6DSO32X_LOW_NORMAL_POWER_MD;
1153 break;
1154
1155 case LSM6DSO32X_ULTRA_LOW_POWER_MD:
1156 *val = LSM6DSO32X_ULTRA_LOW_POWER_MD;
1157 break;
1158
1159 default:
1160 *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
1161 break;
1162 }
1163 }
1164
1165 return ret;
1166 }
1167
1168 /**
1169 * @brief Operating mode for gyroscope.[set]
1170 *
1171 * @param ctx read / write interface definitions
1172 * @param val change the values of g_hm_mode in reg CTRL7_G
1173 * @retval interface status (MANDATORY: return 0 -> no Error).
1174 *
1175 */
lsm6dso32x_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_g_hm_mode_t val)1176 int32_t lsm6dso32x_gy_power_mode_set(const stmdev_ctx_t *ctx,
1177 lsm6dso32x_g_hm_mode_t val)
1178 {
1179 lsm6dso32x_ctrl7_g_t reg;
1180 int32_t ret;
1181
1182 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1183
1184 if (ret == 0)
1185 {
1186 reg.g_hm_mode = (uint8_t)val;
1187 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1188 }
1189
1190 return ret;
1191 }
1192
1193 /**
1194 * @brief Operating mode for gyroscope.[get]
1195 *
1196 * @param ctx read / write interface definitions
1197 * @param val Get the values of g_hm_mode in reg CTRL7_G
1198 * @retval interface status (MANDATORY: return 0 -> no Error).
1199 *
1200 */
lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_g_hm_mode_t * val)1201 int32_t lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t *ctx,
1202 lsm6dso32x_g_hm_mode_t *val)
1203 {
1204 lsm6dso32x_ctrl7_g_t reg;
1205 int32_t ret;
1206
1207 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1208
1209 switch (reg.g_hm_mode)
1210 {
1211 case LSM6DSO32X_GY_HIGH_PERFORMANCE:
1212 *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
1213 break;
1214
1215 case LSM6DSO32X_GY_NORMAL:
1216 *val = LSM6DSO32X_GY_NORMAL;
1217 break;
1218
1219 default:
1220 *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
1221 break;
1222 }
1223
1224 return ret;
1225 }
1226
1227 /**
1228 * @brief The STATUS_REG register is read by the primary interface.[get]
1229 *
1230 * @param ctx read / write interface definitions
1231 * @param val register STATUS_REG
1232 * @retval interface status (MANDATORY: return 0 -> no Error).
1233 *
1234 */
lsm6dso32x_status_reg_get(const stmdev_ctx_t * ctx,lsm6dso32x_status_reg_t * val)1235 int32_t lsm6dso32x_status_reg_get(const stmdev_ctx_t *ctx,
1236 lsm6dso32x_status_reg_t *val)
1237 {
1238 int32_t ret;
1239
1240 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *) val, 1);
1241
1242 return ret;
1243 }
1244
1245 /**
1246 * @brief Accelerometer new data available.[get]
1247 *
1248 * @param ctx read / write interface definitions
1249 * @param val change the values of xlda in reg STATUS_REG
1250 * @retval interface status (MANDATORY: return 0 -> no Error).
1251 *
1252 */
lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1253 int32_t lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1254 {
1255 lsm6dso32x_status_reg_t reg;
1256 int32_t ret;
1257
1258 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1259 *val = reg.xlda;
1260
1261 return ret;
1262 }
1263
1264 /**
1265 * @brief Gyroscope new data available.[get]
1266 *
1267 * @param ctx read / write interface definitions
1268 * @param val change the values of gda in reg STATUS_REG
1269 * @retval interface status (MANDATORY: return 0 -> no Error).
1270 *
1271 */
lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1272 int32_t lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1273 {
1274 lsm6dso32x_status_reg_t reg;
1275 int32_t ret;
1276
1277 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1278 *val = reg.gda;
1279
1280 return ret;
1281 }
1282
1283 /**
1284 * @brief Temperature new data available.[get]
1285 *
1286 * @param ctx read / write interface definitions
1287 * @param val change the values of tda in reg STATUS_REG
1288 * @retval interface status (MANDATORY: return 0 -> no Error).
1289 *
1290 */
lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1291 int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1292 {
1293 lsm6dso32x_status_reg_t reg;
1294 int32_t ret;
1295
1296 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1297 *val = reg.tda;
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * @brief Accelerometer X-axis user offset correction expressed in
1304 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1305 * The value must be in the range [-127 127].[set]
1306 *
1307 * @param ctx read / write interface definitions
1308 * @param buff buffer that contains data to write
1309 * @retval interface status (MANDATORY: return 0 -> no Error).
1310 *
1311 */
lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1312 int32_t lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1313 {
1314 int32_t ret;
1315
1316 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
1317
1318 return ret;
1319 }
1320
1321 /**
1322 * @brief Accelerometer X-axis user offset correction expressed in two’s
1323 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1324 * The value must be in the range [-127 127].[get]
1325 *
1326 * @param ctx read / write interface definitions
1327 * @param buff buffer that stores data read
1328 * @retval interface status (MANDATORY: return 0 -> no Error).
1329 *
1330 */
lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1331 int32_t lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1332 {
1333 int32_t ret;
1334
1335 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
1336
1337 return ret;
1338 }
1339
1340 /**
1341 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1342 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1343 * The value must be in the range [-127 127].[set]
1344 *
1345 * @param ctx read / write interface definitions
1346 * @param buff buffer that contains data to write
1347 * @retval interface status (MANDATORY: return 0 -> no Error).
1348 *
1349 */
lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1350 int32_t lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1351 {
1352 int32_t ret;
1353
1354 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
1355
1356 return ret;
1357 }
1358
1359 /**
1360 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1361 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1362 * The value must be in the range [-127 127].[get]
1363 *
1364 * @param ctx read / write interface definitions
1365 * @param buff buffer that stores data read
1366 * @retval interface status (MANDATORY: return 0 -> no Error).
1367 *
1368 */
lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1369 int32_t lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1370 {
1371 int32_t ret;
1372
1373 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
1374
1375 return ret;
1376 }
1377
1378 /**
1379 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1380 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1381 * The value must be in the range [-127 127].[set]
1382 *
1383 * @param ctx read / write interface definitions
1384 * @param buff buffer that contains data to write
1385 * @retval interface status (MANDATORY: return 0 -> no Error).
1386 *
1387 */
lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1388 int32_t lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1389 {
1390 int32_t ret;
1391
1392 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
1393
1394 return ret;
1395 }
1396
1397 /**
1398 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1399 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1400 * The value must be in the range [-127 127].[get]
1401 *
1402 * @param ctx read / write interface definitions
1403 * @param buff buffer that stores data read
1404 * @retval interface status (MANDATORY: return 0 -> no Error).
1405 *
1406 */
lsm6dso32x_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1407 int32_t lsm6dso32x_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1408 {
1409 int32_t ret;
1410
1411 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
1412
1413 return ret;
1414 }
1415
1416 /**
1417 * @brief Enables user offset on out.[set]
1418 *
1419 * @param ctx read / write interface definitions
1420 * @param val change the values of usr_off_on_out in reg CTRL7_G
1421 * @retval interface status (MANDATORY: return 0 -> no Error).
1422 *
1423 */
lsm6dso32x_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1424 int32_t lsm6dso32x_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1425 {
1426 lsm6dso32x_ctrl7_g_t reg;
1427 int32_t ret;
1428
1429 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1430
1431 if (ret == 0)
1432 {
1433 reg.usr_off_on_out = val;
1434 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1435 }
1436
1437 return ret;
1438 }
1439
1440 /**
1441 * @brief User offset on out flag.[get]
1442 *
1443 * @param ctx read / write interface definitions
1444 * @param val values of usr_off_on_out in reg CTRL7_G
1445 * @retval interface status (MANDATORY: return 0 -> no Error).
1446 *
1447 */
lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1448 int32_t lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1449 {
1450 lsm6dso32x_ctrl7_g_t reg;
1451 int32_t ret;
1452
1453 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1454 *val = reg.usr_off_on_out;
1455
1456 return ret;
1457 }
1458
1459 /**
1460 * @}
1461 *
1462 */
1463
1464 /**
1465 * @defgroup LSM6DSO32X_Timestamp
1466 * @brief This section groups all the functions that manage the
1467 * timestamp generation.
1468 * @{
1469 *
1470 */
1471
1472 /**
1473 * @brief Reset timestamp counter.[set]
1474 *
1475 * @param ctx Read / write interface definitions.(ptr)
1476 * @retval Interface status (MANDATORY: return 0 -> no Error).
1477 * @retval interface status (MANDATORY: return 0 -> no Error).
1478 *
1479 */
lsm6dso32x_timestamp_rst(const stmdev_ctx_t * ctx)1480 int32_t lsm6dso32x_timestamp_rst(const stmdev_ctx_t *ctx)
1481 {
1482 uint8_t rst_val = 0xAA;
1483 return lsm6dso32x_write_reg(ctx, LSM6DSO32X_TIMESTAMP2, &rst_val, 1);
1484 }
1485
1486 /**
1487 * @brief Enables timestamp counter.[set]
1488 *
1489 * @param ctx read / write interface definitions
1490 * @param val change the values of timestamp_en in reg CTRL10_C
1491 * @retval interface status (MANDATORY: return 0 -> no Error).
1492 *
1493 */
lsm6dso32x_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1494 int32_t lsm6dso32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1495 {
1496 lsm6dso32x_ctrl10_c_t reg;
1497 int32_t ret;
1498
1499 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1500
1501 if (ret == 0)
1502 {
1503 reg.timestamp_en = val;
1504 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1505 }
1506
1507 return ret;
1508 }
1509
1510 /**
1511 * @brief Enables timestamp counter.[get]
1512 *
1513 * @param ctx read / write interface definitions
1514 * @param val change the values of timestamp_en in reg CTRL10_C
1515 * @retval interface status (MANDATORY: return 0 -> no Error).
1516 *
1517 */
lsm6dso32x_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1518 int32_t lsm6dso32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1519 {
1520 lsm6dso32x_ctrl10_c_t reg;
1521 int32_t ret;
1522
1523 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1524 *val = reg.timestamp_en;
1525
1526 return ret;
1527 }
1528
1529 /**
1530 * @brief Timestamp first data output register (r).
1531 * The value is expressed as a 32-bit word and the bit
1532 * resolution is 25 μs.[get]
1533 *
1534 * @param ctx read / write interface definitions
1535 * @param buff buffer that stores data read
1536 * @retval interface status (MANDATORY: return 0 -> no Error).
1537 *
1538 */
lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1539 int32_t lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1540 {
1541 uint8_t buff[4];
1542 int32_t ret;
1543
1544 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TIMESTAMP0, buff, 4);
1545 *val = buff[3];
1546 *val = (*val * 256U) + buff[2];
1547 *val = (*val * 256U) + buff[1];
1548 *val = (*val * 256U) + buff[0];
1549
1550 return ret;
1551 }
1552
1553 /**
1554 * @}
1555 *
1556 */
1557
1558 /**
1559 * @defgroup LSM6DSO32X_Data output
1560 * @brief This section groups all the data output functions.
1561 * @{
1562 *
1563 */
1564
1565 /**
1566 * @brief Circular burst-mode (rounding) read of the output
1567 * registers.[set]
1568 *
1569 * @param ctx read / write interface definitions
1570 * @param val change the values of rounding in reg CTRL5_C
1571 * @retval interface status (MANDATORY: return 0 -> no Error).
1572 *
1573 */
lsm6dso32x_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_rounding_t val)1574 int32_t lsm6dso32x_rounding_mode_set(const stmdev_ctx_t *ctx,
1575 lsm6dso32x_rounding_t val)
1576 {
1577 lsm6dso32x_ctrl5_c_t reg;
1578 int32_t ret;
1579
1580 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1581
1582 if (ret == 0)
1583 {
1584 reg.rounding = (uint8_t)val;
1585 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1586 }
1587
1588 return ret;
1589 }
1590
1591 /**
1592 * @brief Gyroscope UI chain full-scale selection.[get]
1593 *
1594 * @param ctx read / write interface definitions
1595 * @param val Get the values of rounding in reg CTRL5_C
1596 * @retval interface status (MANDATORY: return 0 -> no Error).
1597 *
1598 */
lsm6dso32x_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_rounding_t * val)1599 int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx,
1600 lsm6dso32x_rounding_t *val)
1601 {
1602 lsm6dso32x_ctrl5_c_t reg;
1603 int32_t ret;
1604
1605 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1606
1607 switch (reg.rounding)
1608 {
1609 case LSM6DSO32X_NO_ROUND:
1610 *val = LSM6DSO32X_NO_ROUND;
1611 break;
1612
1613 case LSM6DSO32X_ROUND_XL:
1614 *val = LSM6DSO32X_ROUND_XL;
1615 break;
1616
1617 case LSM6DSO32X_ROUND_GY:
1618 *val = LSM6DSO32X_ROUND_GY;
1619 break;
1620
1621 case LSM6DSO32X_ROUND_GY_XL:
1622 *val = LSM6DSO32X_ROUND_GY_XL;
1623 break;
1624
1625 default:
1626 *val = LSM6DSO32X_NO_ROUND;
1627 break;
1628 }
1629
1630 return ret;
1631 }
1632
1633 /**
1634 * @brief Temperature data output register (r).
1635 * L and H registers together express a 16-bit word in two’s
1636 * complement.[get]
1637 *
1638 * @param ctx read / write interface definitions
1639 * @param buff buffer that stores data read
1640 * @retval interface status (MANDATORY: return 0 -> no Error).
1641 *
1642 */
lsm6dso32x_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1643 int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx,
1644 int16_t *val)
1645 {
1646 uint8_t buff[2];
1647 int32_t ret;
1648
1649 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 2);
1650 *val = (int16_t)buff[1];
1651 *val = (*val * 256) + (int16_t)buff[0];
1652
1653 return ret;
1654 }
1655
1656 /**
1657 * @brief Angular rate sensor. The value is expressed as a 16-bit
1658 * word in two’s complement.[get]
1659 *
1660 * @param ctx read / write interface definitions
1661 * @param buff buffer that stores data read
1662 * @retval interface status (MANDATORY: return 0 -> no Error).
1663 *
1664 */
lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1665 int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1666 int16_t *val)
1667 {
1668 uint8_t buff[6];
1669 int32_t ret;
1670
1671 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_G, buff, 6);
1672 val[0] = (int16_t)buff[1];
1673 val[0] = (val[0] * 256) + (int16_t)buff[0];
1674 val[1] = (int16_t)buff[3];
1675 val[1] = (val[1] * 256) + (int16_t)buff[2];
1676 val[2] = (int16_t)buff[5];
1677 val[2] = (val[2] * 256) + (int16_t)buff[4];
1678
1679 return ret;
1680 }
1681
1682 /**
1683 * @brief Linear acceleration output register.
1684 * The value is expressed as a 16-bit word in two’s complement.[get]
1685 *
1686 * @param ctx read / write interface definitions
1687 * @param buff buffer that stores data read
1688 * @retval interface status (MANDATORY: return 0 -> no Error).
1689 *
1690 */
lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1691 int32_t lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t *ctx,
1692 int16_t *val)
1693 {
1694 uint8_t buff[6];
1695 int32_t ret;
1696
1697 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_A, buff, 6);
1698 val[0] = (int16_t)buff[1];
1699 val[0] = (val[0] * 256) + (int16_t)buff[0];
1700 val[1] = (int16_t)buff[3];
1701 val[1] = (val[1] * 256) + (int16_t)buff[2];
1702 val[2] = (int16_t)buff[5];
1703 val[2] = (val[2] * 256) + (int16_t)buff[4];
1704
1705 return ret;
1706 }
1707
1708 /**
1709 * @brief FIFO data output [get]
1710 *
1711 * @param ctx read / write interface definitions
1712 * @param buff buffer that stores data read
1713 * @retval interface status (MANDATORY: return 0 -> no Error).
1714 *
1715 */
lsm6dso32x_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1716 int32_t lsm6dso32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1717 {
1718 int32_t ret;
1719
1720 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_X_L, buff, 6);
1721
1722 return ret;
1723 }
1724
1725 /**
1726 * @brief Step counter output register.[get]
1727 *
1728 * @param ctx read / write interface definitions
1729 * @param buff buffer that stores data read
1730 * @retval interface status (MANDATORY: return 0 -> no Error).
1731 *
1732 */
lsm6dso32x_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1733 int32_t lsm6dso32x_number_of_steps_get(const stmdev_ctx_t *ctx,
1734 uint16_t *val)
1735 {
1736 uint8_t buff[2];
1737 int32_t ret;
1738
1739 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1740
1741 if (ret == 0)
1742 {
1743 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STEP_COUNTER_L, buff, 2);
1744 *val = buff[1];
1745 *val = (*val * 256U) + buff[0];
1746 }
1747
1748 if (ret == 0)
1749 {
1750 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1751 }
1752
1753 return ret;
1754 }
1755
1756 /**
1757 * @brief Reset step counter register.[get]
1758 *
1759 * @param ctx read / write interface definitions
1760 * @retval interface status (MANDATORY: return 0 -> no Error).
1761 *
1762 */
lsm6dso32x_steps_reset(const stmdev_ctx_t * ctx)1763 int32_t lsm6dso32x_steps_reset(const stmdev_ctx_t *ctx)
1764 {
1765 lsm6dso32x_emb_func_src_t reg;
1766 int32_t ret;
1767
1768 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1769
1770 if (ret == 0)
1771 {
1772 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
1773 (uint8_t *)®, 1);
1774 }
1775
1776 if (ret == 0)
1777 {
1778 reg.pedo_rst_step = PROPERTY_ENABLE;
1779 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
1780 (uint8_t *)®, 1);
1781 }
1782
1783 if (ret == 0)
1784 {
1785 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1786 }
1787
1788 return ret;
1789 }
1790
1791 /**
1792 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
1793 *
1794 * @param ctx_t *ctx: read / write interface definitions
1795 * @param uint8_t * : buffer that stores data read
1796 * @retval interface status (MANDATORY: return 0 -> no Error).
1797 *
1798 */
lsm6dso32x_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)1799 int32_t lsm6dso32x_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1800 {
1801 int32_t ret;
1802
1803 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1804
1805 if (ret == 0)
1806 {
1807 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC0_SRC, buff, 8);
1808 }
1809
1810 if (ret == 0)
1811 {
1812 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1813 }
1814
1815 return ret;
1816 }
1817
1818 /**
1819 * @}
1820 *
1821 */
1822
1823 /**
1824 * @defgroup LSM6DSO32X_common
1825 * @brief This section groups common useful functions.
1826 * @{
1827 *
1828 */
1829
1830 /**
1831 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1832 * with respect to the typical.
1833 * Step: 0.15%. 8-bit format, 2's complement.[set]
1834 *
1835 * @param ctx read / write interface definitions
1836 * @param val change the values of freq_fine in reg
1837 * INTERNAL_FREQ_FINE
1838 * @retval interface status (MANDATORY: return 0 -> no Error).
1839 *
1840 */
lsm6dso32x_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1841 int32_t lsm6dso32x_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1842 {
1843 lsm6dso32x_internal_freq_fine_t reg;
1844 int32_t ret;
1845
1846 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1847 (uint8_t *)®, 1);
1848
1849 if (ret == 0)
1850 {
1851 reg.freq_fine = val;
1852 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1853 (uint8_t *)®, 1);
1854 }
1855
1856 return ret;
1857 }
1858
1859 /**
1860 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1861 * with respect to the typical.
1862 * Step: 0.15%. 8-bit format, 2's complement.[get]
1863 *
1864 * @param ctx read / write interface definitions
1865 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
1866 * @retval interface status (MANDATORY: return 0 -> no Error).
1867 *
1868 */
lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1869 int32_t lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1870 {
1871 lsm6dso32x_internal_freq_fine_t reg;
1872 int32_t ret;
1873
1874 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1875 (uint8_t *)®, 1);
1876 *val = reg.freq_fine;
1877
1878 return ret;
1879 }
1880
1881
1882 /**
1883 * @brief Enable access to the embedded functions/sensor
1884 * hub configuration registers.[set]
1885 *
1886 * @param ctx read / write interface definitions
1887 * @param val change the values of reg_access in
1888 * reg FUNC_CFG_ACCESS
1889 * @retval interface status (MANDATORY: return 0 -> no Error).
1890 *
1891 */
lsm6dso32x_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dso32x_reg_access_t val)1892 int32_t lsm6dso32x_mem_bank_set(const stmdev_ctx_t *ctx,
1893 lsm6dso32x_reg_access_t val)
1894 {
1895 lsm6dso32x_func_cfg_access_t reg;
1896 int32_t ret;
1897
1898 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1899 (uint8_t *)®, 1);
1900
1901 if (ret == 0)
1902 {
1903 reg.reg_access = (uint8_t)val;
1904 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1905 (uint8_t *)®, 1);
1906 }
1907
1908 return ret;
1909 }
1910
1911 /**
1912 * @brief Enable access to the embedded functions/sensor
1913 * hub configuration registers.[get]
1914 *
1915 * @param ctx read / write interface definitions
1916 * @param val Get the values of reg_access in
1917 * reg FUNC_CFG_ACCESS
1918 * @retval interface status (MANDATORY: return 0 -> no Error).
1919 *
1920 */
lsm6dso32x_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dso32x_reg_access_t * val)1921 int32_t lsm6dso32x_mem_bank_get(const stmdev_ctx_t *ctx,
1922 lsm6dso32x_reg_access_t *val)
1923 {
1924 lsm6dso32x_func_cfg_access_t reg;
1925 int32_t ret;
1926
1927 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1928 (uint8_t *)®, 1);
1929
1930 switch (reg.reg_access)
1931 {
1932 case LSM6DSO32X_USER_BANK:
1933 *val = LSM6DSO32X_USER_BANK;
1934 break;
1935
1936 case LSM6DSO32X_SENSOR_HUB_BANK:
1937 *val = LSM6DSO32X_SENSOR_HUB_BANK;
1938 break;
1939
1940 case LSM6DSO32X_EMBEDDED_FUNC_BANK:
1941 *val = LSM6DSO32X_EMBEDDED_FUNC_BANK;
1942 break;
1943
1944 default:
1945 *val = LSM6DSO32X_USER_BANK;
1946 break;
1947 }
1948
1949 return ret;
1950 }
1951
1952 /**
1953 * @brief Write a line(byte) in a page.[set]
1954 *
1955 * @param ctx read / write interface definitions
1956 * @param uint8_t address: page line address
1957 * @param val value to write
1958 * @retval interface status (MANDATORY: return 0 -> no Error).
1959 *
1960 */
lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1961 int32_t lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t *ctx,
1962 uint16_t address,
1963 uint8_t *val)
1964 {
1965 lsm6dso32x_page_rw_t page_rw;
1966 lsm6dso32x_page_sel_t page_sel;
1967 lsm6dso32x_page_address_t page_address;
1968 int32_t ret;
1969
1970 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1971
1972 if (ret == 0)
1973 {
1974 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
1975 (uint8_t *) &page_rw, 1);
1976 }
1977
1978 if (ret == 0)
1979 {
1980 page_rw.page_rw = 0x02; /* page_write enable */
1981 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
1982 (uint8_t *) &page_rw, 1);
1983 }
1984
1985 if (ret == 0)
1986 {
1987 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
1988 (uint8_t *) &page_sel, 1);
1989 }
1990
1991 if (ret == 0)
1992 {
1993 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1994 page_sel.not_used_01 = 1;
1995 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
1996 (uint8_t *) &page_sel, 1);
1997 }
1998
1999 if (ret == 0)
2000 {
2001 page_address.page_addr = (uint8_t)address & 0xFFU;
2002 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
2003 (uint8_t *)&page_address, 1);
2004 }
2005
2006 if (ret == 0)
2007 {
2008 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
2009 }
2010
2011 if (ret == 0)
2012 {
2013 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2014 (uint8_t *) &page_rw, 1);
2015 }
2016
2017 if (ret == 0)
2018 {
2019 page_rw.page_rw = 0x00; /* page_write disable */
2020 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2021 (uint8_t *) &page_rw, 1);
2022 }
2023
2024 if (ret == 0)
2025 {
2026 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2027 }
2028
2029 return ret;
2030 }
2031
2032 /**
2033 * @brief Write buffer in a page.[set]
2034 *
2035 * @param ctx read / write interface definitions
2036 * @param uint8_t address: page line address
2037 * @param uint8_t *buf: buffer to write
2038 * @param uint8_t len: buffer len
2039 * @retval interface status (MANDATORY: return 0 -> no Error).
2040 *
2041 */
lsm6dso32x_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2042 int32_t lsm6dso32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
2043 uint8_t *buf, uint8_t len)
2044 {
2045 lsm6dso32x_page_rw_t page_rw;
2046 lsm6dso32x_page_sel_t page_sel;
2047 lsm6dso32x_page_address_t page_address;
2048 int32_t ret;
2049
2050 uint8_t msb, lsb;
2051 uint8_t i ;
2052 msb = ((uint8_t)(address >> 8) & 0x0FU);
2053 lsb = (uint8_t)address & 0xFFU;
2054 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
2055
2056 if (ret == 0)
2057 {
2058 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2059 (uint8_t *) &page_rw, 1);
2060 }
2061
2062 if (ret == 0)
2063 {
2064 page_rw.page_rw = 0x02; /* page_write enable*/
2065 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2066 (uint8_t *) &page_rw, 1);
2067 }
2068
2069 if (ret == 0)
2070 {
2071 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2072 (uint8_t *) &page_sel, 1);
2073 }
2074
2075 if (ret == 0)
2076 {
2077 page_sel.page_sel = msb;
2078 page_sel.not_used_01 = 1;
2079 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2080 (uint8_t *) &page_sel, 1);
2081 }
2082
2083 if (ret == 0)
2084 {
2085 page_address.page_addr = lsb;
2086 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
2087 (uint8_t *)&page_address, 1);
2088 }
2089
2090 if (ret == 0)
2091 {
2092 for (i = 0; ((i < len) && (ret == 0)); i++)
2093 {
2094 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, &buf[i], 1);
2095 lsb++;
2096
2097 /* Check if page wrap */
2098 if ((lsb == 0x00U) && (ret == 0))
2099 {
2100 msb++;
2101 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2102 (uint8_t *)&page_sel, 1);
2103
2104 if (ret == 0)
2105 {
2106 page_sel.page_sel = msb;
2107 page_sel.not_used_01 = 1;
2108 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2109 (uint8_t *)&page_sel, 1);
2110 }
2111 }
2112 }
2113 }
2114
2115 page_sel.page_sel = 0;
2116 page_sel.not_used_01 = 1;
2117 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2118 (uint8_t *) &page_sel, 1);
2119
2120 if (ret == 0)
2121 {
2122 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2123 (uint8_t *) &page_rw, 1);
2124 }
2125
2126 if (ret == 0)
2127 {
2128 page_rw.page_rw = 0x00; /* page_write disable */
2129 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2130 (uint8_t *) &page_rw, 1);
2131 }
2132
2133 if (ret == 0)
2134 {
2135 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2136 }
2137
2138 return ret;
2139 }
2140
2141 /**
2142 * @brief Read a line(byte) in a page.[get]
2143 *
2144 * @param ctx read / write interface definitions
2145 * @param uint8_t address: page line address
2146 * @param val read value
2147 * @retval interface status (MANDATORY: return 0 -> no Error).
2148 *
2149 */
lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)2150 int32_t lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t *ctx,
2151 uint16_t address,
2152 uint8_t *val)
2153 {
2154 lsm6dso32x_page_rw_t page_rw;
2155 lsm6dso32x_page_sel_t page_sel;
2156 lsm6dso32x_page_address_t page_address;
2157 int32_t ret;
2158
2159 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
2160
2161 if (ret == 0)
2162 {
2163 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2164 (uint8_t *) &page_rw, 1);
2165 }
2166
2167 if (ret == 0)
2168 {
2169 page_rw.page_rw = 0x01; /* page_read enable*/
2170 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2171 (uint8_t *) &page_rw, 1);
2172 }
2173
2174 if (ret == 0)
2175 {
2176 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2177 (uint8_t *) &page_sel, 1);
2178 }
2179
2180 if (ret == 0)
2181 {
2182 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
2183 page_sel.not_used_01 = 1;
2184 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2185 (uint8_t *) &page_sel, 1);
2186 }
2187
2188 if (ret == 0)
2189 {
2190 page_address.page_addr = (uint8_t)address & 0x00FFU;
2191 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
2192 (uint8_t *)&page_address, 1);
2193 }
2194
2195 if (ret == 0)
2196 {
2197 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
2198 }
2199
2200 if (ret == 0)
2201 {
2202 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2203 (uint8_t *) &page_rw, 1);
2204 }
2205
2206 if (ret == 0)
2207 {
2208 page_rw.page_rw = 0x00; /* page_read disable */
2209 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2210 (uint8_t *) &page_rw, 1);
2211 }
2212
2213 if (ret == 0)
2214 {
2215 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2216 }
2217
2218 return ret;
2219 }
2220
2221 /**
2222 * @brief Data-ready pulsed / letched mode.[set]
2223 *
2224 * @param ctx read / write interface definitions
2225 * @param val change the values of
2226 * dataready_pulsed in
2227 * reg COUNTER_BDR_REG1
2228 * @retval interface status (MANDATORY: return 0 -> no Error).
2229 *
2230 */
lsm6dso32x_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_dataready_pulsed_t val)2231 int32_t lsm6dso32x_data_ready_mode_set(const stmdev_ctx_t *ctx,
2232 lsm6dso32x_dataready_pulsed_t val)
2233 {
2234 lsm6dso32x_counter_bdr_reg1_t reg;
2235 int32_t ret;
2236
2237 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2238 (uint8_t *)®, 1);
2239
2240 if (ret == 0)
2241 {
2242 reg.dataready_pulsed = (uint8_t)val;
2243 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2244 (uint8_t *)®, 1);
2245 }
2246
2247 return ret;
2248 }
2249
2250 /**
2251 * @brief Data-ready pulsed / letched mode.[get]
2252 *
2253 * @param ctx read / write interface definitions
2254 * @param val Get the values of
2255 * dataready_pulsed in
2256 * reg COUNTER_BDR_REG1
2257 * @retval interface status (MANDATORY: return 0 -> no Error).
2258 *
2259 */
lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_dataready_pulsed_t * val)2260 int32_t lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t *ctx,
2261 lsm6dso32x_dataready_pulsed_t *val)
2262 {
2263 lsm6dso32x_counter_bdr_reg1_t reg;
2264 int32_t ret;
2265
2266 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2267 (uint8_t *)®, 1);
2268
2269 switch (reg.dataready_pulsed)
2270 {
2271 case LSM6DSO32X_DRDY_LATCHED:
2272 *val = LSM6DSO32X_DRDY_LATCHED;
2273 break;
2274
2275 case LSM6DSO32X_DRDY_PULSED:
2276 *val = LSM6DSO32X_DRDY_PULSED;
2277 break;
2278
2279 default:
2280 *val = LSM6DSO32X_DRDY_LATCHED;
2281 break;
2282 }
2283
2284 return ret;
2285 }
2286
2287 /**
2288 * @brief Device "Who am I".[get]
2289 *
2290 * @param ctx read / write interface definitions
2291 * @param buff buffer that stores data read
2292 * @retval interface status (MANDATORY: return 0 -> no Error).
2293 *
2294 */
lsm6dso32x_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2295 int32_t lsm6dso32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2296 {
2297 int32_t ret;
2298
2299 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I, buff, 1);
2300
2301 return ret;
2302 }
2303
2304 /**
2305 * @brief Software reset. Restore the default values
2306 * in user registers[set]
2307 *
2308 * @param ctx read / write interface definitions
2309 * @param val change the values of sw_reset in reg CTRL3_C
2310 * @retval interface status (MANDATORY: return 0 -> no Error).
2311 *
2312 */
lsm6dso32x_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2313 int32_t lsm6dso32x_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2314 {
2315 lsm6dso32x_ctrl3_c_t reg;
2316 int32_t ret;
2317
2318 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2319
2320 if (ret == 0)
2321 {
2322 reg.sw_reset = val;
2323 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2324 }
2325
2326 return ret;
2327 }
2328
2329 /**
2330 * @brief Software reset. Restore the default values in user registers.[get]
2331 *
2332 * @param ctx read / write interface definitions
2333 * @param val change the values of sw_reset in reg CTRL3_C
2334 * @retval interface status (MANDATORY: return 0 -> no Error).
2335 *
2336 */
lsm6dso32x_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2337 int32_t lsm6dso32x_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2338 {
2339 lsm6dso32x_ctrl3_c_t reg;
2340 int32_t ret;
2341
2342 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2343 *val = reg.sw_reset;
2344
2345 return ret;
2346 }
2347
2348 /**
2349 * @brief Register address automatically incremented during a multiple byte
2350 * access with a serial interface.[set]
2351 *
2352 * @param ctx read / write interface definitions
2353 * @param val change the values of if_inc in reg CTRL3_C
2354 * @retval interface status (MANDATORY: return 0 -> no Error).
2355 *
2356 */
lsm6dso32x_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2357 int32_t lsm6dso32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2358 {
2359 lsm6dso32x_ctrl3_c_t reg;
2360 int32_t ret;
2361
2362 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2363
2364 if (ret == 0)
2365 {
2366 reg.if_inc = val;
2367 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2368 }
2369
2370 return ret;
2371 }
2372
2373 /**
2374 * @brief Register address automatically incremented during a multiple byte
2375 * access with a serial interface.[get]
2376 *
2377 * @param ctx read / write interface definitions
2378 * @param val change the values of if_inc in reg CTRL3_C
2379 * @retval interface status (MANDATORY: return 0 -> no Error).
2380 *
2381 */
lsm6dso32x_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2382 int32_t lsm6dso32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2383 {
2384 lsm6dso32x_ctrl3_c_t reg;
2385 int32_t ret;
2386
2387 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2388 *val = reg.if_inc;
2389
2390 return ret;
2391 }
2392
2393 /**
2394 * @brief Reboot memory content. Reload the calibration parameters.[set]
2395 *
2396 * @param ctx read / write interface definitions
2397 * @param val change the values of boot in reg CTRL3_C
2398 * @retval interface status (MANDATORY: return 0 -> no Error).
2399 *
2400 */
lsm6dso32x_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2401 int32_t lsm6dso32x_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2402 {
2403 lsm6dso32x_ctrl3_c_t reg;
2404 int32_t ret;
2405
2406 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2407
2408 if (ret == 0)
2409 {
2410 reg.boot = val;
2411 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2412 }
2413
2414 return ret;
2415 }
2416
2417 /**
2418 * @brief Reboot memory content. Reload the calibration parameters.[get]
2419 *
2420 * @param ctx read / write interface definitions
2421 * @param val change the values of boot in reg CTRL3_C
2422 * @retval interface status (MANDATORY: return 0 -> no Error).
2423 *
2424 */
lsm6dso32x_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2425 int32_t lsm6dso32x_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2426 {
2427 lsm6dso32x_ctrl3_c_t reg;
2428 int32_t ret;
2429
2430 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2431 *val = reg.boot;
2432
2433 return ret;
2434 }
2435
2436 /**
2437 * @brief Linear acceleration sensor self-test enable.[set]
2438 *
2439 * @param ctx read / write interface definitions
2440 * @param val change the values of st_xl in reg CTRL5_C
2441 * @retval interface status (MANDATORY: return 0 -> no Error).
2442 *
2443 */
lsm6dso32x_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dso32x_st_xl_t val)2444 int32_t lsm6dso32x_xl_self_test_set(const stmdev_ctx_t *ctx,
2445 lsm6dso32x_st_xl_t val)
2446 {
2447 lsm6dso32x_ctrl5_c_t reg;
2448 int32_t ret;
2449
2450 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2451
2452 if (ret == 0)
2453 {
2454 reg.st_xl = (uint8_t)val;
2455 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * @brief Linear acceleration sensor self-test enable.[get]
2463 *
2464 * @param ctx read / write interface definitions
2465 * @param val Get the values of st_xl in reg CTRL5_C
2466 * @retval interface status (MANDATORY: return 0 -> no Error).
2467 *
2468 */
lsm6dso32x_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dso32x_st_xl_t * val)2469 int32_t lsm6dso32x_xl_self_test_get(const stmdev_ctx_t *ctx,
2470 lsm6dso32x_st_xl_t *val)
2471 {
2472 lsm6dso32x_ctrl5_c_t reg;
2473 int32_t ret;
2474
2475 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2476
2477 switch (reg.st_xl)
2478 {
2479 case LSM6DSO32X_XL_ST_DISABLE:
2480 *val = LSM6DSO32X_XL_ST_DISABLE;
2481 break;
2482
2483 case LSM6DSO32X_XL_ST_POSITIVE:
2484 *val = LSM6DSO32X_XL_ST_POSITIVE;
2485 break;
2486
2487 case LSM6DSO32X_XL_ST_NEGATIVE:
2488 *val = LSM6DSO32X_XL_ST_NEGATIVE;
2489 break;
2490
2491 default:
2492 *val = LSM6DSO32X_XL_ST_DISABLE;
2493 break;
2494 }
2495
2496 return ret;
2497 }
2498
2499 /**
2500 * @brief Angular rate sensor self-test enable.[set]
2501 *
2502 * @param ctx read / write interface definitions
2503 * @param val change the values of st_g in reg CTRL5_C
2504 * @retval interface status (MANDATORY: return 0 -> no Error).
2505 *
2506 */
lsm6dso32x_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dso32x_st_g_t val)2507 int32_t lsm6dso32x_gy_self_test_set(const stmdev_ctx_t *ctx,
2508 lsm6dso32x_st_g_t val)
2509 {
2510 lsm6dso32x_ctrl5_c_t reg;
2511 int32_t ret;
2512
2513 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2514
2515 if (ret == 0)
2516 {
2517 reg.st_g = (uint8_t)val;
2518 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2519 }
2520
2521 return ret;
2522 }
2523
2524 /**
2525 * @brief Angular rate sensor self-test enable.[get]
2526 *
2527 * @param ctx read / write interface definitions
2528 * @param val Get the values of st_g in reg CTRL5_C
2529 * @retval interface status (MANDATORY: return 0 -> no Error).
2530 *
2531 */
lsm6dso32x_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dso32x_st_g_t * val)2532 int32_t lsm6dso32x_gy_self_test_get(const stmdev_ctx_t *ctx,
2533 lsm6dso32x_st_g_t *val)
2534 {
2535 lsm6dso32x_ctrl5_c_t reg;
2536 int32_t ret;
2537
2538 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2539
2540 switch (reg.st_g)
2541 {
2542 case LSM6DSO32X_GY_ST_DISABLE:
2543 *val = LSM6DSO32X_GY_ST_DISABLE;
2544 break;
2545
2546 case LSM6DSO32X_GY_ST_POSITIVE:
2547 *val = LSM6DSO32X_GY_ST_POSITIVE;
2548 break;
2549
2550 case LSM6DSO32X_GY_ST_NEGATIVE:
2551 *val = LSM6DSO32X_GY_ST_NEGATIVE;
2552 break;
2553
2554 default:
2555 *val = LSM6DSO32X_GY_ST_DISABLE;
2556 break;
2557 }
2558
2559 return ret;
2560 }
2561
2562 /**
2563 * @}
2564 *
2565 */
2566
2567 /**
2568 * @defgroup LSM6DSO32X_filters
2569 * @brief This section group all the functions concerning the
2570 * filters configuration
2571 * @{
2572 *
2573 */
2574
2575 /**
2576 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2577 *
2578 * @param ctx read / write interface definitions
2579 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2580 * @retval interface status (MANDATORY: return 0 -> no Error).
2581 *
2582 */
lsm6dso32x_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2583 int32_t lsm6dso32x_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2584 {
2585 lsm6dso32x_ctrl1_xl_t reg;
2586 int32_t ret;
2587
2588 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2589
2590 if (ret == 0)
2591 {
2592 reg.lpf2_xl_en = val;
2593 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2594 }
2595
2596 return ret;
2597 }
2598
2599 /**
2600 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2601 *
2602 * @param ctx read / write interface definitions
2603 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2604 * @retval interface status (MANDATORY: return 0 -> no Error).
2605 *
2606 */
lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2607 int32_t lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2608 {
2609 lsm6dso32x_ctrl1_xl_t reg;
2610 int32_t ret;
2611
2612 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2613 *val = reg.lpf2_xl_en;
2614
2615 return ret;
2616 }
2617
2618 /**
2619 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2620 * the bandwidth can be selected through FTYPE [2:0]
2621 * in CTRL6_C (15h).[set]
2622 *
2623 * @param ctx read / write interface definitions
2624 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2625 * @retval interface status (MANDATORY: return 0 -> no Error).
2626 *
2627 */
lsm6dso32x_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2628 int32_t lsm6dso32x_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2629 {
2630 lsm6dso32x_ctrl4_c_t reg;
2631 int32_t ret;
2632
2633 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2634
2635 if (ret == 0)
2636 {
2637 reg.lpf1_sel_g = val;
2638 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2639 }
2640
2641 return ret;
2642 }
2643
2644 /**
2645 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2646 * the bandwidth can be selected through FTYPE [2:0]
2647 * in CTRL6_C (15h).[get]
2648 *
2649 * @param ctx read / write interface definitions
2650 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2651 * @retval interface status (MANDATORY: return 0 -> no Error).
2652 *
2653 */
lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2654 int32_t lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2655 {
2656 lsm6dso32x_ctrl4_c_t reg;
2657 int32_t ret;
2658
2659 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2660 *val = reg.lpf1_sel_g;
2661
2662 return ret;
2663 }
2664
2665 /**
2666 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2667 * (XL and Gyro independently masked).[set]
2668 *
2669 * @param ctx read / write interface definitions
2670 * @param val change the values of drdy_mask in reg CTRL4_C
2671 * @retval interface status (MANDATORY: return 0 -> no Error).
2672 *
2673 */
lsm6dso32x_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2674 int32_t lsm6dso32x_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2675 uint8_t val)
2676 {
2677 lsm6dso32x_ctrl4_c_t reg;
2678 int32_t ret;
2679
2680 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2681
2682 if (ret == 0)
2683 {
2684 reg.drdy_mask = val;
2685 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2686 }
2687
2688 return ret;
2689 }
2690
2691 /**
2692 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2693 * (XL and Gyro independently masked).[get]
2694 *
2695 * @param ctx read / write interface definitions
2696 * @param val change the values of drdy_mask in reg CTRL4_C
2697 * @retval interface status (MANDATORY: return 0 -> no Error).
2698 *
2699 */
lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2700 int32_t lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2701 uint8_t *val)
2702 {
2703 lsm6dso32x_ctrl4_c_t reg;
2704 int32_t ret;
2705
2706 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2707 *val = reg.drdy_mask;
2708
2709 return ret;
2710 }
2711
2712 /**
2713 * @brief Gyroscope lp1 bandwidth.[set]
2714 *
2715 * @param ctx read / write interface definitions
2716 * @param val change the values of ftype in reg CTRL6_C
2717 * @retval interface status (MANDATORY: return 0 -> no Error).
2718 *
2719 */
lsm6dso32x_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso32x_ftype_t val)2720 int32_t lsm6dso32x_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2721 lsm6dso32x_ftype_t val)
2722 {
2723 lsm6dso32x_ctrl6_c_t reg;
2724 int32_t ret;
2725
2726 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2727
2728 if (ret == 0)
2729 {
2730 reg.ftype = (uint8_t)val;
2731 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2732 }
2733
2734 return ret;
2735 }
2736
2737 /**
2738 * @brief Gyroscope lp1 bandwidth.[get]
2739 *
2740 * @param ctx read / write interface definitions
2741 * @param val Get the values of ftype in reg CTRL6_C
2742 * @retval interface status (MANDATORY: return 0 -> no Error).
2743 *
2744 */
lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso32x_ftype_t * val)2745 int32_t lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2746 lsm6dso32x_ftype_t *val)
2747 {
2748 lsm6dso32x_ctrl6_c_t reg;
2749 int32_t ret;
2750
2751 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2752
2753 switch (reg.ftype)
2754 {
2755 case LSM6DSO32X_ULTRA_LIGHT:
2756 *val = LSM6DSO32X_ULTRA_LIGHT;
2757 break;
2758
2759 case LSM6DSO32X_VERY_LIGHT:
2760 *val = LSM6DSO32X_VERY_LIGHT;
2761 break;
2762
2763 case LSM6DSO32X_LIGHT:
2764 *val = LSM6DSO32X_LIGHT;
2765 break;
2766
2767 case LSM6DSO32X_MEDIUM:
2768 *val = LSM6DSO32X_MEDIUM;
2769 break;
2770
2771 case LSM6DSO32X_STRONG:
2772 *val = LSM6DSO32X_STRONG;
2773 break;
2774
2775 case LSM6DSO32X_VERY_STRONG:
2776 *val = LSM6DSO32X_VERY_STRONG;
2777 break;
2778
2779 case LSM6DSO32X_AGGRESSIVE:
2780 *val = LSM6DSO32X_AGGRESSIVE;
2781 break;
2782
2783 case LSM6DSO32X_XTREME:
2784 *val = LSM6DSO32X_XTREME;
2785 break;
2786
2787 default:
2788 *val = LSM6DSO32X_ULTRA_LIGHT;
2789 break;
2790 }
2791
2792 return ret;
2793 }
2794
2795 /**
2796 * @brief Low pass filter 2 on 6D function selection.[set]
2797 *
2798 * @param ctx read / write interface definitions
2799 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2800 * @retval interface status (MANDATORY: return 0 -> no Error).
2801 *
2802 */
lsm6dso32x_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2803 int32_t lsm6dso32x_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2804 {
2805 lsm6dso32x_ctrl8_xl_t reg;
2806 int32_t ret;
2807
2808 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2809
2810 if (ret == 0)
2811 {
2812 reg.low_pass_on_6d = val;
2813 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2814 }
2815
2816 return ret;
2817 }
2818
2819 /**
2820 * @brief Low pass filter 2 on 6D function selection.[get]
2821 *
2822 * @param ctx read / write interface definitions
2823 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2824 * @retval interface status (MANDATORY: return 0 -> no Error).
2825 *
2826 */
lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2827 int32_t lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2828 {
2829 lsm6dso32x_ctrl8_xl_t reg;
2830 int32_t ret;
2831
2832 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2833 *val = reg.low_pass_on_6d;
2834
2835 return ret;
2836 }
2837
2838 /**
2839 * @brief Accelerometer slope filter / high-pass filter selection
2840 * on output.[set]
2841 *
2842 * @param ctx read / write interface definitions
2843 * @param val change the values of hp_slope_xl_en
2844 * in reg CTRL8_XL
2845 * @retval interface status (MANDATORY: return 0 -> no Error).
2846 *
2847 */
lsm6dso32x_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dso32x_hp_slope_xl_en_t val)2848 int32_t lsm6dso32x_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2849 lsm6dso32x_hp_slope_xl_en_t val)
2850 {
2851 lsm6dso32x_ctrl8_xl_t reg;
2852 int32_t ret;
2853
2854 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2855
2856 if (ret == 0)
2857 {
2858 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2859 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2860 reg.hpcf_xl = (uint8_t)val & 0x07U;
2861 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2862 }
2863
2864 return ret;
2865 }
2866
2867 /**
2868 * @brief Accelerometer slope filter / high-pass filter selection
2869 * on output.[get]
2870 *
2871 * @param ctx read / write interface definitions
2872 * @param val Get the values of hp_slope_xl_en
2873 * in reg CTRL8_XL
2874 * @retval interface status (MANDATORY: return 0 -> no Error).
2875 *
2876 */
lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dso32x_hp_slope_xl_en_t * val)2877 int32_t lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2878 lsm6dso32x_hp_slope_xl_en_t *val)
2879 {
2880 lsm6dso32x_ctrl8_xl_t reg;
2881 int32_t ret;
2882
2883 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2884
2885 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2886 reg.hpcf_xl)
2887 {
2888 case LSM6DSO32X_HP_PATH_DISABLE_ON_OUT:
2889 *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
2890 break;
2891
2892 case LSM6DSO32X_SLOPE_ODR_DIV_4:
2893 *val = LSM6DSO32X_SLOPE_ODR_DIV_4;
2894 break;
2895
2896 case LSM6DSO32X_HP_ODR_DIV_10:
2897 *val = LSM6DSO32X_HP_ODR_DIV_10;
2898 break;
2899
2900 case LSM6DSO32X_HP_ODR_DIV_20:
2901 *val = LSM6DSO32X_HP_ODR_DIV_20;
2902 break;
2903
2904 case LSM6DSO32X_HP_ODR_DIV_45:
2905 *val = LSM6DSO32X_HP_ODR_DIV_45;
2906 break;
2907
2908 case LSM6DSO32X_HP_ODR_DIV_100:
2909 *val = LSM6DSO32X_HP_ODR_DIV_100;
2910 break;
2911
2912 case LSM6DSO32X_HP_ODR_DIV_200:
2913 *val = LSM6DSO32X_HP_ODR_DIV_200;
2914 break;
2915
2916 case LSM6DSO32X_HP_ODR_DIV_400:
2917 *val = LSM6DSO32X_HP_ODR_DIV_400;
2918 break;
2919
2920 case LSM6DSO32X_HP_ODR_DIV_800:
2921 *val = LSM6DSO32X_HP_ODR_DIV_800;
2922 break;
2923
2924 case LSM6DSO32X_HP_REF_MD_ODR_DIV_10:
2925 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_10;
2926 break;
2927
2928 case LSM6DSO32X_HP_REF_MD_ODR_DIV_20:
2929 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_20;
2930 break;
2931
2932 case LSM6DSO32X_HP_REF_MD_ODR_DIV_45:
2933 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_45;
2934 break;
2935
2936 case LSM6DSO32X_HP_REF_MD_ODR_DIV_100:
2937 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_100;
2938 break;
2939
2940 case LSM6DSO32X_HP_REF_MD_ODR_DIV_200:
2941 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_200;
2942 break;
2943
2944 case LSM6DSO32X_HP_REF_MD_ODR_DIV_400:
2945 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_400;
2946 break;
2947
2948 case LSM6DSO32X_HP_REF_MD_ODR_DIV_800:
2949 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_800;
2950 break;
2951
2952 case LSM6DSO32X_LP_ODR_DIV_10:
2953 *val = LSM6DSO32X_LP_ODR_DIV_10;
2954 break;
2955
2956 case LSM6DSO32X_LP_ODR_DIV_20:
2957 *val = LSM6DSO32X_LP_ODR_DIV_20;
2958 break;
2959
2960 case LSM6DSO32X_LP_ODR_DIV_45:
2961 *val = LSM6DSO32X_LP_ODR_DIV_45;
2962 break;
2963
2964 case LSM6DSO32X_LP_ODR_DIV_100:
2965 *val = LSM6DSO32X_LP_ODR_DIV_100;
2966 break;
2967
2968 case LSM6DSO32X_LP_ODR_DIV_200:
2969 *val = LSM6DSO32X_LP_ODR_DIV_200;
2970 break;
2971
2972 case LSM6DSO32X_LP_ODR_DIV_400:
2973 *val = LSM6DSO32X_LP_ODR_DIV_400;
2974 break;
2975
2976 case LSM6DSO32X_LP_ODR_DIV_800:
2977 *val = LSM6DSO32X_LP_ODR_DIV_800;
2978 break;
2979
2980 default:
2981 *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
2982 break;
2983 }
2984
2985 return ret;
2986 }
2987
2988 /**
2989 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2990 * The filter sets the second samples after writing this bit.
2991 * Active only during device exit from power-down mode.[set]
2992 *
2993 * @param ctx read / write interface definitions
2994 * @param val change the values of fastsettl_mode_xl in
2995 * reg CTRL8_XL
2996 * @retval interface status (MANDATORY: return 0 -> no Error).
2997 *
2998 */
lsm6dso32x_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2999 int32_t lsm6dso32x_xl_fast_settling_set(const stmdev_ctx_t *ctx,
3000 uint8_t val)
3001 {
3002 lsm6dso32x_ctrl8_xl_t reg;
3003 int32_t ret;
3004
3005 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
3006
3007 if (ret == 0)
3008 {
3009 reg.fastsettl_mode_xl = val;
3010 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
3011 }
3012
3013 return ret;
3014 }
3015
3016 /**
3017 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3018 * The filter sets the second samples after writing this bit.
3019 * Active only during device exit from power-down mode.[get]
3020 *
3021 * @param ctx read / write interface definitions
3022 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
3023 * @retval interface status (MANDATORY: return 0 -> no Error).
3024 *
3025 */
lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3026 int32_t lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t *ctx,
3027 uint8_t *val)
3028 {
3029 lsm6dso32x_ctrl8_xl_t reg;
3030 int32_t ret;
3031
3032 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
3033 *val = reg.fastsettl_mode_xl;
3034
3035 return ret;
3036 }
3037
3038 /**
3039 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3040 * functions.[set]
3041 *
3042 * @param ctx read / write interface definitions
3043 * @param val change the values of slope_fds in reg TAP_CFG0
3044 * @retval interface status (MANDATORY: return 0 -> no Error).
3045 *
3046 */
lsm6dso32x_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso32x_slope_fds_t val)3047 int32_t lsm6dso32x_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
3048 lsm6dso32x_slope_fds_t val)
3049 {
3050 lsm6dso32x_tap_cfg0_t reg;
3051 int32_t ret;
3052
3053 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3054
3055 if (ret == 0)
3056 {
3057 reg.slope_fds = (uint8_t)val;
3058 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3059 }
3060
3061 return ret;
3062 }
3063
3064 /**
3065 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3066 * functions.[get]
3067 *
3068 * @param ctx read / write interface definitions
3069 * @param val Change the values of slope_fds in reg TAP_CFG0
3070 * @retval interface status (MANDATORY: return 0 -> no Error).
3071 *
3072 */
lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso32x_slope_fds_t * val)3073 int32_t lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
3074 lsm6dso32x_slope_fds_t *val)
3075 {
3076 lsm6dso32x_tap_cfg0_t reg;
3077 int32_t ret;
3078
3079 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3080
3081 switch (reg.slope_fds)
3082 {
3083 case LSM6DSO32X_USE_SLOPE:
3084 *val = LSM6DSO32X_USE_SLOPE;
3085 break;
3086
3087 case LSM6DSO32X_USE_HPF:
3088 *val = LSM6DSO32X_USE_HPF;
3089 break;
3090
3091 default:
3092 *val = LSM6DSO32X_USE_SLOPE;
3093 break;
3094 }
3095
3096 return ret;
3097 }
3098
3099 /**
3100 * @brief Enables gyroscope digital high-pass filter. The filter is
3101 * enabled only if the gyro is in HP mode.[set]
3102 *
3103 * @param ctx read / write interface definitions
3104 * @param val Get the values of hp_en_g and hp_en_g
3105 * in reg CTRL7_G
3106 * @retval interface status (MANDATORY: return 0 -> no Error).
3107 *
3108 */
lsm6dso32x_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso32x_hpm_g_t val)3109 int32_t lsm6dso32x_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
3110 lsm6dso32x_hpm_g_t val)
3111 {
3112 lsm6dso32x_ctrl7_g_t reg;
3113 int32_t ret;
3114
3115 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3116
3117 if (ret == 0)
3118 {
3119 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
3120 reg.hpm_g = (uint8_t)val & 0x03U;
3121 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3122 }
3123
3124 return ret;
3125 }
3126
3127 /**
3128 * @brief Enables gyroscope digital high-pass filter. The filter is
3129 * enabled only if the gyro is in HP mode.[get]
3130 *
3131 * @param ctx read / write interface definitions
3132 * @param val Get the values of hp_en_g and hp_en_g
3133 * in reg CTRL7_G
3134 * @retval interface status (MANDATORY: return 0 -> no Error).
3135 *
3136 */
lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso32x_hpm_g_t * val)3137 int32_t lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
3138 lsm6dso32x_hpm_g_t *val)
3139 {
3140 lsm6dso32x_ctrl7_g_t reg;
3141 int32_t ret;
3142
3143 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3144
3145 switch ((reg.hp_en_g << 7) + reg.hpm_g)
3146 {
3147 case LSM6DSO32X_HP_FILTER_NONE:
3148 *val = LSM6DSO32X_HP_FILTER_NONE;
3149 break;
3150
3151 case LSM6DSO32X_HP_FILTER_16mHz:
3152 *val = LSM6DSO32X_HP_FILTER_16mHz;
3153 break;
3154
3155 case LSM6DSO32X_HP_FILTER_65mHz:
3156 *val = LSM6DSO32X_HP_FILTER_65mHz;
3157 break;
3158
3159 case LSM6DSO32X_HP_FILTER_260mHz:
3160 *val = LSM6DSO32X_HP_FILTER_260mHz;
3161 break;
3162
3163 case LSM6DSO32X_HP_FILTER_1Hz04:
3164 *val = LSM6DSO32X_HP_FILTER_1Hz04;
3165 break;
3166
3167 default:
3168 *val = LSM6DSO32X_HP_FILTER_NONE;
3169 break;
3170 }
3171
3172 return ret;
3173 }
3174
3175 /**
3176 * @}
3177 *
3178 */
3179
3180 /**
3181 * @defgroup LSM6DSO32X_ main_serial_interface
3182 * @brief This section groups all the functions concerning main
3183 * serial interface management (not auxiliary)
3184 * @{
3185 *
3186 */
3187
3188 /**
3189 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
3190 *
3191 * @param ctx read / write interface definitions
3192 * @param val change the values of sdo_pu_en in
3193 * reg PIN_CTRL
3194 * @retval interface status (MANDATORY: return 0 -> no Error).
3195 *
3196 */
lsm6dso32x_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_sdo_pu_en_t val)3197 int32_t lsm6dso32x_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
3198 lsm6dso32x_sdo_pu_en_t val)
3199 {
3200 lsm6dso32x_pin_ctrl_t reg;
3201 int32_t ret;
3202
3203 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3204
3205 if (ret == 0)
3206 {
3207 reg.sdo_pu_en = (uint8_t)val;
3208 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3209 }
3210
3211 return ret;
3212 }
3213
3214 /**
3215 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
3216 *
3217 * @param ctx read / write interface definitions
3218 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
3219 * @retval interface status (MANDATORY: return 0 -> no Error).
3220 *
3221 */
lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_sdo_pu_en_t * val)3222 int32_t lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
3223 lsm6dso32x_sdo_pu_en_t *val)
3224 {
3225 lsm6dso32x_pin_ctrl_t reg;
3226 int32_t ret;
3227
3228 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3229
3230 switch (reg.sdo_pu_en)
3231 {
3232 case LSM6DSO32X_PULL_UP_DISC:
3233 *val = LSM6DSO32X_PULL_UP_DISC;
3234 break;
3235
3236 case LSM6DSO32X_PULL_UP_CONNECT:
3237 *val = LSM6DSO32X_PULL_UP_CONNECT;
3238 break;
3239
3240 default:
3241 *val = LSM6DSO32X_PULL_UP_DISC;
3242 break;
3243 }
3244
3245 return ret;
3246 }
3247
3248 /**
3249 * @brief SPI Serial Interface Mode selection.[set]
3250 *
3251 * @param ctx read / write interface definitions
3252 * @param val change the values of sim in reg CTRL3_C
3253 * @retval interface status (MANDATORY: return 0 -> no Error).
3254 *
3255 */
lsm6dso32x_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_sim_t val)3256 int32_t lsm6dso32x_spi_mode_set(const stmdev_ctx_t *ctx,
3257 lsm6dso32x_sim_t val)
3258 {
3259 lsm6dso32x_ctrl3_c_t reg;
3260 int32_t ret;
3261
3262 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3263
3264 if (ret == 0)
3265 {
3266 reg.sim = (uint8_t)val;
3267 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3268 }
3269
3270 return ret;
3271 }
3272
3273 /**
3274 * @brief SPI Serial Interface Mode selection.[get]
3275 *
3276 * @param ctx read / write interface definitions
3277 * @param val Get the values of sim in reg CTRL3_C
3278 * @retval interface status (MANDATORY: return 0 -> no Error).
3279 *
3280 */
lsm6dso32x_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_sim_t * val)3281 int32_t lsm6dso32x_spi_mode_get(const stmdev_ctx_t *ctx,
3282 lsm6dso32x_sim_t *val)
3283 {
3284 lsm6dso32x_ctrl3_c_t reg;
3285 int32_t ret;
3286
3287 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3288
3289 switch (reg.sim)
3290 {
3291 case LSM6DSO32X_SPI_4_WIRE:
3292 *val = LSM6DSO32X_SPI_4_WIRE;
3293 break;
3294
3295 case LSM6DSO32X_SPI_3_WIRE:
3296 *val = LSM6DSO32X_SPI_3_WIRE;
3297 break;
3298
3299 default:
3300 *val = LSM6DSO32X_SPI_4_WIRE;
3301 break;
3302 }
3303
3304 return ret;
3305 }
3306
3307 /**
3308 * @brief Disable / Enable I2C interface.[set]
3309 *
3310 * @param ctx read / write interface definitions
3311 * @param val change the values of i2c_disable in
3312 * reg CTRL4_C
3313 * @retval interface status (MANDATORY: return 0 -> no Error).
3314 *
3315 */
lsm6dso32x_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dso32x_i2c_disable_t val)3316 int32_t lsm6dso32x_i2c_interface_set(const stmdev_ctx_t *ctx,
3317 lsm6dso32x_i2c_disable_t val)
3318 {
3319 lsm6dso32x_ctrl4_c_t reg;
3320 int32_t ret;
3321
3322 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3323
3324 if (ret == 0)
3325 {
3326 reg.i2c_disable = (uint8_t)val;
3327 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3328 }
3329
3330 return ret;
3331 }
3332
3333 /**
3334 * @brief Disable / Enable I2C interface.[get]
3335 *
3336 * @param ctx read / write interface definitions
3337 * @param val Get the values of i2c_disable in
3338 * reg CTRL4_C
3339 * @retval interface status (MANDATORY: return 0 -> no Error).
3340 *
3341 */
lsm6dso32x_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dso32x_i2c_disable_t * val)3342 int32_t lsm6dso32x_i2c_interface_get(const stmdev_ctx_t *ctx,
3343 lsm6dso32x_i2c_disable_t *val)
3344 {
3345 lsm6dso32x_ctrl4_c_t reg;
3346 int32_t ret;
3347
3348 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3349
3350 switch (reg.i2c_disable)
3351 {
3352 case LSM6DSO32X_I2C_ENABLE:
3353 *val = LSM6DSO32X_I2C_ENABLE;
3354 break;
3355
3356 case LSM6DSO32X_I2C_DISABLE:
3357 *val = LSM6DSO32X_I2C_DISABLE;
3358 break;
3359
3360 default:
3361 *val = LSM6DSO32X_I2C_ENABLE;
3362 break;
3363 }
3364
3365 return ret;
3366 }
3367
3368 /**
3369 * @brief I3C Enable/Disable communication protocol[.set]
3370 *
3371 * @param ctx read / write interface definitions
3372 * @param val change the values of i3c_disable
3373 * in reg CTRL9_XL
3374 * @retval interface status (MANDATORY: return 0 -> no Error).
3375 *
3376 */
lsm6dso32x_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dso32x_i3c_disable_t val)3377 int32_t lsm6dso32x_i3c_disable_set(const stmdev_ctx_t *ctx,
3378 lsm6dso32x_i3c_disable_t val)
3379 {
3380 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3381 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
3382 int32_t ret;
3383
3384 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
3385 (uint8_t *)&ctrl9_xl, 1);
3386
3387 if (ret == 0)
3388 {
3389 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3390 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
3391 (uint8_t *)&ctrl9_xl, 1);
3392 }
3393
3394 if (ret == 0)
3395 {
3396 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3397 (uint8_t *)&i3c_bus_avb, 1);
3398 }
3399
3400 if (ret == 0)
3401 {
3402 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3403 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3404 (uint8_t *)&i3c_bus_avb, 1);
3405 }
3406
3407 return ret;
3408 }
3409
3410 /**
3411 * @brief I3C Enable/Disable communication protocol.[get]
3412 *
3413 * @param ctx read / write interface definitions
3414 * @param val change the values of i3c_disable in
3415 * reg CTRL9_XL
3416 * @retval interface status (MANDATORY: return 0 -> no Error).
3417 *
3418 */
lsm6dso32x_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dso32x_i3c_disable_t * val)3419 int32_t lsm6dso32x_i3c_disable_get(const stmdev_ctx_t *ctx,
3420 lsm6dso32x_i3c_disable_t *val)
3421 {
3422 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
3423 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3424 int32_t ret;
3425
3426 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
3427 (uint8_t *)&ctrl9_xl, 1);
3428
3429 if (ret == 0)
3430 {
3431 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3432 (uint8_t *)&i3c_bus_avb, 1);
3433
3434 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
3435 {
3436 case LSM6DSO32X_I3C_DISABLE:
3437 *val = LSM6DSO32X_I3C_DISABLE;
3438 break;
3439
3440 case LSM6DSO32X_I3C_ENABLE_T_50us:
3441 *val = LSM6DSO32X_I3C_ENABLE_T_50us;
3442 break;
3443
3444 case LSM6DSO32X_I3C_ENABLE_T_2us:
3445 *val = LSM6DSO32X_I3C_ENABLE_T_2us;
3446 break;
3447
3448 case LSM6DSO32X_I3C_ENABLE_T_1ms:
3449 *val = LSM6DSO32X_I3C_ENABLE_T_1ms;
3450 break;
3451
3452 case LSM6DSO32X_I3C_ENABLE_T_25ms:
3453 *val = LSM6DSO32X_I3C_ENABLE_T_25ms;
3454 break;
3455
3456 default:
3457 *val = LSM6DSO32X_I3C_DISABLE;
3458 break;
3459 }
3460 }
3461
3462 return ret;
3463 }
3464
3465 /**
3466 * @}
3467 *
3468 */
3469
3470 /**
3471 * @defgroup LSM6DSO32X_interrupt_pins
3472 * @brief This section groups all the functions that manage interrupt pins
3473 * @{
3474 *
3475 */
3476
3477 /**
3478 * @brief Push-pull/open drain selection on interrupt pads.[set]
3479 *
3480 * @param ctx read / write interface definitions
3481 * @param val change the values of pp_od in reg CTRL3_C
3482 * @retval interface status (MANDATORY: return 0 -> no Error).
3483 *
3484 */
lsm6dso32x_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_pp_od_t val)3485 int32_t lsm6dso32x_pin_mode_set(const stmdev_ctx_t *ctx,
3486 lsm6dso32x_pp_od_t val)
3487 {
3488 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3489 lsm6dso32x_ctrl3_c_t ctrl3_c;
3490 int32_t ret;
3491
3492 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
3493 (uint8_t *)&ctrl3_c, 1);
3494
3495 if (ret == 0)
3496 {
3497 ctrl3_c.pp_od = (uint8_t)val;
3498 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
3499 (uint8_t *)&ctrl3_c, 1);
3500 }
3501
3502 if (ret == 0)
3503 {
3504 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3505 (uint8_t *)&i3c_bus_avb, 1);
3506 }
3507
3508 if (ret == 0)
3509 {
3510 i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1;
3511 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3512 (uint8_t *)&i3c_bus_avb, 1);
3513 }
3514
3515 return ret;
3516 }
3517
3518 /**
3519 * @brief Push-pull/open drain selection on interrupt pads.[get]
3520 *
3521 * @param ctx read / write interface definitions
3522 * @param val Get the values of pp_od in reg CTRL3_C
3523 * @retval interface status (MANDATORY: return 0 -> no Error).
3524 *
3525 */
lsm6dso32x_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_pp_od_t * val)3526 int32_t lsm6dso32x_pin_mode_get(const stmdev_ctx_t *ctx,
3527 lsm6dso32x_pp_od_t *val)
3528 {
3529 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3530 lsm6dso32x_ctrl3_c_t ctrl3_c;
3531 int32_t ret;
3532
3533 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
3534 (uint8_t *)&ctrl3_c, 1);
3535
3536 if (ret == 0)
3537 {
3538 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3539 (uint8_t *)&i3c_bus_avb, 1);
3540 }
3541
3542 switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od)
3543 {
3544 case LSM6DSO32X_PUSH_PULL:
3545 *val = LSM6DSO32X_PUSH_PULL;
3546 break;
3547
3548 case LSM6DSO32X_OPEN_DRAIN:
3549 *val = LSM6DSO32X_OPEN_DRAIN;
3550 break;
3551
3552 case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
3553 *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
3554 break;
3555
3556 case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
3557 *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
3558 break;
3559
3560 default:
3561 *val = LSM6DSO32X_PUSH_PULL;
3562 break;
3563 }
3564
3565 return ret;
3566 }
3567
3568 /**
3569 * @brief Interrupt active-high/low.[set]
3570 *
3571 * @param ctx read / write interface definitions
3572 * @param val change the values of h_lactive in reg CTRL3_C
3573 * @retval interface status (MANDATORY: return 0 -> no Error).
3574 *
3575 */
lsm6dso32x_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dso32x_h_lactive_t val)3576 int32_t lsm6dso32x_pin_polarity_set(const stmdev_ctx_t *ctx,
3577 lsm6dso32x_h_lactive_t val)
3578 {
3579 lsm6dso32x_ctrl3_c_t reg;
3580 int32_t ret;
3581
3582 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3583
3584 if (ret == 0)
3585 {
3586 reg.h_lactive = (uint8_t)val;
3587 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3588 }
3589
3590 return ret;
3591 }
3592
3593 /**
3594 * @brief Interrupt active-high/low.[get]
3595 *
3596 * @param ctx read / write interface definitions
3597 * @param val Get the values of h_lactive in reg CTRL3_C
3598 * @retval interface status (MANDATORY: return 0 -> no Error).
3599 *
3600 */
lsm6dso32x_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dso32x_h_lactive_t * val)3601 int32_t lsm6dso32x_pin_polarity_get(const stmdev_ctx_t *ctx,
3602 lsm6dso32x_h_lactive_t *val)
3603 {
3604 lsm6dso32x_ctrl3_c_t reg;
3605 int32_t ret;
3606
3607 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3608
3609 switch (reg.h_lactive)
3610 {
3611 case LSM6DSO32X_ACTIVE_HIGH:
3612 *val = LSM6DSO32X_ACTIVE_HIGH;
3613 break;
3614
3615 case LSM6DSO32X_ACTIVE_LOW:
3616 *val = LSM6DSO32X_ACTIVE_LOW;
3617 break;
3618
3619 default:
3620 *val = LSM6DSO32X_ACTIVE_HIGH;
3621 break;
3622 }
3623
3624 return ret;
3625 }
3626
3627 /**
3628 * @brief All interrupt signals become available on INT1 pin.[set]
3629 *
3630 * @param ctx read / write interface definitions
3631 * @param val change the values of int2_on_int1 in reg CTRL4_C
3632 * @retval interface status (MANDATORY: return 0 -> no Error).
3633 *
3634 */
lsm6dso32x_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3635 int32_t lsm6dso32x_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3636 {
3637 lsm6dso32x_ctrl4_c_t reg;
3638 int32_t ret;
3639
3640 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3641
3642 if (ret == 0)
3643 {
3644 reg.int2_on_int1 = val;
3645 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3646 }
3647
3648 return ret;
3649 }
3650
3651 /**
3652 * @brief All interrupt signals become available on INT1 pin.[get]
3653 *
3654 * @param ctx read / write interface definitions
3655 * @param val change the values of int2_on_int1 in reg CTRL4_C
3656 * @retval interface status (MANDATORY: return 0 -> no Error).
3657 *
3658 */
lsm6dso32x_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3659 int32_t lsm6dso32x_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3660 {
3661 lsm6dso32x_ctrl4_c_t reg;
3662 int32_t ret;
3663
3664 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3665 *val = reg.int2_on_int1;
3666
3667 return ret;
3668 }
3669
3670 /**
3671 * @brief Interrupt notification mode.[set]
3672 *
3673 * @param ctx read / write interface definitions
3674 * @param val change the values of lir in reg TAP_CFG0
3675 * @retval interface status (MANDATORY: return 0 -> no Error).
3676 *
3677 */
lsm6dso32x_int_notification_set(const stmdev_ctx_t * ctx,lsm6dso32x_lir_t val)3678 int32_t lsm6dso32x_int_notification_set(const stmdev_ctx_t *ctx,
3679 lsm6dso32x_lir_t val)
3680 {
3681 lsm6dso32x_tap_cfg0_t tap_cfg0;
3682 lsm6dso32x_page_rw_t page_rw;
3683 int32_t ret;
3684
3685 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
3686 (uint8_t *) &tap_cfg0, 1);
3687
3688 if (ret == 0)
3689 {
3690 tap_cfg0.lir = (uint8_t)val & 0x01U;
3691 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3692 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
3693 (uint8_t *) &tap_cfg0, 1);
3694 }
3695
3696 if (ret == 0)
3697 {
3698 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3699 }
3700
3701 if (ret == 0)
3702 {
3703 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3704 (uint8_t *) &page_rw, 1);
3705 }
3706
3707 if (ret == 0)
3708 {
3709 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3710 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
3711 (uint8_t *) &page_rw, 1);
3712 }
3713
3714 if (ret == 0)
3715 {
3716 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3717 }
3718
3719 return ret;
3720 }
3721
3722 /**
3723 * @brief Interrupt notification mode.[get]
3724 *
3725 * @param ctx read / write interface definitions
3726 * @param val Get the values of lir in reg TAP_CFG0
3727 * @retval interface status (MANDATORY: return 0 -> no Error).
3728 *
3729 */
lsm6dso32x_int_notification_get(const stmdev_ctx_t * ctx,lsm6dso32x_lir_t * val)3730 int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx,
3731 lsm6dso32x_lir_t *val)
3732 {
3733 lsm6dso32x_tap_cfg0_t tap_cfg0;
3734 lsm6dso32x_page_rw_t page_rw;
3735 int32_t ret;
3736
3737 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
3738 (uint8_t *) &tap_cfg0, 1);
3739
3740 if (ret == 0)
3741 {
3742 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3743 }
3744
3745 if (ret == 0)
3746 {
3747 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3748 (uint8_t *) &page_rw, 1);
3749 }
3750
3751 if (ret == 0)
3752 {
3753 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3754 }
3755
3756 if (ret == 0)
3757 {
3758 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
3759 {
3760 case LSM6DSO32X_ALL_INT_PULSED:
3761 *val = LSM6DSO32X_ALL_INT_PULSED;
3762 break;
3763
3764 case LSM6DSO32X_BASE_LATCHED_EMB_PULSED:
3765 *val = LSM6DSO32X_BASE_LATCHED_EMB_PULSED;
3766 break;
3767
3768 case LSM6DSO32X_BASE_PULSED_EMB_LATCHED:
3769 *val = LSM6DSO32X_BASE_PULSED_EMB_LATCHED;
3770 break;
3771
3772 case LSM6DSO32X_ALL_INT_LATCHED:
3773 *val = LSM6DSO32X_ALL_INT_LATCHED;
3774 break;
3775
3776 default:
3777 *val = LSM6DSO32X_ALL_INT_PULSED;
3778 break;
3779 }
3780
3781 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3782 }
3783
3784 if (ret == 0)
3785 {
3786 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3787 (uint8_t *) &page_rw, 1);
3788 }
3789
3790 if (ret == 0)
3791 {
3792 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3793 }
3794
3795 return ret;
3796 }
3797
3798 /**
3799 * @}
3800 *
3801 */
3802
3803 /**
3804 * @defgroup LSM6DSO32X_Wake_Up_event
3805 * @brief This section groups all the functions that manage the Wake Up
3806 * event generation.
3807 * @{
3808 *
3809 */
3810
3811 /**
3812 * @brief Weight of 1 LSB of wakeup threshold.[set]
3813 * 0: 1 LSB =FS_XL / 64
3814 * 1: 1 LSB = FS_XL / 256
3815 *
3816 * @param ctx read / write interface definitions
3817 * @param val change the values of wake_ths_w in
3818 * reg WAKE_UP_DUR
3819 * @retval interface status (MANDATORY: return 0 -> no Error).
3820 *
3821 */
lsm6dso32x_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dso32x_wake_ths_w_t val)3822 int32_t lsm6dso32x_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
3823 lsm6dso32x_wake_ths_w_t val)
3824 {
3825 lsm6dso32x_wake_up_dur_t reg;
3826 int32_t ret;
3827
3828 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3829 (uint8_t *)®, 1);
3830
3831 if (ret == 0)
3832 {
3833 reg.wake_ths_w = (uint8_t)val;
3834 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3835 (uint8_t *)®, 1);
3836 }
3837
3838 return ret;
3839 }
3840
3841 /**
3842 * @brief Weight of 1 LSB of wakeup threshold.[get]
3843 * 0: 1 LSB =FS_XL / 64
3844 * 1: 1 LSB = FS_XL / 256
3845 *
3846 * @param ctx read / write interface definitions
3847 * @param val Get the values of wake_ths_w in
3848 * reg WAKE_UP_DUR
3849 * @retval interface status (MANDATORY: return 0 -> no Error).
3850 *
3851 */
lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dso32x_wake_ths_w_t * val)3852 int32_t lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
3853 lsm6dso32x_wake_ths_w_t *val)
3854 {
3855 lsm6dso32x_wake_up_dur_t reg;
3856 int32_t ret;
3857
3858 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3859 (uint8_t *)®, 1);
3860
3861 switch (reg.wake_ths_w)
3862 {
3863 case LSM6DSO32X_LSb_FS_DIV_64:
3864 *val = LSM6DSO32X_LSb_FS_DIV_64;
3865 break;
3866
3867 case LSM6DSO32X_LSb_FS_DIV_256:
3868 *val = LSM6DSO32X_LSb_FS_DIV_256;
3869 break;
3870
3871 default:
3872 *val = LSM6DSO32X_LSb_FS_DIV_64;
3873 break;
3874 }
3875
3876 return ret;
3877 }
3878
3879 /**
3880 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3881 * WAKE_UP_DUR.[set]
3882 *
3883 * @param ctx read / write interface definitions
3884 * @param val change the values of wk_ths in reg WAKE_UP_THS
3885 * @retval interface status (MANDATORY: return 0 -> no Error).
3886 *
3887 */
lsm6dso32x_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3888 int32_t lsm6dso32x_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3889 {
3890 lsm6dso32x_wake_up_ths_t reg;
3891 int32_t ret;
3892
3893 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3894 (uint8_t *)®, 1);
3895
3896 if (ret == 0)
3897 {
3898 reg.wk_ths = val;
3899 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3900 (uint8_t *)®, 1);
3901 }
3902
3903 return ret;
3904 }
3905
3906 /**
3907 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3908 * WAKE_UP_DUR.[get]
3909 *
3910 * @param ctx read / write interface definitions
3911 * @param val change the values of wk_ths in reg WAKE_UP_THS
3912 * @retval interface status (MANDATORY: return 0 -> no Error).
3913 *
3914 */
lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3915 int32_t lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3916 {
3917 lsm6dso32x_wake_up_ths_t reg;
3918 int32_t ret;
3919
3920 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3921 (uint8_t *)®, 1);
3922 *val = reg.wk_ths;
3923
3924 return ret;
3925 }
3926
3927 /**
3928 * @brief Wake up duration event.[set]
3929 * 1LSb = 1 / ODR
3930 *
3931 * @param ctx read / write interface definitions
3932 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3933 * @retval interface status (MANDATORY: return 0 -> no Error).
3934 *
3935 */
lsm6dso32x_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)3936 int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
3937 uint8_t val)
3938 {
3939 lsm6dso32x_wake_up_ths_t reg;
3940 int32_t ret;
3941
3942 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3943 (uint8_t *)®, 1);
3944
3945 if (ret == 0)
3946 {
3947 reg.usr_off_on_wu = val;
3948 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3949 (uint8_t *)®, 1);
3950 }
3951
3952 return ret;
3953 }
3954
3955 /**
3956 * @brief Wake up duration event.[get]
3957 * 1LSb = 1 / ODR
3958 *
3959 * @param ctx read / write interface definitions
3960 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3961 * @retval interface status (MANDATORY: return 0 -> no Error).
3962 *
3963 */
lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)3964 int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
3965 uint8_t *val)
3966 {
3967 lsm6dso32x_wake_up_ths_t reg;
3968 int32_t ret;
3969
3970 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3971 (uint8_t *)®, 1);
3972 *val = reg.usr_off_on_wu;
3973
3974 return ret;
3975 }
3976
3977 /**
3978 * @brief Wake up duration event.[set]
3979 * 1LSb = 1 / ODR
3980 *
3981 * @param ctx read / write interface definitions
3982 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3983 * @retval interface status (MANDATORY: return 0 -> no Error).
3984 *
3985 */
lsm6dso32x_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3986 int32_t lsm6dso32x_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3987 {
3988 lsm6dso32x_wake_up_dur_t reg;
3989 int32_t ret;
3990
3991 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3992 (uint8_t *)®, 1);
3993
3994 if (ret == 0)
3995 {
3996 reg.wake_dur = val;
3997 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3998 (uint8_t *)®, 1);
3999 }
4000
4001 return ret;
4002 }
4003
4004 /**
4005 * @brief Wake up duration event.[get]
4006 * 1LSb = 1 / ODR
4007 *
4008 * @param ctx read / write interface definitions
4009 * @param val change the values of wake_dur in reg WAKE_UP_DUR
4010 * @retval interface status (MANDATORY: return 0 -> no Error).
4011 *
4012 */
lsm6dso32x_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4013 int32_t lsm6dso32x_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4014 {
4015 lsm6dso32x_wake_up_dur_t reg;
4016 int32_t ret;
4017
4018 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4019 (uint8_t *)®, 1);
4020 *val = reg.wake_dur;
4021
4022 return ret;
4023 }
4024
4025 /**
4026 * @}
4027 *
4028 */
4029
4030 /**
4031 * @defgroup LSM6DSO32X_ Activity/Inactivity_detection
4032 * @brief This section groups all the functions concerning
4033 * activity/inactivity detection.
4034 * @{
4035 *
4036 */
4037
4038 /**
4039 * @brief Enables gyroscope Sleep mode.[set]
4040 *
4041 * @param ctx read / write interface definitions
4042 * @param val change the values of sleep_g in reg CTRL4_C
4043 * @retval interface status (MANDATORY: return 0 -> no Error).
4044 *
4045 */
lsm6dso32x_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4046 int32_t lsm6dso32x_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4047 {
4048 lsm6dso32x_ctrl4_c_t reg;
4049 int32_t ret;
4050
4051 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4052
4053 if (ret == 0)
4054 {
4055 reg.sleep_g = val;
4056 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4057 }
4058
4059 return ret;
4060 }
4061
4062 /**
4063 * @brief Enables gyroscope Sleep mode.[get]
4064 *
4065 * @param ctx read / write interface definitions
4066 * @param val change the values of sleep_g in reg CTRL4_C
4067 * @retval interface status (MANDATORY: return 0 -> no Error).
4068 *
4069 */
lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4070 int32_t lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4071 {
4072 lsm6dso32x_ctrl4_c_t reg;
4073 int32_t ret;
4074
4075 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4076 *val = reg.sleep_g;
4077
4078 return ret;
4079 }
4080
4081 /**
4082 * @brief Drives the sleep status instead of
4083 * sleep change on INT pins
4084 * (only if INT1_SLEEP_CHANGE or
4085 * INT2_SLEEP_CHANGE bits are enabled).[set]
4086 *
4087 * @param ctx read / write interface definitions
4088 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
4089 * @retval interface status (MANDATORY: return 0 -> no Error).
4090 *
4091 */
lsm6dso32x_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dso32x_sleep_status_on_int_t val)4092 int32_t lsm6dso32x_act_pin_notification_set(const stmdev_ctx_t *ctx,
4093 lsm6dso32x_sleep_status_on_int_t val)
4094 {
4095 lsm6dso32x_tap_cfg0_t reg;
4096 int32_t ret;
4097
4098 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4099
4100 if (ret == 0)
4101 {
4102 reg.sleep_status_on_int = (uint8_t)val;
4103 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4104 }
4105
4106 return ret;
4107 }
4108
4109 /**
4110 * @brief Drives the sleep status instead of
4111 * sleep change on INT pins (only if
4112 * INT1_SLEEP_CHANGE or
4113 * INT2_SLEEP_CHANGE bits are enabled).[get]
4114 *
4115 * @param ctx read / write interface definitions
4116 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
4117 * @retval interface status (MANDATORY: return 0 -> no Error).
4118 *
4119 */
lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dso32x_sleep_status_on_int_t * val)4120 int32_t lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t *ctx,
4121 lsm6dso32x_sleep_status_on_int_t *val)
4122 {
4123 lsm6dso32x_tap_cfg0_t reg;
4124 int32_t ret;
4125
4126 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4127
4128 switch (reg.sleep_status_on_int)
4129 {
4130 case LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT:
4131 *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
4132 break;
4133
4134 case LSM6DSO32X_DRIVE_SLEEP_STATUS:
4135 *val = LSM6DSO32X_DRIVE_SLEEP_STATUS;
4136 break;
4137
4138 default:
4139 *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
4140 break;
4141 }
4142
4143 return ret;
4144 }
4145
4146 /**
4147 * @brief Enable inactivity function.[set]
4148 *
4149 * @param ctx read / write interface definitions
4150 * @param val change the values of inact_en in reg TAP_CFG2
4151 * @retval interface status (MANDATORY: return 0 -> no Error).
4152 *
4153 */
lsm6dso32x_act_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_inact_en_t val)4154 int32_t lsm6dso32x_act_mode_set(const stmdev_ctx_t *ctx,
4155 lsm6dso32x_inact_en_t val)
4156 {
4157 lsm6dso32x_tap_cfg2_t reg;
4158 int32_t ret;
4159
4160 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4161
4162 if (ret == 0)
4163 {
4164 reg.inact_en = (uint8_t)val;
4165 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4166 }
4167
4168 return ret;
4169 }
4170
4171 /**
4172 * @brief Enable inactivity function.[get]
4173 *
4174 * @param ctx read / write interface definitions
4175 * @param val Get the values of inact_en in reg TAP_CFG2
4176 * @retval interface status (MANDATORY: return 0 -> no Error).
4177 *
4178 */
lsm6dso32x_act_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_inact_en_t * val)4179 int32_t lsm6dso32x_act_mode_get(const stmdev_ctx_t *ctx,
4180 lsm6dso32x_inact_en_t *val)
4181 {
4182 lsm6dso32x_tap_cfg2_t reg;
4183 int32_t ret;
4184
4185 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4186
4187 switch (reg.inact_en)
4188 {
4189 case LSM6DSO32X_XL_AND_GY_NOT_AFFECTED:
4190 *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
4191 break;
4192
4193 case LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED:
4194 *val = LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED;
4195 break;
4196
4197 case LSM6DSO32X_XL_12Hz5_GY_SLEEP:
4198 *val = LSM6DSO32X_XL_12Hz5_GY_SLEEP;
4199 break;
4200
4201 case LSM6DSO32X_XL_12Hz5_GY_PD:
4202 *val = LSM6DSO32X_XL_12Hz5_GY_PD;
4203 break;
4204
4205 default:
4206 *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
4207 break;
4208 }
4209
4210 return ret;
4211 }
4212
4213 /**
4214 * @brief Duration to go in sleep mode.[set]
4215 * 1 LSb = 512 / ODR
4216 *
4217 * @param ctx read / write interface definitions
4218 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4219 * @retval interface status (MANDATORY: return 0 -> no Error).
4220 *
4221 */
lsm6dso32x_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4222 int32_t lsm6dso32x_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4223 {
4224 lsm6dso32x_wake_up_dur_t reg;
4225 int32_t ret;
4226
4227 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4228 (uint8_t *)®, 1);
4229
4230 if (ret == 0)
4231 {
4232 reg.sleep_dur = val;
4233 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4234 (uint8_t *)®, 1);
4235 }
4236
4237 return ret;
4238 }
4239
4240 /**
4241 * @brief Duration to go in sleep mode.[get]
4242 * 1 LSb = 512 / ODR
4243 *
4244 * @param ctx read / write interface definitions
4245 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4246 * @retval interface status (MANDATORY: return 0 -> no Error).
4247 *
4248 */
lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4249 int32_t lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4250 {
4251 lsm6dso32x_wake_up_dur_t reg;
4252 int32_t ret;
4253
4254 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4255 (uint8_t *)®, 1);
4256 *val = reg.sleep_dur;
4257
4258 return ret;
4259 }
4260
4261 /**
4262 * @}
4263 *
4264 */
4265
4266 /**
4267 * @defgroup LSM6DSO32X_tap_generator
4268 * @brief This section groups all the functions that manage the
4269 * tap and double tap event generation.
4270 * @{
4271 *
4272 */
4273
4274 /**
4275 * @brief Enable Z direction in tap recognition.[set]
4276 *
4277 * @param ctx read / write interface definitions
4278 * @param val change the values of tap_z_en in reg TAP_CFG0
4279 * @retval interface status (MANDATORY: return 0 -> no Error).
4280 *
4281 */
lsm6dso32x_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)4282 int32_t lsm6dso32x_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
4283 uint8_t val)
4284 {
4285 lsm6dso32x_tap_cfg0_t reg;
4286 int32_t ret;
4287
4288 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4289
4290 if (ret == 0)
4291 {
4292 reg.tap_z_en = val;
4293 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4294 }
4295
4296 return ret;
4297 }
4298
4299 /**
4300 * @brief Enable Z direction in tap recognition.[get]
4301 *
4302 * @param ctx read / write interface definitions
4303 * @param val change the values of tap_z_en in reg TAP_CFG0
4304 * @retval interface status (MANDATORY: return 0 -> no Error).
4305 *
4306 */
lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4307 int32_t lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
4308 uint8_t *val)
4309 {
4310 lsm6dso32x_tap_cfg0_t reg;
4311 int32_t ret;
4312
4313 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4314 *val = reg.tap_z_en;
4315
4316 return ret;
4317 }
4318
4319 /**
4320 * @brief Enable Y direction in tap recognition.[set]
4321 *
4322 * @param ctx read / write interface definitions
4323 * @param val change the values of tap_y_en in reg TAP_CFG0
4324 * @retval interface status (MANDATORY: return 0 -> no Error).
4325 *
4326 */
lsm6dso32x_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)4327 int32_t lsm6dso32x_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
4328 uint8_t val)
4329 {
4330 lsm6dso32x_tap_cfg0_t reg;
4331 int32_t ret;
4332
4333 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4334
4335 if (ret == 0)
4336 {
4337 reg.tap_y_en = val;
4338 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4339 }
4340
4341 return ret;
4342 }
4343
4344 /**
4345 * @brief Enable Y direction in tap recognition.[get]
4346 *
4347 * @param ctx read / write interface definitions
4348 * @param val change the values of tap_y_en in reg TAP_CFG0
4349 * @retval interface status (MANDATORY: return 0 -> no Error).
4350 *
4351 */
lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4352 int32_t lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
4353 uint8_t *val)
4354 {
4355 lsm6dso32x_tap_cfg0_t reg;
4356 int32_t ret;
4357
4358 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4359 *val = reg.tap_y_en;
4360
4361 return ret;
4362 }
4363
4364 /**
4365 * @brief Enable X direction in tap recognition.[set]
4366 *
4367 * @param ctx read / write interface definitions
4368 * @param val change the values of tap_x_en in reg TAP_CFG0
4369 * @retval interface status (MANDATORY: return 0 -> no Error).
4370 *
4371 */
lsm6dso32x_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)4372 int32_t lsm6dso32x_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
4373 uint8_t val)
4374 {
4375 lsm6dso32x_tap_cfg0_t reg;
4376 int32_t ret;
4377
4378 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4379
4380 if (ret == 0)
4381 {
4382 reg.tap_x_en = val;
4383 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4384 }
4385
4386 return ret;
4387 }
4388
4389 /**
4390 * @brief Enable X direction in tap recognition.[get]
4391 *
4392 * @param ctx read / write interface definitions
4393 * @param val change the values of tap_x_en in reg TAP_CFG0
4394 * @retval interface status (MANDATORY: return 0 -> no Error).
4395 *
4396 */
lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4397 int32_t lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
4398 uint8_t *val)
4399 {
4400 lsm6dso32x_tap_cfg0_t reg;
4401 int32_t ret;
4402
4403 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4404 *val = reg.tap_x_en;
4405
4406 return ret;
4407 }
4408
4409 /**
4410 * @brief X-axis tap recognition threshold.[set]
4411 *
4412 * @param ctx read / write interface definitions
4413 * @param val change the values of tap_ths_x in reg TAP_CFG1
4414 * @retval interface status (MANDATORY: return 0 -> no Error).
4415 *
4416 */
lsm6dso32x_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)4417 int32_t lsm6dso32x_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
4418 {
4419 lsm6dso32x_tap_cfg1_t reg;
4420 int32_t ret;
4421
4422 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4423
4424 if (ret == 0)
4425 {
4426 reg.tap_ths_x = val;
4427 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4428 }
4429
4430 return ret;
4431 }
4432
4433 /**
4434 * @brief X-axis tap recognition threshold.[get]
4435 *
4436 * @param ctx read / write interface definitions
4437 * @param val change the values of tap_ths_x in reg TAP_CFG1
4438 * @retval interface status (MANDATORY: return 0 -> no Error).
4439 *
4440 */
lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4441 int32_t lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t *ctx,
4442 uint8_t *val)
4443 {
4444 lsm6dso32x_tap_cfg1_t reg;
4445 int32_t ret;
4446
4447 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4448 *val = reg.tap_ths_x;
4449
4450 return ret;
4451 }
4452
4453 /**
4454 * @brief Selection of axis priority for TAP detection.[set]
4455 *
4456 * @param ctx read / write interface definitions
4457 * @param val change the values of tap_priority in
4458 * reg TAP_CFG1
4459 * @retval interface status (MANDATORY: return 0 -> no Error).
4460 *
4461 */
lsm6dso32x_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dso32x_tap_priority_t val)4462 int32_t lsm6dso32x_tap_axis_priority_set(const stmdev_ctx_t *ctx,
4463 lsm6dso32x_tap_priority_t val)
4464 {
4465 lsm6dso32x_tap_cfg1_t reg;
4466 int32_t ret;
4467
4468 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4469
4470 if (ret == 0)
4471 {
4472 reg.tap_priority = (uint8_t)val;
4473 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4474 }
4475
4476 return ret;
4477 }
4478
4479 /**
4480 * @brief Selection of axis priority for TAP detection.[get]
4481 *
4482 * @param ctx read / write interface definitions
4483 * @param val Get the values of tap_priority in
4484 * reg TAP_CFG1
4485 * @retval interface status (MANDATORY: return 0 -> no Error).
4486 *
4487 */
lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dso32x_tap_priority_t * val)4488 int32_t lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t *ctx,
4489 lsm6dso32x_tap_priority_t *val)
4490 {
4491 lsm6dso32x_tap_cfg1_t reg;
4492 int32_t ret;
4493
4494 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4495
4496 switch (reg.tap_priority)
4497 {
4498 case LSM6DSO32X_XYZ:
4499 *val = LSM6DSO32X_XYZ;
4500 break;
4501
4502 case LSM6DSO32X_YXZ:
4503 *val = LSM6DSO32X_YXZ;
4504 break;
4505
4506 case LSM6DSO32X_XZY:
4507 *val = LSM6DSO32X_XZY;
4508 break;
4509
4510 case LSM6DSO32X_ZYX:
4511 *val = LSM6DSO32X_ZYX;
4512 break;
4513
4514 case LSM6DSO32X_YZX:
4515 *val = LSM6DSO32X_YZX;
4516 break;
4517
4518 case LSM6DSO32X_ZXY:
4519 *val = LSM6DSO32X_ZXY;
4520 break;
4521
4522 default:
4523 *val = LSM6DSO32X_XYZ;
4524 break;
4525 }
4526
4527 return ret;
4528 }
4529
4530 /**
4531 * @brief Y-axis tap recognition threshold.[set]
4532 *
4533 * @param ctx read / write interface definitions
4534 * @param val change the values of tap_ths_y in reg TAP_CFG2
4535 * @retval interface status (MANDATORY: return 0 -> no Error).
4536 *
4537 */
lsm6dso32x_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)4538 int32_t lsm6dso32x_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
4539 {
4540 lsm6dso32x_tap_cfg2_t reg;
4541 int32_t ret;
4542
4543 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4544
4545 if (ret == 0)
4546 {
4547 reg.tap_ths_y = val;
4548 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4549 }
4550
4551 return ret;
4552 }
4553
4554 /**
4555 * @brief Y-axis tap recognition threshold.[get]
4556 *
4557 * @param ctx read / write interface definitions
4558 * @param val change the values of tap_ths_y in reg TAP_CFG2
4559 * @retval interface status (MANDATORY: return 0 -> no Error).
4560 *
4561 */
lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4562 int32_t lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t *ctx,
4563 uint8_t *val)
4564 {
4565 lsm6dso32x_tap_cfg2_t reg;
4566 int32_t ret;
4567
4568 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4569 *val = reg.tap_ths_y;
4570
4571 return ret;
4572 }
4573
4574 /**
4575 * @brief Z-axis recognition threshold.[set]
4576 *
4577 * @param ctx read / write interface definitions
4578 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4579 * @retval interface status (MANDATORY: return 0 -> no Error).
4580 *
4581 */
lsm6dso32x_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)4582 int32_t lsm6dso32x_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
4583 {
4584 lsm6dso32x_tap_ths_6d_t reg;
4585 int32_t ret;
4586
4587 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4588
4589 if (ret == 0)
4590 {
4591 reg.tap_ths_z = val;
4592 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4593 (uint8_t *)®, 1);
4594 }
4595
4596 return ret;
4597 }
4598
4599 /**
4600 * @brief Z-axis recognition threshold.[get]
4601 *
4602 * @param ctx read / write interface definitions
4603 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4604 * @retval interface status (MANDATORY: return 0 -> no Error).
4605 *
4606 */
lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4607 int32_t lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t *ctx,
4608 uint8_t *val)
4609 {
4610 lsm6dso32x_tap_ths_6d_t reg;
4611 int32_t ret;
4612
4613 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4614 *val = reg.tap_ths_z;
4615
4616 return ret;
4617 }
4618
4619 /**
4620 * @brief Maximum duration is the maximum time of an
4621 * over threshold signal detection to be recognized
4622 * as a tap event. The default value of these bits
4623 * is 00b which corresponds to 4*ODR_XL time.
4624 * If the SHOCK[1:0] bits are set to a different
4625 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4626 *
4627 * @param ctx read / write interface definitions
4628 * @param val change the values of shock in reg INT_DUR2
4629 * @retval interface status (MANDATORY: return 0 -> no Error).
4630 *
4631 */
lsm6dso32x_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)4632 int32_t lsm6dso32x_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
4633 {
4634 lsm6dso32x_int_dur2_t reg;
4635 int32_t ret;
4636
4637 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4638
4639 if (ret == 0)
4640 {
4641 reg.shock = val;
4642 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4643 }
4644
4645 return ret;
4646 }
4647
4648 /**
4649 * @brief Maximum duration is the maximum time of an
4650 * over threshold signal detection to be recognized
4651 * as a tap event. The default value of these bits
4652 * is 00b which corresponds to 4*ODR_XL time.
4653 * If the SHOCK[1:0] bits are set to a different
4654 * value, 1LSB corresponds to 8*ODR_XL time.[get]
4655 *
4656 * @param ctx read / write interface definitions
4657 * @param val change the values of shock in reg INT_DUR2
4658 * @retval interface status (MANDATORY: return 0 -> no Error).
4659 *
4660 */
lsm6dso32x_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)4661 int32_t lsm6dso32x_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
4662 {
4663 lsm6dso32x_int_dur2_t reg;
4664 int32_t ret;
4665
4666 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4667 *val = reg.shock;
4668
4669 return ret;
4670 }
4671
4672 /**
4673 * @brief Quiet time is the time after the first detected
4674 * tap in which there must not be any over threshold
4675 * event.
4676 * The default value of these bits is 00b which
4677 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
4678 * bits are set to a different value,
4679 * 1LSB corresponds to 4*ODR_XL time.[set]
4680 *
4681 * @param ctx read / write interface definitions
4682 * @param val change the values of quiet in reg INT_DUR2
4683 * @retval interface status (MANDATORY: return 0 -> no Error).
4684 *
4685 */
lsm6dso32x_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)4686 int32_t lsm6dso32x_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
4687 {
4688 lsm6dso32x_int_dur2_t reg;
4689 int32_t ret;
4690
4691 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4692
4693 if (ret == 0)
4694 {
4695 reg.quiet = val;
4696 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4697 }
4698
4699 return ret;
4700 }
4701
4702 /**
4703 * @brief Quiet time is the time after the first detected
4704 * tap in which there must not be any over threshold
4705 * event.
4706 * The default value of these bits is 00b which
4707 * corresponds to 2*ODR_XL time.
4708 * If the QUIET[1:0] bits are set to a different
4709 * value, 1LSB corresponds to 4*ODR_XL time.[get]
4710 *
4711 * @param ctx read / write interface definitions
4712 * @param val change the values of quiet in reg INT_DUR2
4713 * @retval interface status (MANDATORY: return 0 -> no Error).
4714 *
4715 */
lsm6dso32x_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)4716 int32_t lsm6dso32x_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
4717 {
4718 lsm6dso32x_int_dur2_t reg;
4719 int32_t ret;
4720
4721 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4722 *val = reg.quiet;
4723
4724 return ret;
4725 }
4726
4727 /**
4728 * @brief When double tap recognition is enabled,
4729 * this register expresses the maximum time
4730 * between two consecutive detected taps to
4731 * determine a double tap event.
4732 * The default value of these bits is 0000b which
4733 * corresponds to 16*ODR_XL time.
4734 * If the DUR[3:0] bits are set to a different value,
4735 * 1LSB corresponds to 32*ODR_XL time.[set]
4736 *
4737 * @param ctx read / write interface definitions
4738 * @param val change the values of dur in reg INT_DUR2
4739 * @retval interface status (MANDATORY: return 0 -> no Error).
4740 *
4741 */
lsm6dso32x_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4742 int32_t lsm6dso32x_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4743 {
4744 lsm6dso32x_int_dur2_t reg;
4745 int32_t ret;
4746
4747 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4748
4749 if (ret == 0)
4750 {
4751 reg.dur = val;
4752 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4753 }
4754
4755 return ret;
4756 }
4757
4758 /**
4759 * @brief When double tap recognition is enabled,
4760 * this register expresses the maximum time
4761 * between two consecutive detected taps to
4762 * determine a double tap event.
4763 * The default value of these bits is 0000b which
4764 * corresponds to 16*ODR_XL time. If the DUR[3:0]
4765 * bits are set to a different value,
4766 * 1LSB corresponds to 32*ODR_XL time.[get]
4767 *
4768 * @param ctx read / write interface definitions
4769 * @param val change the values of dur in reg INT_DUR2
4770 * @retval interface status (MANDATORY: return 0 -> no Error).
4771 *
4772 */
lsm6dso32x_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4773 int32_t lsm6dso32x_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4774 {
4775 lsm6dso32x_int_dur2_t reg;
4776 int32_t ret;
4777
4778 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4779 *val = reg.dur;
4780
4781 return ret;
4782 }
4783
4784 /**
4785 * @brief Single/double-tap event enable.[set]
4786 *
4787 * @param ctx read / write interface definitions
4788 * @param val change the values of single_double_tap in reg WAKE_UP_THS
4789 * @retval interface status (MANDATORY: return 0 -> no Error).
4790 *
4791 */
lsm6dso32x_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_single_double_tap_t val)4792 int32_t lsm6dso32x_tap_mode_set(const stmdev_ctx_t *ctx,
4793 lsm6dso32x_single_double_tap_t val)
4794 {
4795 lsm6dso32x_wake_up_ths_t reg;
4796 int32_t ret;
4797
4798 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4799 (uint8_t *)®, 1);
4800
4801 if (ret == 0)
4802 {
4803 reg.single_double_tap = (uint8_t)val;
4804 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4805 (uint8_t *)®, 1);
4806 }
4807
4808 return ret;
4809 }
4810
4811 /**
4812 * @brief Single/double-tap event enable.[get]
4813 *
4814 * @param ctx read / write interface definitions
4815 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
4816 * @retval interface status (MANDATORY: return 0 -> no Error).
4817 *
4818 */
lsm6dso32x_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_single_double_tap_t * val)4819 int32_t lsm6dso32x_tap_mode_get(const stmdev_ctx_t *ctx,
4820 lsm6dso32x_single_double_tap_t *val)
4821 {
4822 lsm6dso32x_wake_up_ths_t reg;
4823 int32_t ret;
4824
4825 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4826 (uint8_t *)®, 1);
4827
4828 switch (reg.single_double_tap)
4829 {
4830 case LSM6DSO32X_ONLY_SINGLE:
4831 *val = LSM6DSO32X_ONLY_SINGLE;
4832 break;
4833
4834 case LSM6DSO32X_BOTH_SINGLE_DOUBLE:
4835 *val = LSM6DSO32X_BOTH_SINGLE_DOUBLE;
4836 break;
4837
4838 default:
4839 *val = LSM6DSO32X_ONLY_SINGLE;
4840 break;
4841 }
4842
4843 return ret;
4844 }
4845
4846 /**
4847 * @}
4848 *
4849 */
4850
4851 /**
4852 * @defgroup LSM6DSO32X_ Six_position_detection(6D/4D)
4853 * @brief This section groups all the functions concerning six position
4854 * detection (6D).
4855 * @{
4856 *
4857 */
4858
4859 /**
4860 * @brief Threshold for 4D/6D function.[set]
4861 *
4862 * @param ctx read / write interface definitions
4863 * @param val change the values of sixd_ths in reg TAP_THS_6D
4864 * @retval interface status (MANDATORY: return 0 -> no Error).
4865 *
4866 */
lsm6dso32x_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dso32x_sixd_ths_t val)4867 int32_t lsm6dso32x_6d_threshold_set(const stmdev_ctx_t *ctx,
4868 lsm6dso32x_sixd_ths_t val)
4869 {
4870 lsm6dso32x_tap_ths_6d_t reg;
4871 int32_t ret;
4872
4873 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4874
4875 if (ret == 0)
4876 {
4877 reg.sixd_ths = (uint8_t)val;
4878 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4879 (uint8_t *)®, 1);
4880 }
4881
4882 return ret;
4883 }
4884
4885 /**
4886 * @brief Threshold for 4D/6D function.[get]
4887 *
4888 * @param ctx read / write interface definitions
4889 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4890 * @retval interface status (MANDATORY: return 0 -> no Error).
4891 *
4892 */
lsm6dso32x_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dso32x_sixd_ths_t * val)4893 int32_t lsm6dso32x_6d_threshold_get(const stmdev_ctx_t *ctx,
4894 lsm6dso32x_sixd_ths_t *val)
4895 {
4896 lsm6dso32x_tap_ths_6d_t reg;
4897 int32_t ret;
4898
4899 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4900
4901 switch (reg.sixd_ths)
4902 {
4903 case LSM6DSO32X_DEG_80:
4904 *val = LSM6DSO32X_DEG_80;
4905 break;
4906
4907 case LSM6DSO32X_DEG_70:
4908 *val = LSM6DSO32X_DEG_70;
4909 break;
4910
4911 case LSM6DSO32X_DEG_60:
4912 *val = LSM6DSO32X_DEG_60;
4913 break;
4914
4915 case LSM6DSO32X_DEG_50:
4916 *val = LSM6DSO32X_DEG_50;
4917 break;
4918
4919 default:
4920 *val = LSM6DSO32X_DEG_80;
4921 break;
4922 }
4923
4924 return ret;
4925 }
4926
4927 /**
4928 * @brief 4D orientation detection enable.[set]
4929 *
4930 * @param ctx read / write interface definitions
4931 * @param val change the values of d4d_en in reg TAP_THS_6D
4932 * @retval interface status (MANDATORY: return 0 -> no Error).
4933 *
4934 */
lsm6dso32x_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4935 int32_t lsm6dso32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4936 {
4937 lsm6dso32x_tap_ths_6d_t reg;
4938 int32_t ret;
4939
4940 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4941
4942 if (ret == 0)
4943 {
4944 reg.d4d_en = val;
4945 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4946 (uint8_t *)®, 1);
4947 }
4948
4949 return ret;
4950 }
4951
4952 /**
4953 * @brief 4D orientation detection enable.[get]
4954 *
4955 * @param ctx read / write interface definitions
4956 * @param val change the values of d4d_en in reg TAP_THS_6D
4957 * @retval interface status (MANDATORY: return 0 -> no Error).
4958 *
4959 */
lsm6dso32x_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4960 int32_t lsm6dso32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4961 {
4962 lsm6dso32x_tap_ths_6d_t reg;
4963 int32_t ret;
4964
4965 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4966 *val = reg.d4d_en;
4967
4968 return ret;
4969 }
4970
4971 /**
4972 * @}
4973 *
4974 */
4975
4976 /**
4977 * @defgroup LSM6DSO32X_free_fall
4978 * @brief This section group all the functions concerning the free
4979 * fall detection.
4980 * @{
4981 *
4982 */
4983 /**
4984 * @brief Free fall threshold setting.[set]
4985 *
4986 * @param ctx read / write interface definitions
4987 * @param val change the values of ff_ths in reg FREE_FALL
4988 * @retval interface status (MANDATORY: return 0 -> no Error).
4989 *
4990 */
lsm6dso32x_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dso32x_ff_ths_t val)4991 int32_t lsm6dso32x_ff_threshold_set(const stmdev_ctx_t *ctx,
4992 lsm6dso32x_ff_ths_t val)
4993 {
4994 lsm6dso32x_free_fall_t reg;
4995 int32_t ret;
4996
4997 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
4998
4999 if (ret == 0)
5000 {
5001 reg.ff_ths = (uint8_t)val;
5002 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
5003 }
5004
5005 return ret;
5006 }
5007
5008 /**
5009 * @brief Free fall threshold setting.[get]
5010 *
5011 * @param ctx read / write interface definitions
5012 * @param val Get the values of ff_ths in reg FREE_FALL
5013 * @retval interface status (MANDATORY: return 0 -> no Error).
5014 *
5015 */
lsm6dso32x_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dso32x_ff_ths_t * val)5016 int32_t lsm6dso32x_ff_threshold_get(const stmdev_ctx_t *ctx,
5017 lsm6dso32x_ff_ths_t *val)
5018 {
5019 lsm6dso32x_free_fall_t reg;
5020 int32_t ret;
5021
5022 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
5023
5024 switch (reg.ff_ths)
5025 {
5026 case LSM6DSO32X_FF_TSH_312mg:
5027 *val = LSM6DSO32X_FF_TSH_312mg;
5028 break;
5029
5030 case LSM6DSO32X_FF_TSH_438mg:
5031 *val = LSM6DSO32X_FF_TSH_438mg;
5032 break;
5033
5034 case LSM6DSO32X_FF_TSH_500mg:
5035 *val = LSM6DSO32X_FF_TSH_500mg;
5036 break;
5037
5038 default:
5039 *val = LSM6DSO32X_FF_TSH_312mg;
5040 break;
5041 }
5042
5043 return ret;
5044 }
5045
5046 /**
5047 * @brief Free-fall duration event.[set]
5048 * 1LSb = 1 / ODR
5049 *
5050 * @param ctx read / write interface definitions
5051 * @param val change the values of ff_dur in reg FREE_FALL
5052 * @retval interface status (MANDATORY: return 0 -> no Error).
5053 *
5054 */
lsm6dso32x_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5055 int32_t lsm6dso32x_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5056 {
5057 lsm6dso32x_wake_up_dur_t wake_up_dur;
5058 lsm6dso32x_free_fall_t free_fall;
5059 int32_t ret;
5060
5061 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5062 (uint8_t *)&wake_up_dur, 1);
5063
5064 if (ret == 0)
5065 {
5066 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
5067 (uint8_t *)&free_fall, 1);
5068 }
5069
5070 if (ret == 0)
5071 {
5072 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
5073 free_fall.ff_dur = (uint8_t)val & 0x1FU;
5074 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5075 (uint8_t *)&wake_up_dur, 1);
5076 }
5077
5078 if (ret == 0)
5079 {
5080 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL,
5081 (uint8_t *)&free_fall, 1);
5082 }
5083
5084 return ret;
5085 }
5086
5087 /**
5088 * @brief Free-fall duration event.[get]
5089 * 1LSb = 1 / ODR
5090 *
5091 * @param ctx read / write interface definitions
5092 * @param val change the values of ff_dur in reg FREE_FALL
5093 * @retval interface status (MANDATORY: return 0 -> no Error).
5094 *
5095 */
lsm6dso32x_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5096 int32_t lsm6dso32x_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5097 {
5098 lsm6dso32x_wake_up_dur_t wake_up_dur;
5099 lsm6dso32x_free_fall_t free_fall;
5100 int32_t ret;
5101
5102 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5103 (uint8_t *)&wake_up_dur, 1);
5104
5105 if (ret == 0)
5106 {
5107 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
5108 (uint8_t *)&free_fall, 1);
5109 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5110 }
5111
5112 return ret;
5113 }
5114
5115 /**
5116 * @}
5117 *
5118 */
5119
5120 /**
5121 * @defgroup LSM6DSO32X_fifo
5122 * @brief This section group all the functions concerning the fifo usage
5123 * @{
5124 *
5125 */
5126
5127 /**
5128 * @brief FIFO watermark level selection.[set]
5129 *
5130 * @param ctx read / write interface definitions
5131 * @param val change the values of wtm in reg FIFO_CTRL1
5132 * @retval interface status (MANDATORY: return 0 -> no Error).
5133 *
5134 */
lsm6dso32x_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)5135 int32_t lsm6dso32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
5136 {
5137 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
5138 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5139 int32_t ret;
5140
5141 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5142 (uint8_t *)&fifo_ctrl2, 1);
5143
5144 if (ret == 0)
5145 {
5146 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
5147 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
5148 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
5149 (uint8_t *)&fifo_ctrl1, 1);
5150 }
5151
5152 if (ret == 0)
5153 {
5154 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5155 (uint8_t *)&fifo_ctrl2, 1);
5156 }
5157
5158 return ret;
5159 }
5160
5161 /**
5162 * @brief FIFO watermark level selection.[get]
5163 *
5164 * @param ctx read / write interface definitions
5165 * @param val change the values of wtm in reg FIFO_CTRL1
5166 * @retval interface status (MANDATORY: return 0 -> no Error).
5167 *
5168 */
lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)5169 int32_t lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t *ctx,
5170 uint16_t *val)
5171 {
5172 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
5173 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5174 int32_t ret;
5175
5176 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
5177 (uint8_t *)&fifo_ctrl1, 1);
5178
5179 if (ret == 0)
5180 {
5181 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5182 (uint8_t *)&fifo_ctrl2, 1);
5183 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
5184 }
5185
5186 return ret;
5187 }
5188
5189 /**
5190 * @brief FIFO compression feature initialization request [set].
5191 *
5192 * @param ctx read / write interface definitions
5193 * @param val change the values of FIFO_COMPR_INIT in
5194 * reg EMB_FUNC_INIT_B
5195 * @retval interface status (MANDATORY: return 0 -> no Error).
5196 *
5197 */
lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)5198 int32_t lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t *ctx,
5199 uint8_t val)
5200 {
5201 lsm6dso32x_emb_func_init_b_t reg;
5202 int32_t ret;
5203
5204 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
5205
5206 if (ret == 0)
5207 {
5208 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5209 (uint8_t *)®, 1);
5210 }
5211
5212 if (ret == 0)
5213 {
5214 reg.fifo_compr_init = val;
5215 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5216 (uint8_t *)®, 1);
5217 }
5218
5219 if (ret == 0)
5220 {
5221 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
5222 }
5223
5224 return ret;
5225 }
5226
5227 /**
5228 * @brief FIFO compression feature initialization request [get].
5229 *
5230 * @param ctx read / write interface definitions
5231 * @param val change the values of FIFO_COMPR_INIT in
5232 * reg EMB_FUNC_INIT_B
5233 * @retval interface status (MANDATORY: return 0 -> no Error).
5234 *
5235 */
lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)5236 int32_t lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t *ctx,
5237 uint8_t *val)
5238 {
5239 lsm6dso32x_emb_func_init_b_t reg;
5240 int32_t ret;
5241
5242 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
5243
5244 if (ret == 0)
5245 {
5246 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5247 (uint8_t *)®, 1);
5248 }
5249
5250 if (ret == 0)
5251 {
5252 *val = reg.fifo_compr_init;
5253 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
5254 }
5255
5256 return ret;
5257 }
5258
5259 /**
5260 * @brief Enable and configure compression algo.[set]
5261 *
5262 * @param ctx read / write interface definitions
5263 * @param val change the values of uncoptr_rate in
5264 * reg FIFO_CTRL2
5265 * @retval interface status (MANDATORY: return 0 -> no Error).
5266 *
5267 */
lsm6dso32x_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dso32x_uncoptr_rate_t val)5268 int32_t lsm6dso32x_compression_algo_set(const stmdev_ctx_t *ctx,
5269 lsm6dso32x_uncoptr_rate_t val)
5270 {
5271 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5272 int32_t ret;
5273
5274 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5275 (uint8_t *)&fifo_ctrl2, 1);
5276
5277 if (ret == 0)
5278 {
5279 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
5280 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
5281 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5282 (uint8_t *)&fifo_ctrl2, 1);
5283 }
5284
5285 return ret;
5286 }
5287
5288 /**
5289 * @brief Enable and configure compression algo.[get]
5290 *
5291 * @param ctx read / write interface definitions
5292 * @param val Get the values of uncoptr_rate in
5293 * reg FIFO_CTRL2
5294 * @retval interface status (MANDATORY: return 0 -> no Error).
5295 *
5296 */
lsm6dso32x_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dso32x_uncoptr_rate_t * val)5297 int32_t lsm6dso32x_compression_algo_get(const stmdev_ctx_t *ctx,
5298 lsm6dso32x_uncoptr_rate_t *val)
5299 {
5300 lsm6dso32x_fifo_ctrl2_t reg;
5301 int32_t ret;
5302
5303 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5304
5305 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
5306 {
5307 case LSM6DSO32X_CMP_DISABLE:
5308 *val = LSM6DSO32X_CMP_DISABLE;
5309 break;
5310
5311 case LSM6DSO32X_CMP_ALWAYS:
5312 *val = LSM6DSO32X_CMP_ALWAYS;
5313 break;
5314
5315 case LSM6DSO32X_CMP_8_TO_1:
5316 *val = LSM6DSO32X_CMP_8_TO_1;
5317 break;
5318
5319 case LSM6DSO32X_CMP_16_TO_1:
5320 *val = LSM6DSO32X_CMP_16_TO_1;
5321 break;
5322
5323 case LSM6DSO32X_CMP_32_TO_1:
5324 *val = LSM6DSO32X_CMP_32_TO_1;
5325 break;
5326
5327 default:
5328 *val = LSM6DSO32X_CMP_DISABLE;
5329 break;
5330 }
5331
5332 return ret;
5333 }
5334
5335 /**
5336 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
5337 *
5338 * @param ctx read / write interface definitions
5339 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5340 * @retval interface status (MANDATORY: return 0 -> no Error).
5341 *
5342 */
lsm6dso32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)5343 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
5344 uint8_t val)
5345 {
5346 lsm6dso32x_fifo_ctrl2_t reg;
5347 int32_t ret;
5348
5349 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5350
5351 if (ret == 0)
5352 {
5353 reg.odrchg_en = val;
5354 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5355 (uint8_t *)®, 1);
5356 }
5357
5358 return ret;
5359 }
5360
5361 /**
5362 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
5363 *
5364 * @param ctx read / write interface definitions
5365 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5366 * @retval interface status (MANDATORY: return 0 -> no Error).
5367 *
5368 */
lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)5369 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
5370 uint8_t *val)
5371 {
5372 lsm6dso32x_fifo_ctrl2_t reg;
5373 int32_t ret;
5374
5375 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5376 *val = reg.odrchg_en;
5377
5378 return ret;
5379 }
5380
5381 /**
5382 * @brief Enables/Disables compression algorithm runtime.[set]
5383 *
5384 * @param ctx read / write interface definitions
5385 * @param val change the values of fifo_compr_rt_en in
5386 * reg FIFO_CTRL2
5387 * @retval interface status (MANDATORY: return 0 -> no Error).
5388 *
5389 */
lsm6dso32x_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)5390 int32_t lsm6dso32x_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
5391 uint8_t val)
5392 {
5393 lsm6dso32x_fifo_ctrl2_t reg;
5394 int32_t ret;
5395
5396 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5397
5398 if (ret == 0)
5399 {
5400 reg.fifo_compr_rt_en = val;
5401 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5402 (uint8_t *)®, 1);
5403 }
5404
5405 return ret;
5406 }
5407
5408 /**
5409 * @brief Enables/Disables compression algorithm runtime. [get]
5410 *
5411 * @param ctx read / write interface definitions
5412 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
5413 * @retval interface status (MANDATORY: return 0 -> no Error).
5414 *
5415 */
lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)5416 int32_t lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
5417 uint8_t *val)
5418 {
5419 lsm6dso32x_fifo_ctrl2_t reg;
5420 int32_t ret;
5421
5422 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5423 *val = reg.fifo_compr_rt_en;
5424
5425 return ret;
5426 }
5427
5428 /**
5429 * @brief Sensing chain FIFO stop values memorization at
5430 * threshold level.[set]
5431 *
5432 * @param ctx read / write interface definitions
5433 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5434 * @retval interface status (MANDATORY: return 0 -> no Error).
5435 *
5436 */
lsm6dso32x_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)5437 int32_t lsm6dso32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx,
5438 uint8_t val)
5439 {
5440 lsm6dso32x_fifo_ctrl2_t reg;
5441 int32_t ret;
5442
5443 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5444
5445 if (ret == 0)
5446 {
5447 reg.stop_on_wtm = val;
5448 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5449 (uint8_t *)®, 1);
5450 }
5451
5452 return ret;
5453 }
5454
5455 /**
5456 * @brief Sensing chain FIFO stop values memorization at
5457 * threshold level.[get]
5458 *
5459 * @param ctx read / write interface definitions
5460 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5461 * @retval interface status (MANDATORY: return 0 -> no Error).
5462 *
5463 */
lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)5464 int32_t lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
5465 uint8_t *val)
5466 {
5467 lsm6dso32x_fifo_ctrl2_t reg;
5468 int32_t ret;
5469
5470 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5471 *val = reg.stop_on_wtm;
5472
5473 return ret;
5474 }
5475
5476 /**
5477 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5478 * for accelerometer data.[set]
5479 *
5480 * @param ctx read / write interface definitions
5481 * @param val change the values of bdr_xl in reg FIFO_CTRL3
5482 * @retval interface status (MANDATORY: return 0 -> no Error).
5483 *
5484 */
lsm6dso32x_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dso32x_bdr_xl_t val)5485 int32_t lsm6dso32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5486 lsm6dso32x_bdr_xl_t val)
5487 {
5488 lsm6dso32x_fifo_ctrl3_t reg;
5489 int32_t ret;
5490
5491 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5492
5493 if (ret == 0)
5494 {
5495 reg.bdr_xl = (uint8_t)val;
5496 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
5497 (uint8_t *)®, 1);
5498 }
5499
5500 return ret;
5501 }
5502
5503 /**
5504 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5505 * for accelerometer data.[get]
5506 *
5507 * @param ctx read / write interface definitions
5508 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
5509 * @retval interface status (MANDATORY: return 0 -> no Error).
5510 *
5511 */
lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dso32x_bdr_xl_t * val)5512 int32_t lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5513 lsm6dso32x_bdr_xl_t *val)
5514 {
5515 lsm6dso32x_fifo_ctrl3_t reg;
5516 int32_t ret;
5517
5518 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5519
5520 switch (reg.bdr_xl)
5521 {
5522 case LSM6DSO32X_XL_NOT_BATCHED:
5523 *val = LSM6DSO32X_XL_NOT_BATCHED;
5524 break;
5525
5526 case LSM6DSO32X_XL_BATCHED_AT_12Hz5:
5527 *val = LSM6DSO32X_XL_BATCHED_AT_12Hz5;
5528 break;
5529
5530 case LSM6DSO32X_XL_BATCHED_AT_26Hz:
5531 *val = LSM6DSO32X_XL_BATCHED_AT_26Hz;
5532 break;
5533
5534 case LSM6DSO32X_XL_BATCHED_AT_52Hz:
5535 *val = LSM6DSO32X_XL_BATCHED_AT_52Hz;
5536 break;
5537
5538 case LSM6DSO32X_XL_BATCHED_AT_104Hz:
5539 *val = LSM6DSO32X_XL_BATCHED_AT_104Hz;
5540 break;
5541
5542 case LSM6DSO32X_XL_BATCHED_AT_208Hz:
5543 *val = LSM6DSO32X_XL_BATCHED_AT_208Hz;
5544 break;
5545
5546 case LSM6DSO32X_XL_BATCHED_AT_417Hz:
5547 *val = LSM6DSO32X_XL_BATCHED_AT_417Hz;
5548 break;
5549
5550 case LSM6DSO32X_XL_BATCHED_AT_833Hz:
5551 *val = LSM6DSO32X_XL_BATCHED_AT_833Hz;
5552 break;
5553
5554 case LSM6DSO32X_XL_BATCHED_AT_1667Hz:
5555 *val = LSM6DSO32X_XL_BATCHED_AT_1667Hz;
5556 break;
5557
5558 case LSM6DSO32X_XL_BATCHED_AT_3333Hz:
5559 *val = LSM6DSO32X_XL_BATCHED_AT_3333Hz;
5560 break;
5561
5562 case LSM6DSO32X_XL_BATCHED_AT_6667Hz:
5563 *val = LSM6DSO32X_XL_BATCHED_AT_6667Hz;
5564 break;
5565
5566 case LSM6DSO32X_XL_BATCHED_AT_6Hz5:
5567 *val = LSM6DSO32X_XL_BATCHED_AT_6Hz5;
5568 break;
5569
5570 default:
5571 *val = LSM6DSO32X_XL_NOT_BATCHED;
5572 break;
5573 }
5574
5575 return ret;
5576 }
5577
5578 /**
5579 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5580 * for gyroscope data.[set]
5581 *
5582 * @param ctx read / write interface definitions
5583 * @param val change the values of bdr_gy in reg FIFO_CTRL3
5584 * @retval interface status (MANDATORY: return 0 -> no Error).
5585 *
5586 */
lsm6dso32x_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dso32x_bdr_gy_t val)5587 int32_t lsm6dso32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5588 lsm6dso32x_bdr_gy_t val)
5589 {
5590 lsm6dso32x_fifo_ctrl3_t reg;
5591 int32_t ret;
5592
5593 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5594
5595 if (ret == 0)
5596 {
5597 reg.bdr_gy = (uint8_t)val;
5598 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
5599 (uint8_t *)®, 1);
5600 }
5601
5602 return ret;
5603 }
5604
5605 /**
5606 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5607 * for gyroscope data.[get]
5608 *
5609 * @param ctx read / write interface definitions
5610 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
5611 * @retval interface status (MANDATORY: return 0 -> no Error).
5612 *
5613 */
lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dso32x_bdr_gy_t * val)5614 int32_t lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5615 lsm6dso32x_bdr_gy_t *val)
5616 {
5617 lsm6dso32x_fifo_ctrl3_t reg;
5618 int32_t ret;
5619
5620 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5621
5622 switch (reg.bdr_gy)
5623 {
5624 case LSM6DSO32X_GY_NOT_BATCHED:
5625 *val = LSM6DSO32X_GY_NOT_BATCHED;
5626 break;
5627
5628 case LSM6DSO32X_GY_BATCHED_AT_12Hz5:
5629 *val = LSM6DSO32X_GY_BATCHED_AT_12Hz5;
5630 break;
5631
5632 case LSM6DSO32X_GY_BATCHED_AT_26Hz:
5633 *val = LSM6DSO32X_GY_BATCHED_AT_26Hz;
5634 break;
5635
5636 case LSM6DSO32X_GY_BATCHED_AT_52Hz:
5637 *val = LSM6DSO32X_GY_BATCHED_AT_52Hz;
5638 break;
5639
5640 case LSM6DSO32X_GY_BATCHED_AT_104Hz:
5641 *val = LSM6DSO32X_GY_BATCHED_AT_104Hz;
5642 break;
5643
5644 case LSM6DSO32X_GY_BATCHED_AT_208Hz:
5645 *val = LSM6DSO32X_GY_BATCHED_AT_208Hz;
5646 break;
5647
5648 case LSM6DSO32X_GY_BATCHED_AT_417Hz:
5649 *val = LSM6DSO32X_GY_BATCHED_AT_417Hz;
5650 break;
5651
5652 case LSM6DSO32X_GY_BATCHED_AT_833Hz:
5653 *val = LSM6DSO32X_GY_BATCHED_AT_833Hz;
5654 break;
5655
5656 case LSM6DSO32X_GY_BATCHED_AT_1667Hz:
5657 *val = LSM6DSO32X_GY_BATCHED_AT_1667Hz;
5658 break;
5659
5660 case LSM6DSO32X_GY_BATCHED_AT_3333Hz:
5661 *val = LSM6DSO32X_GY_BATCHED_AT_3333Hz;
5662 break;
5663
5664 case LSM6DSO32X_GY_BATCHED_AT_6667Hz:
5665 *val = LSM6DSO32X_GY_BATCHED_AT_6667Hz;
5666 break;
5667
5668 case LSM6DSO32X_GY_BATCHED_AT_6Hz5:
5669 *val = LSM6DSO32X_GY_BATCHED_AT_6Hz5;
5670 break;
5671
5672 default:
5673 *val = LSM6DSO32X_GY_NOT_BATCHED;
5674 break;
5675 }
5676
5677 return ret;
5678 }
5679
5680 /**
5681 * @brief FIFO mode selection.[set]
5682 *
5683 * @param ctx read / write interface definitions
5684 * @param val change the values of fifo_mode in reg FIFO_CTRL4
5685 * @retval interface status (MANDATORY: return 0 -> no Error).
5686 *
5687 */
lsm6dso32x_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_fifo_mode_t val)5688 int32_t lsm6dso32x_fifo_mode_set(const stmdev_ctx_t *ctx,
5689 lsm6dso32x_fifo_mode_t val)
5690 {
5691 lsm6dso32x_fifo_ctrl4_t reg;
5692 int32_t ret;
5693
5694 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5695
5696 if (ret == 0)
5697 {
5698 reg.fifo_mode = (uint8_t)val;
5699 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5700 (uint8_t *)®, 1);
5701 }
5702
5703 return ret;
5704 }
5705
5706 /**
5707 * @brief FIFO mode selection.[get]
5708 *
5709 * @param ctx read / write interface definitions
5710 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
5711 * @retval interface status (MANDATORY: return 0 -> no Error).
5712 *
5713 */
lsm6dso32x_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_fifo_mode_t * val)5714 int32_t lsm6dso32x_fifo_mode_get(const stmdev_ctx_t *ctx,
5715 lsm6dso32x_fifo_mode_t *val)
5716 {
5717 lsm6dso32x_fifo_ctrl4_t reg;
5718 int32_t ret;
5719
5720 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5721
5722 switch (reg.fifo_mode)
5723 {
5724 case LSM6DSO32X_BYPASS_MODE:
5725 *val = LSM6DSO32X_BYPASS_MODE;
5726 break;
5727
5728 case LSM6DSO32X_FIFO_MODE:
5729 *val = LSM6DSO32X_FIFO_MODE;
5730 break;
5731
5732 case LSM6DSO32X_STREAM_TO_FIFO_MODE:
5733 *val = LSM6DSO32X_STREAM_TO_FIFO_MODE;
5734 break;
5735
5736 case LSM6DSO32X_BYPASS_TO_STREAM_MODE:
5737 *val = LSM6DSO32X_BYPASS_TO_STREAM_MODE;
5738 break;
5739
5740 case LSM6DSO32X_STREAM_MODE:
5741 *val = LSM6DSO32X_STREAM_MODE;
5742 break;
5743
5744 case LSM6DSO32X_BYPASS_TO_FIFO_MODE:
5745 *val = LSM6DSO32X_BYPASS_TO_FIFO_MODE;
5746 break;
5747
5748 default:
5749 *val = LSM6DSO32X_BYPASS_MODE;
5750 break;
5751 }
5752
5753 return ret;
5754 }
5755
5756 /**
5757 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5758 * for temperature data.[set]
5759 *
5760 * @param ctx read / write interface definitions
5761 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
5762 * @retval interface status (MANDATORY: return 0 -> no Error).
5763 *
5764 */
lsm6dso32x_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dso32x_odr_t_batch_t val)5765 int32_t lsm6dso32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
5766 lsm6dso32x_odr_t_batch_t val)
5767 {
5768 lsm6dso32x_fifo_ctrl4_t reg;
5769 int32_t ret;
5770
5771 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5772
5773 if (ret == 0)
5774 {
5775 reg.odr_t_batch = (uint8_t)val;
5776 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5777 (uint8_t *)®, 1);
5778 }
5779
5780 return ret;
5781 }
5782
5783 /**
5784 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5785 * for temperature data.[get]
5786 *
5787 * @param ctx read / write interface definitions
5788 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
5789 * @retval interface status (MANDATORY: return 0 -> no Error).
5790 *
5791 */
lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dso32x_odr_t_batch_t * val)5792 int32_t lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
5793 lsm6dso32x_odr_t_batch_t *val)
5794 {
5795 lsm6dso32x_fifo_ctrl4_t reg;
5796 int32_t ret;
5797
5798 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5799
5800 switch (reg.odr_t_batch)
5801 {
5802 case LSM6DSO32X_TEMP_NOT_BATCHED:
5803 *val = LSM6DSO32X_TEMP_NOT_BATCHED;
5804 break;
5805
5806 case LSM6DSO32X_TEMP_BATCHED_AT_1Hz6:
5807 *val = LSM6DSO32X_TEMP_BATCHED_AT_1Hz6;
5808 break;
5809
5810 case LSM6DSO32X_TEMP_BATCHED_AT_12Hz5:
5811 *val = LSM6DSO32X_TEMP_BATCHED_AT_12Hz5;
5812 break;
5813
5814 case LSM6DSO32X_TEMP_BATCHED_AT_52Hz:
5815 *val = LSM6DSO32X_TEMP_BATCHED_AT_52Hz;
5816 break;
5817
5818 default:
5819 *val = LSM6DSO32X_TEMP_NOT_BATCHED;
5820 break;
5821 }
5822
5823 return ret;
5824 }
5825
5826 /**
5827 * @brief Selects decimation for timestamp batching in FIFO.
5828 * Writing rate will be the maximum rate between XL and
5829 * GYRO BDR divided by decimation decoder.[set]
5830 *
5831 * @param ctx read / write interface definitions
5832 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
5833 * @retval interface status (MANDATORY: return 0 -> no Error).
5834 *
5835 */
lsm6dso32x_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dso32x_odr_ts_batch_t val)5836 int32_t lsm6dso32x_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
5837 lsm6dso32x_odr_ts_batch_t val)
5838 {
5839 lsm6dso32x_fifo_ctrl4_t reg;
5840 int32_t ret;
5841
5842 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5843
5844 if (ret == 0)
5845 {
5846 reg.odr_ts_batch = (uint8_t)val;
5847 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5848 (uint8_t *)®, 1);
5849 }
5850
5851 return ret;
5852 }
5853
5854 /**
5855 * @brief Selects decimation for timestamp batching in FIFO.
5856 * Writing rate will be the maximum rate between XL and
5857 * GYRO BDR divided by decimation decoder.[get]
5858 *
5859 * @param ctx read / write interface definitions
5860 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
5861 * @retval interface status (MANDATORY: return 0 -> no Error).
5862 *
5863 */
lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dso32x_odr_ts_batch_t * val)5864 int32_t lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
5865 lsm6dso32x_odr_ts_batch_t *val)
5866 {
5867 lsm6dso32x_fifo_ctrl4_t reg;
5868 int32_t ret;
5869
5870 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5871
5872 switch (reg.odr_ts_batch)
5873 {
5874 case LSM6DSO32X_NO_DECIMATION:
5875 *val = LSM6DSO32X_NO_DECIMATION;
5876 break;
5877
5878 case LSM6DSO32X_DEC_1:
5879 *val = LSM6DSO32X_DEC_1;
5880 break;
5881
5882 case LSM6DSO32X_DEC_8:
5883 *val = LSM6DSO32X_DEC_8;
5884 break;
5885
5886 case LSM6DSO32X_DEC_32:
5887 *val = LSM6DSO32X_DEC_32;
5888 break;
5889
5890 default:
5891 *val = LSM6DSO32X_NO_DECIMATION;
5892 break;
5893 }
5894
5895 return ret;
5896 }
5897
5898 /**
5899 * @brief Selects the trigger for the internal counter of batching events
5900 * between XL and gyro.[set]
5901 *
5902 * @param ctx read / write interface definitions
5903 * @param val change the values of trig_counter_bdr
5904 * in reg COUNTER_BDR_REG1
5905 * @retval interface status (MANDATORY: return 0 -> no Error).
5906 *
5907 */
lsm6dso32x_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dso32x_trig_counter_bdr_t val)5908 int32_t lsm6dso32x_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
5909 lsm6dso32x_trig_counter_bdr_t val)
5910 {
5911 lsm6dso32x_counter_bdr_reg1_t reg;
5912 int32_t ret;
5913
5914 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5915 (uint8_t *)®, 1);
5916
5917 if (ret == 0)
5918 {
5919 reg.trig_counter_bdr = (uint8_t)val;
5920 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5921 (uint8_t *)®, 1);
5922 }
5923
5924 return ret;
5925 }
5926
5927 /**
5928 * @brief Selects the trigger for the internal counter of batching events
5929 * between XL and gyro.[get]
5930 *
5931 * @param ctx read / write interface definitions
5932 * @param val Get the values of trig_counter_bdr
5933 * in reg COUNTER_BDR_REG1
5934 * @retval interface status (MANDATORY: return 0 -> no Error).
5935 *
5936 */
lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dso32x_trig_counter_bdr_t * val)5937 int32_t lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
5938 lsm6dso32x_trig_counter_bdr_t *val)
5939 {
5940 lsm6dso32x_counter_bdr_reg1_t reg;
5941 int32_t ret;
5942
5943 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5944 (uint8_t *)®, 1);
5945
5946 switch (reg.trig_counter_bdr)
5947 {
5948 case LSM6DSO32X_XL_BATCH_EVENT:
5949 *val = LSM6DSO32X_XL_BATCH_EVENT;
5950 break;
5951
5952 case LSM6DSO32X_GYRO_BATCH_EVENT:
5953 *val = LSM6DSO32X_GYRO_BATCH_EVENT;
5954 break;
5955
5956 default:
5957 *val = LSM6DSO32X_XL_BATCH_EVENT;
5958 break;
5959 }
5960
5961 return ret;
5962 }
5963
5964 /**
5965 * @brief Resets the internal counter of batching vents for a single sensor.
5966 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5967 *
5968 * @param ctx read / write interface definitions
5969 * @param val change the values of rst_counter_bdr in
5970 * reg COUNTER_BDR_REG1
5971 * @retval interface status (MANDATORY: return 0 -> no Error).
5972 *
5973 */
lsm6dso32x_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)5974 int32_t lsm6dso32x_rst_batch_counter_set(const stmdev_ctx_t *ctx,
5975 uint8_t val)
5976 {
5977 lsm6dso32x_counter_bdr_reg1_t reg;
5978 int32_t ret;
5979
5980 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5981 (uint8_t *)®, 1);
5982
5983 if (ret == 0)
5984 {
5985 reg.rst_counter_bdr = val;
5986 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5987 (uint8_t *)®, 1);
5988 }
5989
5990 return ret;
5991 }
5992
5993 /**
5994 * @brief Resets the internal counter of batching events for a single sensor.
5995 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5996 *
5997 * @param ctx read / write interface definitions
5998 * @param val change the values of rst_counter_bdr in
5999 * reg COUNTER_BDR_REG1
6000 * @retval interface status (MANDATORY: return 0 -> no Error).
6001 *
6002 */
lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)6003 int32_t lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t *ctx,
6004 uint8_t *val)
6005 {
6006 lsm6dso32x_counter_bdr_reg1_t reg;
6007 int32_t ret;
6008
6009 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6010 (uint8_t *)®, 1);
6011 *val = reg.rst_counter_bdr;
6012
6013 return ret;
6014 }
6015
6016 /**
6017 * @brief Batch data rate counter.[set]
6018 *
6019 * @param ctx read / write interface definitions
6020 * @param val change the values of cnt_bdr_th in
6021 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6022 * @retval interface status (MANDATORY: return 0 -> no Error).
6023 *
6024 */
lsm6dso32x_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)6025 int32_t lsm6dso32x_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
6026 uint16_t val)
6027 {
6028 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
6029 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
6030 int32_t ret;
6031
6032 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6033 (uint8_t *)&counter_bdr_reg1, 1);
6034
6035 if (ret == 0)
6036 {
6037 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
6038 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
6039 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6040 (uint8_t *)&counter_bdr_reg1, 1);
6041 }
6042
6043 if (ret == 0)
6044 {
6045 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
6046 (uint8_t *)&counter_bdr_reg2, 1);
6047 }
6048
6049 return ret;
6050 }
6051
6052 /**
6053 * @brief Batch data rate counter.[get]
6054 *
6055 * @param ctx read / write interface definitions
6056 * @param val change the values of cnt_bdr_th in
6057 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6058 * @retval interface status (MANDATORY: return 0 -> no Error).
6059 *
6060 */
lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)6061 int32_t lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
6062 uint16_t *val)
6063 {
6064 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
6065 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
6066 int32_t ret;
6067
6068 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6069 (uint8_t *)&counter_bdr_reg1, 1);
6070
6071 if (ret == 0)
6072 {
6073 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
6074 (uint8_t *)&counter_bdr_reg2, 1);
6075 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
6076 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
6077 }
6078
6079 return ret;
6080 }
6081
6082 /**
6083 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
6084 *
6085 * @param ctx Read / write interface definitions.(ptr)
6086 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
6087 * @retval Interface status (MANDATORY: return 0 -> no Error).
6088 *
6089 */
lsm6dso32x_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)6090 int32_t lsm6dso32x_fifo_data_level_get(const stmdev_ctx_t *ctx,
6091 uint16_t *val)
6092 {
6093 uint8_t reg[2];
6094 lsm6dso32x_fifo_status1_t *fifo_status1 = (lsm6dso32x_fifo_status1_t *)®[0];
6095 lsm6dso32x_fifo_status2_t *fifo_status2 = (lsm6dso32x_fifo_status2_t *)®[1];
6096 int32_t ret;
6097
6098 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6099 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1, (uint8_t *)reg, 2);
6100 if (ret == 0)
6101 {
6102 *val = fifo_status2->diff_fifo;
6103 *val = (*val * 256U) + fifo_status1->diff_fifo;
6104 }
6105
6106 return ret;
6107 }
6108
6109 /**
6110 * @brief Smart FIFO status.[get]
6111 *
6112 * @param ctx Read / write interface definitions.(ptr)
6113 * @param val Read registers FIFO_STATUS2
6114 * @retval Interface status (MANDATORY: return 0 -> no Error).
6115 *
6116 */
lsm6dso32x_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dso32x_fifo_status2_t * val)6117 int32_t lsm6dso32x_fifo_status_get(const stmdev_ctx_t *ctx,
6118 lsm6dso32x_fifo_status2_t *val)
6119 {
6120 uint8_t reg[2];
6121 lsm6dso32x_fifo_status2_t *fifo_status2 = (lsm6dso32x_fifo_status2_t *)®[1];
6122 int32_t ret;
6123
6124 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6125 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1, (uint8_t *)reg, 2);
6126 if (ret == 0)
6127 {
6128 *val = *fifo_status2;
6129 }
6130
6131 return ret;
6132 }
6133
6134 /**
6135 * @brief Smart FIFO full status.[get]
6136 *
6137 * @param ctx Read / write interface definitions.(ptr)
6138 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
6139 * @retval Interface status (MANDATORY: return 0 -> no Error).
6140 *
6141 */
lsm6dso32x_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6142 int32_t lsm6dso32x_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6143 {
6144 uint8_t reg[2];
6145 lsm6dso32x_fifo_status2_t *fifo_status2 = (lsm6dso32x_fifo_status2_t *)®[1];
6146 int32_t ret;
6147
6148 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6149 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1, (uint8_t *)reg, 2);
6150 if (ret == 0)
6151 {
6152 *val = fifo_status2->fifo_full_ia;
6153 }
6154
6155 return ret;
6156 }
6157
6158 /**
6159 * @brief FIFO overrun status.[get]
6160 *
6161 * @param ctx Read / write interface definitions.(ptr)
6162 * @param val Read the values of fifo_over_run_latched in
6163 * reg FIFO_STATUS2
6164 * @retval Interface status (MANDATORY: return 0 -> no Error).
6165 *
6166 */
lsm6dso32x_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6167 int32_t lsm6dso32x_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6168 {
6169 uint8_t reg[2];
6170 lsm6dso32x_fifo_status2_t *fifo_status2 = (lsm6dso32x_fifo_status2_t *)®[1];
6171 int32_t ret;
6172
6173 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6174 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1, (uint8_t *)reg, 2);
6175 if (ret == 0)
6176 {
6177 *val = fifo_status2->fifo_ovr_ia;
6178 }
6179
6180 return ret;
6181 }
6182
6183 /**
6184 * @brief FIFO watermark status.[get]
6185 *
6186 * @param ctx Read / write interface definitions.(ptr)
6187 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
6188 * @retval Interface status (MANDATORY: return 0 -> no Error).
6189 *
6190 */
lsm6dso32x_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6191 int32_t lsm6dso32x_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6192 {
6193 uint8_t reg[2];
6194 lsm6dso32x_fifo_status2_t *fifo_status2 = (lsm6dso32x_fifo_status2_t *)®[1];
6195 int32_t ret;
6196
6197 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6198 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1, (uint8_t *)reg, 2);
6199 if (ret == 0)
6200 {
6201 *val = fifo_status2->fifo_wtm_ia;
6202 }
6203
6204 return ret;
6205 }
6206
6207 /**
6208 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
6209 *
6210 * @param ctx read / write interface definitions
6211 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
6212 * @retval interface status (MANDATORY: return 0 -> no Error).
6213 *
6214 */
lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dso32x_fifo_tag_t * val)6215 int32_t lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
6216 lsm6dso32x_fifo_tag_t *val)
6217 {
6218 lsm6dso32x_fifo_data_out_tag_t reg;
6219 int32_t ret;
6220
6221 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_TAG,
6222 (uint8_t *)®, 1);
6223
6224 switch (reg.tag_sensor)
6225 {
6226 case LSM6DSO32X_GYRO_NC_TAG:
6227 *val = LSM6DSO32X_GYRO_NC_TAG;
6228 break;
6229
6230 case LSM6DSO32X_XL_NC_TAG:
6231 *val = LSM6DSO32X_XL_NC_TAG;
6232 break;
6233
6234 case LSM6DSO32X_TEMPERATURE_TAG:
6235 *val = LSM6DSO32X_TEMPERATURE_TAG;
6236 break;
6237
6238 case LSM6DSO32X_TIMESTAMP_TAG:
6239 *val = LSM6DSO32X_TIMESTAMP_TAG;
6240 break;
6241
6242 case LSM6DSO32X_CFG_CHANGE_TAG:
6243 *val = LSM6DSO32X_CFG_CHANGE_TAG;
6244 break;
6245
6246 case LSM6DSO32X_XL_NC_T_2_TAG:
6247 *val = LSM6DSO32X_XL_NC_T_2_TAG;
6248 break;
6249
6250 case LSM6DSO32X_XL_NC_T_1_TAG:
6251 *val = LSM6DSO32X_XL_NC_T_1_TAG;
6252 break;
6253
6254 case LSM6DSO32X_XL_2XC_TAG:
6255 *val = LSM6DSO32X_XL_2XC_TAG;
6256 break;
6257
6258 case LSM6DSO32X_XL_3XC_TAG:
6259 *val = LSM6DSO32X_XL_3XC_TAG;
6260 break;
6261
6262 case LSM6DSO32X_GYRO_NC_T_2_TAG:
6263 *val = LSM6DSO32X_GYRO_NC_T_2_TAG;
6264 break;
6265
6266 case LSM6DSO32X_GYRO_NC_T_1_TAG:
6267 *val = LSM6DSO32X_GYRO_NC_T_1_TAG;
6268 break;
6269
6270 case LSM6DSO32X_GYRO_2XC_TAG:
6271 *val = LSM6DSO32X_GYRO_2XC_TAG;
6272 break;
6273
6274 case LSM6DSO32X_GYRO_3XC_TAG:
6275 *val = LSM6DSO32X_GYRO_3XC_TAG;
6276 break;
6277
6278 case LSM6DSO32X_SENSORHUB_SLAVE0_TAG:
6279 *val = LSM6DSO32X_SENSORHUB_SLAVE0_TAG;
6280 break;
6281
6282 case LSM6DSO32X_SENSORHUB_SLAVE1_TAG:
6283 *val = LSM6DSO32X_SENSORHUB_SLAVE1_TAG;
6284 break;
6285
6286 case LSM6DSO32X_SENSORHUB_SLAVE2_TAG:
6287 *val = LSM6DSO32X_SENSORHUB_SLAVE2_TAG;
6288 break;
6289
6290 case LSM6DSO32X_SENSORHUB_SLAVE3_TAG:
6291 *val = LSM6DSO32X_SENSORHUB_SLAVE3_TAG;
6292 break;
6293
6294 case LSM6DSO32X_STEP_CPUNTER_TAG:
6295 *val = LSM6DSO32X_STEP_CPUNTER_TAG;
6296 break;
6297
6298 case LSM6DSO32X_GAME_ROTATION_TAG:
6299 *val = LSM6DSO32X_GAME_ROTATION_TAG;
6300 break;
6301
6302 case LSM6DSO32X_GEOMAG_ROTATION_TAG:
6303 *val = LSM6DSO32X_GEOMAG_ROTATION_TAG;
6304 break;
6305
6306 case LSM6DSO32X_ROTATION_TAG:
6307 *val = LSM6DSO32X_ROTATION_TAG;
6308 break;
6309
6310 case LSM6DSO32X_SENSORHUB_NACK_TAG:
6311 *val = LSM6DSO32X_SENSORHUB_NACK_TAG;
6312 break;
6313
6314 default:
6315 *val = LSM6DSO32X_GYRO_NC_TAG;
6316 break;
6317 }
6318
6319 return ret;
6320 }
6321
6322 /**
6323 * @brief : Enable FIFO batching of pedometer embedded
6324 * function values.[set]
6325 *
6326 * @param ctx read / write interface definitions
6327 * @param val change the values of gbias_fifo_en in
6328 * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
6329 * @retval interface status (MANDATORY: return 0 -> no Error).
6330 *
6331 */
lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)6332 int32_t lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
6333 {
6334 lsm6dso32x_emb_func_fifo_cfg_t reg;
6335 int32_t ret;
6336
6337 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
6338
6339 if (ret == 0)
6340 {
6341 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6342 (uint8_t *)®, 1);
6343 }
6344
6345 if (ret == 0)
6346 {
6347 reg.pedo_fifo_en = val;
6348 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6349 (uint8_t *)®, 1);
6350 }
6351
6352 if (ret == 0)
6353 {
6354 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6355 }
6356
6357 return ret;
6358 }
6359
6360 /**
6361 * @brief Enable FIFO batching of pedometer embedded function values.[get]
6362 *
6363 * @param ctx read / write interface definitions
6364 * @param val change the values of pedo_fifo_en in
6365 * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
6366 * @retval interface status (MANDATORY: return 0 -> no Error).
6367 *
6368 */
lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)6369 int32_t lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t *ctx,
6370 uint8_t *val)
6371 {
6372 lsm6dso32x_emb_func_fifo_cfg_t reg;
6373 int32_t ret;
6374
6375 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
6376
6377 if (ret == 0)
6378 {
6379 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6380 (uint8_t *)®, 1);
6381 }
6382
6383 if (ret == 0)
6384 {
6385 *val = reg.pedo_fifo_en;
6386 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6387 }
6388
6389 return ret;
6390 }
6391
6392 /**
6393 * @brief Enable FIFO batching data of first slave.[set]
6394 *
6395 * @param ctx read / write interface definitions
6396 * @param val change the values of batch_ext_sens_0_en in
6397 * reg SLV0_CONFIG
6398 * @retval interface status (MANDATORY: return 0 -> no Error).
6399 *
6400 */
lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)6401 int32_t lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t *ctx,
6402 uint8_t val)
6403 {
6404 lsm6dso32x_slv0_config_t reg;
6405 int32_t ret;
6406
6407 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6408
6409 if (ret == 0)
6410 {
6411 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6412 (uint8_t *)®, 1);
6413 }
6414
6415 if (ret == 0)
6416 {
6417 reg.batch_ext_sens_0_en = val;
6418 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6419 (uint8_t *)®, 1);
6420 }
6421
6422 if (ret == 0)
6423 {
6424 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6425 }
6426
6427 return ret;
6428 }
6429
6430 /**
6431 * @brief Enable FIFO batching data of first slave.[get]
6432 *
6433 * @param ctx read / write interface definitions
6434 * @param val change the values of batch_ext_sens_0_en in
6435 * reg SLV0_CONFIG
6436 * @retval interface status (MANDATORY: return 0 -> no Error).
6437 *
6438 */
lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)6439 int32_t lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t *ctx,
6440 uint8_t *val)
6441 {
6442 lsm6dso32x_slv0_config_t reg;
6443 int32_t ret;
6444
6445 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6446
6447 if (ret == 0)
6448 {
6449 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6450 (uint8_t *)®, 1);
6451 }
6452
6453 if (ret == 0)
6454 {
6455 *val = reg.batch_ext_sens_0_en;
6456 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6457 }
6458
6459 return ret;
6460 }
6461
6462 /**
6463 * @brief Enable FIFO batching data of second slave.[set]
6464 *
6465 * @param ctx read / write interface definitions
6466 * @param val change the values of batch_ext_sens_1_en in
6467 * reg SLV1_CONFIG
6468 * @retval interface status (MANDATORY: return 0 -> no Error).
6469 *
6470 */
lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)6471 int32_t lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t *ctx,
6472 uint8_t val)
6473 {
6474 lsm6dso32x_slv1_config_t reg;
6475 int32_t ret;
6476
6477 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6478
6479 if (ret == 0)
6480 {
6481 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6482 (uint8_t *)®, 1);
6483 }
6484
6485 if (ret == 0)
6486 {
6487 reg.batch_ext_sens_1_en = val;
6488 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6489 (uint8_t *)®, 1);
6490 }
6491
6492 if (ret == 0)
6493 {
6494 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6495 }
6496
6497 return ret;
6498 }
6499
6500 /**
6501 * @brief Enable FIFO batching data of second slave.[get]
6502 *
6503 * @param ctx read / write interface definitions
6504 * @param val change the values of batch_ext_sens_1_en in
6505 * reg SLV1_CONFIG
6506 * @retval interface status (MANDATORY: return 0 -> no Error).
6507 *
6508 */
lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)6509 int32_t lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t *ctx,
6510 uint8_t *val)
6511 {
6512 lsm6dso32x_slv1_config_t reg;
6513 int32_t ret;
6514
6515 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6516
6517 if (ret == 0)
6518 {
6519 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6520 (uint8_t *)®, 1);
6521 *val = reg.batch_ext_sens_1_en;
6522 }
6523
6524 if (ret == 0)
6525 {
6526 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6527 }
6528
6529 return ret;
6530 }
6531
6532 /**
6533 * @brief Enable FIFO batching data of third slave.[set]
6534 *
6535 * @param ctx read / write interface definitions
6536 * @param val change the values of batch_ext_sens_2_en in
6537 * reg SLV2_CONFIG
6538 * @retval interface status (MANDATORY: return 0 -> no Error).
6539 *
6540 */
lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)6541 int32_t lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t *ctx,
6542 uint8_t val)
6543 {
6544 lsm6dso32x_slv2_config_t reg;
6545 int32_t ret;
6546
6547 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6548
6549 if (ret == 0)
6550 {
6551 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6552 (uint8_t *)®, 1);
6553 }
6554
6555 if (ret == 0)
6556 {
6557 reg.batch_ext_sens_2_en = val;
6558 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6559 (uint8_t *)®, 1);
6560 }
6561
6562 if (ret == 0)
6563 {
6564 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6565 }
6566
6567 return ret;
6568 }
6569
6570 /**
6571 * @brief Enable FIFO batching data of third slave.[get]
6572 *
6573 * @param ctx read / write interface definitions
6574 * @param val change the values of batch_ext_sens_2_en in
6575 * reg SLV2_CONFIG
6576 * @retval interface status (MANDATORY: return 0 -> no Error).
6577 *
6578 */
lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)6579 int32_t lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t *ctx,
6580 uint8_t *val)
6581 {
6582 lsm6dso32x_slv2_config_t reg;
6583 int32_t ret;
6584
6585 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6586
6587 if (ret == 0)
6588 {
6589 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6590 (uint8_t *)®, 1);
6591 }
6592
6593 if (ret == 0)
6594 {
6595 *val = reg.batch_ext_sens_2_en;
6596 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6597 }
6598
6599 return ret;
6600 }
6601
6602 /**
6603 * @brief Enable FIFO batching data of fourth slave.[set]
6604 *
6605 * @param ctx read / write interface definitions
6606 * @param val change the values of batch_ext_sens_3_en
6607 * in reg SLV3_CONFIG
6608 * @retval interface status (MANDATORY: return 0 -> no Error).
6609 *
6610 */
lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)6611 int32_t lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t *ctx,
6612 uint8_t val)
6613 {
6614 lsm6dso32x_slv3_config_t reg;
6615 int32_t ret;
6616
6617 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6618
6619 if (ret == 0)
6620 {
6621 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6622 (uint8_t *)®, 1);
6623 }
6624
6625 if (ret == 0)
6626 {
6627 reg.batch_ext_sens_3_en = val;
6628 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6629 (uint8_t *)®, 1);
6630 }
6631
6632 if (ret == 0)
6633 {
6634 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6635 }
6636
6637 return ret;
6638 }
6639
6640 /**
6641 * @brief Enable FIFO batching data of fourth slave.[get]
6642 *
6643 * @param ctx read / write interface definitions
6644 * @param val change the values of batch_ext_sens_3_en in
6645 * reg SLV3_CONFIG
6646 * @retval interface status (MANDATORY: return 0 -> no Error).
6647 *
6648 */
lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)6649 int32_t lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t *ctx,
6650 uint8_t *val)
6651 {
6652 lsm6dso32x_slv3_config_t reg;
6653 int32_t ret;
6654
6655 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6656
6657 if (ret == 0)
6658 {
6659 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6660 (uint8_t *)®, 1);
6661 }
6662
6663 if (ret == 0)
6664 {
6665 *val = reg.batch_ext_sens_3_en;
6666 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6667 }
6668
6669 return ret;
6670 }
6671
6672 /**
6673 * @}
6674 *
6675 */
6676
6677 /**
6678 * @defgroup LSM6DSO32X_DEN_functionality
6679 * @brief This section groups all the functions concerning
6680 * DEN functionality.
6681 * @{
6682 *
6683 */
6684
6685 /**
6686 * @brief DEN functionality marking mode.[set]
6687 *
6688 * @param ctx read / write interface definitions
6689 * @param val change the values of den_mode in reg CTRL6_C
6690 * @retval interface status (MANDATORY: return 0 -> no Error).
6691 *
6692 */
lsm6dso32x_den_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_den_mode_t val)6693 int32_t lsm6dso32x_den_mode_set(const stmdev_ctx_t *ctx,
6694 lsm6dso32x_den_mode_t val)
6695 {
6696 lsm6dso32x_ctrl6_c_t reg;
6697 int32_t ret;
6698
6699 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6700
6701 if (ret == 0)
6702 {
6703 reg.den_mode = (uint8_t)val;
6704 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6705 }
6706
6707 return ret;
6708 }
6709
6710 /**
6711 * @brief DEN functionality marking mode.[get]
6712 *
6713 * @param ctx read / write interface definitions
6714 * @param val Get the values of den_mode in reg CTRL6_C
6715 * @retval interface status (MANDATORY: return 0 -> no Error).
6716 *
6717 */
lsm6dso32x_den_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_den_mode_t * val)6718 int32_t lsm6dso32x_den_mode_get(const stmdev_ctx_t *ctx,
6719 lsm6dso32x_den_mode_t *val)
6720 {
6721 lsm6dso32x_ctrl6_c_t reg;
6722 int32_t ret;
6723
6724 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6725
6726 switch (reg.den_mode)
6727 {
6728 case LSM6DSO32X_DEN_DISABLE:
6729 *val = LSM6DSO32X_DEN_DISABLE;
6730 break;
6731
6732 case LSM6DSO32X_LEVEL_FIFO:
6733 *val = LSM6DSO32X_LEVEL_FIFO;
6734 break;
6735
6736 case LSM6DSO32X_LEVEL_LETCHED:
6737 *val = LSM6DSO32X_LEVEL_LETCHED;
6738 break;
6739
6740 case LSM6DSO32X_LEVEL_TRIGGER:
6741 *val = LSM6DSO32X_LEVEL_TRIGGER;
6742 break;
6743
6744 case LSM6DSO32X_EDGE_TRIGGER:
6745 *val = LSM6DSO32X_EDGE_TRIGGER;
6746 break;
6747
6748 default:
6749 *val = LSM6DSO32X_DEN_DISABLE;
6750 break;
6751 }
6752
6753 return ret;
6754 }
6755
6756 /**
6757 * @brief DEN active level configuration.[set]
6758 *
6759 * @param ctx read / write interface definitions
6760 * @param val change the values of den_lh in reg CTRL9_XL
6761 * @retval interface status (MANDATORY: return 0 -> no Error).
6762 *
6763 */
lsm6dso32x_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dso32x_den_lh_t val)6764 int32_t lsm6dso32x_den_polarity_set(const stmdev_ctx_t *ctx,
6765 lsm6dso32x_den_lh_t val)
6766 {
6767 lsm6dso32x_ctrl9_xl_t reg;
6768 int32_t ret;
6769
6770 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6771
6772 if (ret == 0)
6773 {
6774 reg.den_lh = (uint8_t)val;
6775 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6776 }
6777
6778 return ret;
6779 }
6780
6781 /**
6782 * @brief DEN active level configuration.[get]
6783 *
6784 * @param ctx read / write interface definitions
6785 * @param val Get the values of den_lh in reg CTRL9_XL
6786 * @retval interface status (MANDATORY: return 0 -> no Error).
6787 *
6788 */
lsm6dso32x_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dso32x_den_lh_t * val)6789 int32_t lsm6dso32x_den_polarity_get(const stmdev_ctx_t *ctx,
6790 lsm6dso32x_den_lh_t *val)
6791 {
6792 lsm6dso32x_ctrl9_xl_t reg;
6793 int32_t ret;
6794
6795 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6796
6797 switch (reg.den_lh)
6798 {
6799 case LSM6DSO32X_DEN_ACT_LOW:
6800 *val = LSM6DSO32X_DEN_ACT_LOW;
6801 break;
6802
6803 case LSM6DSO32X_DEN_ACT_HIGH:
6804 *val = LSM6DSO32X_DEN_ACT_HIGH;
6805 break;
6806
6807 default:
6808 *val = LSM6DSO32X_DEN_ACT_LOW;
6809 break;
6810 }
6811
6812 return ret;
6813 }
6814
6815 /**
6816 * @brief DEN enable.[set]
6817 *
6818 * @param ctx read / write interface definitions
6819 * @param val change the values of den_xl_g in reg CTRL9_XL
6820 * @retval interface status (MANDATORY: return 0 -> no Error).
6821 *
6822 */
lsm6dso32x_den_enable_set(const stmdev_ctx_t * ctx,lsm6dso32x_den_xl_g_t val)6823 int32_t lsm6dso32x_den_enable_set(const stmdev_ctx_t *ctx,
6824 lsm6dso32x_den_xl_g_t val)
6825 {
6826 lsm6dso32x_ctrl9_xl_t reg;
6827 int32_t ret;
6828
6829 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6830
6831 if (ret == 0)
6832 {
6833 reg.den_xl_g = (uint8_t)val;
6834 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6835 }
6836
6837 return ret;
6838 }
6839
6840 /**
6841 * @brief DEN enable.[get]
6842 *
6843 * @param ctx read / write interface definitions
6844 * @param val Get the values of den_xl_g in reg CTRL9_XL
6845 * @retval interface status (MANDATORY: return 0 -> no Error).
6846 *
6847 */
lsm6dso32x_den_enable_get(const stmdev_ctx_t * ctx,lsm6dso32x_den_xl_g_t * val)6848 int32_t lsm6dso32x_den_enable_get(const stmdev_ctx_t *ctx,
6849 lsm6dso32x_den_xl_g_t *val)
6850 {
6851 lsm6dso32x_ctrl9_xl_t reg;
6852 int32_t ret;
6853
6854 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6855
6856 switch (reg.den_xl_g)
6857 {
6858 case LSM6DSO32X_STAMP_IN_GY_DATA:
6859 *val = LSM6DSO32X_STAMP_IN_GY_DATA;
6860 break;
6861
6862 case LSM6DSO32X_STAMP_IN_XL_DATA:
6863 *val = LSM6DSO32X_STAMP_IN_XL_DATA;
6864 break;
6865
6866 case LSM6DSO32X_STAMP_IN_GY_XL_DATA:
6867 *val = LSM6DSO32X_STAMP_IN_GY_XL_DATA;
6868 break;
6869
6870 default:
6871 *val = LSM6DSO32X_STAMP_IN_GY_DATA;
6872 break;
6873 }
6874
6875 return ret;
6876 }
6877
6878 /**
6879 * @brief DEN value stored in LSB of X-axis.[set]
6880 *
6881 * @param ctx read / write interface definitions
6882 * @param val change the values of den_z in reg CTRL9_XL
6883 * @retval interface status (MANDATORY: return 0 -> no Error).
6884 *
6885 */
lsm6dso32x_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)6886 int32_t lsm6dso32x_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
6887 {
6888 lsm6dso32x_ctrl9_xl_t reg;
6889 int32_t ret;
6890
6891 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6892
6893 if (ret == 0)
6894 {
6895 reg.den_z = val;
6896 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6897 }
6898
6899 return ret;
6900 }
6901
6902 /**
6903 * @brief DEN value stored in LSB of X-axis.[get]
6904 *
6905 * @param ctx read / write interface definitions
6906 * @param val change the values of den_z in reg CTRL9_XL
6907 * @retval interface status (MANDATORY: return 0 -> no Error).
6908 *
6909 */
lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6910 int32_t lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t *ctx,
6911 uint8_t *val)
6912 {
6913 lsm6dso32x_ctrl9_xl_t reg;
6914 int32_t ret;
6915
6916 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6917 *val = reg.den_z;
6918
6919 return ret;
6920 }
6921
6922 /**
6923 * @brief DEN value stored in LSB of Y-axis.[set]
6924 *
6925 * @param ctx read / write interface definitions
6926 * @param val change the values of den_y in reg CTRL9_XL
6927 * @retval interface status (MANDATORY: return 0 -> no Error).
6928 *
6929 */
lsm6dso32x_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)6930 int32_t lsm6dso32x_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6931 {
6932 lsm6dso32x_ctrl9_xl_t reg;
6933 int32_t ret;
6934
6935 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6936
6937 if (ret == 0)
6938 {
6939 reg.den_y = val;
6940 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6941 }
6942
6943 return ret;
6944 }
6945
6946 /**
6947 * @brief DEN value stored in LSB of Y-axis.[get]
6948 *
6949 * @param ctx read / write interface definitions
6950 * @param val change the values of den_y in reg CTRL9_XL
6951 * @retval interface status (MANDATORY: return 0 -> no Error).
6952 *
6953 */
lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6954 int32_t lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t *ctx,
6955 uint8_t *val)
6956 {
6957 lsm6dso32x_ctrl9_xl_t reg;
6958 int32_t ret;
6959
6960 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6961 *val = reg.den_y;
6962
6963 return ret;
6964 }
6965
6966 /**
6967 * @brief DEN value stored in LSB of Z-axis.[set]
6968 *
6969 * @param ctx read / write interface definitions
6970 * @param val change the values of den_x in reg CTRL9_XL
6971 * @retval interface status (MANDATORY: return 0 -> no Error).
6972 *
6973 */
lsm6dso32x_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)6974 int32_t lsm6dso32x_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6975 {
6976 lsm6dso32x_ctrl9_xl_t reg;
6977 int32_t ret;
6978
6979 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6980
6981 if (ret == 0)
6982 {
6983 reg.den_x = val;
6984 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6985 }
6986
6987 return ret;
6988 }
6989
6990 /**
6991 * @brief DEN value stored in LSB of Z-axis.[get]
6992 *
6993 * @param ctx read / write interface definitions
6994 * @param val change the values of den_x in reg CTRL9_XL
6995 * @retval interface status (MANDATORY: return 0 -> no Error).
6996 *
6997 */
lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6998 int32_t lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t *ctx,
6999 uint8_t *val)
7000 {
7001 lsm6dso32x_ctrl9_xl_t reg;
7002 int32_t ret;
7003
7004 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
7005 *val = reg.den_x;
7006
7007 return ret;
7008 }
7009
7010 /**
7011 * @}
7012 *
7013 */
7014
7015 /**
7016 * @defgroup LSM6DSO32X_Pedometer
7017 * @brief This section groups all the functions that manage pedometer.
7018 * @{
7019 *
7020 */
7021
7022 /**
7023 * @brief Enable pedometer algorithm.[set]
7024 *
7025 * @param ctx read / write interface definitions
7026 * @param val turn on and configure pedometer
7027 * @retval interface status (MANDATORY: return 0 -> no Error).
7028 *
7029 */
lsm6dso32x_pedo_sens_set(const stmdev_ctx_t * ctx,lsm6dso32x_pedo_md_t val)7030 int32_t lsm6dso32x_pedo_sens_set(const stmdev_ctx_t *ctx,
7031 lsm6dso32x_pedo_md_t val)
7032 {
7033 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
7034 int32_t ret;
7035
7036 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7037 (uint8_t *)&pedo_cmd_reg);
7038
7039 if (ret == 0)
7040 {
7041 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
7042 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
7043 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7044 (uint8_t *)&pedo_cmd_reg);
7045 }
7046
7047 return ret;
7048 }
7049
7050 /**
7051 * @brief Enable pedometer algorithm.[get]
7052 *
7053 * @param ctx read / write interface definitions
7054 * @param val turn on and configure pedometer
7055 * @retval interface status (MANDATORY: return 0 -> no Error).
7056 *
7057 */
lsm6dso32x_pedo_sens_get(const stmdev_ctx_t * ctx,lsm6dso32x_pedo_md_t * val)7058 int32_t lsm6dso32x_pedo_sens_get(const stmdev_ctx_t *ctx,
7059 lsm6dso32x_pedo_md_t *val)
7060 {
7061 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
7062 int32_t ret;
7063
7064 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7065 (uint8_t *)&pedo_cmd_reg);
7066
7067 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
7068 << 4))
7069 {
7070 case LSM6DSO32X_PEDO_BASE_MODE:
7071 *val = LSM6DSO32X_PEDO_BASE_MODE;
7072 break;
7073
7074 case LSM6DSO32X_FALSE_STEP_REJ:
7075 *val = LSM6DSO32X_FALSE_STEP_REJ;
7076 break;
7077
7078 case LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE:
7079 *val = LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE;
7080 break;
7081
7082 default:
7083 *val = LSM6DSO32X_PEDO_BASE_MODE;
7084 break;
7085 }
7086
7087 return ret;
7088 }
7089
7090 /**
7091 * @brief Interrupt status bit for step detection.[get]
7092 *
7093 * @param ctx read / write interface definitions
7094 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
7095 * @retval interface status (MANDATORY: return 0 -> no Error).
7096 *
7097 */
lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)7098 int32_t lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t *ctx,
7099 uint8_t *val)
7100 {
7101 lsm6dso32x_emb_func_status_t reg;
7102 int32_t ret;
7103
7104 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7105
7106 if (ret == 0)
7107 {
7108 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7109 (uint8_t *)®, 1);
7110 }
7111
7112 if (ret == 0)
7113 {
7114 *val = reg.is_step_det;
7115 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7116 }
7117
7118 return ret;
7119 }
7120
7121 /**
7122 * @brief Pedometer debounce configuration register (r/w).[set]
7123 *
7124 * @param ctx read / write interface definitions
7125 * @param buff buffer that contains data to write
7126 * @retval interface status (MANDATORY: return 0 -> no Error).
7127 *
7128 */
lsm6dso32x_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)7129 int32_t lsm6dso32x_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
7130 uint8_t *buff)
7131 {
7132 int32_t ret;
7133
7134 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
7135 buff);
7136
7137 return ret;
7138 }
7139
7140 /**
7141 * @brief Pedometer debounce configuration register (r/w).[get]
7142 *
7143 * @param ctx read / write interface definitions
7144 * @param buff buffer that stores data read
7145 * @retval interface status (MANDATORY: return 0 -> no Error).
7146 *
7147 */
lsm6dso32x_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)7148 int32_t lsm6dso32x_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
7149 uint8_t *buff)
7150 {
7151 int32_t ret;
7152
7153 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
7154 buff);
7155
7156 return ret;
7157 }
7158
7159 /**
7160 * @brief Time period register for step detection on delta time (r/w).[set]
7161 *
7162 * @param ctx read / write interface definitions
7163 * @param buff buffer that contains data to write
7164 * @retval interface status (MANDATORY: return 0 -> no Error).
7165 *
7166 */
lsm6dso32x_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)7167 int32_t lsm6dso32x_pedo_steps_period_set(const stmdev_ctx_t *ctx,
7168 uint16_t val)
7169 {
7170 uint8_t buff[2];
7171 int32_t ret;
7172
7173 buff[1] = (uint8_t)(val / 256U);
7174 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7175 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
7176 &buff[0]);
7177
7178 if (ret == 0)
7179 {
7180 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
7181 &buff[1]);
7182 }
7183
7184 return ret;
7185 }
7186
7187 /**
7188 * @brief Time period register for step detection on delta time (r/w).[get]
7189 *
7190 * @param ctx read / write interface definitions
7191 * @param buff buffer that stores data read
7192 * @retval interface status (MANDATORY: return 0 -> no Error).
7193 *
7194 */
lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)7195 int32_t lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t *ctx,
7196 uint16_t *val)
7197 {
7198 uint8_t buff[2];
7199 int32_t ret;
7200
7201 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
7202 &buff[0]);
7203
7204 if (ret == 0)
7205 {
7206 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
7207 &buff[1]);
7208 *val = buff[1];
7209 *val = (*val * 256U) + buff[0];
7210 }
7211
7212 return ret;
7213 }
7214
7215 /**
7216 * @brief Set when user wants to generate interrupt on count overflow
7217 * event/every step.[set]
7218 *
7219 * @param ctx read / write interface definitions
7220 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
7221 * @retval interface status (MANDATORY: return 0 -> no Error).
7222 *
7223 */
lsm6dso32x_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_carry_count_en_t val)7224 int32_t lsm6dso32x_pedo_int_mode_set(const stmdev_ctx_t *ctx,
7225 lsm6dso32x_carry_count_en_t val)
7226 {
7227 lsm6dso32x_pedo_cmd_reg_t reg;
7228 int32_t ret;
7229
7230 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7231 (uint8_t *)®);
7232
7233 if (ret == 0)
7234 {
7235 reg.carry_count_en = (uint8_t)val;
7236 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7237 (uint8_t *)®);
7238 }
7239
7240 return ret;
7241 }
7242
7243 /**
7244 * @brief Set when user wants to generate interrupt on count overflow
7245 * event/every step.[get]
7246 *
7247 * @param ctx read / write interface definitions
7248 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
7249 * @retval interface status (MANDATORY: return 0 -> no Error).
7250 *
7251 */
lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_carry_count_en_t * val)7252 int32_t lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t *ctx,
7253 lsm6dso32x_carry_count_en_t *val)
7254 {
7255 lsm6dso32x_pedo_cmd_reg_t reg;
7256 int32_t ret;
7257
7258 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7259 (uint8_t *)®);
7260
7261 switch (reg.carry_count_en)
7262 {
7263 case LSM6DSO32X_EVERY_STEP:
7264 *val = LSM6DSO32X_EVERY_STEP;
7265 break;
7266
7267 case LSM6DSO32X_COUNT_OVERFLOW:
7268 *val = LSM6DSO32X_COUNT_OVERFLOW;
7269 break;
7270
7271 default:
7272 *val = LSM6DSO32X_EVERY_STEP;
7273 break;
7274 }
7275
7276 return ret;
7277 }
7278
7279 /**
7280 * @}
7281 *
7282 */
7283
7284 /**
7285 * @defgroup LSM6DSO32X_significant_motion
7286 * @brief This section groups all the functions that manage the
7287 * significant motion detection.
7288 * @{
7289 *
7290 */
7291
7292 /**
7293 * @brief Interrupt status bit for significant motion detection.[get]
7294 *
7295 * @param ctx read / write interface definitions
7296 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
7297 * @retval interface status (MANDATORY: return 0 -> no Error).
7298 *
7299 */
lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7300 int32_t lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
7301 uint8_t *val)
7302 {
7303 lsm6dso32x_emb_func_status_t reg;
7304 int32_t ret;
7305
7306 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7307
7308 if (ret == 0)
7309 {
7310 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7311 (uint8_t *)®, 1);
7312 }
7313
7314 if (ret == 0)
7315 {
7316 *val = reg.is_sigmot;
7317 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7318 }
7319
7320 return ret;
7321 }
7322
7323 /**
7324 * @}
7325 *
7326 */
7327
7328 /**
7329 * @defgroup LSM6DSO32X_tilt_detection
7330 * @brief This section groups all the functions that manage the tilt
7331 * event detection.
7332 * @{
7333 *
7334 */
7335
7336 /**
7337 * @brief Interrupt status bit for tilt detection.[get]
7338 *
7339 * @param ctx read / write interface definitions
7340 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
7341 * @retval interface status (MANDATORY: return 0 -> no Error).
7342 *
7343 */
lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7344 int32_t lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
7345 uint8_t *val)
7346 {
7347 lsm6dso32x_emb_func_status_t reg;
7348 int32_t ret;
7349
7350 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7351
7352 if (ret == 0)
7353 {
7354 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7355 (uint8_t *)®, 1);
7356 }
7357
7358 if (ret == 0)
7359 {
7360 *val = reg.is_tilt;
7361 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7362 }
7363
7364 return ret;
7365 }
7366
7367 /**
7368 * @}
7369 *
7370 */
7371
7372 /**
7373 * @defgroup LSM6DSO32X_ magnetometer_sensor
7374 * @brief This section groups all the functions that manage additional
7375 * magnetometer sensor.
7376 * @{
7377 *
7378 */
7379
7380 /**
7381 * @brief External magnetometer sensitivity value register for
7382 * Sensor hub.[set]
7383 *
7384 * @param ctx read / write interface definitions
7385 * @param buff buffer that contains data to write
7386 * @retval interface status (MANDATORY: return 0 -> no Error).
7387 *
7388 */
lsm6dso32x_sh_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7389 int32_t lsm6dso32x_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx,
7390 uint16_t val)
7391 {
7392 uint8_t buff[2];
7393 int32_t ret;
7394
7395 buff[1] = (uint8_t)(val / 256U);
7396 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7397 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
7398 &buff[0]);
7399
7400 if (ret == 0)
7401 {
7402 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
7403 &buff[1]);
7404 }
7405
7406 return ret;
7407 }
7408
7409 /**
7410 * @brief External magnetometer sensitivity value register for
7411 * Sensor hub.[get]
7412 *
7413 * @param ctx read / write interface definitions
7414 * @param buff buffer that stores data read
7415 * @retval interface status (MANDATORY: return 0 -> no Error).
7416 *
7417 */
lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7418 int32_t lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx,
7419 uint16_t *val)
7420 {
7421 uint8_t buff[2];
7422 int32_t ret;
7423
7424 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
7425 &buff[0]);
7426
7427 if (ret == 0)
7428 {
7429 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
7430 &buff[1]);
7431 *val = buff[1];
7432 *val = (*val * 256U) + buff[0];
7433 }
7434
7435 return ret;
7436 }
7437
7438 /**
7439 * @brief External magnetometer sensitivity value register for
7440 * Machine Learning Core.[set]
7441 *
7442 * @param ctx read / write interface definitions
7443 * @param buff buffer that contains data to write
7444 * @retval interface status (MANDATORY: return 0 -> no Error).
7445 *
7446 */
lsm6dso32x_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7447 int32_t lsm6dso32x_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx,
7448 uint16_t val)
7449 {
7450 uint8_t buff[2];
7451 int32_t ret;
7452
7453 buff[1] = (uint8_t)(val / 256U);
7454 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7455 ret = lsm6dso32x_ln_pg_write_byte(ctx,
7456 LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
7457 &buff[0]);
7458
7459 if (ret == 0)
7460 {
7461 ret = lsm6dso32x_ln_pg_write_byte(ctx,
7462 LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
7463 &buff[1]);
7464 }
7465
7466 return ret;
7467 }
7468
7469 /**
7470 * @brief External magnetometer sensitivity value register for
7471 * Machine Learning Core.[get]
7472 *
7473 * @param ctx read / write interface definitions
7474 * @param buff buffer that stores data read
7475 * @retval interface status (MANDATORY: return 0 -> no Error).
7476 *
7477 */
lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7478 int32_t lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx,
7479 uint16_t *val)
7480 {
7481 uint8_t buff[2];
7482 int32_t ret;
7483
7484 ret = lsm6dso32x_ln_pg_read_byte(ctx,
7485 LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
7486 &buff[0]);
7487
7488 if (ret == 0)
7489 {
7490 ret = lsm6dso32x_ln_pg_read_byte(ctx,
7491 LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
7492 &buff[1]);
7493 *val = buff[1];
7494 *val = (*val * 256U) + buff[0];
7495 }
7496
7497 return ret;
7498 }
7499
7500
7501 /**
7502 * @brief Offset for hard-iron compensation register (r/w).[set]
7503 *
7504 * @param ctx read / write interface definitions
7505 * @param buff buffer that contains data to write
7506 * @retval interface status (MANDATORY: return 0 -> no Error).
7507 *
7508 */
lsm6dso32x_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)7509 int32_t lsm6dso32x_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
7510 {
7511 uint8_t buff[6];
7512 int32_t ret;
7513
7514 uint8_t i;
7515 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7516 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7517 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7518 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7519 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7520 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7521 i = 0x00U;
7522 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
7523 &buff[i]);
7524
7525 if (ret == 0)
7526 {
7527 i++;
7528 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
7529 &buff[i]);
7530 }
7531
7532 if (ret == 0)
7533 {
7534 i++;
7535 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
7536 &buff[i]);
7537 }
7538
7539 if (ret == 0)
7540 {
7541 i++;
7542 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
7543 &buff[i]);
7544 }
7545
7546 if (ret == 0)
7547 {
7548 i++;
7549 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
7550 &buff[i]);
7551 }
7552
7553 if (ret == 0)
7554 {
7555 i++;
7556 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
7557 &buff[i]);
7558 }
7559
7560 return ret;
7561 }
7562
7563 /**
7564 * @brief Offset for hard-iron compensation register (r/w).[get]
7565 *
7566 * @param ctx read / write interface definitions
7567 * @param buff buffer that stores data read
7568 * @retval interface status (MANDATORY: return 0 -> no Error).
7569 *
7570 */
lsm6dso32x_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)7571 int32_t lsm6dso32x_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
7572 {
7573 uint8_t buff[6];
7574 int32_t ret;
7575
7576 uint8_t i;
7577 i = 0x00U;
7578 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
7579 &buff[i]);
7580
7581 if (ret == 0)
7582 {
7583 i++;
7584 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
7585 &buff[i]);
7586 }
7587
7588 if (ret == 0)
7589 {
7590 i++;
7591 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
7592 &buff[i]);
7593 }
7594
7595 if (ret == 0)
7596 {
7597 i++;
7598 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
7599 &buff[i]);
7600 }
7601
7602 if (ret == 0)
7603 {
7604 i++;
7605 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
7606 &buff[i]);
7607 }
7608
7609 if (ret == 0)
7610 {
7611 i++;
7612 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
7613 &buff[i]);
7614 }
7615
7616 val[0] = (int16_t)buff[1];
7617 val[0] = (val[0] * 256) + (int16_t)buff[0];
7618 val[1] = (int16_t)buff[3];
7619 val[1] = (val[1] * 256) + (int16_t)buff[2];
7620 val[2] = (int16_t)buff[5];
7621 val[2] = (val[2] * 256) + (int16_t)buff[4];
7622
7623 return ret;
7624 }
7625
7626 /**
7627 * @brief Soft-iron (3x3 symmetric) matrix correction
7628 * register (r/w). The value is expressed as
7629 * half-precision floating-point format:
7630 * SEEEEEFFFFFFFFFF
7631 * S: 1 sign bit;
7632 * E: 5 exponent bits;
7633 * F: 10 fraction bits).[set]
7634 *
7635 * @param ctx read / write interface definitions
7636 * @param buff buffer that contains data to write
7637 * @retval interface status (MANDATORY: return 0 -> no Error).
7638 *
7639 */
lsm6dso32x_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)7640 int32_t lsm6dso32x_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
7641 {
7642 uint8_t buff[12];
7643 uint8_t index;
7644 int32_t ret;
7645
7646 buff[1] = (uint8_t)(val[0] / 256U);
7647 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
7648 buff[3] = (uint8_t)(val[1] / 256U);
7649 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
7650 buff[5] = (uint8_t)(val[2] / 256U);
7651 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
7652 buff[7] = (uint8_t)(val[3] / 256U);
7653 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
7654 buff[9] = (uint8_t)(val[4] / 256U);
7655 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
7656 buff[11] = (uint8_t)(val[5] / 256U);
7657 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
7658 index = 0x00U;
7659 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
7660 &buff[index]);
7661
7662 if (ret == 0)
7663 {
7664 index++;
7665 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
7666 &buff[index]);
7667 }
7668
7669 if (ret == 0)
7670 {
7671 index++;
7672 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
7673 &buff[index]);
7674 }
7675
7676 if (ret == 0)
7677 {
7678 index++;
7679 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
7680 &buff[index]);
7681 }
7682
7683 if (ret == 0)
7684 {
7685 index++;
7686 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
7687 &buff[index]);
7688 }
7689
7690 if (ret == 0)
7691 {
7692 index++;
7693 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
7694 &buff[index]);
7695 }
7696
7697 if (ret == 0)
7698 {
7699 index++;
7700 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
7701 &buff[index]);
7702 }
7703
7704 if (ret == 0)
7705 {
7706 index++;
7707 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
7708 &buff[index]);
7709 }
7710
7711 if (ret == 0)
7712 {
7713 index++;
7714 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
7715 &buff[index]);
7716 }
7717
7718 if (ret == 0)
7719 {
7720 index++;
7721 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
7722 &buff[index]);
7723 }
7724
7725 if (ret == 0)
7726 {
7727 index++;
7728 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
7729 &buff[index]);
7730 }
7731
7732 if (ret == 0)
7733 {
7734 index++;
7735 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
7736 &buff[index]);
7737 }
7738
7739 return ret;
7740 }
7741
7742 /**
7743 * @brief Soft-iron (3x3 symmetric) matrix
7744 * correction register (r/w).
7745 * The value is expressed as half-precision
7746 * floating-point format:
7747 * SEEEEEFFFFFFFFFF
7748 * S: 1 sign bit;
7749 * E: 5 exponent bits;
7750 * F: 10 fraction bits.[get]
7751 *
7752 * @param ctx read / write interface definitions
7753 * @param buff buffer that stores data read
7754 * @retval interface status (MANDATORY: return 0 -> no Error).
7755 *
7756 */
lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)7757 int32_t lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
7758 {
7759 uint8_t buff[12];
7760 uint8_t index;
7761 int32_t ret;
7762
7763 index = 0x00U;
7764 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
7765 &buff[index]);
7766
7767 if (ret == 0)
7768 {
7769 index++;
7770 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
7771 &buff[index]);
7772 }
7773
7774 if (ret == 0)
7775 {
7776 index++;
7777 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
7778 &buff[index]);
7779 }
7780
7781 if (ret == 0)
7782 {
7783 index++;
7784 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
7785 &buff[index]);
7786 }
7787
7788 if (ret == 0)
7789 {
7790 index++;
7791 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
7792 &buff[index]);
7793 }
7794
7795 if (ret == 0)
7796 {
7797 index++;
7798 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
7799 &buff[index]);
7800 }
7801
7802 if (ret == 0)
7803 {
7804 index++;
7805 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
7806 &buff[index]);
7807 }
7808
7809 if (ret == 0)
7810 {
7811 index++;
7812 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
7813 &buff[index]);
7814 }
7815
7816 if (ret == 0)
7817 {
7818 index++;
7819 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
7820 &buff[index]);
7821 }
7822
7823 if (ret == 0)
7824 {
7825 index++;
7826 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
7827 &buff[index]);
7828 }
7829
7830 if (ret == 0)
7831 {
7832 index++;
7833 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
7834 &buff[index]);
7835 }
7836
7837 if (ret == 0)
7838 {
7839 index++;
7840 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
7841 &buff[index]);
7842 }
7843
7844 val[0] = buff[1];
7845 val[0] = (val[0] * 256U) + buff[0];
7846 val[1] = buff[3];
7847 val[1] = (val[1] * 256U) + buff[2];
7848 val[2] = buff[5];
7849 val[2] = (val[2] * 256U) + buff[4];
7850 val[3] = buff[7];
7851 val[3] = (val[3] * 256U) + buff[6];
7852 val[4] = buff[9];
7853 val[4] = (val[4] * 256U) + buff[8];
7854 val[5] = buff[11];
7855 val[6] = (val[5] * 256U) + buff[10];
7856
7857 return ret;
7858 }
7859
7860 /**
7861 * @brief Magnetometer Z-axis coordinates
7862 * rotation (to be aligned to
7863 * accelerometer/gyroscope axes
7864 * orientation).[set]
7865 *
7866 * @param ctx read / write interface definitions
7867 * @param val change the values of mag_z_axis in reg MAG_CFG_A
7868 * @retval interface status (MANDATORY: return 0 -> no Error).
7869 *
7870 */
lsm6dso32x_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dso32x_mag_z_axis_t val)7871 int32_t lsm6dso32x_mag_z_orient_set(const stmdev_ctx_t *ctx,
7872 lsm6dso32x_mag_z_axis_t val)
7873 {
7874 lsm6dso32x_mag_cfg_a_t reg;
7875 int32_t ret;
7876
7877 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7878 (uint8_t *)®);
7879
7880 if (ret == 0)
7881 {
7882 reg.mag_z_axis = (uint8_t) val;
7883 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7884 (uint8_t *)®);
7885 }
7886
7887 return ret;
7888 }
7889
7890 /**
7891 * @brief Magnetometer Z-axis coordinates
7892 * rotation (to be aligned to
7893 * accelerometer/gyroscope axes
7894 * orientation).[get]
7895 *
7896 * @param ctx read / write interface definitions
7897 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
7898 * @retval interface status (MANDATORY: return 0 -> no Error).
7899 *
7900 */
lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dso32x_mag_z_axis_t * val)7901 int32_t lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t *ctx,
7902 lsm6dso32x_mag_z_axis_t *val)
7903 {
7904 lsm6dso32x_mag_cfg_a_t reg;
7905 int32_t ret;
7906
7907 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7908 (uint8_t *)®);
7909
7910 switch (reg.mag_z_axis)
7911 {
7912 case LSM6DSO32X_Z_EQ_Y:
7913 *val = LSM6DSO32X_Z_EQ_Y;
7914 break;
7915
7916 case LSM6DSO32X_Z_EQ_MIN_Y:
7917 *val = LSM6DSO32X_Z_EQ_MIN_Y;
7918 break;
7919
7920 case LSM6DSO32X_Z_EQ_X:
7921 *val = LSM6DSO32X_Z_EQ_X;
7922 break;
7923
7924 case LSM6DSO32X_Z_EQ_MIN_X:
7925 *val = LSM6DSO32X_Z_EQ_MIN_X;
7926 break;
7927
7928 case LSM6DSO32X_Z_EQ_MIN_Z:
7929 *val = LSM6DSO32X_Z_EQ_MIN_Z;
7930 break;
7931
7932 case LSM6DSO32X_Z_EQ_Z:
7933 *val = LSM6DSO32X_Z_EQ_Z;
7934 break;
7935
7936 default:
7937 *val = LSM6DSO32X_Z_EQ_Y;
7938 break;
7939 }
7940
7941 return ret;
7942 }
7943
7944 /**
7945 * @brief Magnetometer Y-axis coordinates
7946 * rotation (to be aligned to
7947 * accelerometer/gyroscope axes
7948 * orientation).[set]
7949 *
7950 * @param ctx read / write interface definitions
7951 * @param val change the values of mag_y_axis in reg MAG_CFG_A
7952 * @retval interface status (MANDATORY: return 0 -> no Error).
7953 *
7954 */
lsm6dso32x_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dso32x_mag_y_axis_t val)7955 int32_t lsm6dso32x_mag_y_orient_set(const stmdev_ctx_t *ctx,
7956 lsm6dso32x_mag_y_axis_t val)
7957 {
7958 lsm6dso32x_mag_cfg_a_t reg;
7959 int32_t ret;
7960
7961 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7962 (uint8_t *)®);
7963
7964 if (ret == 0)
7965 {
7966 reg.mag_y_axis = (uint8_t)val;
7967 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7968 (uint8_t *) ®);
7969 }
7970
7971 return ret;
7972 }
7973
7974 /**
7975 * @brief Magnetometer Y-axis coordinates
7976 * rotation (to be aligned to
7977 * accelerometer/gyroscope axes
7978 * orientation).[get]
7979 *
7980 * @param ctx read / write interface definitions
7981 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
7982 * @retval interface status (MANDATORY: return 0 -> no Error).
7983 *
7984 */
lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dso32x_mag_y_axis_t * val)7985 int32_t lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t *ctx,
7986 lsm6dso32x_mag_y_axis_t *val)
7987 {
7988 lsm6dso32x_mag_cfg_a_t reg;
7989 int32_t ret;
7990
7991 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7992 (uint8_t *)®);
7993
7994 switch (reg.mag_y_axis)
7995 {
7996 case LSM6DSO32X_Y_EQ_Y:
7997 *val = LSM6DSO32X_Y_EQ_Y;
7998 break;
7999
8000 case LSM6DSO32X_Y_EQ_MIN_Y:
8001 *val = LSM6DSO32X_Y_EQ_MIN_Y;
8002 break;
8003
8004 case LSM6DSO32X_Y_EQ_X:
8005 *val = LSM6DSO32X_Y_EQ_X;
8006 break;
8007
8008 case LSM6DSO32X_Y_EQ_MIN_X:
8009 *val = LSM6DSO32X_Y_EQ_MIN_X;
8010 break;
8011
8012 case LSM6DSO32X_Y_EQ_MIN_Z:
8013 *val = LSM6DSO32X_Y_EQ_MIN_Z;
8014 break;
8015
8016 case LSM6DSO32X_Y_EQ_Z:
8017 *val = LSM6DSO32X_Y_EQ_Z;
8018 break;
8019
8020 default:
8021 *val = LSM6DSO32X_Y_EQ_Y;
8022 break;
8023 }
8024
8025 return ret;
8026 }
8027
8028 /**
8029 * @brief Magnetometer X-axis coordinates
8030 * rotation (to be aligned to
8031 * accelerometer/gyroscope axes
8032 * orientation).[set]
8033 *
8034 * @param ctx read / write interface definitions
8035 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8036 * @retval interface status (MANDATORY: return 0 -> no Error).
8037 *
8038 */
lsm6dso32x_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dso32x_mag_x_axis_t val)8039 int32_t lsm6dso32x_mag_x_orient_set(const stmdev_ctx_t *ctx,
8040 lsm6dso32x_mag_x_axis_t val)
8041 {
8042 lsm6dso32x_mag_cfg_b_t reg;
8043 int32_t ret;
8044
8045 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8046 (uint8_t *)®);
8047
8048 if (ret == 0)
8049 {
8050 reg.mag_x_axis = (uint8_t)val;
8051 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8052 (uint8_t *)®);
8053 }
8054
8055 return ret;
8056 }
8057
8058 /**
8059 * @brief Magnetometer X-axis coordinates
8060 * rotation (to be aligned to
8061 * accelerometer/gyroscope axes
8062 * orientation).[get]
8063 *
8064 * @param ctx read / write interface definitions
8065 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8066 * @retval interface status (MANDATORY: return 0 -> no Error).
8067 *
8068 */
lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dso32x_mag_x_axis_t * val)8069 int32_t lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t *ctx,
8070 lsm6dso32x_mag_x_axis_t *val)
8071 {
8072 lsm6dso32x_mag_cfg_b_t reg;
8073 int32_t ret;
8074
8075 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8076 (uint8_t *)®);
8077
8078 switch (reg.mag_x_axis)
8079 {
8080 case LSM6DSO32X_X_EQ_Y:
8081 *val = LSM6DSO32X_X_EQ_Y;
8082 break;
8083
8084 case LSM6DSO32X_X_EQ_MIN_Y:
8085 *val = LSM6DSO32X_X_EQ_MIN_Y;
8086 break;
8087
8088 case LSM6DSO32X_X_EQ_X:
8089 *val = LSM6DSO32X_X_EQ_X;
8090 break;
8091
8092 case LSM6DSO32X_X_EQ_MIN_X:
8093 *val = LSM6DSO32X_X_EQ_MIN_X;
8094 break;
8095
8096 case LSM6DSO32X_X_EQ_MIN_Z:
8097 *val = LSM6DSO32X_X_EQ_MIN_Z;
8098 break;
8099
8100 case LSM6DSO32X_X_EQ_Z:
8101 *val = LSM6DSO32X_X_EQ_Z;
8102 break;
8103
8104 default:
8105 *val = LSM6DSO32X_X_EQ_Y;
8106 break;
8107 }
8108
8109 return ret;
8110 }
8111
8112 /**
8113 * @}
8114 *
8115 */
8116
8117 /**
8118 * @defgroup LSM6DSO32X_finite_state_machine
8119 * @brief This section groups all the functions that manage the
8120 * state_machine.
8121 * @{
8122 *
8123 */
8124
8125 /**
8126 * @brief Interrupt status bit for FSM long counter
8127 * timeout interrupt event.[get]
8128 *
8129 * @param ctx read / write interface definitions
8130 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
8131 * @retval interface status (MANDATORY: return 0 -> no Error).
8132 *
8133 */
lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8134 int32_t lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
8135 uint8_t *val)
8136 {
8137 lsm6dso32x_emb_func_status_t reg;
8138 int32_t ret;
8139
8140 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8141
8142 if (ret == 0)
8143 {
8144 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
8145 (uint8_t *)®, 1);
8146 }
8147
8148 if (ret == 0)
8149 {
8150 *val = reg.is_fsm_lc;
8151 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8152 }
8153
8154 return ret;
8155 }
8156
8157 /**
8158 * @brief Finite State Machine enable.[set]
8159 *
8160 * @param ctx read / write interface definitions
8161 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8162 * @retval interface status (MANDATORY: return 0 -> no Error).
8163 *
8164 */
lsm6dso32x_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dso32x_emb_fsm_enable_t * val)8165 int32_t lsm6dso32x_fsm_enable_set(const stmdev_ctx_t *ctx,
8166 lsm6dso32x_emb_fsm_enable_t *val)
8167 {
8168 int32_t ret;
8169
8170 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8171
8172 if (ret == 0)
8173 {
8174 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
8175 (uint8_t *)&val->fsm_enable_a, 1);
8176 }
8177
8178 if (ret == 0)
8179 {
8180 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_B,
8181 (uint8_t *)&val->fsm_enable_b, 1);
8182 }
8183
8184 if (ret == 0)
8185 {
8186 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8187 }
8188
8189 return ret;
8190 }
8191
8192 /**
8193 * @brief Finite State Machine enable.[get]
8194 *
8195 * @param ctx read / write interface definitions
8196 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8197 * @retval interface status (MANDATORY: return 0 -> no Error).
8198 *
8199 */
lsm6dso32x_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dso32x_emb_fsm_enable_t * val)8200 int32_t lsm6dso32x_fsm_enable_get(const stmdev_ctx_t *ctx,
8201 lsm6dso32x_emb_fsm_enable_t *val)
8202 {
8203 int32_t ret;
8204
8205 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8206
8207 if (ret == 0)
8208 {
8209 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
8210 (uint8_t *) val,
8211 2);
8212 }
8213
8214 if (ret == 0)
8215 {
8216 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8217 }
8218
8219 return ret;
8220 }
8221
8222 /**
8223 * @brief FSM long counter status register. Long counter value is an
8224 * unsigned integer value (16-bit format).[set]
8225 *
8226 * @param ctx read / write interface definitions
8227 * @param buff buffer that contains data to write
8228 * @retval interface status (MANDATORY: return 0 -> no Error).
8229 *
8230 */
lsm6dso32x_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)8231 int32_t lsm6dso32x_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
8232 {
8233 uint8_t buff[2];
8234 int32_t ret;
8235
8236 buff[1] = (uint8_t)(val / 256U);
8237 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8238 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8239
8240 if (ret == 0)
8241 {
8242 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
8243 2);
8244 }
8245
8246 if (ret == 0)
8247 {
8248 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8249 }
8250
8251 return ret;
8252 }
8253
8254 /**
8255 * @brief FSM long counter status register. Long counter value is an
8256 * unsigned integer value (16-bit format).[get]
8257 *
8258 * @param ctx read / write interface definitions
8259 * @param buff buffer that stores data read
8260 * @retval interface status (MANDATORY: return 0 -> no Error).
8261 *
8262 */
lsm6dso32x_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)8263 int32_t lsm6dso32x_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
8264 {
8265 uint8_t buff[2];
8266 int32_t ret;
8267
8268 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8269
8270 if (ret == 0)
8271 {
8272 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
8273 2);
8274 *val = buff[1];
8275 *val = (*val * 256U) + buff[0];
8276 }
8277
8278 if (ret == 0)
8279 {
8280 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8281 }
8282
8283 return ret;
8284 }
8285
8286 /**
8287 * @brief Clear FSM long counter value.[set]
8288 *
8289 * @param ctx read / write interface definitions
8290 * @param val change the values of fsm_lc_clr in
8291 * reg FSM_LONG_COUNTER_CLEAR
8292 * @retval interface status (MANDATORY: return 0 -> no Error).
8293 *
8294 */
lsm6dso32x_long_clr_set(const stmdev_ctx_t * ctx,lsm6dso32x_fsm_lc_clr_t val)8295 int32_t lsm6dso32x_long_clr_set(const stmdev_ctx_t *ctx,
8296 lsm6dso32x_fsm_lc_clr_t val)
8297 {
8298 lsm6dso32x_fsm_long_counter_clear_t reg;
8299 int32_t ret;
8300
8301 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8302
8303 if (ret == 0)
8304 {
8305 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8306 (uint8_t *)®, 1);
8307 }
8308
8309 if (ret == 0)
8310 {
8311 reg. fsm_lc_clr = (uint8_t)val;
8312 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8313 (uint8_t *)®, 1);
8314 }
8315
8316 if (ret == 0)
8317 {
8318 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8319 }
8320
8321 return ret;
8322 }
8323
8324 /**
8325 * @brief Clear FSM long counter value.[get]
8326 *
8327 * @param ctx read / write interface definitions
8328 * @param val Get the values of fsm_lc_clr in
8329 * reg FSM_LONG_COUNTER_CLEAR
8330 * @retval interface status (MANDATORY: return 0 -> no Error).
8331 *
8332 */
lsm6dso32x_long_clr_get(const stmdev_ctx_t * ctx,lsm6dso32x_fsm_lc_clr_t * val)8333 int32_t lsm6dso32x_long_clr_get(const stmdev_ctx_t *ctx,
8334 lsm6dso32x_fsm_lc_clr_t *val)
8335 {
8336 lsm6dso32x_fsm_long_counter_clear_t reg;
8337 int32_t ret;
8338
8339 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8340
8341 if (ret == 0)
8342 {
8343 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8344 (uint8_t *)®, 1);
8345 }
8346
8347 if (ret == 0)
8348 {
8349 switch (reg.fsm_lc_clr)
8350 {
8351 case LSM6DSO32X_LC_NORMAL:
8352 *val = LSM6DSO32X_LC_NORMAL;
8353 break;
8354
8355 case LSM6DSO32X_LC_CLEAR:
8356 *val = LSM6DSO32X_LC_CLEAR;
8357 break;
8358
8359 case LSM6DSO32X_LC_CLEAR_DONE:
8360 *val = LSM6DSO32X_LC_CLEAR_DONE;
8361 break;
8362
8363 default:
8364 *val = LSM6DSO32X_LC_NORMAL;
8365 break;
8366 }
8367 }
8368
8369 if (ret == 0)
8370 {
8371 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8372 }
8373
8374 return ret;
8375 }
8376
8377 /**
8378 * @brief FSM output registers[get]
8379 *
8380 * @param ctx read / write interface definitions
8381 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
8382 * @retval interface status (MANDATORY: return 0 -> no Error).
8383 *
8384 */
lsm6dso32x_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dso32x_fsm_out_t * val)8385 int32_t lsm6dso32x_fsm_out_get(const stmdev_ctx_t *ctx,
8386 lsm6dso32x_fsm_out_t *val)
8387 {
8388 int32_t ret;
8389
8390 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8391
8392 if (ret == 0)
8393 {
8394 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_OUTS1, (uint8_t *)val,
8395 16);
8396 }
8397
8398 if (ret == 0)
8399 {
8400 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8401 }
8402
8403 return ret;
8404 }
8405
8406 /**
8407 * @brief Finite State Machine ODR configuration.[set]
8408 *
8409 * @param ctx read / write interface definitions
8410 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8411 * @retval interface status (MANDATORY: return 0 -> no Error).
8412 *
8413 */
lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32x_fsm_odr_t val)8414 int32_t lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t *ctx,
8415 lsm6dso32x_fsm_odr_t val)
8416 {
8417 lsm6dso32x_emb_func_odr_cfg_b_t reg;
8418 int32_t ret;
8419
8420 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8421
8422 if (ret == 0)
8423 {
8424 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8425 (uint8_t *)®, 1);
8426 }
8427
8428 if (ret == 0)
8429 {
8430 reg.not_used_01 = 3; /* set default values */
8431 reg.not_used_02 = 2; /* set default values */
8432 reg.fsm_odr = (uint8_t)val;
8433 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8434 (uint8_t *)®, 1);
8435 }
8436
8437 if (ret == 0)
8438 {
8439 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8440 }
8441
8442 return ret;
8443 }
8444
8445 /**
8446 * @brief Finite State Machine ODR configuration.[get]
8447 *
8448 * @param ctx read / write interface definitions
8449 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8450 * @retval interface status (MANDATORY: return 0 -> no Error).
8451 *
8452 */
lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32x_fsm_odr_t * val)8453 int32_t lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t *ctx,
8454 lsm6dso32x_fsm_odr_t *val)
8455 {
8456 lsm6dso32x_emb_func_odr_cfg_b_t reg;
8457 int32_t ret;
8458
8459 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8460
8461 if (ret == 0)
8462 {
8463 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8464 (uint8_t *)®, 1);
8465 }
8466
8467 if (ret == 0)
8468 {
8469 switch (reg.fsm_odr)
8470 {
8471 case LSM6DSO32X_ODR_FSM_12Hz5:
8472 *val = LSM6DSO32X_ODR_FSM_12Hz5;
8473 break;
8474
8475 case LSM6DSO32X_ODR_FSM_26Hz:
8476 *val = LSM6DSO32X_ODR_FSM_26Hz;
8477 break;
8478
8479 case LSM6DSO32X_ODR_FSM_52Hz:
8480 *val = LSM6DSO32X_ODR_FSM_52Hz;
8481 break;
8482
8483 case LSM6DSO32X_ODR_FSM_104Hz:
8484 *val = LSM6DSO32X_ODR_FSM_104Hz;
8485 break;
8486
8487 default:
8488 *val = LSM6DSO32X_ODR_FSM_12Hz5;
8489 break;
8490 }
8491
8492 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8493 }
8494
8495 return ret;
8496 }
8497
8498 /**
8499 * @brief FSM initialization request.[set]
8500 *
8501 * @param ctx read / write interface definitions
8502 * @param val change the values of fsm_init in reg FSM_INIT
8503 * @retval interface status (MANDATORY: return 0 -> no Error).
8504 *
8505 */
lsm6dso32x_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)8506 int32_t lsm6dso32x_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
8507 {
8508 lsm6dso32x_emb_func_init_b_t reg;
8509 int32_t ret;
8510
8511 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8512
8513 if (ret == 0)
8514 {
8515 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8516 (uint8_t *)®, 1);
8517 }
8518
8519 if (ret == 0)
8520 {
8521 reg.fsm_init = val;
8522 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8523 (uint8_t *)®, 1);
8524 }
8525
8526 if (ret == 0)
8527 {
8528 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8529 }
8530
8531 return ret;
8532 }
8533
8534 /**
8535 * @brief FSM initialization request.[get]
8536 *
8537 * @param ctx read / write interface definitions
8538 * @param val change the values of fsm_init in reg FSM_INIT
8539 * @retval interface status (MANDATORY: return 0 -> no Error).
8540 *
8541 */
lsm6dso32x_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)8542 int32_t lsm6dso32x_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
8543 {
8544 lsm6dso32x_emb_func_init_b_t reg;
8545 int32_t ret;
8546
8547 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8548
8549 if (ret == 0)
8550 {
8551 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8552 (uint8_t *)®, 1);
8553 }
8554
8555 if (ret == 0)
8556 {
8557 *val = reg.fsm_init;
8558 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8559 }
8560
8561 return ret;
8562 }
8563
8564 /**
8565 * @brief FSM long counter timeout register (r/w). The long counter
8566 * timeout value is an unsigned integer value (16-bit format).
8567 * When the long counter value reached this value,
8568 * the FSM generates an interrupt.[set]
8569 *
8570 * @param ctx read / write interface definitions
8571 * @param val the value of long counter
8572 * @retval interface status (MANDATORY: return 0 -> no Error).
8573 *
8574 */
lsm6dso32x_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)8575 int32_t lsm6dso32x_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
8576 uint16_t val)
8577 {
8578 int32_t ret;
8579
8580 uint8_t add_l;
8581 uint8_t add_h;
8582 add_h = (uint8_t)((val & 0xFF00U) >> 8);
8583 add_l = (uint8_t)(val & 0x00FFU);
8584 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
8585 &add_l);
8586
8587 if (ret == 0)
8588 {
8589 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
8590 &add_h);
8591 }
8592
8593 return ret;
8594 }
8595
8596 /**
8597 * @brief FSM long counter timeout register (r/w). The long counter
8598 * timeout value is an unsigned integer value (16-bit format).
8599 * When the long counter value reached this value,
8600 * the FSM generates an interrupt.[get]
8601 *
8602 * @param ctx read / write interface definitions
8603 * @param val buffer that stores the value of long counter
8604 * @retval interface status (MANDATORY: return 0 -> no Error).
8605 *
8606 */
lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)8607 int32_t lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
8608 uint16_t *val)
8609 {
8610 int32_t ret;
8611
8612 uint8_t add_l;
8613 uint8_t add_h;
8614 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
8615 &add_l);
8616
8617 if (ret == 0)
8618 {
8619 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
8620 &add_h);
8621 *val = add_h;
8622 *val = *val << 8;
8623 *val += add_l;
8624 }
8625
8626 return ret;
8627 }
8628
8629 /**
8630 * @brief FSM number of programs register.[set]
8631 *
8632 * @param ctx read / write interface definitions
8633 * @param val value to write
8634 * @retval interface status (MANDATORY: return 0 -> no Error).
8635 *
8636 */
lsm6dso32x_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)8637 int32_t lsm6dso32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
8638 uint8_t val)
8639 {
8640 int32_t ret;
8641
8642 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, &val);
8643
8644 return ret;
8645 }
8646
8647 /**
8648 * @brief FSM number of programs register.[get]
8649 *
8650 * @param ctx read / write interface definitions
8651 * @param val buffer that stores data read.
8652 * @retval interface status (MANDATORY: return 0 -> no Error).
8653 *
8654 */
lsm6dso32x_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)8655 int32_t lsm6dso32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
8656 uint8_t *val)
8657 {
8658 int32_t ret;
8659
8660 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, val);
8661
8662 return ret;
8663 }
8664
8665 /**
8666 * @brief FSM start address register (r/w).
8667 * First available address is 0x033C.[set]
8668 *
8669 * @param ctx read / write interface definitions
8670 * @param val the value of start address
8671 * @retval interface status (MANDATORY: return 0 -> no Error).
8672 *
8673 */
lsm6dso32x_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)8674 int32_t lsm6dso32x_fsm_start_address_set(const stmdev_ctx_t *ctx,
8675 uint16_t val)
8676 {
8677 int32_t ret;
8678
8679 uint8_t add_l;
8680 uint8_t add_h;
8681 add_h = (uint8_t)((val & 0xFF00U) >> 8);
8682 add_l = (uint8_t)(val & 0x00FFU);
8683 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
8684 &add_l);
8685
8686 if (ret == 0)
8687 {
8688 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
8689 &add_h);
8690 }
8691
8692 return ret;
8693 }
8694
8695 /**
8696 * @brief FSM start address register (r/w).
8697 * First available address is 0x033C.[get]
8698 *
8699 * @param ctx read / write interface definitions
8700 * @param val buffer the value of start address.
8701 * @retval interface status (MANDATORY: return 0 -> no Error).
8702 *
8703 */
lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)8704 int32_t lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t *ctx,
8705 uint16_t *val)
8706 {
8707 int32_t ret;
8708
8709 uint8_t add_l;
8710 uint8_t add_h;
8711 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
8712 &add_l);
8713
8714 if (ret == 0)
8715 {
8716 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
8717 &add_h);
8718 *val = add_h;
8719 *val = *val << 8;
8720 *val += add_l;
8721 }
8722
8723 return ret;
8724 }
8725
8726 /**
8727 * @}
8728 *
8729 */
8730
8731 /**
8732 * @addtogroup Machine Learning Core
8733 * @brief This section group all the functions concerning the
8734 * usage of Machine Learning Core
8735 * @{
8736 *
8737 */
8738
8739 /**
8740 * @brief Machine Learning Core status register[get]
8741 *
8742 * @param ctx read / write interface definitions
8743 * @param val register MLC_STATUS_MAINPAGE
8744 * @retval interface status (MANDATORY: return 0 -> no Error).
8745 *
8746 */
lsm6dso32x_mlc_status_get(const stmdev_ctx_t * ctx,lsm6dso32x_mlc_status_mainpage_t * val)8747 int32_t lsm6dso32x_mlc_status_get(const stmdev_ctx_t *ctx,
8748 lsm6dso32x_mlc_status_mainpage_t *val)
8749 {
8750 return lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_STATUS_MAINPAGE,
8751 (uint8_t *) val, 1);
8752 }
8753
8754 /**
8755 * @brief Machine Learning Core data rate selection.[set]
8756 *
8757 * @param ctx read / write interface definitions
8758 * @param val get the values of mlc_odr in
8759 * reg EMB_FUNC_ODR_CFG_C
8760 * @retval interface status (MANDATORY: return 0 -> no Error).
8761 *
8762 */
lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32x_mlc_odr_t val)8763 int32_t lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t *ctx,
8764 lsm6dso32x_mlc_odr_t val)
8765 {
8766 lsm6dso32x_emb_func_odr_cfg_c_t reg;
8767 int32_t ret;
8768
8769 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8770
8771 if (ret == 0)
8772 {
8773 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8774 (uint8_t *)®, 1);
8775 }
8776
8777 if (ret == 0)
8778 {
8779 reg.mlc_odr = (uint8_t)val;
8780 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8781 (uint8_t *)®, 1);
8782 }
8783
8784 if (ret == 0)
8785 {
8786 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8787 }
8788
8789 return ret;
8790 }
8791
8792 /**
8793 * @brief Machine Learning Core data rate selection.[get]
8794 *
8795 * @param ctx read / write interface definitions
8796 * @param val change the values of mlc_odr in
8797 * reg EMB_FUNC_ODR_CFG_C
8798 * @retval interface status (MANDATORY: return 0 -> no Error).
8799 *
8800 */
lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32x_mlc_odr_t * val)8801 int32_t lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t *ctx,
8802 lsm6dso32x_mlc_odr_t *val)
8803 {
8804 lsm6dso32x_emb_func_odr_cfg_c_t reg;
8805 int32_t ret;
8806
8807 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8808
8809 if (ret == 0)
8810 {
8811 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8812 (uint8_t *)®, 1);
8813 }
8814
8815 if (ret == 0)
8816 {
8817 switch (reg.mlc_odr)
8818 {
8819 case LSM6DSO32X_ODR_PRGS_12Hz5:
8820 *val = LSM6DSO32X_ODR_PRGS_12Hz5;
8821 break;
8822
8823 case LSM6DSO32X_ODR_PRGS_26Hz:
8824 *val = LSM6DSO32X_ODR_PRGS_26Hz;
8825 break;
8826
8827 case LSM6DSO32X_ODR_PRGS_52Hz:
8828 *val = LSM6DSO32X_ODR_PRGS_52Hz;
8829 break;
8830
8831 case LSM6DSO32X_ODR_PRGS_104Hz:
8832 *val = LSM6DSO32X_ODR_PRGS_104Hz;
8833 break;
8834
8835 default:
8836 *val = LSM6DSO32X_ODR_PRGS_12Hz5;
8837 break;
8838 }
8839
8840 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8841 }
8842
8843 return ret;
8844 }
8845
8846 /**
8847 * @}
8848 *
8849 */
8850
8851 /**
8852 * @defgroup LSM6DSO32X_Sensor_hub
8853 * @brief This section groups all the functions that manage the
8854 * sensor hub.
8855 * @{
8856 *
8857 */
8858
8859 /**
8860 * @brief Sensor hub output registers.[get]
8861 *
8862 * @param ctx read / write interface definitions
8863 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
8864 *
8865 */
lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dso32x_emb_sh_read_t * val,uint8_t len)8866 int32_t lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
8867 lsm6dso32x_emb_sh_read_t *val,
8868 uint8_t len)
8869 {
8870 int32_t ret;
8871
8872 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8873
8874 if (ret == 0)
8875 {
8876 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SENSOR_HUB_1,
8877 (uint8_t *) val,
8878 len);
8879 }
8880
8881 if (ret == 0)
8882 {
8883 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8884 }
8885
8886 return ret;
8887 }
8888
8889 /**
8890 * @brief Number of external sensors to be read by the sensor hub.[set]
8891 *
8892 * @param ctx read / write interface definitions
8893 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
8894 * @retval interface status (MANDATORY: return 0 -> no Error).
8895 *
8896 */
lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dso32x_aux_sens_on_t val)8897 int32_t lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8898 lsm6dso32x_aux_sens_on_t val)
8899 {
8900 lsm6dso32x_master_config_t reg;
8901 int32_t ret;
8902
8903 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8904
8905 if (ret == 0)
8906 {
8907 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8908 (uint8_t *)®, 1);
8909 }
8910
8911 if (ret == 0)
8912 {
8913 reg.aux_sens_on = (uint8_t)val;
8914 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8915 (uint8_t *)®, 1);
8916 }
8917
8918 if (ret == 0)
8919 {
8920 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8921 }
8922
8923 return ret;
8924 }
8925
8926 /**
8927 * @brief Number of external sensors to be read by the sensor hub.[get]
8928 *
8929 * @param ctx read / write interface definitions
8930 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
8931 * @retval interface status (MANDATORY: return 0 -> no Error).
8932 *
8933 */
lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dso32x_aux_sens_on_t * val)8934 int32_t lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8935 lsm6dso32x_aux_sens_on_t *val)
8936 {
8937 lsm6dso32x_master_config_t reg;
8938 int32_t ret;
8939
8940 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8941
8942 if (ret == 0)
8943 {
8944 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8945 (uint8_t *)®, 1);
8946 }
8947
8948 if (ret == 0)
8949 {
8950 switch (reg.aux_sens_on)
8951 {
8952 case LSM6DSO32X_SLV_0:
8953 *val = LSM6DSO32X_SLV_0;
8954 break;
8955
8956 case LSM6DSO32X_SLV_0_1:
8957 *val = LSM6DSO32X_SLV_0_1;
8958 break;
8959
8960 case LSM6DSO32X_SLV_0_1_2:
8961 *val = LSM6DSO32X_SLV_0_1_2;
8962 break;
8963
8964 case LSM6DSO32X_SLV_0_1_2_3:
8965 *val = LSM6DSO32X_SLV_0_1_2_3;
8966 break;
8967
8968 default:
8969 *val = LSM6DSO32X_SLV_0;
8970 break;
8971 }
8972
8973 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8974 }
8975
8976 return ret;
8977 }
8978
8979 /**
8980 * @brief Sensor hub I2C master enable.[set]
8981 *
8982 * @param ctx read / write interface definitions
8983 * @param val change the values of master_on in reg MASTER_CONFIG
8984 * @retval interface status (MANDATORY: return 0 -> no Error).
8985 *
8986 */
lsm6dso32x_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8987 int32_t lsm6dso32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8988 {
8989 lsm6dso32x_master_config_t reg;
8990 int32_t ret;
8991
8992 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8993
8994 if (ret == 0)
8995 {
8996 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8997 (uint8_t *)®, 1);
8998 }
8999
9000 if (ret == 0)
9001 {
9002 reg.master_on = val;
9003 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9004 (uint8_t *)®, 1);
9005 }
9006
9007 if (ret == 0)
9008 {
9009 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9010 }
9011
9012 return ret;
9013 }
9014
9015 /**
9016 * @brief Sensor hub I2C master enable.[get]
9017 *
9018 * @param ctx read / write interface definitions
9019 * @param val change the values of master_on in reg MASTER_CONFIG
9020 * @retval interface status (MANDATORY: return 0 -> no Error).
9021 *
9022 */
lsm6dso32x_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)9023 int32_t lsm6dso32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
9024 {
9025 lsm6dso32x_master_config_t reg;
9026 int32_t ret;
9027
9028 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9029
9030 if (ret == 0)
9031 {
9032 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9033 (uint8_t *)®, 1);
9034 }
9035
9036 if (ret == 0)
9037 {
9038 *val = reg.master_on;
9039 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9040 }
9041
9042 return ret;
9043 }
9044
9045 /**
9046 * @brief Master I2C pull-up enable.[set]
9047 *
9048 * @param ctx read / write interface definitions
9049 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
9050 * @retval interface status (MANDATORY: return 0 -> no Error).
9051 *
9052 */
lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_shub_pu_en_t val)9053 int32_t lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t *ctx,
9054 lsm6dso32x_shub_pu_en_t val)
9055 {
9056 lsm6dso32x_master_config_t reg;
9057 int32_t ret;
9058
9059 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9060
9061 if (ret == 0)
9062 {
9063 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9064 (uint8_t *)®, 1);
9065 }
9066
9067 if (ret == 0)
9068 {
9069 reg.shub_pu_en = (uint8_t)val;
9070 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9071 (uint8_t *)®, 1);
9072 }
9073
9074 if (ret == 0)
9075 {
9076 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9077 }
9078
9079 return ret;
9080 }
9081
9082 /**
9083 * @brief Master I2C pull-up enable.[get]
9084 *
9085 * @param ctx read / write interface definitions
9086 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
9087 * @retval interface status (MANDATORY: return 0 -> no Error).
9088 *
9089 */
lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_shub_pu_en_t * val)9090 int32_t lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t *ctx,
9091 lsm6dso32x_shub_pu_en_t *val)
9092 {
9093 lsm6dso32x_master_config_t reg;
9094 int32_t ret;
9095
9096 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9097
9098 if (ret == 0)
9099 {
9100 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9101 (uint8_t *)®, 1);
9102 }
9103
9104 if (ret == 0)
9105 {
9106 switch (reg.shub_pu_en)
9107 {
9108 case LSM6DSO32X_EXT_PULL_UP:
9109 *val = LSM6DSO32X_EXT_PULL_UP;
9110 break;
9111
9112 case LSM6DSO32X_INTERNAL_PULL_UP:
9113 *val = LSM6DSO32X_INTERNAL_PULL_UP;
9114 break;
9115
9116 default:
9117 *val = LSM6DSO32X_EXT_PULL_UP;
9118 break;
9119 }
9120
9121 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9122 }
9123
9124 return ret;
9125 }
9126
9127 /**
9128 * @brief I2C interface pass-through.[set]
9129 *
9130 * @param ctx read / write interface definitions
9131 * @param val change the values of pass_through_mode in
9132 * reg MASTER_CONFIG
9133 * @retval interface status (MANDATORY: return 0 -> no Error).
9134 *
9135 */
lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)9136 int32_t lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
9137 {
9138 lsm6dso32x_master_config_t reg;
9139 int32_t ret;
9140
9141 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9142
9143 if (ret == 0)
9144 {
9145 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9146 (uint8_t *)®, 1);
9147 }
9148
9149 if (ret == 0)
9150 {
9151 reg.pass_through_mode = val;
9152 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9153 (uint8_t *)®, 1);
9154 }
9155
9156 if (ret == 0)
9157 {
9158 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9159 }
9160
9161 return ret;
9162 }
9163
9164 /**
9165 * @brief I2C interface pass-through.[get]
9166 *
9167 * @param ctx read / write interface definitions
9168 * @param val change the values of pass_through_mode in
9169 * reg MASTER_CONFIG
9170 * @retval interface status (MANDATORY: return 0 -> no Error).
9171 *
9172 */
lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)9173 int32_t lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t *ctx,
9174 uint8_t *val)
9175 {
9176 lsm6dso32x_master_config_t reg;
9177 int32_t ret;
9178
9179 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9180
9181 if (ret == 0)
9182 {
9183 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9184 (uint8_t *)®, 1);
9185 }
9186
9187 if (ret == 0)
9188 {
9189 *val = reg.pass_through_mode;
9190 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9191 }
9192
9193 return ret;
9194 }
9195
9196 /**
9197 * @brief Sensor hub trigger signal selection.[set]
9198 *
9199 * @param ctx read / write interface definitions
9200 * @param val change the values of start_config in reg MASTER_CONFIG
9201 * @retval interface status (MANDATORY: return 0 -> no Error).
9202 *
9203 */
lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_start_config_t val)9204 int32_t lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
9205 lsm6dso32x_start_config_t val)
9206 {
9207 lsm6dso32x_master_config_t reg;
9208 int32_t ret;
9209
9210 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9211
9212 if (ret == 0)
9213 {
9214 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9215 (uint8_t *)®, 1);
9216 }
9217
9218 if (ret == 0)
9219 {
9220 reg.start_config = (uint8_t)val;
9221 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9222 (uint8_t *)®, 1);
9223 }
9224
9225 if (ret == 0)
9226 {
9227 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9228 }
9229
9230 return ret;
9231 }
9232
9233 /**
9234 * @brief Sensor hub trigger signal selection.[get]
9235 *
9236 * @param ctx read / write interface definitions
9237 * @param val Get the values of start_config in reg MASTER_CONFIG
9238 * @retval interface status (MANDATORY: return 0 -> no Error).
9239 *
9240 */
lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_start_config_t * val)9241 int32_t lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
9242 lsm6dso32x_start_config_t *val)
9243 {
9244 lsm6dso32x_master_config_t reg;
9245 int32_t ret;
9246
9247 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9248
9249 if (ret == 0)
9250 {
9251 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9252 (uint8_t *)®, 1);
9253 }
9254
9255 if (ret == 0)
9256 {
9257 switch (reg.start_config)
9258 {
9259 case LSM6DSO32X_EXT_ON_INT2_PIN:
9260 *val = LSM6DSO32X_EXT_ON_INT2_PIN;
9261 break;
9262
9263 case LSM6DSO32X_XL_GY_DRDY:
9264 *val = LSM6DSO32X_XL_GY_DRDY;
9265 break;
9266
9267 default:
9268 *val = LSM6DSO32X_EXT_ON_INT2_PIN;
9269 break;
9270 }
9271
9272 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9273 }
9274
9275 return ret;
9276 }
9277
9278 /**
9279 * @brief Slave 0 write operation is performed only at the first
9280 * sensor hub cycle.[set]
9281 *
9282 * @param ctx read / write interface definitions
9283 * @param val change the values of write_once in reg MASTER_CONFIG
9284 * @retval interface status (MANDATORY: return 0 -> no Error).
9285 *
9286 */
lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_write_once_t val)9287 int32_t lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t *ctx,
9288 lsm6dso32x_write_once_t val)
9289 {
9290 lsm6dso32x_master_config_t reg;
9291 int32_t ret;
9292
9293 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9294
9295 if (ret == 0)
9296 {
9297 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9298 (uint8_t *)®, 1);
9299 }
9300
9301 if (ret == 0)
9302 {
9303 reg.write_once = (uint8_t)val;
9304 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9305 (uint8_t *)®, 1);
9306 }
9307
9308 if (ret == 0)
9309 {
9310 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9311 }
9312
9313 return ret;
9314 }
9315
9316 /**
9317 * @brief Slave 0 write operation is performed only at the first sensor
9318 * hub cycle.[get]
9319 *
9320 * @param ctx read / write interface definitions
9321 * @param val Get the values of write_once in reg MASTER_CONFIG
9322 * @retval interface status (MANDATORY: return 0 -> no Error).
9323 *
9324 */
lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_write_once_t * val)9325 int32_t lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t *ctx,
9326 lsm6dso32x_write_once_t *val)
9327 {
9328 lsm6dso32x_master_config_t reg;
9329 int32_t ret;
9330
9331 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9332
9333 if (ret == 0)
9334 {
9335 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9336 (uint8_t *)®, 1);
9337 }
9338
9339 if (ret == 0)
9340 {
9341 switch (reg.write_once)
9342 {
9343 case LSM6DSO32X_EACH_SH_CYCLE:
9344 *val = LSM6DSO32X_EACH_SH_CYCLE;
9345 break;
9346
9347 case LSM6DSO32X_ONLY_FIRST_CYCLE:
9348 *val = LSM6DSO32X_ONLY_FIRST_CYCLE;
9349 break;
9350
9351 default:
9352 *val = LSM6DSO32X_EACH_SH_CYCLE;
9353 break;
9354 }
9355
9356 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9357 }
9358
9359 return ret;
9360 }
9361
9362 /**
9363 * @brief Reset Master logic and output registers.[set]
9364 *
9365 * @param ctx read / write interface definitions
9366 * @retval interface status (MANDATORY: return 0 -> no Error).
9367 *
9368 */
lsm6dso32x_sh_reset_set(const stmdev_ctx_t * ctx)9369 int32_t lsm6dso32x_sh_reset_set(const stmdev_ctx_t *ctx)
9370 {
9371 lsm6dso32x_master_config_t reg;
9372 int32_t ret;
9373
9374 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9375
9376 if (ret == 0)
9377 {
9378 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9379 (uint8_t *)®, 1);
9380 }
9381
9382 if (ret == 0)
9383 {
9384 reg.rst_master_regs = PROPERTY_ENABLE;
9385 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9386 (uint8_t *)®, 1);
9387 }
9388
9389 if (ret == 0)
9390 {
9391 reg.rst_master_regs = PROPERTY_DISABLE;
9392 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9393 (uint8_t *)®, 1);
9394 }
9395
9396 if (ret == 0)
9397 {
9398 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9399 }
9400
9401 return ret;
9402 }
9403
9404 /**
9405 * @brief Reset Master logic and output registers.[get]
9406 *
9407 * @param ctx read / write interface definitions
9408 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
9409 * @retval interface status (MANDATORY: return 0 -> no Error).
9410 *
9411 */
lsm6dso32x_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)9412 int32_t lsm6dso32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
9413 {
9414 lsm6dso32x_master_config_t reg;
9415 int32_t ret;
9416
9417 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9418
9419 if (ret == 0)
9420 {
9421 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9422 (uint8_t *)®, 1);
9423 }
9424
9425 if (ret == 0)
9426 {
9427 *val = reg.rst_master_regs;
9428 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9429 }
9430
9431 return ret;
9432 }
9433
9434 /**
9435 * @brief Rate at which the master communicates.[set]
9436 *
9437 * @param ctx read / write interface definitions
9438 * @param val change the values of shub_odr in reg slv1_CONFIG
9439 * @retval interface status (MANDATORY: return 0 -> no Error).
9440 *
9441 */
lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32x_shub_odr_t val)9442 int32_t lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t *ctx,
9443 lsm6dso32x_shub_odr_t val)
9444 {
9445 lsm6dso32x_slv0_config_t reg;
9446 int32_t ret;
9447
9448 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9449
9450 if (ret == 0)
9451 {
9452 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9453 (uint8_t *)®, 1);
9454 }
9455
9456 if (ret == 0)
9457 {
9458 reg.shub_odr = (uint8_t)val;
9459 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9460 (uint8_t *)®, 1);
9461 }
9462
9463 if (ret == 0)
9464 {
9465 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9466 }
9467
9468 return ret;
9469 }
9470
9471 /**
9472 * @brief Rate at which the master communicates.[get]
9473 *
9474 * @param ctx read / write interface definitions
9475 * @param val Get the values of shub_odr in reg slv1_CONFIG
9476 * @retval interface status (MANDATORY: return 0 -> no Error).
9477 *
9478 */
lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32x_shub_odr_t * val)9479 int32_t lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t *ctx,
9480 lsm6dso32x_shub_odr_t *val)
9481 {
9482 lsm6dso32x_slv0_config_t reg;
9483 int32_t ret;
9484
9485 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9486
9487 if (ret == 0)
9488 {
9489 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9490 (uint8_t *)®, 1);
9491 }
9492
9493 if (ret == 0)
9494 {
9495 switch (reg.shub_odr)
9496 {
9497 case LSM6DSO32X_SH_ODR_104Hz:
9498 *val = LSM6DSO32X_SH_ODR_104Hz;
9499 break;
9500
9501 case LSM6DSO32X_SH_ODR_52Hz:
9502 *val = LSM6DSO32X_SH_ODR_52Hz;
9503 break;
9504
9505 case LSM6DSO32X_SH_ODR_26Hz:
9506 *val = LSM6DSO32X_SH_ODR_26Hz;
9507 break;
9508
9509 case LSM6DSO32X_SH_ODR_13Hz:
9510 *val = LSM6DSO32X_SH_ODR_13Hz;
9511 break;
9512
9513 default:
9514 *val = LSM6DSO32X_SH_ODR_104Hz;
9515 break;
9516 }
9517
9518 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9519 }
9520
9521 return ret;
9522 }
9523
9524 /**
9525 * @brief Configure slave 0 for perform a write.[set]
9526 *
9527 * @param ctx read / write interface definitions
9528 * @param val a structure that contain
9529 * - uint8_t slv1_add; 8 bit i2c device address
9530 * - uint8_t slv1_subadd; 8 bit register device address
9531 * - uint8_t slv1_data; 8 bit data to write
9532 * @retval interface status (MANDATORY: return 0 -> no Error).
9533 *
9534 */
lsm6dso32x_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_write_t * val)9535 int32_t lsm6dso32x_sh_cfg_write(const stmdev_ctx_t *ctx,
9536 lsm6dso32x_sh_cfg_write_t *val)
9537 {
9538 lsm6dso32x_slv0_add_t reg;
9539 int32_t ret;
9540
9541 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9542
9543 if (ret == 0)
9544 {
9545 reg.slave0 = val->slv0_add;
9546 reg.rw_0 = 0;
9547 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD, (uint8_t *)®, 1);
9548 }
9549
9550 if (ret == 0)
9551 {
9552 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
9553 &(val->slv0_subadd), 1);
9554 }
9555
9556 if (ret == 0)
9557 {
9558 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_DATAWRITE_SLV0,
9559 &(val->slv0_data), 1);
9560 }
9561
9562 if (ret == 0)
9563 {
9564 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9565 }
9566
9567 return ret;
9568 }
9569
9570 /**
9571 * @brief Configure slave 0 for perform a read.[set]
9572 *
9573 * @param ctx read / write interface definitions
9574 * @param val Structure that contain
9575 * - uint8_t slv1_add; 8 bit i2c device address
9576 * - uint8_t slv1_subadd; 8 bit register device address
9577 * - uint8_t slv1_len; num of bit to read
9578 * @retval interface status (MANDATORY: return 0 -> no Error).
9579 *
9580 */
lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9581 int32_t lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
9582 lsm6dso32x_sh_cfg_read_t *val)
9583 {
9584 lsm6dso32x_slv0_add_t slv0_add;
9585 lsm6dso32x_slv0_config_t slv0_config;
9586 int32_t ret;
9587
9588 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9589
9590 if (ret == 0)
9591 {
9592 slv0_add.slave0 = val->slv_add;
9593 slv0_add.rw_0 = 1;
9594 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD,
9595 (uint8_t *)&slv0_add, 1);
9596 }
9597
9598 if (ret == 0)
9599 {
9600 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
9601 &(val->slv_subadd), 1);
9602 }
9603
9604 if (ret == 0)
9605 {
9606 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9607 (uint8_t *)&slv0_config, 1);
9608 }
9609
9610 if (ret == 0)
9611 {
9612 slv0_config.slave0_numop = val->slv_len;
9613 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9614 (uint8_t *)&slv0_config, 1);
9615 }
9616
9617 if (ret == 0)
9618 {
9619 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9620 }
9621
9622 return ret;
9623 }
9624
9625 /**
9626 * @brief Configure slave 0 for perform a write/read.[set]
9627 *
9628 * @param ctx read / write interface definitions
9629 * @param val Structure that contain
9630 * - uint8_t slv1_add; 8 bit i2c device address
9631 * - uint8_t slv1_subadd; 8 bit register device address
9632 * - uint8_t slv1_len; num of bit to read
9633 * @retval interface status (MANDATORY: return 0 -> no Error).
9634 *
9635 */
lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9636 int32_t lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
9637 lsm6dso32x_sh_cfg_read_t *val)
9638 {
9639 lsm6dso32x_slv1_add_t slv1_add;
9640 lsm6dso32x_slv1_config_t slv1_config;
9641 int32_t ret;
9642
9643 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9644
9645 if (ret == 0)
9646 {
9647 slv1_add.slave1_add = val->slv_add;
9648 slv1_add.r_1 = 1;
9649 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_ADD,
9650 (uint8_t *)&slv1_add, 1);
9651 }
9652
9653 if (ret == 0)
9654 {
9655 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_SUBADD,
9656 &(val->slv_subadd), 1);
9657 }
9658
9659 if (ret == 0)
9660 {
9661 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
9662 (uint8_t *)&slv1_config, 1);
9663 }
9664
9665 if (ret == 0)
9666 {
9667 slv1_config.slave1_numop = val->slv_len;
9668 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
9669 (uint8_t *)&slv1_config, 1);
9670 }
9671
9672 if (ret == 0)
9673 {
9674 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9675 }
9676
9677 return ret;
9678 }
9679
9680 /**
9681 * @brief Configure slave 0 for perform a write/read.[set]
9682 *
9683 * @param ctx read / write interface definitions
9684 * @param val Structure that contain
9685 * - uint8_t slv2_add; 8 bit i2c device address
9686 * - uint8_t slv2_subadd; 8 bit register device address
9687 * - uint8_t slv2_len; num of bit to read
9688 * @retval interface status (MANDATORY: return 0 -> no Error).
9689 *
9690 */
lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9691 int32_t lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
9692 lsm6dso32x_sh_cfg_read_t *val)
9693 {
9694 lsm6dso32x_slv2_add_t slv2_add;
9695 lsm6dso32x_slv2_config_t slv2_config;
9696 int32_t ret;
9697
9698 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9699
9700 if (ret == 0)
9701 {
9702 slv2_add.slave2_add = val->slv_add;
9703 slv2_add.r_2 = 1;
9704 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_ADD,
9705 (uint8_t *)&slv2_add, 1);
9706 }
9707
9708 if (ret == 0)
9709 {
9710 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_SUBADD,
9711 &(val->slv_subadd), 1);
9712 }
9713
9714 if (ret == 0)
9715 {
9716 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
9717 (uint8_t *)&slv2_config, 1);
9718 }
9719
9720 if (ret == 0)
9721 {
9722 slv2_config.slave2_numop = val->slv_len;
9723 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
9724 (uint8_t *)&slv2_config, 1);
9725 }
9726
9727 if (ret == 0)
9728 {
9729 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9730 }
9731
9732 return ret;
9733 }
9734
9735 /**
9736 * @brief Configure slave 0 for perform a write/read.[set]
9737 *
9738 * @param ctx read / write interface definitions
9739 * @param val Structure that contain
9740 * - uint8_t slv3_add; 8 bit i2c device address
9741 * - uint8_t slv3_subadd; 8 bit register device address
9742 * - uint8_t slv3_len; num of bit to read
9743 * @retval interface status (MANDATORY: return 0 -> no Error).
9744 *
9745 */
lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9746 int32_t lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
9747 lsm6dso32x_sh_cfg_read_t *val)
9748 {
9749 lsm6dso32x_slv3_add_t slv3_add;
9750 lsm6dso32x_slv3_config_t slv3_config;
9751 int32_t ret;
9752
9753 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9754
9755 if (ret == 0)
9756 {
9757 slv3_add.slave3_add = val->slv_add;
9758 slv3_add.r_3 = 1;
9759 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_ADD,
9760 (uint8_t *)&slv3_add, 1);
9761 }
9762
9763 if (ret == 0)
9764 {
9765 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_SUBADD,
9766 &(val->slv_subadd), 1);
9767 }
9768
9769 if (ret == 0)
9770 {
9771 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
9772 (uint8_t *)&slv3_config, 1);
9773 }
9774
9775 if (ret == 0)
9776 {
9777 slv3_config.slave3_numop = val->slv_len;
9778 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
9779 (uint8_t *)&slv3_config, 1);
9780 }
9781
9782 if (ret == 0)
9783 {
9784 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9785 }
9786
9787 return ret;
9788 }
9789
9790 /**
9791 * @brief Sensor hub source register.[get]
9792 *
9793 * @param ctx read / write interface definitions
9794 * @param val union of registers from STATUS_MASTER to
9795 * @retval interface status (MANDATORY: return 0 -> no Error).
9796 *
9797 */
lsm6dso32x_sh_status_get(const stmdev_ctx_t * ctx,lsm6dso32x_status_master_t * val)9798 int32_t lsm6dso32x_sh_status_get(const stmdev_ctx_t *ctx,
9799 lsm6dso32x_status_master_t *val)
9800 {
9801 int32_t ret;
9802
9803 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9804
9805 if (ret == 0)
9806 {
9807 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_MASTER,
9808 (uint8_t *) val, 1);
9809 }
9810
9811 if (ret == 0)
9812 {
9813 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9814 }
9815
9816 return ret;
9817 }
9818
9819 /**
9820 * @}
9821 *
9822 */
9823
9824 /**
9825 * @defgroup Basic configuration
9826 * @brief This section groups all the functions concerning
9827 * device basic configuration.
9828 * @{
9829 *
9830 */
9831
9832 /**
9833 * @brief Device "Who am I".[get]
9834 *
9835 * @param ctx communication interface handler. Use NULL to ignore
9836 * this interface.(ptr)
9837 * @param val ID values read from the two interfaces. ID values
9838 * will be the same.(ptr)
9839 * @retval interface status (MANDATORY: return 0 -> no Error).
9840 *
9841 */
lsm6dso32x_id_get(const stmdev_ctx_t * ctx,lsm6dso32x_id_t * val)9842 int32_t lsm6dso32x_id_get(const stmdev_ctx_t *ctx, lsm6dso32x_id_t *val)
9843 {
9844 int32_t ret = 0;
9845
9846 if (ctx != NULL)
9847 {
9848 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I,
9849 (uint8_t *) & (val->ui), 1);
9850 }
9851
9852 return ret;
9853 }
9854
9855 /**
9856 * @brief Re-initialize the device.[set]
9857 *
9858 * @param ctx communication interface handler.(ptr)
9859 * @param val re-initialization mode. Refer to datasheet
9860 * and application note for more information
9861 * about differencies between boot and sw_reset
9862 * procedure.
9863 * @retval interface status (MANDATORY: return 0 -> no Error).
9864 *
9865 */
lsm6dso32x_init_set(const stmdev_ctx_t * ctx,lsm6dso32x_init_t val)9866 int32_t lsm6dso32x_init_set(const stmdev_ctx_t *ctx, lsm6dso32x_init_t val)
9867 {
9868 lsm6dso32x_emb_func_init_a_t emb_func_init_a;
9869 lsm6dso32x_emb_func_init_b_t emb_func_init_b;
9870 lsm6dso32x_ctrl3_c_t ctrl3_c;
9871 int32_t ret;
9872
9873 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
9874
9875 if (ret == 0)
9876 {
9877 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
9878 (uint8_t *)&emb_func_init_b, 1);
9879 }
9880
9881 if (ret == 0)
9882 {
9883 emb_func_init_b.fifo_compr_init = (uint8_t)val
9884 & ((uint8_t)LSM6DSO32X_FIFO_COMP >> 2);
9885 emb_func_init_b.fsm_init = (uint8_t)val
9886 & ((uint8_t)LSM6DSO32X_FSM >> 3);
9887 emb_func_init_b.mlc_init = (uint8_t)val
9888 & ((uint8_t)LSM6DSO32X_MLC >> 4);
9889 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
9890 (uint8_t *)&emb_func_init_b, 1);
9891 }
9892
9893 if (ret == 0)
9894 {
9895 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
9896 (uint8_t *)&emb_func_init_a, 1);
9897 }
9898
9899 if (ret == 0)
9900 {
9901 emb_func_init_a.step_det_init = ((uint8_t)val
9902 & (uint8_t)LSM6DSO32X_PEDO) >> 5;
9903 emb_func_init_a.tilt_init = ((uint8_t)val
9904 & (uint8_t)LSM6DSO32X_TILT) >> 6;
9905 emb_func_init_a.sig_mot_init = ((uint8_t)val
9906 & (uint8_t)LSM6DSO32X_SMOTION) >> 7;
9907 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
9908 (uint8_t *)&emb_func_init_a, 1);
9909 }
9910
9911 if (ret == 0)
9912 {
9913 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9914 }
9915
9916 if (ret == 0)
9917 {
9918 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
9919 (uint8_t *)&ctrl3_c, 1);
9920 }
9921
9922 if (((val == LSM6DSO32X_BOOT) || (val == LSM6DSO32X_RESET)) &&
9923 (ret == 0))
9924 {
9925 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO32X_BOOT;
9926 ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO32X_RESET) >> 1;
9927 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
9928 (uint8_t *)&ctrl3_c, 1);
9929 }
9930
9931 if ((val == LSM6DSO32X_DRV_RDY)
9932 && ((ctrl3_c.bdu == PROPERTY_DISABLE)
9933 || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
9934 {
9935 ctrl3_c.bdu = PROPERTY_ENABLE;
9936 ctrl3_c.if_inc = PROPERTY_ENABLE;
9937 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
9938 (uint8_t *)&ctrl3_c, 1);
9939 }
9940
9941 return ret;
9942 }
9943
9944 /**
9945 * @brief Configures the bus operating mode.[set]
9946 *
9947 * @param ctx communication interface handler. Use NULL to ignore
9948 * this interface.(ptr)
9949 * @param val configures the bus operating mode for both the
9950 * main and the auxiliary interface.
9951 * @retval interface status (MANDATORY: return 0 -> no Error).
9952 *
9953 */
lsm6dso32x_bus_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_bus_mode_t val)9954 int32_t lsm6dso32x_bus_mode_set(const stmdev_ctx_t *ctx,
9955 lsm6dso32x_bus_mode_t val)
9956 {
9957 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
9958 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
9959 lsm6dso32x_ctrl3_c_t ctrl3_c;
9960 lsm6dso32x_ctrl4_c_t ctrl4_c;
9961 uint8_t bit_val;
9962 int32_t ret;
9963
9964 ret = 0;
9965
9966 if (ctx != NULL)
9967 {
9968 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
9969 (uint8_t *)&ctrl9_xl, 1);
9970
9971 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
9972
9973 if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
9974 {
9975 ctrl9_xl.i3c_disable = bit_val;
9976 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
9977 (uint8_t *)&ctrl9_xl, 1);
9978 }
9979
9980 if (ret == 0)
9981 {
9982 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
9983 (uint8_t *)&i3c_bus_avb, 1);
9984 }
9985
9986 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
9987
9988 if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
9989 {
9990 i3c_bus_avb.i3c_bus_avb_sel = bit_val;
9991 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
9992 (uint8_t *)&i3c_bus_avb, 1);
9993 }
9994
9995 if (ret == 0)
9996 {
9997 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
9998 (uint8_t *)&ctrl4_c, 1);
9999 }
10000
10001 bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
10002
10003 if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
10004 {
10005 ctrl4_c.i2c_disable = bit_val;
10006 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
10007 (uint8_t *)&ctrl4_c, 1);
10008 }
10009
10010 if (ret == 0)
10011 {
10012 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10013 (uint8_t *)&ctrl3_c, 1);
10014 }
10015
10016 bit_val = (uint8_t)val.ui_bus_md & 0x01U;
10017
10018 if ((ret == 0) && (ctrl3_c.sim != bit_val))
10019 {
10020 ctrl3_c.sim = bit_val;
10021 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
10022 (uint8_t *)&ctrl3_c, 1);
10023 }
10024 }
10025
10026 return ret;
10027 }
10028
10029 /**
10030 * @brief Get the bus operating mode.[get]
10031 *
10032 * @param ctx communication interface handler. Use NULL to ignore
10033 * this interface.(ptr)
10034 * @param val retrieves the bus operating mode for both the main
10035 * and the auxiliary interface.(ptr)
10036 * @retval interface status (MANDATORY: return 0 -> no Error).
10037 *
10038 */
lsm6dso32x_bus_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_bus_mode_t * val)10039 int32_t lsm6dso32x_bus_mode_get(const stmdev_ctx_t *ctx,
10040 lsm6dso32x_bus_mode_t *val)
10041 {
10042 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10043 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
10044 lsm6dso32x_ctrl3_c_t ctrl3_c;
10045 lsm6dso32x_ctrl4_c_t ctrl4_c;
10046 int32_t ret = 0;
10047
10048 if (ctx != NULL)
10049 {
10050 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
10051 (uint8_t *)&ctrl9_xl, 1);
10052
10053 if (ret == 0)
10054 {
10055 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10056 (uint8_t *)&i3c_bus_avb, 1);
10057 }
10058
10059 if (ret == 0)
10060 {
10061 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10062 (uint8_t *)&ctrl4_c, 1);
10063 }
10064
10065 if (ret == 0)
10066 {
10067 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10068 (uint8_t *)&ctrl3_c, 1);
10069
10070 switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
10071 (ctrl9_xl.i3c_disable << 2) &
10072 (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
10073 {
10074 case LSM6DSO32X_SEL_BY_HW:
10075 val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
10076 break;
10077
10078 case LSM6DSO32X_SPI_4W:
10079 val->ui_bus_md = LSM6DSO32X_SPI_4W;
10080 break;
10081
10082 case LSM6DSO32X_SPI_3W:
10083 val->ui_bus_md = LSM6DSO32X_SPI_3W;
10084 break;
10085
10086 case LSM6DSO32X_I2C:
10087 val->ui_bus_md = LSM6DSO32X_I2C;
10088 break;
10089
10090 case LSM6DSO32X_I3C_T_50us:
10091 val->ui_bus_md = LSM6DSO32X_I3C_T_50us;
10092 break;
10093
10094 case LSM6DSO32X_I3C_T_2us:
10095 val->ui_bus_md = LSM6DSO32X_I3C_T_2us;
10096 break;
10097
10098 case LSM6DSO32X_I3C_T_1ms:
10099 val->ui_bus_md = LSM6DSO32X_I3C_T_1ms;
10100 break;
10101
10102 case LSM6DSO32X_I3C_T_25ms:
10103 val->ui_bus_md = LSM6DSO32X_I3C_T_25ms;
10104 break;
10105
10106 default:
10107 val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
10108 break;
10109 }
10110 }
10111 }
10112
10113 return ret;
10114 }
10115
10116 /**
10117 * @brief Get the status of the device.[get]
10118 *
10119 * @param ctx communication interface handler. Use NULL to ignore
10120 * this interface.(ptr)
10121 * @param val the status of the device.(ptr)
10122 * @retval interface status (MANDATORY: return 0 -> no Error).
10123 *
10124 */
lsm6dso32x_status_get(const stmdev_ctx_t * ctx,lsm6dso32x_status_t * val)10125 int32_t lsm6dso32x_status_get(const stmdev_ctx_t *ctx,
10126 lsm6dso32x_status_t *val)
10127 {
10128 lsm6dso32x_status_reg_t status_reg;
10129 lsm6dso32x_ctrl3_c_t ctrl3_c;
10130 int32_t ret;
10131 ret = 0;
10132
10133 if (ctx != NULL)
10134 {
10135 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10136 (uint8_t *)&ctrl3_c, 1);
10137 val->sw_reset = ctrl3_c.sw_reset;
10138 val->boot = ctrl3_c.boot;
10139
10140 if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
10141 (ctrl3_c.boot == PROPERTY_DISABLE))
10142 {
10143 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG,
10144 (uint8_t *)&status_reg, 1);
10145 val->drdy_xl = status_reg.xlda;
10146 val->drdy_g = status_reg.gda;
10147 val->drdy_temp = status_reg.tda;
10148 }
10149 }
10150
10151 return ret;
10152 }
10153
10154 /**
10155 * @brief Electrical pin configuration.[set]
10156 *
10157 * @param ctx communication interface handler.(ptr)
10158 * @param val the electrical settings for the configurable
10159 * pins.
10160 * @retval interface status (MANDATORY: return 0 -> no Error).
10161 *
10162 */
lsm6dso32x_pin_conf_set(const stmdev_ctx_t * ctx,lsm6dso32x_pin_conf_t val)10163 int32_t lsm6dso32x_pin_conf_set(const stmdev_ctx_t *ctx,
10164 lsm6dso32x_pin_conf_t val)
10165 {
10166 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10167 lsm6dso32x_pin_ctrl_t pin_ctrl;
10168 lsm6dso32x_ctrl3_c_t ctrl3_c;
10169 int32_t ret;
10170
10171 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
10172 (uint8_t *)&pin_ctrl, 1);
10173
10174 if (ret == 0)
10175 {
10176 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
10177 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL,
10178 (uint8_t *)&pin_ctrl, 1);
10179 }
10180
10181 if (ret == 0)
10182 {
10183 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10184 (uint8_t *)&ctrl3_c, 1);
10185 }
10186
10187 if (ret == 0)
10188 {
10189 ctrl3_c.pp_od = ~val.int1_int2_push_pull;
10190 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
10191 (uint8_t *)&ctrl3_c, 1);
10192 }
10193
10194 if (ret == 0)
10195 {
10196 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10197 (uint8_t *)&i3c_bus_avb, 1);
10198 }
10199
10200 if (ret == 0)
10201 {
10202 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
10203 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10204 (uint8_t *)&i3c_bus_avb, 1);
10205 }
10206
10207 return ret;
10208 }
10209
10210 /**
10211 * @brief Electrical pin configuration.[get]
10212 *
10213 * @param ctx communication interface handler.(ptr)
10214 * @param val the electrical settings for the configurable
10215 * pins.(ptr)
10216 * @retval interface status (MANDATORY: return 0 -> no Error).
10217 *
10218 */
lsm6dso32x_pin_conf_get(const stmdev_ctx_t * ctx,lsm6dso32x_pin_conf_t * val)10219 int32_t lsm6dso32x_pin_conf_get(const stmdev_ctx_t *ctx,
10220 lsm6dso32x_pin_conf_t *val)
10221 {
10222 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10223 lsm6dso32x_pin_ctrl_t pin_ctrl;
10224 lsm6dso32x_ctrl3_c_t ctrl3_c;
10225 int32_t ret;
10226
10227 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
10228 (uint8_t *)&pin_ctrl, 1);
10229
10230 if (ret == 0)
10231 {
10232 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
10233 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10234 (uint8_t *)&ctrl3_c, 1);
10235 }
10236
10237 if (ret == 0)
10238 {
10239 val->int1_int2_push_pull = ~ctrl3_c.pp_od;
10240 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10241 (uint8_t *)&i3c_bus_avb, 1);
10242 }
10243
10244 if (ret == 0)
10245 {
10246 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
10247 }
10248
10249 return ret;
10250 }
10251
10252 /**
10253 * @brief Interrupt pins hardware signal configuration.[set]
10254 *
10255 * @param ctx communication interface handler.(ptr)
10256 * @param val the pins hardware signal settings.
10257 * @retval interface status (MANDATORY: return 0 -> no Error).
10258 *
10259 */
lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_int_mode_t val)10260 int32_t lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t *ctx,
10261 lsm6dso32x_int_mode_t val)
10262 {
10263 lsm6dso32x_tap_cfg0_t tap_cfg0;
10264 lsm6dso32x_page_rw_t page_rw;
10265 lsm6dso32x_ctrl3_c_t ctrl3_c;
10266 int32_t ret;
10267
10268 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10269 (uint8_t *)&ctrl3_c, 1);
10270
10271 if (ret == 0)
10272 {
10273 ctrl3_c.h_lactive = val.active_low;
10274 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
10275 (uint8_t *)&ctrl3_c, 1);
10276 }
10277
10278 if (ret == 0)
10279 {
10280 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
10281 (uint8_t *) &tap_cfg0, 1);
10282 }
10283
10284 if (ret == 0)
10285 {
10286 tap_cfg0.lir = val.base_latched;
10287 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
10288 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
10289 (uint8_t *) &tap_cfg0, 1);
10290 }
10291
10292 if (ret == 0)
10293 {
10294 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10295 }
10296
10297 if (ret == 0)
10298 {
10299 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
10300 (uint8_t *) &page_rw, 1);
10301 }
10302
10303 if (ret == 0)
10304 {
10305 page_rw.emb_func_lir = val.emb_latched;
10306 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
10307 (uint8_t *) &page_rw, 1);
10308 }
10309
10310 if (ret == 0)
10311 {
10312 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10313 }
10314
10315 return ret;
10316 }
10317
10318 /**
10319 * @brief Interrupt pins hardware signal configuration.[get]
10320 *
10321 * @param ctx communication interface handler.(ptr)
10322 * @param val the pins hardware signal settings.(ptr)
10323 * @retval interface status (MANDATORY: return 0 -> no Error).
10324 *
10325 */
lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_int_mode_t * val)10326 int32_t lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t *ctx,
10327 lsm6dso32x_int_mode_t *val)
10328 {
10329 lsm6dso32x_tap_cfg0_t tap_cfg0;
10330 lsm6dso32x_page_rw_t page_rw;
10331 lsm6dso32x_ctrl3_c_t ctrl3_c;
10332 int32_t ret;
10333
10334 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10335 (uint8_t *)&ctrl3_c, 1);
10336
10337 if (ret == 0)
10338 {
10339 ctrl3_c.h_lactive = val->active_low;
10340 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
10341 (uint8_t *) &tap_cfg0, 1);
10342 }
10343
10344 if (ret == 0)
10345 {
10346 tap_cfg0.lir = val->base_latched;
10347 tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
10348 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10349 }
10350
10351 if (ret == 0)
10352 {
10353 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
10354 (uint8_t *) &page_rw, 1);
10355 }
10356
10357 if (ret == 0)
10358 {
10359 page_rw.emb_func_lir = val->emb_latched;
10360 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
10361 (uint8_t *) &page_rw, 1);
10362 }
10363
10364 if (ret == 0)
10365 {
10366 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10367 }
10368
10369 return ret;
10370 }
10371
10372 /**
10373 * @brief Route interrupt signals on int1 pin.[set]
10374 *
10375 * @param ctx communication interface handler.(ptr)
10376 * @param val the signals to route on int1 pin.
10377 * @retval interface status (MANDATORY: return 0 -> no Error).
10378 *
10379 */
lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dso32x_pin_int1_route_t val)10380 int32_t lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t *ctx,
10381 lsm6dso32x_pin_int1_route_t val)
10382 {
10383 lsm6dso32x_pin_int2_route_t pin_int2_route;
10384 lsm6dso32x_emb_func_int1_t emb_func_int1 = {0};
10385 lsm6dso32x_fsm_int1_a_t fsm_int1_a = {0};
10386 lsm6dso32x_fsm_int1_b_t fsm_int1_b = {0};
10387 lsm6dso32x_int1_ctrl_t int1_ctrl = {0};
10388 lsm6dso32x_int2_ctrl_t int2_ctrl;
10389 lsm6dso32x_mlc_int1_t mlc_int1 = {0};
10390 lsm6dso32x_tap_cfg2_t tap_cfg2;
10391 lsm6dso32x_md2_cfg_t md2_cfg;
10392 lsm6dso32x_md1_cfg_t md1_cfg = {0};
10393 lsm6dso32x_ctrl4_c_t ctrl4_c;
10394 int32_t ret;
10395
10396 int1_ctrl.int1_drdy_xl = val.drdy_xl;
10397 int1_ctrl.int1_drdy_g = val.drdy_g;
10398 int1_ctrl.int1_boot = val.boot;
10399 int1_ctrl.int1_fifo_th = val.fifo_th;
10400 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
10401 int1_ctrl.int1_fifo_full = val.fifo_full;
10402 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
10403 int1_ctrl.den_drdy_flag = val.den_flag;
10404 md1_cfg.int1_shub = val.sh_endop;
10405 md1_cfg.int1_6d = val.six_d;
10406 md1_cfg.int1_double_tap = val.double_tap;
10407 md1_cfg.int1_ff = val.free_fall;
10408 md1_cfg.int1_wu = val.wake_up;
10409 md1_cfg.int1_single_tap = val.single_tap;
10410 md1_cfg.int1_sleep_change = val.sleep_change;
10411 emb_func_int1.int1_step_detector = val.step_detector;
10412 emb_func_int1.int1_tilt = val.tilt;
10413 emb_func_int1.int1_sig_mot = val.sig_mot;
10414 emb_func_int1.int1_fsm_lc = val.fsm_lc;
10415 fsm_int1_a.int1_fsm1 = val.fsm1;
10416 fsm_int1_a.int1_fsm2 = val.fsm2;
10417 fsm_int1_a.int1_fsm3 = val.fsm3;
10418 fsm_int1_a.int1_fsm4 = val.fsm4;
10419 fsm_int1_a.int1_fsm5 = val.fsm5;
10420 fsm_int1_a.int1_fsm6 = val.fsm6;
10421 fsm_int1_a.int1_fsm7 = val.fsm7;
10422 fsm_int1_a.int1_fsm8 = val.fsm8;
10423 fsm_int1_b.int1_fsm9 = val.fsm9 ;
10424 fsm_int1_b.int1_fsm10 = val.fsm10;
10425 fsm_int1_b.int1_fsm11 = val.fsm11;
10426 fsm_int1_b.int1_fsm12 = val.fsm12;
10427 fsm_int1_b.int1_fsm13 = val.fsm13;
10428 fsm_int1_b.int1_fsm14 = val.fsm14;
10429 fsm_int1_b.int1_fsm15 = val.fsm15;
10430 fsm_int1_b.int1_fsm16 = val.fsm16;
10431 mlc_int1.int1_mlc1 = val.mlc1;
10432 mlc_int1.int1_mlc2 = val.mlc2;
10433 mlc_int1.int1_mlc3 = val.mlc3;
10434 mlc_int1.int1_mlc4 = val.mlc4;
10435 mlc_int1.int1_mlc5 = val.mlc5;
10436 mlc_int1.int1_mlc6 = val.mlc6;
10437 mlc_int1.int1_mlc7 = val.mlc7;
10438 mlc_int1.int1_mlc8 = val.mlc8;
10439 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10440 (uint8_t *)&ctrl4_c, 1);
10441
10442 if (ret == 0)
10443 {
10444 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
10445 {
10446 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
10447 }
10448
10449 else
10450 {
10451 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
10452 }
10453
10454 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
10455 (uint8_t *)&ctrl4_c, 1);
10456 }
10457
10458 if (ret == 0)
10459 {
10460 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10461 }
10462
10463 if (ret == 0)
10464 {
10465 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT1,
10466 (uint8_t *)&mlc_int1, 1);
10467 }
10468
10469 if (ret == 0)
10470 {
10471 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
10472 (uint8_t *)&emb_func_int1, 1);
10473 }
10474
10475 if (ret == 0)
10476 {
10477 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_A,
10478 (uint8_t *)&fsm_int1_a, 1);
10479 }
10480
10481 if (ret == 0)
10482 {
10483 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_B,
10484 (uint8_t *)&fsm_int1_b, 1);
10485 }
10486
10487 if (ret == 0)
10488 {
10489 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10490 }
10491
10492 if (ret == 0)
10493 {
10494 if ((emb_func_int1.int1_fsm_lc
10495 | emb_func_int1.int1_sig_mot
10496 | emb_func_int1.int1_step_detector
10497 | emb_func_int1.int1_tilt
10498 | fsm_int1_a.int1_fsm1
10499 | fsm_int1_a.int1_fsm2
10500 | fsm_int1_a.int1_fsm3
10501 | fsm_int1_a.int1_fsm4
10502 | fsm_int1_a.int1_fsm5
10503 | fsm_int1_a.int1_fsm6
10504 | fsm_int1_a.int1_fsm7
10505 | fsm_int1_a.int1_fsm8
10506 | fsm_int1_b.int1_fsm9
10507 | fsm_int1_b.int1_fsm10
10508 | fsm_int1_b.int1_fsm11
10509 | fsm_int1_b.int1_fsm12
10510 | fsm_int1_b.int1_fsm13
10511 | fsm_int1_b.int1_fsm14
10512 | fsm_int1_b.int1_fsm15
10513 | fsm_int1_b.int1_fsm16
10514 | mlc_int1.int1_mlc1
10515 | mlc_int1.int1_mlc2
10516 | mlc_int1.int1_mlc3
10517 | mlc_int1.int1_mlc4
10518 | mlc_int1.int1_mlc5
10519 | mlc_int1.int1_mlc6
10520 | mlc_int1.int1_mlc7
10521 | mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
10522 {
10523 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
10524 }
10525
10526 else
10527 {
10528 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
10529 }
10530
10531 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT1_CTRL,
10532 (uint8_t *)&int1_ctrl, 1);
10533 }
10534
10535 if (ret == 0)
10536 {
10537 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD1_CFG,
10538 (uint8_t *)&md1_cfg, 1);
10539 }
10540
10541 if (ret == 0)
10542 {
10543 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
10544 (uint8_t *)&int2_ctrl, 1);
10545 }
10546
10547 if (ret == 0)
10548 {
10549 int2_ctrl.int2_drdy_temp = val.drdy_temp;
10550 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
10551 (uint8_t *)&int2_ctrl, 1);
10552 }
10553
10554 if (ret == 0)
10555 {
10556 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
10557 (uint8_t *)&md2_cfg, 1);
10558 }
10559
10560 if (ret == 0)
10561 {
10562 md2_cfg.int2_timestamp = val.timestamp;
10563 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
10564 (uint8_t *)&md2_cfg, 1);
10565 }
10566
10567 if (ret == 0)
10568 {
10569 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
10570 (uint8_t *) &tap_cfg2, 1);
10571 }
10572
10573 if (ret == 0)
10574 {
10575 ret = lsm6dso32x_pin_int2_route_get(ctx, &pin_int2_route);
10576 }
10577
10578 if (ret == 0)
10579 {
10580 if ((pin_int2_route.fifo_bdr
10581 | pin_int2_route.drdy_g
10582 | pin_int2_route.drdy_temp
10583 | pin_int2_route.drdy_xl
10584 | pin_int2_route.fifo_full
10585 | pin_int2_route.fifo_ovr
10586 | pin_int2_route.fifo_th
10587 | pin_int2_route.six_d
10588 | pin_int2_route.double_tap
10589 | pin_int2_route.free_fall
10590 | pin_int2_route.wake_up
10591 | pin_int2_route.single_tap
10592 | pin_int2_route.sleep_change
10593 | int1_ctrl.den_drdy_flag
10594 | int1_ctrl.int1_boot
10595 | int1_ctrl.int1_cnt_bdr
10596 | int1_ctrl.int1_drdy_g
10597 | int1_ctrl.int1_drdy_xl
10598 | int1_ctrl.int1_fifo_full
10599 | int1_ctrl.int1_fifo_ovr
10600 | int1_ctrl.int1_fifo_th
10601 | md1_cfg.int1_shub
10602 | md1_cfg.int1_6d
10603 | md1_cfg.int1_double_tap
10604 | md1_cfg.int1_ff
10605 | md1_cfg.int1_wu
10606 | md1_cfg.int1_single_tap
10607 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
10608 {
10609 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
10610 }
10611
10612 else
10613 {
10614 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
10615 }
10616
10617 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
10618 (uint8_t *) &tap_cfg2, 1);
10619 }
10620
10621 return ret;
10622 }
10623
10624 /**
10625 * @brief Route interrupt signals on int1 pin.[get]
10626 *
10627 * @param ctx communication interface handler.(ptr)
10628 * @param val the signals that are routed on int1 pin.(ptr)
10629 * @retval interface status (MANDATORY: return 0 -> no Error).
10630 *
10631 */
lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dso32x_pin_int1_route_t * val)10632 int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx,
10633 lsm6dso32x_pin_int1_route_t *val)
10634 {
10635 lsm6dso32x_emb_func_int1_t emb_func_int1;
10636 lsm6dso32x_fsm_int1_a_t fsm_int1_a;
10637 lsm6dso32x_fsm_int1_b_t fsm_int1_b;
10638 lsm6dso32x_int1_ctrl_t int1_ctrl;
10639 lsm6dso32x_int2_ctrl_t int2_ctrl;
10640 lsm6dso32x_mlc_int1_t mlc_int1;
10641 lsm6dso32x_md2_cfg_t md2_cfg;
10642 lsm6dso32x_md1_cfg_t md1_cfg;
10643 lsm6dso32x_ctrl4_c_t ctrl4_c;
10644 int32_t ret;
10645 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10646
10647 if (ret == 0)
10648 {
10649 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT1,
10650 (uint8_t *)&mlc_int1, 1);
10651 }
10652
10653 if (ret == 0)
10654 {
10655 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
10656 (uint8_t *)&emb_func_int1, 1);
10657 }
10658
10659 if (ret == 0)
10660 {
10661 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_A,
10662 (uint8_t *)&fsm_int1_a, 1);
10663 }
10664
10665 if (ret == 0)
10666 {
10667 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_B,
10668 (uint8_t *)&fsm_int1_b, 1);
10669 }
10670
10671 if (ret == 0)
10672 {
10673 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10674 }
10675
10676 if (ret == 0)
10677 {
10678 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT1_CTRL,
10679 (uint8_t *)&int1_ctrl, 1);
10680 }
10681
10682 if (ret == 0)
10683 {
10684 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD1_CFG,
10685 (uint8_t *)&md1_cfg, 1);
10686 }
10687
10688 if (ret == 0)
10689 {
10690 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10691 (uint8_t *)&ctrl4_c, 1);
10692 }
10693
10694 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
10695 {
10696 if (ret == 0)
10697 {
10698 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
10699 (uint8_t *)&int2_ctrl, 1);
10700 val->drdy_temp = int2_ctrl.int2_drdy_temp;
10701 }
10702
10703 if (ret == 0)
10704 {
10705 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
10706 (uint8_t *)&md2_cfg, 1);
10707 val->timestamp = md2_cfg.int2_timestamp;
10708 }
10709 }
10710
10711 else
10712 {
10713 val->drdy_temp = PROPERTY_DISABLE;
10714 val->timestamp = PROPERTY_DISABLE;
10715 }
10716
10717 val->drdy_xl = int1_ctrl.int1_drdy_xl;
10718 val->drdy_g = int1_ctrl.int1_drdy_g;
10719 val->boot = int1_ctrl.int1_boot;
10720 val->fifo_th = int1_ctrl.int1_fifo_th;
10721 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
10722 val->fifo_full = int1_ctrl.int1_fifo_full;
10723 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
10724 val->den_flag = int1_ctrl.den_drdy_flag;
10725 val->sh_endop = md1_cfg.int1_shub;
10726 val->six_d = md1_cfg.int1_6d;
10727 val->double_tap = md1_cfg.int1_double_tap;
10728 val->free_fall = md1_cfg.int1_ff;
10729 val->wake_up = md1_cfg.int1_wu;
10730 val->single_tap = md1_cfg.int1_single_tap;
10731 val->sleep_change = md1_cfg.int1_sleep_change;
10732 val->step_detector = emb_func_int1.int1_step_detector;
10733 val->tilt = emb_func_int1.int1_tilt;
10734 val->sig_mot = emb_func_int1.int1_sig_mot;
10735 val->fsm_lc = emb_func_int1.int1_fsm_lc;
10736 val->fsm1 = fsm_int1_a.int1_fsm1;
10737 val->fsm2 = fsm_int1_a.int1_fsm2;
10738 val->fsm3 = fsm_int1_a.int1_fsm3;
10739 val->fsm4 = fsm_int1_a.int1_fsm4;
10740 val->fsm5 = fsm_int1_a.int1_fsm5;
10741 val->fsm6 = fsm_int1_a.int1_fsm6;
10742 val->fsm7 = fsm_int1_a.int1_fsm7;
10743 val->fsm8 = fsm_int1_a.int1_fsm8;
10744 val->fsm9 = fsm_int1_b.int1_fsm9;
10745 val->fsm10 = fsm_int1_b.int1_fsm10;
10746 val->fsm11 = fsm_int1_b.int1_fsm11;
10747 val->fsm12 = fsm_int1_b.int1_fsm12;
10748 val->fsm13 = fsm_int1_b.int1_fsm13;
10749 val->fsm14 = fsm_int1_b.int1_fsm14;
10750 val->fsm15 = fsm_int1_b.int1_fsm15;
10751 val->fsm16 = fsm_int1_b.int1_fsm16;
10752 val->mlc1 = mlc_int1.int1_mlc1;
10753 val->mlc2 = mlc_int1.int1_mlc2;
10754 val->mlc3 = mlc_int1.int1_mlc3;
10755 val->mlc4 = mlc_int1.int1_mlc4;
10756 val->mlc5 = mlc_int1.int1_mlc5;
10757 val->mlc6 = mlc_int1.int1_mlc6;
10758 val->mlc7 = mlc_int1.int1_mlc7;
10759 val->mlc8 = mlc_int1.int1_mlc8;
10760
10761 return ret;
10762 }
10763
10764 /**
10765 * @brief Route interrupt signals on int2 pin.[set]
10766 *
10767 * @param ctx communication interface handler. Use NULL to ignore
10768 * this interface.(ptr)
10769 * @param val the signals to route on int2 pin.
10770 * @retval interface status (MANDATORY: return 0 -> no Error).
10771 *
10772 */
lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dso32x_pin_int2_route_t val)10773 int32_t lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t *ctx,
10774 lsm6dso32x_pin_int2_route_t val)
10775 {
10776 lsm6dso32x_pin_int1_route_t pin_int1_route;
10777 lsm6dso32x_emb_func_int2_t emb_func_int2 = {0};
10778 lsm6dso32x_fsm_int2_a_t fsm_int2_a = {0};
10779 lsm6dso32x_fsm_int2_b_t fsm_int2_b = {0};
10780 lsm6dso32x_int2_ctrl_t int2_ctrl = {0};
10781 lsm6dso32x_mlc_int2_t mlc_int2 = {0};
10782 lsm6dso32x_tap_cfg2_t tap_cfg2;
10783 lsm6dso32x_md2_cfg_t md2_cfg = {0};
10784 lsm6dso32x_ctrl4_c_t ctrl4_c;
10785 int32_t ret;
10786 ret = 0;
10787
10788 if (ctx != NULL)
10789 {
10790 int2_ctrl.int2_drdy_xl = val.drdy_xl;
10791 int2_ctrl.int2_drdy_g = val.drdy_g;
10792 int2_ctrl.int2_drdy_temp = val.drdy_temp;
10793 int2_ctrl.int2_fifo_th = val.fifo_th;
10794 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
10795 int2_ctrl.int2_fifo_full = val.fifo_full;
10796 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
10797 md2_cfg.int2_timestamp = val.timestamp;
10798 md2_cfg.int2_6d = val.six_d;
10799 md2_cfg.int2_double_tap = val.double_tap;
10800 md2_cfg.int2_ff = val.free_fall;
10801 md2_cfg.int2_wu = val.wake_up;
10802 md2_cfg.int2_single_tap = val.single_tap;
10803 md2_cfg.int2_sleep_change = val.sleep_change;
10804 emb_func_int2. int2_step_detector = val.step_detector;
10805 emb_func_int2.int2_tilt = val.tilt;
10806 emb_func_int2.int2_fsm_lc = val.fsm_lc;
10807 fsm_int2_a.int2_fsm1 = val.fsm1;
10808 fsm_int2_a.int2_fsm2 = val.fsm2;
10809 fsm_int2_a.int2_fsm3 = val.fsm3;
10810 fsm_int2_a.int2_fsm4 = val.fsm4;
10811 fsm_int2_a.int2_fsm5 = val.fsm5;
10812 fsm_int2_a.int2_fsm6 = val.fsm6;
10813 fsm_int2_a.int2_fsm7 = val.fsm7;
10814 fsm_int2_a.int2_fsm8 = val.fsm8;
10815 fsm_int2_b.int2_fsm9 = val.fsm9 ;
10816 fsm_int2_b.int2_fsm10 = val.fsm10;
10817 fsm_int2_b.int2_fsm11 = val.fsm11;
10818 fsm_int2_b.int2_fsm12 = val.fsm12;
10819 fsm_int2_b.int2_fsm13 = val.fsm13;
10820 fsm_int2_b.int2_fsm14 = val.fsm14;
10821 fsm_int2_b.int2_fsm15 = val.fsm15;
10822 fsm_int2_b.int2_fsm16 = val.fsm16;
10823 mlc_int2.int2_mlc1 = val.mlc1;
10824 mlc_int2.int2_mlc2 = val.mlc2;
10825 mlc_int2.int2_mlc3 = val.mlc3;
10826 mlc_int2.int2_mlc4 = val.mlc4;
10827 mlc_int2.int2_mlc5 = val.mlc5;
10828 mlc_int2.int2_mlc6 = val.mlc6;
10829 mlc_int2.int2_mlc7 = val.mlc7;
10830 mlc_int2.int2_mlc8 = val.mlc8;
10831
10832 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10833 (uint8_t *)&ctrl4_c, 1);
10834
10835 if (ret == 0)
10836 {
10837 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
10838 {
10839 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
10840 }
10841 else
10842 {
10843 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
10844 }
10845
10846 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
10847 (uint8_t *)&ctrl4_c, 1);
10848 }
10849
10850 if (ret == 0)
10851 {
10852 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10853 }
10854
10855 if (ret == 0)
10856 {
10857 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT2,
10858 (uint8_t *)&mlc_int2, 1);
10859 }
10860
10861 if (ret == 0)
10862 {
10863 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
10864 (uint8_t *)&emb_func_int2, 1);
10865 }
10866
10867 if (ret == 0)
10868 {
10869 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_A,
10870 (uint8_t *)&fsm_int2_a, 1);
10871 }
10872
10873 if (ret == 0)
10874 {
10875 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_B,
10876 (uint8_t *)&fsm_int2_b, 1);
10877 }
10878
10879 if (ret == 0)
10880 {
10881 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10882 }
10883
10884 if (ret == 0)
10885 {
10886 if ((emb_func_int2.int2_fsm_lc
10887 | emb_func_int2.int2_sig_mot
10888 | emb_func_int2.int2_step_detector
10889 | emb_func_int2.int2_tilt
10890 | fsm_int2_a.int2_fsm1
10891 | fsm_int2_a.int2_fsm2
10892 | fsm_int2_a.int2_fsm3
10893 | fsm_int2_a.int2_fsm4
10894 | fsm_int2_a.int2_fsm5
10895 | fsm_int2_a.int2_fsm6
10896 | fsm_int2_a.int2_fsm7
10897 | fsm_int2_a.int2_fsm8
10898 | fsm_int2_b.int2_fsm9
10899 | fsm_int2_b.int2_fsm10
10900 | fsm_int2_b.int2_fsm11
10901 | fsm_int2_b.int2_fsm12
10902 | fsm_int2_b.int2_fsm13
10903 | fsm_int2_b.int2_fsm14
10904 | fsm_int2_b.int2_fsm15
10905 | fsm_int2_b.int2_fsm16
10906 | mlc_int2.int2_mlc1
10907 | mlc_int2.int2_mlc2
10908 | mlc_int2.int2_mlc3
10909 | mlc_int2.int2_mlc4
10910 | mlc_int2.int2_mlc5
10911 | mlc_int2.int2_mlc6
10912 | mlc_int2.int2_mlc7
10913 | mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
10914 {
10915 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
10916 }
10917
10918 else
10919 {
10920 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
10921 }
10922
10923 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
10924 (uint8_t *)&int2_ctrl, 1);
10925 }
10926
10927 if (ret == 0)
10928 {
10929 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
10930 (uint8_t *)&md2_cfg, 1);
10931 }
10932
10933 if (ret == 0)
10934 {
10935 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
10936 (uint8_t *) &tap_cfg2, 1);
10937 }
10938
10939 if (ret == 0)
10940 {
10941 ret = lsm6dso32x_pin_int1_route_get(ctx, &pin_int1_route);
10942 }
10943
10944 if (ret == 0)
10945 {
10946 if ((val.fifo_bdr
10947 | val.drdy_g
10948 | val.drdy_temp
10949 | val.drdy_xl
10950 | val.fifo_full
10951 | val.fifo_ovr
10952 | val.fifo_th
10953 | val.six_d
10954 | val.double_tap
10955 | val.free_fall
10956 | val.wake_up
10957 | val.single_tap
10958 | val.sleep_change
10959 | pin_int1_route.den_flag
10960 | pin_int1_route.boot
10961 | pin_int1_route.fifo_bdr
10962 | pin_int1_route.drdy_g
10963 | pin_int1_route.drdy_xl
10964 | pin_int1_route.fifo_full
10965 | pin_int1_route.fifo_ovr
10966 | pin_int1_route.fifo_th
10967 | pin_int1_route.six_d
10968 | pin_int1_route.double_tap
10969 | pin_int1_route.free_fall
10970 | pin_int1_route.wake_up
10971 | pin_int1_route.single_tap
10972 | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
10973 {
10974 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
10975 }
10976
10977 else
10978 {
10979 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
10980 }
10981
10982 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
10983 (uint8_t *) &tap_cfg2, 1);
10984 }
10985 }
10986
10987 return ret;
10988 }
10989
10990 /**
10991 * @brief Route interrupt signals on int2 pin.[get]
10992 *
10993 * @param ctx communication interface handler. Use NULL to ignore
10994 * this interface.(ptr)
10995 * @param val the signals that are routed on int2 pin.(ptr)
10996 * @retval interface status (MANDATORY: return 0 -> no Error).
10997 *
10998 */
lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dso32x_pin_int2_route_t * val)10999 int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx,
11000 lsm6dso32x_pin_int2_route_t *val)
11001 {
11002 lsm6dso32x_emb_func_int2_t emb_func_int2;
11003 lsm6dso32x_fsm_int2_a_t fsm_int2_a;
11004 lsm6dso32x_fsm_int2_b_t fsm_int2_b;
11005 lsm6dso32x_int2_ctrl_t int2_ctrl;
11006 lsm6dso32x_mlc_int2_t mlc_int2;
11007 lsm6dso32x_md2_cfg_t md2_cfg;
11008 lsm6dso32x_ctrl4_c_t ctrl4_c;
11009 int32_t ret;
11010 ret = 0;
11011
11012 if (ctx != NULL)
11013 {
11014 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
11015
11016 if (ret == 0)
11017 {
11018 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT2,
11019 (uint8_t *)&mlc_int2, 1);
11020 }
11021
11022 if (ret == 0)
11023 {
11024 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
11025 (uint8_t *)&emb_func_int2, 1);
11026 }
11027
11028 if (ret == 0)
11029 {
11030 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_A,
11031 (uint8_t *)&fsm_int2_a, 1);
11032 }
11033
11034 if (ret == 0)
11035 {
11036 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_B,
11037 (uint8_t *)&fsm_int2_b, 1);
11038 }
11039
11040 if (ret == 0)
11041 {
11042 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
11043 }
11044
11045 if (ret == 0)
11046 {
11047 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
11048 (uint8_t *)&int2_ctrl, 1);
11049 }
11050
11051 if (ret == 0)
11052 {
11053 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
11054 (uint8_t *)&md2_cfg, 1);
11055 }
11056
11057 if (ret == 0)
11058 {
11059 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
11060 (uint8_t *)&ctrl4_c, 1);
11061 }
11062
11063 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
11064 {
11065 if (ret == 0)
11066 {
11067 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
11068 (uint8_t *)&int2_ctrl, 1);
11069 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11070 }
11071
11072 if (ret == 0)
11073 {
11074 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
11075 (uint8_t *)&md2_cfg, 1);
11076 val->timestamp = md2_cfg.int2_timestamp;
11077 }
11078 }
11079
11080 else
11081 {
11082 val->drdy_temp = PROPERTY_DISABLE;
11083 val->timestamp = PROPERTY_DISABLE;
11084 }
11085
11086 val->drdy_xl = int2_ctrl.int2_drdy_xl;
11087 val->drdy_g = int2_ctrl.int2_drdy_g;
11088 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11089 val->fifo_th = int2_ctrl.int2_fifo_th;
11090 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
11091 val->fifo_full = int2_ctrl.int2_fifo_full;
11092 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
11093 val->timestamp = md2_cfg.int2_timestamp;
11094 val->six_d = md2_cfg.int2_6d;
11095 val->double_tap = md2_cfg.int2_double_tap;
11096 val->free_fall = md2_cfg.int2_ff;
11097 val->wake_up = md2_cfg.int2_wu;
11098 val->single_tap = md2_cfg.int2_single_tap;
11099 val->sleep_change = md2_cfg.int2_sleep_change;
11100 val->step_detector = emb_func_int2. int2_step_detector;
11101 val->tilt = emb_func_int2.int2_tilt;
11102 val->fsm_lc = emb_func_int2.int2_fsm_lc;
11103 val->fsm1 = fsm_int2_a.int2_fsm1;
11104 val->fsm2 = fsm_int2_a.int2_fsm2;
11105 val->fsm3 = fsm_int2_a.int2_fsm3;
11106 val->fsm4 = fsm_int2_a.int2_fsm4;
11107 val->fsm5 = fsm_int2_a.int2_fsm5;
11108 val->fsm6 = fsm_int2_a.int2_fsm6;
11109 val->fsm7 = fsm_int2_a.int2_fsm7;
11110 val->fsm8 = fsm_int2_a.int2_fsm8;
11111 val->fsm9 = fsm_int2_b.int2_fsm9;
11112 val->fsm10 = fsm_int2_b.int2_fsm10;
11113 val->fsm11 = fsm_int2_b.int2_fsm11;
11114 val->fsm12 = fsm_int2_b.int2_fsm12;
11115 val->fsm13 = fsm_int2_b.int2_fsm13;
11116 val->fsm14 = fsm_int2_b.int2_fsm14;
11117 val->fsm15 = fsm_int2_b.int2_fsm15;
11118 val->fsm16 = fsm_int2_b.int2_fsm16;
11119 val->mlc1 = mlc_int2.int2_mlc1;
11120 val->mlc2 = mlc_int2.int2_mlc2;
11121 val->mlc3 = mlc_int2.int2_mlc3;
11122 val->mlc4 = mlc_int2.int2_mlc4;
11123 val->mlc5 = mlc_int2.int2_mlc5;
11124 val->mlc6 = mlc_int2.int2_mlc6;
11125 val->mlc7 = mlc_int2.int2_mlc7;
11126 val->mlc8 = mlc_int2.int2_mlc8;
11127 }
11128
11129 return ret;
11130 }
11131
11132 /**
11133 * @brief Get the status of all the interrupt sources.[get]
11134 *
11135 * @param ctx communication interface handler.(ptr)
11136 * @param val the status of all the interrupt sources.(ptr)
11137 * @retval interface status (MANDATORY: return 0 -> no Error).
11138 *
11139 */
lsm6dso32x_all_sources_get(const stmdev_ctx_t * ctx,lsm6dso32x_all_sources_t * val)11140 int32_t lsm6dso32x_all_sources_get(const stmdev_ctx_t *ctx,
11141 lsm6dso32x_all_sources_t *val)
11142 {
11143 lsm6dso32x_emb_func_status_mainpage_t emb_func_status_mainpage;
11144 lsm6dso32x_status_master_mainpage_t status_master_mainpage;
11145 lsm6dso32x_fsm_status_a_mainpage_t fsm_status_a_mainpage;
11146 lsm6dso32x_fsm_status_b_mainpage_t fsm_status_b_mainpage;
11147 lsm6dso32x_mlc_status_mainpage_t mlc_status_mainpage;
11148 lsm6dso32x_fifo_status1_t fifo_status1;
11149 lsm6dso32x_fifo_status2_t fifo_status2;
11150 lsm6dso32x_all_int_src_t all_int_src;
11151 lsm6dso32x_wake_up_src_t wake_up_src;
11152 lsm6dso32x_status_reg_t status_reg;
11153 lsm6dso32x_tap_src_t tap_src;
11154 lsm6dso32x_d6d_src_t d6d_src;
11155 lsm6dso32x_ctrl5_c_t ctrl5_c;
11156 uint8_t reg[12];
11157 int32_t ret;
11158 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
11159 (uint8_t *)&ctrl5_c, 1);
11160
11161 if (ret == 0)
11162 {
11163 ctrl5_c.not_used_01 = PROPERTY_ENABLE;
11164 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
11165 (uint8_t *)&ctrl5_c, 1);
11166 }
11167
11168 if (ret == 0)
11169 {
11170 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_ALL_INT_SRC, reg, 12);
11171 }
11172
11173 if (ret == 0)
11174 {
11175 bytecpy((uint8_t *)&all_int_src, ®[0]);
11176 bytecpy((uint8_t *)&wake_up_src, ®[1]);
11177 bytecpy((uint8_t *)&tap_src, ®[2]);
11178 bytecpy((uint8_t *)&d6d_src, ®[3]);
11179 bytecpy((uint8_t *)&status_reg, ®[4]);
11180 bytecpy((uint8_t *)&emb_func_status_mainpage, ®[5]);
11181 bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[6]);
11182 bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[7]);
11183 bytecpy((uint8_t *)&mlc_status_mainpage, ®[8]);
11184 bytecpy((uint8_t *)&status_master_mainpage, ®[9]);
11185 bytecpy((uint8_t *)&fifo_status1, ®[10]);
11186 bytecpy((uint8_t *)&fifo_status2, ®[11]);
11187 val->timestamp = all_int_src.timestamp_endcount;
11188 val->wake_up_z = wake_up_src.z_wu;
11189 val->wake_up_y = wake_up_src.y_wu;
11190 val->wake_up_x = wake_up_src.x_wu;
11191 val->wake_up = wake_up_src.wu_ia;
11192 val->sleep_state = wake_up_src.sleep_state;
11193 val->free_fall = wake_up_src.ff_ia;
11194 val->sleep_change = wake_up_src.sleep_change_ia;
11195 val->tap_x = tap_src.x_tap;
11196 val->tap_y = tap_src.y_tap;
11197 val->tap_z = tap_src.z_tap;
11198 val->tap_sign = tap_src.tap_sign;
11199 val->double_tap = tap_src.double_tap;
11200 val->single_tap = tap_src.single_tap;
11201 val->six_d_xl = d6d_src.xl;
11202 val->six_d_xh = d6d_src.xh;
11203 val->six_d_yl = d6d_src.yl;
11204 val->six_d_yh = d6d_src.yh;
11205 val->six_d_zl = d6d_src.zl;
11206 val->six_d_zh = d6d_src.zh;
11207 val->six_d = d6d_src.d6d_ia;
11208 val->den_flag = d6d_src.den_drdy;
11209 val->drdy_xl = status_reg.xlda;
11210 val->drdy_g = status_reg.gda;
11211 val->drdy_temp = status_reg.tda;
11212 val->step_detector = emb_func_status_mainpage.is_step_det;
11213 val->tilt = emb_func_status_mainpage.is_tilt;
11214 val->sig_mot = emb_func_status_mainpage.is_sigmot;
11215 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
11216 val->fsm1 = fsm_status_a_mainpage.is_fsm1;
11217 val->fsm2 = fsm_status_a_mainpage.is_fsm2;
11218 val->fsm3 = fsm_status_a_mainpage.is_fsm3;
11219 val->fsm4 = fsm_status_a_mainpage.is_fsm4;
11220 val->fsm5 = fsm_status_a_mainpage.is_fsm5;
11221 val->fsm6 = fsm_status_a_mainpage.is_fsm6;
11222 val->fsm7 = fsm_status_a_mainpage.is_fsm7;
11223 val->fsm8 = fsm_status_a_mainpage.is_fsm8;
11224 val->fsm9 = fsm_status_b_mainpage.is_fsm9;
11225 val->fsm10 = fsm_status_b_mainpage.is_fsm10;
11226 val->fsm11 = fsm_status_b_mainpage.is_fsm11;
11227 val->fsm12 = fsm_status_b_mainpage.is_fsm12;
11228 val->fsm13 = fsm_status_b_mainpage.is_fsm13;
11229 val->fsm14 = fsm_status_b_mainpage.is_fsm14;
11230 val->fsm15 = fsm_status_b_mainpage.is_fsm15;
11231 val->fsm16 = fsm_status_b_mainpage.is_fsm16;
11232 val->mlc1 = mlc_status_mainpage.is_mlc1;
11233 val->mlc2 = mlc_status_mainpage.is_mlc2;
11234 val->mlc3 = mlc_status_mainpage.is_mlc3;
11235 val->mlc4 = mlc_status_mainpage.is_mlc4;
11236 val->mlc5 = mlc_status_mainpage.is_mlc5;
11237 val->mlc6 = mlc_status_mainpage.is_mlc6;
11238 val->mlc7 = mlc_status_mainpage.is_mlc7;
11239 val->mlc8 = mlc_status_mainpage.is_mlc8;
11240 val->sh_endop = status_master_mainpage.sens_hub_endop;
11241 val->sh_slave0_nack = status_master_mainpage.slave0_nack;
11242 val->sh_slave1_nack = status_master_mainpage.slave1_nack;
11243 val->sh_slave2_nack = status_master_mainpage.slave2_nack;
11244 val->sh_slave3_nack = status_master_mainpage.slave3_nack;
11245 val->sh_wr_once = status_master_mainpage.wr_once_done;
11246 val->fifo_diff = (256U * fifo_status2.diff_fifo) +
11247 fifo_status1.diff_fifo;
11248 val->fifo_ovr_latched = fifo_status2.over_run_latched;
11249 val->fifo_bdr = fifo_status2.counter_bdr_ia;
11250 val->fifo_full = fifo_status2.fifo_full_ia;
11251 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
11252 val->fifo_th = fifo_status2.fifo_wtm_ia;
11253 ctrl5_c.not_used_01 = PROPERTY_DISABLE;
11254 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
11255 (uint8_t *)&ctrl5_c, 1);
11256 }
11257
11258 return ret;
11259 }
11260
11261 /**
11262 * @brief Sensor conversion parameters selection.[set]
11263 *
11264 * @param ctx communication interface handler. Use NULL to ignore
11265 * this interface.(ptr)
11266 * @param val set the sensor conversion parameters by checking
11267 * the constraints of the device.(ptr)
11268 * @retval interface status (MANDATORY: return 0 -> no Error).
11269 *
11270 */
lsm6dso32x_mode_set(const stmdev_ctx_t * ctx,lsm6dso32x_md_t * val)11271 int32_t lsm6dso32x_mode_set(const stmdev_ctx_t *ctx,
11272 lsm6dso32x_md_t *val)
11273 {
11274 lsm6dso32x_func_cfg_access_t func_cfg_access;
11275 lsm6dso32x_ctrl1_xl_t ctrl1_xl;
11276 lsm6dso32x_ctrl8_xl_t ctrl8_xl;
11277 lsm6dso32x_ctrl2_g_t ctrl2_g;
11278 lsm6dso32x_ctrl3_c_t ctrl3_c = {0};
11279 lsm6dso32x_ctrl4_c_t ctrl4_c = {0};
11280 lsm6dso32x_ctrl5_c_t ctrl5_c;
11281 lsm6dso32x_ctrl6_c_t ctrl6_c;
11282 lsm6dso32x_ctrl7_g_t ctrl7_g;
11283 uint8_t xl_hm_mode;
11284 uint8_t g_hm_mode;
11285 uint8_t xl_ulp_en;
11286 uint8_t odr_gy;
11287 uint8_t odr_xl;
11288 uint8_t reg[8];
11289 int32_t ret;
11290
11291 ret = 0;
11292 /* FIXME: Remove warnings with STM32CubeIDE */
11293 ctrl3_c.not_used_01 = 0;
11294 ctrl4_c.not_used_01 = 0;
11295 /* reading input configuration */
11296 xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
11297 xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
11298 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
11299 g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
11300 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
11301
11302 /* reading registers to be configured */
11303 if (ctx != NULL)
11304 {
11305 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 8);
11306 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
11307 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
11308 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
11309 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
11310 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
11311 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
11312 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
11313 bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
11314
11315 if (ret == 0)
11316 {
11317 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11318 (uint8_t *)&func_cfg_access, 1);
11319 }
11320
11321 /* if toggle xl ultra low power mode, turn off xl before reconfigure */
11322 if (ctrl5_c.xl_ulp_en != xl_ulp_en)
11323 {
11324 ctrl1_xl.odr_xl = (uint8_t) 0x00U;
11325 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL,
11326 (uint8_t *)&ctrl1_xl, 1);
11327 }
11328 }
11329
11330 /* Check the Finite State Machine data rate constraints */
11331 if (val->fsm.sens != LSM6DSO32X_FSM_DISABLE)
11332 {
11333 switch (val->fsm.odr)
11334 {
11335 case LSM6DSO32X_ODR_FSM_12Hz5:
11336 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl == 0x00U))
11337 {
11338 odr_xl = 0x01U;
11339 }
11340
11341 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy == 0x00U))
11342 {
11343 xl_ulp_en = PROPERTY_DISABLE;
11344 odr_gy = 0x01U;
11345 }
11346
11347 break;
11348
11349 case LSM6DSO32X_ODR_FSM_26Hz:
11350 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x02U))
11351 {
11352 odr_xl = 0x02U;
11353 }
11354
11355 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x02U))
11356 {
11357 xl_ulp_en = PROPERTY_DISABLE;
11358 odr_gy = 0x02U;
11359 }
11360
11361 break;
11362
11363 case LSM6DSO32X_ODR_FSM_52Hz:
11364 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x03U))
11365 {
11366 odr_xl = 0x03U;
11367 }
11368
11369 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x03U))
11370 {
11371 xl_ulp_en = PROPERTY_DISABLE;
11372 odr_gy = 0x03U;
11373 }
11374
11375 break;
11376
11377 case LSM6DSO32X_ODR_FSM_104Hz:
11378 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x04U))
11379 {
11380 odr_xl = 0x04U;
11381 }
11382
11383 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x04U))
11384 {
11385 xl_ulp_en = PROPERTY_DISABLE;
11386 odr_gy = 0x04U;
11387 }
11388
11389 break;
11390
11391 default:
11392 odr_xl = 0x00U;
11393 odr_gy = 0x00U;
11394 break;
11395 }
11396 }
11397
11398 /* Check the Machine Learning Core data rate constraints */
11399 if (val->mlc.sens != LSM6DSO32X_MLC_DISABLE)
11400 {
11401 switch (val->mlc.odr)
11402 {
11403 case LSM6DSO32X_ODR_PRGS_12Hz5:
11404 if (odr_xl == 0x00U)
11405 {
11406 odr_xl = 0x01U;
11407 }
11408
11409 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy == 0x00U))
11410 {
11411 xl_ulp_en = PROPERTY_DISABLE;
11412 odr_gy = 0x01U;
11413 }
11414
11415 break;
11416
11417 case LSM6DSO32X_ODR_PRGS_26Hz:
11418 if (odr_xl < 0x02U)
11419 {
11420 odr_xl = 0x02U;
11421 }
11422
11423 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x02U))
11424 {
11425 xl_ulp_en = PROPERTY_DISABLE;
11426 odr_gy = 0x02U;
11427 }
11428
11429 break;
11430
11431 case LSM6DSO32X_ODR_PRGS_52Hz:
11432 if (odr_xl < 0x03U)
11433 {
11434 odr_xl = 0x03U;
11435 }
11436
11437 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x03U))
11438 {
11439 xl_ulp_en = PROPERTY_DISABLE;
11440 odr_gy = 0x03U;
11441 }
11442
11443 break;
11444
11445 case LSM6DSO32X_ODR_PRGS_104Hz:
11446 if (odr_xl < 0x04U)
11447 {
11448 odr_xl = 0x04U;
11449 }
11450
11451 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x04U))
11452 {
11453 xl_ulp_en = PROPERTY_DISABLE;
11454 odr_gy = 0x04U;
11455 }
11456
11457 break;
11458
11459 default:
11460 odr_xl = 0x00U;
11461 odr_gy = 0x00U;
11462 break;
11463 }
11464 }
11465
11466 /* Updating the accelerometer data rate configuration */
11467 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
11468 ctrl1_xl.odr_xl)
11469 {
11470 case LSM6DSO32X_XL_UI_OFF:
11471 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11472 break;
11473
11474 case LSM6DSO32X_XL_UI_12Hz5_HP:
11475 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
11476 break;
11477
11478 case LSM6DSO32X_XL_UI_26Hz_HP:
11479 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
11480 break;
11481
11482 case LSM6DSO32X_XL_UI_52Hz_HP:
11483 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
11484 break;
11485
11486 case LSM6DSO32X_XL_UI_104Hz_HP:
11487 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
11488 break;
11489
11490 case LSM6DSO32X_XL_UI_208Hz_HP:
11491 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
11492 break;
11493
11494 case LSM6DSO32X_XL_UI_416Hz_HP:
11495 val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
11496 break;
11497
11498 case LSM6DSO32X_XL_UI_833Hz_HP:
11499 val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
11500 break;
11501
11502 case LSM6DSO32X_XL_UI_1667Hz_HP:
11503 val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
11504 break;
11505
11506 case LSM6DSO32X_XL_UI_3333Hz_HP:
11507 val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
11508 break;
11509
11510 case LSM6DSO32X_XL_UI_6667Hz_HP:
11511 val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
11512 break;
11513
11514 case LSM6DSO32X_XL_UI_1Hz6_LP:
11515 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
11516 break;
11517
11518 case LSM6DSO32X_XL_UI_12Hz5_LP:
11519 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
11520 break;
11521
11522 case LSM6DSO32X_XL_UI_26Hz_LP:
11523 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
11524 break;
11525
11526 case LSM6DSO32X_XL_UI_52Hz_LP:
11527 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
11528 break;
11529
11530 case LSM6DSO32X_XL_UI_104Hz_NM:
11531 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
11532 break;
11533
11534 case LSM6DSO32X_XL_UI_208Hz_NM:
11535 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
11536 break;
11537
11538 case LSM6DSO32X_XL_UI_1Hz6_ULP:
11539 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
11540 break;
11541
11542 case LSM6DSO32X_XL_UI_12Hz5_ULP:
11543 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
11544 break;
11545
11546 case LSM6DSO32X_XL_UI_26Hz_ULP:
11547 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
11548 break;
11549
11550 case LSM6DSO32X_XL_UI_52Hz_ULP:
11551 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
11552 break;
11553
11554 case LSM6DSO32X_XL_UI_104Hz_ULP:
11555 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
11556 break;
11557
11558 case LSM6DSO32X_XL_UI_208Hz_ULP:
11559 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
11560 break;
11561
11562 default:
11563 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11564 break;
11565 }
11566
11567 /* Updating the accelerometer data rate configuration */
11568 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
11569 {
11570 case LSM6DSO32X_GY_UI_OFF:
11571 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11572 break;
11573
11574 case LSM6DSO32X_GY_UI_12Hz5_LP:
11575 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
11576 break;
11577
11578 case LSM6DSO32X_GY_UI_12Hz5_HP:
11579 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
11580 break;
11581
11582 case LSM6DSO32X_GY_UI_26Hz_LP:
11583 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
11584 break;
11585
11586 case LSM6DSO32X_GY_UI_26Hz_HP:
11587 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
11588 break;
11589
11590 case LSM6DSO32X_GY_UI_52Hz_LP:
11591 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
11592 break;
11593
11594 case LSM6DSO32X_GY_UI_52Hz_HP:
11595 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
11596 break;
11597
11598 case LSM6DSO32X_GY_UI_104Hz_NM:
11599 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
11600 break;
11601
11602 case LSM6DSO32X_GY_UI_104Hz_HP:
11603 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
11604 break;
11605
11606 case LSM6DSO32X_GY_UI_208Hz_NM:
11607 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
11608 break;
11609
11610 case LSM6DSO32X_GY_UI_208Hz_HP:
11611 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
11612 break;
11613
11614 case LSM6DSO32X_GY_UI_416Hz_HP:
11615 val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
11616 break;
11617
11618 case LSM6DSO32X_GY_UI_833Hz_HP:
11619 val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
11620 break;
11621
11622 case LSM6DSO32X_GY_UI_1667Hz_HP:
11623 val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
11624 break;
11625
11626 case LSM6DSO32X_GY_UI_3333Hz_HP:
11627 val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
11628 break;
11629
11630 case LSM6DSO32X_GY_UI_6667Hz_HP:
11631 val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
11632 break;
11633
11634 default:
11635 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11636 break;
11637 }
11638
11639 /* prapare new configuration */
11640 /* UI new configuration */
11641 ctrl1_xl.odr_xl = odr_xl;
11642 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
11643 ctrl5_c.xl_ulp_en = xl_ulp_en;
11644 ctrl6_c.xl_hm_mode = xl_hm_mode;
11645 ctrl7_g.g_hm_mode = g_hm_mode;
11646 ctrl2_g.odr_g = odr_gy;
11647 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
11648
11649 /* writing checked configuration */
11650 if (ctx != NULL)
11651 {
11652 bytecpy(®[0], (uint8_t *)&ctrl1_xl);
11653 bytecpy(®[1], (uint8_t *)&ctrl2_g);
11654 bytecpy(®[2], (uint8_t *)&ctrl3_c);
11655 bytecpy(®[3], (uint8_t *)&ctrl4_c);
11656 bytecpy(®[4], (uint8_t *)&ctrl5_c);
11657 bytecpy(®[5], (uint8_t *)&ctrl6_c);
11658 bytecpy(®[6], (uint8_t *)&ctrl7_g);
11659 bytecpy(®[7], (uint8_t *)&ctrl8_xl);
11660
11661 if (ret == 0)
11662 {
11663 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®,
11664 8);
11665 }
11666
11667 if (ret == 0)
11668 {
11669 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11670 (uint8_t *)&func_cfg_access, 1);
11671 }
11672 }
11673
11674 return ret;
11675 }
11676
11677 /**
11678 * @brief Sensor conversion parameters selection.[get]
11679 *
11680 * @param ctx communication interface handler. Use NULL to ignore
11681 * this interface.(ptr)
11682 * @param val get the sensor conversion parameters.(ptr)
11683 * @retval interface status (MANDATORY: return 0 -> no Error).
11684 *
11685 */
lsm6dso32x_mode_get(const stmdev_ctx_t * ctx,lsm6dso32x_md_t * val)11686 int32_t lsm6dso32x_mode_get(const stmdev_ctx_t *ctx,
11687 lsm6dso32x_md_t *val)
11688 {
11689 lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
11690 lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
11691 lsm6dso32x_func_cfg_access_t func_cfg_access;
11692 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
11693 lsm6dso32x_fsm_enable_a_t fsm_enable_a;
11694 lsm6dso32x_fsm_enable_b_t fsm_enable_b;
11695 lsm6dso32x_ctrl1_xl_t ctrl1_xl;
11696 lsm6dso32x_ctrl2_g_t ctrl2_g;
11697 lsm6dso32x_ctrl3_c_t ctrl3_c;
11698 lsm6dso32x_ctrl4_c_t ctrl4_c;
11699 lsm6dso32x_ctrl5_c_t ctrl5_c;
11700 lsm6dso32x_ctrl6_c_t ctrl6_c;
11701 lsm6dso32x_ctrl7_g_t ctrl7_g;
11702 uint8_t reg[8];
11703 int32_t ret;
11704
11705 ret = 0;
11706
11707 /* reading the registers of the device */
11708 if (ctx != NULL)
11709 {
11710 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 7);
11711 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
11712 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
11713 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
11714 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
11715 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
11716 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
11717 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
11718
11719 if (ret == 0)
11720 {
11721 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11722 (uint8_t *)&func_cfg_access, 1);
11723 }
11724
11725 if (ret == 0)
11726 {
11727 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
11728 }
11729
11730 if (ret == 0)
11731 {
11732 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B, reg, 2);
11733 bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
11734 bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]);
11735 }
11736
11737 if (ret == 0)
11738 {
11739 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
11740 (uint8_t *)&emb_func_en_b, 1);
11741 }
11742
11743 if (ret == 0)
11744 {
11745 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A, reg, 2);
11746 bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
11747 bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
11748 }
11749
11750 if (ret == 0)
11751 {
11752 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
11753 }
11754 }
11755
11756 /* fill the input structure */
11757
11758 /* get accelerometer configuration */
11759 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
11760 ctrl1_xl.odr_xl)
11761 {
11762 case LSM6DSO32X_XL_UI_OFF:
11763 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11764 break;
11765
11766 case LSM6DSO32X_XL_UI_12Hz5_HP:
11767 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
11768 break;
11769
11770 case LSM6DSO32X_XL_UI_26Hz_HP:
11771 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
11772 break;
11773
11774 case LSM6DSO32X_XL_UI_52Hz_HP:
11775 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
11776 break;
11777
11778 case LSM6DSO32X_XL_UI_104Hz_HP:
11779 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
11780 break;
11781
11782 case LSM6DSO32X_XL_UI_208Hz_HP:
11783 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
11784 break;
11785
11786 case LSM6DSO32X_XL_UI_416Hz_HP:
11787 val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
11788 break;
11789
11790 case LSM6DSO32X_XL_UI_833Hz_HP:
11791 val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
11792 break;
11793
11794 case LSM6DSO32X_XL_UI_1667Hz_HP:
11795 val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
11796 break;
11797
11798 case LSM6DSO32X_XL_UI_3333Hz_HP:
11799 val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
11800 break;
11801
11802 case LSM6DSO32X_XL_UI_6667Hz_HP:
11803 val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
11804 break;
11805
11806 case LSM6DSO32X_XL_UI_1Hz6_LP:
11807 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
11808 break;
11809
11810 case LSM6DSO32X_XL_UI_12Hz5_LP:
11811 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
11812 break;
11813
11814 case LSM6DSO32X_XL_UI_26Hz_LP:
11815 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
11816 break;
11817
11818 case LSM6DSO32X_XL_UI_52Hz_LP:
11819 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
11820 break;
11821
11822 case LSM6DSO32X_XL_UI_104Hz_NM:
11823 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
11824 break;
11825
11826 case LSM6DSO32X_XL_UI_208Hz_NM:
11827 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
11828 break;
11829
11830 case LSM6DSO32X_XL_UI_1Hz6_ULP:
11831 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
11832 break;
11833
11834 case LSM6DSO32X_XL_UI_12Hz5_ULP:
11835 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
11836 break;
11837
11838 case LSM6DSO32X_XL_UI_26Hz_ULP:
11839 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
11840 break;
11841
11842 case LSM6DSO32X_XL_UI_52Hz_ULP:
11843 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
11844 break;
11845
11846 case LSM6DSO32X_XL_UI_104Hz_ULP:
11847 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
11848 break;
11849
11850 case LSM6DSO32X_XL_UI_208Hz_ULP:
11851 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
11852 break;
11853
11854 default:
11855 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11856 break;
11857 }
11858
11859 switch (ctrl1_xl.fs_xl)
11860 {
11861 case LSM6DSO32X_XL_UI_32g:
11862 val->ui.xl.fs = LSM6DSO32X_XL_UI_32g;
11863 break;
11864
11865 case LSM6DSO32X_XL_UI_4g:
11866 val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
11867 break;
11868
11869 case LSM6DSO32X_XL_UI_8g:
11870 val->ui.xl.fs = LSM6DSO32X_XL_UI_8g;
11871 break;
11872
11873 case LSM6DSO32X_XL_UI_16g:
11874 val->ui.xl.fs = LSM6DSO32X_XL_UI_16g;
11875 break;
11876
11877 default:
11878 val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
11879 break;
11880 }
11881
11882 /* get gyroscope configuration */
11883 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
11884 {
11885 case LSM6DSO32X_GY_UI_OFF:
11886 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11887 break;
11888
11889 case LSM6DSO32X_GY_UI_12Hz5_LP:
11890 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
11891 break;
11892
11893 case LSM6DSO32X_GY_UI_12Hz5_HP:
11894 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
11895 break;
11896
11897 case LSM6DSO32X_GY_UI_26Hz_LP:
11898 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
11899 break;
11900
11901 case LSM6DSO32X_GY_UI_26Hz_HP:
11902 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
11903 break;
11904
11905 case LSM6DSO32X_GY_UI_52Hz_LP:
11906 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
11907 break;
11908
11909 case LSM6DSO32X_GY_UI_52Hz_HP:
11910 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
11911 break;
11912
11913 case LSM6DSO32X_GY_UI_104Hz_NM:
11914 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
11915 break;
11916
11917 case LSM6DSO32X_GY_UI_104Hz_HP:
11918 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
11919 break;
11920
11921 case LSM6DSO32X_GY_UI_208Hz_NM:
11922 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
11923 break;
11924
11925 case LSM6DSO32X_GY_UI_208Hz_HP:
11926 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
11927 break;
11928
11929 case LSM6DSO32X_GY_UI_416Hz_HP:
11930 val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
11931 break;
11932
11933 case LSM6DSO32X_GY_UI_833Hz_HP:
11934 val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
11935 break;
11936
11937 case LSM6DSO32X_GY_UI_1667Hz_HP:
11938 val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
11939 break;
11940
11941 case LSM6DSO32X_GY_UI_3333Hz_HP:
11942 val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
11943 break;
11944
11945 case LSM6DSO32X_GY_UI_6667Hz_HP:
11946 val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
11947 break;
11948
11949 default:
11950 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11951 break;
11952 }
11953
11954 switch (ctrl2_g.fs_g)
11955 {
11956 case LSM6DSO32X_GY_UI_125dps:
11957 val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
11958 break;
11959
11960 case LSM6DSO32X_GY_UI_250dps:
11961 val->ui.gy.fs = LSM6DSO32X_GY_UI_250dps;
11962 break;
11963
11964 case LSM6DSO32X_GY_UI_500dps:
11965 val->ui.gy.fs = LSM6DSO32X_GY_UI_500dps;
11966 break;
11967
11968 case LSM6DSO32X_GY_UI_1000dps:
11969 val->ui.gy.fs = LSM6DSO32X_GY_UI_1000dps;
11970 break;
11971
11972 case LSM6DSO32X_GY_UI_2000dps:
11973 val->ui.gy.fs = LSM6DSO32X_GY_UI_2000dps;
11974 break;
11975
11976 default:
11977 val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
11978 break;
11979 }
11980
11981 /* get finite state machine configuration */
11982 if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
11983 fsm_enable_a.fsm3_en |
11984 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
11985 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
11986 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
11987 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
11988 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
11989 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
11990 {
11991 switch (emb_func_odr_cfg_b.fsm_odr)
11992 {
11993 case LSM6DSO32X_ODR_FSM_12Hz5:
11994 val->fsm.odr = LSM6DSO32X_ODR_FSM_12Hz5;
11995 break;
11996
11997 case LSM6DSO32X_ODR_FSM_26Hz:
11998 val->fsm.odr = LSM6DSO32X_ODR_FSM_26Hz;
11999 break;
12000
12001 case LSM6DSO32X_ODR_FSM_52Hz:
12002 val->fsm.odr = LSM6DSO32X_ODR_FSM_52Hz;
12003 break;
12004
12005 case LSM6DSO32X_ODR_FSM_104Hz:
12006 val->fsm.odr = LSM6DSO32X_ODR_FSM_104Hz;
12007 break;
12008
12009 default:
12010 val->fsm.odr = LSM6DSO32X_ODR_FSM_12Hz5;
12011 break;
12012 }
12013
12014 val->fsm.sens = LSM6DSO32X_FSM_XL_GY;
12015
12016 if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
12017 {
12018 val->fsm.sens = LSM6DSO32X_FSM_XL;
12019 }
12020
12021 if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
12022 {
12023 val->fsm.sens = LSM6DSO32X_FSM_GY;
12024 }
12025 }
12026
12027 else
12028 {
12029 val->fsm.sens = LSM6DSO32X_FSM_DISABLE;
12030 }
12031
12032 /* get machine learning core configuration */
12033 if (emb_func_en_b.mlc_en == PROPERTY_ENABLE)
12034 {
12035 switch (emb_func_odr_cfg_c.mlc_odr)
12036 {
12037 case LSM6DSO32X_ODR_PRGS_12Hz5:
12038 val->mlc.odr = LSM6DSO32X_ODR_PRGS_12Hz5;
12039 break;
12040
12041 case LSM6DSO32X_ODR_PRGS_26Hz:
12042 val->mlc.odr = LSM6DSO32X_ODR_PRGS_26Hz;
12043 break;
12044
12045 case LSM6DSO32X_ODR_PRGS_52Hz:
12046 val->mlc.odr = LSM6DSO32X_ODR_PRGS_52Hz;
12047 break;
12048
12049 case LSM6DSO32X_ODR_PRGS_104Hz:
12050 val->mlc.odr = LSM6DSO32X_ODR_PRGS_104Hz;
12051 break;
12052
12053 default:
12054 val->mlc.odr = LSM6DSO32X_ODR_PRGS_12Hz5;
12055 break;
12056 }
12057
12058 val->mlc.sens = LSM6DSO32X_MLC_XL_GY;
12059
12060 if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
12061 {
12062 val->mlc.sens = LSM6DSO32X_MLC_XL;
12063 }
12064
12065 if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
12066 {
12067 val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
12068 }
12069 }
12070
12071 else
12072 {
12073 val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
12074 }
12075
12076 return ret;
12077 }
12078
12079 /**
12080 * @brief Read data in engineering unit.[get]
12081 *
12082 * @param ctx communication interface handler.(ptr)
12083 * @param md the sensor conversion parameters.(ptr)
12084 * @retval interface status (MANDATORY: return 0 -> no Error).
12085 *
12086 */
lsm6dso32x_data_get(const stmdev_ctx_t * ctx,lsm6dso32x_md_t * md,lsm6dso32x_data_t * data)12087 int32_t lsm6dso32x_data_get(const stmdev_ctx_t *ctx,
12088 lsm6dso32x_md_t *md,
12089 lsm6dso32x_data_t *data)
12090 {
12091 uint8_t buff[14];
12092 int32_t ret;
12093
12094 uint8_t i;
12095 uint8_t j;
12096 ret = 0;
12097
12098 /* read data */
12099 if (ctx != NULL)
12100 {
12101 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 14);
12102 }
12103
12104 j = 0;
12105 /* temperature conversion */
12106 data->ui.heat.raw = (int16_t)buff[j + 1U];
12107 data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
12108 (int16_t)buff[j]);
12109 j += 2U;
12110 data->ui.heat.deg_c = lsm6dso32x_from_lsb_to_celsius((
12111 int16_t)data->ui.heat.raw);
12112
12113 /* angular rate conversion */
12114 for (i = 0U; i < 3U; i++)
12115 {
12116 data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
12117 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
12118 j += 2U;
12119
12120 switch (md->ui.gy.fs)
12121 {
12122 case LSM6DSO32X_GY_UI_250dps:
12123 data->ui.gy.mdps[i] = lsm6dso32x_from_fs250_to_mdps(
12124 data->ui.gy.raw[i]);
12125 break;
12126
12127 case LSM6DSO32X_GY_UI_125dps:
12128 data->ui.gy.mdps[i] = lsm6dso32x_from_fs125_to_mdps(
12129 data->ui.gy.raw[i]);
12130 break;
12131
12132 case LSM6DSO32X_GY_UI_500dps:
12133 data->ui.gy.mdps[i] = lsm6dso32x_from_fs500_to_mdps(
12134 data->ui.gy.raw[i]);
12135 break;
12136
12137 case LSM6DSO32X_GY_UI_1000dps:
12138 data->ui.gy.mdps[i] = lsm6dso32x_from_fs1000_to_mdps(
12139 data->ui.gy.raw[i]);
12140 break;
12141
12142 case LSM6DSO32X_GY_UI_2000dps:
12143 data->ui.gy.mdps[i] = lsm6dso32x_from_fs2000_to_mdps(
12144 data->ui.gy.raw[i]);
12145 break;
12146
12147 default:
12148 data->ui.gy.mdps[i] = 0.0f;
12149 break;
12150 }
12151 }
12152
12153 /* acceleration conversion */
12154 for (i = 0U; i < 3U; i++)
12155 {
12156 data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
12157 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
12158 j += 2U;
12159
12160 switch (md->ui.xl.fs)
12161 {
12162 case LSM6DSO32X_XL_UI_4g:
12163 data->ui.xl.mg[i] = lsm6dso32x_from_fs4_to_mg(data->ui.xl.raw[i]);
12164 break;
12165
12166 case LSM6DSO32X_XL_UI_32g:
12167 data->ui.xl.mg[i] = lsm6dso32x_from_fs32_to_mg(data->ui.xl.raw[i]);
12168 break;
12169
12170 case LSM6DSO32X_XL_UI_8g:
12171 data->ui.xl.mg[i] = lsm6dso32x_from_fs8_to_mg(data->ui.xl.raw[i]);
12172 break;
12173
12174 case LSM6DSO32X_XL_UI_16g:
12175 data->ui.xl.mg[i] = lsm6dso32x_from_fs16_to_mg(data->ui.xl.raw[i]);
12176 break;
12177
12178 default:
12179 data->ui.xl.mg[i] = 0.0f;
12180 break;
12181 }
12182 }
12183
12184 return ret;
12185 }
12186
12187 /**
12188 * @brief Embedded functions.[set]
12189 *
12190 * @param ctx read / write interface definitions
12191 * @param val change the values of registers
12192 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12193 * @retval interface status (MANDATORY: return 0 -> no Error).
12194 *
12195 */
lsm6dso32x_embedded_sens_set(const stmdev_ctx_t * ctx,lsm6dso32x_emb_sens_t * val)12196 int32_t lsm6dso32x_embedded_sens_set(const stmdev_ctx_t *ctx,
12197 lsm6dso32x_emb_sens_t *val)
12198 {
12199 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12200 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12201 int32_t ret;
12202
12203 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12204
12205 if (ret == 0)
12206 {
12207 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12208 (uint8_t *)&emb_func_en_a, 1);
12209 }
12210
12211 if (ret == 0)
12212 {
12213 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12214 (uint8_t *)&emb_func_en_b, 1);
12215 emb_func_en_b.mlc_en = val->mlc;
12216 emb_func_en_b.fsm_en = val->fsm;
12217 emb_func_en_a.tilt_en = val->tilt;
12218 emb_func_en_a.pedo_en = val->step;
12219 emb_func_en_a.sign_motion_en = val->sig_mot;
12220 emb_func_en_b.fifo_compr_en = val->fifo_compr;
12221 }
12222
12223 if (ret == 0)
12224 {
12225 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12226 (uint8_t *)&emb_func_en_a, 1);
12227 }
12228
12229 if (ret == 0)
12230 {
12231 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12232 (uint8_t *)&emb_func_en_b, 1);
12233 }
12234
12235 if (ret == 0)
12236 {
12237 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12238 }
12239
12240 return ret;
12241 }
12242
12243 /**
12244 * @brief Embedded functions.[get]
12245 *
12246 * @param ctx read / write interface definitions
12247 * @param val get the values of registers
12248 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12249 * @retval interface status (MANDATORY: return 0 -> no Error).
12250 *
12251 */
lsm6dso32x_embedded_sens_get(const stmdev_ctx_t * ctx,lsm6dso32x_emb_sens_t * emb_sens)12252 int32_t lsm6dso32x_embedded_sens_get(const stmdev_ctx_t *ctx,
12253 lsm6dso32x_emb_sens_t *emb_sens)
12254 {
12255 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12256 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12257 int32_t ret;
12258
12259 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12260
12261 if (ret == 0)
12262 {
12263 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12264 (uint8_t *)&emb_func_en_a, 1);
12265 }
12266
12267 if (ret == 0)
12268 {
12269 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12270 (uint8_t *)&emb_func_en_b, 1);
12271 emb_sens->mlc = emb_func_en_b.mlc_en;
12272 emb_sens->fsm = emb_func_en_b.fsm_en;
12273 emb_sens->tilt = emb_func_en_a.tilt_en;
12274 emb_sens->step = emb_func_en_a.pedo_en;
12275 emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
12276 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
12277 }
12278
12279 if (ret == 0)
12280 {
12281 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12282 }
12283
12284 return ret;
12285 }
12286
12287 /**
12288 * @brief turn off all embedded functions.[get]
12289 *
12290 * @param ctx read / write interface definitions
12291 * @param val get the values of registers
12292 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12293 * @retval interface status (MANDATORY: return 0 -> no Error).
12294 *
12295 */
lsm6dso32x_embedded_sens_off(const stmdev_ctx_t * ctx)12296 int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx)
12297 {
12298 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12299 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12300 int32_t ret;
12301
12302 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12303
12304 if (ret == 0)
12305 {
12306 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12307 (uint8_t *)&emb_func_en_a, 1);
12308 }
12309
12310 if (ret == 0)
12311 {
12312 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12313 (uint8_t *)&emb_func_en_b, 1);
12314 emb_func_en_b.mlc_en = PROPERTY_DISABLE;
12315 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
12316 emb_func_en_a.tilt_en = PROPERTY_DISABLE;
12317 emb_func_en_a.pedo_en = PROPERTY_DISABLE;
12318 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
12319 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
12320 }
12321
12322 if (ret == 0)
12323 {
12324 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12325 (uint8_t *)&emb_func_en_a, 1);
12326 }
12327
12328 if (ret == 0)
12329 {
12330 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12331 (uint8_t *)&emb_func_en_b, 1);
12332 }
12333
12334 if (ret == 0)
12335 {
12336 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12337 }
12338
12339 return ret;
12340 }
12341
12342 /**
12343 * @}
12344 *
12345 */
12346
12347 /**
12348 * @}
12349 *
12350 */
12351
12352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
12353
