1 /**
2 ******************************************************************************
3 * @file lsm6dso32_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO32 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso32_reg.h"
21
22 /**
23 * @defgroup LSM6DSO32
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso32 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSO32_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dso32_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso32_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
lsm6dso32_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak lsm6dso32_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup LSM6DSO32_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
lsm6dso32_from_fs4_to_mg(int16_t lsb)96 float_t lsm6dso32_from_fs4_to_mg(int16_t lsb)
97 {
98 return ((float_t)lsb) * 0.122f;
99 }
100
lsm6dso32_from_fs8_to_mg(int16_t lsb)101 float_t lsm6dso32_from_fs8_to_mg(int16_t lsb)
102 {
103 return ((float_t)lsb) * 0.244f;
104 }
105
lsm6dso32_from_fs16_to_mg(int16_t lsb)106 float_t lsm6dso32_from_fs16_to_mg(int16_t lsb)
107 {
108 return ((float_t)lsb) * 0.488f;
109 }
110
lsm6dso32_from_fs32_to_mg(int16_t lsb)111 float_t lsm6dso32_from_fs32_to_mg(int16_t lsb)
112 {
113 return ((float_t)lsb) * 0.976f;
114 }
115
lsm6dso32_from_fs125_to_mdps(int16_t lsb)116 float_t lsm6dso32_from_fs125_to_mdps(int16_t lsb)
117 {
118 return ((float_t)lsb) * 4.375f;
119 }
120
lsm6dso32_from_fs250_to_mdps(int16_t lsb)121 float_t lsm6dso32_from_fs250_to_mdps(int16_t lsb)
122 {
123 return ((float_t)lsb) * 8.75f;
124 }
125
lsm6dso32_from_fs500_to_mdps(int16_t lsb)126 float_t lsm6dso32_from_fs500_to_mdps(int16_t lsb)
127 {
128 return ((float_t)lsb) * 17.50f;
129 }
130
lsm6dso32_from_fs1000_to_mdps(int16_t lsb)131 float_t lsm6dso32_from_fs1000_to_mdps(int16_t lsb)
132 {
133 return ((float_t)lsb) * 35.0f;
134 }
135
lsm6dso32_from_fs2000_to_mdps(int16_t lsb)136 float_t lsm6dso32_from_fs2000_to_mdps(int16_t lsb)
137 {
138 return ((float_t)lsb) * 70.0f;
139 }
140
lsm6dso32_from_lsb_to_celsius(int16_t lsb)141 float_t lsm6dso32_from_lsb_to_celsius(int16_t lsb)
142 {
143 return (((float_t)lsb / 256.0f) + 25.0f);
144 }
145
lsm6dso32_from_lsb_to_nsec(int16_t lsb)146 float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb)
147 {
148 return ((float_t)lsb * 25000.0f);
149 }
150
151 /**
152 * @}
153 *
154 */
155
156 /**
157 * @defgroup LSM6DSO32_Data_Generation
158 * @brief This section groups all the functions concerning
159 * data generation.
160 *
161 */
162
163 /**
164 * @brief Accelerometer full-scale selection.[set]
165 *
166 * @param ctx read / write interface definitions
167 * @param val change the values of fs_xl in reg CTRL1_XL
168 * @retval interface status (MANDATORY: return 0 -> no Error)
169 *
170 */
lsm6dso32_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso32_fs_xl_t val)171 int32_t lsm6dso32_xl_full_scale_set(const stmdev_ctx_t *ctx,
172 lsm6dso32_fs_xl_t val)
173 {
174 lsm6dso32_ctrl1_xl_t ctrl1_xl;
175 int32_t ret;
176
177 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
178 (uint8_t *)&ctrl1_xl, 1);
179
180 if (ret == 0)
181 {
182 ctrl1_xl.fs_xl = (uint8_t) val & 0x03U;
183 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
184 (uint8_t *)&ctrl1_xl, 1);
185 }
186
187 return ret;
188 }
189
190 /**
191 * @brief Accelerometer full-scale selection.[get]
192 *
193 * @param ctx read / write interface definitions
194 * @param val Get the values of fs_xl in reg CTRL1_XL
195 * @retval interface status (MANDATORY: return 0 -> no Error)
196 *
197 */
lsm6dso32_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso32_fs_xl_t * val)198 int32_t lsm6dso32_xl_full_scale_get(const stmdev_ctx_t *ctx,
199 lsm6dso32_fs_xl_t *val)
200 {
201 lsm6dso32_ctrl1_xl_t reg;
202 int32_t ret;
203
204 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
205
206 switch (reg.fs_xl)
207 {
208 case LSM6DSO32_4g:
209 *val = LSM6DSO32_4g;
210 break;
211
212 case LSM6DSO32_8g:
213 *val = LSM6DSO32_8g;
214 break;
215
216 case LSM6DSO32_16g:
217 *val = LSM6DSO32_16g;
218 break;
219
220 case LSM6DSO32_32g:
221 *val = LSM6DSO32_32g;
222 break;
223
224 default:
225 *val = LSM6DSO32_4g;
226 break;
227 }
228
229 return ret;
230 }
231
232 /**
233 * @brief Accelerometer UI data rate and power mode selection.[set]
234 *
235 * @param ctx read / write interface definitions
236 * @param val Change the data rate and the power mode of
237 * the accelerometer
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
lsm6dso32_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32_odr_xl_t val)241 int32_t lsm6dso32_xl_data_rate_set(const stmdev_ctx_t *ctx,
242 lsm6dso32_odr_xl_t val)
243 {
244 lsm6dso32_ctrl1_xl_t ctrl1_xl;
245 lsm6dso32_ctrl5_c_t ctrl5_c;
246 lsm6dso32_ctrl6_c_t ctrl6_c;
247 lsm6dso32_func_cfg_access_t func_cfg_access;
248 int32_t ret;
249
250 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
251 (uint8_t *)&ctrl1_xl, 1);
252
253 if (ret == 0)
254 {
255 ctrl1_xl.odr_xl = (uint8_t) LSM6DSO32_XL_ODR_OFF & 0x0FU;
256 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
257 (uint8_t *)&ctrl1_xl, 1);
258 }
259
260 if (ret == 0)
261 {
262 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
263 (uint8_t *)&func_cfg_access, 1);
264 }
265
266 if (ret == 0)
267 {
268 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
269 }
270
271 if (ret == 0)
272 {
273 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x20U) >> 5;
274 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C,
275 (uint8_t *) &ctrl5_c, 1);
276 }
277
278 if (ret == 0)
279 {
280 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
281 }
282
283 if (ret == 0)
284 {
285 ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x10U) >> 4;
286 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C,
287 (uint8_t *) &ctrl6_c, 1);
288 }
289
290 if (ret == 0)
291 {
292 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
293 (uint8_t *)&ctrl1_xl, 1);
294 }
295
296 if (ret == 0)
297 {
298 ctrl1_xl.odr_xl = (uint8_t) val & 0x0FU;
299 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
300 (uint8_t *)&ctrl1_xl, 1);
301 }
302
303 return ret;
304 }
305
306 /**
307 * @brief Accelerometer UI data rate selection.[get]
308 *
309 * @param ctx read / write interface definitions
310 * @param val Get the data rate and the power mode of
311 * the accelerometer
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
lsm6dso32_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32_odr_xl_t * val)315 int32_t lsm6dso32_xl_data_rate_get(const stmdev_ctx_t *ctx,
316 lsm6dso32_odr_xl_t *val)
317 {
318 lsm6dso32_ctrl1_xl_t ctrl1_xl;
319 lsm6dso32_ctrl5_c_t ctrl5_c;
320 lsm6dso32_ctrl6_c_t ctrl6_c;
321 lsm6dso32_func_cfg_access_t func_cfg_access;
322 int32_t ret;
323
324 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
325 (uint8_t *)&ctrl1_xl, 1);
326
327 if (ret == 0)
328 {
329 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
330 (uint8_t *)&func_cfg_access, 1);
331 }
332
333 if (ret == 0)
334 {
335 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
336 }
337
338 if (ret == 0)
339 {
340 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
341 }
342
343 switch ((ctrl5_c.xl_ulp_en << 5) + (ctrl6_c.xl_hm_mode << 4) +
344 ctrl1_xl.odr_xl)
345 {
346 case LSM6DSO32_XL_ODR_OFF:
347 *val = LSM6DSO32_XL_ODR_OFF;
348 break;
349
350 case LSM6DSO32_XL_ODR_1Hz6_LOW_PW:
351 *val = LSM6DSO32_XL_ODR_1Hz6_LOW_PW;
352 break;
353
354 case LSM6DSO32_XL_ODR_12Hz5_LOW_PW:
355 *val = LSM6DSO32_XL_ODR_12Hz5_LOW_PW;
356 break;
357
358 case LSM6DSO32_XL_ODR_26Hz_LOW_PW:
359 *val = LSM6DSO32_XL_ODR_26Hz_LOW_PW;
360 break;
361
362 case LSM6DSO32_XL_ODR_52Hz_LOW_PW:
363 *val = LSM6DSO32_XL_ODR_52Hz_LOW_PW;
364 break;
365
366 case LSM6DSO32_XL_ODR_104Hz_NORMAL_MD:
367 *val = LSM6DSO32_XL_ODR_104Hz_NORMAL_MD;
368 break;
369
370 case LSM6DSO32_XL_ODR_208Hz_NORMAL_MD:
371 *val = LSM6DSO32_XL_ODR_208Hz_NORMAL_MD;
372 break;
373
374 case LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF:
375 *val = LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF;
376 break;
377
378 case LSM6DSO32_XL_ODR_26Hz_HIGH_PERF:
379 *val = LSM6DSO32_XL_ODR_26Hz_HIGH_PERF;
380 break;
381
382 case LSM6DSO32_XL_ODR_52Hz_HIGH_PERF:
383 *val = LSM6DSO32_XL_ODR_52Hz_HIGH_PERF;
384 break;
385
386 case LSM6DSO32_XL_ODR_104Hz_HIGH_PERF:
387 *val = LSM6DSO32_XL_ODR_104Hz_HIGH_PERF;
388 break;
389
390 case LSM6DSO32_XL_ODR_208Hz_HIGH_PERF:
391 *val = LSM6DSO32_XL_ODR_208Hz_HIGH_PERF;
392 break;
393
394 case LSM6DSO32_XL_ODR_417Hz_HIGH_PERF:
395 *val = LSM6DSO32_XL_ODR_417Hz_HIGH_PERF;
396 break;
397
398 case LSM6DSO32_XL_ODR_833Hz_HIGH_PERF:
399 *val = LSM6DSO32_XL_ODR_833Hz_HIGH_PERF;
400 break;
401
402 case LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF:
403 *val = LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF;
404 break;
405
406 case LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF:
407 *val = LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF;
408 break;
409
410 case LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF:
411 *val = LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF;
412 break;
413
414 case LSM6DSO32_XL_ODR_1Hz6_ULTRA_LOW_PW:
415 *val = LSM6DSO32_XL_ODR_1Hz6_ULTRA_LOW_PW;
416 break;
417
418 case LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW:
419 *val = LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW;
420 break;
421
422 case LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW:
423 *val = LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW;
424 break;
425
426 case LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW:
427 *val = LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW;
428 break;
429
430 case LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW:
431 *val = LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW;
432 break;
433
434 case LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW:
435 *val = LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW;
436 break;
437
438 default:
439 *val = LSM6DSO32_XL_ODR_OFF;
440 break;
441 }
442
443 return ret;
444 }
445
446 /**
447 * @brief Gyroscope UI chain full-scale selection.[set]
448 *
449 * @param ctx read / write interface definitions
450 * @param val change the values of fs_g in reg CTRL2_G
451 * @retval interface status (MANDATORY: return 0 -> no Error)
452 *
453 */
lsm6dso32_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso32_fs_g_t val)454 int32_t lsm6dso32_gy_full_scale_set(const stmdev_ctx_t *ctx,
455 lsm6dso32_fs_g_t val)
456 {
457 lsm6dso32_ctrl2_g_t reg;
458 int32_t ret;
459
460 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
461
462 if (ret == 0)
463 {
464 reg.fs_g = (uint8_t) val;
465 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
466 }
467
468 return ret;
469 }
470
471 /**
472 * @brief Gyroscope UI chain full-scale selection.[get]
473 *
474 * @param ctx read / write interface definitions
475 * @param val Get the values of fs_g in reg CTRL2_G
476 * @retval interface status (MANDATORY: return 0 -> no Error)
477 *
478 */
lsm6dso32_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso32_fs_g_t * val)479 int32_t lsm6dso32_gy_full_scale_get(const stmdev_ctx_t *ctx,
480 lsm6dso32_fs_g_t *val)
481 {
482 lsm6dso32_ctrl2_g_t reg;
483 int32_t ret;
484
485 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
486
487 switch (reg.fs_g)
488 {
489 case LSM6DSO32_250dps:
490 *val = LSM6DSO32_250dps;
491 break;
492
493 case LSM6DSO32_125dps:
494 *val = LSM6DSO32_125dps;
495 break;
496
497 case LSM6DSO32_500dps:
498 *val = LSM6DSO32_500dps;
499 break;
500
501 case LSM6DSO32_1000dps:
502 *val = LSM6DSO32_1000dps;
503 break;
504
505 case LSM6DSO32_2000dps:
506 *val = LSM6DSO32_2000dps;
507 break;
508
509 default:
510 *val = LSM6DSO32_250dps;
511 break;
512 }
513
514 return ret;
515 }
516
517 /**
518 * @brief Gyroscope UI data rate selection.[set]
519 *
520 * @param ctx read / write interface definitions
521 * @param val change the values of odr_g in reg CTRL2_G
522 * @retval interface status (MANDATORY: return 0 -> no Error)
523 *
524 */
lsm6dso32_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32_odr_g_t val)525 int32_t lsm6dso32_gy_data_rate_set(const stmdev_ctx_t *ctx,
526 lsm6dso32_odr_g_t val)
527 {
528 lsm6dso32_ctrl2_g_t ctrl2_g;
529 lsm6dso32_ctrl7_g_t ctrl7_g;
530 int32_t ret;
531
532 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
533
534 if (ret == 0)
535 {
536 ctrl2_g.odr_g = (uint8_t) LSM6DSO32_GY_ODR_OFF & 0x0FU;
537 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
538 }
539
540 if (ret == 0)
541 {
542 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
543 }
544
545 if (ret == 0)
546 {
547 ctrl7_g.g_hm_mode = ((uint8_t)val & 0x10U) >> 4;
548 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
549 }
550
551 if (ret == 0)
552 {
553 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
554 }
555
556 if (ret == 0)
557 {
558 ctrl2_g.odr_g = (uint8_t)val & 0x0FU;
559 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
560 }
561
562 return ret;
563 }
564
565 /**
566 * @brief Gyroscope UI data rate selection.[get]
567 *
568 * @param ctx read / write interface definitions
569 * @param val Get the values of odr_g in reg CTRL2_G
570 * @retval interface status (MANDATORY: return 0 -> no Error)
571 *
572 */
lsm6dso32_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32_odr_g_t * val)573 int32_t lsm6dso32_gy_data_rate_get(const stmdev_ctx_t *ctx,
574 lsm6dso32_odr_g_t *val)
575 {
576 lsm6dso32_ctrl2_g_t ctrl2_g;
577 lsm6dso32_ctrl7_g_t ctrl7_g;
578 int32_t ret;
579
580 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
581
582 if (ret == 0)
583 {
584 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
585 }
586
587 switch ((ctrl7_g.g_hm_mode << 4) + ctrl2_g.odr_g)
588 {
589 case LSM6DSO32_GY_ODR_OFF:
590 *val = LSM6DSO32_GY_ODR_OFF;
591 break;
592
593 case LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF:
594 *val = LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF;
595 break;
596
597 case LSM6DSO32_GY_ODR_26Hz_HIGH_PERF:
598 *val = LSM6DSO32_GY_ODR_26Hz_HIGH_PERF;
599 break;
600
601 case LSM6DSO32_GY_ODR_52Hz_HIGH_PERF:
602 *val = LSM6DSO32_GY_ODR_52Hz_HIGH_PERF;
603 break;
604
605 case LSM6DSO32_GY_ODR_104Hz_HIGH_PERF:
606 *val = LSM6DSO32_GY_ODR_104Hz_HIGH_PERF;
607 break;
608
609 case LSM6DSO32_GY_ODR_208Hz_HIGH_PERF:
610 *val = LSM6DSO32_GY_ODR_208Hz_HIGH_PERF;
611 break;
612
613 case LSM6DSO32_GY_ODR_417Hz_HIGH_PERF:
614 *val = LSM6DSO32_GY_ODR_417Hz_HIGH_PERF;
615 break;
616
617 case LSM6DSO32_GY_ODR_833Hz_HIGH_PERF:
618 *val = LSM6DSO32_GY_ODR_833Hz_HIGH_PERF;
619 break;
620
621 case LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF:
622 *val = LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF;
623 break;
624
625 case LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF:
626 *val = LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF;
627 break;
628
629 case LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF:
630 *val = LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF;
631 break;
632
633 case LSM6DSO32_GY_ODR_104Hz_NORMAL_MD:
634 *val = LSM6DSO32_GY_ODR_104Hz_NORMAL_MD;
635 break;
636
637 case LSM6DSO32_GY_ODR_208Hz_NORMAL_MD:
638 *val = LSM6DSO32_GY_ODR_208Hz_NORMAL_MD;
639 break;
640
641 case LSM6DSO32_GY_ODR_12Hz5_LOW_PW:
642 *val = LSM6DSO32_GY_ODR_12Hz5_LOW_PW;
643 break;
644
645 case LSM6DSO32_GY_ODR_26Hz_LOW_PW:
646 *val = LSM6DSO32_GY_ODR_26Hz_LOW_PW;
647 break;
648
649 case LSM6DSO32_GY_ODR_52Hz_LOW_PW:
650 *val = LSM6DSO32_GY_ODR_52Hz_LOW_PW;
651 break;
652
653 default:
654 *val = LSM6DSO32_GY_ODR_OFF;
655 break;
656 }
657
658 return ret;
659 }
660
661 /**
662 * @brief Block data update.[set]
663 *
664 * @param ctx read / write interface definitions
665 * @param val change the values of bdu in reg CTRL3_C
666 * @retval interface status (MANDATORY: return 0 -> no Error)
667 *
668 */
lsm6dso32_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)669 int32_t lsm6dso32_block_data_update_set(const stmdev_ctx_t *ctx,
670 uint8_t val)
671 {
672 lsm6dso32_ctrl3_c_t reg;
673 int32_t ret;
674
675 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
676
677 if (ret == 0)
678 {
679 reg.bdu = val;
680 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
681 }
682
683 return ret;
684 }
685
686 /**
687 * @brief Block data update.[get]
688 *
689 * @param ctx read / write interface definitions
690 * @param val change the values of bdu in reg CTRL3_C
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
lsm6dso32_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)694 int32_t lsm6dso32_block_data_update_get(const stmdev_ctx_t *ctx,
695 uint8_t *val)
696 {
697 lsm6dso32_ctrl3_c_t reg;
698 int32_t ret;
699
700 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
701 *val = reg.bdu;
702
703 return ret;
704 }
705
706 /**
707 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
708 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
709 *
710 * @param ctx read / write interface definitions
711 * @param val change the values of usr_off_w in reg CTRL6_C
712 * @retval interface status (MANDATORY: return 0 -> no Error)
713 *
714 */
lsm6dso32_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dso32_usr_off_w_t val)715 int32_t lsm6dso32_xl_offset_weight_set(const stmdev_ctx_t *ctx,
716 lsm6dso32_usr_off_w_t val)
717 {
718 lsm6dso32_ctrl6_c_t reg;
719 int32_t ret;
720
721 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
722
723 if (ret == 0)
724 {
725 reg.usr_off_w = (uint8_t)val;
726 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
727 }
728
729 return ret;
730 }
731
732 /**
733 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
734 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
735 *
736 * @param ctx read / write interface definitions
737 * @param val Get the values of usr_off_w in reg CTRL6_C
738 * @retval interface status (MANDATORY: return 0 -> no Error)
739 *
740 */
lsm6dso32_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dso32_usr_off_w_t * val)741 int32_t lsm6dso32_xl_offset_weight_get(const stmdev_ctx_t *ctx,
742 lsm6dso32_usr_off_w_t *val)
743 {
744 lsm6dso32_ctrl6_c_t reg;
745 int32_t ret;
746
747 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
748
749 switch (reg.usr_off_w)
750 {
751 case LSM6DSO32_LSb_1mg:
752 *val = LSM6DSO32_LSb_1mg;
753 break;
754
755 case LSM6DSO32_LSb_16mg:
756 *val = LSM6DSO32_LSb_16mg;
757 break;
758
759 default:
760 *val = LSM6DSO32_LSb_1mg;
761 break;
762 }
763
764 return ret;
765 }
766
767 /**
768 * @brief Read all the interrupt flag of the device.[get]
769 *
770 * @param ctx read / write interface definitions
771 * @param val registers ALL_INT_SRC; WAKE_UP_SRC;
772 * TAP_SRC; D6D_SRC; STATUS_REG;
773 * EMB_FUNC_STATUS; FSM_STATUS_A/B
774 * @retval interface status (MANDATORY: return 0 -> no Error)
775 *
776 */
lsm6dso32_all_sources_get(const stmdev_ctx_t * ctx,lsm6dso32_all_sources_t * val)777 int32_t lsm6dso32_all_sources_get(const stmdev_ctx_t *ctx,
778 lsm6dso32_all_sources_t *val)
779 {
780 int32_t ret;
781
782 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_ALL_INT_SRC,
783 (uint8_t *)&val->all_int_src, 1);
784
785 if (ret == 0)
786 {
787 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_SRC,
788 (uint8_t *)&val->wake_up_src, 1);
789 }
790
791 if (ret == 0)
792 {
793 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_SRC,
794 (uint8_t *)&val->tap_src, 1);
795 }
796
797 if (ret == 0)
798 {
799 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_D6D_SRC,
800 (uint8_t *)&val->d6d_src, 1);
801 }
802
803 if (ret == 0)
804 {
805 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG,
806 (uint8_t *)&val->status_reg, 1);
807 }
808
809 if (ret == 0)
810 {
811 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
812 }
813
814 if (ret == 0)
815 {
816 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
817 (uint8_t *)&val->emb_func_status, 1);
818 }
819
820 if (ret == 0)
821 {
822 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_A,
823 (uint8_t *)&val->fsm_status_a, 1);
824 }
825
826 if (ret == 0)
827 {
828 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_B,
829 (uint8_t *)&val->fsm_status_b, 1);
830 }
831
832 if (ret == 0)
833 {
834 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
835 }
836
837 return ret;
838 }
839
840 /**
841 * @brief The STATUS_REG register is read by the primary interface.[get]
842 *
843 * @param ctx read / write interface definitions
844 * @param val register STATUS_REG
845 * @retval interface status (MANDATORY: return 0 -> no Error)
846 *
847 */
lsm6dso32_status_reg_get(const stmdev_ctx_t * ctx,lsm6dso32_status_reg_t * val)848 int32_t lsm6dso32_status_reg_get(const stmdev_ctx_t *ctx,
849 lsm6dso32_status_reg_t *val)
850 {
851 int32_t ret;
852
853 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *) val, 1);
854
855 return ret;
856 }
857
858 /**
859 * @brief Accelerometer new data available.[get]
860 *
861 * @param ctx read / write interface definitions
862 * @param val change the values of xlda in reg STATUS_REG
863 * @retval interface status (MANDATORY: return 0 -> no Error)
864 *
865 */
lsm6dso32_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)866 int32_t lsm6dso32_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
867 uint8_t *val)
868 {
869 lsm6dso32_status_reg_t reg;
870 int32_t ret;
871
872 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
873 *val = reg.xlda;
874
875 return ret;
876 }
877
878 /**
879 * @brief Gyroscope new data available.[get]
880 *
881 * @param ctx read / write interface definitions
882 * @param val change the values of gda in reg STATUS_REG
883 * @retval interface status (MANDATORY: return 0 -> no Error)
884 *
885 */
lsm6dso32_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)886 int32_t lsm6dso32_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
887 uint8_t *val)
888 {
889 lsm6dso32_status_reg_t reg;
890 int32_t ret;
891
892 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
893 *val = reg.gda;
894
895 return ret;
896 }
897
898 /**
899 * @brief Temperature new data available.[get]
900 *
901 * @param ctx read / write interface definitions
902 * @param val change the values of tda in reg STATUS_REG
903 * @retval interface status (MANDATORY: return 0 -> no Error)
904 *
905 */
lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)906 int32_t lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
907 uint8_t *val)
908 {
909 lsm6dso32_status_reg_t reg;
910 int32_t ret;
911
912 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
913 *val = reg.tda;
914
915 return ret;
916 }
917
918 /**
919 * @brief Accelerometer X-axis user offset correction expressed in
920 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
921 * The value must be in the range [-127 127].[set]
922 *
923 * @param ctx read / write interface definitions
924 * @param buff buffer that contains data to write
925 * @retval interface status (MANDATORY: return 0 -> no Error)
926 *
927 */
lsm6dso32_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)928 int32_t lsm6dso32_xl_usr_offset_x_set(const stmdev_ctx_t *ctx,
929 uint8_t *buff)
930 {
931 int32_t ret;
932
933 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
934
935 return ret;
936 }
937
938 /**
939 * @brief Accelerometer X-axis user offset correction expressed in two’s
940 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
941 * The value must be in the range [-127 127].[get]
942 *
943 * @param ctx read / write interface definitions
944 * @param buff buffer that stores data read
945 * @retval interface status (MANDATORY: return 0 -> no Error)
946 *
947 */
lsm6dso32_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)948 int32_t lsm6dso32_xl_usr_offset_x_get(const stmdev_ctx_t *ctx,
949 uint8_t *buff)
950 {
951 int32_t ret;
952
953 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
954
955 return ret;
956 }
957
958 /**
959 * @brief Accelerometer Y-axis user offset correction expressed in two’s
960 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
961 * The value must be in the range [-127 127].[set]
962 *
963 * @param ctx read / write interface definitions
964 * @param buff buffer that contains data to write
965 * @retval interface status (MANDATORY: return 0 -> no Error)
966 *
967 */
lsm6dso32_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)968 int32_t lsm6dso32_xl_usr_offset_y_set(const stmdev_ctx_t *ctx,
969 uint8_t *buff)
970 {
971 int32_t ret;
972
973 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
974
975 return ret;
976 }
977
978 /**
979 * @brief Accelerometer Y-axis user offset correction expressed in two’s
980 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
981 * The value must be in the range [-127 127].[get]
982 *
983 * @param ctx read / write interface definitions
984 * @param buff buffer that stores data read
985 * @retval interface status (MANDATORY: return 0 -> no Error)
986 *
987 */
lsm6dso32_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)988 int32_t lsm6dso32_xl_usr_offset_y_get(const stmdev_ctx_t *ctx,
989 uint8_t *buff)
990 {
991 int32_t ret;
992
993 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
994
995 return ret;
996 }
997
998 /**
999 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1000 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1001 * The value must be in the range [-127 127].[set]
1002 *
1003 * @param ctx read / write interface definitions
1004 * @param buff buffer that contains data to write
1005 * @retval interface status (MANDATORY: return 0 -> no Error)
1006 *
1007 */
lsm6dso32_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1008 int32_t lsm6dso32_xl_usr_offset_z_set(const stmdev_ctx_t *ctx,
1009 uint8_t *buff)
1010 {
1011 int32_t ret;
1012
1013 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
1014
1015 return ret;
1016 }
1017
1018 /**
1019 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1020 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1021 * The value must be in the range [-127 127].[get]
1022 *
1023 * @param ctx read / write interface definitions
1024 * @param buff buffer that stores data read
1025 * @retval interface status (MANDATORY: return 0 -> no Error)
1026 *
1027 */
lsm6dso32_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1028 int32_t lsm6dso32_xl_usr_offset_z_get(const stmdev_ctx_t *ctx,
1029 uint8_t *buff)
1030 {
1031 int32_t ret;
1032
1033 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
1034
1035 return ret;
1036 }
1037
1038 /**
1039 * @brief Enables user offset on out.[set]
1040 *
1041 * @param ctx read / write interface definitions
1042 * @param val change the values of usr_off_on_out in reg CTRL7_G
1043 * @retval interface status (MANDATORY: return 0 -> no Error)
1044 *
1045 */
lsm6dso32_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1046 int32_t lsm6dso32_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1047 {
1048 lsm6dso32_ctrl7_g_t reg;
1049 int32_t ret;
1050
1051 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1052
1053 if (ret == 0)
1054 {
1055 reg.usr_off_on_out = val;
1056 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1057 }
1058
1059 return ret;
1060 }
1061
1062 /**
1063 * @brief User offset on out flag.[get]
1064 *
1065 * @param ctx read / write interface definitions
1066 * @param val values of usr_off_on_out in reg CTRL7_G
1067 * @retval interface status (MANDATORY: return 0 -> no Error)
1068 *
1069 */
lsm6dso32_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1070 int32_t lsm6dso32_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1071 {
1072 lsm6dso32_ctrl7_g_t reg;
1073 int32_t ret;
1074
1075 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1076 *val = reg.usr_off_on_out;
1077
1078 return ret;
1079 }
1080
1081 /**
1082 * @}
1083 *
1084 */
1085
1086 /**
1087 * @defgroup LSM6DSO32_Timestamp
1088 * @brief This section groups all the functions that manage the
1089 * timestamp generation.
1090 * @{
1091 *
1092 */
1093
1094 /**
1095 * @brief Enables timestamp counter.[set]
1096 *
1097 * @param ctx read / write interface definitions
1098 * @param val change the values of timestamp_en in reg CTRL10_C
1099 * @retval interface status (MANDATORY: return 0 -> no Error)
1100 *
1101 */
lsm6dso32_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1102 int32_t lsm6dso32_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1103 {
1104 lsm6dso32_ctrl10_c_t reg;
1105 int32_t ret;
1106
1107 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1108
1109 if (ret == 0)
1110 {
1111 reg.timestamp_en = val;
1112 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1113 }
1114
1115 return ret;
1116 }
1117
1118 /**
1119 * @brief Enables timestamp counter.[get]
1120 *
1121 * @param ctx read / write interface definitions
1122 * @param val change the values of timestamp_en in reg CTRL10_C
1123 * @retval interface status (MANDATORY: return 0 -> no Error)
1124 *
1125 */
lsm6dso32_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1126 int32_t lsm6dso32_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1127 {
1128 lsm6dso32_ctrl10_c_t reg;
1129 int32_t ret;
1130
1131 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1132 *val = reg.timestamp_en;
1133
1134 return ret;
1135 }
1136
1137 /**
1138 * @brief Timestamp first data output register (r).
1139 * The value is expressed as a 32-bit word and the bit
1140 * resolution is 25 μs.[get]
1141 *
1142 * @param ctx read / write interface definitions
1143 * @param buff buffer that stores data read
1144 * @retval interface status (MANDATORY: return 0 -> no Error)
1145 *
1146 */
lsm6dso32_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1147 int32_t lsm6dso32_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1148 {
1149 uint8_t buff[4];
1150 int32_t ret;
1151
1152 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TIMESTAMP0, buff, 4);
1153 *val = buff[3];
1154 *val = (*val * 256U) + buff[2];
1155 *val = (*val * 256U) + buff[1];
1156 *val = (*val * 256U) + buff[0];
1157
1158 return ret;
1159 }
1160
1161 /**
1162 * @}
1163 *
1164 */
1165
1166 /**
1167 * @defgroup LSM6DSO32_Data output
1168 * @brief This section groups all the data output functions.
1169 * @{
1170 *
1171 */
1172
1173 /**
1174 * @brief Circular burst-mode (rounding) read of the output
1175 * registers.[set]
1176 *
1177 * @param ctx read / write interface definitions
1178 * @param val change the values of rounding in reg CTRL5_C
1179 * @retval interface status (MANDATORY: return 0 -> no Error)
1180 *
1181 */
lsm6dso32_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_rounding_t val)1182 int32_t lsm6dso32_rounding_mode_set(const stmdev_ctx_t *ctx,
1183 lsm6dso32_rounding_t val)
1184 {
1185 lsm6dso32_ctrl5_c_t reg;
1186 int32_t ret;
1187
1188 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1189
1190 if (ret == 0)
1191 {
1192 reg.rounding = (uint8_t)val;
1193 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1194 }
1195
1196 return ret;
1197 }
1198
1199 /**
1200 * @brief Gyroscope UI chain full-scale selection.[get]
1201 *
1202 * @param ctx read / write interface definitions
1203 * @param val Get the values of rounding in reg CTRL5_C
1204 * @retval interface status (MANDATORY: return 0 -> no Error)
1205 *
1206 */
lsm6dso32_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_rounding_t * val)1207 int32_t lsm6dso32_rounding_mode_get(const stmdev_ctx_t *ctx,
1208 lsm6dso32_rounding_t *val)
1209 {
1210 lsm6dso32_ctrl5_c_t reg;
1211 int32_t ret;
1212
1213 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1214
1215 switch (reg.rounding)
1216 {
1217 case LSM6DSO32_NO_ROUND:
1218 *val = LSM6DSO32_NO_ROUND;
1219 break;
1220
1221 case LSM6DSO32_ROUND_XL:
1222 *val = LSM6DSO32_ROUND_XL;
1223 break;
1224
1225 case LSM6DSO32_ROUND_GY:
1226 *val = LSM6DSO32_ROUND_GY;
1227 break;
1228
1229 case LSM6DSO32_ROUND_GY_XL:
1230 *val = LSM6DSO32_ROUND_GY_XL;
1231 break;
1232
1233 default:
1234 *val = LSM6DSO32_NO_ROUND;
1235 break;
1236 }
1237
1238 return ret;
1239 }
1240
1241 /**
1242 * @brief Temperature data output register (r).
1243 * L and H registers together express a 16-bit word in two’s
1244 * complement.[get]
1245 *
1246 * @param ctx read / write interface definitions
1247 * @param buff buffer that stores data read
1248 * @retval interface status (MANDATORY: return 0 -> no Error)
1249 *
1250 */
lsm6dso32_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1251 int32_t lsm6dso32_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1252 {
1253 uint8_t buff[2];
1254 int32_t ret;
1255
1256 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUT_TEMP_L, buff, 2);
1257 val[0] = (int16_t)buff[1];
1258 val[0] = (val[0] * 256) + (int16_t)buff[0];
1259
1260 return ret;
1261 }
1262
1263 /**
1264 * @brief Angular rate sensor. The value is expressed as a 16-bit
1265 * word in two’s complement.[get]
1266 *
1267 * @param ctx read / write interface definitions
1268 * @param buff buffer that stores data read
1269 * @retval interface status (MANDATORY: return 0 -> no Error)
1270 *
1271 */
lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1272 int32_t lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1273 int16_t *val)
1274 {
1275 uint8_t buff[6];
1276 int32_t ret;
1277
1278 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_G, buff, 6);
1279 val[0] = (int16_t)buff[1];
1280 val[0] = (val[0] * 256) + (int16_t)buff[0];
1281 val[1] = (int16_t)buff[3];
1282 val[1] = (val[1] * 256) + (int16_t)buff[2];
1283 val[2] = (int16_t)buff[5];
1284 val[2] = (val[2] * 256) + (int16_t)buff[4];
1285
1286 return ret;
1287 }
1288
1289 /**
1290 * @brief Linear acceleration output register.
1291 * The value is expressed as a 16-bit word in two’s complement.[get]
1292 *
1293 * @param ctx read / write interface definitions
1294 * @param buff buffer that stores data read
1295 * @retval interface status (MANDATORY: return 0 -> no Error)
1296 *
1297 */
lsm6dso32_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1298 int32_t lsm6dso32_acceleration_raw_get(const stmdev_ctx_t *ctx,
1299 int16_t *val)
1300 {
1301 uint8_t buff[6];
1302 int32_t ret;
1303
1304 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_A, buff, 6);
1305 val[0] = (int16_t)buff[1];
1306 val[0] = (val[0] * 256) + (int16_t)buff[0];
1307 val[1] = (int16_t)buff[3];
1308 val[1] = (val[1] * 256) + (int16_t)buff[2];
1309 val[2] = (int16_t)buff[5];
1310 val[2] = (val[2] * 256) + (int16_t)buff[4];
1311
1312 return ret;
1313 }
1314
1315 /**
1316 * @brief FIFO data output [get]
1317 *
1318 * @param ctx read / write interface definitions
1319 * @param buff buffer that stores data read
1320 * @retval interface status (MANDATORY: return 0 -> no Error)
1321 *
1322 */
lsm6dso32_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1323 int32_t lsm6dso32_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1324 {
1325 int32_t ret;
1326
1327 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_X_L, buff, 6);
1328
1329 return ret;
1330 }
1331
1332 /**
1333 * @brief Step counter output register.[get]
1334 *
1335 * @param ctx read / write interface definitions
1336 * @param buff buffer that stores data read
1337 * @retval interface status (MANDATORY: return 0 -> no Error)
1338 *
1339 */
lsm6dso32_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1340 int32_t lsm6dso32_number_of_steps_get(const stmdev_ctx_t *ctx,
1341 uint16_t *val)
1342 {
1343 uint8_t buff[2];
1344 int32_t ret;
1345
1346 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1347
1348 if (ret == 0)
1349 {
1350 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STEP_COUNTER_L, buff, 2);
1351 }
1352
1353 if (ret == 0)
1354 {
1355 *val = buff[1];
1356 *val = (*val * 256U) + buff[0];
1357 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1358 }
1359
1360 return ret;
1361 }
1362
1363 /**
1364 * @brief Reset step counter register.[get]
1365 *
1366 * @param ctx read / write interface definitions
1367 * @retval interface status (MANDATORY: return 0 -> no Error)
1368 *
1369 */
lsm6dso32_steps_reset(const stmdev_ctx_t * ctx)1370 int32_t lsm6dso32_steps_reset(const stmdev_ctx_t *ctx)
1371 {
1372 lsm6dso32_emb_func_src_t reg;
1373 int32_t ret;
1374
1375 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1376
1377 if (ret == 0)
1378 {
1379 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_SRC, (uint8_t *)®, 1);
1380 }
1381
1382 if (ret == 0)
1383 {
1384 reg.pedo_rst_step = PROPERTY_ENABLE;
1385 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_SRC,
1386 (uint8_t *)®, 1);
1387 }
1388
1389 if (ret == 0)
1390 {
1391 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1392 }
1393
1394 return ret;
1395 }
1396
1397 /**
1398 * @}
1399 *
1400 */
1401
1402 /**
1403 * @defgroup LSM6DSO32_common
1404 * @brief This section groups common useful functions.
1405 * @{
1406 *
1407 */
1408
1409 /**
1410 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1411 * with respect to the typical.
1412 * Step: 0.15%. 8-bit format, 2's complement.[set]
1413 *
1414 * @param ctx read / write interface definitions
1415 * @param val change the values of freq_fine in reg
1416 * INTERNAL_FREQ_FINE
1417 * @retval interface status (MANDATORY: return 0 -> no Error)
1418 *
1419 */
lsm6dso32_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1420 int32_t lsm6dso32_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1421 {
1422 lsm6dso32_internal_freq_fine_t reg;
1423 int32_t ret;
1424
1425 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1426 (uint8_t *)®, 1);
1427
1428 if (ret == 0)
1429 {
1430 reg.freq_fine = val;
1431 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1432 (uint8_t *)®, 1);
1433 }
1434
1435 return ret;
1436 }
1437
1438 /**
1439 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1440 * with respect to the typical.
1441 * Step: 0.15%. 8-bit format, 2's complement.[get]
1442 *
1443 * @param ctx read / write interface definitions
1444 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
1445 * @retval interface status (MANDATORY: return 0 -> no Error)
1446 *
1447 */
lsm6dso32_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1448 int32_t lsm6dso32_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1449 {
1450 lsm6dso32_internal_freq_fine_t reg;
1451 int32_t ret;
1452
1453 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1454 (uint8_t *)®, 1);
1455 *val = reg.freq_fine;
1456
1457 return ret;
1458 }
1459
1460
1461 /**
1462 * @brief Enable access to the embedded functions/sensor
1463 * hub configuration registers.[set]
1464 *
1465 * @param ctx read / write interface definitions
1466 * @param val change the values of reg_access in reg FUNC_CFG_ACCESS
1467 * @retval interface status (MANDATORY: return 0 -> no Error)
1468 *
1469 */
lsm6dso32_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dso32_reg_access_t val)1470 int32_t lsm6dso32_mem_bank_set(const stmdev_ctx_t *ctx,
1471 lsm6dso32_reg_access_t val)
1472 {
1473 lsm6dso32_func_cfg_access_t reg;
1474 int32_t ret;
1475
1476 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1477 (uint8_t *)®, 1);
1478
1479 if (ret == 0)
1480 {
1481 reg.reg_access = (uint8_t)val;
1482 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1483 (uint8_t *)®, 1);
1484 }
1485
1486 return ret;
1487 }
1488
1489 /**
1490 * @brief Enable access to the embedded functions/sensor
1491 * hub configuration registers.[get]
1492 *
1493 * @param ctx read / write interface definitions
1494 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1495 * @retval interface status (MANDATORY: return 0 -> no Error)
1496 *
1497 */
lsm6dso32_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dso32_reg_access_t * val)1498 int32_t lsm6dso32_mem_bank_get(const stmdev_ctx_t *ctx,
1499 lsm6dso32_reg_access_t *val)
1500 {
1501 lsm6dso32_func_cfg_access_t reg;
1502 int32_t ret;
1503
1504 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1505 (uint8_t *)®, 1);
1506
1507 switch (reg.reg_access)
1508 {
1509 case LSM6DSO32_USER_BANK:
1510 *val = LSM6DSO32_USER_BANK;
1511 break;
1512
1513 case LSM6DSO32_SENSOR_HUB_BANK:
1514 *val = LSM6DSO32_SENSOR_HUB_BANK;
1515 break;
1516
1517 case LSM6DSO32_EMBEDDED_FUNC_BANK:
1518 *val = LSM6DSO32_EMBEDDED_FUNC_BANK;
1519 break;
1520
1521 default:
1522 *val = LSM6DSO32_USER_BANK;
1523 break;
1524 }
1525
1526 return ret;
1527 }
1528
1529 /**
1530 * @brief Write a line(byte) in a page.[set]
1531 *
1532 * @param ctx read / write interface definitions
1533 * @param uint8_t address: page line address
1534 * @param val value to write
1535 * @retval interface status (MANDATORY: return 0 -> no Error)
1536 *
1537 */
lsm6dso32_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1538 int32_t lsm6dso32_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
1539 {
1540 return lsm6dso32_ln_pg_write(ctx, address, val, 1);
1541 }
1542
1543 /**
1544 * @brief Write buffer in a page.[set]
1545 *
1546 * @param ctx read / write interface definitions
1547 * @param uint8_t address: page line address
1548 * @param uint8_t *buf: buffer to write
1549 * @param uint8_t len: buffer len
1550 * @retval interface status (MANDATORY: return 0 -> no Error)
1551 *
1552 */
lsm6dso32_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1553 int32_t lsm6dso32_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1554 uint8_t *buf, uint8_t len)
1555 {
1556 lsm6dso32_page_rw_t page_rw;
1557 lsm6dso32_page_sel_t page_sel;
1558 lsm6dso32_page_address_t page_address;
1559 uint8_t msb;
1560 uint8_t lsb;
1561 int32_t ret;
1562 uint8_t i ;
1563
1564 msb = ((uint8_t)(address >> 8) & 0x0FU);
1565 lsb = (uint8_t)address & 0xFFU;
1566
1567 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1568 if (ret != 0) { return ret; }
1569
1570 /* set page write */
1571 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1572 page_rw.page_rw = 0x02; /* page_write enable*/
1573 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1574 if (ret != 0) { goto exit; }
1575
1576 /* select page */
1577 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1578 page_sel.page_sel = msb;
1579 page_sel.not_used_01 = 1;
1580 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1581 if (ret != 0) { goto exit; }
1582
1583 /* set page addr */
1584 page_address.page_addr = lsb;
1585 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
1586 (uint8_t *)&page_address, 1);
1587 if (ret != 0) { goto exit; }
1588
1589 for (i = 0; ((i < len) && (ret == 0)); i++)
1590 {
1591 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1);
1592 if (ret != 0) { goto exit; }
1593
1594 lsb++;
1595
1596 /* Check if page wrap */
1597 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1598 {
1599 msb++;
1600 ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1);
1601 if (ret != 0) { goto exit; }
1602
1603 page_sel.page_sel = msb;
1604 page_sel.not_used_01 = 1;
1605 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1);
1606 if (ret != 0) { goto exit; }
1607 }
1608 }
1609
1610 page_sel.page_sel = 0;
1611 page_sel.not_used_01 = 1;
1612 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1613 if (ret != 0) { goto exit; }
1614
1615 /* unset page write */
1616 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1617 page_rw.page_rw = 0x00; /* page_write disable */
1618 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1619
1620 exit:
1621 ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1622
1623 return ret;
1624 }
1625
1626 /**
1627 * @brief Read a line(byte) in a page.[get]
1628 *
1629 * @param ctx read / write interface definitions
1630 * @param uint8_t address: page line address
1631 * @param val read value
1632 * @retval interface status (MANDATORY: return 0 -> no Error)
1633 *
1634 */
lsm6dso32_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1635 int32_t lsm6dso32_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
1636 {
1637 return lsm6dso32_ln_pg_read(ctx, address, val, 1);
1638 }
1639
lsm6dso32_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1640 int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
1641 uint8_t len)
1642 {
1643 lsm6dso32_page_rw_t page_rw;
1644 lsm6dso32_page_sel_t page_sel;
1645 lsm6dso32_page_address_t page_address;
1646 uint8_t msb;
1647 uint8_t lsb;
1648 int32_t ret;
1649 uint8_t i ;
1650
1651 msb = ((uint8_t)(address >> 8) & 0x0FU);
1652 lsb = (uint8_t)address & 0xFFU;
1653
1654 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1655 if (ret != 0) { return ret; }
1656
1657 /* set page write */
1658 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1659 page_rw.page_rw = 0x01; /* page_read enable*/
1660 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1661 if (ret != 0) { goto exit; }
1662
1663 /* select page */
1664 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1665 page_sel.page_sel = msb;
1666 page_sel.not_used_01 = 1;
1667 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1668 if (ret != 0) { goto exit; }
1669
1670 for (i = 0; ((i < len) && (ret == 0)); i++)
1671 {
1672 /* set page addr */
1673 page_address.page_addr = lsb;
1674 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
1675 (uint8_t *)&page_address, 1);
1676 if (ret != 0) { goto exit; }
1677
1678 ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1);
1679 if (ret != 0) { goto exit; }
1680
1681 lsb++;
1682
1683 /* Check if page wrap */
1684 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1685 {
1686 msb++;
1687 ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1);
1688 if (ret != 0) { goto exit; }
1689
1690 page_sel.page_sel = msb;
1691 page_sel.not_used_01 = 1;
1692 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1);
1693 if (ret != 0) { goto exit; }
1694 }
1695 }
1696
1697 page_sel.page_sel = 0;
1698 page_sel.not_used_01 = 1;
1699 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1);
1700 if (ret != 0) { goto exit; }
1701
1702 /* unset page write */
1703 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1704 page_rw.page_rw = 0x00; /* page_write disable */
1705 ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1706
1707 exit:
1708 ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1709
1710 return ret;
1711 }
1712
1713 /**
1714 * @brief Data-ready pulsed / letched mode.[set]
1715 *
1716 * @param ctx read / write interface definitions
1717 * @param val change the values of dataready_pulsed in
1718 * reg COUNTER_BDR_REG1
1719 * @retval interface status (MANDATORY: return 0 -> no Error)
1720 *
1721 */
lsm6dso32_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_dataready_pulsed_t val)1722 int32_t lsm6dso32_data_ready_mode_set(const stmdev_ctx_t *ctx,
1723 lsm6dso32_dataready_pulsed_t val)
1724 {
1725 lsm6dso32_counter_bdr_reg1_t reg;
1726 int32_t ret;
1727
1728 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1729 (uint8_t *)®, 1);
1730
1731 if (ret == 0)
1732 {
1733 reg.dataready_pulsed = (uint8_t)val;
1734 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1735 (uint8_t *)®, 1);
1736 }
1737
1738 return ret;
1739 }
1740
1741 /**
1742 * @brief Data-ready pulsed / letched mode.[get]
1743 *
1744 * @param ctx read / write interface definitions
1745 * @param val Get the values of
1746 * dataready_pulsed in
1747 * reg COUNTER_BDR_REG1
1748 * @retval interface status (MANDATORY: return 0 -> no Error)
1749 *
1750 */
lsm6dso32_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_dataready_pulsed_t * val)1751 int32_t lsm6dso32_data_ready_mode_get(const stmdev_ctx_t *ctx,
1752 lsm6dso32_dataready_pulsed_t *val)
1753 {
1754 lsm6dso32_counter_bdr_reg1_t reg;
1755 int32_t ret;
1756
1757 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1758 (uint8_t *)®, 1);
1759
1760 switch (reg.dataready_pulsed)
1761 {
1762 case LSM6DSO32_DRDY_LATCHED:
1763 *val = LSM6DSO32_DRDY_LATCHED;
1764 break;
1765
1766 case LSM6DSO32_DRDY_PULSED:
1767 *val = LSM6DSO32_DRDY_PULSED;
1768 break;
1769
1770 default:
1771 *val = LSM6DSO32_DRDY_LATCHED;
1772 break;
1773 }
1774
1775 return ret;
1776 }
1777
1778 /**
1779 * @brief Device "Who am I".[get]
1780 *
1781 * @param ctx read / write interface definitions
1782 * @param buff buffer that stores data read
1783 * @retval interface status (MANDATORY: return 0 -> no Error)
1784 *
1785 */
lsm6dso32_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1786 int32_t lsm6dso32_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1787 {
1788 int32_t ret;
1789
1790 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WHO_AM_I, buff, 1);
1791
1792 return ret;
1793 }
1794
1795 /**
1796 * @brief Software reset. Restore the default values
1797 * in user registers[set]
1798 *
1799 * @param ctx read / write interface definitions
1800 * @param val change the values of sw_reset in reg CTRL3_C
1801 * @retval interface status (MANDATORY: return 0 -> no Error)
1802 *
1803 */
lsm6dso32_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1804 int32_t lsm6dso32_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1805 {
1806 lsm6dso32_ctrl3_c_t reg;
1807 int32_t ret;
1808
1809 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1810
1811 if (ret == 0)
1812 {
1813 reg.sw_reset = val;
1814 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1815 }
1816
1817 return ret;
1818 }
1819
1820 /**
1821 * @brief Software reset. Restore the default values in user registers.[get]
1822 *
1823 * @param ctx read / write interface definitions
1824 * @param val change the values of sw_reset in reg CTRL3_C
1825 * @retval interface status (MANDATORY: return 0 -> no Error)
1826 *
1827 */
lsm6dso32_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1828 int32_t lsm6dso32_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1829 {
1830 lsm6dso32_ctrl3_c_t reg;
1831 int32_t ret;
1832
1833 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1834 *val = reg.sw_reset;
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief Register address automatically incremented during a multiple byte
1841 * access with a serial interface.[set]
1842 *
1843 * @param ctx read / write interface definitions
1844 * @param val change the values of if_inc in reg CTRL3_C
1845 * @retval interface status (MANDATORY: return 0 -> no Error)
1846 *
1847 */
lsm6dso32_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1848 int32_t lsm6dso32_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1849 {
1850 lsm6dso32_ctrl3_c_t reg;
1851 int32_t ret;
1852
1853 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1854
1855 if (ret == 0)
1856 {
1857 reg.if_inc = val;
1858 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1859 }
1860
1861 return ret;
1862 }
1863
1864 /**
1865 * @brief Register address automatically incremented during a multiple byte
1866 * access with a serial interface.[get]
1867 *
1868 * @param ctx read / write interface definitions
1869 * @param val change the values of if_inc in reg CTRL3_C
1870 * @retval interface status (MANDATORY: return 0 -> no Error)
1871 *
1872 */
lsm6dso32_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1873 int32_t lsm6dso32_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1874 {
1875 lsm6dso32_ctrl3_c_t reg;
1876 int32_t ret;
1877
1878 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1879 *val = reg.if_inc;
1880
1881 return ret;
1882 }
1883
1884 /**
1885 * @brief Reboot memory content. Reload the calibration parameters.[set]
1886 *
1887 * @param ctx read / write interface definitions
1888 * @param val change the values of boot in reg CTRL3_C
1889 * @retval interface status (MANDATORY: return 0 -> no Error)
1890 *
1891 */
lsm6dso32_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1892 int32_t lsm6dso32_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1893 {
1894 lsm6dso32_ctrl3_c_t reg;
1895 int32_t ret;
1896
1897 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1898
1899 if (ret == 0)
1900 {
1901 reg.boot = val;
1902 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1903 }
1904
1905 return ret;
1906 }
1907
1908 /**
1909 * @brief Reboot memory content. Reload the calibration parameters.[get]
1910 *
1911 * @param ctx read / write interface definitions
1912 * @param val change the values of boot in reg CTRL3_C
1913 * @retval interface status (MANDATORY: return 0 -> no Error)
1914 *
1915 */
lsm6dso32_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1916 int32_t lsm6dso32_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1917 {
1918 lsm6dso32_ctrl3_c_t reg;
1919 int32_t ret;
1920
1921 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1922 *val = reg.boot;
1923
1924 return ret;
1925 }
1926
1927 /**
1928 * @brief Linear acceleration sensor self-test enable.[set]
1929 *
1930 * @param ctx read / write interface definitions
1931 * @param val change the values of st_xl in reg CTRL5_C
1932 * @retval interface status (MANDATORY: return 0 -> no Error)
1933 *
1934 */
lsm6dso32_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dso32_st_xl_t val)1935 int32_t lsm6dso32_xl_self_test_set(const stmdev_ctx_t *ctx,
1936 lsm6dso32_st_xl_t val)
1937 {
1938 lsm6dso32_ctrl5_c_t reg;
1939 int32_t ret;
1940
1941 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1942
1943 if (ret == 0)
1944 {
1945 reg.st_xl = (uint8_t)val;
1946 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1947 }
1948
1949 return ret;
1950 }
1951
1952 /**
1953 * @brief Linear acceleration sensor self-test enable.[get]
1954 *
1955 * @param ctx read / write interface definitions
1956 * @param val Get the values of st_xl in reg CTRL5_C
1957 * @retval interface status (MANDATORY: return 0 -> no Error)
1958 *
1959 */
lsm6dso32_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dso32_st_xl_t * val)1960 int32_t lsm6dso32_xl_self_test_get(const stmdev_ctx_t *ctx,
1961 lsm6dso32_st_xl_t *val)
1962 {
1963 lsm6dso32_ctrl5_c_t reg;
1964 int32_t ret;
1965
1966 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1967
1968 switch (reg.st_xl)
1969 {
1970 case LSM6DSO32_XL_ST_DISABLE:
1971 *val = LSM6DSO32_XL_ST_DISABLE;
1972 break;
1973
1974 case LSM6DSO32_XL_ST_POSITIVE:
1975 *val = LSM6DSO32_XL_ST_POSITIVE;
1976 break;
1977
1978 case LSM6DSO32_XL_ST_NEGATIVE:
1979 *val = LSM6DSO32_XL_ST_NEGATIVE;
1980 break;
1981
1982 default:
1983 *val = LSM6DSO32_XL_ST_DISABLE;
1984 break;
1985 }
1986
1987 return ret;
1988 }
1989
1990 /**
1991 * @brief Angular rate sensor self-test enable.[set]
1992 *
1993 * @param ctx read / write interface definitions
1994 * @param val change the values of st_g in reg CTRL5_C
1995 * @retval interface status (MANDATORY: return 0 -> no Error)
1996 *
1997 */
lsm6dso32_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dso32_st_g_t val)1998 int32_t lsm6dso32_gy_self_test_set(const stmdev_ctx_t *ctx,
1999 lsm6dso32_st_g_t val)
2000 {
2001 lsm6dso32_ctrl5_c_t reg;
2002 int32_t ret;
2003
2004 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2005
2006 if (ret == 0)
2007 {
2008 reg.st_g = (uint8_t)val;
2009 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2010 }
2011
2012 return ret;
2013 }
2014
2015 /**
2016 * @brief Angular rate sensor self-test enable.[get]
2017 *
2018 * @param ctx read / write interface definitions
2019 * @param val Get the values of st_g in reg CTRL5_C
2020 * @retval interface status (MANDATORY: return 0 -> no Error)
2021 *
2022 */
lsm6dso32_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dso32_st_g_t * val)2023 int32_t lsm6dso32_gy_self_test_get(const stmdev_ctx_t *ctx,
2024 lsm6dso32_st_g_t *val)
2025 {
2026 lsm6dso32_ctrl5_c_t reg;
2027 int32_t ret;
2028
2029 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2030
2031 switch (reg.st_g)
2032 {
2033 case LSM6DSO32_GY_ST_DISABLE:
2034 *val = LSM6DSO32_GY_ST_DISABLE;
2035 break;
2036
2037 case LSM6DSO32_GY_ST_POSITIVE:
2038 *val = LSM6DSO32_GY_ST_POSITIVE;
2039 break;
2040
2041 case LSM6DSO32_GY_ST_NEGATIVE:
2042 *val = LSM6DSO32_GY_ST_NEGATIVE;
2043 break;
2044
2045 default:
2046 *val = LSM6DSO32_GY_ST_DISABLE;
2047 break;
2048 }
2049
2050 return ret;
2051 }
2052
2053 /**
2054 * @}
2055 *
2056 */
2057
2058 /**
2059 * @defgroup LSM6DSO32_filters
2060 * @brief This section group all the functions concerning the
2061 * filters configuration
2062 * @{
2063 *
2064 */
2065
2066 /**
2067 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2068 *
2069 * @param ctx read / write interface definitions
2070 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2071 * @retval interface status (MANDATORY: return 0 -> no Error)
2072 *
2073 */
lsm6dso32_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2074 int32_t lsm6dso32_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2075 {
2076 lsm6dso32_ctrl1_xl_t reg;
2077 int32_t ret;
2078
2079 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2080
2081 if (ret == 0)
2082 {
2083 reg.lpf2_xl_en = val;
2084 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2085 }
2086
2087 return ret;
2088 }
2089
2090 /**
2091 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2092 *
2093 * @param ctx read / write interface definitions
2094 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2095 * @retval interface status (MANDATORY: return 0 -> no Error)
2096 *
2097 */
lsm6dso32_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2098 int32_t lsm6dso32_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2099 {
2100 lsm6dso32_ctrl1_xl_t reg;
2101 int32_t ret;
2102
2103 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2104 *val = reg.lpf2_xl_en;
2105
2106 return ret;
2107 }
2108
2109 /**
2110 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2111 * the bandwidth can be selected through FTYPE [2:0]
2112 * in CTRL6_C (15h).[set]
2113 *
2114 * @param ctx read / write interface definitions
2115 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2116 * @retval interface status (MANDATORY: return 0 -> no Error)
2117 *
2118 */
lsm6dso32_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2119 int32_t lsm6dso32_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2120 {
2121 lsm6dso32_ctrl4_c_t reg;
2122 int32_t ret;
2123
2124 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2125
2126 if (ret == 0)
2127 {
2128 reg.lpf1_sel_g = val;
2129 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2130 }
2131
2132 return ret;
2133 }
2134
2135 /**
2136 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2137 * the bandwidth can be selected through FTYPE [2:0]
2138 * in CTRL6_C (15h).[get]
2139 *
2140 * @param ctx read / write interface definitions
2141 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2142 * @retval interface status (MANDATORY: return 0 -> no Error)
2143 *
2144 */
lsm6dso32_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2145 int32_t lsm6dso32_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2146 {
2147 lsm6dso32_ctrl4_c_t reg;
2148 int32_t ret;
2149
2150 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2151 *val = reg.lpf1_sel_g;
2152
2153 return ret;
2154 }
2155
2156 /**
2157 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2158 * (XL and Gyro independently masked).[set]
2159 *
2160 * @param ctx read / write interface definitions
2161 * @param val change the values of drdy_mask in reg CTRL4_C
2162 * @retval interface status (MANDATORY: return 0 -> no Error)
2163 *
2164 */
lsm6dso32_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2165 int32_t lsm6dso32_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2166 uint8_t val)
2167 {
2168 lsm6dso32_ctrl4_c_t reg;
2169 int32_t ret;
2170
2171 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2172
2173 if (ret == 0)
2174 {
2175 reg.drdy_mask = val;
2176 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2177 }
2178
2179 return ret;
2180 }
2181
2182 /**
2183 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2184 * (XL and Gyro independently masked).[get]
2185 *
2186 * @param ctx read / write interface definitions
2187 * @param val change the values of drdy_mask in reg CTRL4_C
2188 * @retval interface status (MANDATORY: return 0 -> no Error)
2189 *
2190 */
lsm6dso32_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2191 int32_t lsm6dso32_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2192 uint8_t *val)
2193 {
2194 lsm6dso32_ctrl4_c_t reg;
2195 int32_t ret;
2196
2197 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2198 *val = reg.drdy_mask;
2199
2200 return ret;
2201 }
2202
2203 /**
2204 * @brief Gyroscope lp1 bandwidth.[set]
2205 *
2206 * @param ctx read / write interface definitions
2207 * @param val change the values of ftype in reg CTRL6_C
2208 * @retval interface status (MANDATORY: return 0 -> no Error)
2209 *
2210 */
lsm6dso32_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso32_ftype_t val)2211 int32_t lsm6dso32_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2212 lsm6dso32_ftype_t val)
2213 {
2214 lsm6dso32_ctrl6_c_t reg;
2215 int32_t ret;
2216
2217 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2218
2219 if (ret == 0)
2220 {
2221 reg.ftype = (uint8_t)val;
2222 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2223 }
2224
2225 return ret;
2226 }
2227
2228 /**
2229 * @brief Gyroscope lp1 bandwidth.[get]
2230 *
2231 * @param ctx read / write interface definitions
2232 * @param val Get the values of ftype in reg CTRL6_C
2233 * @retval interface status (MANDATORY: return 0 -> no Error)
2234 *
2235 */
lsm6dso32_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso32_ftype_t * val)2236 int32_t lsm6dso32_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2237 lsm6dso32_ftype_t *val)
2238 {
2239 lsm6dso32_ctrl6_c_t reg;
2240 int32_t ret;
2241
2242 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2243
2244 switch (reg.ftype)
2245 {
2246 case LSM6DSO32_ULTRA_LIGHT:
2247 *val = LSM6DSO32_ULTRA_LIGHT;
2248 break;
2249
2250 case LSM6DSO32_VERY_LIGHT:
2251 *val = LSM6DSO32_VERY_LIGHT;
2252 break;
2253
2254 case LSM6DSO32_LIGHT:
2255 *val = LSM6DSO32_LIGHT;
2256 break;
2257
2258 case LSM6DSO32_MEDIUM:
2259 *val = LSM6DSO32_MEDIUM;
2260 break;
2261
2262 case LSM6DSO32_STRONG:
2263 *val = LSM6DSO32_STRONG;
2264 break;
2265
2266 case LSM6DSO32_VERY_STRONG:
2267 *val = LSM6DSO32_VERY_STRONG;
2268 break;
2269
2270 case LSM6DSO32_AGGRESSIVE:
2271 *val = LSM6DSO32_AGGRESSIVE;
2272 break;
2273
2274 case LSM6DSO32_XTREME:
2275 *val = LSM6DSO32_XTREME;
2276 break;
2277
2278 default:
2279 *val = LSM6DSO32_ULTRA_LIGHT;
2280 break;
2281 }
2282
2283 return ret;
2284 }
2285
2286 /**
2287 * @brief Low pass filter 2 on 6D function selection.[set]
2288 *
2289 * @param ctx read / write interface definitions
2290 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2291 * @retval interface status (MANDATORY: return 0 -> no Error)
2292 *
2293 */
lsm6dso32_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2294 int32_t lsm6dso32_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2295 {
2296 lsm6dso32_ctrl8_xl_t reg;
2297 int32_t ret;
2298
2299 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2300
2301 if (ret == 0)
2302 {
2303 reg.low_pass_on_6d = val;
2304 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2305 }
2306
2307 return ret;
2308 }
2309
2310 /**
2311 * @brief Low pass filter 2 on 6D function selection.[get]
2312 *
2313 * @param ctx read / write interface definitions
2314 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2315 * @retval interface status (MANDATORY: return 0 -> no Error)
2316 *
2317 */
lsm6dso32_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2318 int32_t lsm6dso32_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2319 {
2320 lsm6dso32_ctrl8_xl_t reg;
2321 int32_t ret;
2322
2323 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2324 *val = reg.low_pass_on_6d;
2325
2326 return ret;
2327 }
2328
2329 /**
2330 * @brief Accelerometer slope filter / high-pass filter selection
2331 * on output.[set]
2332 *
2333 * @param ctx read / write interface definitions
2334 * @param val change the values of hp_slope_xl_en
2335 * in reg CTRL8_XL
2336 * @retval interface status (MANDATORY: return 0 -> no Error)
2337 *
2338 */
lsm6dso32_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dso32_hp_slope_xl_en_t val)2339 int32_t lsm6dso32_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2340 lsm6dso32_hp_slope_xl_en_t val)
2341 {
2342 lsm6dso32_ctrl8_xl_t reg;
2343 int32_t ret;
2344
2345 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2346
2347 if (ret == 0)
2348 {
2349 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2350 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2351 reg.hpcf_xl = (uint8_t)val & 0x07U;
2352 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2353 }
2354
2355 return ret;
2356 }
2357
2358 /**
2359 * @brief Accelerometer slope filter / high-pass filter selection
2360 * on output.[get]
2361 *
2362 * @param ctx read / write interface definitions
2363 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2364 * @retval interface status (MANDATORY: return 0 -> no Error)
2365 *
2366 */
lsm6dso32_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dso32_hp_slope_xl_en_t * val)2367 int32_t lsm6dso32_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2368 lsm6dso32_hp_slope_xl_en_t *val)
2369 {
2370 lsm6dso32_ctrl8_xl_t reg;
2371 int32_t ret;
2372
2373 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2374
2375 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2376 reg.hpcf_xl)
2377 {
2378 case LSM6DSO32_HP_PATH_DISABLE_ON_OUT:
2379 *val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
2380 break;
2381
2382 case LSM6DSO32_SLOPE_ODR_DIV_4:
2383 *val = LSM6DSO32_SLOPE_ODR_DIV_4;
2384 break;
2385
2386 case LSM6DSO32_HP_ODR_DIV_10:
2387 *val = LSM6DSO32_HP_ODR_DIV_10;
2388 break;
2389
2390 case LSM6DSO32_HP_ODR_DIV_20:
2391 *val = LSM6DSO32_HP_ODR_DIV_20;
2392 break;
2393
2394 case LSM6DSO32_HP_ODR_DIV_45:
2395 *val = LSM6DSO32_HP_ODR_DIV_45;
2396 break;
2397
2398 case LSM6DSO32_HP_ODR_DIV_100:
2399 *val = LSM6DSO32_HP_ODR_DIV_100;
2400 break;
2401
2402 case LSM6DSO32_HP_ODR_DIV_200:
2403 *val = LSM6DSO32_HP_ODR_DIV_200;
2404 break;
2405
2406 case LSM6DSO32_HP_ODR_DIV_400:
2407 *val = LSM6DSO32_HP_ODR_DIV_400;
2408 break;
2409
2410 case LSM6DSO32_HP_ODR_DIV_800:
2411 *val = LSM6DSO32_HP_ODR_DIV_800;
2412 break;
2413
2414 case LSM6DSO32_HP_REF_MD_ODR_DIV_10:
2415 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_10;
2416 break;
2417
2418 case LSM6DSO32_HP_REF_MD_ODR_DIV_20:
2419 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_20;
2420 break;
2421
2422 case LSM6DSO32_HP_REF_MD_ODR_DIV_45:
2423 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_45;
2424 break;
2425
2426 case LSM6DSO32_HP_REF_MD_ODR_DIV_100:
2427 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_100;
2428 break;
2429
2430 case LSM6DSO32_HP_REF_MD_ODR_DIV_200:
2431 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_200;
2432 break;
2433
2434 case LSM6DSO32_HP_REF_MD_ODR_DIV_400:
2435 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_400;
2436 break;
2437
2438 case LSM6DSO32_HP_REF_MD_ODR_DIV_800:
2439 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_800;
2440 break;
2441
2442 case LSM6DSO32_LP_ODR_DIV_10:
2443 *val = LSM6DSO32_LP_ODR_DIV_10;
2444 break;
2445
2446 case LSM6DSO32_LP_ODR_DIV_20:
2447 *val = LSM6DSO32_LP_ODR_DIV_20;
2448 break;
2449
2450 case LSM6DSO32_LP_ODR_DIV_45:
2451 *val = LSM6DSO32_LP_ODR_DIV_45;
2452 break;
2453
2454 case LSM6DSO32_LP_ODR_DIV_100:
2455 *val = LSM6DSO32_LP_ODR_DIV_100;
2456 break;
2457
2458 case LSM6DSO32_LP_ODR_DIV_200:
2459 *val = LSM6DSO32_LP_ODR_DIV_200;
2460 break;
2461
2462 case LSM6DSO32_LP_ODR_DIV_400:
2463 *val = LSM6DSO32_LP_ODR_DIV_400;
2464 break;
2465
2466 case LSM6DSO32_LP_ODR_DIV_800:
2467 *val = LSM6DSO32_LP_ODR_DIV_800;
2468 break;
2469
2470 default:
2471 *val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
2472 break;
2473 }
2474
2475 return ret;
2476 }
2477
2478 /**
2479 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2480 * The filter sets the second samples after writing this bit.
2481 * Active only during device exit from power-down mode.[set]
2482 *
2483 * @param ctx read / write interface definitions
2484 * @param val change the values of fastsettl_mode_xl in
2485 * reg CTRL8_XL
2486 * @retval interface status (MANDATORY: return 0 -> no Error)
2487 *
2488 */
lsm6dso32_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2489 int32_t lsm6dso32_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2490 {
2491 lsm6dso32_ctrl8_xl_t reg;
2492 int32_t ret;
2493
2494 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2495
2496 if (ret == 0)
2497 {
2498 reg.fastsettl_mode_xl = val;
2499 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2500 }
2501
2502 return ret;
2503 }
2504
2505 /**
2506 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2507 * The filter sets the second samples after writing this bit.
2508 * Active only during device exit from power-down mode.[get]
2509 *
2510 * @param ctx read / write interface definitions
2511 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
2512 * @retval interface status (MANDATORY: return 0 -> no Error)
2513 *
2514 */
lsm6dso32_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2515 int32_t lsm6dso32_xl_fast_settling_get(const stmdev_ctx_t *ctx,
2516 uint8_t *val)
2517 {
2518 lsm6dso32_ctrl8_xl_t reg;
2519 int32_t ret;
2520
2521 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2522 *val = reg.fastsettl_mode_xl;
2523
2524 return ret;
2525 }
2526
2527 /**
2528 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2529 * functions.[set]
2530 *
2531 * @param ctx read / write interface definitions
2532 * @param val change the values of slope_fds in reg TAP_CFG0
2533 * @retval interface status (MANDATORY: return 0 -> no Error)
2534 *
2535 */
lsm6dso32_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso32_slope_fds_t val)2536 int32_t lsm6dso32_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2537 lsm6dso32_slope_fds_t val)
2538 {
2539 lsm6dso32_tap_cfg0_t reg;
2540 int32_t ret;
2541
2542 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2543
2544 if (ret == 0)
2545 {
2546 reg.slope_fds = (uint8_t)val;
2547 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2548 }
2549
2550 return ret;
2551 }
2552
2553 /**
2554 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2555 * functions.[get]
2556 *
2557 * @param ctx read / write interface definitions
2558 * @param val Get the values of slope_fds in reg TAP_CFG0
2559 * @retval interface status (MANDATORY: return 0 -> no Error)
2560 *
2561 */
lsm6dso32_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso32_slope_fds_t * val)2562 int32_t lsm6dso32_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2563 lsm6dso32_slope_fds_t *val)
2564 {
2565 lsm6dso32_tap_cfg0_t reg;
2566 int32_t ret;
2567
2568 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2569
2570 switch (reg.slope_fds)
2571 {
2572 case LSM6DSO32_USE_SLOPE:
2573 *val = LSM6DSO32_USE_SLOPE;
2574 break;
2575
2576 case LSM6DSO32_USE_HPF:
2577 *val = LSM6DSO32_USE_HPF;
2578 break;
2579
2580 default:
2581 *val = LSM6DSO32_USE_SLOPE;
2582 break;
2583 }
2584
2585 return ret;
2586 }
2587
2588 /**
2589 * @brief Enables gyroscope digital high-pass filter. The filter is
2590 * enabled only if the gyro is in HP mode.[set]
2591 *
2592 * @param ctx read / write interface definitions
2593 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2594 * @retval interface status (MANDATORY: return 0 -> no Error)
2595 *
2596 */
lsm6dso32_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso32_hpm_g_t val)2597 int32_t lsm6dso32_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2598 lsm6dso32_hpm_g_t val)
2599 {
2600 lsm6dso32_ctrl7_g_t reg;
2601 int32_t ret;
2602
2603 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2604
2605 if (ret == 0)
2606 {
2607 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2608 reg.hpm_g = (uint8_t)val & 0x03U;
2609 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2610 }
2611
2612 return ret;
2613 }
2614
2615 /**
2616 * @brief Enables gyroscope digital high-pass filter. The filter is
2617 * enabled only if the gyro is in HP mode.[get]
2618 *
2619 * @param ctx read / write interface definitions
2620 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2621 * @retval interface status (MANDATORY: return 0 -> no Error)
2622 *
2623 */
lsm6dso32_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso32_hpm_g_t * val)2624 int32_t lsm6dso32_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
2625 lsm6dso32_hpm_g_t *val)
2626 {
2627 lsm6dso32_ctrl7_g_t reg;
2628 int32_t ret;
2629
2630 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2631
2632 switch ((reg.hp_en_g << 7) + reg.hpm_g)
2633 {
2634 case LSM6DSO32_HP_FILTER_NONE:
2635 *val = LSM6DSO32_HP_FILTER_NONE;
2636 break;
2637
2638 case LSM6DSO32_HP_FILTER_16mHz:
2639 *val = LSM6DSO32_HP_FILTER_16mHz;
2640 break;
2641
2642 case LSM6DSO32_HP_FILTER_65mHz:
2643 *val = LSM6DSO32_HP_FILTER_65mHz;
2644 break;
2645
2646 case LSM6DSO32_HP_FILTER_260mHz:
2647 *val = LSM6DSO32_HP_FILTER_260mHz;
2648 break;
2649
2650 case LSM6DSO32_HP_FILTER_1Hz04:
2651 *val = LSM6DSO32_HP_FILTER_1Hz04;
2652 break;
2653
2654 default:
2655 *val = LSM6DSO32_HP_FILTER_NONE;
2656 break;
2657 }
2658
2659 return ret;
2660 }
2661
2662 /**
2663 * @}
2664 *
2665 */
2666
2667 /**
2668 * @defgroup LSM6DSO32 main_serial_interface
2669 * @brief This section groups all the functions concerning main
2670 * serial interface management (not auxiliary)
2671 * @{
2672 *
2673 */
2674
2675 /**
2676 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2677 *
2678 * @param ctx read / write interface definitions
2679 * @param val change the values of sdo_pu_en in
2680 * reg PIN_CTRL
2681 * @retval interface status (MANDATORY: return 0 -> no Error)
2682 *
2683 */
lsm6dso32_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_sdo_pu_en_t val)2684 int32_t lsm6dso32_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2685 lsm6dso32_sdo_pu_en_t val)
2686 {
2687 lsm6dso32_pin_ctrl_t reg;
2688 int32_t ret;
2689
2690 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2691
2692 if (ret == 0)
2693 {
2694 reg.sdo_pu_en = (uint8_t)val;
2695 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2696 }
2697
2698 return ret;
2699 }
2700
2701 /**
2702 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2703 *
2704 * @param ctx read / write interface definitions
2705 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2706 * @retval interface status (MANDATORY: return 0 -> no Error)
2707 *
2708 */
lsm6dso32_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_sdo_pu_en_t * val)2709 int32_t lsm6dso32_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2710 lsm6dso32_sdo_pu_en_t *val)
2711 {
2712 lsm6dso32_pin_ctrl_t reg;
2713 int32_t ret;
2714
2715 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2716
2717 switch (reg.sdo_pu_en)
2718 {
2719 case LSM6DSO32_PULL_UP_DISC:
2720 *val = LSM6DSO32_PULL_UP_DISC;
2721 break;
2722
2723 case LSM6DSO32_PULL_UP_CONNECT:
2724 *val = LSM6DSO32_PULL_UP_CONNECT;
2725 break;
2726
2727 default:
2728 *val = LSM6DSO32_PULL_UP_DISC;
2729 break;
2730 }
2731
2732 return ret;
2733 }
2734
2735 /**
2736 * @brief SPI Serial Interface Mode selection.[set]
2737 *
2738 * @param ctx read / write interface definitions
2739 * @param val change the values of sim in reg CTRL3_C
2740 * @retval interface status (MANDATORY: return 0 -> no Error)
2741 *
2742 */
lsm6dso32_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_sim_t val)2743 int32_t lsm6dso32_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_sim_t val)
2744 {
2745 lsm6dso32_ctrl3_c_t reg;
2746 int32_t ret;
2747
2748 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2749
2750 if (ret == 0)
2751 {
2752 reg.sim = (uint8_t)val;
2753 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2754 }
2755
2756 return ret;
2757 }
2758
2759 /**
2760 * @brief SPI Serial Interface Mode selection.[get]
2761 *
2762 * @param ctx read / write interface definitions
2763 * @param val Get the values of sim in reg CTRL3_C
2764 * @retval interface status (MANDATORY: return 0 -> no Error)
2765 *
2766 */
lsm6dso32_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_sim_t * val)2767 int32_t lsm6dso32_spi_mode_get(const stmdev_ctx_t *ctx,
2768 lsm6dso32_sim_t *val)
2769 {
2770 lsm6dso32_ctrl3_c_t reg;
2771 int32_t ret;
2772
2773 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2774
2775 switch (reg.sim)
2776 {
2777 case LSM6DSO32_SPI_4_WIRE:
2778 *val = LSM6DSO32_SPI_4_WIRE;
2779 break;
2780
2781 case LSM6DSO32_SPI_3_WIRE:
2782 *val = LSM6DSO32_SPI_3_WIRE;
2783 break;
2784
2785 default:
2786 *val = LSM6DSO32_SPI_4_WIRE;
2787 break;
2788 }
2789
2790 return ret;
2791 }
2792
2793 /**
2794 * @brief Disable / Enable I2C interface.[set]
2795 *
2796 * @param ctx read / write interface definitions
2797 * @param val change the values of i2c_disable in
2798 * reg CTRL4_C
2799 * @retval interface status (MANDATORY: return 0 -> no Error)
2800 *
2801 */
lsm6dso32_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dso32_i2c_disable_t val)2802 int32_t lsm6dso32_i2c_interface_set(const stmdev_ctx_t *ctx,
2803 lsm6dso32_i2c_disable_t val)
2804 {
2805 lsm6dso32_ctrl4_c_t reg;
2806 int32_t ret;
2807
2808 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2809
2810 if (ret == 0)
2811 {
2812 reg.i2c_disable = (uint8_t)val;
2813 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2814 }
2815
2816 return ret;
2817 }
2818
2819 /**
2820 * @brief Disable / Enable I2C interface.[get]
2821 *
2822 * @param ctx read / write interface definitions
2823 * @param val Get the values of i2c_disable in
2824 * reg CTRL4_C
2825 * @retval interface status (MANDATORY: return 0 -> no Error)
2826 *
2827 */
lsm6dso32_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dso32_i2c_disable_t * val)2828 int32_t lsm6dso32_i2c_interface_get(const stmdev_ctx_t *ctx,
2829 lsm6dso32_i2c_disable_t *val)
2830 {
2831 lsm6dso32_ctrl4_c_t reg;
2832 int32_t ret;
2833
2834 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2835
2836 switch (reg.i2c_disable)
2837 {
2838 case LSM6DSO32_I2C_ENABLE:
2839 *val = LSM6DSO32_I2C_ENABLE;
2840 break;
2841
2842 case LSM6DSO32_I2C_DISABLE:
2843 *val = LSM6DSO32_I2C_DISABLE;
2844 break;
2845
2846 default:
2847 *val = LSM6DSO32_I2C_ENABLE;
2848 break;
2849 }
2850
2851 return ret;
2852 }
2853
2854 /**
2855 * @brief I3C Enable/Disable communication protocol[.set]
2856 *
2857 * @param ctx read / write interface definitions
2858 * @param val change the values of i3c_disable in reg CTRL9_XL
2859 * @retval interface status (MANDATORY: return 0 -> no Error)
2860 *
2861 */
lsm6dso32_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dso32_i3c_disable_t val)2862 int32_t lsm6dso32_i3c_disable_set(const stmdev_ctx_t *ctx,
2863 lsm6dso32_i3c_disable_t val)
2864 {
2865 lsm6dso32_i3c_bus_avb_t i3c_bus_avb;
2866 lsm6dso32_ctrl9_xl_t ctrl9_xl;
2867 int32_t ret;
2868
2869 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
2870 (uint8_t *)&ctrl9_xl, 1);
2871
2872 if (ret == 0)
2873 {
2874 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
2875 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL,
2876 (uint8_t *)&ctrl9_xl, 1);
2877 }
2878
2879 if (ret == 0)
2880 {
2881 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2882 (uint8_t *)&i3c_bus_avb, 1);
2883 }
2884
2885 if (ret == 0)
2886 {
2887 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
2888 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2889 (uint8_t *)&i3c_bus_avb, 1);
2890 }
2891
2892 return ret;
2893 }
2894
2895 /**
2896 * @brief I3C Enable/Disable communication protocol.[get]
2897 *
2898 * @param ctx read / write interface definitions
2899 * @param val change the values of i3c_disable in reg CTRL9_XL
2900 * @retval interface status (MANDATORY: return 0 -> no Error)
2901 *
2902 */
lsm6dso32_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dso32_i3c_disable_t * val)2903 int32_t lsm6dso32_i3c_disable_get(const stmdev_ctx_t *ctx,
2904 lsm6dso32_i3c_disable_t *val)
2905 {
2906 lsm6dso32_ctrl9_xl_t ctrl9_xl;
2907 lsm6dso32_i3c_bus_avb_t i3c_bus_avb;
2908 int32_t ret;
2909
2910 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
2911 (uint8_t *)&ctrl9_xl, 1);
2912
2913 if (ret == 0)
2914 {
2915 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2916 (uint8_t *)&i3c_bus_avb, 1);
2917
2918 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
2919 {
2920 case LSM6DSO32_I3C_DISABLE:
2921 *val = LSM6DSO32_I3C_DISABLE;
2922 break;
2923
2924 case LSM6DSO32_I3C_ENABLE_T_50us:
2925 *val = LSM6DSO32_I3C_ENABLE_T_50us;
2926 break;
2927
2928 case LSM6DSO32_I3C_ENABLE_T_2us:
2929 *val = LSM6DSO32_I3C_ENABLE_T_2us;
2930 break;
2931
2932 case LSM6DSO32_I3C_ENABLE_T_1ms:
2933 *val = LSM6DSO32_I3C_ENABLE_T_1ms;
2934 break;
2935
2936 case LSM6DSO32_I3C_ENABLE_T_25ms:
2937 *val = LSM6DSO32_I3C_ENABLE_T_25ms;
2938 break;
2939
2940 default:
2941 *val = LSM6DSO32_I3C_DISABLE;
2942 break;
2943 }
2944 }
2945
2946 return ret;
2947 }
2948
2949 /**
2950 * @}
2951 *
2952 */
2953
2954 /**
2955 * @defgroup LSM6DSO32_interrupt_pins
2956 * @brief This section groups all the functions that manage interrupt pins
2957 * @{
2958 *
2959 */
2960
2961 /**
2962 * @brief Connect/Disconnect INT1 internal pull-down.[set]
2963 *
2964 * @param ctx read / write interface definitions
2965 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
2966 * @retval interface status (MANDATORY: return 0 -> no Error)
2967 *
2968 */
lsm6dso32_int1_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_int1_pd_en_t val)2969 int32_t lsm6dso32_int1_mode_set(const stmdev_ctx_t *ctx,
2970 lsm6dso32_int1_pd_en_t val)
2971 {
2972 lsm6dso32_i3c_bus_avb_t reg;
2973 int32_t ret;
2974
2975 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
2976
2977 if (ret == 0)
2978 {
2979 reg.pd_dis_int1 = (uint8_t)val;
2980 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
2981 }
2982
2983 return ret;
2984 }
2985
2986 /**
2987 * @brief Connect/Disconnect INT1 internal pull-down.[get]
2988 *
2989 * @param ctx read / write interface definitions
2990 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
2991 * @retval interface status (MANDATORY: return 0 -> no Error)
2992 *
2993 */
lsm6dso32_int1_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_int1_pd_en_t * val)2994 int32_t lsm6dso32_int1_mode_get(const stmdev_ctx_t *ctx,
2995 lsm6dso32_int1_pd_en_t *val)
2996 {
2997 lsm6dso32_i3c_bus_avb_t reg;
2998 int32_t ret;
2999
3000 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
3001
3002 switch (reg.pd_dis_int1)
3003 {
3004 case LSM6DSO32_PULL_DOWN_DISC:
3005 *val = LSM6DSO32_PULL_DOWN_DISC;
3006 break;
3007
3008 case LSM6DSO32_PULL_DOWN_CONNECT:
3009 *val = LSM6DSO32_PULL_DOWN_CONNECT;
3010 break;
3011
3012 default:
3013 *val = LSM6DSO32_PULL_DOWN_DISC;
3014 break;
3015 }
3016
3017 return ret;
3018 }
3019
3020 /**
3021 * @brief Select the signal that need to route on int1 pad.[set]
3022 *
3023 * @param ctx read / write interface definitions
3024 * @param val struct of registers: INT1_CTRL,
3025 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3026 * FSM_INT1_B
3027 * @retval interface status (MANDATORY: return 0 -> no Error)
3028 *
3029 */
lsm6dso32_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dso32_pin_int1_route_t * val)3030 int32_t lsm6dso32_pin_int1_route_set(const stmdev_ctx_t *ctx,
3031 lsm6dso32_pin_int1_route_t *val)
3032 {
3033 lsm6dso32_pin_int2_route_t pin_int2_route;
3034 lsm6dso32_tap_cfg2_t tap_cfg2;
3035 int32_t ret;
3036
3037 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3038
3039 if (ret == 0)
3040 {
3041 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
3042 (uint8_t *)&val->emb_func_int1, 1);
3043 }
3044
3045 if (ret == 0)
3046 {
3047 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_A,
3048 (uint8_t *)&val->fsm_int1_a, 1);
3049 }
3050
3051 if (ret == 0)
3052 {
3053 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_B,
3054 (uint8_t *)&val->fsm_int1_b, 1);
3055 }
3056
3057 if (ret == 0)
3058 {
3059 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3060 }
3061
3062 if (ret == 0)
3063 {
3064 if ((val->emb_func_int1.int1_fsm_lc
3065 | val->emb_func_int1.int1_sig_mot
3066 | val->emb_func_int1.int1_step_detector
3067 | val->emb_func_int1.int1_tilt
3068 | val->fsm_int1_a.int1_fsm1
3069 | val->fsm_int1_a.int1_fsm2
3070 | val->fsm_int1_a.int1_fsm3
3071 | val->fsm_int1_a.int1_fsm4
3072 | val->fsm_int1_a.int1_fsm5
3073 | val->fsm_int1_a.int1_fsm6
3074 | val->fsm_int1_a.int1_fsm7
3075 | val->fsm_int1_a.int1_fsm8
3076 | val->fsm_int1_b.int1_fsm9
3077 | val->fsm_int1_b.int1_fsm10
3078 | val->fsm_int1_b.int1_fsm11
3079 | val->fsm_int1_b.int1_fsm12
3080 | val->fsm_int1_b.int1_fsm13
3081 | val->fsm_int1_b.int1_fsm14
3082 | val->fsm_int1_b.int1_fsm15
3083 | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
3084 {
3085 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3086 }
3087
3088 else
3089 {
3090 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3091 }
3092
3093 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT1_CTRL,
3094 (uint8_t *)&val->int1_ctrl, 1);
3095 }
3096
3097 if (ret == 0)
3098 {
3099 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD1_CFG,
3100 (uint8_t *)&val->md1_cfg, 1);
3101 }
3102
3103 if (ret == 0)
3104 {
3105 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
3106 (uint8_t *) &tap_cfg2, 1);
3107 }
3108
3109 if (ret == 0)
3110 {
3111 ret = lsm6dso32_pin_int2_route_get(ctx, &pin_int2_route);
3112 }
3113
3114 if (ret == 0)
3115 {
3116 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3117 | pin_int2_route.int2_ctrl.int2_drdy_g
3118 | pin_int2_route.int2_ctrl.int2_drdy_temp
3119 | pin_int2_route.int2_ctrl.int2_drdy_xl
3120 | pin_int2_route.int2_ctrl.int2_fifo_full
3121 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3122 | pin_int2_route.int2_ctrl.int2_fifo_th
3123 | pin_int2_route.md2_cfg.int2_6d
3124 | pin_int2_route.md2_cfg.int2_double_tap
3125 | pin_int2_route.md2_cfg.int2_ff
3126 | pin_int2_route.md2_cfg.int2_wu
3127 | pin_int2_route.md2_cfg.int2_single_tap
3128 | pin_int2_route.md2_cfg.int2_sleep_change
3129 | val->int1_ctrl.den_drdy_flag
3130 | val->int1_ctrl.int1_boot
3131 | val->int1_ctrl.int1_cnt_bdr
3132 | val->int1_ctrl.int1_drdy_g
3133 | val->int1_ctrl.int1_drdy_xl
3134 | val->int1_ctrl.int1_fifo_full
3135 | val->int1_ctrl.int1_fifo_ovr
3136 | val->int1_ctrl.int1_fifo_th
3137 | val->md1_cfg.int1_6d
3138 | val->md1_cfg.int1_double_tap
3139 | val->md1_cfg.int1_ff
3140 | val->md1_cfg.int1_wu
3141 | val->md1_cfg.int1_single_tap
3142 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3143 {
3144 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
3145 }
3146
3147 else
3148 {
3149 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
3150 }
3151
3152 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
3153 (uint8_t *) &tap_cfg2, 1);
3154 }
3155
3156 return ret;
3157 }
3158
3159 /**
3160 * @brief Select the signal that need to route on int1 pad.[get]
3161 *
3162 * @param ctx read / write interface definitions
3163 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3164 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3165 * @retval interface status (MANDATORY: return 0 -> no Error)
3166 *
3167 */
lsm6dso32_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dso32_pin_int1_route_t * val)3168 int32_t lsm6dso32_pin_int1_route_get(const stmdev_ctx_t *ctx,
3169 lsm6dso32_pin_int1_route_t *val)
3170 {
3171 int32_t ret;
3172
3173 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3174
3175 if (ret == 0)
3176 {
3177 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
3178 (uint8_t *)&val->emb_func_int1, 1);
3179 }
3180
3181 if (ret == 0)
3182 {
3183 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_A,
3184 (uint8_t *)&val->fsm_int1_a, 1);
3185 }
3186
3187 if (ret == 0)
3188 {
3189 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_B,
3190 (uint8_t *)&val->fsm_int1_b, 1);
3191 }
3192
3193 if (ret == 0)
3194 {
3195 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3196 }
3197
3198 if (ret == 0)
3199 {
3200 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT1_CTRL,
3201 (uint8_t *)&val->int1_ctrl, 1);
3202 }
3203
3204 if (ret == 0)
3205 {
3206 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD1_CFG,
3207 (uint8_t *)&val->md1_cfg, 1);
3208 }
3209
3210 return ret;
3211 }
3212
3213 /**
3214 * @brief Select the signal that need to route on int2 pad.[set]
3215 *
3216 * @param ctx read / write interface definitions
3217 * @param val union of registers INT2_CTRL, MD2_CFG,
3218 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3219 * @retval interface status (MANDATORY: return 0 -> no Error)
3220 *
3221 */
lsm6dso32_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dso32_pin_int2_route_t * val)3222 int32_t lsm6dso32_pin_int2_route_set(const stmdev_ctx_t *ctx,
3223 lsm6dso32_pin_int2_route_t *val)
3224 {
3225 lsm6dso32_pin_int1_route_t pin_int1_route;
3226 lsm6dso32_tap_cfg2_t tap_cfg2;
3227 int32_t ret;
3228
3229 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3230
3231 if (ret == 0)
3232 {
3233 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
3234 (uint8_t *)&val->emb_func_int2, 1);
3235 }
3236
3237 if (ret == 0)
3238 {
3239 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_A,
3240 (uint8_t *)&val->fsm_int2_a, 1);
3241 }
3242
3243 if (ret == 0)
3244 {
3245 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_B,
3246 (uint8_t *)&val->fsm_int2_b, 1);
3247 }
3248
3249 if (ret == 0)
3250 {
3251 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3252 }
3253
3254 if (ret == 0)
3255 {
3256 if ((val->emb_func_int2.int2_fsm_lc
3257 | val->emb_func_int2.int2_sig_mot
3258 | val->emb_func_int2.int2_step_detector
3259 | val->emb_func_int2.int2_tilt
3260 | val->fsm_int2_a.int2_fsm1
3261 | val->fsm_int2_a.int2_fsm2
3262 | val->fsm_int2_a.int2_fsm3
3263 | val->fsm_int2_a.int2_fsm4
3264 | val->fsm_int2_a.int2_fsm5
3265 | val->fsm_int2_a.int2_fsm6
3266 | val->fsm_int2_a.int2_fsm7
3267 | val->fsm_int2_a.int2_fsm8
3268 | val->fsm_int2_b.int2_fsm9
3269 | val->fsm_int2_b.int2_fsm10
3270 | val->fsm_int2_b.int2_fsm11
3271 | val->fsm_int2_b.int2_fsm12
3272 | val->fsm_int2_b.int2_fsm13
3273 | val->fsm_int2_b.int2_fsm14
3274 | val->fsm_int2_b.int2_fsm15
3275 | val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
3276 {
3277 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3278 }
3279
3280 else
3281 {
3282 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3283 }
3284
3285 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT2_CTRL,
3286 (uint8_t *)&val->int2_ctrl, 1);
3287 }
3288
3289 if (ret == 0)
3290 {
3291 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD2_CFG,
3292 (uint8_t *)&val->md2_cfg, 1);
3293 }
3294
3295 if (ret == 0)
3296 {
3297 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
3298 (uint8_t *) &tap_cfg2, 1);
3299 }
3300
3301 if (ret == 0)
3302 {
3303 ret = lsm6dso32_pin_int1_route_get(ctx, &pin_int1_route);
3304 }
3305
3306 if (ret == 0)
3307 {
3308 if ((val->int2_ctrl.int2_cnt_bdr
3309 | val->int2_ctrl.int2_drdy_g
3310 | val->int2_ctrl.int2_drdy_temp
3311 | val->int2_ctrl.int2_drdy_xl
3312 | val->int2_ctrl.int2_fifo_full
3313 | val->int2_ctrl.int2_fifo_ovr
3314 | val->int2_ctrl.int2_fifo_th
3315 | val->md2_cfg.int2_6d
3316 | val->md2_cfg.int2_double_tap
3317 | val->md2_cfg.int2_ff
3318 | val->md2_cfg.int2_wu
3319 | val->md2_cfg.int2_single_tap
3320 | val->md2_cfg.int2_sleep_change
3321 | pin_int1_route.int1_ctrl.den_drdy_flag
3322 | pin_int1_route.int1_ctrl.int1_boot
3323 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3324 | pin_int1_route.int1_ctrl.int1_drdy_g
3325 | pin_int1_route.int1_ctrl.int1_drdy_xl
3326 | pin_int1_route.int1_ctrl.int1_fifo_full
3327 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3328 | pin_int1_route.int1_ctrl.int1_fifo_th
3329 | pin_int1_route.md1_cfg.int1_6d
3330 | pin_int1_route.md1_cfg.int1_double_tap
3331 | pin_int1_route.md1_cfg.int1_ff
3332 | pin_int1_route.md1_cfg.int1_wu
3333 | pin_int1_route.md1_cfg.int1_single_tap
3334 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3335 {
3336 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
3337 }
3338
3339 else
3340 {
3341 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
3342 }
3343
3344 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
3345 (uint8_t *) &tap_cfg2, 1);
3346 }
3347
3348 return ret;
3349 }
3350
3351 /**
3352 * @brief Select the signal that need to route on int2 pad.[get]
3353 *
3354 * @param ctx read / write interface definitions
3355 * @param val union of registers INT2_CTRL, MD2_CFG,
3356 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3357 * @retval interface status (MANDATORY: return 0 -> no Error)
3358 *
3359 */
lsm6dso32_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dso32_pin_int2_route_t * val)3360 int32_t lsm6dso32_pin_int2_route_get(const stmdev_ctx_t *ctx,
3361 lsm6dso32_pin_int2_route_t *val)
3362 {
3363 int32_t ret;
3364
3365 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3366
3367 if (ret == 0)
3368 {
3369 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
3370 (uint8_t *)&val->emb_func_int2, 1);
3371 }
3372
3373 if (ret == 0)
3374 {
3375 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_A,
3376 (uint8_t *)&val->fsm_int2_a, 1);
3377 }
3378
3379 if (ret == 0)
3380 {
3381 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_B,
3382 (uint8_t *)&val->fsm_int2_b, 1);
3383 }
3384
3385 if (ret == 0)
3386 {
3387 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3388 }
3389
3390 if (ret == 0)
3391 {
3392 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT2_CTRL,
3393 (uint8_t *)&val->int2_ctrl, 1);
3394 }
3395
3396 if (ret == 0)
3397 {
3398 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD2_CFG,
3399 (uint8_t *)&val->md2_cfg, 1);
3400 }
3401
3402 return ret;
3403 }
3404
3405 /**
3406 * @brief Push-pull/open drain selection on interrupt pads.[set]
3407 *
3408 * @param ctx read / write interface definitions
3409 * @param val change the values of pp_od in reg CTRL3_C
3410 * @retval interface status (MANDATORY: return 0 -> no Error)
3411 *
3412 */
lsm6dso32_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_pp_od_t val)3413 int32_t lsm6dso32_pin_mode_set(const stmdev_ctx_t *ctx,
3414 lsm6dso32_pp_od_t val)
3415 {
3416 lsm6dso32_ctrl3_c_t reg;
3417 int32_t ret;
3418
3419 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3420
3421 if (ret == 0)
3422 {
3423 reg.pp_od = (uint8_t)val;
3424 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3425 }
3426
3427 return ret;
3428 }
3429
3430 /**
3431 * @brief Push-pull/open drain selection on interrupt pads.[get]
3432 *
3433 * @param ctx read / write interface definitions
3434 * @param val Get the values of pp_od in reg CTRL3_C
3435 * @retval interface status (MANDATORY: return 0 -> no Error)
3436 *
3437 */
lsm6dso32_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_pp_od_t * val)3438 int32_t lsm6dso32_pin_mode_get(const stmdev_ctx_t *ctx,
3439 lsm6dso32_pp_od_t *val)
3440 {
3441 lsm6dso32_ctrl3_c_t reg;
3442 int32_t ret;
3443
3444 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3445
3446 switch (reg.pp_od)
3447 {
3448 case LSM6DSO32_PUSH_PULL:
3449 *val = LSM6DSO32_PUSH_PULL;
3450 break;
3451
3452 case LSM6DSO32_OPEN_DRAIN:
3453 *val = LSM6DSO32_OPEN_DRAIN;
3454 break;
3455
3456 default:
3457 *val = LSM6DSO32_PUSH_PULL;
3458 break;
3459 }
3460
3461 return ret;
3462 }
3463
3464 /**
3465 * @brief Interrupt active-high/low.[set]
3466 *
3467 * @param ctx read / write interface definitions
3468 * @param val change the values of h_lactive in reg CTRL3_C
3469 * @retval interface status (MANDATORY: return 0 -> no Error)
3470 *
3471 */
lsm6dso32_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dso32_h_lactive_t val)3472 int32_t lsm6dso32_pin_polarity_set(const stmdev_ctx_t *ctx,
3473 lsm6dso32_h_lactive_t val)
3474 {
3475 lsm6dso32_ctrl3_c_t reg;
3476 int32_t ret;
3477
3478 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3479
3480 if (ret == 0)
3481 {
3482 reg.h_lactive = (uint8_t)val;
3483 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3484 }
3485
3486 return ret;
3487 }
3488
3489 /**
3490 * @brief Interrupt active-high/low.[get]
3491 *
3492 * @param ctx read / write interface definitions
3493 * @param val Get the values of h_lactive in reg CTRL3_C
3494 * @retval interface status (MANDATORY: return 0 -> no Error)
3495 *
3496 */
lsm6dso32_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dso32_h_lactive_t * val)3497 int32_t lsm6dso32_pin_polarity_get(const stmdev_ctx_t *ctx,
3498 lsm6dso32_h_lactive_t *val)
3499 {
3500 lsm6dso32_ctrl3_c_t reg;
3501 int32_t ret;
3502
3503 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3504
3505 switch (reg.h_lactive)
3506 {
3507 case LSM6DSO32_ACTIVE_HIGH:
3508 *val = LSM6DSO32_ACTIVE_HIGH;
3509 break;
3510
3511 case LSM6DSO32_ACTIVE_LOW:
3512 *val = LSM6DSO32_ACTIVE_LOW;
3513 break;
3514
3515 default:
3516 *val = LSM6DSO32_ACTIVE_HIGH;
3517 break;
3518 }
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @brief All interrupt signals become available on INT1 pin.[set]
3525 *
3526 * @param ctx read / write interface definitions
3527 * @param val change the values of int2_on_int1 in reg CTRL4_C
3528 * @retval interface status (MANDATORY: return 0 -> no Error)
3529 *
3530 */
lsm6dso32_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3531 int32_t lsm6dso32_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3532 {
3533 lsm6dso32_ctrl4_c_t reg;
3534 int32_t ret;
3535
3536 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3537
3538 if (ret == 0)
3539 {
3540 reg.int2_on_int1 = val;
3541 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3542 }
3543
3544 return ret;
3545 }
3546
3547 /**
3548 * @brief All interrupt signals become available on INT1 pin.[get]
3549 *
3550 * @param ctx read / write interface definitions
3551 * @param val change the values of int2_on_int1 in reg CTRL4_C
3552 * @retval interface status (MANDATORY: return 0 -> no Error)
3553 *
3554 */
lsm6dso32_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3555 int32_t lsm6dso32_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3556 {
3557 lsm6dso32_ctrl4_c_t reg;
3558 int32_t ret;
3559
3560 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3561 *val = reg.int2_on_int1;
3562
3563 return ret;
3564 }
3565
3566 /**
3567 * @brief Interrupt notification mode.[set]
3568 *
3569 * @param ctx read / write interface definitions
3570 * @param val change the values of lir in reg TAP_CFG0
3571 * @retval interface status (MANDATORY: return 0 -> no Error)
3572 *
3573 */
lsm6dso32_int_notification_set(const stmdev_ctx_t * ctx,lsm6dso32_lir_t val)3574 int32_t lsm6dso32_int_notification_set(const stmdev_ctx_t *ctx,
3575 lsm6dso32_lir_t val)
3576 {
3577 lsm6dso32_tap_cfg0_t tap_cfg0;
3578 lsm6dso32_page_rw_t page_rw;
3579 int32_t ret;
3580
3581 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
3582 (uint8_t *) &tap_cfg0, 1);
3583
3584 if (ret == 0)
3585 {
3586 tap_cfg0.lir = (uint8_t)val & 0x01U;
3587 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3588 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0,
3589 (uint8_t *) &tap_cfg0, 1);
3590 }
3591
3592 if (ret == 0)
3593 {
3594 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3595 }
3596
3597 if (ret == 0)
3598 {
3599 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3600 }
3601
3602 if (ret == 0)
3603 {
3604 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3605 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
3606 (uint8_t *) &page_rw, 1);
3607 }
3608
3609 if (ret == 0)
3610 {
3611 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3612 }
3613
3614 return ret;
3615 }
3616
3617 /**
3618 * @brief Interrupt notification mode.[get]
3619 *
3620 * @param ctx read / write interface definitions
3621 * @param val Get the values of lir in reg TAP_CFG0
3622 * @retval interface status (MANDATORY: return 0 -> no Error)
3623 *
3624 */
lsm6dso32_int_notification_get(const stmdev_ctx_t * ctx,lsm6dso32_lir_t * val)3625 int32_t lsm6dso32_int_notification_get(const stmdev_ctx_t *ctx,
3626 lsm6dso32_lir_t *val)
3627 {
3628 lsm6dso32_tap_cfg0_t tap_cfg0;
3629 lsm6dso32_page_rw_t page_rw;
3630 int32_t ret;
3631
3632 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
3633 (uint8_t *) &tap_cfg0, 1);
3634
3635 if (ret == 0)
3636 {
3637 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3638 }
3639
3640 if (ret == 0)
3641 {
3642 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3643 }
3644
3645 if (ret == 0)
3646 {
3647 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3648 }
3649
3650 if (ret == 0)
3651 {
3652 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
3653 {
3654 case LSM6DSO32_ALL_INT_PULSED:
3655 *val = LSM6DSO32_ALL_INT_PULSED;
3656 break;
3657
3658 case LSM6DSO32_BASE_LATCHED_EMB_PULSED:
3659 *val = LSM6DSO32_BASE_LATCHED_EMB_PULSED;
3660 break;
3661
3662 case LSM6DSO32_BASE_PULSED_EMB_LATCHED:
3663 *val = LSM6DSO32_BASE_PULSED_EMB_LATCHED;
3664 break;
3665
3666 case LSM6DSO32_ALL_INT_LATCHED:
3667 *val = LSM6DSO32_ALL_INT_LATCHED;
3668 break;
3669
3670 default:
3671 *val = LSM6DSO32_ALL_INT_PULSED;
3672 break;
3673 }
3674
3675 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3676 }
3677
3678 if (ret == 0)
3679 {
3680 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3681 }
3682
3683 if (ret == 0)
3684 {
3685 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3686 }
3687
3688 return ret;
3689 }
3690
3691 /**
3692 * @}
3693 *
3694 */
3695
3696 /**
3697 * @defgroup LSM6DSO32_Wake_Up_event
3698 * @brief This section groups all the functions that manage the Wake Up
3699 * event generation.
3700 * @{
3701 *
3702 */
3703
3704 /**
3705 * @brief Weight of 1 LSB of wakeup threshold.[set]
3706 * 0: 1 LSB =FS_XL / 64
3707 * 1: 1 LSB = FS_XL / 256
3708 *
3709 * @param ctx read / write interface definitions
3710 * @param val change the values of wake_ths_w in
3711 * reg WAKE_UP_DUR
3712 * @retval interface status (MANDATORY: return 0 -> no Error)
3713 *
3714 */
lsm6dso32_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dso32_wake_ths_w_t val)3715 int32_t lsm6dso32_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
3716 lsm6dso32_wake_ths_w_t val)
3717 {
3718 lsm6dso32_wake_up_dur_t reg;
3719 int32_t ret;
3720
3721 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3722
3723 if (ret == 0)
3724 {
3725 reg.wake_ths_w = (uint8_t)val;
3726 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3727 }
3728
3729 return ret;
3730 }
3731
3732 /**
3733 * @brief Weight of 1 LSB of wakeup threshold.[get]
3734 * 0: 1 LSB =FS_XL / 64
3735 * 1: 1 LSB = FS_XL / 256
3736 *
3737 * @param ctx read / write interface definitions
3738 * @param val Get the values of wake_ths_w in
3739 * reg WAKE_UP_DUR
3740 * @retval interface status (MANDATORY: return 0 -> no Error)
3741 *
3742 */
lsm6dso32_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dso32_wake_ths_w_t * val)3743 int32_t lsm6dso32_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
3744 lsm6dso32_wake_ths_w_t *val)
3745 {
3746 lsm6dso32_wake_up_dur_t reg;
3747 int32_t ret;
3748
3749 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3750
3751 switch (reg.wake_ths_w)
3752 {
3753 case LSM6DSO32_LSb_FS_DIV_64:
3754 *val = LSM6DSO32_LSb_FS_DIV_64;
3755 break;
3756
3757 case LSM6DSO32_LSb_FS_DIV_256:
3758 *val = LSM6DSO32_LSb_FS_DIV_256;
3759 break;
3760
3761 default:
3762 *val = LSM6DSO32_LSb_FS_DIV_64;
3763 break;
3764 }
3765
3766 return ret;
3767 }
3768
3769 /**
3770 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3771 * WAKE_UP_DUR.[set]
3772 *
3773 * @param ctx read / write interface definitions
3774 * @param val change the values of wk_ths in reg WAKE_UP_THS
3775 * @retval interface status (MANDATORY: return 0 -> no Error)
3776 *
3777 */
lsm6dso32_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3778 int32_t lsm6dso32_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3779 {
3780 lsm6dso32_wake_up_ths_t reg;
3781 int32_t ret;
3782
3783 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3784
3785 if (ret == 0)
3786 {
3787 reg.wk_ths = val;
3788 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3789 }
3790
3791 return ret;
3792 }
3793
3794 /**
3795 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3796 * WAKE_UP_DUR.[get]
3797 *
3798 * @param ctx read / write interface definitions
3799 * @param val change the values of wk_ths in reg WAKE_UP_THS
3800 * @retval interface status (MANDATORY: return 0 -> no Error)
3801 *
3802 */
lsm6dso32_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3803 int32_t lsm6dso32_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3804 {
3805 lsm6dso32_wake_up_ths_t reg;
3806 int32_t ret;
3807
3808 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3809 *val = reg.wk_ths;
3810
3811 return ret;
3812 }
3813
3814 /**
3815 * @brief Wake up duration event.[set]
3816 * 1LSb = 1 / ODR
3817 *
3818 * @param ctx read / write interface definitions
3819 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3820 * @retval interface status (MANDATORY: return 0 -> no Error)
3821 *
3822 */
lsm6dso32_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)3823 int32_t lsm6dso32_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
3824 uint8_t val)
3825 {
3826 lsm6dso32_wake_up_ths_t reg;
3827 int32_t ret;
3828
3829 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3830
3831 if (ret == 0)
3832 {
3833 reg.usr_off_on_wu = val;
3834 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3835 }
3836
3837 return ret;
3838 }
3839
3840 /**
3841 * @brief Wake up duration event.[get]
3842 * 1LSb = 1 / ODR
3843 *
3844 * @param ctx read / write interface definitions
3845 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3846 * @retval interface status (MANDATORY: return 0 -> no Error)
3847 *
3848 */
lsm6dso32_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)3849 int32_t lsm6dso32_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
3850 uint8_t *val)
3851 {
3852 lsm6dso32_wake_up_ths_t reg;
3853 int32_t ret;
3854
3855 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3856 *val = reg.usr_off_on_wu;
3857
3858 return ret;
3859 }
3860
3861 /**
3862 * @brief Wake up duration event.[set]
3863 * 1LSb = 1 / ODR
3864 *
3865 * @param ctx read / write interface definitions
3866 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3867 * @retval interface status (MANDATORY: return 0 -> no Error)
3868 *
3869 */
lsm6dso32_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3870 int32_t lsm6dso32_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3871 {
3872 lsm6dso32_wake_up_dur_t reg;
3873 int32_t ret;
3874
3875 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3876
3877 if (ret == 0)
3878 {
3879 reg.wake_dur = val;
3880 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3881 }
3882
3883 return ret;
3884 }
3885
3886 /**
3887 * @brief Wake up duration event.[get]
3888 * 1LSb = 1 / ODR
3889 *
3890 * @param ctx read / write interface definitions
3891 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3892 * @retval interface status (MANDATORY: return 0 -> no Error)
3893 *
3894 */
lsm6dso32_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3895 int32_t lsm6dso32_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3896 {
3897 lsm6dso32_wake_up_dur_t reg;
3898 int32_t ret;
3899
3900 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3901 *val = reg.wake_dur;
3902
3903 return ret;
3904 }
3905
3906 /**
3907 * @}
3908 *
3909 */
3910
3911 /**
3912 * @defgroup LSM6DSO32_ Activity/Inactivity_detection
3913 * @brief This section groups all the functions concerning
3914 * activity/inactivity detection.
3915 * @{
3916 *
3917 */
3918
3919 /**
3920 * @brief Enables gyroscope Sleep mode.[set]
3921 *
3922 * @param ctx read / write interface definitions
3923 * @param val change the values of sleep_g in reg CTRL4_C
3924 * @retval interface status (MANDATORY: return 0 -> no Error)
3925 *
3926 */
lsm6dso32_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)3927 int32_t lsm6dso32_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
3928 {
3929 lsm6dso32_ctrl4_c_t reg;
3930 int32_t ret;
3931
3932 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3933
3934 if (ret == 0)
3935 {
3936 reg.sleep_g = val;
3937 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3938 }
3939
3940 return ret;
3941 }
3942
3943 /**
3944 * @brief Enables gyroscope Sleep mode.[get]
3945 *
3946 * @param ctx read / write interface definitions
3947 * @param val change the values of sleep_g in reg CTRL4_C
3948 * @retval interface status (MANDATORY: return 0 -> no Error)
3949 *
3950 */
lsm6dso32_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)3951 int32_t lsm6dso32_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
3952 {
3953 lsm6dso32_ctrl4_c_t reg;
3954 int32_t ret;
3955
3956 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3957 *val = reg.sleep_g;
3958
3959 return ret;
3960 }
3961
3962 /**
3963 * @brief Drives the sleep status instead of
3964 * sleep change on INT pins
3965 * (only if INT1_SLEEP_CHANGE or
3966 * INT2_SLEEP_CHANGE bits are enabled).[set]
3967 *
3968 * @param ctx read / write interface definitions
3969 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
3970 * @retval interface status (MANDATORY: return 0 -> no Error)
3971 *
3972 */
lsm6dso32_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dso32_sleep_status_on_int_t val)3973 int32_t lsm6dso32_act_pin_notification_set(const stmdev_ctx_t *ctx,
3974 lsm6dso32_sleep_status_on_int_t val)
3975 {
3976 lsm6dso32_tap_cfg0_t reg;
3977 int32_t ret;
3978
3979 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
3980
3981 if (ret == 0)
3982 {
3983 reg.sleep_status_on_int = (uint8_t)val;
3984 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
3985 }
3986
3987 return ret;
3988 }
3989
3990 /**
3991 * @brief Drives the sleep status instead of
3992 * sleep change on INT pins (only if
3993 * INT1_SLEEP_CHANGE or
3994 * INT2_SLEEP_CHANGE bits are enabled).[get]
3995 *
3996 * @param ctx read / write interface definitions
3997 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
3998 * @retval interface status (MANDATORY: return 0 -> no Error)
3999 *
4000 */
lsm6dso32_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dso32_sleep_status_on_int_t * val)4001 int32_t lsm6dso32_act_pin_notification_get(const stmdev_ctx_t *ctx,
4002 lsm6dso32_sleep_status_on_int_t *val)
4003 {
4004 lsm6dso32_tap_cfg0_t reg;
4005 int32_t ret;
4006
4007 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4008
4009 switch (reg.sleep_status_on_int)
4010 {
4011 case LSM6DSO32_DRIVE_SLEEP_CHG_EVENT:
4012 *val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
4013 break;
4014
4015 case LSM6DSO32_DRIVE_SLEEP_STATUS:
4016 *val = LSM6DSO32_DRIVE_SLEEP_STATUS;
4017 break;
4018
4019 default:
4020 *val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
4021 break;
4022 }
4023
4024 return ret;
4025 }
4026
4027 /**
4028 * @brief Enable inactivity function.[set]
4029 *
4030 * @param ctx read / write interface definitions
4031 * @param val change the values of inact_en in reg TAP_CFG2
4032 * @retval interface status (MANDATORY: return 0 -> no Error)
4033 *
4034 */
lsm6dso32_act_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_inact_en_t val)4035 int32_t lsm6dso32_act_mode_set(const stmdev_ctx_t *ctx,
4036 lsm6dso32_inact_en_t val)
4037 {
4038 lsm6dso32_tap_cfg2_t reg;
4039 int32_t ret;
4040
4041 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4042
4043 if (ret == 0)
4044 {
4045 reg.inact_en = (uint8_t)val;
4046 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4047 }
4048
4049 return ret;
4050 }
4051
4052 /**
4053 * @brief Enable inactivity function.[get]
4054 *
4055 * @param ctx read / write interface definitions
4056 * @param val Get the values of inact_en in reg TAP_CFG2
4057 * @retval interface status (MANDATORY: return 0 -> no Error)
4058 *
4059 */
lsm6dso32_act_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_inact_en_t * val)4060 int32_t lsm6dso32_act_mode_get(const stmdev_ctx_t *ctx,
4061 lsm6dso32_inact_en_t *val)
4062 {
4063 lsm6dso32_tap_cfg2_t reg;
4064 int32_t ret;
4065
4066 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4067
4068 switch (reg.inact_en)
4069 {
4070 case LSM6DSO32_XL_AND_GY_NOT_AFFECTED:
4071 *val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
4072 break;
4073
4074 case LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED:
4075 *val = LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED;
4076 break;
4077
4078 case LSM6DSO32_XL_12Hz5_GY_SLEEP:
4079 *val = LSM6DSO32_XL_12Hz5_GY_SLEEP;
4080 break;
4081
4082 case LSM6DSO32_XL_12Hz5_GY_PD:
4083 *val = LSM6DSO32_XL_12Hz5_GY_PD;
4084 break;
4085
4086 default:
4087 *val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
4088 break;
4089 }
4090
4091 return ret;
4092 }
4093
4094 /**
4095 * @brief Duration to go in sleep mode.[set]
4096 * 1 LSb = 512 / ODR
4097 *
4098 * @param ctx read / write interface definitions
4099 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4100 * @retval interface status (MANDATORY: return 0 -> no Error)
4101 *
4102 */
lsm6dso32_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4103 int32_t lsm6dso32_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4104 {
4105 lsm6dso32_wake_up_dur_t reg;
4106 int32_t ret;
4107
4108 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4109
4110 if (ret == 0)
4111 {
4112 reg.sleep_dur = val;
4113 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4114 }
4115
4116 return ret;
4117 }
4118
4119 /**
4120 * @brief Duration to go in sleep mode.[get]
4121 * 1 LSb = 512 / ODR
4122 *
4123 * @param ctx read / write interface definitions
4124 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4125 * @retval interface status (MANDATORY: return 0 -> no Error)
4126 *
4127 */
lsm6dso32_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4128 int32_t lsm6dso32_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4129 {
4130 lsm6dso32_wake_up_dur_t reg;
4131 int32_t ret;
4132
4133 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4134 *val = reg.sleep_dur;
4135
4136 return ret;
4137 }
4138
4139 /**
4140 * @}
4141 *
4142 */
4143
4144 /**
4145 * @defgroup LSM6DSO32_tap_generator
4146 * @brief This section groups all the functions that manage the
4147 * tap and double tap event generation.
4148 * @{
4149 *
4150 */
4151
4152 /**
4153 * @brief Enable Z direction in tap recognition.[set]
4154 *
4155 * @param ctx read / write interface definitions
4156 * @param val change the values of tap_z_en in reg TAP_CFG0
4157 * @retval interface status (MANDATORY: return 0 -> no Error)
4158 *
4159 */
lsm6dso32_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)4160 int32_t lsm6dso32_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
4161 uint8_t val)
4162 {
4163 lsm6dso32_tap_cfg0_t reg;
4164 int32_t ret;
4165
4166 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4167
4168 if (ret == 0)
4169 {
4170 reg.tap_z_en = val;
4171 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4172 }
4173
4174 return ret;
4175 }
4176
4177 /**
4178 * @brief Enable Z direction in tap recognition.[get]
4179 *
4180 * @param ctx read / write interface definitions
4181 * @param val change the values of tap_z_en in reg TAP_CFG0
4182 * @retval interface status (MANDATORY: return 0 -> no Error)
4183 *
4184 */
lsm6dso32_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4185 int32_t lsm6dso32_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
4186 uint8_t *val)
4187 {
4188 lsm6dso32_tap_cfg0_t reg;
4189 int32_t ret;
4190
4191 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4192 *val = reg.tap_z_en;
4193
4194 return ret;
4195 }
4196
4197 /**
4198 * @brief Enable Y direction in tap recognition.[set]
4199 *
4200 * @param ctx read / write interface definitions
4201 * @param val change the values of tap_y_en in reg TAP_CFG0
4202 * @retval interface status (MANDATORY: return 0 -> no Error)
4203 *
4204 */
lsm6dso32_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)4205 int32_t lsm6dso32_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
4206 uint8_t val)
4207 {
4208 lsm6dso32_tap_cfg0_t reg;
4209 int32_t ret;
4210
4211 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4212
4213 if (ret == 0)
4214 {
4215 reg.tap_y_en = val;
4216 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4217 }
4218
4219 return ret;
4220 }
4221
4222 /**
4223 * @brief Enable Y direction in tap recognition.[get]
4224 *
4225 * @param ctx read / write interface definitions
4226 * @param val change the values of tap_y_en in reg TAP_CFG0
4227 * @retval interface status (MANDATORY: return 0 -> no Error)
4228 *
4229 */
lsm6dso32_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4230 int32_t lsm6dso32_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
4231 uint8_t *val)
4232 {
4233 lsm6dso32_tap_cfg0_t reg;
4234 int32_t ret;
4235
4236 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4237 *val = reg.tap_y_en;
4238
4239 return ret;
4240 }
4241
4242 /**
4243 * @brief Enable X direction in tap recognition.[set]
4244 *
4245 * @param ctx read / write interface definitions
4246 * @param val change the values of tap_x_en in reg TAP_CFG0
4247 * @retval interface status (MANDATORY: return 0 -> no Error)
4248 *
4249 */
lsm6dso32_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)4250 int32_t lsm6dso32_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
4251 uint8_t val)
4252 {
4253 lsm6dso32_tap_cfg0_t reg;
4254 int32_t ret;
4255
4256 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4257
4258 if (ret == 0)
4259 {
4260 reg.tap_x_en = val;
4261 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4262 }
4263
4264 return ret;
4265 }
4266
4267 /**
4268 * @brief Enable X direction in tap recognition.[get]
4269 *
4270 * @param ctx read / write interface definitions
4271 * @param val change the values of tap_x_en in reg TAP_CFG0
4272 * @retval interface status (MANDATORY: return 0 -> no Error)
4273 *
4274 */
lsm6dso32_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4275 int32_t lsm6dso32_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
4276 uint8_t *val)
4277 {
4278 lsm6dso32_tap_cfg0_t reg;
4279 int32_t ret;
4280
4281 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4282 *val = reg.tap_x_en;
4283
4284 return ret;
4285 }
4286
4287 /**
4288 * @brief X-axis tap recognition threshold.[set]
4289 *
4290 * @param ctx read / write interface definitions
4291 * @param val change the values of tap_ths_x in reg TAP_CFG1
4292 * @retval interface status (MANDATORY: return 0 -> no Error)
4293 *
4294 */
lsm6dso32_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)4295 int32_t lsm6dso32_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
4296 {
4297 lsm6dso32_tap_cfg1_t reg;
4298 int32_t ret;
4299
4300 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4301
4302 if (ret == 0)
4303 {
4304 reg.tap_ths_x = val;
4305 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4306 }
4307
4308 return ret;
4309 }
4310
4311 /**
4312 * @brief X-axis tap recognition threshold.[get]
4313 *
4314 * @param ctx read / write interface definitions
4315 * @param val change the values of tap_ths_x in reg TAP_CFG1
4316 * @retval interface status (MANDATORY: return 0 -> no Error)
4317 *
4318 */
lsm6dso32_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4319 int32_t lsm6dso32_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
4320 {
4321 lsm6dso32_tap_cfg1_t reg;
4322 int32_t ret;
4323
4324 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4325 *val = reg.tap_ths_x;
4326
4327 return ret;
4328 }
4329
4330 /**
4331 * @brief Selection of axis priority for TAP detection.[set]
4332 *
4333 * @param ctx read / write interface definitions
4334 * @param val change the values of tap_priority in reg TAP_CFG1
4335 * @retval interface status (MANDATORY: return 0 -> no Error)
4336 *
4337 */
lsm6dso32_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dso32_tap_priority_t val)4338 int32_t lsm6dso32_tap_axis_priority_set(const stmdev_ctx_t *ctx,
4339 lsm6dso32_tap_priority_t val)
4340 {
4341 lsm6dso32_tap_cfg1_t reg;
4342 int32_t ret;
4343
4344 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4345
4346 if (ret == 0)
4347 {
4348 reg.tap_priority = (uint8_t)val;
4349 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4350 }
4351
4352 return ret;
4353 }
4354
4355 /**
4356 * @brief Selection of axis priority for TAP detection.[get]
4357 *
4358 * @param ctx read / write interface definitions
4359 * @param val Get the values of tap_priority in reg TAP_CFG1
4360 * @retval interface status (MANDATORY: return 0 -> no Error)
4361 *
4362 */
lsm6dso32_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dso32_tap_priority_t * val)4363 int32_t lsm6dso32_tap_axis_priority_get(const stmdev_ctx_t *ctx,
4364 lsm6dso32_tap_priority_t *val)
4365 {
4366 lsm6dso32_tap_cfg1_t reg;
4367 int32_t ret;
4368
4369 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4370
4371 switch (reg.tap_priority)
4372 {
4373 case LSM6DSO32_XYZ:
4374 *val = LSM6DSO32_XYZ;
4375 break;
4376
4377 case LSM6DSO32_YXZ:
4378 *val = LSM6DSO32_YXZ;
4379 break;
4380
4381 case LSM6DSO32_XZY:
4382 *val = LSM6DSO32_XZY;
4383 break;
4384
4385 case LSM6DSO32_ZYX:
4386 *val = LSM6DSO32_ZYX;
4387 break;
4388
4389 case LSM6DSO32_YZX:
4390 *val = LSM6DSO32_YZX;
4391 break;
4392
4393 case LSM6DSO32_ZXY:
4394 *val = LSM6DSO32_ZXY;
4395 break;
4396
4397 default:
4398 *val = LSM6DSO32_XYZ;
4399 break;
4400 }
4401
4402 return ret;
4403 }
4404
4405 /**
4406 * @brief Y-axis tap recognition threshold.[set]
4407 *
4408 * @param ctx read / write interface definitions
4409 * @param val change the values of tap_ths_y in reg TAP_CFG2
4410 * @retval interface status (MANDATORY: return 0 -> no Error)
4411 *
4412 */
lsm6dso32_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)4413 int32_t lsm6dso32_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
4414 {
4415 lsm6dso32_tap_cfg2_t reg;
4416 int32_t ret;
4417
4418 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4419
4420 if (ret == 0)
4421 {
4422 reg.tap_ths_y = val;
4423 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4424 }
4425
4426 return ret;
4427 }
4428
4429 /**
4430 * @brief Y-axis tap recognition threshold.[get]
4431 *
4432 * @param ctx read / write interface definitions
4433 * @param val change the values of tap_ths_y in reg TAP_CFG2
4434 * @retval interface status (MANDATORY: return 0 -> no Error)
4435 *
4436 */
lsm6dso32_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4437 int32_t lsm6dso32_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
4438 {
4439 lsm6dso32_tap_cfg2_t reg;
4440 int32_t ret;
4441
4442 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4443 *val = reg.tap_ths_y;
4444
4445 return ret;
4446 }
4447
4448 /**
4449 * @brief Z-axis recognition threshold.[set]
4450 *
4451 * @param ctx read / write interface definitions
4452 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4453 * @retval interface status (MANDATORY: return 0 -> no Error)
4454 *
4455 */
lsm6dso32_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)4456 int32_t lsm6dso32_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
4457 {
4458 lsm6dso32_tap_ths_6d_t reg;
4459 int32_t ret;
4460
4461 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4462
4463 if (ret == 0)
4464 {
4465 reg.tap_ths_z = val;
4466 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4467 }
4468
4469 return ret;
4470 }
4471
4472 /**
4473 * @brief Z-axis recognition threshold.[get]
4474 *
4475 * @param ctx read / write interface definitions
4476 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4477 * @retval interface status (MANDATORY: return 0 -> no Error)
4478 *
4479 */
lsm6dso32_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4480 int32_t lsm6dso32_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
4481 {
4482 lsm6dso32_tap_ths_6d_t reg;
4483 int32_t ret;
4484
4485 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4486 *val = reg.tap_ths_z;
4487
4488 return ret;
4489 }
4490
4491 /**
4492 * @brief Maximum duration is the maximum time of an
4493 * over threshold signal detection to be recognized
4494 * as a tap event. The default value of these bits
4495 * is 00b which corresponds to 4*ODR_XL time.
4496 * If the SHOCK[1:0] bits are set to a different
4497 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4498 *
4499 * @param ctx read / write interface definitions
4500 * @param val change the values of shock in reg INT_DUR2
4501 * @retval interface status (MANDATORY: return 0 -> no Error)
4502 *
4503 */
lsm6dso32_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)4504 int32_t lsm6dso32_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
4505 {
4506 lsm6dso32_int_dur2_t reg;
4507 int32_t ret;
4508
4509 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4510
4511 if (ret == 0)
4512 {
4513 reg.shock = val;
4514 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4515 }
4516
4517 return ret;
4518 }
4519
4520 /**
4521 * @brief Maximum duration is the maximum time of an
4522 * over threshold signal detection to be recognized
4523 * as a tap event. The default value of these bits
4524 * is 00b which corresponds to 4*ODR_XL time.
4525 * If the SHOCK[1:0] bits are set to a different
4526 * value, 1LSB corresponds to 8*ODR_XL time.[get]
4527 *
4528 * @param ctx read / write interface definitions
4529 * @param val change the values of shock in reg INT_DUR2
4530 * @retval interface status (MANDATORY: return 0 -> no Error)
4531 *
4532 */
lsm6dso32_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)4533 int32_t lsm6dso32_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
4534 {
4535 lsm6dso32_int_dur2_t reg;
4536 int32_t ret;
4537
4538 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4539 *val = reg.shock;
4540
4541 return ret;
4542 }
4543
4544 /**
4545 * @brief Quiet time is the time after the first detected
4546 * tap in which there must not be any over threshold
4547 * event.
4548 * The default value of these bits is 00b which
4549 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
4550 * bits are set to a different value,
4551 * 1LSB corresponds to 4*ODR_XL time.[set]
4552 *
4553 * @param ctx read / write interface definitions
4554 * @param val change the values of quiet in reg INT_DUR2
4555 * @retval interface status (MANDATORY: return 0 -> no Error)
4556 *
4557 */
lsm6dso32_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)4558 int32_t lsm6dso32_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
4559 {
4560 lsm6dso32_int_dur2_t reg;
4561 int32_t ret;
4562
4563 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4564
4565 if (ret == 0)
4566 {
4567 reg.quiet = val;
4568 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4569 }
4570
4571 return ret;
4572 }
4573
4574 /**
4575 * @brief Quiet time is the time after the first detected
4576 * tap in which there must not be any over threshold
4577 * event.
4578 * The default value of these bits is 00b which
4579 * corresponds to 2*ODR_XL time.
4580 * If the QUIET[1:0] bits are set to a different
4581 * value, 1LSB corresponds to 4*ODR_XL time.[get]
4582 *
4583 * @param ctx read / write interface definitions
4584 * @param val change the values of quiet in reg INT_DUR2
4585 * @retval interface status (MANDATORY: return 0 -> no Error)
4586 *
4587 */
lsm6dso32_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)4588 int32_t lsm6dso32_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
4589 {
4590 lsm6dso32_int_dur2_t reg;
4591 int32_t ret;
4592
4593 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4594 *val = reg.quiet;
4595
4596 return ret;
4597 }
4598
4599 /**
4600 * @brief When double tap recognition is enabled,
4601 * this register expresses the maximum time
4602 * between two consecutive detected taps to
4603 * determine a double tap event.
4604 * The default value of these bits is 0000b which
4605 * corresponds to 16*ODR_XL time.
4606 * If the DUR[3:0] bits are set to a different value,
4607 * 1LSB corresponds to 32*ODR_XL time.[set]
4608 *
4609 * @param ctx read / write interface definitions
4610 * @param val change the values of dur in reg INT_DUR2
4611 * @retval interface status (MANDATORY: return 0 -> no Error)
4612 *
4613 */
lsm6dso32_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4614 int32_t lsm6dso32_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4615 {
4616 lsm6dso32_int_dur2_t reg;
4617 int32_t ret;
4618
4619 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4620
4621 if (ret == 0)
4622 {
4623 reg.dur = val;
4624 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4625 }
4626
4627 return ret;
4628 }
4629
4630 /**
4631 * @brief When double tap recognition is enabled,
4632 * this register expresses the maximum time
4633 * between two consecutive detected taps to
4634 * determine a double tap event.
4635 * The default value of these bits is 0000b which
4636 * corresponds to 16*ODR_XL time. If the DUR[3:0]
4637 * bits are set to a different value,
4638 * 1LSB corresponds to 32*ODR_XL time.[get]
4639 *
4640 * @param ctx read / write interface definitions
4641 * @param val change the values of dur in reg INT_DUR2
4642 * @retval interface status (MANDATORY: return 0 -> no Error)
4643 *
4644 */
lsm6dso32_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4645 int32_t lsm6dso32_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4646 {
4647 lsm6dso32_int_dur2_t reg;
4648 int32_t ret;
4649
4650 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4651 *val = reg.dur;
4652
4653 return ret;
4654 }
4655
4656 /**
4657 * @brief Single/double-tap event enable.[set]
4658 *
4659 * @param ctx read / write interface definitions
4660 * @param val change the values of single_double_tap in reg WAKE_UP_THS
4661 * @retval interface status (MANDATORY: return 0 -> no Error)
4662 *
4663 */
lsm6dso32_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_single_double_tap_t val)4664 int32_t lsm6dso32_tap_mode_set(const stmdev_ctx_t *ctx,
4665 lsm6dso32_single_double_tap_t val)
4666 {
4667 lsm6dso32_wake_up_ths_t reg;
4668 int32_t ret;
4669
4670 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4671
4672 if (ret == 0)
4673 {
4674 reg.single_double_tap = (uint8_t)val;
4675 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4676 }
4677
4678 return ret;
4679 }
4680
4681 /**
4682 * @brief Single/double-tap event enable.[get]
4683 *
4684 * @param ctx read / write interface definitions
4685 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
4686 * @retval interface status (MANDATORY: return 0 -> no Error)
4687 *
4688 */
lsm6dso32_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_single_double_tap_t * val)4689 int32_t lsm6dso32_tap_mode_get(const stmdev_ctx_t *ctx,
4690 lsm6dso32_single_double_tap_t *val)
4691 {
4692 lsm6dso32_wake_up_ths_t reg;
4693 int32_t ret;
4694
4695 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4696
4697 switch (reg.single_double_tap)
4698 {
4699 case LSM6DSO32_ONLY_SINGLE:
4700 *val = LSM6DSO32_ONLY_SINGLE;
4701 break;
4702
4703 case LSM6DSO32_BOTH_SINGLE_DOUBLE:
4704 *val = LSM6DSO32_BOTH_SINGLE_DOUBLE;
4705 break;
4706
4707 default:
4708 *val = LSM6DSO32_ONLY_SINGLE;
4709 break;
4710 }
4711
4712 return ret;
4713 }
4714
4715 /**
4716 * @}
4717 *
4718 */
4719
4720 /**
4721 * @defgroup LSM6DSO32_ Six_position_detection(6D/4D)
4722 * @brief This section groups all the functions concerning six position
4723 * detection (6D).
4724 * @{
4725 *
4726 */
4727
4728 /**
4729 * @brief Threshold for 4D/6D function.[set]
4730 *
4731 * @param ctx read / write interface definitions
4732 * @param val change the values of sixd_ths in reg TAP_THS_6D
4733 * @retval interface status (MANDATORY: return 0 -> no Error)
4734 *
4735 */
lsm6dso32_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dso32_sixd_ths_t val)4736 int32_t lsm6dso32_6d_threshold_set(const stmdev_ctx_t *ctx,
4737 lsm6dso32_sixd_ths_t val)
4738 {
4739 lsm6dso32_tap_ths_6d_t reg;
4740 int32_t ret;
4741
4742 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4743
4744 if (ret == 0)
4745 {
4746 reg.sixd_ths = (uint8_t)val;
4747 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4748 }
4749
4750 return ret;
4751 }
4752
4753 /**
4754 * @brief Threshold for 4D/6D function.[get]
4755 *
4756 * @param ctx read / write interface definitions
4757 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4758 * @retval interface status (MANDATORY: return 0 -> no Error)
4759 *
4760 */
lsm6dso32_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dso32_sixd_ths_t * val)4761 int32_t lsm6dso32_6d_threshold_get(const stmdev_ctx_t *ctx,
4762 lsm6dso32_sixd_ths_t *val)
4763 {
4764 lsm6dso32_tap_ths_6d_t reg;
4765 int32_t ret;
4766
4767 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4768
4769 switch (reg.sixd_ths)
4770 {
4771 case LSM6DSO32_DEG_68:
4772 *val = LSM6DSO32_DEG_68;
4773 break;
4774
4775 case LSM6DSO32_DEG_47:
4776 *val = LSM6DSO32_DEG_47;
4777 break;
4778
4779 default:
4780 *val = LSM6DSO32_DEG_68;
4781 break;
4782 }
4783
4784 return ret;
4785 }
4786
4787 /**
4788 * @brief 4D orientation detection enable.[set]
4789 *
4790 * @param ctx read / write interface definitions
4791 * @param val change the values of d4d_en in reg TAP_THS_6D
4792 * @retval interface status (MANDATORY: return 0 -> no Error)
4793 *
4794 */
lsm6dso32_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4795 int32_t lsm6dso32_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4796 {
4797 lsm6dso32_tap_ths_6d_t reg;
4798 int32_t ret;
4799
4800 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4801
4802 if (ret == 0)
4803 {
4804 reg.d4d_en = val;
4805 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4806 }
4807
4808 return ret;
4809 }
4810
4811 /**
4812 * @brief 4D orientation detection enable.[get]
4813 *
4814 * @param ctx read / write interface definitions
4815 * @param val change the values of d4d_en in reg TAP_THS_6D
4816 * @retval interface status (MANDATORY: return 0 -> no Error)
4817 *
4818 */
lsm6dso32_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4819 int32_t lsm6dso32_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4820 {
4821 lsm6dso32_tap_ths_6d_t reg;
4822 int32_t ret;
4823
4824 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4825 *val = reg.d4d_en;
4826
4827 return ret;
4828 }
4829
4830 /**
4831 * @}
4832 *
4833 */
4834
4835 /**
4836 * @defgroup LSM6DSO32_free_fall
4837 * @brief This section group all the functions concerning the free
4838 * fall detection.
4839 * @{
4840 *
4841 */
4842
4843 /**
4844 * @brief Free fall threshold setting.[set]
4845 *
4846 * @param ctx read / write interface definitions
4847 * @param val change the values of ff_ths in reg FREE_FALL
4848 * @retval interface status (MANDATORY: return 0 -> no Error)
4849 *
4850 */
lsm6dso32_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dso32_ff_ths_t val)4851 int32_t lsm6dso32_ff_threshold_set(const stmdev_ctx_t *ctx,
4852 lsm6dso32_ff_ths_t val)
4853 {
4854 lsm6dso32_free_fall_t reg;
4855 int32_t ret;
4856
4857 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4858
4859 if (ret == 0)
4860 {
4861 reg.ff_ths = (uint8_t)val;
4862 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4863 }
4864
4865 return ret;
4866 }
4867
4868 /**
4869 * @brief Free fall threshold setting.[get]
4870 *
4871 * @param ctx read / write interface definitions
4872 * @param val Get the values of ff_ths in reg FREE_FALL
4873 * @retval interface status (MANDATORY: return 0 -> no Error)
4874 *
4875 */
lsm6dso32_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dso32_ff_ths_t * val)4876 int32_t lsm6dso32_ff_threshold_get(const stmdev_ctx_t *ctx,
4877 lsm6dso32_ff_ths_t *val)
4878 {
4879 lsm6dso32_free_fall_t reg;
4880 int32_t ret;
4881
4882 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4883
4884 switch (reg.ff_ths)
4885 {
4886 case LSM6DSO32_FF_TSH_312mg:
4887 *val = LSM6DSO32_FF_TSH_312mg;
4888 break;
4889
4890 case LSM6DSO32_FF_TSH_438mg:
4891 *val = LSM6DSO32_FF_TSH_438mg;
4892 break;
4893
4894 case LSM6DSO32_FF_TSH_500mg:
4895 *val = LSM6DSO32_FF_TSH_500mg;
4896 break;
4897
4898 default:
4899 *val = LSM6DSO32_FF_TSH_312mg;
4900 break;
4901 }
4902
4903 return ret;
4904 }
4905
4906 /**
4907 * @brief Free-fall duration event.[set]
4908 * 1LSb = 1 / ODR
4909 *
4910 * @param ctx read / write interface definitions
4911 * @param val change the values of ff_dur in reg FREE_FALL
4912 * @retval interface status (MANDATORY: return 0 -> no Error)
4913 *
4914 */
lsm6dso32_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4915 int32_t lsm6dso32_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4916 {
4917 lsm6dso32_wake_up_dur_t wake_up_dur;
4918 lsm6dso32_free_fall_t free_fall;
4919 int32_t ret;
4920
4921 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
4922 (uint8_t *)&wake_up_dur, 1);
4923
4924 if (ret == 0)
4925 {
4926 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
4927 (uint8_t *)&free_fall, 1);
4928 }
4929
4930 if (ret == 0)
4931 {
4932 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
4933 free_fall.ff_dur = (uint8_t)val & 0x1FU;
4934 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
4935 (uint8_t *)&wake_up_dur, 1);
4936 }
4937
4938 if (ret == 0)
4939 {
4940 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL,
4941 (uint8_t *)&free_fall, 1);
4942 }
4943
4944 return ret;
4945 }
4946
4947 /**
4948 * @brief Free-fall duration event.[get]
4949 * 1LSb = 1 / ODR
4950 *
4951 * @param ctx read / write interface definitions
4952 * @param val change the values of ff_dur in reg FREE_FALL
4953 * @retval interface status (MANDATORY: return 0 -> no Error)
4954 *
4955 */
lsm6dso32_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4956 int32_t lsm6dso32_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4957 {
4958 lsm6dso32_wake_up_dur_t wake_up_dur;
4959 lsm6dso32_free_fall_t free_fall;
4960 int32_t ret;
4961
4962 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
4963 (uint8_t *)&wake_up_dur, 1);
4964
4965 if (ret == 0)
4966 {
4967 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
4968 (uint8_t *)&free_fall, 1);
4969 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4970 }
4971
4972 return ret;
4973 }
4974
4975 /**
4976 * @}
4977 *
4978 */
4979
4980 /**
4981 * @defgroup LSM6DSO32_fifo
4982 * @brief This section group all the functions concerning the fifo usage
4983 * @{
4984 *
4985 */
4986
4987 /**
4988 * @brief FIFO watermark level selection.[set]
4989 *
4990 * @param ctx read / write interface definitions
4991 * @param val change the values of wtm in reg FIFO_CTRL1
4992 * @retval interface status (MANDATORY: return 0 -> no Error)
4993 *
4994 */
lsm6dso32_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)4995 int32_t lsm6dso32_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
4996 {
4997 lsm6dso32_fifo_ctrl1_t fifo_ctrl1;
4998 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
4999 int32_t ret;
5000
5001 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5002 (uint8_t *)&fifo_ctrl2, 1);
5003
5004 if (ret == 0)
5005 {
5006 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
5007 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
5008 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL1,
5009 (uint8_t *)&fifo_ctrl1, 1);
5010 }
5011
5012 if (ret == 0)
5013 {
5014 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5015 (uint8_t *)&fifo_ctrl2, 1);
5016 }
5017
5018 return ret;
5019 }
5020
5021 /**
5022 * @brief FIFO watermark level selection.[get]
5023 *
5024 * @param ctx read / write interface definitions
5025 * @param val change the values of wtm in reg FIFO_CTRL1
5026 * @retval interface status (MANDATORY: return 0 -> no Error)
5027 *
5028 */
lsm6dso32_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)5029 int32_t lsm6dso32_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
5030 {
5031 lsm6dso32_fifo_ctrl1_t fifo_ctrl1;
5032 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
5033 int32_t ret;
5034
5035 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL1,
5036 (uint8_t *)&fifo_ctrl1, 1);
5037
5038 if (ret == 0)
5039 {
5040 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5041 (uint8_t *)&fifo_ctrl2, 1);
5042 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
5043 }
5044
5045 return ret;
5046 }
5047
5048 /**
5049 * @brief FIFO compression feature initialization request [set].
5050 *
5051 * @param ctx read / write interface definitions
5052 * @param val change the values of FIFO_COMPR_INIT in
5053 * reg EMB_FUNC_INIT_B
5054 * @retval interface status (MANDATORY: return 0 -> no Error)
5055 *
5056 */
lsm6dso32_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)5057 int32_t lsm6dso32_compression_algo_init_set(const stmdev_ctx_t *ctx,
5058 uint8_t val)
5059 {
5060 lsm6dso32_emb_func_init_b_t reg;
5061 int32_t ret;
5062
5063 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5064
5065 if (ret == 0)
5066 {
5067 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5068 (uint8_t *)®, 1);
5069 }
5070
5071 if (ret == 0)
5072 {
5073 reg.fifo_compr_init = val;
5074 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5075 (uint8_t *)®, 1);
5076 }
5077
5078 if (ret == 0)
5079 {
5080 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5081 }
5082
5083 return ret;
5084 }
5085
5086 /**
5087 * @brief FIFO compression feature initialization request [get].
5088 *
5089 * @param ctx read / write interface definitions
5090 * @param val change the values of FIFO_COMPR_INIT in
5091 * reg EMB_FUNC_INIT_B
5092 * @retval interface status (MANDATORY: return 0 -> no Error)
5093 *
5094 */
lsm6dso32_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)5095 int32_t lsm6dso32_compression_algo_init_get(const stmdev_ctx_t *ctx,
5096 uint8_t *val)
5097 {
5098 lsm6dso32_emb_func_init_b_t reg;
5099 int32_t ret;
5100
5101 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5102
5103 if (ret == 0)
5104 {
5105 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5106 (uint8_t *)®, 1);
5107 }
5108
5109 if (ret == 0)
5110 {
5111 *val = reg.fifo_compr_init;
5112 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5113 }
5114
5115 return ret;
5116 }
5117
5118 /**
5119 * @brief Enable and configure compression algo.[set]
5120 *
5121 * @param ctx read / write interface definitions
5122 * @param val change the values of uncoptr_rate in
5123 * reg FIFO_CTRL2
5124 * @retval interface status (MANDATORY: return 0 -> no Error)
5125 *
5126 */
lsm6dso32_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dso32_uncoptr_rate_t val)5127 int32_t lsm6dso32_compression_algo_set(const stmdev_ctx_t *ctx,
5128 lsm6dso32_uncoptr_rate_t val)
5129 {
5130 lsm6dso32_emb_func_en_b_t emb_func_en_b;
5131 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
5132 int32_t ret;
5133
5134 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5135
5136 if (ret == 0)
5137 {
5138 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
5139 (uint8_t *)&emb_func_en_b, 1);
5140 }
5141
5142 if (ret == 0)
5143 {
5144 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
5145 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
5146 (uint8_t *)&emb_func_en_b, 1);
5147 }
5148
5149 if (ret == 0)
5150 {
5151 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5152 }
5153
5154 if (ret == 0)
5155 {
5156 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5157 (uint8_t *)&fifo_ctrl2, 1);
5158 }
5159
5160 if (ret == 0)
5161 {
5162 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
5163 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
5164 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5165 (uint8_t *)&fifo_ctrl2, 1);
5166 }
5167
5168 return ret;
5169 }
5170
5171 /**
5172 * @brief Enable and configure compression algo.[get]
5173 *
5174 * @param ctx read / write interface definitions
5175 * @param val Get the values of uncoptr_rate in
5176 * reg FIFO_CTRL2
5177 * @retval interface status (MANDATORY: return 0 -> no Error)
5178 *
5179 */
lsm6dso32_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dso32_uncoptr_rate_t * val)5180 int32_t lsm6dso32_compression_algo_get(const stmdev_ctx_t *ctx,
5181 lsm6dso32_uncoptr_rate_t *val)
5182 {
5183 lsm6dso32_fifo_ctrl2_t reg;
5184 int32_t ret;
5185
5186 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5187
5188 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
5189 {
5190 case LSM6DSO32_CMP_DISABLE:
5191 *val = LSM6DSO32_CMP_DISABLE;
5192 break;
5193
5194 case LSM6DSO32_CMP_ALWAYS:
5195 *val = LSM6DSO32_CMP_ALWAYS;
5196 break;
5197
5198 case LSM6DSO32_CMP_8_TO_1:
5199 *val = LSM6DSO32_CMP_8_TO_1;
5200 break;
5201
5202 case LSM6DSO32_CMP_16_TO_1:
5203 *val = LSM6DSO32_CMP_16_TO_1;
5204 break;
5205
5206 case LSM6DSO32_CMP_32_TO_1:
5207 *val = LSM6DSO32_CMP_32_TO_1;
5208 break;
5209
5210 default:
5211 *val = LSM6DSO32_CMP_DISABLE;
5212 break;
5213 }
5214
5215 return ret;
5216 }
5217
5218 /**
5219 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
5220 *
5221 * @param ctx read / write interface definitions
5222 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5223 * @retval interface status (MANDATORY: return 0 -> no Error)
5224 *
5225 */
lsm6dso32_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)5226 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
5227 uint8_t val)
5228 {
5229 lsm6dso32_fifo_ctrl2_t reg;
5230 int32_t ret;
5231
5232 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5233
5234 if (ret == 0)
5235 {
5236 reg.odrchg_en = val;
5237 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5238 }
5239
5240 return ret;
5241 }
5242
5243 /**
5244 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
5245 *
5246 * @param ctx read / write interface definitions
5247 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5248 * @retval interface status (MANDATORY: return 0 -> no Error)
5249 *
5250 */
lsm6dso32_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)5251 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
5252 uint8_t *val)
5253 {
5254 lsm6dso32_fifo_ctrl2_t reg;
5255 int32_t ret;
5256
5257 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5258 *val = reg.odrchg_en;
5259
5260 return ret;
5261 }
5262
5263 /**
5264 * @brief Enables/Disables compression algorithm runtime.[set]
5265 *
5266 * @param ctx read / write interface definitions
5267 * @param val change the values of fifo_compr_rt_en in
5268 * reg FIFO_CTRL2
5269 * @retval interface status (MANDATORY: return 0 -> no Error)
5270 *
5271 */
lsm6dso32_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)5272 int32_t lsm6dso32_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
5273 uint8_t val)
5274 {
5275 lsm6dso32_fifo_ctrl2_t reg;
5276 int32_t ret;
5277
5278 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5279
5280 if (ret == 0)
5281 {
5282 reg.fifo_compr_rt_en = val;
5283 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5284 }
5285
5286 return ret;
5287 }
5288
5289 /**
5290 * @brief Enables/Disables compression algorithm runtime.[get]
5291 *
5292 * @param ctx read / write interface definitions
5293 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
5294 * @retval interface status (MANDATORY: return 0 -> no Error)
5295 *
5296 */
lsm6dso32_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)5297 int32_t lsm6dso32_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
5298 uint8_t *val)
5299 {
5300 lsm6dso32_fifo_ctrl2_t reg;
5301 int32_t ret;
5302
5303 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5304 *val = reg.fifo_compr_rt_en;
5305
5306 return ret;
5307 }
5308
5309 /**
5310 * @brief Sensing chain FIFO stop values memorization at
5311 * threshold level.[set]
5312 *
5313 * @param ctx read / write interface definitions
5314 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5315 * @retval interface status (MANDATORY: return 0 -> no Error)
5316 *
5317 */
lsm6dso32_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)5318 int32_t lsm6dso32_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
5319 {
5320 lsm6dso32_fifo_ctrl2_t reg;
5321 int32_t ret;
5322
5323 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5324
5325 if (ret == 0)
5326 {
5327 reg.stop_on_wtm = val;
5328 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5329 }
5330
5331 return ret;
5332 }
5333
5334 /**
5335 * @brief Sensing chain FIFO stop values memorization at
5336 * threshold level.[get]
5337 *
5338 * @param ctx read / write interface definitions
5339 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5340 * @retval interface status (MANDATORY: return 0 -> no Error)
5341 *
5342 */
lsm6dso32_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)5343 int32_t lsm6dso32_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
5344 uint8_t *val)
5345 {
5346 lsm6dso32_fifo_ctrl2_t reg;
5347 int32_t ret;
5348
5349 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5350 *val = reg.stop_on_wtm;
5351
5352 return ret;
5353 }
5354
5355 /**
5356 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5357 * for accelerometer data.[set]
5358 *
5359 * @param ctx read / write interface definitions
5360 * @param val change the values of bdr_xl in reg FIFO_CTRL3
5361 * @retval interface status (MANDATORY: return 0 -> no Error)
5362 *
5363 */
lsm6dso32_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dso32_bdr_xl_t val)5364 int32_t lsm6dso32_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5365 lsm6dso32_bdr_xl_t val)
5366 {
5367 lsm6dso32_fifo_ctrl3_t reg;
5368 int32_t ret;
5369
5370 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5371
5372 if (ret == 0)
5373 {
5374 reg.bdr_xl = (uint8_t)val;
5375 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5376 }
5377
5378 return ret;
5379 }
5380
5381 /**
5382 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5383 * for accelerometer data.[get]
5384 *
5385 * @param ctx read / write interface definitions
5386 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
5387 * @retval interface status (MANDATORY: return 0 -> no Error)
5388 *
5389 */
lsm6dso32_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dso32_bdr_xl_t * val)5390 int32_t lsm6dso32_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5391 lsm6dso32_bdr_xl_t *val)
5392 {
5393 lsm6dso32_fifo_ctrl3_t reg;
5394 int32_t ret;
5395
5396 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5397
5398 switch (reg.bdr_xl)
5399 {
5400 case LSM6DSO32_XL_NOT_BATCHED:
5401 *val = LSM6DSO32_XL_NOT_BATCHED;
5402 break;
5403
5404 case LSM6DSO32_XL_BATCHED_AT_12Hz5:
5405 *val = LSM6DSO32_XL_BATCHED_AT_12Hz5;
5406 break;
5407
5408 case LSM6DSO32_XL_BATCHED_AT_26Hz:
5409 *val = LSM6DSO32_XL_BATCHED_AT_26Hz;
5410 break;
5411
5412 case LSM6DSO32_XL_BATCHED_AT_52Hz:
5413 *val = LSM6DSO32_XL_BATCHED_AT_52Hz;
5414 break;
5415
5416 case LSM6DSO32_XL_BATCHED_AT_104Hz:
5417 *val = LSM6DSO32_XL_BATCHED_AT_104Hz;
5418 break;
5419
5420 case LSM6DSO32_XL_BATCHED_AT_208Hz:
5421 *val = LSM6DSO32_XL_BATCHED_AT_208Hz;
5422 break;
5423
5424 case LSM6DSO32_XL_BATCHED_AT_417Hz:
5425 *val = LSM6DSO32_XL_BATCHED_AT_417Hz;
5426 break;
5427
5428 case LSM6DSO32_XL_BATCHED_AT_833Hz:
5429 *val = LSM6DSO32_XL_BATCHED_AT_833Hz;
5430 break;
5431
5432 case LSM6DSO32_XL_BATCHED_AT_1667Hz:
5433 *val = LSM6DSO32_XL_BATCHED_AT_1667Hz;
5434 break;
5435
5436 case LSM6DSO32_XL_BATCHED_AT_3333Hz:
5437 *val = LSM6DSO32_XL_BATCHED_AT_3333Hz;
5438 break;
5439
5440 case LSM6DSO32_XL_BATCHED_AT_6667Hz:
5441 *val = LSM6DSO32_XL_BATCHED_AT_6667Hz;
5442 break;
5443
5444 case LSM6DSO32_XL_BATCHED_AT_6Hz5:
5445 *val = LSM6DSO32_XL_BATCHED_AT_6Hz5;
5446 break;
5447
5448 default:
5449 *val = LSM6DSO32_XL_NOT_BATCHED;
5450 break;
5451 }
5452
5453 return ret;
5454 }
5455
5456 /**
5457 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5458 * for gyroscope data.[set]
5459 *
5460 * @param ctx read / write interface definitions
5461 * @param val change the values of bdr_gy in reg FIFO_CTRL3
5462 * @retval interface status (MANDATORY: return 0 -> no Error)
5463 *
5464 */
lsm6dso32_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dso32_bdr_gy_t val)5465 int32_t lsm6dso32_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5466 lsm6dso32_bdr_gy_t val)
5467 {
5468 lsm6dso32_fifo_ctrl3_t reg;
5469 int32_t ret;
5470
5471 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5472
5473 if (ret == 0)
5474 {
5475 reg.bdr_gy = (uint8_t)val;
5476 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5477 }
5478
5479 return ret;
5480 }
5481
5482 /**
5483 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5484 * for gyroscope data.[get]
5485 *
5486 * @param ctx read / write interface definitions
5487 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
5488 * @retval interface status (MANDATORY: return 0 -> no Error)
5489 *
5490 */
lsm6dso32_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dso32_bdr_gy_t * val)5491 int32_t lsm6dso32_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5492 lsm6dso32_bdr_gy_t *val)
5493 {
5494 lsm6dso32_fifo_ctrl3_t reg;
5495 int32_t ret;
5496
5497 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5498
5499 switch (reg.bdr_gy)
5500 {
5501 case LSM6DSO32_GY_NOT_BATCHED:
5502 *val = LSM6DSO32_GY_NOT_BATCHED;
5503 break;
5504
5505 case LSM6DSO32_GY_BATCHED_AT_12Hz5:
5506 *val = LSM6DSO32_GY_BATCHED_AT_12Hz5;
5507 break;
5508
5509 case LSM6DSO32_GY_BATCHED_AT_26Hz:
5510 *val = LSM6DSO32_GY_BATCHED_AT_26Hz;
5511 break;
5512
5513 case LSM6DSO32_GY_BATCHED_AT_52Hz:
5514 *val = LSM6DSO32_GY_BATCHED_AT_52Hz;
5515 break;
5516
5517 case LSM6DSO32_GY_BATCHED_AT_104Hz:
5518 *val = LSM6DSO32_GY_BATCHED_AT_104Hz;
5519 break;
5520
5521 case LSM6DSO32_GY_BATCHED_AT_208Hz:
5522 *val = LSM6DSO32_GY_BATCHED_AT_208Hz;
5523 break;
5524
5525 case LSM6DSO32_GY_BATCHED_AT_417Hz:
5526 *val = LSM6DSO32_GY_BATCHED_AT_417Hz;
5527 break;
5528
5529 case LSM6DSO32_GY_BATCHED_AT_833Hz:
5530 *val = LSM6DSO32_GY_BATCHED_AT_833Hz;
5531 break;
5532
5533 case LSM6DSO32_GY_BATCHED_AT_1667Hz:
5534 *val = LSM6DSO32_GY_BATCHED_AT_1667Hz;
5535 break;
5536
5537 case LSM6DSO32_GY_BATCHED_AT_3333Hz:
5538 *val = LSM6DSO32_GY_BATCHED_AT_3333Hz;
5539 break;
5540
5541 case LSM6DSO32_GY_BATCHED_AT_6667Hz:
5542 *val = LSM6DSO32_GY_BATCHED_AT_6667Hz;
5543 break;
5544
5545 case LSM6DSO32_GY_BATCHED_AT_6Hz5:
5546 *val = LSM6DSO32_GY_BATCHED_AT_6Hz5;
5547 break;
5548
5549 default:
5550 *val = LSM6DSO32_GY_NOT_BATCHED;
5551 break;
5552 }
5553
5554 return ret;
5555 }
5556
5557 /**
5558 * @brief FIFO mode selection.[set]
5559 *
5560 * @param ctx read / write interface definitions
5561 * @param val change the values of fifo_mode in reg FIFO_CTRL4
5562 * @retval interface status (MANDATORY: return 0 -> no Error)
5563 *
5564 */
lsm6dso32_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_fifo_mode_t val)5565 int32_t lsm6dso32_fifo_mode_set(const stmdev_ctx_t *ctx,
5566 lsm6dso32_fifo_mode_t val)
5567 {
5568 lsm6dso32_fifo_ctrl4_t reg;
5569 int32_t ret;
5570
5571 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5572
5573 if (ret == 0)
5574 {
5575 reg.fifo_mode = (uint8_t)val;
5576 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5577 }
5578
5579 return ret;
5580 }
5581
5582 /**
5583 * @brief FIFO mode selection.[get]
5584 *
5585 * @param ctx read / write interface definitions
5586 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
5587 * @retval interface status (MANDATORY: return 0 -> no Error)
5588 *
5589 */
lsm6dso32_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_fifo_mode_t * val)5590 int32_t lsm6dso32_fifo_mode_get(const stmdev_ctx_t *ctx,
5591 lsm6dso32_fifo_mode_t *val)
5592 {
5593 lsm6dso32_fifo_ctrl4_t reg;
5594 int32_t ret;
5595
5596 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5597
5598 switch (reg.fifo_mode)
5599 {
5600 case LSM6DSO32_BYPASS_MODE:
5601 *val = LSM6DSO32_BYPASS_MODE;
5602 break;
5603
5604 case LSM6DSO32_FIFO_MODE:
5605 *val = LSM6DSO32_FIFO_MODE;
5606 break;
5607
5608 case LSM6DSO32_STREAM_TO_FIFO_MODE:
5609 *val = LSM6DSO32_STREAM_TO_FIFO_MODE;
5610 break;
5611
5612 case LSM6DSO32_BYPASS_TO_STREAM_MODE:
5613 *val = LSM6DSO32_BYPASS_TO_STREAM_MODE;
5614 break;
5615
5616 case LSM6DSO32_STREAM_MODE:
5617 *val = LSM6DSO32_STREAM_MODE;
5618 break;
5619
5620 case LSM6DSO32_BYPASS_TO_FIFO_MODE:
5621 *val = LSM6DSO32_BYPASS_TO_FIFO_MODE;
5622 break;
5623
5624 default:
5625 *val = LSM6DSO32_BYPASS_MODE;
5626 break;
5627 }
5628
5629 return ret;
5630 }
5631
5632 /**
5633 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5634 * for temperature data.[set]
5635 *
5636 * @param ctx read / write interface definitions
5637 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
5638 * @retval interface status (MANDATORY: return 0 -> no Error)
5639 *
5640 */
lsm6dso32_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dso32_odr_t_batch_t val)5641 int32_t lsm6dso32_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
5642 lsm6dso32_odr_t_batch_t val)
5643 {
5644 lsm6dso32_fifo_ctrl4_t reg;
5645 int32_t ret;
5646
5647 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5648
5649 if (ret == 0)
5650 {
5651 reg.odr_t_batch = (uint8_t)val;
5652 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5653 }
5654
5655 return ret;
5656 }
5657
5658 /**
5659 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5660 * for temperature data.[get]
5661 *
5662 * @param ctx read / write interface definitions
5663 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
5664 * @retval interface status (MANDATORY: return 0 -> no Error)
5665 *
5666 */
lsm6dso32_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dso32_odr_t_batch_t * val)5667 int32_t lsm6dso32_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
5668 lsm6dso32_odr_t_batch_t *val)
5669 {
5670 lsm6dso32_fifo_ctrl4_t reg;
5671 int32_t ret;
5672
5673 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5674
5675 switch (reg.odr_t_batch)
5676 {
5677 case LSM6DSO32_TEMP_NOT_BATCHED:
5678 *val = LSM6DSO32_TEMP_NOT_BATCHED;
5679 break;
5680
5681 case LSM6DSO32_TEMP_BATCHED_AT_1Hz6:
5682 *val = LSM6DSO32_TEMP_BATCHED_AT_1Hz6;
5683 break;
5684
5685 case LSM6DSO32_TEMP_BATCHED_AT_12Hz5:
5686 *val = LSM6DSO32_TEMP_BATCHED_AT_12Hz5;
5687 break;
5688
5689 case LSM6DSO32_TEMP_BATCHED_AT_52Hz:
5690 *val = LSM6DSO32_TEMP_BATCHED_AT_52Hz;
5691 break;
5692
5693 default:
5694 *val = LSM6DSO32_TEMP_NOT_BATCHED;
5695 break;
5696 }
5697
5698 return ret;
5699 }
5700
5701 /**
5702 * @brief Selects decimation for timestamp batching in FIFO.
5703 * Writing rate will be the maximum rate between XL and
5704 * GYRO BDR divided by decimation decoder.[set]
5705 *
5706 * @param ctx read / write interface definitions
5707 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
5708 * @retval interface status (MANDATORY: return 0 -> no Error)
5709 *
5710 */
lsm6dso32_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dso32_odr_ts_batch_t val)5711 int32_t lsm6dso32_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
5712 lsm6dso32_odr_ts_batch_t val)
5713 {
5714 lsm6dso32_fifo_ctrl4_t reg;
5715 int32_t ret;
5716
5717 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5718
5719 if (ret == 0)
5720 {
5721 reg.odr_ts_batch = (uint8_t)val;
5722 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5723 }
5724
5725 return ret;
5726 }
5727
5728 /**
5729 * @brief Selects decimation for timestamp batching in FIFO.
5730 * Writing rate will be the maximum rate between XL and
5731 * GYRO BDR divided by decimation decoder.[get]
5732 *
5733 * @param ctx read / write interface definitions
5734 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
5735 * @retval interface status (MANDATORY: return 0 -> no Error)
5736 *
5737 */
lsm6dso32_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dso32_odr_ts_batch_t * val)5738 int32_t lsm6dso32_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
5739 lsm6dso32_odr_ts_batch_t *val)
5740 {
5741 lsm6dso32_fifo_ctrl4_t reg;
5742 int32_t ret;
5743
5744 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5745
5746 switch (reg.odr_ts_batch)
5747 {
5748 case LSM6DSO32_NO_DECIMATION:
5749 *val = LSM6DSO32_NO_DECIMATION;
5750 break;
5751
5752 case LSM6DSO32_DEC_1:
5753 *val = LSM6DSO32_DEC_1;
5754 break;
5755
5756 case LSM6DSO32_DEC_8:
5757 *val = LSM6DSO32_DEC_8;
5758 break;
5759
5760 case LSM6DSO32_DEC_32:
5761 *val = LSM6DSO32_DEC_32;
5762 break;
5763
5764 default:
5765 *val = LSM6DSO32_NO_DECIMATION;
5766 break;
5767 }
5768
5769 return ret;
5770 }
5771
5772 /**
5773 * @brief Selects the trigger for the internal counter of batching events
5774 * between XL and gyro.[set]
5775 *
5776 * @param ctx read / write interface definitions
5777 * @param val change the values of trig_counter_bdr
5778 * in reg COUNTER_BDR_REG1
5779 * @retval interface status (MANDATORY: return 0 -> no Error)
5780 *
5781 */
lsm6dso32_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dso32_trig_counter_bdr_t val)5782 int32_t lsm6dso32_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
5783 lsm6dso32_trig_counter_bdr_t val)
5784 {
5785 lsm6dso32_counter_bdr_reg1_t reg;
5786 int32_t ret;
5787
5788 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5789 (uint8_t *)®, 1);
5790
5791 if (ret == 0)
5792 {
5793 reg.trig_counter_bdr = (uint8_t)val;
5794 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5795 (uint8_t *)®, 1);
5796 }
5797
5798 return ret;
5799 }
5800
5801 /**
5802 * @brief Selects the trigger for the internal counter of batching events
5803 * between XL and gyro.[get]
5804 *
5805 * @param ctx read / write interface definitions
5806 * @param val Get the values of trig_counter_bdr
5807 * in reg COUNTER_BDR_REG1
5808 * @retval interface status (MANDATORY: return 0 -> no Error)
5809 *
5810 */
lsm6dso32_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dso32_trig_counter_bdr_t * val)5811 int32_t lsm6dso32_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
5812 lsm6dso32_trig_counter_bdr_t *val)
5813 {
5814 lsm6dso32_counter_bdr_reg1_t reg;
5815 int32_t ret;
5816
5817 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5818 (uint8_t *)®, 1);
5819
5820 switch (reg.trig_counter_bdr)
5821 {
5822 case LSM6DSO32_XL_BATCH_EVENT:
5823 *val = LSM6DSO32_XL_BATCH_EVENT;
5824 break;
5825
5826 case LSM6DSO32_GYRO_BATCH_EVENT:
5827 *val = LSM6DSO32_GYRO_BATCH_EVENT;
5828 break;
5829
5830 default:
5831 *val = LSM6DSO32_XL_BATCH_EVENT;
5832 break;
5833 }
5834
5835 return ret;
5836 }
5837
5838 /**
5839 * @brief Resets the internal counter of batching vents for a single sensor.
5840 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5841 *
5842 * @param ctx read / write interface definitions
5843 * @param val change the values of rst_counter_bdr in
5844 * reg COUNTER_BDR_REG1
5845 * @retval interface status (MANDATORY: return 0 -> no Error)
5846 *
5847 */
lsm6dso32_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)5848 int32_t lsm6dso32_rst_batch_counter_set(const stmdev_ctx_t *ctx,
5849 uint8_t val)
5850 {
5851 lsm6dso32_counter_bdr_reg1_t reg;
5852 int32_t ret;
5853
5854 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5855 (uint8_t *)®, 1);
5856
5857 if (ret == 0)
5858 {
5859 reg.rst_counter_bdr = val;
5860 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5861 (uint8_t *)®, 1);
5862 }
5863
5864 return ret;
5865 }
5866
5867 /**
5868 * @brief Resets the internal counter of batching events for a single sensor.
5869 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5870 *
5871 * @param ctx read / write interface definitions
5872 * @param val change the values of rst_counter_bdr in
5873 * reg COUNTER_BDR_REG1
5874 * @retval interface status (MANDATORY: return 0 -> no Error)
5875 *
5876 */
lsm6dso32_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)5877 int32_t lsm6dso32_rst_batch_counter_get(const stmdev_ctx_t *ctx,
5878 uint8_t *val)
5879 {
5880 lsm6dso32_counter_bdr_reg1_t reg;
5881 int32_t ret;
5882
5883 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5884 (uint8_t *)®, 1);
5885 *val = reg.rst_counter_bdr;
5886
5887 return ret;
5888 }
5889
5890 /**
5891 * @brief Batch data rate counter.[set]
5892 *
5893 * @param ctx read / write interface definitions
5894 * @param val change the values of cnt_bdr_th in
5895 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
5896 * @retval interface status (MANDATORY: return 0 -> no Error)
5897 *
5898 */
lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5899 int32_t lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
5900 uint16_t val)
5901 {
5902 lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1;
5903 lsm6dso32_counter_bdr_reg2_t counter_bdr_reg2;
5904 int32_t ret;
5905
5906 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5907 (uint8_t *)&counter_bdr_reg1, 1);
5908
5909 if (ret == 0)
5910 {
5911 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
5912 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
5913 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5914 (uint8_t *)&counter_bdr_reg1, 1);
5915 }
5916
5917 if (ret == 0)
5918 {
5919 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
5920 (uint8_t *)&counter_bdr_reg2, 1);
5921 }
5922
5923 return ret;
5924 }
5925
5926 /**
5927 * @brief Batch data rate counter.[get]
5928 *
5929 * @param ctx read / write interface definitions
5930 * @param val change the values of cnt_bdr_th in
5931 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
5932 * @retval interface status (MANDATORY: return 0 -> no Error)
5933 *
5934 */
lsm6dso32_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5935 int32_t lsm6dso32_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5936 uint16_t *val)
5937 {
5938 lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1;
5939 lsm6dso32_counter_bdr_reg2_t counter_bdr_reg2;
5940 int32_t ret;
5941
5942 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5943 (uint8_t *)&counter_bdr_reg1, 1);
5944
5945 if (ret == 0)
5946 {
5947 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
5948 (uint8_t *)&counter_bdr_reg2, 1);
5949 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
5950 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
5951 }
5952
5953 return ret;
5954 }
5955
5956 /**
5957 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
5958 *
5959 * @param ctx Read / write interface definitions.(ptr)
5960 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
5961 * @retval Interface status (MANDATORY: return 0 -> no Error).
5962 *
5963 */
lsm6dso32_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5964 int32_t lsm6dso32_fifo_data_level_get(const stmdev_ctx_t *ctx,
5965 uint16_t *val)
5966 {
5967 uint8_t reg[2];
5968 lsm6dso32_fifo_status1_t *fifo_status1 = (lsm6dso32_fifo_status1_t *)®[0];
5969 lsm6dso32_fifo_status2_t *fifo_status2 = (lsm6dso32_fifo_status2_t *)®[1];
5970 int32_t ret;
5971
5972 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5973 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2);
5974 if (ret == 0)
5975 {
5976 *val = fifo_status2->diff_fifo;
5977 *val = (*val * 256U) + fifo_status1->diff_fifo;
5978 }
5979
5980 return ret;
5981 }
5982
5983 /**
5984 * @brief Smart FIFO status.[get]
5985 *
5986 * @param ctx Read / write interface definitions.(ptr)
5987 * @param val Read registers FIFO_STATUS2
5988 * @retval Interface status (MANDATORY: return 0 -> no Error).
5989 *
5990 */
lsm6dso32_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dso32_fifo_status2_t * val)5991 int32_t lsm6dso32_fifo_status_get(const stmdev_ctx_t *ctx,
5992 lsm6dso32_fifo_status2_t *val)
5993 {
5994 uint8_t reg[2];
5995 lsm6dso32_fifo_status2_t *fifo_status2 = (lsm6dso32_fifo_status2_t *)®[1];
5996 int32_t ret;
5997
5998 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5999 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2);
6000 if (ret == 0)
6001 {
6002 *val = *fifo_status2;
6003 }
6004
6005 return ret;
6006 }
6007
6008 /**
6009 * @brief Smart FIFO full status.[get]
6010 *
6011 * @param ctx Read / write interface definitions.(ptr)
6012 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
6013 * @retval Interface status (MANDATORY: return 0 -> no Error).
6014 *
6015 */
lsm6dso32_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6016 int32_t lsm6dso32_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6017 {
6018 uint8_t reg[2];
6019 lsm6dso32_fifo_status2_t *fifo_status2 = (lsm6dso32_fifo_status2_t *)®[1];
6020 int32_t ret;
6021
6022 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6023 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2);
6024 if (ret == 0)
6025 {
6026 *val = fifo_status2->fifo_full_ia;
6027 }
6028
6029 return ret;
6030 }
6031
6032 /**
6033 * @brief FIFO overrun status.[get]
6034 *
6035 * @param ctx Read / write interface definitions.(ptr)
6036 * @param val Read the values of fifo_over_run_latched in
6037 * reg FIFO_STATUS2
6038 * @retval Interface status (MANDATORY: return 0 -> no Error).
6039 *
6040 */
lsm6dso32_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6041 int32_t lsm6dso32_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6042 {
6043 uint8_t reg[2];
6044 lsm6dso32_fifo_status2_t *fifo_status2 = (lsm6dso32_fifo_status2_t *)®[1];
6045 int32_t ret;
6046
6047 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6048 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2);
6049 if (ret == 0)
6050 {
6051 *val = fifo_status2->fifo_ovr_ia;
6052 }
6053
6054 return ret;
6055 }
6056
6057 /**
6058 * @brief FIFO watermark status.[get]
6059 *
6060 * @param ctx Read / write interface definitions.(ptr)
6061 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
6062 * @retval Interface status (MANDATORY: return 0 -> no Error).
6063 *
6064 */
lsm6dso32_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6065 int32_t lsm6dso32_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6066 {
6067 uint8_t reg[2];
6068 lsm6dso32_fifo_status2_t *fifo_status2 = (lsm6dso32_fifo_status2_t *)®[1];
6069 int32_t ret;
6070
6071 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6072 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1, (uint8_t *)reg, 2);
6073 if (ret == 0)
6074 {
6075 *val = fifo_status2->fifo_wtm_ia;
6076 }
6077
6078 return ret;
6079 }
6080
6081 /**
6082 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
6083 *
6084 * @param ctx read / write interface definitions
6085 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
6086 * @retval interface status (MANDATORY: return 0 -> no Error)
6087 *
6088 */
lsm6dso32_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dso32_fifo_tag_t * val)6089 int32_t lsm6dso32_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
6090 lsm6dso32_fifo_tag_t *val)
6091 {
6092 lsm6dso32_fifo_data_out_tag_t reg;
6093 int32_t ret;
6094
6095 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_TAG,
6096 (uint8_t *)®, 1);
6097
6098 switch (reg.tag_sensor)
6099 {
6100 case LSM6DSO32_GYRO_NC_TAG:
6101 *val = LSM6DSO32_GYRO_NC_TAG;
6102 break;
6103
6104 case LSM6DSO32_XL_NC_TAG:
6105 *val = LSM6DSO32_XL_NC_TAG;
6106 break;
6107
6108 case LSM6DSO32_TEMPERATURE_TAG:
6109 *val = LSM6DSO32_TEMPERATURE_TAG;
6110 break;
6111
6112 case LSM6DSO32_TIMESTAMP_TAG:
6113 *val = LSM6DSO32_TIMESTAMP_TAG;
6114 break;
6115
6116 case LSM6DSO32_CFG_CHANGE_TAG:
6117 *val = LSM6DSO32_CFG_CHANGE_TAG;
6118 break;
6119
6120 case LSM6DSO32_XL_NC_T_2_TAG:
6121 *val = LSM6DSO32_XL_NC_T_2_TAG;
6122 break;
6123
6124 case LSM6DSO32_XL_NC_T_1_TAG:
6125 *val = LSM6DSO32_XL_NC_T_1_TAG;
6126 break;
6127
6128 case LSM6DSO32_XL_2XC_TAG:
6129 *val = LSM6DSO32_XL_2XC_TAG;
6130 break;
6131
6132 case LSM6DSO32_XL_3XC_TAG:
6133 *val = LSM6DSO32_XL_3XC_TAG;
6134 break;
6135
6136 case LSM6DSO32_GYRO_NC_T_2_TAG:
6137 *val = LSM6DSO32_GYRO_NC_T_2_TAG;
6138 break;
6139
6140 case LSM6DSO32_GYRO_NC_T_1_TAG:
6141 *val = LSM6DSO32_GYRO_NC_T_1_TAG;
6142 break;
6143
6144 case LSM6DSO32_GYRO_2XC_TAG:
6145 *val = LSM6DSO32_GYRO_2XC_TAG;
6146 break;
6147
6148 case LSM6DSO32_GYRO_3XC_TAG:
6149 *val = LSM6DSO32_GYRO_3XC_TAG;
6150 break;
6151
6152 case LSM6DSO32_SENSORHUB_SLAVE0_TAG:
6153 *val = LSM6DSO32_SENSORHUB_SLAVE0_TAG;
6154 break;
6155
6156 case LSM6DSO32_SENSORHUB_SLAVE1_TAG:
6157 *val = LSM6DSO32_SENSORHUB_SLAVE1_TAG;
6158 break;
6159
6160 case LSM6DSO32_SENSORHUB_SLAVE2_TAG:
6161 *val = LSM6DSO32_SENSORHUB_SLAVE2_TAG;
6162 break;
6163
6164 case LSM6DSO32_SENSORHUB_SLAVE3_TAG:
6165 *val = LSM6DSO32_SENSORHUB_SLAVE3_TAG;
6166 break;
6167
6168 case LSM6DSO32_STEP_COUNTER_TAG:
6169 *val = LSM6DSO32_STEP_COUNTER_TAG;
6170 break;
6171
6172 case LSM6DSO32_SENSORHUB_NACK_TAG:
6173 *val = LSM6DSO32_SENSORHUB_NACK_TAG;
6174 break;
6175
6176 default:
6177 *val = LSM6DSO32_GYRO_NC_TAG;
6178 break;
6179 }
6180
6181 return ret;
6182 }
6183
6184 /**
6185 * @brief : Enable FIFO batching of pedometer embedded
6186 * function values.[set]
6187 *
6188 * @param ctx read / write interface definitions
6189 * @param val change the values of gbias_fifo_en in
6190 * reg LSM6DSO32_EMB_FUNC_FIFO_CFG
6191 * @retval interface status (MANDATORY: return 0 -> no Error)
6192 *
6193 */
lsm6dso32_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)6194 int32_t lsm6dso32_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
6195 {
6196 lsm6dso32_emb_func_fifo_cfg_t reg;
6197 int32_t ret;
6198
6199 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6200
6201 if (ret == 0)
6202 {
6203 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6204 (uint8_t *)®, 1);
6205 }
6206
6207 if (ret == 0)
6208 {
6209 reg.pedo_fifo_en = val;
6210 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6211 (uint8_t *)®, 1);
6212 }
6213
6214 if (ret == 0)
6215 {
6216 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6217 }
6218
6219 return ret;
6220 }
6221
6222 /**
6223 * @brief Enable FIFO batching of pedometer embedded function values.[get]
6224 *
6225 * @param ctx read / write interface definitions
6226 * @param val change the values of pedo_fifo_en in
6227 * reg LSM6DSO32_EMB_FUNC_FIFO_CFG
6228 * @retval interface status (MANDATORY: return 0 -> no Error)
6229 *
6230 */
lsm6dso32_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)6231 int32_t lsm6dso32_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
6232 {
6233 lsm6dso32_emb_func_fifo_cfg_t reg;
6234 int32_t ret;
6235
6236 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6237
6238 if (ret == 0)
6239 {
6240 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6241 (uint8_t *)®, 1);
6242 }
6243
6244 if (ret == 0)
6245 {
6246 *val = reg.pedo_fifo_en;
6247 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6248 }
6249
6250 return ret;
6251 }
6252
6253 /**
6254 * @brief Enable FIFO batching data of first slave.[set]
6255 *
6256 * @param ctx read / write interface definitions
6257 * @param val change the values of batch_ext_sens_0_en in
6258 * reg SLV0_CONFIG
6259 * @retval interface status (MANDATORY: return 0 -> no Error)
6260 *
6261 */
lsm6dso32_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)6262 int32_t lsm6dso32_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val)
6263 {
6264 lsm6dso32_slv0_config_t reg;
6265 int32_t ret;
6266
6267 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6268
6269 if (ret == 0)
6270 {
6271 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6272 }
6273
6274 if (ret == 0)
6275 {
6276 reg.batch_ext_sens_0_en = val;
6277 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6278 }
6279
6280 if (ret == 0)
6281 {
6282 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6283 }
6284
6285 return ret;
6286 }
6287
6288 /**
6289 * @brief Enable FIFO batching data of first slave.[get]
6290 *
6291 * @param ctx read / write interface definitions
6292 * @param val change the values of batch_ext_sens_0_en in
6293 * reg SLV0_CONFIG
6294 * @retval interface status (MANDATORY: return 0 -> no Error)
6295 *
6296 */
lsm6dso32_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)6297 int32_t lsm6dso32_sh_batch_slave_0_get(const stmdev_ctx_t *ctx,
6298 uint8_t *val)
6299 {
6300 lsm6dso32_slv0_config_t reg;
6301 int32_t ret;
6302
6303 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6304
6305 if (ret == 0)
6306 {
6307 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6308 }
6309
6310 if (ret == 0)
6311 {
6312 *val = reg.batch_ext_sens_0_en;
6313 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6314 }
6315
6316 return ret;
6317 }
6318
6319 /**
6320 * @brief Enable FIFO batching data of second slave.[set]
6321 *
6322 * @param ctx read / write interface definitions
6323 * @param val change the values of batch_ext_sens_1_en in
6324 * reg SLV1_CONFIG
6325 * @retval interface status (MANDATORY: return 0 -> no Error)
6326 *
6327 */
lsm6dso32_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)6328 int32_t lsm6dso32_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val)
6329 {
6330 lsm6dso32_slv1_config_t reg;
6331 int32_t ret;
6332
6333 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6334
6335 if (ret == 0)
6336 {
6337 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6338 }
6339
6340 if (ret == 0)
6341 {
6342 reg.batch_ext_sens_1_en = val;
6343 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6344 }
6345
6346 if (ret == 0)
6347 {
6348 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6349 }
6350
6351 return ret;
6352 }
6353
6354 /**
6355 * @brief Enable FIFO batching data of second slave.[get]
6356 *
6357 * @param ctx read / write interface definitions
6358 * @param val change the values of batch_ext_sens_1_en in
6359 * reg SLV1_CONFIG
6360 * @retval interface status (MANDATORY: return 0 -> no Error)
6361 *
6362 */
lsm6dso32_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)6363 int32_t lsm6dso32_sh_batch_slave_1_get(const stmdev_ctx_t *ctx,
6364 uint8_t *val)
6365 {
6366 lsm6dso32_slv1_config_t reg;
6367 int32_t ret;
6368
6369 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6370
6371 if (ret == 0)
6372 {
6373 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6374 *val = reg.batch_ext_sens_1_en;
6375 }
6376
6377 if (ret == 0)
6378 {
6379 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6380 }
6381
6382 return ret;
6383 }
6384
6385 /**
6386 * @brief Enable FIFO batching data of third slave.[set]
6387 *
6388 * @param ctx read / write interface definitions
6389 * @param val change the values of batch_ext_sens_2_en in
6390 * reg SLV2_CONFIG
6391 * @retval interface status (MANDATORY: return 0 -> no Error)
6392 *
6393 */
lsm6dso32_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)6394 int32_t lsm6dso32_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val)
6395 {
6396 lsm6dso32_slv2_config_t reg;
6397 int32_t ret;
6398
6399 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6400
6401 if (ret == 0)
6402 {
6403 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6404 }
6405
6406 if (ret == 0)
6407 {
6408 reg.batch_ext_sens_2_en = val;
6409 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6410 }
6411
6412 if (ret == 0)
6413 {
6414 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6415 }
6416
6417 return ret;
6418 }
6419
6420 /**
6421 * @brief Enable FIFO batching data of third slave.[get]
6422 *
6423 * @param ctx read / write interface definitions
6424 * @param val change the values of batch_ext_sens_2_en in
6425 * reg SLV2_CONFIG
6426 * @retval interface status (MANDATORY: return 0 -> no Error)
6427 *
6428 */
lsm6dso32_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)6429 int32_t lsm6dso32_sh_batch_slave_2_get(const stmdev_ctx_t *ctx,
6430 uint8_t *val)
6431 {
6432 lsm6dso32_slv2_config_t reg;
6433 int32_t ret;
6434
6435 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6436
6437 if (ret == 0)
6438 {
6439 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6440 }
6441
6442 if (ret == 0)
6443 {
6444 *val = reg.batch_ext_sens_2_en;
6445 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6446 }
6447
6448 return ret;
6449 }
6450
6451 /**
6452 * @brief Enable FIFO batching data of fourth slave.[set]
6453 *
6454 * @param ctx read / write interface definitions
6455 * @param val change the values of batch_ext_sens_3_en
6456 * in reg SLV3_CONFIG
6457 * @retval interface status (MANDATORY: return 0 -> no Error)
6458 *
6459 */
lsm6dso32_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)6460 int32_t lsm6dso32_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val)
6461 {
6462 lsm6dso32_slv3_config_t reg;
6463 int32_t ret;
6464
6465 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6466
6467 if (ret == 0)
6468 {
6469 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6470 }
6471
6472 if (ret == 0)
6473 {
6474 reg.batch_ext_sens_3_en = val;
6475 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6476 }
6477
6478 if (ret == 0)
6479 {
6480 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6481 }
6482
6483 return ret;
6484 }
6485
6486 /**
6487 * @brief Enable FIFO batching data of fourth slave.[get]
6488 *
6489 * @param ctx read / write interface definitions
6490 * @param val change the values of batch_ext_sens_3_en in
6491 * reg SLV3_CONFIG
6492 * @retval interface status (MANDATORY: return 0 -> no Error)
6493 *
6494 */
lsm6dso32_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)6495 int32_t lsm6dso32_sh_batch_slave_3_get(const stmdev_ctx_t *ctx,
6496 uint8_t *val)
6497 {
6498 lsm6dso32_slv3_config_t reg;
6499 int32_t ret;
6500
6501 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6502
6503 if (ret == 0)
6504 {
6505 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6506 }
6507
6508 if (ret == 0)
6509 {
6510 *val = reg.batch_ext_sens_3_en;
6511 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6512 }
6513
6514 return ret;
6515 }
6516
6517 /**
6518 * @}
6519 *
6520 */
6521
6522 /**
6523 * @defgroup LSM6DSO32_DEN_functionality
6524 * @brief This section groups all the functions concerning
6525 * DEN functionality.
6526 * @{
6527 *
6528 */
6529
6530 /**
6531 * @brief DEN functionality marking mode.[set]
6532 *
6533 * @param ctx read / write interface definitions
6534 * @param val change the values of den_mode in reg CTRL6_C
6535 * @retval interface status (MANDATORY: return 0 -> no Error)
6536 *
6537 */
lsm6dso32_den_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_den_mode_t val)6538 int32_t lsm6dso32_den_mode_set(const stmdev_ctx_t *ctx,
6539 lsm6dso32_den_mode_t val)
6540 {
6541 lsm6dso32_ctrl6_c_t reg;
6542 int32_t ret;
6543
6544 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6545
6546 if (ret == 0)
6547 {
6548 reg.den_mode = (uint8_t)val;
6549 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6550 }
6551
6552 return ret;
6553 }
6554
6555 /**
6556 * @brief DEN functionality marking mode.[get]
6557 *
6558 * @param ctx read / write interface definitions
6559 * @param val Get the values of den_mode in reg CTRL6_C
6560 * @retval interface status (MANDATORY: return 0 -> no Error)
6561 *
6562 */
lsm6dso32_den_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_den_mode_t * val)6563 int32_t lsm6dso32_den_mode_get(const stmdev_ctx_t *ctx,
6564 lsm6dso32_den_mode_t *val)
6565 {
6566 lsm6dso32_ctrl6_c_t reg;
6567 int32_t ret;
6568
6569 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6570
6571 switch (reg.den_mode)
6572 {
6573 case LSM6DSO32_DEN_DISABLE:
6574 *val = LSM6DSO32_DEN_DISABLE;
6575 break;
6576
6577 case LSM6DSO32_LEVEL_FIFO:
6578 *val = LSM6DSO32_LEVEL_FIFO;
6579 break;
6580
6581 case LSM6DSO32_LEVEL_LETCHED:
6582 *val = LSM6DSO32_LEVEL_LETCHED;
6583 break;
6584
6585 case LSM6DSO32_LEVEL_TRIGGER:
6586 *val = LSM6DSO32_LEVEL_TRIGGER;
6587 break;
6588
6589 case LSM6DSO32_EDGE_TRIGGER:
6590 *val = LSM6DSO32_EDGE_TRIGGER;
6591 break;
6592
6593 default:
6594 *val = LSM6DSO32_DEN_DISABLE;
6595 break;
6596 }
6597
6598 return ret;
6599 }
6600
6601 /**
6602 * @brief DEN active level configuration.[set]
6603 *
6604 * @param ctx read / write interface definitions
6605 * @param val change the values of den_lh in reg CTRL9_XL
6606 * @retval interface status (MANDATORY: return 0 -> no Error)
6607 *
6608 */
lsm6dso32_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dso32_den_lh_t val)6609 int32_t lsm6dso32_den_polarity_set(const stmdev_ctx_t *ctx,
6610 lsm6dso32_den_lh_t val)
6611 {
6612 lsm6dso32_ctrl9_xl_t reg;
6613 int32_t ret;
6614
6615 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6616
6617 if (ret == 0)
6618 {
6619 reg.den_lh = (uint8_t)val;
6620 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6621 }
6622
6623 return ret;
6624 }
6625
6626 /**
6627 * @brief DEN active level configuration.[get]
6628 *
6629 * @param ctx read / write interface definitions
6630 * @param val Get the values of den_lh in reg CTRL9_XL
6631 * @retval interface status (MANDATORY: return 0 -> no Error)
6632 *
6633 */
lsm6dso32_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dso32_den_lh_t * val)6634 int32_t lsm6dso32_den_polarity_get(const stmdev_ctx_t *ctx,
6635 lsm6dso32_den_lh_t *val)
6636 {
6637 lsm6dso32_ctrl9_xl_t reg;
6638 int32_t ret;
6639
6640 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6641
6642 switch (reg.den_lh)
6643 {
6644 case LSM6DSO32_DEN_ACT_LOW:
6645 *val = LSM6DSO32_DEN_ACT_LOW;
6646 break;
6647
6648 case LSM6DSO32_DEN_ACT_HIGH:
6649 *val = LSM6DSO32_DEN_ACT_HIGH;
6650 break;
6651
6652 default:
6653 *val = LSM6DSO32_DEN_ACT_LOW;
6654 break;
6655 }
6656
6657 return ret;
6658 }
6659
6660 /**
6661 * @brief DEN enable.[set]
6662 *
6663 * @param ctx read / write interface definitions
6664 * @param val change the values of den_xl_g in reg CTRL9_XL
6665 * @retval interface status (MANDATORY: return 0 -> no Error)
6666 *
6667 */
lsm6dso32_den_enable_set(const stmdev_ctx_t * ctx,lsm6dso32_den_xl_g_t val)6668 int32_t lsm6dso32_den_enable_set(const stmdev_ctx_t *ctx,
6669 lsm6dso32_den_xl_g_t val)
6670 {
6671 lsm6dso32_ctrl9_xl_t reg;
6672 int32_t ret;
6673
6674 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6675
6676 if (ret == 0)
6677 {
6678 reg.den_xl_g = (uint8_t)val;
6679 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6680 }
6681
6682 return ret;
6683 }
6684
6685 /**
6686 * @brief DEN enable.[get]
6687 *
6688 * @param ctx read / write interface definitions
6689 * @param val Get the values of den_xl_g in reg CTRL9_XL
6690 * @retval interface status (MANDATORY: return 0 -> no Error)
6691 *
6692 */
lsm6dso32_den_enable_get(const stmdev_ctx_t * ctx,lsm6dso32_den_xl_g_t * val)6693 int32_t lsm6dso32_den_enable_get(const stmdev_ctx_t *ctx,
6694 lsm6dso32_den_xl_g_t *val)
6695 {
6696 lsm6dso32_ctrl9_xl_t reg;
6697 int32_t ret;
6698
6699 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6700
6701 switch (reg.den_xl_g)
6702 {
6703 case LSM6DSO32_STAMP_IN_GY_DATA:
6704 *val = LSM6DSO32_STAMP_IN_GY_DATA;
6705 break;
6706
6707 case LSM6DSO32_STAMP_IN_XL_DATA:
6708 *val = LSM6DSO32_STAMP_IN_XL_DATA;
6709 break;
6710
6711 case LSM6DSO32_STAMP_IN_GY_XL_DATA:
6712 *val = LSM6DSO32_STAMP_IN_GY_XL_DATA;
6713 break;
6714
6715 default:
6716 *val = LSM6DSO32_STAMP_IN_GY_DATA;
6717 break;
6718 }
6719
6720 return ret;
6721 }
6722
6723 /**
6724 * @brief DEN value stored in LSB of X-axis.[set]
6725 *
6726 * @param ctx read / write interface definitions
6727 * @param val change the values of den_z in reg CTRL9_XL
6728 * @retval interface status (MANDATORY: return 0 -> no Error)
6729 *
6730 */
lsm6dso32_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)6731 int32_t lsm6dso32_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
6732 {
6733 lsm6dso32_ctrl9_xl_t reg;
6734 int32_t ret;
6735
6736 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6737
6738 if (ret == 0)
6739 {
6740 reg.den_z = val;
6741 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6742 }
6743
6744 return ret;
6745 }
6746
6747 /**
6748 * @brief DEN value stored in LSB of X-axis.[get]
6749 *
6750 * @param ctx read / write interface definitions
6751 * @param val change the values of den_z in reg CTRL9_XL
6752 * @retval interface status (MANDATORY: return 0 -> no Error)
6753 *
6754 */
lsm6dso32_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6755 int32_t lsm6dso32_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
6756 {
6757 lsm6dso32_ctrl9_xl_t reg;
6758 int32_t ret;
6759
6760 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6761 *val = reg.den_z;
6762
6763 return ret;
6764 }
6765
6766 /**
6767 * @brief DEN value stored in LSB of Y-axis.[set]
6768 *
6769 * @param ctx read / write interface definitions
6770 * @param val change the values of den_y in reg CTRL9_XL
6771 * @retval interface status (MANDATORY: return 0 -> no Error)
6772 *
6773 */
lsm6dso32_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)6774 int32_t lsm6dso32_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6775 {
6776 lsm6dso32_ctrl9_xl_t reg;
6777 int32_t ret;
6778
6779 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6780
6781 if (ret == 0)
6782 {
6783 reg.den_y = val;
6784 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6785 }
6786
6787 return ret;
6788 }
6789
6790 /**
6791 * @brief DEN value stored in LSB of Y-axis.[get]
6792 *
6793 * @param ctx read / write interface definitions
6794 * @param val change the values of den_y in reg CTRL9_XL
6795 * @retval interface status (MANDATORY: return 0 -> no Error)
6796 *
6797 */
lsm6dso32_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6798 int32_t lsm6dso32_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
6799 {
6800 lsm6dso32_ctrl9_xl_t reg;
6801 int32_t ret;
6802
6803 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6804 *val = reg.den_y;
6805
6806 return ret;
6807 }
6808
6809 /**
6810 * @brief DEN value stored in LSB of Z-axis.[set]
6811 *
6812 * @param ctx read / write interface definitions
6813 * @param val change the values of den_x in reg CTRL9_XL
6814 * @retval interface status (MANDATORY: return 0 -> no Error)
6815 *
6816 */
lsm6dso32_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)6817 int32_t lsm6dso32_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6818 {
6819 lsm6dso32_ctrl9_xl_t reg;
6820 int32_t ret;
6821
6822 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6823
6824 if (ret == 0)
6825 {
6826 reg.den_x = val;
6827 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6828 }
6829
6830 return ret;
6831 }
6832
6833 /**
6834 * @brief DEN value stored in LSB of Z-axis.[get]
6835 *
6836 * @param ctx read / write interface definitions
6837 * @param val change the values of den_x in reg CTRL9_XL
6838 * @retval interface status (MANDATORY: return 0 -> no Error)
6839 *
6840 */
lsm6dso32_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6841 int32_t lsm6dso32_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
6842 {
6843 lsm6dso32_ctrl9_xl_t reg;
6844 int32_t ret;
6845
6846 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6847 *val = reg.den_x;
6848
6849 return ret;
6850 }
6851
6852 /**
6853 * @}
6854 *
6855 */
6856
6857 /**
6858 * @defgroup LSM6DSO32_Pedometer
6859 * @brief This section groups all the functions that manage pedometer.
6860 * @{
6861 *
6862 */
6863
6864 /**
6865 * @brief Enable pedometer algorithm.[set]
6866 *
6867 * @param ctx read / write interface definitions
6868 * @param val turn on and configure pedometer
6869 * @retval interface status (MANDATORY: return 0 -> no Error)
6870 *
6871 */
lsm6dso32_pedo_sens_set(const stmdev_ctx_t * ctx,lsm6dso32_pedo_md_t val)6872 int32_t lsm6dso32_pedo_sens_set(const stmdev_ctx_t *ctx,
6873 lsm6dso32_pedo_md_t val)
6874 {
6875 lsm6dso32_emb_func_en_a_t emb_func_en_a;
6876 lsm6dso32_emb_func_en_b_t emb_func_en_b;
6877 lsm6dso32_pedo_cmd_reg_t pedo_cmd_reg;
6878 int32_t ret;
6879
6880 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
6881 (uint8_t *)&pedo_cmd_reg);
6882
6883 if (ret == 0)
6884 {
6885 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6886 }
6887
6888 if (ret == 0)
6889 {
6890 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
6891 (uint8_t *)&emb_func_en_a, 1);
6892 }
6893
6894 if (ret == 0)
6895 {
6896 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
6897 (uint8_t *)&emb_func_en_b, 1);
6898 emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
6899 emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1;
6900 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
6901 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
6902 }
6903
6904 if (ret == 0)
6905 {
6906 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
6907 (uint8_t *)&emb_func_en_a, 1);
6908 }
6909
6910 if (ret == 0)
6911 {
6912 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
6913 (uint8_t *)&emb_func_en_b, 1);
6914 }
6915
6916 if (ret == 0)
6917 {
6918 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6919 }
6920
6921 if (ret == 0)
6922 {
6923 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
6924 (uint8_t *)&pedo_cmd_reg);
6925 }
6926
6927 return ret;
6928 }
6929
6930 /**
6931 * @brief Enable pedometer algorithm.[get]
6932 *
6933 * @param ctx read / write interface definitions
6934 * @param val turn on and configure pedometer
6935 * @retval interface status (MANDATORY: return 0 -> no Error)
6936 *
6937 */
lsm6dso32_pedo_sens_get(const stmdev_ctx_t * ctx,lsm6dso32_pedo_md_t * val)6938 int32_t lsm6dso32_pedo_sens_get(const stmdev_ctx_t *ctx,
6939 lsm6dso32_pedo_md_t *val)
6940 {
6941 lsm6dso32_emb_func_en_a_t emb_func_en_a;
6942 lsm6dso32_emb_func_en_b_t emb_func_en_b;
6943 lsm6dso32_pedo_cmd_reg_t pedo_cmd_reg;
6944 int32_t ret;
6945
6946 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
6947 (uint8_t *)&pedo_cmd_reg);
6948
6949 if (ret == 0)
6950 {
6951 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6952 }
6953
6954 if (ret == 0)
6955 {
6956 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
6957 (uint8_t *)&emb_func_en_a, 1);
6958 }
6959
6960 if (ret == 0)
6961 {
6962 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
6963 (uint8_t *)&emb_func_en_b, 1);
6964 }
6965
6966 if (ret == 0)
6967 {
6968 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6969 }
6970
6971 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
6972 << 4) |
6973 (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en)
6974 {
6975 case LSM6DSO32_PEDO_DISABLE:
6976 *val = LSM6DSO32_PEDO_DISABLE;
6977 break;
6978
6979 case LSM6DSO32_PEDO_BASE_MODE:
6980 *val = LSM6DSO32_PEDO_BASE_MODE;
6981 break;
6982
6983 case LSM6DSO32_PEDO_ADV_MODE:
6984 *val = LSM6DSO32_PEDO_ADV_MODE;
6985 break;
6986
6987 case LSM6DSO32_FALSE_STEP_REJ:
6988 *val = LSM6DSO32_FALSE_STEP_REJ;
6989 break;
6990
6991 case LSM6DSO32_FALSE_STEP_REJ_ADV_MODE:
6992 *val = LSM6DSO32_FALSE_STEP_REJ_ADV_MODE;
6993 break;
6994
6995 default:
6996 *val = LSM6DSO32_PEDO_DISABLE;
6997 break;
6998 }
6999
7000 return ret;
7001 }
7002
7003 /**
7004 * @brief Interrupt status bit for step detection.[get]
7005 *
7006 * @param ctx read / write interface definitions
7007 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
7008 * @retval interface status (MANDATORY: return 0 -> no Error)
7009 *
7010 */
lsm6dso32_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)7011 int32_t lsm6dso32_pedo_step_detect_get(const stmdev_ctx_t *ctx,
7012 uint8_t *val)
7013 {
7014 lsm6dso32_emb_func_status_t reg;
7015 int32_t ret;
7016
7017 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7018
7019 if (ret == 0)
7020 {
7021 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7022 (uint8_t *)®, 1);
7023 }
7024
7025 if (ret == 0)
7026 {
7027 *val = reg.is_step_det;
7028 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7029 }
7030
7031 return ret;
7032 }
7033
7034 /**
7035 * @brief Pedometer debounce configuration register (r/w).[set]
7036 *
7037 * @param ctx read / write interface definitions
7038 * @param buff buffer that contains data to write
7039 * @retval interface status (MANDATORY: return 0 -> no Error)
7040 *
7041 */
lsm6dso32_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)7042 int32_t lsm6dso32_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
7043 uint8_t *buff)
7044 {
7045 int32_t ret;
7046
7047 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
7048 buff);
7049
7050 return ret;
7051 }
7052
7053 /**
7054 * @brief Pedometer debounce configuration register (r/w).[get]
7055 *
7056 * @param ctx read / write interface definitions
7057 * @param buff buffer that stores data read
7058 * @retval interface status (MANDATORY: return 0 -> no Error)
7059 *
7060 */
lsm6dso32_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)7061 int32_t lsm6dso32_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
7062 uint8_t *buff)
7063 {
7064 int32_t ret;
7065
7066 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
7067 buff);
7068
7069 return ret;
7070 }
7071
7072 /**
7073 * @brief Time period register for step detection on delta time (r/w).[set]
7074 *
7075 * @param ctx read / write interface definitions
7076 * @param buff buffer that contains data to write
7077 * @retval interface status (MANDATORY: return 0 -> no Error)
7078 *
7079 */
lsm6dso32_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)7080 int32_t lsm6dso32_pedo_steps_period_set(const stmdev_ctx_t *ctx,
7081 uint16_t val)
7082 {
7083 uint8_t buff[2];
7084 int32_t ret;
7085
7086 buff[1] = (uint8_t)(val / 256U);
7087 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7088 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
7089 &buff[0]);
7090
7091 if (ret == 0)
7092 {
7093 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
7094 &buff[1]);
7095 }
7096
7097 return ret;
7098 }
7099
7100 /**
7101 * @brief Time period register for step detection on delta time (r/w).[get]
7102 *
7103 * @param ctx read / write interface definitions
7104 * @param buff buffer that stores data read
7105 * @retval interface status (MANDATORY: return 0 -> no Error)
7106 *
7107 */
lsm6dso32_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)7108 int32_t lsm6dso32_pedo_steps_period_get(const stmdev_ctx_t *ctx,
7109 uint16_t *val)
7110 {
7111 uint8_t buff[2];
7112 int32_t ret;
7113
7114 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
7115 &buff[0]);
7116
7117 if (ret == 0)
7118 {
7119 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
7120 &buff[1]);
7121 *val = buff[1];
7122 *val = (*val * 256U) + buff[0];
7123 }
7124
7125 return ret;
7126 }
7127
7128 /**
7129 * @brief Set when user wants to generate interrupt on count overflow
7130 * event/every step.[set]
7131 *
7132 * @param ctx read / write interface definitions
7133 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
7134 * @retval interface status (MANDATORY: return 0 -> no Error)
7135 *
7136 */
lsm6dso32_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_carry_count_en_t val)7137 int32_t lsm6dso32_pedo_int_mode_set(const stmdev_ctx_t *ctx,
7138 lsm6dso32_carry_count_en_t val)
7139 {
7140 lsm6dso32_pedo_cmd_reg_t reg;
7141 int32_t ret;
7142
7143 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7144 (uint8_t *)®);
7145
7146 if (ret == 0)
7147 {
7148 reg.carry_count_en = (uint8_t)val;
7149 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7150 (uint8_t *)®);
7151 }
7152
7153 return ret;
7154 }
7155
7156 /**
7157 * @brief Set when user wants to generate interrupt on count overflow
7158 * event/every step.[get]
7159 *
7160 * @param ctx read / write interface definitions
7161 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
7162 * @retval interface status (MANDATORY: return 0 -> no Error)
7163 *
7164 */
lsm6dso32_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_carry_count_en_t * val)7165 int32_t lsm6dso32_pedo_int_mode_get(const stmdev_ctx_t *ctx,
7166 lsm6dso32_carry_count_en_t *val)
7167 {
7168 lsm6dso32_pedo_cmd_reg_t reg;
7169 int32_t ret;
7170
7171 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7172 (uint8_t *)®);
7173
7174 switch (reg.carry_count_en)
7175 {
7176 case LSM6DSO32_EVERY_STEP:
7177 *val = LSM6DSO32_EVERY_STEP;
7178 break;
7179
7180 case LSM6DSO32_COUNT_OVERFLOW:
7181 *val = LSM6DSO32_COUNT_OVERFLOW;
7182 break;
7183
7184 default:
7185 *val = LSM6DSO32_EVERY_STEP;
7186 break;
7187 }
7188
7189 return ret;
7190 }
7191
7192 /**
7193 * @}
7194 *
7195 */
7196
7197 /**
7198 * @defgroup LSM6DSO32_significant_motion
7199 * @brief This section groups all the functions that manage the
7200 * significant motion detection.
7201 * @{
7202 *
7203 */
7204
7205 /**
7206 * @brief Enable significant motion detection function.[set]
7207 *
7208 * @param ctx read / write interface definitions
7209 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
7210 * @retval interface status (MANDATORY: return 0 -> no Error)
7211 *
7212 */
lsm6dso32_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)7213 int32_t lsm6dso32_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
7214 {
7215 lsm6dso32_emb_func_en_a_t reg;
7216 int32_t ret;
7217
7218 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7219
7220 if (ret == 0)
7221 {
7222 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7223 (uint8_t *)®, 1);
7224 }
7225
7226 if (ret == 0)
7227 {
7228 reg.sign_motion_en = val;
7229 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7230 (uint8_t *)®, 1);
7231 }
7232
7233 if (ret == 0)
7234 {
7235 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7236 }
7237
7238 return ret;
7239 }
7240
7241 /**
7242 * @brief Enable significant motion detection function.[get]
7243 *
7244 * @param ctx read / write interface definitions
7245 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
7246 * @retval interface status (MANDATORY: return 0 -> no Error)
7247 *
7248 */
lsm6dso32_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)7249 int32_t lsm6dso32_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
7250 {
7251 lsm6dso32_emb_func_en_a_t reg;
7252 int32_t ret;
7253
7254 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7255
7256 if (ret == 0)
7257 {
7258 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7259 (uint8_t *)®, 1);
7260 }
7261
7262 if (ret == 0)
7263 {
7264 *val = reg.sign_motion_en;
7265 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7266 }
7267
7268 return ret;
7269 }
7270
7271 /**
7272 * @brief Interrupt status bit for significant motion detection.[get]
7273 *
7274 * @param ctx read / write interface definitions
7275 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
7276 * @retval interface status (MANDATORY: return 0 -> no Error)
7277 *
7278 */
lsm6dso32_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7279 int32_t lsm6dso32_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
7280 uint8_t *val)
7281 {
7282 lsm6dso32_emb_func_status_t reg;
7283 int32_t ret;
7284
7285 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7286
7287 if (ret == 0)
7288 {
7289 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7290 (uint8_t *)®, 1);
7291 }
7292
7293 if (ret == 0)
7294 {
7295 *val = reg.is_sigmot;
7296 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7297 }
7298
7299 return ret;
7300 }
7301
7302 /**
7303 * @}
7304 *
7305 */
7306
7307 /**
7308 * @defgroup LSM6DSO32_tilt_detection
7309 * @brief This section groups all the functions that manage the tilt
7310 * event detection.
7311 * @{
7312 *
7313 */
7314
7315 /**
7316 * @brief Enable tilt calculation.[set]
7317 *
7318 * @param ctx read / write interface definitions
7319 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
7320 * @retval interface status (MANDATORY: return 0 -> no Error)
7321 *
7322 */
lsm6dso32_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)7323 int32_t lsm6dso32_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
7324 {
7325 lsm6dso32_emb_func_en_a_t reg;
7326 int32_t ret;
7327
7328 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7329
7330 if (ret == 0)
7331 {
7332 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7333 (uint8_t *)®, 1);
7334 }
7335
7336 if (ret == 0)
7337 {
7338 reg.tilt_en = val;
7339 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7340 (uint8_t *)®, 1);
7341 }
7342
7343 if (ret == 0)
7344 {
7345 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7346 }
7347
7348 return ret;
7349 }
7350
7351 /**
7352 * @brief Enable tilt calculation.[get]
7353 *
7354 * @param ctx read / write interface definitions
7355 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
7356 * @retval interface status (MANDATORY: return 0 -> no Error)
7357 *
7358 */
lsm6dso32_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)7359 int32_t lsm6dso32_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
7360 {
7361 lsm6dso32_emb_func_en_a_t reg;
7362 int32_t ret;
7363
7364 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7365
7366 if (ret == 0)
7367 {
7368 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7369 (uint8_t *)®, 1);
7370 }
7371
7372 if (ret == 0)
7373 {
7374 *val = reg.tilt_en;
7375 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7376 }
7377
7378 return ret;
7379 }
7380
7381 /**
7382 * @brief Interrupt status bit for tilt detection.[get]
7383 *
7384 * @param ctx read / write interface definitions
7385 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
7386 * @retval interface status (MANDATORY: return 0 -> no Error)
7387 *
7388 */
lsm6dso32_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7389 int32_t lsm6dso32_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
7390 uint8_t *val)
7391 {
7392 lsm6dso32_emb_func_status_t reg;
7393 int32_t ret;
7394
7395 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7396
7397 if (ret == 0)
7398 {
7399 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7400 (uint8_t *)®, 1);
7401 }
7402
7403 if (ret == 0)
7404 {
7405 *val = reg.is_tilt;
7406 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7407 }
7408
7409 return ret;
7410 }
7411
7412 /**
7413 * @}
7414 *
7415 */
7416
7417 /**
7418 * @defgroup LSM6DSO32_ magnetometer_sensor
7419 * @brief This section groups all the functions that manage additional
7420 * magnetometer sensor.
7421 * @{
7422 *
7423 */
7424
7425 /**
7426 * @brief External magnetometer sensitivity value register.[set]
7427 *
7428 * @param ctx read / write interface definitions
7429 * @param buff buffer that contains data to write
7430 * @retval interface status (MANDATORY: return 0 -> no Error)
7431 *
7432 */
lsm6dso32_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7433 int32_t lsm6dso32_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7434 {
7435 uint8_t buff[2];
7436 int32_t ret;
7437
7438 buff[1] = (uint8_t)(val / 256U);
7439 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7440 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
7441 &buff[0]);
7442
7443 if (ret == 0)
7444 {
7445 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
7446 &buff[1]);
7447 }
7448
7449 return ret;
7450 }
7451
7452 /**
7453 * @brief External magnetometer sensitivity value register.[get]
7454 *
7455 * @param ctx read / write interface definitions
7456 * @param buff buffer that stores data read
7457 * @retval interface status (MANDATORY: return 0 -> no Error)
7458 *
7459 */
lsm6dso32_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7460 int32_t lsm6dso32_mag_sensitivity_get(const stmdev_ctx_t *ctx,
7461 uint16_t *val)
7462 {
7463 uint8_t buff[2];
7464 int32_t ret;
7465
7466 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
7467 &buff[0]);
7468
7469 if (ret == 0)
7470 {
7471 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
7472 &buff[1]);
7473 *val = buff[1];
7474 *val = (*val * 256U) + buff[0];
7475 }
7476
7477 return ret;
7478 }
7479
7480 /**
7481 * @brief Offset for hard-iron compensation register (r/w).[set]
7482 *
7483 * @param ctx read / write interface definitions
7484 * @param buff buffer that contains data to write
7485 * @retval interface status (MANDATORY: return 0 -> no Error)
7486 *
7487 */
lsm6dso32_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)7488 int32_t lsm6dso32_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
7489 {
7490 uint8_t buff[6];
7491 int32_t ret;
7492
7493 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7494 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7495 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7496 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7497 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7498 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7499 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_L,
7500 &buff[0]);
7501
7502 if (ret == 0)
7503 {
7504 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_H,
7505 &buff[1]);
7506 }
7507
7508 if (ret == 0)
7509 {
7510 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_L,
7511 &buff[2]);
7512 }
7513
7514 if (ret == 0)
7515 {
7516 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_H,
7517 &buff[3]);
7518 }
7519
7520 if (ret == 0)
7521 {
7522 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
7523 &buff[4]);
7524 }
7525
7526 if (ret == 0)
7527 {
7528 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
7529 &buff[5]);
7530 }
7531
7532 return ret;
7533 }
7534
7535 /**
7536 * @brief Offset for hard-iron compensation register (r/w).[get]
7537 *
7538 * @param ctx read / write interface definitions
7539 * @param buff buffer that stores data read
7540 * @retval interface status (MANDATORY: return 0 -> no Error)
7541 *
7542 */
lsm6dso32_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)7543 int32_t lsm6dso32_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
7544 {
7545 uint8_t buff[6];
7546 int32_t ret;
7547
7548 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_L,
7549 &buff[0]);
7550
7551 if (ret == 0)
7552 {
7553 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_H,
7554 &buff[1]);
7555 }
7556
7557 if (ret == 0)
7558 {
7559 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_L,
7560 &buff[2]);
7561 }
7562
7563 if (ret == 0)
7564 {
7565 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_H,
7566 &buff[3]);
7567 }
7568
7569 if (ret == 0)
7570 {
7571 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
7572 &buff[4]);
7573 }
7574
7575 if (ret == 0)
7576 {
7577 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
7578 &buff[5]);
7579 val[0] = (int16_t)buff[1];
7580 val[0] = (val[0] * 256) + (int16_t)buff[0];
7581 val[1] = (int16_t)buff[3];
7582 val[1] = (val[1] * 256) + (int16_t)buff[2];
7583 val[2] = (int16_t)buff[5];
7584 val[2] = (val[2] * 256) + (int16_t)buff[4];
7585 }
7586
7587 return ret;
7588 }
7589
7590 /**
7591 * @brief Soft-iron (3x3 symmetric) matrix correction
7592 * register (r/w). The value is expressed as
7593 * half-precision floating-point format:
7594 * SEEEEEFFFFFFFFFF
7595 * S: 1 sign bit;
7596 * E: 5 exponent bits;
7597 * F: 10 fraction bits).[set]
7598 *
7599 * @param ctx read / write interface definitions
7600 * @param buff buffer that contains data to write
7601 * @retval interface status (MANDATORY: return 0 -> no Error)
7602 *
7603 */
lsm6dso32_mag_soft_iron_set(const stmdev_ctx_t * ctx,int16_t * val)7604 int32_t lsm6dso32_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val)
7605 {
7606 uint8_t buff[12];
7607 int32_t ret;
7608
7609 uint8_t index;
7610 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7611 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7612 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7613 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7614 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7615 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7616 buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
7617 buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
7618 buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
7619 buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
7620 buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
7621 buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
7622 index = 0x00U;
7623 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
7624 &buff[index]);
7625
7626 if (ret == 0)
7627 {
7628 index++;
7629 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
7630 &buff[index]);
7631 }
7632
7633 if (ret == 0)
7634 {
7635 index++;
7636 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
7637 &buff[index]);
7638 }
7639
7640 if (ret == 0)
7641 {
7642 index++;
7643 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
7644 &buff[index]);
7645 }
7646
7647 if (ret == 0)
7648 {
7649 index++;
7650 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
7651 &buff[index]);
7652 }
7653
7654 if (ret == 0)
7655 {
7656 index++;
7657 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
7658 &buff[index]);
7659 }
7660
7661 if (ret == 0)
7662 {
7663 index++;
7664 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
7665 &buff[index]);
7666 }
7667
7668 if (ret == 0)
7669 {
7670 index++;
7671 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
7672 &buff[index]);
7673 }
7674
7675 if (ret == 0)
7676 {
7677 index++;
7678 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
7679 &buff[index]);
7680 }
7681
7682 if (ret == 0)
7683 {
7684 index++;
7685 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
7686 &buff[index]);
7687 }
7688
7689 if (ret == 0)
7690 {
7691 index++;
7692 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
7693 &buff[index]);
7694 }
7695
7696 if (ret == 0)
7697 {
7698 index++;
7699 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
7700 &buff[index]);
7701 }
7702
7703 return ret;
7704 }
7705
7706 /**
7707 * @brief Soft-iron (3x3 symmetric) matrix
7708 * correction register (r/w).
7709 * The value is expressed as half-precision
7710 * floating-point format:
7711 * SEEEEEFFFFFFFFFF
7712 * S: 1 sign bit;
7713 * E: 5 exponent bits;
7714 * F: 10 fraction bits.[get]
7715 *
7716 * @param ctx read / write interface definitions
7717 * @param buff buffer that stores data read
7718 * @retval interface status (MANDATORY: return 0 -> no Error)
7719 *
7720 */
lsm6dso32_mag_soft_iron_get(const stmdev_ctx_t * ctx,int16_t * val)7721 int32_t lsm6dso32_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val)
7722 {
7723 uint8_t buff[12];
7724 int32_t ret;
7725
7726 uint8_t index;
7727 index = 0x00U;
7728 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
7729 &buff[index]);
7730
7731 if (ret == 0)
7732 {
7733 index++;
7734 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
7735 &buff[index]);
7736 }
7737
7738 if (ret == 0)
7739 {
7740 index++;
7741 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
7742 &buff[index]);
7743 }
7744
7745 if (ret == 0)
7746 {
7747 index++;
7748 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
7749 &buff[index]);
7750 }
7751
7752 if (ret == 0)
7753 {
7754 index++;
7755 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
7756 &buff[index]);
7757 }
7758
7759 if (ret == 0)
7760 {
7761 index++;
7762 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
7763 &buff[index]);
7764 }
7765
7766 if (ret == 0)
7767 {
7768 index++;
7769 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
7770 &buff[index]);
7771 }
7772
7773 if (ret == 0)
7774 {
7775 index++;
7776 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
7777 &buff[index]);
7778 }
7779
7780 if (ret == 0)
7781 {
7782 index++;
7783 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
7784 &buff[index]);
7785 }
7786
7787 if (ret == 0)
7788 {
7789 index++;
7790 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
7791 &buff[index]);
7792 }
7793
7794 if (ret == 0)
7795 {
7796 index++;
7797 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
7798 &buff[index]);
7799 }
7800
7801 if (ret == 0)
7802 {
7803 index++;
7804 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
7805 &buff[index]);
7806 }
7807
7808 val[0] = (int16_t)buff[1];
7809 val[0] = (val[0] * 256) + (int16_t)buff[0];
7810 val[1] = (int16_t)buff[3];
7811 val[1] = (val[1] * 256) + (int16_t)buff[2];
7812 val[2] = (int16_t)buff[5];
7813 val[2] = (val[2] * 256) + (int16_t)buff[4];
7814 val[3] = (int16_t)buff[7];
7815 val[3] = (val[3] * 256) + (int16_t)buff[6];
7816 val[4] = (int16_t)buff[9];
7817 val[4] = (val[4] * 256) + (int16_t)buff[8];
7818 val[5] = (int16_t)buff[11];
7819 val[5] = (val[5] * 256) + (int16_t)buff[10];
7820
7821 return ret;
7822 }
7823
7824 /**
7825 * @brief Magnetometer Z-axis coordinates
7826 * rotation (to be aligned to
7827 * accelerometer/gyroscope axes
7828 * orientation).[set]
7829 *
7830 * @param ctx read / write interface definitions
7831 * @param val change the values of mag_z_axis in reg MAG_CFG_A
7832 * @retval interface status (MANDATORY: return 0 -> no Error)
7833 *
7834 */
lsm6dso32_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dso32_mag_z_axis_t val)7835 int32_t lsm6dso32_mag_z_orient_set(const stmdev_ctx_t *ctx,
7836 lsm6dso32_mag_z_axis_t val)
7837 {
7838 lsm6dso32_mag_cfg_a_t reg;
7839 int32_t ret;
7840
7841 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7842 (uint8_t *)®);
7843
7844 if (ret == 0)
7845 {
7846 reg.mag_z_axis = (uint8_t) val;
7847 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
7848 (uint8_t *)®);
7849 }
7850
7851 return ret;
7852 }
7853
7854 /**
7855 * @brief Magnetometer Z-axis coordinates
7856 * rotation (to be aligned to
7857 * accelerometer/gyroscope axes
7858 * orientation).[get]
7859 *
7860 * @param ctx read / write interface definitions
7861 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
7862 * @retval interface status (MANDATORY: return 0 -> no Error)
7863 *
7864 */
lsm6dso32_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dso32_mag_z_axis_t * val)7865 int32_t lsm6dso32_mag_z_orient_get(const stmdev_ctx_t *ctx,
7866 lsm6dso32_mag_z_axis_t *val)
7867 {
7868 lsm6dso32_mag_cfg_a_t reg;
7869 int32_t ret;
7870
7871 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7872 (uint8_t *)®);
7873
7874 switch (reg.mag_z_axis)
7875 {
7876 case LSM6DSO32_Z_EQ_Y:
7877 *val = LSM6DSO32_Z_EQ_Y;
7878 break;
7879
7880 case LSM6DSO32_Z_EQ_MIN_Y:
7881 *val = LSM6DSO32_Z_EQ_MIN_Y;
7882 break;
7883
7884 case LSM6DSO32_Z_EQ_X:
7885 *val = LSM6DSO32_Z_EQ_X;
7886 break;
7887
7888 case LSM6DSO32_Z_EQ_MIN_X:
7889 *val = LSM6DSO32_Z_EQ_MIN_X;
7890 break;
7891
7892 case LSM6DSO32_Z_EQ_MIN_Z:
7893 *val = LSM6DSO32_Z_EQ_MIN_Z;
7894 break;
7895
7896 case LSM6DSO32_Z_EQ_Z:
7897 *val = LSM6DSO32_Z_EQ_Z;
7898 break;
7899
7900 default:
7901 *val = LSM6DSO32_Z_EQ_Y;
7902 break;
7903 }
7904
7905 return ret;
7906 }
7907
7908 /**
7909 * @brief Magnetometer Y-axis coordinates
7910 * rotation (to be aligned to
7911 * accelerometer/gyroscope axes
7912 * orientation).[set]
7913 *
7914 * @param ctx read / write interface definitions
7915 * @param val change the values of mag_y_axis in reg MAG_CFG_A
7916 * @retval interface status (MANDATORY: return 0 -> no Error)
7917 *
7918 */
lsm6dso32_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dso32_mag_y_axis_t val)7919 int32_t lsm6dso32_mag_y_orient_set(const stmdev_ctx_t *ctx,
7920 lsm6dso32_mag_y_axis_t val)
7921 {
7922 lsm6dso32_mag_cfg_a_t reg;
7923 int32_t ret;
7924
7925 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7926 (uint8_t *)®);
7927
7928 if (ret == 0)
7929 {
7930 reg.mag_y_axis = (uint8_t)val;
7931 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
7932 (uint8_t *) ®);
7933 }
7934
7935 return ret;
7936 }
7937
7938 /**
7939 * @brief Magnetometer Y-axis coordinates
7940 * rotation (to be aligned to
7941 * accelerometer/gyroscope axes
7942 * orientation).[get]
7943 *
7944 * @param ctx read / write interface definitions
7945 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
7946 * @retval interface status (MANDATORY: return 0 -> no Error)
7947 *
7948 */
lsm6dso32_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dso32_mag_y_axis_t * val)7949 int32_t lsm6dso32_mag_y_orient_get(const stmdev_ctx_t *ctx,
7950 lsm6dso32_mag_y_axis_t *val)
7951 {
7952 lsm6dso32_mag_cfg_a_t reg;
7953 int32_t ret;
7954
7955 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7956 (uint8_t *)®);
7957
7958 switch (reg.mag_y_axis)
7959 {
7960 case LSM6DSO32_Y_EQ_Y:
7961 *val = LSM6DSO32_Y_EQ_Y;
7962 break;
7963
7964 case LSM6DSO32_Y_EQ_MIN_Y:
7965 *val = LSM6DSO32_Y_EQ_MIN_Y;
7966 break;
7967
7968 case LSM6DSO32_Y_EQ_X:
7969 *val = LSM6DSO32_Y_EQ_X;
7970 break;
7971
7972 case LSM6DSO32_Y_EQ_MIN_X:
7973 *val = LSM6DSO32_Y_EQ_MIN_X;
7974 break;
7975
7976 case LSM6DSO32_Y_EQ_MIN_Z:
7977 *val = LSM6DSO32_Y_EQ_MIN_Z;
7978 break;
7979
7980 case LSM6DSO32_Y_EQ_Z:
7981 *val = LSM6DSO32_Y_EQ_Z;
7982 break;
7983
7984 default:
7985 *val = LSM6DSO32_Y_EQ_Y;
7986 break;
7987 }
7988
7989 return ret;
7990 }
7991
7992 /**
7993 * @brief Magnetometer X-axis coordinates
7994 * rotation (to be aligned to
7995 * accelerometer/gyroscope axes
7996 * orientation).[set]
7997 *
7998 * @param ctx read / write interface definitions
7999 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8000 * @retval interface status (MANDATORY: return 0 -> no Error)
8001 *
8002 */
lsm6dso32_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dso32_mag_x_axis_t val)8003 int32_t lsm6dso32_mag_x_orient_set(const stmdev_ctx_t *ctx,
8004 lsm6dso32_mag_x_axis_t val)
8005 {
8006 lsm6dso32_mag_cfg_b_t reg;
8007 int32_t ret;
8008
8009 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
8010 (uint8_t *)®);
8011
8012 if (ret == 0)
8013 {
8014 reg.mag_x_axis = (uint8_t)val;
8015 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_B,
8016 (uint8_t *)®);
8017 }
8018
8019 return ret;
8020 }
8021
8022 /**
8023 * @brief Magnetometer X-axis coordinates
8024 * rotation (to be aligned to
8025 * accelerometer/gyroscope axes
8026 * orientation).[get]
8027 *
8028 * @param ctx read / write interface definitions
8029 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8030 * @retval interface status (MANDATORY: return 0 -> no Error)
8031 *
8032 */
lsm6dso32_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dso32_mag_x_axis_t * val)8033 int32_t lsm6dso32_mag_x_orient_get(const stmdev_ctx_t *ctx,
8034 lsm6dso32_mag_x_axis_t *val)
8035 {
8036 lsm6dso32_mag_cfg_b_t reg;
8037 int32_t ret;
8038
8039 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
8040 (uint8_t *)®);
8041
8042 switch (reg.mag_x_axis)
8043 {
8044 case LSM6DSO32_X_EQ_Y:
8045 *val = LSM6DSO32_X_EQ_Y;
8046 break;
8047
8048 case LSM6DSO32_X_EQ_MIN_Y:
8049 *val = LSM6DSO32_X_EQ_MIN_Y;
8050 break;
8051
8052 case LSM6DSO32_X_EQ_X:
8053 *val = LSM6DSO32_X_EQ_X;
8054 break;
8055
8056 case LSM6DSO32_X_EQ_MIN_X:
8057 *val = LSM6DSO32_X_EQ_MIN_X;
8058 break;
8059
8060 case LSM6DSO32_X_EQ_MIN_Z:
8061 *val = LSM6DSO32_X_EQ_MIN_Z;
8062 break;
8063
8064 case LSM6DSO32_X_EQ_Z:
8065 *val = LSM6DSO32_X_EQ_Z;
8066 break;
8067
8068 default:
8069 *val = LSM6DSO32_X_EQ_Y;
8070 break;
8071 }
8072
8073 return ret;
8074 }
8075
8076 /**
8077 * @}
8078 *
8079 */
8080
8081 /**
8082 * @defgroup LSM6DSO32_finite_state_machine
8083 * @brief This section groups all the functions that manage the
8084 * state_machine.
8085 * @{
8086 *
8087 */
8088
8089 /**
8090 * @brief Interrupt status bit for FSM long counter
8091 * timeout interrupt event.[get]
8092 *
8093 * @param ctx read / write interface definitions
8094 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
8095 * @retval interface status (MANDATORY: return 0 -> no Error)
8096 *
8097 */
lsm6dso32_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8098 int32_t lsm6dso32_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
8099 uint8_t *val)
8100 {
8101 lsm6dso32_emb_func_status_t reg;
8102 int32_t ret;
8103
8104 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8105
8106 if (ret == 0)
8107 {
8108 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
8109 (uint8_t *)®, 1);
8110 }
8111
8112 if (ret == 0)
8113 {
8114 *val = reg.is_fsm_lc;
8115 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8116 }
8117
8118 return ret;
8119 }
8120
8121 /**
8122 * @brief Final State Machine global enable.[set]
8123 *
8124 * @param ctx read / write interface definitions
8125 * @param val change the values of fsm_en in reg EMB_FUNC_EN_B
8126 * @retval interface status (MANDATORY: return 0 -> no Error)
8127 *
8128 */
lsm6dso32_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)8129 int32_t lsm6dso32_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
8130 {
8131 int32_t ret;
8132
8133 lsm6dso32_emb_func_en_b_t reg;
8134 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8135
8136 if (ret == 0)
8137 {
8138 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8139 (uint8_t *)®, 1);
8140 }
8141
8142 if (ret == 0)
8143 {
8144 reg.fsm_en = val;
8145 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8146 (uint8_t *)®, 1);
8147 }
8148
8149 if (ret == 0)
8150 {
8151 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8152 }
8153
8154 return ret;
8155 }
8156
8157 /**
8158 * @brief Final State Machine global enable.[get]
8159 *
8160 * @param ctx read / write interface definitions
8161 * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
8162 * @retval interface status (MANDATORY: return 0 -> no Error)
8163 *
8164 */
lsm6dso32_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)8165 int32_t lsm6dso32_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
8166 {
8167 int32_t ret;
8168
8169 lsm6dso32_emb_func_en_b_t reg;
8170 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8171
8172 if (ret == 0)
8173 {
8174 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8175 (uint8_t *)®, 1);
8176 }
8177
8178 if (ret == 0)
8179 {
8180 *val = reg.fsm_en;
8181 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8182 (uint8_t *)®, 1);
8183 }
8184
8185 if (ret == 0)
8186 {
8187 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8188 }
8189
8190 return ret;
8191 }
8192
8193 /**
8194 * @brief Final State Machine enable.[set]
8195 *
8196 * @param ctx read / write interface definitions
8197 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8198 * @retval interface status (MANDATORY: return 0 -> no Error)
8199 *
8200 */
lsm6dso32_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dso32_emb_fsm_enable_t * val)8201 int32_t lsm6dso32_fsm_enable_set(const stmdev_ctx_t *ctx,
8202 lsm6dso32_emb_fsm_enable_t *val)
8203 {
8204 int32_t ret;
8205
8206 lsm6dso32_emb_func_en_b_t reg;
8207 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8208
8209 if (ret == 0)
8210 {
8211 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_A,
8212 (uint8_t *)&val->fsm_enable_a, 1);
8213 }
8214
8215 if (ret == 0)
8216 {
8217 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_B,
8218 (uint8_t *)&val->fsm_enable_b, 1);
8219 }
8220
8221 if (ret == 0)
8222 {
8223 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8224 (uint8_t *)®, 1);
8225 }
8226
8227 if (ret == 0)
8228 {
8229 if ((val->fsm_enable_a.fsm1_en |
8230 val->fsm_enable_a.fsm2_en |
8231 val->fsm_enable_a.fsm3_en |
8232 val->fsm_enable_a.fsm4_en |
8233 val->fsm_enable_a.fsm5_en |
8234 val->fsm_enable_a.fsm6_en |
8235 val->fsm_enable_a.fsm7_en |
8236 val->fsm_enable_a.fsm8_en |
8237 val->fsm_enable_b.fsm9_en |
8238 val->fsm_enable_b.fsm10_en |
8239 val->fsm_enable_b.fsm11_en |
8240 val->fsm_enable_b.fsm12_en |
8241 val->fsm_enable_b.fsm13_en |
8242 val->fsm_enable_b.fsm14_en |
8243 val->fsm_enable_b.fsm15_en |
8244 val->fsm_enable_b.fsm16_en)
8245 != PROPERTY_DISABLE)
8246 {
8247 reg.fsm_en = PROPERTY_ENABLE;
8248 }
8249
8250 else
8251 {
8252 reg.fsm_en = PROPERTY_DISABLE;
8253 }
8254
8255 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8256 (uint8_t *)®, 1);
8257 }
8258
8259 if (ret == 0)
8260 {
8261 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8262 }
8263
8264 return ret;
8265 }
8266
8267 /**
8268 * @brief Final State Machine enable.[get]
8269 *
8270 * @param ctx read / write interface definitions
8271 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8272 * @retval interface status (MANDATORY: return 0 -> no Error)
8273 *
8274 */
lsm6dso32_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dso32_emb_fsm_enable_t * val)8275 int32_t lsm6dso32_fsm_enable_get(const stmdev_ctx_t *ctx,
8276 lsm6dso32_emb_fsm_enable_t *val)
8277 {
8278 int32_t ret;
8279
8280 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8281
8282 if (ret == 0)
8283 {
8284 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_ENABLE_A, (uint8_t *) val,
8285 2);
8286 }
8287
8288 if (ret == 0)
8289 {
8290 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8291 }
8292
8293 return ret;
8294 }
8295
8296 /**
8297 * @brief FSM long counter status register. Long counter value is an
8298 * unsigned integer value (16-bit format).[set]
8299 *
8300 * @param ctx read / write interface definitions
8301 * @param buff buffer that contains data to write
8302 * @retval interface status (MANDATORY: return 0 -> no Error)
8303 *
8304 */
lsm6dso32_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)8305 int32_t lsm6dso32_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
8306 {
8307 uint8_t buff[2];
8308 int32_t ret;
8309
8310 buff[1] = (uint8_t)(val / 256U);
8311 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8312 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8313
8314 if (ret == 0)
8315 {
8316 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
8317 }
8318
8319 if (ret == 0)
8320 {
8321 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8322 }
8323
8324 return ret;
8325 }
8326
8327 /**
8328 * @brief FSM long counter status register. Long counter value is an
8329 * unsigned integer value (16-bit format).[get]
8330 *
8331 * @param ctx read / write interface definitions
8332 * @param buff buffer that stores data read
8333 * @retval interface status (MANDATORY: return 0 -> no Error)
8334 *
8335 */
lsm6dso32_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)8336 int32_t lsm6dso32_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
8337 {
8338 uint8_t buff[2];
8339 int32_t ret;
8340
8341 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8342
8343 if (ret == 0)
8344 {
8345 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
8346 }
8347
8348 if (ret == 0)
8349 {
8350 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8351 *val = buff[1];
8352 *val = (*val * 256U) + buff[0];
8353 }
8354
8355 return ret;
8356 }
8357
8358 /**
8359 * @brief Clear FSM long counter value.[set]
8360 *
8361 * @param ctx read / write interface definitions
8362 * @param val change the values of fsm_lc_clr in
8363 * reg FSM_LONG_COUNTER_CLEAR
8364 * @retval interface status (MANDATORY: return 0 -> no Error)
8365 *
8366 */
lsm6dso32_long_clr_set(const stmdev_ctx_t * ctx,lsm6dso32_fsm_lc_clr_t val)8367 int32_t lsm6dso32_long_clr_set(const stmdev_ctx_t *ctx,
8368 lsm6dso32_fsm_lc_clr_t val)
8369 {
8370 lsm6dso32_fsm_long_counter_clear_t reg;
8371 int32_t ret;
8372
8373 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8374
8375 if (ret == 0)
8376 {
8377 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8378 (uint8_t *)®, 1);
8379 }
8380
8381 if (ret == 0)
8382 {
8383 reg. fsm_lc_clr = (uint8_t)val;
8384 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8385 (uint8_t *)®, 1);
8386 }
8387
8388 if (ret == 0)
8389 {
8390 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8391 }
8392
8393 return ret;
8394 }
8395
8396 /**
8397 * @brief Clear FSM long counter value.[get]
8398 *
8399 * @param ctx read / write interface definitions
8400 * @param val Get the values of fsm_lc_clr in
8401 * reg FSM_LONG_COUNTER_CLEAR
8402 * @retval interface status (MANDATORY: return 0 -> no Error)
8403 *
8404 */
lsm6dso32_long_clr_get(const stmdev_ctx_t * ctx,lsm6dso32_fsm_lc_clr_t * val)8405 int32_t lsm6dso32_long_clr_get(const stmdev_ctx_t *ctx,
8406 lsm6dso32_fsm_lc_clr_t *val)
8407 {
8408 lsm6dso32_fsm_long_counter_clear_t reg;
8409 int32_t ret;
8410
8411 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8412
8413 if (ret == 0)
8414 {
8415 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8416 (uint8_t *)®, 1);
8417 }
8418
8419 if (ret == 0)
8420 {
8421 switch (reg.fsm_lc_clr)
8422 {
8423 case LSM6DSO32_LC_NORMAL:
8424 *val = LSM6DSO32_LC_NORMAL;
8425 break;
8426
8427 case LSM6DSO32_LC_CLEAR:
8428 *val = LSM6DSO32_LC_CLEAR;
8429 break;
8430
8431 case LSM6DSO32_LC_CLEAR_DONE:
8432 *val = LSM6DSO32_LC_CLEAR_DONE;
8433 break;
8434
8435 default:
8436 *val = LSM6DSO32_LC_NORMAL;
8437 break;
8438 }
8439 }
8440
8441 if (ret == 0)
8442 {
8443 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8444 }
8445
8446 return ret;
8447 }
8448
8449 /**
8450 * @brief FSM output registers[get]
8451 *
8452 * @param ctx read / write interface definitions
8453 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
8454 * @retval interface status (MANDATORY: return 0 -> no Error)
8455 *
8456 */
lsm6dso32_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dso32_fsm_out_t * val)8457 int32_t lsm6dso32_fsm_out_get(const stmdev_ctx_t *ctx,
8458 lsm6dso32_fsm_out_t *val)
8459 {
8460 int32_t ret;
8461
8462 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8463
8464 if (ret == 0)
8465 {
8466 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_OUTS1, (uint8_t *) &val,
8467 16);
8468 }
8469
8470 if (ret == 0)
8471 {
8472 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8473 }
8474
8475 return ret;
8476 }
8477
8478 /**
8479 * @brief Finite State Machine ODR configuration.[set]
8480 *
8481 * @param ctx read / write interface definitions
8482 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8483 * @retval interface status (MANDATORY: return 0 -> no Error)
8484 *
8485 */
lsm6dso32_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32_fsm_odr_t val)8486 int32_t lsm6dso32_fsm_data_rate_set(const stmdev_ctx_t *ctx,
8487 lsm6dso32_fsm_odr_t val)
8488 {
8489 lsm6dso32_emb_func_odr_cfg_b_t reg;
8490 int32_t ret;
8491
8492 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8493
8494 if (ret == 0)
8495 {
8496 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8497 (uint8_t *)®, 1);
8498 }
8499
8500 if (ret == 0)
8501 {
8502 reg.not_used_01 = 3; /* set default values */
8503 reg.not_used_02 = 1; /* set default values */
8504 reg.fsm_odr = (uint8_t)val;
8505 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8506 (uint8_t *)®, 1);
8507 }
8508
8509 if (ret == 0)
8510 {
8511 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8512 }
8513
8514 return ret;
8515 }
8516
8517 /**
8518 * @brief Finite State Machine ODR configuration.[get]
8519 *
8520 * @param ctx read / write interface definitions
8521 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8522 * @retval interface status (MANDATORY: return 0 -> no Error)
8523 *
8524 */
lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32_fsm_odr_t * val)8525 int32_t lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t *ctx,
8526 lsm6dso32_fsm_odr_t *val)
8527 {
8528 lsm6dso32_emb_func_odr_cfg_b_t reg;
8529 int32_t ret;
8530
8531 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8532
8533 if (ret == 0)
8534 {
8535 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8536 (uint8_t *)®, 1);
8537 }
8538
8539 if (ret == 0)
8540 {
8541 switch (reg.fsm_odr)
8542 {
8543 case LSM6DSO32_ODR_FSM_12Hz5:
8544 *val = LSM6DSO32_ODR_FSM_12Hz5;
8545 break;
8546
8547 case LSM6DSO32_ODR_FSM_26Hz:
8548 *val = LSM6DSO32_ODR_FSM_26Hz;
8549 break;
8550
8551 case LSM6DSO32_ODR_FSM_52Hz:
8552 *val = LSM6DSO32_ODR_FSM_52Hz;
8553 break;
8554
8555 case LSM6DSO32_ODR_FSM_104Hz:
8556 *val = LSM6DSO32_ODR_FSM_104Hz;
8557 break;
8558
8559 default:
8560 *val = LSM6DSO32_ODR_FSM_12Hz5;
8561 break;
8562 }
8563
8564 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8565 }
8566
8567 return ret;
8568 }
8569
8570 /**
8571 * @brief FSM initialization request.[set]
8572 *
8573 * @param ctx read / write interface definitions
8574 * @param val change the values of fsm_init in reg FSM_INIT
8575 * @retval interface status (MANDATORY: return 0 -> no Error)
8576 *
8577 */
lsm6dso32_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)8578 int32_t lsm6dso32_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
8579 {
8580 lsm6dso32_emb_func_init_b_t reg;
8581 int32_t ret;
8582
8583 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8584
8585 if (ret == 0)
8586 {
8587 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8588 (uint8_t *)®, 1);
8589 }
8590
8591 if (ret == 0)
8592 {
8593 reg.fsm_init = val;
8594 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8595 (uint8_t *)®, 1);
8596 }
8597
8598 if (ret == 0)
8599 {
8600 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8601 }
8602
8603 return ret;
8604 }
8605
8606 /**
8607 * @brief FSM initialization request.[get]
8608 *
8609 * @param ctx read / write interface definitions
8610 * @param val change the values of fsm_init in reg FSM_INIT
8611 * @retval interface status (MANDATORY: return 0 -> no Error)
8612 *
8613 */
lsm6dso32_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)8614 int32_t lsm6dso32_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
8615 {
8616 lsm6dso32_emb_func_init_b_t reg;
8617 int32_t ret;
8618
8619 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8620
8621 if (ret == 0)
8622 {
8623 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8624 (uint8_t *)®, 1);
8625 }
8626
8627 if (ret == 0)
8628 {
8629 *val = reg.fsm_init;
8630 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8631 }
8632
8633 return ret;
8634 }
8635
8636 /**
8637 * @brief FSM long counter timeout register (r/w). The long counter
8638 * timeout value is an unsigned integer value (16-bit format).
8639 * When the long counter value reached this value,
8640 * the FSM generates an interrupt.[set]
8641 *
8642 * @param ctx read / write interface definitions
8643 * @param buff buffer that contains data to write
8644 * @retval interface status (MANDATORY: return 0 -> no Error)
8645 *
8646 */
lsm6dso32_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)8647 int32_t lsm6dso32_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
8648 uint16_t val)
8649 {
8650 uint8_t buff[2];
8651 int32_t ret;
8652
8653 buff[1] = (uint8_t)(val / 256U);
8654 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8655 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
8656 &buff[0]);
8657
8658 if (ret == 0)
8659 {
8660 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
8661 &buff[1]);
8662 }
8663
8664 return ret;
8665 }
8666
8667 /**
8668 * @brief FSM long counter timeout register (r/w). The long counter
8669 * timeout value is an unsigned integer value (16-bit format).
8670 * When the long counter value reached this value,
8671 * the FSM generates an interrupt.[get]
8672 *
8673 * @param ctx read / write interface definitions
8674 * @param buff buffer that stores data read
8675 * @retval interface status (MANDATORY: return 0 -> no Error)
8676 *
8677 */
lsm6dso32_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)8678 int32_t lsm6dso32_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
8679 uint16_t *val)
8680 {
8681 uint8_t buff[2];
8682 int32_t ret;
8683
8684 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
8685 &buff[0]);
8686
8687 if (ret == 0)
8688 {
8689 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
8690 &buff[1]);
8691 *val = buff[1];
8692 *val = (*val * 256U) + buff[0];
8693 }
8694
8695 return ret;
8696 }
8697
8698 /**
8699 * @brief FSM number of programs register.[set]
8700 *
8701 * @param ctx read / write interface definitions
8702 * @param buff buffer that contains data to write
8703 * @retval interface status (MANDATORY: return 0 -> no Error)
8704 *
8705 */
lsm6dso32_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)8706 int32_t lsm6dso32_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
8707 uint8_t *buff)
8708 {
8709 int32_t ret;
8710
8711 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_PROGRAMS, buff);
8712
8713 return ret;
8714 }
8715
8716 /**
8717 * @brief FSM number of programs register.[get]
8718 *
8719 * @param ctx read / write interface definitions
8720 * @param buff buffer that stores data read
8721 * @retval interface status (MANDATORY: return 0 -> no Error)
8722 *
8723 */
lsm6dso32_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)8724 int32_t lsm6dso32_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
8725 uint8_t *buff)
8726 {
8727 int32_t ret;
8728
8729 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_PROGRAMS, buff);
8730
8731 return ret;
8732 }
8733
8734 /**
8735 * @brief FSM start address register (r/w).
8736 * First available address is 0x033C.[set]
8737 *
8738 * @param ctx read / write interface definitions
8739 * @param buff buffer that contains data to write
8740 * @retval interface status (MANDATORY: return 0 -> no Error)
8741 *
8742 */
lsm6dso32_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)8743 int32_t lsm6dso32_fsm_start_address_set(const stmdev_ctx_t *ctx,
8744 uint16_t val)
8745 {
8746 uint8_t buff[2];
8747 int32_t ret;
8748
8749 buff[1] = (uint8_t)(val / 256U);
8750 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8751 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
8752 &buff[0]);
8753
8754 if (ret == 0)
8755 {
8756 ;
8757 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
8758 &buff[1]);
8759 }
8760
8761 return ret;
8762 }
8763
8764 /**
8765 * @brief FSM start address register (r/w).
8766 * First available address is 0x033C.[get]
8767 *
8768 * @param ctx read / write interface definitions
8769 * @param buff buffer that stores data read
8770 * @retval interface status (MANDATORY: return 0 -> no Error)
8771 *
8772 */
lsm6dso32_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)8773 int32_t lsm6dso32_fsm_start_address_get(const stmdev_ctx_t *ctx,
8774 uint16_t *val)
8775 {
8776 uint8_t buff[2];
8777 int32_t ret;
8778
8779 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
8780 &buff[0]);
8781
8782 if (ret == 0)
8783 {
8784 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
8785 &buff[1]);
8786 *val = buff[1];
8787 *val = (*val * 256U) + buff[0];
8788 }
8789
8790 return ret;
8791 }
8792
8793 /**
8794 * @}
8795 *
8796 */
8797
8798 /**
8799 * @defgroup LSM6DSO32_Sensor_hub
8800 * @brief This section groups all the functions that manage the
8801 * sensor hub.
8802 * @{
8803 *
8804 */
8805
8806 /**
8807 * @brief Sensor hub output registers.[get]
8808 *
8809 * @param ctx read / write interface definitions
8810 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
8811 * @retval interface status (MANDATORY: return 0 -> no Error)
8812 *
8813 */
lsm6dso32_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dso32_emb_sh_read_t * val)8814 int32_t lsm6dso32_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
8815 lsm6dso32_emb_sh_read_t *val)
8816 {
8817 int32_t ret;
8818
8819 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8820
8821 if (ret == 0)
8822 {
8823 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SENSOR_HUB_1,
8824 (uint8_t *) val, 18U);
8825 }
8826
8827 if (ret == 0)
8828 {
8829 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8830 }
8831
8832 return ret;
8833 }
8834
8835 /**
8836 * @brief Number of external sensors to be read by the sensor hub.[set]
8837 *
8838 * @param ctx read / write interface definitions
8839 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
8840 * @retval interface status (MANDATORY: return 0 -> no Error)
8841 *
8842 */
lsm6dso32_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dso32_aux_sens_on_t val)8843 int32_t lsm6dso32_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8844 lsm6dso32_aux_sens_on_t val)
8845 {
8846 lsm6dso32_master_config_t reg;
8847 int32_t ret;
8848
8849 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8850
8851 if (ret == 0)
8852 {
8853 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8854 (uint8_t *)®, 1);
8855 }
8856
8857 if (ret == 0)
8858 {
8859 reg.aux_sens_on = (uint8_t)val;
8860 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8861 (uint8_t *)®, 1);
8862 }
8863
8864 if (ret == 0)
8865 {
8866 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8867 }
8868
8869 return ret;
8870 }
8871
8872 /**
8873 * @brief Number of external sensors to be read by the sensor hub.[get]
8874 *
8875 * @param ctx read / write interface definitions
8876 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
8877 * @retval interface status (MANDATORY: return 0 -> no Error)
8878 *
8879 */
lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dso32_aux_sens_on_t * val)8880 int32_t lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8881 lsm6dso32_aux_sens_on_t *val)
8882 {
8883 lsm6dso32_master_config_t reg;
8884 int32_t ret;
8885
8886 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8887
8888 if (ret == 0)
8889 {
8890 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8891 (uint8_t *)®, 1);
8892 }
8893
8894 if (ret == 0)
8895 {
8896 switch (reg.aux_sens_on)
8897 {
8898 case LSM6DSO32_SLV_0:
8899 *val = LSM6DSO32_SLV_0;
8900 break;
8901
8902 case LSM6DSO32_SLV_0_1:
8903 *val = LSM6DSO32_SLV_0_1;
8904 break;
8905
8906 case LSM6DSO32_SLV_0_1_2:
8907 *val = LSM6DSO32_SLV_0_1_2;
8908 break;
8909
8910 case LSM6DSO32_SLV_0_1_2_3:
8911 *val = LSM6DSO32_SLV_0_1_2_3;
8912 break;
8913
8914 default:
8915 *val = LSM6DSO32_SLV_0;
8916 break;
8917 }
8918
8919 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8920 }
8921
8922 return ret;
8923 }
8924
8925 /**
8926 * @brief Sensor hub I2C master enable.[set]
8927 *
8928 * @param ctx read / write interface definitions
8929 * @param val change the values of master_on in reg MASTER_CONFIG
8930 * @retval interface status (MANDATORY: return 0 -> no Error)
8931 *
8932 */
lsm6dso32_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8933 int32_t lsm6dso32_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8934 {
8935 lsm6dso32_master_config_t reg;
8936 int32_t ret;
8937
8938 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8939
8940 if (ret == 0)
8941 {
8942 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8943 (uint8_t *)®, 1);
8944 }
8945
8946 if (ret == 0)
8947 {
8948 reg.master_on = val;
8949 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8950 (uint8_t *)®, 1);
8951 }
8952
8953 if (ret == 0)
8954 {
8955 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8956 }
8957
8958 return ret;
8959 }
8960
8961 /**
8962 * @brief Sensor hub I2C master enable.[get]
8963 *
8964 * @param ctx read / write interface definitions
8965 * @param val change the values of master_on in reg MASTER_CONFIG
8966 * @retval interface status (MANDATORY: return 0 -> no Error)
8967 *
8968 */
lsm6dso32_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)8969 int32_t lsm6dso32_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
8970 {
8971 lsm6dso32_master_config_t reg;
8972 int32_t ret;
8973
8974 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8975
8976 if (ret == 0)
8977 {
8978 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8979 (uint8_t *)®, 1);
8980 }
8981
8982 if (ret == 0)
8983 {
8984 *val = reg.master_on;
8985 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8986 }
8987
8988 return ret;
8989 }
8990
8991 /**
8992 * @brief Master I2C pull-up enable.[set]
8993 *
8994 * @param ctx read / write interface definitions
8995 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
8996 * @retval interface status (MANDATORY: return 0 -> no Error)
8997 *
8998 */
lsm6dso32_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_shub_pu_en_t val)8999 int32_t lsm6dso32_sh_pin_mode_set(const stmdev_ctx_t *ctx,
9000 lsm6dso32_shub_pu_en_t val)
9001 {
9002 lsm6dso32_master_config_t reg;
9003 int32_t ret;
9004
9005 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9006
9007 if (ret == 0)
9008 {
9009 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9010 (uint8_t *)®, 1);
9011 }
9012
9013 if (ret == 0)
9014 {
9015 reg.shub_pu_en = (uint8_t)val;
9016 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9017 (uint8_t *)®, 1);
9018 }
9019
9020 if (ret == 0)
9021 {
9022 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9023 }
9024
9025 return ret;
9026 }
9027
9028 /**
9029 * @brief Master I2C pull-up enable.[get]
9030 *
9031 * @param ctx read / write interface definitions
9032 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
9033 * @retval interface status (MANDATORY: return 0 -> no Error)
9034 *
9035 */
lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_shub_pu_en_t * val)9036 int32_t lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t *ctx,
9037 lsm6dso32_shub_pu_en_t *val)
9038 {
9039 lsm6dso32_master_config_t reg;
9040 int32_t ret;
9041
9042 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9043
9044 if (ret == 0)
9045 {
9046 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9047 (uint8_t *)®, 1);
9048 }
9049
9050 if (ret == 0)
9051 {
9052 switch (reg.shub_pu_en)
9053 {
9054 case LSM6DSO32_EXT_PULL_UP:
9055 *val = LSM6DSO32_EXT_PULL_UP;
9056 break;
9057
9058 case LSM6DSO32_INTERNAL_PULL_UP:
9059 *val = LSM6DSO32_INTERNAL_PULL_UP;
9060 break;
9061
9062 default:
9063 *val = LSM6DSO32_EXT_PULL_UP;
9064 break;
9065 }
9066
9067 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9068 }
9069
9070 return ret;
9071 }
9072
9073 /**
9074 * @brief I2C interface pass-through.[set]
9075 *
9076 * @param ctx read / write interface definitions
9077 * @param val change the values of pass_through_mode in
9078 * reg MASTER_CONFIG
9079 * @retval interface status (MANDATORY: return 0 -> no Error)
9080 *
9081 */
lsm6dso32_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)9082 int32_t lsm6dso32_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
9083 {
9084 lsm6dso32_master_config_t reg;
9085 int32_t ret;
9086
9087 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9088
9089 if (ret == 0)
9090 {
9091 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9092 (uint8_t *)®, 1);
9093 }
9094
9095 if (ret == 0)
9096 {
9097 reg.pass_through_mode = val;
9098 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9099 (uint8_t *)®, 1);
9100 }
9101
9102 if (ret == 0)
9103 {
9104 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9105 }
9106
9107 return ret;
9108 }
9109
9110 /**
9111 * @brief I2C interface pass-through.[get]
9112 *
9113 * @param ctx read / write interface definitions
9114 * @param val change the values of pass_through_mode in
9115 * reg MASTER_CONFIG
9116 * @retval interface status (MANDATORY: return 0 -> no Error)
9117 *
9118 */
lsm6dso32_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)9119 int32_t lsm6dso32_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
9120 {
9121 lsm6dso32_master_config_t reg;
9122 int32_t ret;
9123
9124 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9125
9126 if (ret == 0)
9127 {
9128 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9129 (uint8_t *)®, 1);
9130 }
9131
9132 if (ret == 0)
9133 {
9134 *val = reg.pass_through_mode;
9135 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9136 }
9137
9138 return ret;
9139 }
9140
9141 /**
9142 * @brief Sensor hub trigger signal selection.[set]
9143 *
9144 * @param ctx read / write interface definitions
9145 * @param val change the values of start_config in reg MASTER_CONFIG
9146 * @retval interface status (MANDATORY: return 0 -> no Error)
9147 *
9148 */
lsm6dso32_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_start_config_t val)9149 int32_t lsm6dso32_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
9150 lsm6dso32_start_config_t val)
9151 {
9152 lsm6dso32_master_config_t reg;
9153 int32_t ret;
9154
9155 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9156
9157 if (ret == 0)
9158 {
9159 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9160 (uint8_t *)®, 1);
9161 }
9162
9163 if (ret == 0)
9164 {
9165 reg.start_config = (uint8_t)val;
9166 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9167 (uint8_t *)®, 1);
9168 }
9169
9170 if (ret == 0)
9171 {
9172 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9173 }
9174
9175 return ret;
9176 }
9177
9178 /**
9179 * @brief Sensor hub trigger signal selection.[get]
9180 *
9181 * @param ctx read / write interface definitions
9182 * @param val Get the values of start_config in reg MASTER_CONFIG
9183 * @retval interface status (MANDATORY: return 0 -> no Error)
9184 *
9185 */
lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_start_config_t * val)9186 int32_t lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
9187 lsm6dso32_start_config_t *val)
9188 {
9189 lsm6dso32_master_config_t reg;
9190 int32_t ret;
9191
9192 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9193
9194 if (ret == 0)
9195 {
9196 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9197 (uint8_t *)®, 1);
9198 }
9199
9200 if (ret == 0)
9201 {
9202 switch (reg.start_config)
9203 {
9204 case LSM6DSO32_EXT_ON_INT2_PIN:
9205 *val = LSM6DSO32_EXT_ON_INT2_PIN;
9206 break;
9207
9208 case LSM6DSO32_XL_GY_DRDY:
9209 *val = LSM6DSO32_XL_GY_DRDY;
9210 break;
9211
9212 default:
9213 *val = LSM6DSO32_EXT_ON_INT2_PIN;
9214 break;
9215 }
9216
9217 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9218 }
9219
9220 return ret;
9221 }
9222
9223 /**
9224 * @brief Slave 0 write operation is performed only at the first
9225 * sensor hub cycle.[set]
9226 *
9227 * @param ctx read / write interface definitions
9228 * @param val change the values of write_once in reg MASTER_CONFIG
9229 * @retval interface status (MANDATORY: return 0 -> no Error)
9230 *
9231 */
lsm6dso32_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dso32_write_once_t val)9232 int32_t lsm6dso32_sh_write_mode_set(const stmdev_ctx_t *ctx,
9233 lsm6dso32_write_once_t val)
9234 {
9235 lsm6dso32_master_config_t reg;
9236 int32_t ret;
9237
9238 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9239
9240 if (ret == 0)
9241 {
9242 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9243 (uint8_t *)®, 1);
9244 }
9245
9246 if (ret == 0)
9247 {
9248 reg.write_once = (uint8_t)val;
9249 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9250 (uint8_t *)®, 1);
9251 }
9252
9253 if (ret == 0)
9254 {
9255 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9256 }
9257
9258 return ret;
9259 }
9260
9261 /**
9262 * @brief Slave 0 write operation is performed only at the first sensor
9263 * hub cycle.[get]
9264 *
9265 * @param ctx read / write interface definitions
9266 * @param val Get the values of write_once in reg MASTER_CONFIG
9267 * @retval interface status (MANDATORY: return 0 -> no Error)
9268 *
9269 */
lsm6dso32_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dso32_write_once_t * val)9270 int32_t lsm6dso32_sh_write_mode_get(const stmdev_ctx_t *ctx,
9271 lsm6dso32_write_once_t *val)
9272 {
9273 lsm6dso32_master_config_t reg;
9274 int32_t ret;
9275
9276 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9277
9278 if (ret == 0)
9279 {
9280 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9281 (uint8_t *)®, 1);
9282 }
9283
9284 if (ret == 0)
9285 {
9286 switch (reg.write_once)
9287 {
9288 case LSM6DSO32_EACH_SH_CYCLE:
9289 *val = LSM6DSO32_EACH_SH_CYCLE;
9290 break;
9291
9292 case LSM6DSO32_ONLY_FIRST_CYCLE:
9293 *val = LSM6DSO32_ONLY_FIRST_CYCLE;
9294 break;
9295
9296 default:
9297 *val = LSM6DSO32_EACH_SH_CYCLE;
9298 break;
9299 }
9300
9301 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9302 }
9303
9304 return ret;
9305 }
9306
9307 /**
9308 * @brief Reset Master logic and output registers.[set]
9309 *
9310 * @param ctx read / write interface definitions
9311 * @retval interface status (MANDATORY: return 0 -> no Error)
9312 *
9313 */
lsm6dso32_sh_reset_set(const stmdev_ctx_t * ctx)9314 int32_t lsm6dso32_sh_reset_set(const stmdev_ctx_t *ctx)
9315 {
9316 lsm6dso32_master_config_t reg;
9317 int32_t ret;
9318
9319 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9320
9321 if (ret == 0)
9322 {
9323 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9324 (uint8_t *)®, 1);
9325 }
9326
9327 if (ret == 0)
9328 {
9329 reg.rst_master_regs = PROPERTY_ENABLE;
9330 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9331 (uint8_t *)®, 1);
9332 }
9333
9334 if (ret == 0)
9335 {
9336 reg.rst_master_regs = PROPERTY_DISABLE;
9337 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9338 (uint8_t *)®, 1);
9339 }
9340
9341 if (ret == 0)
9342 {
9343 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9344 }
9345
9346 return ret;
9347 }
9348
9349 /**
9350 * @brief Reset Master logic and output registers.[get]
9351 *
9352 * @param ctx read / write interface definitions
9353 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
9354 * @retval interface status (MANDATORY: return 0 -> no Error)
9355 *
9356 */
lsm6dso32_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)9357 int32_t lsm6dso32_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
9358 {
9359 lsm6dso32_master_config_t reg;
9360 int32_t ret;
9361
9362 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9363
9364 if (ret == 0)
9365 {
9366 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9367 (uint8_t *)®, 1);
9368 }
9369
9370 if (ret == 0)
9371 {
9372 *val = reg.rst_master_regs;
9373 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9374 }
9375
9376 return ret;
9377 }
9378
9379 /**
9380 * @brief Rate at which the master communicates.[set]
9381 *
9382 * @param ctx read / write interface definitions
9383 * @param val change the values of shub_odr in reg slv1_CONFIG
9384 * @retval interface status (MANDATORY: return 0 -> no Error)
9385 *
9386 */
lsm6dso32_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso32_shub_odr_t val)9387 int32_t lsm6dso32_sh_data_rate_set(const stmdev_ctx_t *ctx,
9388 lsm6dso32_shub_odr_t val)
9389 {
9390 lsm6dso32_slv0_config_t reg;
9391 int32_t ret;
9392
9393 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9394
9395 if (ret == 0)
9396 {
9397 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9398 }
9399
9400 if (ret == 0)
9401 {
9402 reg.shub_odr = (uint8_t)val;
9403 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9404 }
9405
9406 if (ret == 0)
9407 {
9408 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9409 }
9410
9411 return ret;
9412 }
9413
9414 /**
9415 * @brief Rate at which the master communicates.[get]
9416 *
9417 * @param ctx read / write interface definitions
9418 * @param val Get the values of shub_odr in reg slv1_CONFIG
9419 * @retval interface status (MANDATORY: return 0 -> no Error)
9420 *
9421 */
lsm6dso32_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso32_shub_odr_t * val)9422 int32_t lsm6dso32_sh_data_rate_get(const stmdev_ctx_t *ctx,
9423 lsm6dso32_shub_odr_t *val)
9424 {
9425 lsm6dso32_slv0_config_t reg;
9426 int32_t ret;
9427
9428 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9429
9430 if (ret == 0)
9431 {
9432 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9433 }
9434
9435 if (ret == 0)
9436 {
9437 switch (reg.shub_odr)
9438 {
9439 case LSM6DSO32_SH_ODR_104Hz:
9440 *val = LSM6DSO32_SH_ODR_104Hz;
9441 break;
9442
9443 case LSM6DSO32_SH_ODR_52Hz:
9444 *val = LSM6DSO32_SH_ODR_52Hz;
9445 break;
9446
9447 case LSM6DSO32_SH_ODR_26Hz:
9448 *val = LSM6DSO32_SH_ODR_26Hz;
9449 break;
9450
9451 case LSM6DSO32_SH_ODR_13Hz:
9452 *val = LSM6DSO32_SH_ODR_13Hz;
9453 break;
9454
9455 default:
9456 *val = LSM6DSO32_SH_ODR_104Hz;
9457 break;
9458 }
9459
9460 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9461 }
9462
9463 return ret;
9464 }
9465
9466 /**
9467 * @brief Configure slave 0 for perform a write.[set]
9468 *
9469 * @param ctx read / write interface definitions
9470 * @param val a structure that contain
9471 * - uint8_t slv1_add; 8 bit i2c device address
9472 * - uint8_t slv1_subadd; 8 bit register device address
9473 * - uint8_t slv1_data; 8 bit data to write
9474 * @retval interface status (MANDATORY: return 0 -> no Error)
9475 *
9476 */
lsm6dso32_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_write_t * val)9477 int32_t lsm6dso32_sh_cfg_write(const stmdev_ctx_t *ctx,
9478 lsm6dso32_sh_cfg_write_t *val)
9479 {
9480 lsm6dso32_slv0_add_t reg;
9481 int32_t ret;
9482
9483 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9484
9485 if (ret == 0)
9486 {
9487 reg.slave0 = val->slv0_add;
9488 reg.rw_0 = 0;
9489 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD, (uint8_t *)®, 1);
9490 }
9491
9492 if (ret == 0)
9493 {
9494 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
9495 &(val->slv0_subadd), 1);
9496 }
9497
9498 if (ret == 0)
9499 {
9500 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_DATAWRITE_SLV0,
9501 &(val->slv0_data), 1);
9502 }
9503
9504 if (ret == 0)
9505 {
9506 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9507 }
9508
9509 return ret;
9510 }
9511
9512 /**
9513 * @brief Configure slave 0 for perform a read.[set]
9514 *
9515 * @param ctx read / write interface definitions
9516 * @param val Structure that contain
9517 * - uint8_t slv1_add; 8 bit i2c device address
9518 * - uint8_t slv1_subadd; 8 bit register device address
9519 * - uint8_t slv1_len; num of bit to read
9520 * @retval interface status (MANDATORY: return 0 -> no Error)
9521 *
9522 */
lsm6dso32_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9523 int32_t lsm6dso32_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
9524 lsm6dso32_sh_cfg_read_t *val)
9525 {
9526 lsm6dso32_slv0_add_t slv0_add;
9527 lsm6dso32_slv0_config_t slv0_config;
9528 int32_t ret;
9529
9530 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9531
9532 if (ret == 0)
9533 {
9534 slv0_add.slave0 = val->slv_add;
9535 slv0_add.rw_0 = 1;
9536 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD,
9537 (uint8_t *)&slv0_add, 1);
9538 }
9539
9540 if (ret == 0)
9541 {
9542 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
9543 &(val->slv_subadd), 1);
9544 }
9545
9546 if (ret == 0)
9547 {
9548 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG,
9549 (uint8_t *)&slv0_config, 1);
9550 }
9551
9552 if (ret == 0)
9553 {
9554 slv0_config.slave0_numop = val->slv_len;
9555 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG,
9556 (uint8_t *)&slv0_config, 1);
9557 }
9558
9559 if (ret == 0)
9560 {
9561 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9562 }
9563
9564 return ret;
9565 }
9566
9567 /**
9568 * @brief Configure slave 0 for perform a write/read.[set]
9569 *
9570 * @param ctx read / write interface definitions
9571 * @param val Structure that contain
9572 * - uint8_t slv1_add; 8 bit i2c device address
9573 * - uint8_t slv1_subadd; 8 bit register device address
9574 * - uint8_t slv1_len; num of bit to read
9575 * @retval interface status (MANDATORY: return 0 -> no Error)
9576 *
9577 */
lsm6dso32_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9578 int32_t lsm6dso32_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
9579 lsm6dso32_sh_cfg_read_t *val)
9580 {
9581 lsm6dso32_slv1_add_t slv1_add;
9582 lsm6dso32_slv1_config_t slv1_config;
9583 int32_t ret;
9584
9585 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9586
9587 if (ret == 0)
9588 {
9589 slv1_add.slave1_add = val->slv_add;
9590 slv1_add.r_1 = 1;
9591 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_ADD,
9592 (uint8_t *)&slv1_add, 1);
9593 }
9594
9595 if (ret == 0)
9596 {
9597 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_SUBADD,
9598 &(val->slv_subadd), 1);
9599 }
9600
9601 if (ret == 0)
9602 {
9603 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG,
9604 (uint8_t *)&slv1_config, 1);
9605 }
9606
9607 if (ret == 0)
9608 {
9609 slv1_config.slave1_numop = val->slv_len;
9610 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG,
9611 (uint8_t *)&slv1_config, 1);
9612 }
9613
9614 if (ret == 0)
9615 {
9616 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9617 }
9618
9619 return ret;
9620 }
9621
9622 /**
9623 * @brief Configure slave 0 for perform a write/read.[set]
9624 *
9625 * @param ctx read / write interface definitions
9626 * @param val Structure that contain
9627 * - uint8_t slv2_add; 8 bit i2c device address
9628 * - uint8_t slv2_subadd; 8 bit register device address
9629 * - uint8_t slv2_len; num of bit to read
9630 * @retval interface status (MANDATORY: return 0 -> no Error)
9631 *
9632 */
lsm6dso32_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9633 int32_t lsm6dso32_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
9634 lsm6dso32_sh_cfg_read_t *val)
9635 {
9636 lsm6dso32_slv2_add_t slv2_add;
9637 lsm6dso32_slv2_config_t slv2_config;
9638 int32_t ret;
9639
9640 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9641
9642 if (ret == 0)
9643 {
9644 slv2_add.slave2_add = val->slv_add;
9645 slv2_add.r_2 = 1;
9646 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_ADD,
9647 (uint8_t *)&slv2_add, 1);
9648 }
9649
9650 if (ret == 0)
9651 {
9652 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_SUBADD,
9653 &(val->slv_subadd), 1);
9654 }
9655
9656 if (ret == 0)
9657 {
9658 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG,
9659 (uint8_t *)&slv2_config, 1);
9660 }
9661
9662 if (ret == 0)
9663 {
9664 slv2_config.slave2_numop = val->slv_len;
9665 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG,
9666 (uint8_t *)&slv2_config, 1);
9667 }
9668
9669 if (ret == 0)
9670 {
9671 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9672 }
9673
9674 return ret;
9675 }
9676
9677 /**
9678 * @brief Configure slave 0 for perform a write/read.[set]
9679 *
9680 * @param ctx read / write interface definitions
9681 * @param val Structure that contain
9682 * - uint8_t slv3_add; 8 bit i2c device address
9683 * - uint8_t slv3_subadd; 8 bit register device address
9684 * - uint8_t slv3_len; num of bit to read
9685 * @retval interface status (MANDATORY: return 0 -> no Error)
9686 *
9687 */
lsm6dso32_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9688 int32_t lsm6dso32_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
9689 lsm6dso32_sh_cfg_read_t *val)
9690 {
9691 lsm6dso32_slv3_add_t slv3_add;
9692 lsm6dso32_slv3_config_t slv3_config;
9693 int32_t ret;
9694
9695 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9696
9697 if (ret == 0)
9698 {
9699 slv3_add.slave3_add = val->slv_add;
9700 slv3_add.r_3 = 1;
9701 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_ADD,
9702 (uint8_t *)&slv3_add, 1);
9703 }
9704
9705 if (ret == 0)
9706 {
9707 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_SUBADD,
9708 &(val->slv_subadd), 1);
9709 }
9710
9711 if (ret == 0)
9712 {
9713 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG,
9714 (uint8_t *)&slv3_config, 1);
9715 }
9716
9717 if (ret == 0)
9718 {
9719 slv3_config.slave3_numop = val->slv_len;
9720 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG,
9721 (uint8_t *)&slv3_config, 1);
9722 }
9723
9724 if (ret == 0)
9725 {
9726 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9727 }
9728
9729 return ret;
9730 }
9731
9732 /**
9733 * @brief Sensor hub source register.[get]
9734 *
9735 * @param ctx read / write interface definitions
9736 * @param val union of registers from STATUS_MASTER to
9737 * @retval interface status (MANDATORY: return 0 -> no Error)
9738 *
9739 */
lsm6dso32_sh_status_get(const stmdev_ctx_t * ctx,lsm6dso32_status_master_t * val)9740 int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx,
9741 lsm6dso32_status_master_t *val)
9742 {
9743 int32_t ret;
9744
9745 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9746
9747 if (ret == 0)
9748 {
9749 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_MASTER,
9750 (uint8_t *) val, 1);
9751 }
9752
9753 if (ret == 0)
9754 {
9755 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9756 }
9757
9758 return ret;
9759 }
9760
9761 /**
9762 * @}
9763 *
9764 */
9765
9766 /**
9767 * @}
9768 *
9769 */
9770
9771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9772
