1 /**
2 ******************************************************************************
3 * @file lsm6dso16is_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO16IS driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso16is_reg.h"
21
22 /**
23 * @defgroup LSM6DSO16IS
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso16is enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dso16is_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso16is_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dso16is_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dso16is_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSO16IS_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm6dso16is_from_fs2g_to_mg(int16_t lsb)103 float_t lsm6dso16is_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
lsm6dso16is_from_fs4g_to_mg(int16_t lsb)108 float_t lsm6dso16is_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
lsm6dso16is_from_fs8g_to_mg(int16_t lsb)113 float_t lsm6dso16is_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
lsm6dso16is_from_fs16g_to_mg(int16_t lsb)118 float_t lsm6dso16is_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb)123 float_t lsm6dso16is_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb)128 float_t lsm6dso16is_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.75f);
131 }
132
lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb)133 float_t lsm6dso16is_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb)138 float_t lsm6dso16is_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb)143 float_t lsm6dso16is_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
lsm6dso16is_from_lsb_to_celsius(int16_t lsb)148 float_t lsm6dso16is_from_lsb_to_celsius(int16_t lsb)
149 {
150 return (((float_t)lsb / 256.0f) + 25.0f);
151 }
152
153 /**
154 * @defgroup Common
155 * @brief Common
156 * @{/
157 *
158 */
159
160 /**
161 * @brief Difference in percentage of the effective ODR (and timestamp rate)
162 * with respect to the typical.[set]
163 * Step: 0.15%. 8-bit format, 2's complement.
164 *
165 * @param ctx Read / write interface definitions.(ptr)
166 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
167 * @retval Interface status (MANDATORY: return 0 -> no Error).
168 *
169 */
lsm6dso16is_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)170 int32_t lsm6dso16is_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
171 {
172 lsm6dso16is_internal_freq_fine_t internal_freq_fine;
173 int32_t ret;
174
175 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
176 (uint8_t *)&internal_freq_fine, 1);
177
178 if (ret == 0)
179 {
180 internal_freq_fine.freq_fine = (uint8_t)val;
181 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
182 (uint8_t *)&internal_freq_fine, 1);
183 }
184
185 return ret;
186 }
187
188 /**
189 * @brief Difference in percentage of the effective ODR (and timestamp rate)
190 * with respect to the typical.[get]
191 * Step: 0.15%. 8-bit format, 2's complement.
192 *
193 * @param ctx Read / write interface definitions.(ptr)
194 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
195 * @retval Interface status (MANDATORY: return 0 -> no Error).
196 *
197 */
lsm6dso16is_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)198 int32_t lsm6dso16is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
199 {
200 lsm6dso16is_internal_freq_fine_t internal_freq_fine;
201 int32_t ret;
202
203 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INTERNAL_FREQ_FINE,
204 (uint8_t *)&internal_freq_fine, 1);
205 *val = internal_freq_fine.freq_fine;
206
207 return ret;
208 }
209
210 /**
211 * @brief Change memory bank.[set]
212 *
213 * @param ctx read / write interface definitions
214 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
215 * @retval interface status (MANDATORY: return 0 -> no Error)
216 *
217 */
lsm6dso16is_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dso16is_mem_bank_t val)218 int32_t lsm6dso16is_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val)
219 {
220 lsm6dso16is_func_cfg_access_t func_cfg_access = {0x0};
221 int32_t ret;
222
223 /* no need to read it first as the only other field is a ispu reset bit */
224 func_cfg_access.shub_reg_access = (val == LSM6DSO16IS_SENSOR_HUB_MEM_BANK) ? 0x1U : 0x0U;
225 func_cfg_access.ispu_reg_access = (val == LSM6DSO16IS_ISPU_MEM_BANK) ? 0x1U : 0x0U;
226 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
227
228 return ret;
229 }
230
231 /**
232 * @brief Change memory bank.[get]
233 *
234 * @param ctx read / write interface definitions
235 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, ISPU_MEM_BANK,
236 * @retval interface status (MANDATORY: return 0 -> no Error)
237 *
238 */
lsm6dso16is_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dso16is_mem_bank_t * val)239 int32_t lsm6dso16is_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val)
240 {
241 lsm6dso16is_func_cfg_access_t func_cfg_access;
242 int32_t ret;
243
244 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
245
246 if (func_cfg_access.shub_reg_access == 1U)
247 {
248 *val = LSM6DSO16IS_SENSOR_HUB_MEM_BANK;
249 }
250 else if (func_cfg_access.ispu_reg_access == 1U)
251 {
252 *val = LSM6DSO16IS_ISPU_MEM_BANK;
253 }
254 else
255 {
256 *val = LSM6DSO16IS_MAIN_MEM_BANK;
257 }
258
259 return ret;
260 }
261
262 /**
263 * @brief Enables pulsed data-ready mode (~75 us).[set]
264 *
265 * @param ctx read / write interface definitions
266 * @param val DRDY_LATCHED, DRDY_PULSED,
267 * @retval interface status (MANDATORY: return 0 -> no Error)
268 *
269 */
lsm6dso16is_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_data_ready_mode_t val)270 int32_t lsm6dso16is_data_ready_mode_set(const stmdev_ctx_t *ctx,
271 lsm6dso16is_data_ready_mode_t val)
272 {
273 lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg;
274 int32_t ret;
275
276 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
277
278 if (ret == 0)
279 {
280 drdy_pulsed_reg.drdy_pulsed = ((uint8_t)val & 0x1U);
281 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
282 }
283
284 return ret;
285 }
286
287 /**
288 * @brief Enables pulsed data-ready mode (~75 us).[get]
289 *
290 * @param ctx read / write interface definitions
291 * @param val DRDY_LATCHED, DRDY_PULSED,
292 * @retval interface status (MANDATORY: return 0 -> no Error)
293 *
294 */
lsm6dso16is_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_data_ready_mode_t * val)295 int32_t lsm6dso16is_data_ready_mode_get(const stmdev_ctx_t *ctx,
296 lsm6dso16is_data_ready_mode_t *val)
297 {
298 lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg;
299 int32_t ret;
300
301 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_DRDY_PULSED_REG, (uint8_t *)&drdy_pulsed_reg, 1);
302
303 switch ((drdy_pulsed_reg.drdy_pulsed))
304 {
305 case LSM6DSO16IS_DRDY_LATCHED:
306 *val = LSM6DSO16IS_DRDY_LATCHED;
307 break;
308
309 case LSM6DSO16IS_DRDY_PULSED:
310 *val = LSM6DSO16IS_DRDY_PULSED;
311 break;
312
313 default:
314 *val = LSM6DSO16IS_DRDY_LATCHED;
315 break;
316 }
317 return ret;
318 }
319
320 /**
321 * @brief Device ID.[get]
322 *
323 * @param ctx read / write interface definitions
324 * @param val Device ID.
325 * @retval interface status (MANDATORY: return 0 -> no Error)
326 *
327 */
lsm6dso16is_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)328 int32_t lsm6dso16is_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
329 {
330 int32_t ret;
331
332 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_WHO_AM_I, (uint8_t *)val, 1);
333
334 return ret;
335 }
336
337 /**
338 * @brief Software reset. Restore the default values in user registers.[set]
339 *
340 * @param ctx Read / write interface definitions.(ptr)
341 * @retval Interface status (MANDATORY: return 0 -> no Error).
342 *
343 */
lsm6dso16is_software_reset(const stmdev_ctx_t * ctx)344 int32_t lsm6dso16is_software_reset(const stmdev_ctx_t *ctx)
345 {
346 lsm6dso16is_ctrl3_c_t ctrl3_c;
347 int32_t ret;
348
349 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
350
351 if (ret == 0)
352 {
353 ret += lsm6dso16is_xl_data_rate_set(ctx, LSM6DSO16IS_XL_ODR_OFF);
354 ret += lsm6dso16is_gy_data_rate_set(ctx, LSM6DSO16IS_GY_ODR_OFF);
355
356 ctrl3_c.sw_reset = PROPERTY_ENABLE;
357 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
358
359 do
360 {
361 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
362 } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE);
363 }
364
365 return ret;
366 }
367
368 /**
369 * @brief Reboot memory content. Reload the calibration parameters.[set]
370 *
371 * @param ctx Read / write interface definitions.(ptr)
372 * @param val Change the values of boot in reg CTRL_REG1
373 * @retval Interface status (MANDATORY: return 0 -> no Error).
374 *
375 */
lsm6dso16is_boot_set(const stmdev_ctx_t * ctx,uint8_t val)376 int32_t lsm6dso16is_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
377 {
378 lsm6dso16is_ctrl3_c_t ctrl3_c;
379 int32_t ret;
380
381 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
382
383 if (ret == 0)
384 {
385 ctrl3_c.boot = val;
386 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
387 }
388
389 return ret;
390 }
391
392 /**
393 * @brief Reboot memory content. Reload the calibration parameters.[get]
394 *
395 * @param ctx Read / write interface definitions.(ptr)
396 * @param val Get the values of boot in reg CTRL_REG1.(ptr)
397 * @retval Interface status (MANDATORY: return 0 -> no Error).
398 *
399 */
lsm6dso16is_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)400 int32_t lsm6dso16is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
401 {
402 lsm6dso16is_ctrl3_c_t ctrl3_c;
403 int32_t ret;
404
405 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
406 *val = ctrl3_c.boot;
407
408 return ret;
409 }
410
411 /**
412 * @brief Enable disable high-performance mode[set]
413 *
414 * @param ctx read / write interface definitions
415 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
416 * @retval interface status (MANDATORY: return 0 -> no Error)
417 *
418 */
lsm6dso16is_xl_hm_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t val)419 int32_t lsm6dso16is_xl_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val)
420 {
421 lsm6dso16is_ctrl6_c_t ctrl6_c;
422 int32_t ret;
423
424 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
425
426 if (ret == 0)
427 {
428 ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x1U);
429 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
430 }
431
432 return ret;
433 }
434
435 /**
436 * @brief Enable disable high-performance mode[get]
437 *
438 * @param ctx read / write interface definitions
439 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
440 * @retval interface status (MANDATORY: return 0 -> no Error)
441 *
442 */
lsm6dso16is_xl_hm_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t * val)443 int32_t lsm6dso16is_xl_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val)
444 {
445 lsm6dso16is_ctrl6_c_t ctrl6_c;
446 int32_t ret;
447
448 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
449
450 switch ((ctrl6_c.xl_hm_mode))
451 {
452 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED:
453 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
454 break;
455
456 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED:
457 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED;
458 break;
459
460 default:
461 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
462 break;
463 }
464 return ret;
465 }
466
467 /**
468 * @brief Accelerometer full-scale selection.[set]
469 *
470 * @param ctx read / write interface definitions
471 * @param val 2g, 4g, 8g, 16g,
472 * @retval interface status (MANDATORY: return 0 -> no Error)
473 *
474 */
lsm6dso16is_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso16is_xl_full_scale_t val)475 int32_t lsm6dso16is_xl_full_scale_set(const stmdev_ctx_t *ctx,
476 lsm6dso16is_xl_full_scale_t val)
477 {
478 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
479 int32_t ret;
480
481 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
482
483 if (ret == 0)
484 {
485 ctrl1_xl.fs_xl = ((uint8_t)val & 0x3U);
486 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
487 }
488
489 return ret;
490 }
491
492 /**
493 * @brief Accelerometer full-scale selection.[get]
494 *
495 * @param ctx read / write interface definitions
496 * @param val 2g, 4g, 8g, 16g,
497 * @retval interface status (MANDATORY: return 0 -> no Error)
498 *
499 */
lsm6dso16is_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso16is_xl_full_scale_t * val)500 int32_t lsm6dso16is_xl_full_scale_get(const stmdev_ctx_t *ctx,
501 lsm6dso16is_xl_full_scale_t *val)
502 {
503 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
504 int32_t ret;
505
506 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
507
508 switch ((ctrl1_xl.fs_xl))
509 {
510 case LSM6DSO16IS_2g:
511 *val = LSM6DSO16IS_2g;
512 break;
513
514 case LSM6DSO16IS_4g:
515 *val = LSM6DSO16IS_4g;
516 break;
517
518 case LSM6DSO16IS_8g:
519 *val = LSM6DSO16IS_8g;
520 break;
521
522 case LSM6DSO16IS_16g:
523 *val = LSM6DSO16IS_16g;
524 break;
525
526 default:
527 *val = LSM6DSO16IS_2g;
528 break;
529 }
530 return ret;
531 }
532
533 /**
534 * @brief Accelerometer output data rate (ODR) selection.[set]
535 *
536 * @param ctx read / write interface definitions
537 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
538 * @retval interface status (MANDATORY: return 0 -> no Error)
539 *
540 */
lsm6dso16is_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso16is_xl_data_rate_t val)541 int32_t lsm6dso16is_xl_data_rate_set(const stmdev_ctx_t *ctx,
542 lsm6dso16is_xl_data_rate_t val)
543 {
544 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
545 int32_t ret;
546
547 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
548
549 if (ret == 0)
550 {
551 if (((uint8_t)val & 0x10U) == 0x10U)
552 {
553 ret += lsm6dso16is_xl_hm_mode_set(ctx, LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED);
554 }
555 else
556 {
557 ret += lsm6dso16is_xl_hm_mode_set(ctx, LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED);
558 }
559
560 ctrl1_xl.odr_xl = ((uint8_t)val & 0xfU);
561 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
562 }
563
564 return ret;
565 }
566
567 /**
568 * @brief Accelerometer output data rate (ODR) selection.[get]
569 *
570 * @param ctx read / write interface definitions
571 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
572 * @retval interface status (MANDATORY: return 0 -> no Error)
573 *
574 */
lsm6dso16is_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso16is_xl_data_rate_t * val)575 int32_t lsm6dso16is_xl_data_rate_get(const stmdev_ctx_t *ctx,
576 lsm6dso16is_xl_data_rate_t *val)
577 {
578 lsm6dso16is_ctrl1_xl_t ctrl1_xl;
579 lsm6dso16is_ctrl6_c_t ctrl6_c;
580 int32_t ret;
581
582 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
583 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
584
585 switch ((ctrl6_c.xl_hm_mode << 4) | (ctrl1_xl.odr_xl))
586 {
587 case LSM6DSO16IS_XL_ODR_OFF:
588 *val = LSM6DSO16IS_XL_ODR_OFF;
589 break;
590
591 case LSM6DSO16IS_XL_ODR_AT_12Hz5_HP:
592 *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_HP;
593 break;
594
595 case LSM6DSO16IS_XL_ODR_AT_26H_HP:
596 *val = LSM6DSO16IS_XL_ODR_AT_26H_HP;
597 break;
598
599 case LSM6DSO16IS_XL_ODR_AT_52Hz_HP:
600 *val = LSM6DSO16IS_XL_ODR_AT_52Hz_HP;
601 break;
602
603 case LSM6DSO16IS_XL_ODR_AT_104Hz_HP:
604 *val = LSM6DSO16IS_XL_ODR_AT_104Hz_HP;
605 break;
606
607 case LSM6DSO16IS_XL_ODR_AT_208Hz_HP:
608 *val = LSM6DSO16IS_XL_ODR_AT_208Hz_HP;
609 break;
610
611 case LSM6DSO16IS_XL_ODR_AT_416Hz_HP:
612 *val = LSM6DSO16IS_XL_ODR_AT_416Hz_HP;
613 break;
614
615 case LSM6DSO16IS_XL_ODR_AT_833Hz_HP:
616 *val = LSM6DSO16IS_XL_ODR_AT_833Hz_HP;
617 break;
618
619 case LSM6DSO16IS_XL_ODR_AT_1667Hz_HP:
620 *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_HP;
621 break;
622
623 case LSM6DSO16IS_XL_ODR_AT_3333Hz_HP:
624 *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_HP;
625 break;
626
627 case LSM6DSO16IS_XL_ODR_AT_6667Hz_HP:
628 *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_HP;
629 break;
630
631 case LSM6DSO16IS_XL_ODR_AT_12Hz5_LP:
632 *val = LSM6DSO16IS_XL_ODR_AT_12Hz5_LP;
633 break;
634
635 case LSM6DSO16IS_XL_ODR_AT_26H_LP:
636 *val = LSM6DSO16IS_XL_ODR_AT_26H_LP;
637 break;
638
639 case LSM6DSO16IS_XL_ODR_AT_52Hz_LP:
640 *val = LSM6DSO16IS_XL_ODR_AT_52Hz_LP;
641 break;
642
643 case LSM6DSO16IS_XL_ODR_AT_104Hz_LP:
644 *val = LSM6DSO16IS_XL_ODR_AT_104Hz_LP;
645 break;
646
647 case LSM6DSO16IS_XL_ODR_AT_208Hz_LP:
648 *val = LSM6DSO16IS_XL_ODR_AT_208Hz_LP;
649 break;
650
651 case LSM6DSO16IS_XL_ODR_AT_416Hz_LP:
652 *val = LSM6DSO16IS_XL_ODR_AT_416Hz_LP;
653 break;
654
655 case LSM6DSO16IS_XL_ODR_AT_833Hz_LP:
656 *val = LSM6DSO16IS_XL_ODR_AT_833Hz_LP;
657 break;
658
659 case LSM6DSO16IS_XL_ODR_AT_1667Hz_LP:
660 *val = LSM6DSO16IS_XL_ODR_AT_1667Hz_LP;
661 break;
662
663 case LSM6DSO16IS_XL_ODR_AT_3333Hz_LP:
664 *val = LSM6DSO16IS_XL_ODR_AT_3333Hz_LP;
665 break;
666
667 case LSM6DSO16IS_XL_ODR_AT_6667Hz_LP:
668 *val = LSM6DSO16IS_XL_ODR_AT_6667Hz_LP;
669 break;
670
671 case LSM6DSO16IS_XL_ODR_AT_1Hz6_LP:
672 *val = LSM6DSO16IS_XL_ODR_AT_1Hz6_LP;
673 break;
674
675 default:
676 *val = LSM6DSO16IS_XL_ODR_OFF;
677 break;
678 }
679
680 return ret;
681 }
682
683 /**
684 * @brief Enable disable high-performance mode[set]
685 *
686 * @param ctx read / write interface definitions
687 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lsm6dso16is_gy_hm_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t val)691 int32_t lsm6dso16is_gy_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val)
692 {
693 lsm6dso16is_ctrl7_g_t ctrl7_g;
694 int32_t ret;
695
696 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
697
698 if (ret == 0)
699 {
700 ctrl7_g.g_hm_mode = ((uint8_t)val & 0x1U);
701 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
702 }
703
704 return ret;
705 }
706
707 /**
708 * @brief Enable disable high-performance mode[get]
709 *
710 * @param ctx read / write interface definitions
711 * @param val HIGH_PERFOMANCE_MODE_ENABLED, HIGH_PERFOMANCE_MODE_DISABLED,
712 * @retval interface status (MANDATORY: return 0 -> no Error)
713 *
714 */
lsm6dso16is_gy_hm_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_hm_mode_t * val)715 int32_t lsm6dso16is_gy_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val)
716 {
717 lsm6dso16is_ctrl7_g_t ctrl7_g;
718 int32_t ret;
719
720 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
721
722 switch ((ctrl7_g.g_hm_mode))
723 {
724 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED:
725 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
726 break;
727
728 case LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED:
729 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED;
730 break;
731
732 default:
733 *val = LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED;
734 break;
735 }
736 return ret;
737 }
738
739 /**
740 * @brief Gyroscope full-scale selection[set]
741 *
742 * @param ctx read / write interface definitions
743 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
744 * @retval interface status (MANDATORY: return 0 -> no Error)
745 *
746 */
lsm6dso16is_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso16is_gy_full_scale_t val)747 int32_t lsm6dso16is_gy_full_scale_set(const stmdev_ctx_t *ctx,
748 lsm6dso16is_gy_full_scale_t val)
749 {
750 lsm6dso16is_ctrl2_g_t ctrl2_g;
751 int32_t ret;
752
753 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
754
755 if (ret == 0)
756 {
757 ctrl2_g.fs_g = ((uint8_t)val & 0x3U);
758 ctrl2_g.fs_125 = ((uint8_t)val >> 4);
759 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
760 }
761
762 return ret;
763 }
764
765 /**
766 * @brief Gyroscope full-scale selection[get]
767 *
768 * @param ctx read / write interface definitions
769 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
770 * @retval interface status (MANDATORY: return 0 -> no Error)
771 *
772 */
lsm6dso16is_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso16is_gy_full_scale_t * val)773 int32_t lsm6dso16is_gy_full_scale_get(const stmdev_ctx_t *ctx,
774 lsm6dso16is_gy_full_scale_t *val)
775 {
776 lsm6dso16is_ctrl2_g_t ctrl2_g;
777 int32_t ret;
778
779 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
780
781 switch ((ctrl2_g.fs_125 << 4) | (ctrl2_g.fs_g))
782 {
783 case LSM6DSO16IS_125dps:
784 *val = LSM6DSO16IS_125dps;
785 break;
786
787 case LSM6DSO16IS_250dps:
788 *val = LSM6DSO16IS_250dps;
789 break;
790
791 case LSM6DSO16IS_500dps:
792 *val = LSM6DSO16IS_500dps;
793 break;
794
795 case LSM6DSO16IS_1000dps:
796 *val = LSM6DSO16IS_1000dps;
797 break;
798
799 case LSM6DSO16IS_2000dps:
800 *val = LSM6DSO16IS_2000dps;
801 break;
802
803 default:
804 *val = LSM6DSO16IS_125dps;
805 break;
806 }
807 return ret;
808 }
809
810 /**
811 * @brief Gyroscope output data rate (ODR) selection.[set]
812 *
813 * @param ctx read / write interface definitions
814 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
815 * @retval interface status (MANDATORY: return 0 -> no Error)
816 *
817 */
lsm6dso16is_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso16is_gy_data_rate_t val)818 int32_t lsm6dso16is_gy_data_rate_set(const stmdev_ctx_t *ctx,
819 lsm6dso16is_gy_data_rate_t val)
820 {
821 lsm6dso16is_ctrl2_g_t ctrl2_g;
822 int32_t ret;
823
824 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
825
826 if (ret == 0)
827 {
828 if (((uint8_t)val & 0x10U) == 0x10U)
829 {
830 ret += lsm6dso16is_gy_hm_mode_set(ctx, LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED);
831 }
832 else
833 {
834 ret += lsm6dso16is_gy_hm_mode_set(ctx, LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED);
835 }
836
837 ctrl2_g.odr_g = ((uint8_t)val & 0xfU);
838 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
839 }
840
841 return ret;
842 }
843
844 /**
845 * @brief Gyroscope output data rate (ODR) selection.[get]
846 *
847 * @param ctx read / write interface definitions
848 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
849 * @retval interface status (MANDATORY: return 0 -> no Error)
850 *
851 */
lsm6dso16is_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso16is_gy_data_rate_t * val)852 int32_t lsm6dso16is_gy_data_rate_get(const stmdev_ctx_t *ctx,
853 lsm6dso16is_gy_data_rate_t *val)
854 {
855 lsm6dso16is_ctrl2_g_t ctrl2_g;
856 lsm6dso16is_ctrl7_g_t ctrl7_g;
857 int32_t ret;
858
859 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
860 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
861
862 switch ((ctrl7_g.g_hm_mode << 4) | (ctrl2_g.odr_g))
863 {
864 case LSM6DSO16IS_GY_ODR_OFF:
865 *val = LSM6DSO16IS_GY_ODR_OFF;
866 break;
867
868 case LSM6DSO16IS_GY_ODR_AT_12Hz5_HP:
869 *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_HP;
870 break;
871
872 case LSM6DSO16IS_GY_ODR_AT_26H_HP:
873 *val = LSM6DSO16IS_GY_ODR_AT_26H_HP;
874 break;
875
876 case LSM6DSO16IS_GY_ODR_AT_52Hz_HP:
877 *val = LSM6DSO16IS_GY_ODR_AT_52Hz_HP;
878 break;
879
880 case LSM6DSO16IS_GY_ODR_AT_104Hz_HP:
881 *val = LSM6DSO16IS_GY_ODR_AT_104Hz_HP;
882 break;
883
884 case LSM6DSO16IS_GY_ODR_AT_208Hz_HP:
885 *val = LSM6DSO16IS_GY_ODR_AT_208Hz_HP;
886 break;
887
888 case LSM6DSO16IS_GY_ODR_AT_416Hz_HP:
889 *val = LSM6DSO16IS_GY_ODR_AT_416Hz_HP;
890 break;
891
892 case LSM6DSO16IS_GY_ODR_AT_833Hz_HP:
893 *val = LSM6DSO16IS_GY_ODR_AT_833Hz_HP;
894 break;
895
896 case LSM6DSO16IS_GY_ODR_AT_1667Hz_HP:
897 *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_HP;
898 break;
899
900 case LSM6DSO16IS_GY_ODR_AT_3333Hz_HP:
901 *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_HP;
902 break;
903
904 case LSM6DSO16IS_GY_ODR_AT_6667Hz_HP:
905 *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_HP;
906 break;
907
908 case LSM6DSO16IS_GY_ODR_AT_12Hz5_LP:
909 *val = LSM6DSO16IS_GY_ODR_AT_12Hz5_LP;
910 break;
911
912 case LSM6DSO16IS_GY_ODR_AT_26H_LP:
913 *val = LSM6DSO16IS_GY_ODR_AT_26H_LP;
914 break;
915
916 case LSM6DSO16IS_GY_ODR_AT_52Hz_LP:
917 *val = LSM6DSO16IS_GY_ODR_AT_52Hz_LP;
918 break;
919
920 case LSM6DSO16IS_GY_ODR_AT_104Hz_LP:
921 *val = LSM6DSO16IS_GY_ODR_AT_104Hz_LP;
922 break;
923
924 case LSM6DSO16IS_GY_ODR_AT_208Hz_LP:
925 *val = LSM6DSO16IS_GY_ODR_AT_208Hz_LP;
926 break;
927
928 case LSM6DSO16IS_GY_ODR_AT_416Hz_LP:
929 *val = LSM6DSO16IS_GY_ODR_AT_416Hz_LP;
930 break;
931
932 case LSM6DSO16IS_GY_ODR_AT_833Hz_LP:
933 *val = LSM6DSO16IS_GY_ODR_AT_833Hz_LP;
934 break;
935
936 case LSM6DSO16IS_GY_ODR_AT_1667Hz_LP:
937 *val = LSM6DSO16IS_GY_ODR_AT_1667Hz_LP;
938 break;
939
940 case LSM6DSO16IS_GY_ODR_AT_3333Hz_LP:
941 *val = LSM6DSO16IS_GY_ODR_AT_3333Hz_LP;
942 break;
943
944 case LSM6DSO16IS_GY_ODR_AT_6667Hz_LP:
945 *val = LSM6DSO16IS_GY_ODR_AT_6667Hz_LP;
946 break;
947
948 default:
949 *val = LSM6DSO16IS_GY_ODR_OFF;
950 break;
951 }
952
953 return ret;
954 }
955
956 /**
957 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
958 *
959 * @param ctx read / write interface definitions
960 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
961 * @retval interface status (MANDATORY: return 0 -> no Error)
962 *
963 */
lsm6dso16is_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)964 int32_t lsm6dso16is_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
965 {
966 lsm6dso16is_ctrl3_c_t ctrl3_c;
967 int32_t ret;
968
969 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
970
971 if (ret == 0)
972 {
973 ctrl3_c.if_inc = val;
974 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
982 *
983 * @param ctx read / write interface definitions
984 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
985 * @retval interface status (MANDATORY: return 0 -> no Error)
986 *
987 */
lsm6dso16is_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)988 int32_t lsm6dso16is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
989 {
990 lsm6dso16is_ctrl3_c_t ctrl3_c;
991 int32_t ret;
992
993 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
994
995 *val = ctrl3_c.if_inc;
996
997 return ret;
998 }
999
1000 /**
1001 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1002 *
1003 * @param ctx read / write interface definitions
1004 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1005 * @retval interface status (MANDATORY: return 0 -> no Error)
1006 *
1007 */
lsm6dso16is_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)1008 int32_t lsm6dso16is_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
1009 {
1010 lsm6dso16is_ctrl3_c_t ctrl3_c;
1011 int32_t ret;
1012
1013 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1014
1015 if (ret == 0)
1016 {
1017 ctrl3_c.bdu = val;
1018 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1019 }
1020
1021 return ret;
1022 }
1023
1024 /**
1025 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1026 *
1027 * @param ctx read / write interface definitions
1028 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1029 * @retval interface status (MANDATORY: return 0 -> no Error)
1030 *
1031 */
lsm6dso16is_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1032 int32_t lsm6dso16is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
1033 {
1034 lsm6dso16is_ctrl3_c_t ctrl3_c;
1035 int32_t ret;
1036
1037 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1038
1039 *val = ctrl3_c.bdu;
1040
1041 return ret;
1042 }
1043
1044 /**
1045 * @brief Enables gyroscope sleep mode[set]
1046 *
1047 * @param ctx read / write interface definitions
1048 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1049 * @retval interface status (MANDATORY: return 0 -> no Error)
1050 *
1051 */
lsm6dso16is_sleep_set(const stmdev_ctx_t * ctx,lsm6dso16is_sleep_t val)1052 int32_t lsm6dso16is_sleep_set(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val)
1053 {
1054 lsm6dso16is_ctrl4_c_t ctrl4_c;
1055 int32_t ret;
1056
1057 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1058
1059 if (ret == 0)
1060 {
1061 ctrl4_c.sleep_g = ((uint8_t)val & 0x1U);
1062 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1063 }
1064
1065 return ret;
1066 }
1067
1068 /**
1069 * @brief Enables gyroscope sleep mode[get]
1070 *
1071 * @param ctx read / write interface definitions
1072 * @param val SLEEP_G_ENABLE, SLEEP_G_DISABLE,
1073 * @retval interface status (MANDATORY: return 0 -> no Error)
1074 *
1075 */
lsm6dso16is_sleep_get(const stmdev_ctx_t * ctx,lsm6dso16is_sleep_t * val)1076 int32_t lsm6dso16is_sleep_get(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val)
1077 {
1078 lsm6dso16is_ctrl4_c_t ctrl4_c;
1079 int32_t ret;
1080
1081 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1082
1083 switch ((ctrl4_c.sleep_g))
1084 {
1085 case LSM6DSO16IS_SLEEP_G_ENABLE:
1086 *val = LSM6DSO16IS_SLEEP_G_ENABLE;
1087 break;
1088
1089 case LSM6DSO16IS_SLEEP_G_DISABLE:
1090 *val = LSM6DSO16IS_SLEEP_G_DISABLE;
1091 break;
1092
1093 default:
1094 *val = LSM6DSO16IS_SLEEP_G_ENABLE;
1095 break;
1096 }
1097 return ret;
1098 }
1099
1100 /**
1101 * @brief Accelerometer self-test selection.[set]
1102 *
1103 * @param ctx read / write interface definitions
1104 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1105 * @retval interface status (MANDATORY: return 0 -> no Error)
1106 *
1107 */
lsm6dso16is_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dso16is_xl_self_test_t val)1108 int32_t lsm6dso16is_xl_self_test_set(const stmdev_ctx_t *ctx,
1109 lsm6dso16is_xl_self_test_t val)
1110 {
1111 lsm6dso16is_ctrl5_c_t ctrl5_c;
1112 int32_t ret;
1113
1114 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1115
1116 if (ret == 0)
1117 {
1118 ctrl5_c.st_xl = ((uint8_t)val & 0x3U);
1119 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1120 }
1121
1122 return ret;
1123 }
1124
1125 /**
1126 * @brief Accelerometer self-test selection.[get]
1127 *
1128 * @param ctx read / write interface definitions
1129 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1130 * @retval interface status (MANDATORY: return 0 -> no Error)
1131 *
1132 */
lsm6dso16is_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dso16is_xl_self_test_t * val)1133 int32_t lsm6dso16is_xl_self_test_get(const stmdev_ctx_t *ctx,
1134 lsm6dso16is_xl_self_test_t *val)
1135 {
1136 lsm6dso16is_ctrl5_c_t ctrl5_c;
1137 int32_t ret;
1138
1139 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1140
1141 switch ((ctrl5_c.st_xl))
1142 {
1143 case LSM6DSO16IS_XL_ST_DISABLE:
1144 *val = LSM6DSO16IS_XL_ST_DISABLE;
1145 break;
1146
1147 case LSM6DSO16IS_XL_ST_POSITIVE:
1148 *val = LSM6DSO16IS_XL_ST_POSITIVE;
1149 break;
1150
1151 case LSM6DSO16IS_XL_ST_NEGATIVE:
1152 *val = LSM6DSO16IS_XL_ST_NEGATIVE;
1153 break;
1154
1155 default:
1156 *val = LSM6DSO16IS_XL_ST_DISABLE;
1157 break;
1158 }
1159 return ret;
1160 }
1161
1162 /**
1163 * @brief Gyroscope self-test selection.[set]
1164 *
1165 * @param ctx read / write interface definitions
1166 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1167 * @retval interface status (MANDATORY: return 0 -> no Error)
1168 *
1169 */
lsm6dso16is_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dso16is_gy_self_test_t val)1170 int32_t lsm6dso16is_gy_self_test_set(const stmdev_ctx_t *ctx,
1171 lsm6dso16is_gy_self_test_t val)
1172 {
1173 lsm6dso16is_ctrl5_c_t ctrl5_c;
1174 int32_t ret;
1175
1176 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1177
1178 if (ret == 0)
1179 {
1180 ctrl5_c.st_g = ((uint8_t)val & 0x3U);
1181 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1182 }
1183
1184 return ret;
1185 }
1186
1187 /**
1188 * @brief Gyroscope self-test selection.[get]
1189 *
1190 * @param ctx read / write interface definitions
1191 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE,
1192 * @retval interface status (MANDATORY: return 0 -> no Error)
1193 *
1194 */
lsm6dso16is_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dso16is_gy_self_test_t * val)1195 int32_t lsm6dso16is_gy_self_test_get(const stmdev_ctx_t *ctx,
1196 lsm6dso16is_gy_self_test_t *val)
1197 {
1198 lsm6dso16is_ctrl5_c_t ctrl5_c;
1199 int32_t ret;
1200
1201 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1202
1203 switch ((ctrl5_c.st_g))
1204 {
1205 case LSM6DSO16IS_GY_ST_DISABLE:
1206 *val = LSM6DSO16IS_GY_ST_DISABLE;
1207 break;
1208
1209 case LSM6DSO16IS_GY_ST_POSITIVE:
1210 *val = LSM6DSO16IS_GY_ST_POSITIVE;
1211 break;
1212
1213 case LSM6DSO16IS_GY_ST_NEGATIVE:
1214 *val = LSM6DSO16IS_GY_ST_NEGATIVE;
1215 break;
1216
1217 default:
1218 *val = LSM6DSO16IS_GY_ST_DISABLE;
1219 break;
1220 }
1221 return ret;
1222 }
1223
1224 /**
1225 * @defgroup Serial Interfaces
1226 * @brief Serial Interfaces
1227 * @{/
1228 *
1229 */
1230 /**
1231 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
1232 *
1233 * @param ctx read / write interface definitions
1234 * @param val Enables pull-up on SDO pin of UI (User Interface).
1235 * @retval interface status (MANDATORY: return 0 -> no Error)
1236 *
1237 */
lsm6dso16is_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)1238 int32_t lsm6dso16is_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
1239 {
1240 lsm6dso16is_pin_ctrl_t pin_ctrl;
1241 int32_t ret;
1242
1243 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1244
1245 if (ret == 0)
1246 {
1247 pin_ctrl.sdo_pu_en = val;
1248 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1249 }
1250
1251 return ret;
1252 }
1253
1254 /**
1255 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
1256 *
1257 * @param ctx read / write interface definitions
1258 * @param val Enables pull-up on SDO pin of UI (User Interface).
1259 * @retval interface status (MANDATORY: return 0 -> no Error)
1260 *
1261 */
lsm6dso16is_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)1262 int32_t lsm6dso16is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
1263 {
1264 lsm6dso16is_pin_ctrl_t pin_ctrl;
1265 int32_t ret;
1266
1267 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1268
1269 *val = pin_ctrl.sdo_pu_en;
1270
1271 return ret;
1272 }
1273
1274 /**
1275 * @brief SPI Serial Interface Mode selection.[set]
1276 *
1277 * @param ctx read / write interface definitions
1278 * @param val SPI_4_WIRE, SPI_3_WIRE,
1279 * @retval interface status (MANDATORY: return 0 -> no Error)
1280 *
1281 */
lsm6dso16is_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_spi_mode_t val)1282 int32_t lsm6dso16is_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val)
1283 {
1284 lsm6dso16is_ctrl3_c_t ctrl3_c;
1285 int32_t ret;
1286
1287 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1288
1289 if (ret == 0)
1290 {
1291 ctrl3_c.sim = ((uint8_t)val & 0x1U);
1292 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1293 }
1294
1295 return ret;
1296 }
1297
1298 /**
1299 * @brief SPI Serial Interface Mode selection.[get]
1300 *
1301 * @param ctx read / write interface definitions
1302 * @param val SPI_4_WIRE, SPI_3_WIRE,
1303 * @retval interface status (MANDATORY: return 0 -> no Error)
1304 *
1305 */
lsm6dso16is_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_spi_mode_t * val)1306 int32_t lsm6dso16is_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val)
1307 {
1308 lsm6dso16is_ctrl3_c_t ctrl3_c;
1309 int32_t ret;
1310
1311 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1312
1313 switch ((ctrl3_c.sim))
1314 {
1315 case LSM6DSO16IS_SPI_4_WIRE:
1316 *val = LSM6DSO16IS_SPI_4_WIRE;
1317 break;
1318
1319 case LSM6DSO16IS_SPI_3_WIRE:
1320 *val = LSM6DSO16IS_SPI_3_WIRE;
1321 break;
1322
1323 default:
1324 *val = LSM6DSO16IS_SPI_4_WIRE;
1325 break;
1326 }
1327 return ret;
1328 }
1329
1330 /**
1331 * @brief Disables I2C on UI (User Interface).[set]
1332 *
1333 * @param ctx read / write interface definitions
1334 * @param val I2C_ENABLE, I2C_DISABLE,
1335 * @retval interface status (MANDATORY: return 0 -> no Error)
1336 *
1337 */
lsm6dso16is_ui_i2c_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_ui_i2c_mode_t val)1338 int32_t lsm6dso16is_ui_i2c_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t val)
1339 {
1340 lsm6dso16is_ctrl4_c_t ctrl4_c;
1341 int32_t ret;
1342
1343 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1344
1345 if (ret == 0)
1346 {
1347 ctrl4_c.i2c_disable = ((uint8_t)val & 0x1U);
1348 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1349 }
1350
1351 return ret;
1352 }
1353
1354 /**
1355 * @brief Disables I2C on UI (User Interface).[get]
1356 *
1357 * @param ctx read / write interface definitions
1358 * @param val I2C_ENABLE, I2C_DISABLE,
1359 * @retval interface status (MANDATORY: return 0 -> no Error)
1360 *
1361 */
lsm6dso16is_ui_i2c_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_ui_i2c_mode_t * val)1362 int32_t lsm6dso16is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t *val)
1363 {
1364 lsm6dso16is_ctrl4_c_t ctrl4_c;
1365 int32_t ret;
1366
1367 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1368
1369 switch ((ctrl4_c.i2c_disable))
1370 {
1371 case LSM6DSO16IS_I2C_ENABLE:
1372 *val = LSM6DSO16IS_I2C_ENABLE;
1373 break;
1374
1375 case LSM6DSO16IS_I2C_DISABLE:
1376 *val = LSM6DSO16IS_I2C_DISABLE;
1377 break;
1378
1379 default:
1380 *val = LSM6DSO16IS_I2C_ENABLE;
1381 break;
1382 }
1383 return ret;
1384 }
1385
1386 /**
1387 * @}
1388 *
1389 */
1390
1391 /**
1392 * @defgroup Timestamp
1393 * @brief Timestamp
1394 * @{/
1395 *
1396 */
1397 /**
1398 * @brief Enables timestamp counter.[set]
1399 *
1400 * @param ctx read / write interface definitions
1401 * @param val Enables timestamp counter.
1402 * @retval interface status (MANDATORY: return 0 -> no Error)
1403 *
1404 */
lsm6dso16is_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1405 int32_t lsm6dso16is_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1406 {
1407 lsm6dso16is_ctrl10_c_t ctrl10_c;
1408 int32_t ret;
1409
1410 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1411
1412 if (ret == 0)
1413 {
1414 ctrl10_c.timestamp_en = val;
1415 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1416 }
1417
1418 return ret;
1419 }
1420
1421 /**
1422 * @brief Enables timestamp counter.[get]
1423 *
1424 * @param ctx read / write interface definitions
1425 * @param val Enables timestamp counter.
1426 * @retval interface status (MANDATORY: return 0 -> no Error)
1427 *
1428 */
lsm6dso16is_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1429 int32_t lsm6dso16is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1430 {
1431 lsm6dso16is_ctrl10_c_t ctrl10_c;
1432 int32_t ret;
1433
1434 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1435
1436 *val = ctrl10_c.timestamp_en;
1437
1438 return ret;
1439 }
1440
1441 /**
1442 * @brief Timestamp data output.[get]
1443 *
1444 * @param ctx read / write interface definitions
1445 * @param val Timestamp data output.
1446 * @retval interface status (MANDATORY: return 0 -> no Error)
1447 *
1448 */
lsm6dso16is_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1449 int32_t lsm6dso16is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1450 {
1451 uint8_t buff[4];
1452 int32_t ret;
1453
1454 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_TIMESTAMP0, &buff[0], 4);
1455
1456 *val = (uint32_t)buff[3];
1457 *val = (*val * 256U) + (uint32_t)buff[2];
1458 *val = (*val * 256U) + (uint32_t)buff[1];
1459 *val = (*val * 256U) + (uint32_t)buff[0];
1460
1461 return ret;
1462 }
1463
1464 /**
1465 * @}
1466 *
1467 */
1468
1469 /**
1470 * @brief Get the status of all the interrupt sources.[get]
1471 *
1472 * @param ctx read / write interface definitions
1473 * @param val Get the status of all the interrupt sources.
1474 * @retval interface status (MANDATORY: return 0 -> no Error)
1475 *
1476 */
lsm6dso16is_all_sources_get(const stmdev_ctx_t * ctx,lsm6dso16is_all_sources_t * val)1477 int32_t lsm6dso16is_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t *val)
1478 {
1479 lsm6dso16is_status_reg_t status_reg;
1480 lsm6dso16is_status_master_mainpage_t status_sh;
1481 uint32_t status_ispu;
1482 int32_t ret;
1483
1484 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1);
1485 if (ret != 0)
1486 {
1487 return ret;
1488 }
1489
1490 val->drdy_xl = status_reg.xlda;
1491 val->drdy_gy = status_reg.gda;
1492 val->drdy_temp = status_reg.tda;
1493
1494 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1);
1495 if (ret != 0)
1496 {
1497 return ret;
1498 }
1499
1500 val->sh_endop = status_sh.sens_hub_endop;
1501 val->sh_slave0_nack = status_sh.sens_hub_endop;
1502 val->sh_slave1_nack = status_sh.sens_hub_endop;
1503 val->sh_slave2_nack = status_sh.sens_hub_endop;
1504 val->sh_slave3_nack = status_sh.sens_hub_endop;
1505 val->sh_wr_once = status_sh.sens_hub_endop;
1506
1507 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4);
1508 if (ret != 0)
1509 {
1510 return ret;
1511 }
1512
1513 val->ispu = status_ispu;
1514
1515 return ret;
1516 }
1517
1518 /**
1519 * @brief The STATUS_REG register is read by the primary interface.[get]
1520 *
1521 * @param ctx Read / write interface definitions.(ptr)
1522 * @param val Get register STATUS_REG
1523 * @retval Interface status (MANDATORY: return 0 -> no Error).
1524 *
1525 */
lsm6dso16is_status_reg_get(const stmdev_ctx_t * ctx,lsm6dso16is_status_reg_t * val)1526 int32_t lsm6dso16is_status_reg_get(const stmdev_ctx_t *ctx,
1527 lsm6dso16is_status_reg_t *val)
1528 {
1529 int32_t ret;
1530 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *) val, 1);
1531
1532 return ret;
1533 }
1534
1535 /**
1536 * @brief Accelerometer new data available.[get]
1537 *
1538 * @param ctx Read / write interface definitions.(ptr)
1539 * @param val Change the values of xlda in reg STATUS_REG
1540 * @retval Interface status (MANDATORY: return 0 -> no Error).
1541 *
1542 */
lsm6dso16is_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1543 int32_t lsm6dso16is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
1544 uint8_t *val)
1545 {
1546 lsm6dso16is_status_reg_t status_reg;
1547 int32_t ret;
1548 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1549 (uint8_t *)&status_reg, 1);
1550 *val = status_reg.xlda;
1551
1552 return ret;
1553 }
1554
1555 /**
1556 * @brief Gyroscope new data available.[get]
1557 *
1558 * @param ctx Read / write interface definitions.(ptr)
1559 * @param val Change the values of gda in reg STATUS_REG
1560 * @retval Interface status (MANDATORY: return 0 -> no Error).
1561 *
1562 */
lsm6dso16is_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1563 int32_t lsm6dso16is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1564 uint8_t *val)
1565 {
1566 lsm6dso16is_status_reg_t status_reg;
1567 int32_t ret;
1568 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1569 (uint8_t *)&status_reg, 1);
1570 *val = status_reg.gda;
1571
1572 return ret;
1573 }
1574
1575 /**
1576 * @brief Temperature new data available.[get]
1577 *
1578 * @param ctx Read / write interface definitions.(ptr)
1579 * @param val Change the values of tda in reg STATUS_REG
1580 * @retval Interface status (MANDATORY: return 0 -> no Error).
1581 *
1582 */
lsm6dso16is_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1583 int32_t lsm6dso16is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1584 uint8_t *val)
1585 {
1586 lsm6dso16is_status_reg_t status_reg;
1587 int32_t ret;
1588 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG,
1589 (uint8_t *)&status_reg, 1);
1590 *val = status_reg.tda;
1591
1592 return ret;
1593 }
1594
1595 /**
1596 * @brief Temperature data output register[get]
1597 *
1598 * @param ctx read / write interface definitions
1599 * @param val Temperature data output register
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
lsm6dso16is_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1603 int32_t lsm6dso16is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1604 {
1605 uint8_t buff[2];
1606 int32_t ret;
1607
1608 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUT_TEMP_L, &buff[0], 2);
1609 *val = (int16_t)buff[1];
1610 *val = (*val * 256) + (int16_t)buff[0];
1611
1612 return ret;
1613 }
1614
1615 /**
1616 * @brief Angular rate sensor.[get]
1617 *
1618 * @param ctx read / write interface definitions
1619 * @param val Angular rate sensor.
1620 * @retval interface status (MANDATORY: return 0 -> no Error)
1621 *
1622 */
lsm6dso16is_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1623 int32_t lsm6dso16is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1624 {
1625 uint8_t buff[6];
1626 int32_t ret;
1627
1628 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_G, buff, 6);
1629 val[0] = (int16_t)buff[1];
1630 val[0] = (val[0] * 256) + (int16_t)buff[0];
1631 val[1] = (int16_t)buff[3];
1632 val[1] = (val[1] * 256) + (int16_t)buff[2];
1633 val[2] = (int16_t)buff[5];
1634 val[2] = (val[2] * 256) + (int16_t)buff[4];
1635
1636 return ret;
1637 }
1638
1639 /**
1640 * @brief Linear acceleration sensor.[get]
1641 *
1642 * @param ctx read / write interface definitions
1643 * @param val Linear acceleration sensor.
1644 * @retval interface status (MANDATORY: return 0 -> no Error)
1645 *
1646 */
lsm6dso16is_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1647 int32_t lsm6dso16is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1648 {
1649 uint8_t buff[6];
1650 int32_t ret;
1651
1652 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_OUTX_L_A, buff, 6);
1653 val[0] = (int16_t)buff[1];
1654 val[0] = (val[0] * 256) + (int16_t)buff[0];
1655 val[1] = (int16_t)buff[3];
1656 val[1] = (val[1] * 256) + (int16_t)buff[2];
1657 val[2] = (int16_t)buff[5];
1658 val[2] = (val[2] * 256) + (int16_t)buff[4];
1659
1660 return ret;
1661 }
1662
1663 /**
1664 * @}
1665 *
1666 */
1667
1668 /**
1669 * @defgroup Interrupt PINs
1670 * @brief Interrupt PINs
1671 * @{/
1672 *
1673 */
1674 /**
1675 * @brief It routes interrupt signals on INT 1 pin.[set]
1676 *
1677 * @param ctx read / write interface definitions
1678 * @param val It routes interrupt signals on INT 1 pin.
1679 * @retval interface status (MANDATORY: return 0 -> no Error)
1680 *
1681 */
lsm6dso16is_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dso16is_pin_int1_route_t val)1682 int32_t lsm6dso16is_pin_int1_route_set(const stmdev_ctx_t *ctx,
1683 lsm6dso16is_pin_int1_route_t val)
1684 {
1685 lsm6dso16is_int1_ctrl_t int1_ctrl;
1686 lsm6dso16is_md1_cfg_t md1_cfg;
1687 int32_t ret;
1688
1689 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1690 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1691 if (ret != 0)
1692 {
1693 return ret;
1694 }
1695
1696 int1_ctrl.int1_drdy_xl = val.drdy_xl;
1697 int1_ctrl.int1_drdy_g = val.drdy_gy;
1698 int1_ctrl.int1_boot = val.boot;
1699 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl,
1700 1);
1701
1702 md1_cfg.int1_shub = val.sh_endop;
1703 md1_cfg.int1_ispu = val.ispu;
1704 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1705
1706 return ret;
1707 }
1708
1709 /**
1710 * @brief It routes interrupt signals on INT 1 pin.[get]
1711 *
1712 * @param ctx read / write interface definitions
1713 * @param val It routes interrupt signals on INT 1 pin.
1714 * @retval interface status (MANDATORY: return 0 -> no Error)
1715 *
1716 */
lsm6dso16is_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dso16is_pin_int1_route_t * val)1717 int32_t lsm6dso16is_pin_int1_route_get(const stmdev_ctx_t *ctx,
1718 lsm6dso16is_pin_int1_route_t *val)
1719 {
1720 lsm6dso16is_int1_ctrl_t int1_ctrl;
1721 lsm6dso16is_md1_cfg_t md1_cfg;
1722 int32_t ret;
1723
1724 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1725 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1726 if (ret != 0)
1727 {
1728 return ret;
1729 }
1730
1731 val->drdy_xl = int1_ctrl.int1_drdy_xl;
1732 val->drdy_gy = int1_ctrl.int1_drdy_g;
1733 val->boot = int1_ctrl.int1_boot;
1734 val->sh_endop = md1_cfg.int1_shub;
1735 val->ispu = md1_cfg.int1_ispu;
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief It routes interrupt signals on INT 2 pin.[set]
1742 *
1743 * @param ctx read / write interface definitions
1744 * @param val It routes interrupt signals on INT 2 pin.
1745 * @retval interface status (MANDATORY: return 0 -> no Error)
1746 *
1747 */
lsm6dso16is_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dso16is_pin_int2_route_t val)1748 int32_t lsm6dso16is_pin_int2_route_set(const stmdev_ctx_t *ctx,
1749 lsm6dso16is_pin_int2_route_t val)
1750 {
1751 lsm6dso16is_int2_ctrl_t int2_ctrl;
1752 lsm6dso16is_md2_cfg_t md2_cfg;
1753 int32_t ret;
1754
1755 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1756 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1757 if (ret != 0)
1758 {
1759 return ret;
1760 }
1761
1762 int2_ctrl.int2_drdy_xl = val.drdy_xl;
1763 int2_ctrl.int2_drdy_g = val.drdy_gy;
1764 int2_ctrl.int2_drdy_temp = val.drdy_temp;
1765 int2_ctrl.int2_sleep_ispu = val.ispu_sleep;
1766 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1767
1768 md2_cfg.int2_ispu = val.ispu;
1769 md2_cfg.int2_timestamp = val.timestamp;
1770 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1771
1772 return ret;
1773 }
1774
1775 /**
1776 * @brief It routes interrupt signals on INT 2 pin.[get]
1777 *
1778 * @param ctx read / write interface definitions
1779 * @param val It routes interrupt signals on INT 2 pin.
1780 * @retval interface status (MANDATORY: return 0 -> no Error)
1781 *
1782 */
lsm6dso16is_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dso16is_pin_int2_route_t * val)1783 int32_t lsm6dso16is_pin_int2_route_get(const stmdev_ctx_t *ctx,
1784 lsm6dso16is_pin_int2_route_t *val)
1785 {
1786 lsm6dso16is_int2_ctrl_t int2_ctrl;
1787 lsm6dso16is_md2_cfg_t md2_cfg;
1788 int32_t ret;
1789
1790 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1791 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1792 if (ret != 0)
1793 {
1794 return ret;
1795 }
1796
1797 val->drdy_xl = int2_ctrl.int2_drdy_xl;
1798 val->drdy_gy = int2_ctrl.int2_drdy_g;
1799 val->drdy_temp = int2_ctrl.int2_drdy_temp;
1800 val->ispu_sleep = int2_ctrl.int2_sleep_ispu;
1801 val->ispu = md2_cfg.int2_ispu;
1802 val->timestamp = md2_cfg.int2_timestamp;
1803
1804 return ret;
1805 }
1806
1807 /**
1808 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
1809 *
1810 * @param ctx read / write interface definitions
1811 * @param val PUSH_PULL, OPEN_DRAIN,
1812 * @retval interface status (MANDATORY: return 0 -> no Error)
1813 *
1814 */
lsm6dso16is_int_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_int_pin_mode_t val)1815 int32_t lsm6dso16is_int_pin_mode_set(const stmdev_ctx_t *ctx,
1816 lsm6dso16is_int_pin_mode_t val)
1817 {
1818 lsm6dso16is_ctrl3_c_t ctrl3_c;
1819 int32_t ret;
1820
1821 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1822
1823 if (ret == 0)
1824 {
1825 ctrl3_c.pp_od = ((uint8_t)val & 0x1U);
1826 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1827 }
1828
1829 return ret;
1830 }
1831
1832 /**
1833 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
1834 *
1835 * @param ctx read / write interface definitions
1836 * @param val PUSH_PULL, OPEN_DRAIN,
1837 * @retval interface status (MANDATORY: return 0 -> no Error)
1838 *
1839 */
lsm6dso16is_int_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_int_pin_mode_t * val)1840 int32_t lsm6dso16is_int_pin_mode_get(const stmdev_ctx_t *ctx,
1841 lsm6dso16is_int_pin_mode_t *val)
1842 {
1843 lsm6dso16is_ctrl3_c_t ctrl3_c;
1844 int32_t ret;
1845
1846 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1847
1848 switch ((ctrl3_c.pp_od))
1849 {
1850 case LSM6DSO16IS_PUSH_PULL:
1851 *val = LSM6DSO16IS_PUSH_PULL;
1852 break;
1853
1854 case LSM6DSO16IS_OPEN_DRAIN:
1855 *val = LSM6DSO16IS_OPEN_DRAIN;
1856 break;
1857
1858 default:
1859 *val = LSM6DSO16IS_PUSH_PULL;
1860 break;
1861 }
1862 return ret;
1863 }
1864
1865 /**
1866 * @brief Interrupt activation level.[set]
1867 *
1868 * @param ctx read / write interface definitions
1869 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1870 * @retval interface status (MANDATORY: return 0 -> no Error)
1871 *
1872 */
lsm6dso16is_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dso16is_pin_polarity_t val)1873 int32_t lsm6dso16is_pin_polarity_set(const stmdev_ctx_t *ctx,
1874 lsm6dso16is_pin_polarity_t val)
1875 {
1876 lsm6dso16is_ctrl3_c_t ctrl3_c;
1877 int32_t ret;
1878
1879 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1880
1881 if (ret == 0)
1882 {
1883 ctrl3_c.h_lactive = ((uint8_t)val & 0x1U);
1884 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1885 }
1886
1887 return ret;
1888 }
1889
1890 /**
1891 * @brief Interrupt activation level.[get]
1892 *
1893 * @param ctx read / write interface definitions
1894 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1895 * @retval interface status (MANDATORY: return 0 -> no Error)
1896 *
1897 */
lsm6dso16is_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dso16is_pin_polarity_t * val)1898 int32_t lsm6dso16is_pin_polarity_get(const stmdev_ctx_t *ctx,
1899 lsm6dso16is_pin_polarity_t *val)
1900 {
1901 lsm6dso16is_ctrl3_c_t ctrl3_c;
1902 int32_t ret;
1903
1904 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1905
1906 switch ((ctrl3_c.h_lactive))
1907 {
1908 case LSM6DSO16IS_ACTIVE_HIGH:
1909 *val = LSM6DSO16IS_ACTIVE_HIGH;
1910 break;
1911
1912 case LSM6DSO16IS_ACTIVE_LOW:
1913 *val = LSM6DSO16IS_ACTIVE_LOW;
1914 break;
1915
1916 default:
1917 *val = LSM6DSO16IS_ACTIVE_HIGH;
1918 break;
1919 }
1920 return ret;
1921 }
1922
1923 /**
1924 * @}
1925 *
1926 */
1927
1928 /**
1929 * @defgroup Sensor hub
1930 * @brief This section groups all the functions that manage the
1931 * sensor hub.
1932 * @{
1933 *
1934 */
1935
1936 /**
1937 * @brief Sensor hub output registers.[get]
1938 *
1939 * @param ctx read / write interface definitions
1940 * @param val Sensor hub output registers.
1941 * @retval interface status (MANDATORY: return 0 -> no Error)
1942 *
1943 */
lsm6dso16is_sh_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)1944 int32_t lsm6dso16is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val,
1945 uint8_t len)
1946 {
1947 int32_t ret;
1948
1949 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
1950 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SENSOR_HUB_1, val, len);
1951 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
1952
1953 return ret;
1954 }
1955
1956 /**
1957 * @brief Number of external sensors to be read by the sensor hub.[set]
1958 *
1959 * @param ctx read / write interface definitions
1960 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
1961 * @retval interface status (MANDATORY: return 0 -> no Error)
1962 *
1963 */
lsm6dso16is_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dso16is_sh_slave_connected_t val)1964 int32_t lsm6dso16is_sh_slave_connected_set(const stmdev_ctx_t *ctx,
1965 lsm6dso16is_sh_slave_connected_t val)
1966 {
1967 lsm6dso16is_master_config_t master_config;
1968 int32_t ret;
1969
1970 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
1971 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1972 if (ret != 0)
1973 {
1974 goto exit;
1975 }
1976
1977 master_config.aux_sens_on = (uint8_t)val & 0x3U;
1978 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
1979
1980 exit:
1981 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
1982
1983 return ret;
1984 }
1985
1986 /**
1987 * @brief Number of external sensors to be read by the sensor hub.[get]
1988 *
1989 * @param ctx read / write interface definitions
1990 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
1991 * @retval interface status (MANDATORY: return 0 -> no Error)
1992 *
1993 */
lsm6dso16is_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dso16is_sh_slave_connected_t * val)1994 int32_t lsm6dso16is_sh_slave_connected_get(const stmdev_ctx_t *ctx,
1995 lsm6dso16is_sh_slave_connected_t *val)
1996 {
1997 lsm6dso16is_master_config_t master_config;
1998 int32_t ret;
1999
2000 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2001 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2002 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2003 if (ret != 0)
2004 {
2005 return ret;
2006 }
2007
2008 switch (master_config.aux_sens_on)
2009 {
2010 case LSM6DSO16IS_SLV_0:
2011 *val = LSM6DSO16IS_SLV_0;
2012 break;
2013
2014 case LSM6DSO16IS_SLV_0_1:
2015 *val = LSM6DSO16IS_SLV_0_1;
2016 break;
2017
2018 case LSM6DSO16IS_SLV_0_1_2:
2019 *val = LSM6DSO16IS_SLV_0_1_2;
2020 break;
2021
2022 case LSM6DSO16IS_SLV_0_1_2_3:
2023 *val = LSM6DSO16IS_SLV_0_1_2_3;
2024 break;
2025
2026 default:
2027 *val = LSM6DSO16IS_SLV_0;
2028 break;
2029 }
2030
2031 return ret;
2032 }
2033
2034 /**
2035 * @brief Sensor hub I2C master enable.[set]
2036 *
2037 * @param ctx read / write interface definitions
2038 * @param val Sensor hub I2C master enable.
2039 * @retval interface status (MANDATORY: return 0 -> no Error)
2040 *
2041 */
lsm6dso16is_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)2042 int32_t lsm6dso16is_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
2043 {
2044 lsm6dso16is_master_config_t master_config;
2045 int32_t ret;
2046
2047 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2048 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2049 if (ret != 0)
2050 {
2051 goto exit;
2052 }
2053
2054 master_config.master_on = val;
2055 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2056
2057 exit:
2058 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2059
2060 return ret;
2061 }
2062
2063 /**
2064 * @brief Sensor hub I2C master enable.[get]
2065 *
2066 * @param ctx read / write interface definitions
2067 * @param val Sensor hub I2C master enable.
2068 * @retval interface status (MANDATORY: return 0 -> no Error)
2069 *
2070 */
lsm6dso16is_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)2071 int32_t lsm6dso16is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
2072 {
2073 lsm6dso16is_master_config_t master_config;
2074 int32_t ret;
2075
2076 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2077 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2078 if (ret != 0)
2079 {
2080 return ret;
2081 }
2082
2083 *val = master_config.master_on;
2084
2085 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2086
2087 return ret;
2088 }
2089
2090 /**
2091 * @brief Sensor Hub master I2C pull-up enable.[set]
2092 *
2093 * @param ctx read / write interface definitions
2094 * @param val Sensor Hub master I2C pull-up enable.
2095 * @retval interface status (MANDATORY: return 0 -> no Error)
2096 *
2097 */
lsm6dso16is_sh_master_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2098 int32_t lsm6dso16is_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2099 {
2100 lsm6dso16is_master_config_t master_config;
2101 int32_t ret;
2102
2103 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2104 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2105 if (ret != 0)
2106 {
2107 goto exit;
2108 }
2109
2110 master_config.shub_pu_en = val;
2111 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2112
2113 exit:
2114 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2115
2116 return ret;
2117 }
2118
2119 /**
2120 * @brief Sensor Hub master I2C pull-up enable.[get]
2121 *
2122 * @param ctx read / write interface definitions
2123 * @param val Sensor Hub master I2C pull-up enable.
2124 * @retval interface status (MANDATORY: return 0 -> no Error)
2125 *
2126 */
lsm6dso16is_sh_master_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2127 int32_t lsm6dso16is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx,
2128 uint8_t *val)
2129 {
2130 lsm6dso16is_master_config_t master_config;
2131 int32_t ret;
2132
2133 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2134 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2135 if (ret != 0)
2136 {
2137 return ret;
2138 }
2139
2140 *val = master_config.shub_pu_en;
2141
2142 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2143
2144 return ret;
2145 }
2146
2147 /**
2148 * @brief I2C interface pass-through.[set]
2149 *
2150 * @param ctx Read / write interface definitions.(ptr)
2151 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2152 * @retval Interface status (MANDATORY: return 0 -> no Error).
2153 *
2154 */
lsm6dso16is_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)2155 int32_t lsm6dso16is_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
2156 {
2157 lsm6dso16is_master_config_t master_config;
2158 int32_t ret;
2159
2160 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2161 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2162 if (ret != 0)
2163 {
2164 goto exit;
2165 }
2166
2167 master_config.pass_through_mode = (uint8_t)val;
2168 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2169
2170 exit:
2171 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2172
2173 return ret;
2174 }
2175
2176 /**
2177 * @brief I2C interface pass-through.[get]
2178 *
2179 * @param ctx Read / write interface definitions.(ptr)
2180 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
2181 * @retval Interface status (MANDATORY: return 0 -> no Error).
2182 *
2183 */
lsm6dso16is_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)2184 int32_t lsm6dso16is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
2185 {
2186 lsm6dso16is_master_config_t master_config;
2187 int32_t ret;
2188
2189 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2190 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2191
2192 *val = master_config.pass_through_mode;
2193 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2194
2195 return ret;
2196 }
2197
2198 /**
2199 * @brief Sensor hub trigger signal selection.[set]
2200 *
2201 * @param ctx read / write interface definitions
2202 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2203 * @retval interface status (MANDATORY: return 0 -> no Error)
2204 *
2205 */
lsm6dso16is_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_sh_syncro_mode_t val)2206 int32_t lsm6dso16is_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
2207 lsm6dso16is_sh_syncro_mode_t val)
2208 {
2209 lsm6dso16is_master_config_t master_config;
2210 int32_t ret;
2211
2212 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2213 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2214 if (ret != 0)
2215 {
2216 goto exit;
2217 }
2218
2219 master_config.start_config = (uint8_t)val & 0x01U;
2220 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2221
2222 exit:
2223 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2224
2225 return ret;
2226 }
2227
2228 /**
2229 * @brief Sensor hub trigger signal selection.[get]
2230 *
2231 * @param ctx read / write interface definitions
2232 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
2233 * @retval interface status (MANDATORY: return 0 -> no Error)
2234 *
2235 */
lsm6dso16is_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_sh_syncro_mode_t * val)2236 int32_t lsm6dso16is_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
2237 lsm6dso16is_sh_syncro_mode_t *val)
2238 {
2239 lsm6dso16is_master_config_t master_config;
2240 int32_t ret;
2241
2242 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2243 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2244 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2245 if (ret != 0)
2246 {
2247 return ret;
2248 }
2249
2250 switch (master_config.start_config)
2251 {
2252 case LSM6DSO16IS_SH_TRG_XL_GY_DRDY:
2253 *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY;
2254 break;
2255
2256 case LSM6DSO16IS_SH_TRIG_INT2:
2257 *val = LSM6DSO16IS_SH_TRIG_INT2;
2258 break;
2259
2260 default:
2261 *val = LSM6DSO16IS_SH_TRG_XL_GY_DRDY;
2262 break;
2263 }
2264
2265 return ret;
2266 }
2267
2268 /**
2269 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
2270 *
2271 * @param ctx read / write interface definitions
2272 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2273 * @retval interface status (MANDATORY: return 0 -> no Error)
2274 *
2275 */
lsm6dso16is_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dso16is_sh_write_mode_t val)2276 int32_t lsm6dso16is_sh_write_mode_set(const stmdev_ctx_t *ctx,
2277 lsm6dso16is_sh_write_mode_t val)
2278 {
2279 lsm6dso16is_master_config_t master_config;
2280 int32_t ret;
2281
2282 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2283 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2284 if (ret != 0)
2285 {
2286 goto exit;
2287 }
2288
2289 master_config.write_once = (uint8_t)val & 0x01U;
2290 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2291
2292 exit:
2293 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2294
2295 return ret;
2296 }
2297
2298 /**
2299 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
2300 *
2301 * @param ctx read / write interface definitions
2302 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
2303 * @retval interface status (MANDATORY: return 0 -> no Error)
2304 *
2305 */
lsm6dso16is_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dso16is_sh_write_mode_t * val)2306 int32_t lsm6dso16is_sh_write_mode_get(const stmdev_ctx_t *ctx,
2307 lsm6dso16is_sh_write_mode_t *val)
2308 {
2309 lsm6dso16is_master_config_t master_config;
2310 int32_t ret;
2311
2312 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2313 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2314 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2315 if (ret != 0)
2316 {
2317 return ret;
2318 }
2319
2320 switch (master_config.write_once)
2321 {
2322 case LSM6DSO16IS_EACH_SH_CYCLE:
2323 *val = LSM6DSO16IS_EACH_SH_CYCLE;
2324 break;
2325
2326 case LSM6DSO16IS_ONLY_FIRST_CYCLE:
2327 *val = LSM6DSO16IS_ONLY_FIRST_CYCLE;
2328 break;
2329
2330 default:
2331 *val = LSM6DSO16IS_EACH_SH_CYCLE;
2332 break;
2333 }
2334
2335 return ret;
2336 }
2337
2338 /**
2339 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
2340 *
2341 * @param ctx read / write interface definitions
2342 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2343 * @retval interface status (MANDATORY: return 0 -> no Error)
2344 *
2345 */
lsm6dso16is_sh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2346 int32_t lsm6dso16is_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2347 {
2348 lsm6dso16is_master_config_t master_config;
2349 int32_t ret;
2350
2351 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2352 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2353 if (ret != 0)
2354 {
2355 goto exit;
2356 }
2357
2358 master_config.rst_master_regs = val;
2359 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2360
2361 exit:
2362 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2363
2364 return ret;
2365 }
2366
2367 /**
2368 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
2369 *
2370 * @param ctx read / write interface definitions
2371 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
2372 * @retval interface status (MANDATORY: return 0 -> no Error)
2373 *
2374 */
lsm6dso16is_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2375 int32_t lsm6dso16is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2376 {
2377 lsm6dso16is_master_config_t master_config;
2378 int32_t ret;
2379
2380 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2381 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1);
2382 if (ret != 0)
2383 {
2384 return ret;
2385 }
2386
2387 *val = master_config.rst_master_regs;
2388
2389 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2390
2391 return ret;
2392 }
2393
2394 /**
2395 * @brief Configure slave 0 for perform a write.[set]
2396 *
2397 * @param ctx read / write interface definitions
2398 * @param val a structure that contain
2399 * - uint8_t slv1_add; 8 bit i2c device address
2400 * - uint8_t slv1_subadd; 8 bit register device address
2401 * - uint8_t slv1_data; 8 bit data to write
2402 * @retval interface status (MANDATORY: return 0 -> no Error)
2403 *
2404 */
lsm6dso16is_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dso16is_sh_cfg_write_t * val)2405 int32_t lsm6dso16is_sh_cfg_write(const stmdev_ctx_t *ctx,
2406 lsm6dso16is_sh_cfg_write_t *val)
2407 {
2408 lsm6dso16is_slv0_add_t reg;
2409 int32_t ret;
2410
2411 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2412 if (ret != 0)
2413 {
2414 return ret;
2415 }
2416
2417 reg.slave0_add = val->slv0_add;
2418 reg.rw_0 = 0;
2419 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)®, 1);
2420 if (ret != 0)
2421 {
2422 goto exit;
2423 }
2424
2425 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD,
2426 &(val->slv0_subadd), 1);
2427 if (ret != 0)
2428 {
2429 goto exit;
2430 }
2431
2432 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DATAWRITE_SLV0,
2433 &(val->slv0_data), 1);
2434
2435 exit:
2436 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2437
2438 return ret;
2439 }
2440
2441 /**
2442 * @brief Rate at which the master communicates.[set]
2443 *
2444 * @param ctx read / write interface definitions
2445 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2446 * @retval interface status (MANDATORY: return 0 -> no Error)
2447 *
2448 */
lsm6dso16is_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso16is_sh_data_rate_t val)2449 int32_t lsm6dso16is_sh_data_rate_set(const stmdev_ctx_t *ctx,
2450 lsm6dso16is_sh_data_rate_t val)
2451 {
2452 lsm6dso16is_slv0_config_t slv0_config;
2453 int32_t ret;
2454
2455 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2456 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2457 if (ret != 0)
2458 {
2459 goto exit;
2460 }
2461
2462 slv0_config.shub_odr = (uint8_t)val & 0x07U;
2463 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2464
2465 exit:
2466 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2467
2468 return ret;
2469 }
2470
2471 /**
2472 * @brief Rate at which the master communicates.[get]
2473 *
2474 * @param ctx read / write interface definitions
2475 * @param val SH_12_5Hz, SH_26Hz, SH_52Hz, SH_104Hz
2476 * @retval interface status (MANDATORY: return 0 -> no Error)
2477 *
2478 */
lsm6dso16is_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso16is_sh_data_rate_t * val)2479 int32_t lsm6dso16is_sh_data_rate_get(const stmdev_ctx_t *ctx,
2480 lsm6dso16is_sh_data_rate_t *val)
2481 {
2482 lsm6dso16is_slv0_config_t slv0_config;
2483 int32_t ret;
2484
2485 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2486 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
2487 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2488 if (ret != 0)
2489 {
2490 return ret;
2491 }
2492
2493 switch (slv0_config.shub_odr)
2494 {
2495 case LSM6DSO16IS_SH_12_5Hz:
2496 *val = LSM6DSO16IS_SH_12_5Hz;
2497 break;
2498
2499 case LSM6DSO16IS_SH_26Hz:
2500 *val = LSM6DSO16IS_SH_26Hz;
2501 break;
2502
2503 case LSM6DSO16IS_SH_52Hz:
2504 *val = LSM6DSO16IS_SH_52Hz;
2505 break;
2506
2507 case LSM6DSO16IS_SH_104Hz:
2508 *val = LSM6DSO16IS_SH_104Hz;
2509 break;
2510
2511 default:
2512 *val = LSM6DSO16IS_SH_12_5Hz;
2513 break;
2514 }
2515
2516 return ret;
2517 }
2518
2519 /**
2520 * @brief Configure slave idx for perform a read.[set]
2521 *
2522 * @param ctx read / write interface definitions
2523 * @param val Structure that contain
2524 * - uint8_t slv_add; 8 bit i2c device address
2525 * - uint8_t slv_subadd; 8 bit register device address
2526 * - uint8_t slv_len; num of bit to read
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
lsm6dso16is_sh_slv_cfg_read(const stmdev_ctx_t * ctx,uint8_t idx,lsm6dso16is_sh_cfg_read_t * val)2530 int32_t lsm6dso16is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx,
2531 lsm6dso16is_sh_cfg_read_t *val)
2532 {
2533 lsm6dso16is_slv0_add_t slv_add;
2534 lsm6dso16is_slv0_config_t slv_config;
2535 int32_t ret;
2536
2537 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK);
2538 if (ret != 0)
2539 {
2540 return ret;
2541 }
2542
2543 slv_add.slave0_add = val->slv_add;
2544 slv_add.rw_0 = 1;
2545 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD + idx * 3U,
2546 (uint8_t *)&slv_add, 1);
2547 if (ret != 0)
2548 {
2549 goto exit;
2550 }
2551
2552 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD + idx * 3U,
2553 &(val->slv_subadd), 1);
2554 if (ret != 0)
2555 {
2556 goto exit;
2557 }
2558
2559 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx * 3U,
2560 (uint8_t *)&slv_config, 1);
2561 if (ret != 0)
2562 {
2563 goto exit;
2564 }
2565
2566 slv_config.slave0_numop = val->slv_len;
2567 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx * 3U,
2568 (uint8_t *)&slv_config, 1);
2569
2570 exit:
2571 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2572
2573 return ret;
2574 }
2575
2576 /**
2577 * @brief Sensor hub source register.[get]
2578 *
2579 * @param ctx read / write interface definitions
2580 * @param val union of registers from STATUS_MASTER to
2581 * @retval interface status (MANDATORY: return 0 -> no Error)
2582 *
2583 */
lsm6dso16is_sh_status_get(const stmdev_ctx_t * ctx,lsm6dso16is_status_master_t * val)2584 int32_t lsm6dso16is_sh_status_get(const stmdev_ctx_t *ctx,
2585 lsm6dso16is_status_master_t *val)
2586 {
2587 int32_t ret;
2588
2589 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
2590
2591 return ret;
2592 }
2593
2594 /**
2595 * @}
2596 *
2597 */
2598
2599 /**
2600 * @defgroup ispu
2601 * @brief ispu
2602 * @{/
2603 *
2604 */
2605 /**
2606 * @brief Software reset of ISPU core.[set]
2607 *
2608 * @param ctx read / write interface definitions
2609 * @param val Software reset of ISPU core.
2610 * @retval interface status (MANDATORY: return 0 -> no Error)
2611 *
2612 */
lsm6dso16is_ispu_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2613 int32_t lsm6dso16is_ispu_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2614 {
2615 lsm6dso16is_func_cfg_access_t func_cfg_access;
2616 int32_t ret;
2617
2618 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2619
2620 if (ret == 0)
2621 {
2622 func_cfg_access.sw_reset_ispu = val;
2623 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2624 }
2625
2626 return ret;
2627 }
2628
2629 /**
2630 * @brief Software reset of ISPU core.[get]
2631 *
2632 * @param ctx read / write interface definitions
2633 * @param val Software reset of ISPU core.
2634 * @retval interface status (MANDATORY: return 0 -> no Error)
2635 *
2636 */
lsm6dso16is_ispu_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2637 int32_t lsm6dso16is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2638 {
2639 lsm6dso16is_func_cfg_access_t func_cfg_access;
2640 int32_t ret;
2641
2642 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
2643
2644 *val = func_cfg_access.sw_reset_ispu;
2645
2646
2647 return ret;
2648 }
2649
lsm6dso16is_ispu_clock_set(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_clock_sel_t val)2650 int32_t lsm6dso16is_ispu_clock_set(const stmdev_ctx_t *ctx,
2651 lsm6dso16is_ispu_clock_sel_t val)
2652 {
2653 lsm6dso16is_ctrl10_c_t ctrl10_c;
2654 int32_t ret;
2655
2656 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2657
2658 if (ret == 0)
2659 {
2660 ctrl10_c.ispu_clk_sel = (uint8_t)val;
2661 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2662 }
2663
2664 return ret;
2665 }
2666
lsm6dso16is_ispu_clock_get(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_clock_sel_t * val)2667 int32_t lsm6dso16is_ispu_clock_get(const stmdev_ctx_t *ctx,
2668 lsm6dso16is_ispu_clock_sel_t *val)
2669 {
2670 lsm6dso16is_ctrl10_c_t ctrl10_c;
2671 int32_t ret;
2672
2673 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
2674
2675 switch (ctrl10_c.ispu_clk_sel)
2676 {
2677 default:
2678 case 0:
2679 *val = LSM6DSO16IS_ISPU_CLK_5MHz;
2680 break;
2681 case 1:
2682 *val = LSM6DSO16IS_ISPU_CLK_10MHz;
2683 break;
2684 }
2685
2686 return ret;
2687 }
2688
2689 /**
2690 * @brief ISPU irq rate selection.[set]
2691 *
2692 * @param ctx read / write interface definitions
2693 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2694 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2695 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2696 * @retval interface status (MANDATORY: return 0 -> no Error)
2697 *
2698 */
lsm6dso16is_ispu_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_data_rate_t val)2699 int32_t lsm6dso16is_ispu_data_rate_set(const stmdev_ctx_t *ctx,
2700 lsm6dso16is_ispu_data_rate_t val)
2701 {
2702 lsm6dso16is_ctrl9_c_t ctrl9_c;
2703 int32_t ret;
2704
2705 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2706
2707 if (ret == 0)
2708 {
2709 ctrl9_c.ispu_rate = ((uint8_t)val & 0xfU);
2710 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2711 }
2712
2713 return ret;
2714 }
2715
2716 /**
2717 * @brief ISPU irq rate selection.[get]
2718 *
2719 * @param ctx read / write interface definitions
2720 * @param val ISPU_ODR_OFF, ISPU_ODR_AT_12Hz5, ISPU_ODR_AT_26Hz, ISPU_ODR_AT_52Hz,
2721 * ISPU_ODR_AT_104Hz, ISPU_ODR_AT_208Hz, ISPU_ODR_AT_417Hz, ISPU_ODR_AT_833Hz,
2722 * ISPU_ODR_AT_1667Hz, ISPU_ODR_AT_3333Hz, ISPU_ODR_AT_6667Hz
2723 * @retval interface status (MANDATORY: return 0 -> no Error)
2724 *
2725 */
lsm6dso16is_ispu_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_data_rate_t * val)2726 int32_t lsm6dso16is_ispu_data_rate_get(const stmdev_ctx_t *ctx,
2727 lsm6dso16is_ispu_data_rate_t *val)
2728 {
2729 lsm6dso16is_ctrl9_c_t ctrl9_c;
2730 int32_t ret;
2731
2732 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2733
2734 switch ((ctrl9_c.ispu_rate))
2735 {
2736 case LSM6DSO16IS_ISPU_ODR_OFF:
2737 *val = LSM6DSO16IS_ISPU_ODR_OFF;
2738 break;
2739
2740 case LSM6DSO16IS_ISPU_ODR_AT_12Hz5:
2741 *val = LSM6DSO16IS_ISPU_ODR_AT_12Hz5;
2742 break;
2743
2744 case LSM6DSO16IS_ISPU_ODR_AT_26Hz:
2745 *val = LSM6DSO16IS_ISPU_ODR_AT_26Hz;
2746 break;
2747
2748 case LSM6DSO16IS_ISPU_ODR_AT_52Hz:
2749 *val = LSM6DSO16IS_ISPU_ODR_AT_52Hz;
2750 break;
2751
2752 case LSM6DSO16IS_ISPU_ODR_AT_104Hz:
2753 *val = LSM6DSO16IS_ISPU_ODR_AT_104Hz;
2754 break;
2755
2756 case LSM6DSO16IS_ISPU_ODR_AT_208Hz:
2757 *val = LSM6DSO16IS_ISPU_ODR_AT_208Hz;
2758 break;
2759
2760 case LSM6DSO16IS_ISPU_ODR_AT_416Hz:
2761 *val = LSM6DSO16IS_ISPU_ODR_AT_416Hz;
2762 break;
2763
2764 case LSM6DSO16IS_ISPU_ODR_AT_833Hz:
2765 *val = LSM6DSO16IS_ISPU_ODR_AT_833Hz;
2766 break;
2767
2768 case LSM6DSO16IS_ISPU_ODR_AT_1667Hz:
2769 *val = LSM6DSO16IS_ISPU_ODR_AT_1667Hz;
2770 break;
2771
2772 case LSM6DSO16IS_ISPU_ODR_AT_3333Hz:
2773 *val = LSM6DSO16IS_ISPU_ODR_AT_3333Hz;
2774 break;
2775
2776 case LSM6DSO16IS_ISPU_ODR_AT_6667Hz:
2777 *val = LSM6DSO16IS_ISPU_ODR_AT_6667Hz;
2778 break;
2779
2780 default:
2781 *val = LSM6DSO16IS_ISPU_ODR_OFF;
2782 break;
2783 }
2784 return ret;
2785 }
2786
2787 /**
2788 * @brief ISPU bdu selection.[set]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
lsm6dso16is_ispu_bdu_set(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_bdu_t val)2795 int32_t lsm6dso16is_ispu_bdu_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val)
2796 {
2797 lsm6dso16is_ctrl9_c_t ctrl9_c;
2798 int32_t ret;
2799
2800 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2801
2802 if (ret == 0)
2803 {
2804 ctrl9_c.ispu_bdu = ((uint8_t)val & 0x3U);
2805 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2806 }
2807
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief ISPU bdu selection.[get]
2813 *
2814 * @param ctx read / write interface definitions
2815 * @param val ISPU_BDU_OFF, ISPU_BDU_ON_2B_4B, ISPU_BDU_ON_2B_2B, ISPU_BDU_ON_4B_4B,
2816 * @retval interface status (MANDATORY: return 0 -> no Error)
2817 *
2818 */
lsm6dso16is_ispu_bdu_get(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_bdu_t * val)2819 int32_t lsm6dso16is_ispu_bdu_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val)
2820 {
2821 lsm6dso16is_ctrl9_c_t ctrl9_c;
2822 int32_t ret;
2823
2824 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL9_C, (uint8_t *)&ctrl9_c, 1);
2825
2826 switch ((ctrl9_c.ispu_rate))
2827 {
2828 case LSM6DSO16IS_ISPU_BDU_OFF:
2829 *val = LSM6DSO16IS_ISPU_BDU_OFF;
2830 break;
2831
2832 case LSM6DSO16IS_ISPU_BDU_ON_2B_4B:
2833 *val = LSM6DSO16IS_ISPU_BDU_ON_2B_4B;
2834 break;
2835
2836 case LSM6DSO16IS_ISPU_BDU_ON_2B_2B:
2837 *val = LSM6DSO16IS_ISPU_BDU_ON_2B_2B;
2838 break;
2839
2840 case LSM6DSO16IS_ISPU_BDU_ON_4B_4B:
2841 *val = LSM6DSO16IS_ISPU_BDU_ON_4B_4B;
2842 break;
2843
2844 default:
2845 *val = LSM6DSO16IS_ISPU_BDU_OFF;
2846 break;
2847 }
2848 return ret;
2849 }
2850
2851 /**
2852 * @brief Generic Interrupt Flags from ISPU.[get]
2853 *
2854 * @param ctx read / write interface definitions
2855 * @param val Generic Interrupt Flags from ISPU.
2856 * @retval interface status (MANDATORY: return 0 -> no Error)
2857 *
2858 */
lsm6dso16is_ia_ispu_get(const stmdev_ctx_t * ctx,uint32_t * val)2859 int32_t lsm6dso16is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val)
2860 {
2861 uint8_t buff[4];
2862 int32_t ret;
2863
2864 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, &buff[0], 4);
2865
2866 *val = (uint32_t)buff[3];
2867 *val = (*val * 256U) + (uint32_t)buff[2];
2868 *val = (*val * 256U) + (uint32_t)buff[1];
2869 *val = (*val * 256U) + (uint32_t)buff[0];
2870
2871 return ret;
2872 }
2873
2874 /**
2875 * @brief General purpose input configuration register for ISPU[set]
2876 *
2877 * @param ctx read / write interface definitions
2878 * @param offset offset from ISPU_DUMMY_CFG_1 register
2879 * @param val General purpose input configuration register for ISPU
2880 * @param len number of bytes to write
2881 * @retval interface status (MANDATORY: return 0 -> no Error)
2882 *
2883 */
lsm6dso16is_ispu_write_dummy_cfg(const stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)2884 int32_t lsm6dso16is_ispu_write_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset,
2885 uint8_t *val, uint8_t len)
2886 {
2887 int32_t ret;
2888
2889 /* check if we are writing outside of the range */
2890 if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len > LSM6DSO16IS_ISPU_DUMMY_CFG_4_H)
2891 {
2892 return -1;
2893 }
2894
2895 ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
2896
2897 return ret;
2898 }
2899
2900 /**
2901 * @brief General purpose input configuration register for ISPU[set]
2902 *
2903 * @param ctx read / write interface definitions
2904 * @param offset offset from ISPU_DUMMY_CFG_1 register
2905 * @param val General purpose input configuration register for ISPU
2906 * @param len number of bytes to write
2907 * @retval interface status (MANDATORY: return 0 -> no Error)
2908 *
2909 */
lsm6dso16is_ispu_read_dummy_cfg(const stmdev_ctx_t * ctx,uint8_t offset,uint8_t * val,uint8_t len)2910 int32_t lsm6dso16is_ispu_read_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset,
2911 uint8_t *val, uint8_t len)
2912 {
2913 int32_t ret;
2914
2915 /* check if we are reading outside of the range */
2916 if (LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset + len > LSM6DSO16IS_ISPU_DUMMY_CFG_4_H)
2917 {
2918 return -1;
2919 }
2920
2921 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DUMMY_CFG_1_L + offset, val, len);
2922
2923 return ret;
2924 }
2925
2926 /**
2927 * @brief Boot ISPU core[set]
2928 *
2929 * @param ctx read / write interface definitions
2930 * @param val Boot ISPU core
2931 * @retval interface status (MANDATORY: return 0 -> no Error)
2932 *
2933 */
lsm6dso16is_ispu_boot_set(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_latched_t val)2934 int32_t lsm6dso16is_ispu_boot_set(const stmdev_ctx_t *ctx,
2935 lsm6dso16is_ispu_boot_latched_t val)
2936 {
2937 lsm6dso16is_ispu_config_t ispu_config;
2938 int32_t ret;
2939
2940 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
2941 if (ret != 0)
2942 {
2943 return ret;
2944 }
2945
2946 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2947 if (ret != 0)
2948 {
2949 goto exit;
2950 }
2951
2952 ispu_config.ispu_rst_n = (uint8_t)val;
2953 ispu_config.clk_dis = (uint8_t)val;
2954 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2955
2956 exit:
2957 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2958
2959 return ret;
2960 }
2961
2962 /**
2963 * @brief Boot ISPU core[get]
2964 *
2965 * @param ctx read / write interface definitions
2966 * @param val Boot ISPU core
2967 * @retval interface status (MANDATORY: return 0 -> no Error)
2968 *
2969 */
lsm6dso16is_ispu_boot_get(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_latched_t * val)2970 int32_t lsm6dso16is_ispu_boot_get(const stmdev_ctx_t *ctx,
2971 lsm6dso16is_ispu_boot_latched_t *val)
2972 {
2973 lsm6dso16is_ispu_config_t ispu_config;
2974 int32_t ret;
2975
2976 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
2977 if (ret != 0)
2978 {
2979 return ret;
2980 }
2981
2982 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
2983 if (ret != 0)
2984 {
2985 goto exit;
2986 }
2987
2988 *val = LSM6DSO16IS_ISPU_TURN_OFF;
2989 if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U)
2990 {
2991 *val = LSM6DSO16IS_ISPU_TURN_ON;
2992 }
2993
2994 exit:
2995 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
2996
2997 return ret;
2998 }
2999
3000 /**
3001 * @brief Enables latched ISPU interrupt.[set]
3002 *
3003 * @param ctx read / write interface definitions
3004 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
3005 * @retval interface status (MANDATORY: return 0 -> no Error)
3006 *
3007 */
lsm6dso16is_ispu_int_latched_set(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_int_latched_t val)3008 int32_t lsm6dso16is_ispu_int_latched_set(const stmdev_ctx_t *ctx,
3009 lsm6dso16is_ispu_int_latched_t val)
3010 {
3011 lsm6dso16is_ispu_config_t ispu_config;
3012 int32_t ret;
3013
3014 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3015 if (ret != 0)
3016 {
3017 return ret;
3018 }
3019
3020 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
3021 if (ret != 0)
3022 {
3023 goto exit;
3024 }
3025
3026 ispu_config.latched = ((uint8_t)val & 0x1U);
3027 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
3028
3029 exit:
3030 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3031
3032 return ret;
3033 }
3034
3035 /**
3036 * @brief Enables latched ISPU interrupt.[get]
3037 *
3038 * @param ctx read / write interface definitions
3039 * @param val ISPU_INT_PULSED, ISPU_INT_LATCHED,
3040 * @retval interface status (MANDATORY: return 0 -> no Error)
3041 *
3042 */
lsm6dso16is_ispu_int_latched_get(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_int_latched_t * val)3043 int32_t lsm6dso16is_ispu_int_latched_get(const stmdev_ctx_t *ctx,
3044 lsm6dso16is_ispu_int_latched_t *val)
3045 {
3046 lsm6dso16is_ispu_config_t ispu_config;
3047 int32_t ret;
3048
3049 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3050 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1);
3051 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3052 if (ret != 0)
3053 {
3054 return ret;
3055 }
3056
3057 switch ((ispu_config.latched))
3058 {
3059 case LSM6DSO16IS_ISPU_INT_PULSED:
3060 *val = LSM6DSO16IS_ISPU_INT_PULSED;
3061 break;
3062
3063 case LSM6DSO16IS_ISPU_INT_LATCHED:
3064 *val = LSM6DSO16IS_ISPU_INT_LATCHED;
3065 break;
3066
3067 default:
3068 *val = LSM6DSO16IS_ISPU_INT_PULSED;
3069 break;
3070 }
3071
3072 return ret;
3073 }
3074
3075 /**
3076 * @brief returns ISPU boot status
3077 *
3078 * @param ctx read / write interface definitions
3079 * @param val LSM6DSO16IS_ISPU_BOOT_IN_PROGRESS, LSM6DSO16IS_ISPU_BOOT_ENDED
3080 * @retval interface status (MANDATORY: return 0 -> no Error)
3081 *
3082 */
lsm6dso16is_ispu_get_boot_status(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_boot_end_t * val)3083 int32_t lsm6dso16is_ispu_get_boot_status(const stmdev_ctx_t *ctx,
3084 lsm6dso16is_ispu_boot_end_t *val)
3085 {
3086 lsm6dso16is_ispu_status_t ispu_boot_status;
3087 int32_t ret;
3088
3089 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3090 if (ret != 0)
3091 {
3092 return ret;
3093 }
3094
3095 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1);
3096 *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end;
3097 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3098
3099 return ret;
3100 }
3101
lsm6dso16is_ispu_sel_memory_addr(const stmdev_ctx_t * ctx,uint16_t mem_addr)3102 static int32_t lsm6dso16is_ispu_sel_memory_addr(const stmdev_ctx_t *ctx, uint16_t mem_addr)
3103 {
3104 uint8_t mem_addr_l, mem_addr_h;
3105 int32_t ret = 0;
3106
3107 mem_addr_l = (uint8_t)(mem_addr & 0xFFU);
3108 mem_addr_h = (uint8_t)(mem_addr / 256U);
3109 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR1,
3110 (uint8_t *)&mem_addr_h, 1);
3111 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR0,
3112 (uint8_t *)&mem_addr_l, 1);
3113
3114 return ret;
3115 }
3116
3117 /**
3118 * @brief ISPU write memory. ISPU clock is disabled inside the routine.
3119 *
3120 * @param ctx read / write interface definitions
3121 * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY
3122 * @param mem_addr memory address
3123 * @param mem_data memory data
3124 * @param len data length
3125 * @retval interface status (MANDATORY: return 0 -> no Error)
3126 *
3127 */
lsm6dso16is_ispu_write_memory(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3128 int32_t lsm6dso16is_ispu_write_memory(const stmdev_ctx_t *ctx,
3129 lsm6dso16is_ispu_memory_type_t mem_sel,
3130 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3131 {
3132 lsm6dso16is_ispu_mem_sel_t ispu_mem_sel;
3133 lsm6dso16is_ispu_config_t ispu_cfg;
3134 uint8_t clk_dis;
3135 int32_t ret;
3136 uint16_t i;
3137
3138 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3139 if (ret == 0)
3140 {
3141 /* disable ISPU clock */
3142 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3143 clk_dis = ispu_cfg.clk_dis;
3144 ispu_cfg.clk_dis = 1;
3145 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3146
3147 /* select memory to be written */
3148 ispu_mem_sel.read_mem_en = 0;
3149 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3150 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3151
3152 if (mem_sel == LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY)
3153 {
3154 uint16_t addr_s[4] = {(uint16_t)0, (uint16_t)0, (uint16_t)0, (uint16_t)0};
3155 uint16_t len_s[4] = {(uint16_t)0, (uint16_t)0, (uint16_t)0, (uint16_t)0};
3156 uint8_t j = 0;
3157 uint16_t k;
3158
3159 addr_s[0] = mem_addr;
3160 k = 0U;
3161 for (i = 0U; i < len; i++)
3162 {
3163 if ((mem_addr + i == 0x2000U) || (mem_addr + i == 0x4000U) || (mem_addr + i == 0x6000U))
3164 {
3165 len_s[j++] = k;
3166 addr_s[j] = mem_addr + i;
3167 k = 0U;
3168 }
3169
3170 k++;
3171 }
3172 len_s[j++] = k;
3173
3174 k = 0U;
3175 for (i = 0U; i < j; i++)
3176 {
3177 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, addr_s[i]);
3178 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]);
3179 k += len_s[i];
3180 }
3181 }
3182 else
3183 {
3184 /* select memory address */
3185 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr);
3186 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len);
3187 }
3188
3189 /* set ISPU clock back to previous value */
3190 ispu_cfg.clk_dis = clk_dis;
3191 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3192 }
3193
3194 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3195
3196 return ret;
3197 }
3198
3199 /**
3200 * @brief ISPU read memory. ISPU clock is disabled inside the routine.
3201 *
3202 * @param ctx read / write interface definitions
3203 * @param mem_sel LSM6DSO16IS_ISPU_DATA_RAM_MEMORY, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY
3204 * @param mem_addr memory address
3205 * @param mem_data memory data
3206 * @param len data length
3207 * @retval interface status (MANDATORY: return 0 -> no Error)
3208 *
3209 */
lsm6dso16is_ispu_read_memory(const stmdev_ctx_t * ctx,lsm6dso16is_ispu_memory_type_t mem_sel,uint16_t mem_addr,uint8_t * mem_data,uint16_t len)3210 int32_t lsm6dso16is_ispu_read_memory(const stmdev_ctx_t *ctx,
3211 lsm6dso16is_ispu_memory_type_t mem_sel,
3212 uint16_t mem_addr, uint8_t *mem_data, uint16_t len)
3213 {
3214 lsm6dso16is_ispu_mem_sel_t ispu_mem_sel;
3215 lsm6dso16is_ispu_config_t ispu_cfg;
3216 uint8_t clk_dis;
3217 int32_t ret;
3218 uint8_t dummy;
3219
3220 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3221 if (ret == 0)
3222 {
3223 /* disable ISPU clock */
3224 ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3225 clk_dis = ispu_cfg.clk_dis;
3226 ispu_cfg.clk_dis = 1;
3227 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3228
3229 /* select memory to be read */
3230 ispu_mem_sel.read_mem_en = 1;
3231 ispu_mem_sel.mem_sel = (uint8_t)mem_sel;
3232 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_SEL, (uint8_t *)&ispu_mem_sel, 1);
3233
3234 /* select memory address */
3235 ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr);
3236
3237 /* read data */
3238 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &dummy, 1);
3239 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len);
3240
3241 /* set ISPU clock back to previous value */
3242 ispu_cfg.clk_dis = clk_dis;
3243 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_cfg, 1);
3244 }
3245
3246 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3247
3248 return ret;
3249 }
3250
3251 /**
3252 * @brief ISPU write flags (IF2S)
3253 *
3254 * @param ctx read / write interface definitions
3255 * @param data ISPU flags
3256 * @retval interface status (MANDATORY: return 0 -> no Error)
3257 *
3258 */
lsm6dso16is_ispu_write_flags(const stmdev_ctx_t * ctx,uint16_t data)3259 int32_t lsm6dso16is_ispu_write_flags(const stmdev_ctx_t *ctx, uint16_t data)
3260 {
3261 lsm6dso16is_ispu_if2s_flag_l_t flag_l;
3262 lsm6dso16is_ispu_if2s_flag_h_t flag_h;
3263 int32_t ret;
3264
3265 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3266 if (ret == 0)
3267 {
3268 /* write the flags */
3269 flag_h.if2s = (uint8_t)(data / 256U);
3270 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_H, (uint8_t *)&flag_h,
3271 1);
3272 flag_l.if2s = (uint8_t)(data & 0xffU);
3273 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_IF2S_FLAG_L, (uint8_t *)&flag_l,
3274 1);
3275 }
3276
3277 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3278
3279 return ret;
3280 }
3281
3282 /**
3283 * @brief ISPU read flags (S2IF)
3284 *
3285 * @param ctx read / write interface definitions
3286 * @param data ISPU flags
3287 * @retval interface status (MANDATORY: return 0 -> no Error)
3288 *
3289 */
lsm6dso16is_ispu_read_flags(const stmdev_ctx_t * ctx,uint16_t * data)3290 int32_t lsm6dso16is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data)
3291 {
3292 uint8_t buff[2];
3293 int32_t ret;
3294
3295 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3296 if (ret == 0)
3297 {
3298 /* read the flags */
3299 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_L, buff, 2);
3300 data[0] = (uint16_t)buff[1];
3301 data[0] = (data[0] * 256U) + (uint16_t)buff[0];
3302 }
3303
3304 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3305
3306 return ret;
3307 }
3308
3309 /**
3310 * @brief ISPU clear flags (S2IF)
3311 *
3312 * @param ctx read / write interface definitions
3313 * @retval interface status (MANDATORY: return 0 -> no Error)
3314 *
3315 */
lsm6dso16is_ispu_clear_flags(const stmdev_ctx_t * ctx)3316 int32_t lsm6dso16is_ispu_clear_flags(const stmdev_ctx_t *ctx)
3317 {
3318 uint8_t data = 1;
3319 int32_t ret;
3320
3321 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3322
3323 if (ret == 0)
3324 {
3325 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_S2IF_FLAG_H, &data, 1);
3326 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3327 }
3328
3329 return ret;
3330 }
3331
3332 /**
3333 * @brief ISPU DOUT registers.[get]
3334 *
3335 * @param ctx read / write interface definitions
3336 * @param val ISPU DOUT output registers.
3337 * @retval interface status (MANDATORY: return 0 -> no Error)
3338 *
3339 */
lsm6dso16is_ispu_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)3340 int32_t lsm6dso16is_ispu_read_data_raw_get(const stmdev_ctx_t *ctx,
3341 uint8_t *val,
3342 uint8_t len)
3343 {
3344 int32_t ret;
3345
3346 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3347 if (ret == 0)
3348 {
3349 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_DOUT_00_L, (uint8_t *) val,
3350 len);
3351 }
3352
3353 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3354
3355 return ret;
3356 }
3357
3358 /**
3359 * @brief ISPU int1_ctrl.[get]
3360 *
3361 * @param ctx read / write interface definitions
3362 * @param val ISPU int1_ctrl register value
3363 * @retval interface status (MANDATORY: return 0 -> no Error)
3364 *
3365 */
lsm6dso16is_ispu_int1_ctrl_get(const stmdev_ctx_t * ctx,uint32_t * val)3366 int32_t lsm6dso16is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val)
3367 {
3368 uint8_t buff[4];
3369 int32_t ret;
3370
3371 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3372 if (ret == 0)
3373 {
3374 /* read int1_ctrl reg */
3375 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, &buff[0], 4);
3376
3377 *val = (uint32_t)buff[3];
3378 *val = (*val * 256U) + (uint32_t)buff[2];
3379 *val = (*val * 256U) + (uint32_t)buff[1];
3380 *val = (*val * 256U) + (uint32_t)buff[0];
3381 }
3382
3383 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3384
3385 return ret;
3386 }
3387
3388 /**
3389 * @brief ISPU int1_ctrl.[set]
3390 *
3391 * @param ctx read / write interface definitions
3392 * @param val ISPU int1_ctrl register value
3393 * @retval interface status (MANDATORY: return 0 -> no Error)
3394 *
3395 */
lsm6dso16is_ispu_int1_ctrl_set(const stmdev_ctx_t * ctx,uint32_t val)3396 int32_t lsm6dso16is_ispu_int1_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val)
3397 {
3398 lsm6dso16is_ispu_int1_ctrl0_t int1_ctrl0;
3399 lsm6dso16is_ispu_int1_ctrl1_t int1_ctrl1;
3400 lsm6dso16is_ispu_int1_ctrl2_t int1_ctrl2;
3401 lsm6dso16is_ispu_int1_ctrl3_t int1_ctrl3;
3402 int32_t ret;
3403
3404 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3405 if (ret == 0)
3406 {
3407 /* write the int1_ctrl reg */
3408 int1_ctrl3.ispu_int1_ctrl = (uint8_t)((val >> 24) & 0xffU);
3409 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL3, (uint8_t *)&int1_ctrl3,
3410 1);
3411
3412 int1_ctrl2.ispu_int1_ctrl = (uint8_t)((val >> 16) & 0xffU);
3413 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL2, (uint8_t *)&int1_ctrl2,
3414 1);
3415
3416 int1_ctrl1.ispu_int1_ctrl = (uint8_t)((val >> 8) & 0xffU);
3417 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL1, (uint8_t *)&int1_ctrl1,
3418 1);
3419
3420 int1_ctrl0.ispu_int1_ctrl = (uint8_t)(val & 0xffU);
3421 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT1_CTRL0, (uint8_t *)&int1_ctrl0,
3422 1);
3423 }
3424
3425 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3426
3427 return ret;
3428 }
3429
3430 /**
3431 * @brief ISPU int2_ctrl.[get]
3432 *
3433 * @param ctx read / write interface definitions
3434 * @param val ISPU int2_ctrl register value
3435 * @retval interface status (MANDATORY: return 0 -> no Error)
3436 *
3437 */
lsm6dso16is_ispu_int2_ctrl_get(const stmdev_ctx_t * ctx,uint32_t * val)3438 int32_t lsm6dso16is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val)
3439 {
3440 uint8_t buff[4];
3441 int32_t ret;
3442
3443 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3444 if (ret == 0)
3445 {
3446 /* read int2_ctrl reg */
3447 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, &buff[0], 4);
3448
3449 *val = (uint32_t)buff[3];
3450 *val = (*val * 256U) + (uint32_t)buff[2];
3451 *val = (*val * 256U) + (uint32_t)buff[1];
3452 *val = (*val * 256U) + (uint32_t)buff[0];
3453 }
3454
3455 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3456
3457 return ret;
3458 }
3459
3460 /**
3461 * @brief ISPU int2_ctrl.[set]
3462 *
3463 * @param ctx read / write interface definitions
3464 * @param val ISPU int2_ctrl register value
3465 * @retval interface status (MANDATORY: return 0 -> no Error)
3466 *
3467 */
lsm6dso16is_ispu_int2_ctrl_set(const stmdev_ctx_t * ctx,uint32_t val)3468 int32_t lsm6dso16is_ispu_int2_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val)
3469 {
3470 lsm6dso16is_ispu_int2_ctrl0_t int2_ctrl0;
3471 lsm6dso16is_ispu_int2_ctrl1_t int2_ctrl1;
3472 lsm6dso16is_ispu_int2_ctrl2_t int2_ctrl2;
3473 lsm6dso16is_ispu_int2_ctrl3_t int2_ctrl3;
3474 int32_t ret;
3475
3476 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3477 if (ret == 0)
3478 {
3479 /* write the int2_ctrl reg */
3480 int2_ctrl3.ispu_int2_ctrl = (uint8_t)((val >> 24) & 0xffU);
3481 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL3, (uint8_t *)&int2_ctrl3,
3482 1);
3483
3484 int2_ctrl2.ispu_int2_ctrl = (uint8_t)((val >> 16) & 0xffU);
3485 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL2, (uint8_t *)&int2_ctrl2,
3486 1);
3487
3488 int2_ctrl1.ispu_int2_ctrl = (uint8_t)((val >> 8) & 0xffU);
3489 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL1, (uint8_t *)&int2_ctrl1,
3490 1);
3491
3492 int2_ctrl0.ispu_int2_ctrl = (uint8_t)(val & 0xffU);
3493 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_INT2_CTRL0, (uint8_t *)&int2_ctrl0,
3494 1);
3495 }
3496
3497 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3498
3499 return ret;
3500 }
3501
3502 /**
3503 * @brief ISPU int_status.[get]
3504 *
3505 * @param ctx read / write interface definitions
3506 * @param val ISPU int2_status register value
3507 * @retval interface status (MANDATORY: return 0 -> no Error)
3508 *
3509 */
lsm6dso16is_ispu_int_status_get(const stmdev_ctx_t * ctx,uint32_t * val)3510 int32_t lsm6dso16is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val)
3511 {
3512 uint8_t buff[4];
3513 int32_t ret;
3514
3515 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3516 if (ret == 0)
3517 {
3518 /* read int2_ctrl reg */
3519 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0, &buff[0], 4);
3520
3521 *val = (uint32_t)buff[3];
3522 *val = (*val * 256U) + (uint32_t)buff[2];
3523 *val = (*val * 256U) + (uint32_t)buff[1];
3524 *val = (*val * 256U) + (uint32_t)buff[0];
3525 }
3526
3527 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3528
3529 return ret;
3530 }
3531
3532 /**
3533 * @brief ISPU algo.[get]
3534 *
3535 * @param ctx read / write interface definitions
3536 * @param val ISPU algo register value
3537 * @retval interface status (MANDATORY: return 0 -> no Error)
3538 *
3539 */
lsm6dso16is_ispu_algo_get(const stmdev_ctx_t * ctx,uint32_t * val)3540 int32_t lsm6dso16is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val)
3541 {
3542 uint8_t buff[4];
3543 int32_t ret;
3544
3545 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3546 if (ret == 0)
3547 {
3548 /* read int2_ctrl reg */
3549 ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, &buff[0], 4);
3550
3551 *val = (uint32_t)buff[3];
3552 *val = (*val * 256U) + (uint32_t)buff[2];
3553 *val = (*val * 256U) + (uint32_t)buff[1];
3554 *val = (*val * 256U) + (uint32_t)buff[0];
3555 }
3556
3557 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3558
3559 return ret;
3560 }
3561
3562 /**
3563 * @brief ISPU algo.[set]
3564 *
3565 * @param ctx read / write interface definitions
3566 * @param val ISPU algo register value
3567 * @retval interface status (MANDATORY: return 0 -> no Error)
3568 *
3569 */
lsm6dso16is_ispu_algo_set(const stmdev_ctx_t * ctx,uint32_t val)3570 int32_t lsm6dso16is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val)
3571 {
3572 lsm6dso16is_ispu_algo0_t algo0;
3573 lsm6dso16is_ispu_algo1_t algo1;
3574 lsm6dso16is_ispu_algo2_t algo2;
3575 lsm6dso16is_ispu_algo3_t algo3;
3576 int32_t ret;
3577
3578 ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK);
3579 if (ret == 0)
3580 {
3581 /* write the algo reg */
3582 algo3.ispu_algo = (uint8_t)((val >> 24) & 0xffU);
3583 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO3, (uint8_t *)&algo3, 1);
3584
3585 algo2.ispu_algo = (uint8_t)((val >> 16) & 0xffU);
3586 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO2, (uint8_t *)&algo2, 1);
3587
3588 algo1.ispu_algo = (uint8_t)((val >> 8) & 0xffU);
3589 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO1, (uint8_t *)&algo1, 1);
3590
3591 algo0.ispu_algo = (uint8_t)(val & 0xffU);
3592 ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_ALGO0, (uint8_t *)&algo0, 1);
3593 }
3594
3595 ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK);
3596
3597 return ret;
3598 }
3599
3600 /**
3601 * @}
3602 *
3603 */
3604
