1 /** 2 ****************************************************************************** 3 * @file lps22df_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lps22df_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LPS22DF_REGS_H 23 #define LPS22DF_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LPS22DF 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LPS22DF_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/ 172 #define LPS22DF_I2C_ADD_L 0xB9U 173 #define LPS22DF_I2C_ADD_H 0xBBU 174 175 /** Device Identification (Who am I) **/ 176 #define LPS22DF_ID 0xB4U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LPS22DF_INTERRUPT_CFG 0x0BU 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t phe : 1; 188 uint8_t ple : 1; 189 uint8_t lir : 1; 190 uint8_t not_used_01 : 1; 191 uint8_t reset_az : 1; 192 uint8_t autozero : 1; 193 uint8_t reset_arp : 1; 194 uint8_t autorefp : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t autorefp : 1; 197 uint8_t reset_arp : 1; 198 uint8_t autozero : 1; 199 uint8_t reset_az : 1; 200 uint8_t not_used_01 : 1; 201 uint8_t lir : 1; 202 uint8_t ple : 1; 203 uint8_t phe : 1; 204 #endif /* DRV_BYTE_ORDER */ 205 } lps22df_interrupt_cfg_t; 206 207 #define LPS22DF_THS_P_L 0x0CU 208 typedef struct 209 { 210 uint8_t ths : 8; 211 } lps22df_ths_p_l_t; 212 213 #define LPS22DF_THS_P_H 0x0DU 214 typedef struct 215 { 216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 217 uint8_t ths : 7; 218 uint8_t not_used_01 : 1; 219 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 220 uint8_t not_used_01 : 1; 221 uint8_t ths : 7; 222 #endif /* DRV_BYTE_ORDER */ 223 } lps22df_ths_p_h_t; 224 225 #define LPS22DF_IF_CTRL 0x0EU 226 typedef struct 227 { 228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 229 uint8_t not_used_01 : 1; 230 uint8_t cs_pu_dis : 1; 231 uint8_t int_pd_dis : 1; 232 uint8_t sdo_pu_en : 1; 233 uint8_t sda_pu_en : 1; 234 uint8_t sim : 1; 235 uint8_t i2c_i3c_dis : 1; 236 uint8_t int_en_i3c : 1; 237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 uint8_t int_en_i3c : 1; 239 uint8_t i2c_i3c_dis : 1; 240 uint8_t sim : 1; 241 uint8_t sda_pu_en : 1; 242 uint8_t sdo_pu_en : 1; 243 uint8_t int_pd_dis : 1; 244 uint8_t cs_pu_dis : 1; 245 uint8_t not_used_01 : 1; 246 #endif /* DRV_BYTE_ORDER */ 247 } lps22df_if_ctrl_t; 248 249 #define LPS22DF_WHO_AM_I 0x0FU 250 #define LPS22DF_CTRL_REG1 0x10U 251 typedef struct 252 { 253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 254 uint8_t avg : 3; 255 uint8_t odr : 4; 256 uint8_t not_used_01 : 1; 257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 258 uint8_t not_used_01 : 1; 259 uint8_t odr : 4; 260 uint8_t avg : 3; 261 #endif /* DRV_BYTE_ORDER */ 262 } lps22df_ctrl_reg1_t; 263 264 #define LPS22DF_CTRL_REG2 0x11U 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t oneshot : 1; 269 uint8_t not_used_01 : 1; 270 uint8_t swreset : 1; 271 uint8_t bdu : 1; 272 uint8_t en_lpfp : 1; 273 uint8_t lfpf_cfg : 1; 274 uint8_t not_used_02 : 1; 275 uint8_t boot : 1; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t boot : 1; 278 uint8_t not_used_02 : 1; 279 uint8_t lfpf_cfg : 1; 280 uint8_t en_lpfp : 1; 281 uint8_t bdu : 1; 282 uint8_t swreset : 1; 283 uint8_t not_used_01 : 1; 284 uint8_t oneshot : 1; 285 #endif /* DRV_BYTE_ORDER */ 286 } lps22df_ctrl_reg2_t; 287 288 #define LPS22DF_CTRL_REG3 0x12U 289 typedef struct 290 { 291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 292 uint8_t if_add_inc : 1; 293 uint8_t pp_od : 1; 294 uint8_t not_used_02 : 1; 295 uint8_t int_h_l : 1; 296 uint8_t not_used_01 : 4; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t not_used_01 : 4; 299 uint8_t int_h_l : 1; 300 uint8_t not_used_02 : 1; 301 uint8_t pp_od : 1; 302 uint8_t if_add_inc : 1; 303 #endif /* DRV_BYTE_ORDER */ 304 } lps22df_ctrl_reg3_t; 305 306 #define LPS22DF_CTRL_REG4 0x13U 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t int_f_ovr : 1; 311 uint8_t int_f_wtm : 1; 312 uint8_t int_f_full : 1; 313 uint8_t not_used_02 : 1; 314 uint8_t int_en : 1; 315 uint8_t drdy : 1; 316 uint8_t drdy_pls : 1; 317 uint8_t not_used_01 : 1; 318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 319 uint8_t not_used_01 : 1; 320 uint8_t drdy_pls : 1; 321 uint8_t drdy : 1; 322 uint8_t int_en : 1; 323 uint8_t not_used_02 : 1; 324 uint8_t int_f_full : 1; 325 uint8_t int_f_wtm : 1; 326 uint8_t int_f_ovr : 1; 327 #endif /* DRV_BYTE_ORDER */ 328 } lps22df_ctrl_reg4_t; 329 330 #define LPS22DF_FIFO_CTRL 0x14U 331 typedef struct 332 { 333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 334 uint8_t f_mode : 2; 335 uint8_t trig_modes : 1; 336 uint8_t stop_on_wtm : 1; 337 uint8_t not_used_01 : 4; 338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 339 uint8_t not_used_01 : 4; 340 uint8_t stop_on_wtm : 1; 341 uint8_t trig_modes : 1; 342 uint8_t f_mode : 2; 343 #endif /* DRV_BYTE_ORDER */ 344 } lps22df_fifo_ctrl_t; 345 346 #define LPS22DF_FIFO_WTM 0x15U 347 typedef struct 348 { 349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 350 uint8_t wtm : 7; 351 uint8_t not_used_01 : 1; 352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 353 uint8_t not_used_01 : 1; 354 uint8_t wtm : 7; 355 #endif /* DRV_BYTE_ORDER */ 356 } lps22df_fifo_wtm_t; 357 358 #define LPS22DF_REF_P_L 0x16U 359 typedef struct 360 { 361 uint8_t refp : 8; 362 } lps22df_ref_p_l_t; 363 364 #define LPS22DF_REF_P_H 0x17U 365 typedef struct 366 { 367 uint8_t refp : 8; 368 } lps22df_ref_p_h_t; 369 370 #define LPS22DF_I3C_IF_CTRL 0x19U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t i3c_bus_avb_sel : 2; 375 uint8_t not_used_02 : 3; 376 uint8_t asf_on : 1; 377 uint8_t not_used_01 : 2; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t not_used_01 : 2; 380 uint8_t asf_on : 1; 381 uint8_t not_used_02 : 3; 382 uint8_t i3c_bus_avb_sel : 2; 383 #endif /* DRV_BYTE_ORDER */ 384 } lps22df_i3c_if_ctrl_t; 385 386 #define LPS22DF_RPDS_L 0x1AU 387 #define LPS22DF_RPDS_H 0x1BU 388 #define LPS22DF_INT_SOURCE 0x24U 389 typedef struct 390 { 391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 392 uint8_t ph : 1; 393 uint8_t pl : 1; 394 uint8_t ia : 1; 395 uint8_t not_used_01 : 4; 396 uint8_t boot_on : 1; 397 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 398 uint8_t boot_on : 1; 399 uint8_t not_used_01 : 4; 400 uint8_t ia : 1; 401 uint8_t pl : 1; 402 uint8_t ph : 1; 403 #endif /* DRV_BYTE_ORDER */ 404 } lps22df_int_source_t; 405 406 #define LPS22DF_FIFO_STATUS1 0x25U 407 typedef struct 408 { 409 uint8_t fss : 8; 410 } lps22df_fifo_status1_t; 411 412 #define LPS22DF_FIFO_STATUS2 0x26U 413 typedef struct 414 { 415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 416 uint8_t not_used_01 : 5; 417 uint8_t fifo_full_ia : 1; 418 uint8_t fifo_ovr_ia : 1; 419 uint8_t fifo_wtm_ia : 1; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t fifo_wtm_ia : 1; 422 uint8_t fifo_ovr_ia : 1; 423 uint8_t fifo_full_ia : 1; 424 uint8_t not_used_01 : 5; 425 #endif /* DRV_BYTE_ORDER */ 426 } lps22df_fifo_status2_t; 427 428 #define LPS22DF_STATUS 0x27U 429 typedef struct 430 { 431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 432 uint8_t p_da : 1; 433 uint8_t t_da : 1; 434 uint8_t not_used_01 : 2; 435 uint8_t p_or : 1; 436 uint8_t t_or : 1; 437 uint8_t not_used_02 : 2; 438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 439 uint8_t not_used_02 : 2; 440 uint8_t t_or : 1; 441 uint8_t p_or : 1; 442 uint8_t not_used_01 : 2; 443 uint8_t t_da : 1; 444 uint8_t p_da : 1; 445 #endif /* DRV_BYTE_ORDER */ 446 } lps22df_status_t; 447 448 #define LPS22DF_PRESS_OUT_XL 0x28U 449 #define LPS22DF_PRESS_OUT_L 0x29U 450 #define LPS22DF_PRESS_OUT_H 0x2AU 451 #define LPS22DF_TEMP_OUT_L 0x2BU 452 #define LPS22DF_TEMP_OUT_H 0x2CU 453 #define LPS22DF_FIFO_DATA_OUT_PRESS_XL 0x78U 454 #define LPS22DF_FIFO_DATA_OUT_PRESS_L 0x79U 455 #define LPS22DF_FIFO_DATA_OUT_PRESS_H 0x7AU 456 457 /** 458 * @defgroup LPS22DF_Register_Union 459 * @brief This union group all the registers that has a bitfield 460 * description. 461 * This union is useful but not need by the driver. 462 * 463 * REMOVING this union you are compliant with: 464 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 465 * 466 * @{ 467 * 468 */ 469 470 typedef union 471 { 472 lps22df_interrupt_cfg_t interrupt_cfg; 473 lps22df_ths_p_l_t ths_p_l; 474 lps22df_ths_p_h_t ths_p_h; 475 lps22df_if_ctrl_t if_ctrl; 476 lps22df_ctrl_reg1_t ctrl_reg1; 477 lps22df_ctrl_reg2_t ctrl_reg2; 478 lps22df_ctrl_reg3_t ctrl_reg3; 479 lps22df_ctrl_reg4_t ctrl_reg4; 480 lps22df_fifo_ctrl_t fifo_ctrl; 481 lps22df_fifo_wtm_t fifo_wtm; 482 lps22df_ref_p_l_t ref_p_l; 483 lps22df_ref_p_h_t ref_p_h; 484 lps22df_i3c_if_ctrl_t i3c_if_ctrl; 485 lps22df_int_source_t int_source; 486 lps22df_fifo_status1_t fifo_status1; 487 lps22df_fifo_status2_t fifo_status2; 488 lps22df_status_t status; 489 bitwise_t bitwise; 490 uint8_t byte; 491 } lps22df_reg_t; 492 493 #ifndef __weak 494 #define __weak __attribute__((weak)) 495 #endif /* __weak */ 496 497 /* 498 * These are the basic platform dependent I/O routines to read 499 * and write device registers connected on a standard bus. 500 * The driver keeps offering a default implementation based on function 501 * pointers to read/write routines for backward compatibility. 502 * The __weak directive allows the final application to overwrite 503 * them with a custom implementation. 504 */ 505 506 int32_t lps22df_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 507 uint8_t *data, uint16_t len); 508 int32_t lps22df_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 509 uint8_t *data, uint16_t len); 510 511 extern float_t lps22df_from_lsb_to_hPa(int32_t lsb); 512 extern float_t lps22df_from_lsb_to_celsius(int16_t lsb); 513 514 typedef struct 515 { 516 uint8_t whoami; 517 } lps22df_id_t; 518 int32_t lps22df_id_get(const stmdev_ctx_t *ctx, lps22df_id_t *val); 519 520 typedef enum 521 { 522 LPS22DF_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 523 LPS22DF_SPI_4W = 0x02, /* Only SPI: SDO / SDI separated pins */ 524 LPS22DF_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ 525 LPS22DF_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ 526 } lps22df_interface_t; 527 528 typedef enum 529 { 530 LPS22DF_FILTER_AUTO = 0x00, /* Disable anti-spike filters */ 531 LPS22DF_FILTER_ALWAYS_ON = 0x01, /* Enable anti-spike filters */ 532 } lps22df_filter_t; 533 534 typedef enum 535 { 536 LPS22DF_IBI_50us = 0x0, 537 LPS22DF_IBI_2us = 0x1, 538 LPS22DF_IBI_1ms = 0x2, 539 LPS22DF_IBI_25ms = 0x3 540 } lps22df_i3c_ibi_time_t; 541 542 typedef struct 543 { 544 lps22df_interface_t interface; 545 lps22df_filter_t filter; 546 lps22df_i3c_ibi_time_t i3c_ibi_time; 547 } lps22df_bus_mode_t; 548 int32_t lps22df_bus_mode_set(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); 549 int32_t lps22df_bus_mode_get(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); 550 551 typedef enum 552 { 553 LPS22DF_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 554 LPS22DF_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 555 LPS22DF_RESET = 0x02, /* Reset configuration registers */ 556 } lps22df_init_t; 557 int32_t lps22df_init_set(const stmdev_ctx_t *ctx, lps22df_init_t val); 558 559 typedef struct 560 { 561 uint8_t sw_reset : 1; /* Restoring configuration registers. */ 562 uint8_t boot : 1; /* Restoring calibration parameters. */ 563 uint8_t drdy_pres : 1; /* Pressure data ready. */ 564 uint8_t drdy_temp : 1; /* Temperature data ready. */ 565 uint8_t ovr_pres : 1; /* Pressure data overrun. */ 566 uint8_t ovr_temp : 1; /* Temperature data overrun. */ 567 uint8_t end_meas : 1; /* Single measurement is finished. */ 568 uint8_t ref_done : 1; /* Auto-Zero value is set. */ 569 } lps22df_stat_t; 570 int32_t lps22df_status_get(const stmdev_ctx_t *ctx, lps22df_stat_t *val); 571 572 typedef struct 573 { 574 uint8_t int_push_pull : 1; /* 1 = push-pull / 0 = open-drain */ 575 uint8_t int_pull_down : 1; /* 1 = pull-down enabled */ 576 uint8_t sdo_pull_up : 1; /* 1 = pull-up enabled */ 577 uint8_t sda_pull_up : 1; /* 1 = pull-up enabled */ 578 uint8_t cs_pull_up : 1; /* 1 = pull-up enabled */ 579 } lps22df_pin_conf_t; 580 int32_t lps22df_pin_conf_set(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); 581 int32_t lps22df_pin_conf_get(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); 582 583 typedef struct 584 { 585 uint8_t drdy_pres : 1; /* Pressure data ready */ 586 uint8_t drdy_temp : 1; /* Temperature data ready */ 587 uint8_t over_pres : 1; /* Over pressure event */ 588 uint8_t under_pres : 1; /* Under pressure event */ 589 uint8_t thrsld_pres : 1; /* Over/Under pressure event */ 590 uint8_t fifo_full : 1; /* FIFO full */ 591 uint8_t fifo_ovr : 1; /* FIFO overrun */ 592 uint8_t fifo_th : 1; /* FIFO threshold reached */ 593 } lps22df_all_sources_t; 594 int32_t lps22df_all_sources_get(const stmdev_ctx_t *ctx, lps22df_all_sources_t *val); 595 596 typedef enum 597 { 598 LPS22DF_ONE_SHOT = 0x00, /* Device in power down till software trigger */ 599 LPS22DF_1Hz = 0x01, 600 LPS22DF_4Hz = 0x02, 601 LPS22DF_10Hz = 0x03, 602 LPS22DF_25Hz = 0x04, 603 LPS22DF_50Hz = 0x05, 604 LPS22DF_75Hz = 0x06, 605 LPS22DF_100Hz = 0x07, 606 LPS22DF_200Hz = 0x08, 607 } lps22df_odr_t; 608 609 typedef enum 610 { 611 LPS22DF_4_AVG = 0, 612 LPS22DF_8_AVG = 1, 613 LPS22DF_16_AVG = 2, 614 LPS22DF_32_AVG = 3, 615 LPS22DF_64_AVG = 4, 616 LPS22DF_128_AVG = 5, 617 LPS22DF_256_AVG = 6, 618 LPS22DF_512_AVG = 7, 619 } lps22df_avg_t; 620 621 typedef enum 622 { 623 LPS22DF_LPF_DISABLE = 0, 624 LPS22DF_LPF_ODR_DIV_4 = 1, 625 LPS22DF_LPF_ODR_DIV_9 = 3, 626 } lps22df_lpf_t; 627 628 typedef struct 629 { 630 lps22df_odr_t odr; 631 lps22df_avg_t avg; 632 lps22df_lpf_t lpf; 633 } lps22df_md_t; 634 int32_t lps22df_mode_set(const stmdev_ctx_t *ctx, lps22df_md_t *val); 635 int32_t lps22df_mode_get(const stmdev_ctx_t *ctx, lps22df_md_t *val); 636 637 int32_t lps22df_trigger_sw(const stmdev_ctx_t *ctx, lps22df_md_t *md); 638 639 typedef struct 640 { 641 struct 642 { 643 float_t hpa; 644 int32_t raw; /* 32 bit signed-left algned format left */ 645 } pressure; 646 struct 647 { 648 float_t deg_c; 649 int16_t raw; 650 } heat; 651 } lps22df_data_t; 652 int32_t lps22df_data_get(const stmdev_ctx_t *ctx, lps22df_data_t *data); 653 654 int32_t lps22df_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 655 int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 656 657 typedef enum 658 { 659 LPS22DF_BYPASS = 0, 660 LPS22DF_FIFO = 1, 661 LPS22DF_STREAM = 2, 662 LPS22DF_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ 663 LPS22DF_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ 664 LPS22DF_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ 665 } lps22df_operation_t; 666 667 typedef struct 668 { 669 lps22df_operation_t operation; 670 uint8_t watermark : 7; /* (0 disable) max 128.*/ 671 } lps22df_fifo_md_t; 672 int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); 673 int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); 674 675 int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 676 677 typedef struct 678 { 679 float_t hpa; 680 int32_t raw; 681 } lps22df_fifo_data_t; 682 int32_t lps22df_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data); 683 684 typedef struct 685 { 686 uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ 687 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 688 uint8_t drdy_latched : 1; /* pulsed ~5 μs with enabled drdy_pres " */ 689 } lps22df_int_mode_t; 690 int32_t lps22df_interrupt_mode_set(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val); 691 int32_t lps22df_interrupt_mode_get(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val); 692 693 typedef struct 694 { 695 uint8_t drdy_pres : 1; /* Pressure data ready */ 696 uint8_t fifo_th : 1; /* FIFO threshold reached */ 697 uint8_t fifo_ovr : 1; /* FIFO overrun */ 698 uint8_t fifo_full : 1; /* FIFO full */ 699 } lps22df_pin_int_route_t; 700 int32_t lps22df_pin_int_route_set(const stmdev_ctx_t *ctx, 701 lps22df_pin_int_route_t *val); 702 int32_t lps22df_pin_int_route_get(const stmdev_ctx_t *ctx, 703 lps22df_pin_int_route_t *val); 704 705 typedef struct 706 { 707 uint16_t threshold; /* Threshold in hPa * 16 */ 708 uint8_t over_th : 1; /* Pressure data over threshold event */ 709 uint8_t under_th : 1; /* Pressure data under threshold event */ 710 } lps22df_int_th_md_t; 711 int32_t lps22df_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 712 lps22df_int_th_md_t *val); 713 int32_t lps22df_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 714 lps22df_int_th_md_t *val); 715 716 typedef enum 717 { 718 LPS22DF_OUT_AND_INTERRUPT = 0, 719 LPS22DF_ONLY_INTERRUPT = 1, 720 LPS22DF_RST_REFS = 2, 721 } lps22df_apply_ref_t; 722 723 typedef struct 724 { 725 lps22df_apply_ref_t apply_ref; 726 uint8_t get_ref : 1; /* Use current pressure value as reference */ 727 } lps22df_ref_md_t; 728 int32_t lps22df_reference_mode_set(const stmdev_ctx_t *ctx, 729 lps22df_ref_md_t *val); 730 int32_t lps22df_reference_mode_get(const stmdev_ctx_t *ctx, 731 lps22df_ref_md_t *val); 732 733 int32_t lps22df_opc_set(const stmdev_ctx_t *ctx, int16_t val); 734 int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val); 735 736 /** 737 *@} 738 * 739 */ 740 741 #ifdef __cplusplus 742 } 743 #endif 744 745 #endif /* LPS22DF_REGS_H */ 746 747 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 748
