1 /**
2 ******************************************************************************
3 * @file lps22df_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LPS22DF driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lps22df_reg.h"
21
22 /**
23 * @defgroup LPS22DF
24 * @brief This file provides a set of functions needed to drive the
25 * lps22df nano pressure sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lps22df_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lps22df_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
lps22df_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak lps22df_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup Private_functions
96 * @brief Section collect all the utility functions needed by APIs.
97 * @{
98 *
99 */
100
bytecpy(uint8_t * target,uint8_t * source)101 static void bytecpy(uint8_t *target, uint8_t *source)
102 {
103 if ((target != NULL) && (source != NULL))
104 {
105 *target = *source;
106 }
107 }
108
109 /**
110 * @}
111 *
112 */
113
114 /**
115 * @defgroup Sensitivity
116 * @brief These functions convert raw-data into engineering units.
117 * @{
118 *
119 */
120
lps22df_from_lsb_to_hPa(int32_t lsb)121 float_t lps22df_from_lsb_to_hPa(int32_t lsb)
122 {
123 return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */
124 }
125
lps22df_from_lsb_to_celsius(int16_t lsb)126 float_t lps22df_from_lsb_to_celsius(int16_t lsb)
127 {
128 return ((float_t)lsb / 100.0f);
129 }
130
131 /**
132 * @}
133 *
134 */
135
136 /**
137 * @defgroup Basic functions
138 * @brief This section groups all the functions concerning device basic
139 * configuration.
140 * @{
141 *
142 */
143
144 /**
145 * @brief Device "Who am I".[get]
146 *
147 * @param ctx communication interface handler.(ptr)
148 * @param val ID values.(ptr)
149 * @retval interface status (MANDATORY: return 0 -> no Error)
150 *
151 */
lps22df_id_get(const stmdev_ctx_t * ctx,lps22df_id_t * val)152 int32_t lps22df_id_get(const stmdev_ctx_t *ctx, lps22df_id_t *val)
153 {
154 uint8_t reg;
155 int32_t ret;
156
157 ret = lps22df_read_reg(ctx, LPS22DF_WHO_AM_I, ®, 1);
158 val->whoami = reg;
159
160 return ret;
161 }
162
163 /**
164 * @brief Configures the bus operating mode.[set]
165 *
166 * @param ctx communication interface handler.(ptr)
167 * @param val configures the bus operating mode.(ptr)
168 * @retval interface status (MANDATORY: return 0 -> no Error)
169 *
170 */
lps22df_bus_mode_set(const stmdev_ctx_t * ctx,lps22df_bus_mode_t * val)171 int32_t lps22df_bus_mode_set(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val)
172 {
173 lps22df_i3c_if_ctrl_t i3c_if_ctrl;
174 lps22df_if_ctrl_t if_ctrl;
175 int32_t ret;
176
177 ret = lps22df_read_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
178 if (ret == 0)
179 {
180 if_ctrl.i2c_i3c_dis = ((uint8_t)val->interface & 0x02U) >> 1;
181 if_ctrl.int_en_i3c = ((uint8_t)val->interface & 0x04U) >> 2;
182 if_ctrl.sim = ((uint8_t)val->interface & 0x01U);
183 ret = lps22df_write_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
184 }
185 if (ret == 0)
186 {
187 ret = lps22df_read_reg(ctx, LPS22DF_I3C_IF_CTRL,
188 (uint8_t *)&i3c_if_ctrl, 1);
189 }
190 if (ret == 0)
191 {
192 i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U;
193 i3c_if_ctrl.i3c_bus_avb_sel = (uint8_t)val->i3c_ibi_time & 0x03U;
194 ret = lps22df_write_reg(ctx, LPS22DF_I3C_IF_CTRL,
195 (uint8_t *)&i3c_if_ctrl, 1);
196 }
197 return ret;
198 }
199
200 /**
201 * @brief Configures the bus operating mode.[set]
202 *
203 * @param ctx communication interface handler.(ptr)
204 * @param val configures the bus operating mode.(ptr)
205 * @retval interface status (MANDATORY: return 0 -> no Error)
206 *
207 */
lps22df_bus_mode_get(const stmdev_ctx_t * ctx,lps22df_bus_mode_t * val)208 int32_t lps22df_bus_mode_get(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val)
209 {
210 lps22df_i3c_if_ctrl_t i3c_if_ctrl;
211 lps22df_if_ctrl_t if_ctrl;
212 int32_t ret;
213
214 ret = lps22df_read_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
215 if (ret == 0)
216 {
217 ret = lps22df_read_reg(ctx, LPS22DF_I3C_IF_CTRL,
218 (uint8_t *)&i3c_if_ctrl, 1);
219
220 switch ((if_ctrl.int_en_i3c << 2) | (if_ctrl.i2c_i3c_dis << 1) |
221 if_ctrl.sim)
222 {
223 case LPS22DF_SEL_BY_HW:
224 val->interface = LPS22DF_SEL_BY_HW;
225 break;
226 case LPS22DF_SPI_3W:
227 val->interface = LPS22DF_SPI_3W;
228 break;
229 case LPS22DF_SPI_4W:
230 val->interface = LPS22DF_SPI_4W;
231 break;
232 case LPS22DF_INT_PIN_ON_I3C:
233 val->interface = LPS22DF_INT_PIN_ON_I3C;
234 break;
235 default:
236 val->interface = LPS22DF_SEL_BY_HW;
237 break;
238 }
239
240 switch (i3c_if_ctrl.asf_on)
241 {
242 case LPS22DF_FILTER_AUTO:
243 val->filter = LPS22DF_FILTER_AUTO;
244 break;
245 case LPS22DF_FILTER_ALWAYS_ON:
246 val->filter = LPS22DF_FILTER_ALWAYS_ON;
247 break;
248 default:
249 val->filter = LPS22DF_FILTER_AUTO;
250 break;
251 }
252
253 switch (i3c_if_ctrl.i3c_bus_avb_sel)
254 {
255 case LPS22DF_IBI_50us:
256 val->i3c_ibi_time = LPS22DF_IBI_50us;
257 break;
258 case LPS22DF_IBI_2us:
259 val->i3c_ibi_time = LPS22DF_IBI_2us;
260 break;
261 case LPS22DF_IBI_1ms:
262 val->i3c_ibi_time = LPS22DF_IBI_1ms;
263 break;
264 case LPS22DF_IBI_25ms:
265 val->i3c_ibi_time = LPS22DF_IBI_25ms;
266 break;
267 default:
268 val->i3c_ibi_time = LPS22DF_IBI_50us;
269 break;
270 }
271 }
272 return ret;
273 }
274
275 /**
276 * @brief Configures the bus operating mode.[get]
277 *
278 * @param ctx communication interface handler.(ptr)
279 * @param val configures the bus operating mode.(ptr)
280 * @retval interface status (MANDATORY: return 0 -> no Error)
281 *
282 */
lps22df_init_set(const stmdev_ctx_t * ctx,lps22df_init_t val)283 int32_t lps22df_init_set(const stmdev_ctx_t *ctx, lps22df_init_t val)
284 {
285 lps22df_ctrl_reg2_t ctrl_reg2;
286 lps22df_ctrl_reg3_t ctrl_reg3;
287 lps22df_int_source_t int_src;
288 lps22df_stat_t status;
289 uint8_t reg[2], cnt = 0;
290 int32_t ret;
291
292 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG2, reg, 2);
293 if (ret == 0)
294 {
295 bytecpy((uint8_t *)&ctrl_reg2, ®[0]);
296 bytecpy((uint8_t *)&ctrl_reg3, ®[1]);
297
298 switch (val)
299 {
300 case LPS22DF_BOOT:
301 ctrl_reg2.boot = PROPERTY_ENABLE;
302 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2,
303 (uint8_t *)&ctrl_reg2, 1);
304 if (ret != 0)
305 {
306 break;
307 }
308
309 do
310 {
311 ret = lps22df_read_reg(ctx, LPS22DF_INT_SOURCE, (uint8_t *)&int_src, 1);
312 if (ret != 0)
313 {
314 break;
315 }
316
317 /* boot procedure ended correctly */
318 if (int_src.boot_on == 0U)
319 {
320 break;
321 }
322
323 if (ctx->mdelay != NULL)
324 {
325 ctx->mdelay(10); /* 10ms of boot time */
326 }
327 } while (cnt++ < 5U);
328
329 if (cnt >= 5U)
330 {
331 ret = -1; /* boot procedure failed */
332 }
333
334 break;
335 case LPS22DF_RESET:
336 ctrl_reg2.swreset = PROPERTY_ENABLE;
337 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2,
338 (uint8_t *)&ctrl_reg2, 1);
339 if (ret != 0)
340 {
341 break;
342 }
343
344 do
345 {
346 ret = lps22df_status_get(ctx, &status);
347 if (ret != 0)
348 {
349 break;
350 }
351
352 /* sw-reset procedure ended correctly */
353 if (status.sw_reset == 0U)
354 {
355 break;
356 }
357
358 if (ctx->mdelay != NULL)
359 {
360 ctx->mdelay(1); /* should be 50 us */
361 }
362 } while (cnt++ < 5U);
363
364 if (cnt >= 5U)
365 {
366 ret = -1; /* sw-reset procedure failed */
367 }
368
369 break;
370 case LPS22DF_DRV_RDY:
371 ctrl_reg2.bdu = PROPERTY_ENABLE;
372 ctrl_reg3.if_add_inc = PROPERTY_ENABLE;
373 bytecpy(®[0], (uint8_t *)&ctrl_reg2);
374 bytecpy(®[1], (uint8_t *)&ctrl_reg3);
375 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2, reg, 2);
376 break;
377 default:
378 ctrl_reg2.swreset = PROPERTY_ENABLE;
379 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2,
380 (uint8_t *)&ctrl_reg2, 1);
381 break;
382 }
383 }
384
385 return ret;
386 }
387
388 /**
389 * @brief Get the status of the device.[get]
390 *
391 * @param ctx communication interface handler.(ptr)
392 * @param val the status of the device.(ptr)
393 * @retval interface status (MANDATORY: return 0 -> no Error)
394 *
395 */
lps22df_status_get(const stmdev_ctx_t * ctx,lps22df_stat_t * val)396 int32_t lps22df_status_get(const stmdev_ctx_t *ctx, lps22df_stat_t *val)
397 {
398 lps22df_interrupt_cfg_t interrupt_cfg;
399 lps22df_int_source_t int_source;
400 lps22df_ctrl_reg2_t ctrl_reg2;
401 lps22df_status_t status;
402 int32_t ret;
403
404 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG2,
405 (uint8_t *)&ctrl_reg2, 1);
406 if (ret == 0)
407 {
408 ret = lps22df_read_reg(ctx, LPS22DF_INT_SOURCE, (uint8_t *)&int_source, 1);
409 }
410 if (ret == 0)
411 {
412 ret = lps22df_read_reg(ctx, LPS22DF_STATUS, (uint8_t *)&status, 1);
413 }
414 if (ret == 0)
415 {
416 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
417 (uint8_t *)&interrupt_cfg, 1);
418 }
419 val->sw_reset = ctrl_reg2.swreset;
420 val->boot = int_source.boot_on;
421 val->drdy_pres = status.p_da;
422 val->drdy_temp = status.t_da;
423 val->ovr_pres = status.p_or;
424 val->ovr_temp = status.t_or;
425 val->end_meas = ~ctrl_reg2.oneshot;
426 val->ref_done = ~interrupt_cfg.autozero;
427
428 return ret;
429 }
430
431 /**
432 * @brief Electrical pin configuration.[set]
433 *
434 * @param ctx communication interface handler.(ptr)
435 * @param val the electrical settings for the configurable pins.(ptr)
436 * @retval interface status (MANDATORY: return 0 -> no Error)
437 *
438 */
lps22df_pin_conf_set(const stmdev_ctx_t * ctx,lps22df_pin_conf_t * val)439 int32_t lps22df_pin_conf_set(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val)
440 {
441 lps22df_ctrl_reg3_t ctrl_reg3;
442 lps22df_if_ctrl_t if_ctrl;
443 int32_t ret;
444
445 ret = lps22df_read_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
446
447 if (ret == 0)
448 {
449 if_ctrl.int_pd_dis = ~val->int_pull_down;
450 if_ctrl.sdo_pu_en = val->sdo_pull_up;
451 if_ctrl.sda_pu_en = val->sda_pull_up;
452 if_ctrl.cs_pu_dis = ~val->cs_pull_up;
453 ret = lps22df_write_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
454 }
455 if (ret == 0)
456 {
457 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
458 }
459 if (ret == 0)
460 {
461 ctrl_reg3.pp_od = ~val->int_push_pull;
462 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
463 }
464
465 return ret;
466 }
467
468 /**
469 * @brief Electrical pin configuration.[get]
470 *
471 * @param ctx communication interface handler.(ptr)
472 * @param val the electrical settings for the configurable pins.(ptr)
473 * @retval interface status (MANDATORY: return 0 -> no Error)
474 *
475 */
lps22df_pin_conf_get(const stmdev_ctx_t * ctx,lps22df_pin_conf_t * val)476 int32_t lps22df_pin_conf_get(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val)
477 {
478 lps22df_ctrl_reg3_t ctrl_reg3;
479 lps22df_if_ctrl_t if_ctrl;
480 int32_t ret;
481
482 ret = lps22df_read_reg(ctx, LPS22DF_IF_CTRL, (uint8_t *)&if_ctrl, 1);
483 if (ret == 0)
484 {
485 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
486 }
487
488 val->sda_pull_up = if_ctrl.sda_pu_en;
489 val->cs_pull_up = ~if_ctrl.cs_pu_dis;
490 val->int_pull_down = ~if_ctrl.int_pd_dis;
491 val->sdo_pull_up = if_ctrl.sdo_pu_en;
492 val->int_push_pull = ~ctrl_reg3.pp_od;
493
494 return ret;
495 }
496
497 /**
498 * @brief Get the status of all the interrupt sources.[get]
499 *
500 * @param ctx communication interface handler.(ptr)
501 * @param val the status of all the interrupt sources.(ptr)
502 * @retval interface status (MANDATORY: return 0 -> no Error)
503 *
504 */
lps22df_all_sources_get(const stmdev_ctx_t * ctx,lps22df_all_sources_t * val)505 int32_t lps22df_all_sources_get(const stmdev_ctx_t *ctx,
506 lps22df_all_sources_t *val)
507 {
508 lps22df_fifo_status2_t fifo_status2;
509 lps22df_int_source_t int_source;
510 lps22df_status_t status;
511 int32_t ret;
512
513 ret = lps22df_read_reg(ctx, LPS22DF_STATUS, (uint8_t *)&status, 1);
514 if (ret == 0)
515 {
516 ret = lps22df_read_reg(ctx, LPS22DF_INT_SOURCE,
517 (uint8_t *)&int_source, 1);
518 }
519 if (ret == 0)
520 {
521 ret = lps22df_read_reg(ctx, LPS22DF_FIFO_STATUS2,
522 (uint8_t *)&fifo_status2, 1);
523 }
524
525 val->drdy_pres = status.p_da;
526 val->drdy_temp = status.t_da;
527 val->over_pres = int_source.ph;
528 val->under_pres = int_source.pl;
529 val->thrsld_pres = int_source.ia;
530 val->fifo_full = fifo_status2.fifo_full_ia;
531 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
532 val->fifo_th = fifo_status2.fifo_wtm_ia;
533
534 return ret;
535 }
536
537
538 /**
539 * @brief Sensor conversion parameters selection.[set]
540 *
541 * @param ctx communication interface handler.(ptr)
542 * @param val set the sensor conversion parameters.(ptr)
543 * @retval interface status (MANDATORY: return 0 -> no Error)
544 *
545 */
lps22df_mode_set(const stmdev_ctx_t * ctx,lps22df_md_t * val)546 int32_t lps22df_mode_set(const stmdev_ctx_t *ctx, lps22df_md_t *val)
547 {
548 lps22df_ctrl_reg1_t ctrl_reg1;
549 lps22df_ctrl_reg2_t ctrl_reg2;
550 uint8_t reg[2];
551 int32_t ret;
552
553 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG1, reg, 2);
554
555 if (ret == 0)
556 {
557 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
558 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
559
560 ctrl_reg1.odr = (uint8_t)val->odr;
561 ctrl_reg1.avg = (uint8_t)val->avg;
562 ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U;
563 ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 2;
564
565 bytecpy(®[0], (uint8_t *)&ctrl_reg1);
566 bytecpy(®[1], (uint8_t *)&ctrl_reg2);
567 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG1, reg, 2);
568 }
569
570 return ret;
571 }
572
573 /**
574 * @brief Sensor conversion parameters selection.[get]
575 *
576 * @param ctx communication interface handler.(ptr)
577 * @param val get the sensor conversion parameters.(ptr)
578 * @retval interface status (MANDATORY: return 0 -> no Error)
579 *
580 */
lps22df_mode_get(const stmdev_ctx_t * ctx,lps22df_md_t * val)581 int32_t lps22df_mode_get(const stmdev_ctx_t *ctx, lps22df_md_t *val)
582 {
583 lps22df_ctrl_reg1_t ctrl_reg1;
584 lps22df_ctrl_reg2_t ctrl_reg2;
585 uint8_t reg[2];
586 int32_t ret;
587
588 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG1, reg, 2);
589
590 if (ret == 0)
591 {
592 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
593 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
594
595 switch (ctrl_reg1.odr)
596 {
597 case LPS22DF_ONE_SHOT:
598 val->odr = LPS22DF_ONE_SHOT;
599 break;
600 case LPS22DF_1Hz:
601 val->odr = LPS22DF_1Hz;
602 break;
603 case LPS22DF_4Hz:
604 val->odr = LPS22DF_4Hz;
605 break;
606 case LPS22DF_10Hz:
607 val->odr = LPS22DF_10Hz;
608 break;
609 case LPS22DF_25Hz:
610 val->odr = LPS22DF_25Hz;
611 break;
612 case LPS22DF_50Hz:
613 val->odr = LPS22DF_50Hz;
614 break;
615 case LPS22DF_75Hz:
616 val->odr = LPS22DF_75Hz;
617 break;
618 case LPS22DF_100Hz:
619 val->odr = LPS22DF_100Hz;
620 break;
621 case LPS22DF_200Hz:
622 val->odr = LPS22DF_200Hz;
623 break;
624 default:
625 val->odr = LPS22DF_ONE_SHOT;
626 break;
627 }
628
629 switch (ctrl_reg1.avg)
630 {
631 case LPS22DF_4_AVG:
632 val->avg = LPS22DF_4_AVG;
633 break;
634 case LPS22DF_8_AVG:
635 val->avg = LPS22DF_8_AVG;
636 break;
637 case LPS22DF_16_AVG:
638 val->avg = LPS22DF_16_AVG;
639 break;
640 case LPS22DF_32_AVG:
641 val->avg = LPS22DF_32_AVG;
642 break;
643 case LPS22DF_64_AVG:
644 val->avg = LPS22DF_64_AVG;
645 break;
646 case LPS22DF_128_AVG:
647 val->avg = LPS22DF_128_AVG;
648 break;
649 case LPS22DF_256_AVG:
650 val->avg = LPS22DF_256_AVG;
651 break;
652 case LPS22DF_512_AVG:
653 val->avg = LPS22DF_512_AVG;
654 break;
655 default:
656 val->avg = LPS22DF_4_AVG;
657 break;
658 }
659
660 switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp)
661 {
662 case LPS22DF_LPF_DISABLE:
663 val->lpf = LPS22DF_LPF_DISABLE;
664 break;
665 case LPS22DF_LPF_ODR_DIV_4:
666 val->lpf = LPS22DF_LPF_ODR_DIV_4;
667 break;
668 case LPS22DF_LPF_ODR_DIV_9:
669 val->lpf = LPS22DF_LPF_ODR_DIV_9;
670 break;
671 default:
672 val->lpf = LPS22DF_LPF_DISABLE;
673 break;
674 }
675 }
676 return ret;
677 }
678
679 /**
680 * @brief Software trigger for One-Shot.[get]
681 *
682 * @param ctx communication interface handler.(ptr)
683 * @param md the sensor conversion parameters.(ptr)
684 * @retval interface status (MANDATORY: return 0 -> no Error)
685 *
686 */
lps22df_trigger_sw(const stmdev_ctx_t * ctx,lps22df_md_t * md)687 int32_t lps22df_trigger_sw(const stmdev_ctx_t *ctx, lps22df_md_t *md)
688 {
689 lps22df_ctrl_reg2_t ctrl_reg2;
690 int32_t ret = 0;
691
692 if (md->odr == LPS22DF_ONE_SHOT)
693 {
694 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
695 ctrl_reg2.oneshot = PROPERTY_ENABLE;
696 if (ret == 0)
697 {
698 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
699 }
700 }
701 return ret;
702 }
703
704 /**
705 * @brief Sensor data.[get]
706 *
707 * @param ctx communication interface handler.(ptr)
708 * @param data data retrieved from the sensor.(ptr)
709 * @retval interface status (MANDATORY: return 0 -> no Error)
710 *
711 */
lps22df_data_get(const stmdev_ctx_t * ctx,lps22df_data_t * data)712 int32_t lps22df_data_get(const stmdev_ctx_t *ctx, lps22df_data_t *data)
713 {
714 uint8_t buff[5];
715 int32_t ret;
716
717 ret = lps22df_read_reg(ctx, LPS22DF_PRESS_OUT_XL, buff, 5);
718
719 /* pressure conversion */
720 data->pressure.raw = (int32_t)buff[2];
721 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1];
722 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0];
723 data->pressure.raw = data->pressure.raw * 256;
724
725 data->pressure.hpa = lps22df_from_lsb_to_hPa(data->pressure.raw);
726
727
728 /* temperature conversion */
729 data->heat.raw = (int16_t)buff[4];
730 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3];
731 data->heat.deg_c = lps22df_from_lsb_to_celsius(data->heat.raw);
732
733 return ret;
734 }
735
736 /**
737 * @brief Pressure output value.[get]
738 *
739 * @param ctx read / write interface definitions
740 * @param buff buffer that stores data read
741 * @retval interface status (MANDATORY: return 0 -> no Error)
742 *
743 */
lps22df_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)744 int32_t lps22df_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
745 {
746 int32_t ret;
747 uint8_t reg[3];
748
749 ret = lps22df_read_reg(ctx, LPS22DF_PRESS_OUT_XL, reg, 3);
750 *buff = reg[2];
751 *buff = (*buff * 256U) + reg[1];
752 *buff = (*buff * 256U) + reg[0];
753 *buff *= 256U;
754
755 return ret;
756 }
757
758 /**
759 * @brief Temperature output value.[get]
760 *
761 * @param ctx read / write interface definitions
762 * @param buff buffer that stores data read
763 * @retval interface status (MANDATORY: return 0 -> no Error)
764 *
765 */
lps22df_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)766 int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
767 {
768 int32_t ret;
769 uint8_t reg[2];
770
771 ret = lps22df_read_reg(ctx, LPS22DF_TEMP_OUT_L, reg, 2);
772 *buff = (int16_t)reg[1];
773 *buff = (*buff * 256) + (int16_t)reg[0];
774
775 return ret;
776 }
777
778 /**
779 * @}
780 *
781 */
782
783 /**
784 * @defgroup FIFO functions
785 * @brief This section groups all the functions concerning the
786 * management of FIFO.
787 * @{
788 *
789 */
790
791 /**
792 * @brief FIFO operation mode selection.[set]
793 *
794 * @param ctx communication interface handler.(ptr)
795 * @param val set the FIFO operation mode.(ptr)
796 * @retval interface status (MANDATORY: return 0 -> no Error)
797 *
798 */
lps22df_fifo_mode_set(const stmdev_ctx_t * ctx,lps22df_fifo_md_t * val)799 int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val)
800 {
801 lps22df_fifo_ctrl_t fifo_ctrl;
802 lps22df_fifo_wtm_t fifo_wtm;
803 uint8_t reg[2];
804 int32_t ret;
805
806 ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2);
807 if (ret == 0)
808 {
809 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
810 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
811
812 fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U;
813 fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2;
814
815 if (val->watermark != 0x00U)
816 {
817 fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE;
818 }
819 else
820 {
821 fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE;
822 }
823
824 fifo_wtm.wtm = val->watermark;
825
826 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
827 bytecpy(®[1], (uint8_t *)&fifo_wtm);
828
829 ret = lps22df_write_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2);
830 }
831 return ret;
832 }
833
834 /**
835 * @brief FIFO operation mode selection.[get]
836 *
837 * @param ctx communication interface handler.(ptr)
838 * @param val get the FIFO operation mode.(ptr)
839 * @retval interface status (MANDATORY: return 0 -> no Error)
840 *
841 */
lps22df_fifo_mode_get(const stmdev_ctx_t * ctx,lps22df_fifo_md_t * val)842 int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val)
843 {
844 lps22df_fifo_ctrl_t fifo_ctrl;
845 lps22df_fifo_wtm_t fifo_wtm;
846 uint8_t reg[2];
847 int32_t ret;
848
849 ret = lps22df_read_reg(ctx, LPS22DF_FIFO_CTRL, reg, 2);
850
851 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
852 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
853
854 switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode)
855 {
856 case LPS22DF_BYPASS:
857 val->operation = LPS22DF_BYPASS;
858 break;
859 case LPS22DF_FIFO:
860 val->operation = LPS22DF_FIFO;
861 break;
862 case LPS22DF_STREAM:
863 val->operation = LPS22DF_STREAM;
864 break;
865 case LPS22DF_STREAM_TO_FIFO:
866 val->operation = LPS22DF_STREAM_TO_FIFO;
867 break;
868 case LPS22DF_BYPASS_TO_STREAM:
869 val->operation = LPS22DF_BYPASS_TO_STREAM;
870 break;
871 case LPS22DF_BYPASS_TO_FIFO:
872 val->operation = LPS22DF_BYPASS_TO_FIFO;
873 break;
874 default:
875 val->operation = LPS22DF_BYPASS;
876 break;
877 }
878
879 val->watermark = fifo_wtm.wtm;
880
881 return ret;
882 }
883
884 /**
885 * @brief Get the number of samples stored in FIFO.[get]
886 *
887 * @param ctx communication interface handler.(ptr)
888 * @param val number of samples stored in FIFO.(ptr)
889 * @retval interface status (MANDATORY: return 0 -> no Error)
890 *
891 */
lps22df_fifo_level_get(const stmdev_ctx_t * ctx,uint8_t * val)892 int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
893 {
894 lps22df_fifo_status1_t fifo_status1;
895 int32_t ret;
896
897 ret = lps22df_read_reg(ctx, LPS22DF_FIFO_STATUS1,
898 (uint8_t *)&fifo_status1, 1);
899
900 *val = fifo_status1.fss;
901
902 return ret;
903 }
904
905 /**
906 * @brief Software trigger for One-Shot.[get]
907 *
908 * @param ctx communication interface handler.(ptr)
909 * @param samp number of samples stored in FIFO.(ptr)
910 * @param data data retrieved from FIFO.(ptr)
911 * @retval interface status (MANDATORY: return 0 -> no Error)
912 *
913 */
lps22df_fifo_data_get(const stmdev_ctx_t * ctx,uint8_t samp,lps22df_fifo_data_t * data)914 int32_t lps22df_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data)
915 {
916 uint8_t fifo_data[3];
917 uint8_t i;
918 int32_t ret = 0;
919
920 for (i = 0U; i < samp; i++)
921 {
922 ret = lps22df_read_reg(ctx, LPS22DF_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3);
923 data[i].raw = (int32_t)fifo_data[2];
924 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1];
925 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0];
926 data[i].raw = (data[i].raw * 256);
927 data[i].hpa = lps22df_from_lsb_to_hPa(data[i].raw);
928 }
929
930 return ret;
931 }
932
933 /**
934 * @}
935 *
936 */
937
938 /**
939 * @defgroup Interrupt signals
940 * @brief This section groups all the functions concerning
941 * the management of interrupt signals.
942 * @{
943 *
944 */
945
946 /**
947 * @brief Interrupt pins hardware signal configuration.[set]
948 *
949 * @param ctx communication interface handler.(ptr)
950 * @param val the pins hardware signal settings.(ptr)
951 * @retval interface status (MANDATORY: return 0 -> no Error)
952 *
953 */
lps22df_interrupt_mode_set(const stmdev_ctx_t * ctx,lps22df_int_mode_t * val)954 int32_t lps22df_interrupt_mode_set(const stmdev_ctx_t *ctx,
955 lps22df_int_mode_t *val)
956 {
957 lps22df_interrupt_cfg_t interrupt_cfg;
958 lps22df_ctrl_reg3_t ctrl_reg3;
959 lps22df_ctrl_reg4_t ctrl_reg4;
960 uint8_t reg[2];
961 int32_t ret;
962
963 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, reg, 2);
964 if (ret == 0)
965 {
966 bytecpy((uint8_t *)&ctrl_reg3, ®[0]);
967 bytecpy((uint8_t *)&ctrl_reg4, ®[1]);
968
969 ctrl_reg3.int_h_l = val->active_low;
970 ctrl_reg4.drdy_pls = ~val->drdy_latched;
971
972 bytecpy(®[0], (uint8_t *)&ctrl_reg3);
973 bytecpy(®[1], (uint8_t *)&ctrl_reg4);
974
975 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG3, reg, 2);
976 }
977 ret += lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
978 (uint8_t *)&interrupt_cfg, 1);
979 if (ret == 0)
980 {
981 interrupt_cfg.lir = val->int_latched ;
982 ret = lps22df_write_reg(ctx, LPS22DF_INTERRUPT_CFG,
983 (uint8_t *)&interrupt_cfg, 1);
984 }
985 return ret;
986 }
987
988 /**
989 * @brief Interrupt pins hardware signal configuration.[get]
990 *
991 * @param ctx communication interface handler.(ptr)
992 * @param val the pins hardware signal settings.(ptr)
993 * @retval interface status (MANDATORY: return 0 -> no Error)
994 *
995 */
lps22df_interrupt_mode_get(const stmdev_ctx_t * ctx,lps22df_int_mode_t * val)996 int32_t lps22df_interrupt_mode_get(const stmdev_ctx_t *ctx,
997 lps22df_int_mode_t *val)
998 {
999 lps22df_interrupt_cfg_t interrupt_cfg;
1000 lps22df_ctrl_reg3_t ctrl_reg3;
1001 lps22df_ctrl_reg4_t ctrl_reg4;
1002 uint8_t reg[2];
1003 int32_t ret;
1004
1005 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG3, reg, 2);
1006 ret += lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
1007 (uint8_t *)&interrupt_cfg, 1);
1008
1009 bytecpy((uint8_t *)&ctrl_reg3, ®[0]);
1010 bytecpy((uint8_t *)&ctrl_reg4, ®[1]);
1011
1012 val->active_low = ctrl_reg3.int_h_l;
1013 val->drdy_latched = ~ctrl_reg4.drdy_pls;
1014 val->int_latched = interrupt_cfg.lir;
1015
1016 return ret;
1017 }
1018
1019 /**
1020 * @brief Route interrupt signals on int1 pin.[set]
1021 *
1022 * @param ctx communication interface handler.(ptr)
1023 * @param val the signals to route on int1 pin.(ptr)
1024 * @retval interface status (MANDATORY: return 0 -> no Error)
1025 *
1026 */
lps22df_pin_int_route_set(const stmdev_ctx_t * ctx,lps22df_pin_int_route_t * val)1027 int32_t lps22df_pin_int_route_set(const stmdev_ctx_t *ctx,
1028 lps22df_pin_int_route_t *val)
1029 {
1030 lps22df_ctrl_reg4_t ctrl_reg4;
1031 int32_t ret;
1032
1033 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1034 if (ret == 0)
1035 {
1036 ctrl_reg4.drdy = val->drdy_pres;
1037 ctrl_reg4.int_f_wtm = val->fifo_th;
1038 ctrl_reg4.int_f_ovr = val->fifo_ovr;
1039 ctrl_reg4.int_f_full = val->fifo_full;
1040
1041 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1042 }
1043 return ret;
1044 }
1045
1046 /**
1047 * @brief Route interrupt signals on int1 pin.[get]
1048 *
1049 * @param ctx communication interface handler.(ptr)
1050 * @param val the signals that are routed on int1 pin.(ptr)
1051 * @retval interface status (MANDATORY: return 0 -> no Error)
1052 *
1053 */
lps22df_pin_int_route_get(const stmdev_ctx_t * ctx,lps22df_pin_int_route_t * val)1054 int32_t lps22df_pin_int_route_get(const stmdev_ctx_t *ctx,
1055 lps22df_pin_int_route_t *val)
1056 {
1057 lps22df_ctrl_reg4_t ctrl_reg4;
1058 int32_t ret;
1059
1060 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1061
1062 val->drdy_pres = ctrl_reg4.drdy;
1063 val->fifo_th = ctrl_reg4.int_f_wtm;
1064 val->fifo_ovr = ctrl_reg4.int_f_ovr;
1065 val->fifo_full = ctrl_reg4.int_f_full;
1066
1067 return ret;
1068
1069 }
1070
1071 /**
1072 * @}
1073 *
1074 */
1075
1076 /**
1077 * @defgroup Interrupt on threshold functions
1078 * @brief This section groups all the functions concerning
1079 * the wake up functionality.
1080 * @{
1081 *
1082 */
1083
1084 /**
1085 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1086 *
1087 * @param ctx communication interface handler.(ptr)
1088 * @param val parameters of configuration.(ptr)
1089 * @retval interface status (MANDATORY: return 0 -> no Error)
1090 *
1091 */
lps22df_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,lps22df_int_th_md_t * val)1092 int32_t lps22df_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1093 lps22df_int_th_md_t *val)
1094 {
1095 lps22df_ctrl_reg4_t ctrl_reg4;
1096 lps22df_interrupt_cfg_t interrupt_cfg;
1097 lps22df_ths_p_l_t ths_p_l;
1098 lps22df_ths_p_h_t ths_p_h;
1099 uint8_t reg[3];
1100 int32_t ret;
1101
1102 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, reg, 3);
1103 if (ret == 0)
1104 {
1105 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1106 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1107 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1108
1109 interrupt_cfg.phe = val->over_th;
1110 interrupt_cfg.ple = val->under_th;
1111 ths_p_h.ths = (uint8_t)(val->threshold / 256U);
1112 ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U));
1113
1114 bytecpy(®[0], (uint8_t *)&interrupt_cfg);
1115 bytecpy(®[1], (uint8_t *)&ths_p_l);
1116 bytecpy(®[2], (uint8_t *)&ths_p_h);
1117
1118 ret = lps22df_write_reg(ctx, LPS22DF_INTERRUPT_CFG, reg, 3);
1119 }
1120
1121 if (ret == 0)
1122 {
1123 ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1124 if (ret == 0)
1125 {
1126 ctrl_reg4.int_en = PROPERTY_ENABLE;
1127 ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1128 }
1129 }
1130
1131 return ret;
1132 }
1133
1134 /**
1135 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1136 *
1137 * @param ctx communication interface handler.(ptr)
1138 * @param val parameters of configuration.(ptr)
1139 * @retval interface status (MANDATORY: return 0 -> no Error)
1140 *
1141 */
lps22df_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,lps22df_int_th_md_t * val)1142 int32_t lps22df_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1143 lps22df_int_th_md_t *val)
1144 {
1145 lps22df_interrupt_cfg_t interrupt_cfg;
1146 lps22df_ths_p_l_t ths_p_l;
1147 lps22df_ths_p_h_t ths_p_h;
1148 uint8_t reg[3];
1149 int32_t ret;
1150
1151 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG, reg, 3);
1152
1153 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1154 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1155 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1156
1157 val->over_th = interrupt_cfg.phe;
1158 val->under_th = interrupt_cfg.ple;
1159 val->threshold = ths_p_h.ths;
1160 val->threshold = (val->threshold * 256U) + ths_p_l.ths;
1161
1162 return ret;
1163 }
1164
1165 /**
1166 * @}
1167 *
1168 */
1169
1170 /**
1171 * @defgroup Reference value of pressure
1172 * @brief This section groups all the functions concerning
1173 * the wake up functionality.
1174 * @{
1175 *
1176 */
1177
1178 /**
1179 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1180 *
1181 * @param ctx communication interface handler.(ptr)
1182 * @param val parameters of configuration.(ptr)
1183 * @retval interface status (MANDATORY: return 0 -> no Error)
1184 *
1185 */
lps22df_reference_mode_set(const stmdev_ctx_t * ctx,lps22df_ref_md_t * val)1186 int32_t lps22df_reference_mode_set(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val)
1187 {
1188 lps22df_interrupt_cfg_t interrupt_cfg;
1189 int32_t ret;
1190
1191 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
1192 (uint8_t *)&interrupt_cfg, 1);
1193 if (ret == 0)
1194 {
1195
1196 interrupt_cfg.autozero = val->get_ref;
1197 interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U;
1198
1199 interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1200 interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1201
1202 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
1203 (uint8_t *)&interrupt_cfg, 1);
1204 }
1205 return ret;
1206 }
1207
1208 /**
1209 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1210 *
1211 * @param ctx communication interface handler.(ptr)
1212 * @param val parameters of configuration.(ptr)
1213 * @retval interface status (MANDATORY: return 0 -> no Error)
1214 *
1215 */
lps22df_reference_mode_get(const stmdev_ctx_t * ctx,lps22df_ref_md_t * val)1216 int32_t lps22df_reference_mode_get(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val)
1217 {
1218 lps22df_interrupt_cfg_t interrupt_cfg;
1219 int32_t ret;
1220
1221 ret = lps22df_read_reg(ctx, LPS22DF_INTERRUPT_CFG,
1222 (uint8_t *)&interrupt_cfg, 1);
1223
1224 switch ((interrupt_cfg.reset_az << 1) |
1225 interrupt_cfg.autorefp)
1226 {
1227 case LPS22DF_OUT_AND_INTERRUPT:
1228 val->apply_ref = LPS22DF_OUT_AND_INTERRUPT;
1229 break;
1230 case LPS22DF_ONLY_INTERRUPT:
1231 val->apply_ref = LPS22DF_ONLY_INTERRUPT;
1232 break;
1233 default:
1234 val->apply_ref = LPS22DF_RST_REFS;
1235 break;
1236 }
1237 val->get_ref = interrupt_cfg.autozero;
1238
1239 return ret;
1240 }
1241
1242
1243 /**
1244 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1245 *
1246 * @param ctx communication interface handler.(ptr)
1247 * @param val parameters of configuration.(ptr)
1248 * @retval interface status (MANDATORY: return 0 -> no Error)
1249 *
1250 */
lps22df_opc_set(const stmdev_ctx_t * ctx,int16_t val)1251 int32_t lps22df_opc_set(const stmdev_ctx_t *ctx, int16_t val)
1252 {
1253 uint8_t reg[2];
1254 int32_t ret;
1255
1256 reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U);
1257 reg[0] = (uint8_t)((uint16_t)val & 0x00FFU);
1258
1259 ret = lps22df_write_reg(ctx, LPS22DF_RPDS_L, reg, 2);
1260
1261 return ret;
1262 }
1263
1264 /**
1265 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1266 *
1267 * @param ctx communication interface handler.(ptr)
1268 * @param val parameters of configuration.(ptr)
1269 * @retval interface status (MANDATORY: return 0 -> no Error)
1270 *
1271 */
lps22df_opc_get(const stmdev_ctx_t * ctx,int16_t * val)1272 int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val)
1273 {
1274 uint8_t reg[2];
1275 int32_t ret;
1276
1277 ret = lps22df_read_reg(ctx, LPS22DF_RPDS_L, reg, 2);
1278
1279 *val = (int16_t)reg[1];
1280 *val = *val * 256 + (int16_t)reg[0];
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @}
1287 *
1288 */
1289
1290 /**
1291 * @}
1292 *
1293 */
1294
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