1 /**
2 ******************************************************************************
3 * @file lis3dhh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS3DHH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis3dhh_reg.h"
21
22 /**
23 * @defgroup LIS3DHH
24 * @brief This file provides a set of functions needed to drive the
25 * lis3dhh enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS3DHH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis3dhh_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis3dhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis3dhh_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis3dhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS3DHH_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lis3dhh_from_lsb_to_mg(int16_t lsb)103 float_t lis3dhh_from_lsb_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.076f);
106 }
107
lis3dhh_from_lsb_to_celsius(int16_t lsb)108 float_t lis3dhh_from_lsb_to_celsius(int16_t lsb)
109 {
110 return (((float_t)lsb / 16.0f) + 25.0f);
111 }
112
113 /**
114 * @}
115 *
116 */
117
118 /**
119 * @defgroup LIS3DHH_Data_generation
120 * @brief This section groups all the functions concerning data
121 * generation
122 * @{
123 *
124 */
125
126 /**
127 * @brief Blockdataupdate.[set]
128 *
129 * @param ctx Read / write interface definitions.(ptr)
130 * @param val Change the values of bdu in reg CTRL_REG1.
131 * @retval Interface status (MANDATORY: return 0 -> no Error).
132 *
133 */
lis3dhh_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)134 int32_t lis3dhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
135 {
136 lis3dhh_ctrl_reg1_t ctrl_reg1;
137 int32_t ret;
138
139 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
140
141 if (ret == 0)
142 {
143 ctrl_reg1.bdu = val;
144 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
145 }
146
147 return ret;
148 }
149
150 /**
151 * @brief Blockdataupdate.[get]
152 *
153 * @param ctx Read / write interface definitions.(ptr)
154 * @param val Get the values of bdu in reg CTRL_REG1.(ptr)
155 * @retval Interface status (MANDATORY: return 0 -> no Error).
156 *
157 */
lis3dhh_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)158 int32_t lis3dhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
159 {
160 lis3dhh_ctrl_reg1_t ctrl_reg1;
161 int32_t ret;
162
163 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
164 *val = ctrl_reg1.bdu;
165
166 return ret;
167 }
168
169 /**
170 * @brief Output data rate selection.[set]
171 *
172 * @param ctx Read / write interface definitions.(ptr)
173 * @param val Change the values of norm_mod_en in reg CTRL_REG1
174 * @retval Interface status (MANDATORY: return 0 -> no Error).
175 *
176 */
lis3dhh_data_rate_set(const stmdev_ctx_t * ctx,lis3dhh_norm_mod_en_t val)177 int32_t lis3dhh_data_rate_set(const stmdev_ctx_t *ctx,
178 lis3dhh_norm_mod_en_t val)
179 {
180 lis3dhh_ctrl_reg1_t ctrl_reg1;
181 int32_t ret;
182
183 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
184
185 if (ret == 0)
186 {
187 ctrl_reg1.norm_mod_en = (uint8_t)val;
188 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
189 }
190
191 return ret;
192 }
193
194 /**
195 * @brief Output data rate selection.[get]
196 *
197 * @param ctx Read / write interface definitions.(ptr)
198 * @param val Get the values of norm_mod_en in reg CTRL_REG1.(ptr)
199 * @retval Interface status (MANDATORY: return 0 -> no Error).
200 *
201 */
lis3dhh_data_rate_get(const stmdev_ctx_t * ctx,lis3dhh_norm_mod_en_t * val)202 int32_t lis3dhh_data_rate_get(const stmdev_ctx_t *ctx,
203 lis3dhh_norm_mod_en_t *val)
204 {
205 lis3dhh_ctrl_reg1_t ctrl_reg1;
206 int32_t ret;
207
208 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
209
210 switch (ctrl_reg1.norm_mod_en)
211 {
212 case LIS3DHH_POWER_DOWN:
213 *val = LIS3DHH_POWER_DOWN;
214 break;
215
216 case LIS3DHH_1kHz1:
217 *val = LIS3DHH_1kHz1;
218 break;
219
220 default:
221 *val = LIS3DHH_POWER_DOWN;
222 break;
223 }
224
225 return ret;
226 }
227
228 /**
229 * @brief Temperature output value.[get]
230 *
231 * @param ctx Read / write interface definitions.(ptr)
232 * @param buff Buffer that stores data read
233 * @retval Interface status (MANDATORY: return 0 -> no Error).
234 *
235 */
lis3dhh_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)236 int32_t lis3dhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
237 {
238 uint8_t buff[2];
239 int32_t ret;
240
241 ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_TEMP_L, buff, 2);
242 *val = (int16_t)buff[1];
243 *val = (*val * 256) + (int16_t)buff[0];
244
245 return ret;
246 }
247
248 /**
249 * @brief acceleration output value.[get]
250 *
251 * @param ctx Read / write interface definitions.(ptr)
252 * @param buff Buffer that stores data read
253 * @retval Interface status (MANDATORY: return 0 -> no Error).
254 *
255 */
lis3dhh_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)256 int32_t lis3dhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
257 {
258 uint8_t buff[6];
259 int32_t ret;
260
261 ret = lis3dhh_read_reg(ctx, LIS3DHH_OUT_X_L_XL, buff, 6);
262 val[0] = (int16_t)buff[1];
263 val[0] = (val[0] * 256) + (int16_t)buff[0];
264 val[1] = (int16_t)buff[3];
265 val[1] = (val[1] * 256) + (int16_t)buff[2];
266 val[2] = (int16_t)buff[5];
267 val[2] = (val[2] * 256) + (int16_t)buff[4];
268
269 return ret;
270 }
271
272 /**
273 * @brief Acceleration set of data available.[get]
274 *
275 * @param ctx Read / write interface definitions.(ptr)
276 * @param val Get the values of zyxda in reg STATUS.(ptr)
277 * @retval Interface status (MANDATORY: return 0 -> no Error).
278 *
279 */
lis3dhh_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)280 int32_t lis3dhh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
281 {
282 lis3dhh_status_t status;
283 int32_t ret;
284
285 ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1);
286 *val = status.zyxda;
287
288 return ret;
289 }
290
291 /**
292 * @brief Acceleration set of data overrun.[get]
293 *
294 * @param ctx Read / write interface definitions.(ptr)
295 * @param val Get the values of zyxor in reg STATUS.(ptr)
296 * @retval Interface status (MANDATORY: return 0 -> no Error).
297 *
298 */
lis3dhh_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)299 int32_t lis3dhh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
300 {
301 lis3dhh_status_t status;
302 int32_t ret;
303
304 ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *)&status, 1);
305 *val = status.zyxor;
306
307 return ret;
308 }
309
310 /**
311 * @}
312 *
313 */
314
315 /**
316 * @defgroup LIS3DHH_common
317 * @brief This section group common useful functions
318 * @{
319 *
320 */
321
322 /**
323 * @brief DeviceWhoamI.[get]
324 *
325 * @param ctx Read / write interface definitions.(ptr)
326 * @param buff Buffer that stores data read
327 * @retval Interface status (MANDATORY: return 0 -> no Error).
328 *
329 */
lis3dhh_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)330 int32_t lis3dhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
331 {
332 int32_t ret;
333
334 ret = lis3dhh_read_reg(ctx, LIS3DHH_WHO_AM_I, buff, 1);
335
336 return ret;
337 }
338
339 /**
340 * @brief Software reset. Restore the default values in user registers.[set]
341 *
342 * @param ctx Read / write interface definitions.(ptr)
343 * @param val Change the values of sw_reset in reg CTRL_REG1.
344 * @retval Interface status (MANDATORY: return 0 -> no Error).
345 *
346 */
lis3dhh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)347 int32_t lis3dhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
348 {
349 lis3dhh_ctrl_reg1_t ctrl_reg1;
350 int32_t ret;
351
352 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
353
354 if (ret == 0)
355 {
356 ctrl_reg1.sw_reset = val;
357 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
358 }
359
360 return ret;
361 }
362
363 /**
364 * @brief Software reset. Restore the default values in user registers.[get]
365 *
366 * @param ctx Read / write interface definitions.(ptr)
367 * @param val Get the values of sw_reset in reg CTRL_REG1.(ptr)
368 * @retval Interface status (MANDATORY: return 0 -> no Error).
369 *
370 */
lis3dhh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)371 int32_t lis3dhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
372 {
373 lis3dhh_ctrl_reg1_t ctrl_reg1;
374 int32_t ret;
375
376 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
377 *val = ctrl_reg1.sw_reset;
378
379 return ret;
380 }
381
382 /**
383 * @brief Reboot memory content. Reload the calibration parameters.[set]
384 *
385 * @param ctx Read / write interface definitions.(ptr)
386 * @param val Change the values of boot in reg CTRL_REG1
387 * @retval Interface status (MANDATORY: return 0 -> no Error).
388 *
389 */
lis3dhh_boot_set(const stmdev_ctx_t * ctx,uint8_t val)390 int32_t lis3dhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
391 {
392 lis3dhh_ctrl_reg1_t ctrl_reg1;
393 int32_t ret;
394
395 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
396
397 if (ret == 0)
398 {
399 ctrl_reg1.boot = val;
400 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
401 }
402
403 return ret;
404 }
405
406 /**
407 * @brief Reboot memory content. Reload the calibration parameters.[get]
408 *
409 * @param ctx Read / write interface definitions.(ptr)
410 * @param val Get the values of boot in reg CTRL_REG1.(ptr)
411 * @retval Interface status (MANDATORY: return 0 -> no Error).
412 *
413 */
lis3dhh_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)414 int32_t lis3dhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
415 {
416 lis3dhh_ctrl_reg1_t ctrl_reg1;
417 int32_t ret;
418
419 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
420 *val = ctrl_reg1.boot;
421
422 return ret;
423 }
424
425 /**
426 * @brief Selftest.[set]
427 *
428 * @param ctx Read / write interface definitions.(ptr)
429 * @param val Change the values of st in reg CTRL_REG4
430 * @retval Interface status (MANDATORY: return 0 -> no Error).
431 *
432 */
lis3dhh_self_test_set(const stmdev_ctx_t * ctx,lis3dhh_st_t val)433 int32_t lis3dhh_self_test_set(const stmdev_ctx_t *ctx, lis3dhh_st_t val)
434 {
435 lis3dhh_ctrl_reg4_t ctrl_reg4;
436 int32_t ret;
437
438 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
439
440 if (ret == 0)
441 {
442 ctrl_reg4.st = (uint8_t)val;
443 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
444 }
445
446 return ret;
447 }
448
449 /**
450 * @brief Selftest.[get]
451 *
452 * @param ctx Read / write interface definitions.(ptr)
453 * @param val Get the values of st in reg CTRL_REG4.(ptr)
454 * @retval Interface status (MANDATORY: return 0 -> no Error).
455 *
456 */
lis3dhh_self_test_get(const stmdev_ctx_t * ctx,lis3dhh_st_t * val)457 int32_t lis3dhh_self_test_get(const stmdev_ctx_t *ctx, lis3dhh_st_t *val)
458 {
459 lis3dhh_ctrl_reg4_t ctrl_reg4;
460 int32_t ret;
461
462 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
463
464 switch (ctrl_reg4.st)
465 {
466 case LIS3DHH_ST_DISABLE:
467 *val = LIS3DHH_ST_DISABLE;
468 break;
469
470 case LIS3DHH_ST_POSITIVE:
471 *val = LIS3DHH_ST_POSITIVE;
472 break;
473
474 case LIS3DHH_ST_NEGATIVE:
475 *val = LIS3DHH_ST_NEGATIVE;
476 break;
477
478 default:
479 *val = LIS3DHH_ST_DISABLE;
480 break;
481 }
482
483 return ret;
484 }
485
486 /**
487 * @brief Digital filtering Phase/bandwidth selection.[set]
488 *
489 * @param ctx Read / write interface definitions.(ptr)
490 * @param val Change the values of dsp in reg CTRL_REG4
491 * @retval Interface status (MANDATORY: return 0 -> no Error).
492 *
493 */
lis3dhh_filter_config_set(const stmdev_ctx_t * ctx,lis3dhh_dsp_t val)494 int32_t lis3dhh_filter_config_set(const stmdev_ctx_t *ctx,
495 lis3dhh_dsp_t val)
496 {
497 lis3dhh_ctrl_reg4_t ctrl_reg4;
498 int32_t ret;
499
500 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
501
502 if (ret == 0)
503 {
504 ctrl_reg4.dsp = (uint8_t)val;
505 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
506 }
507
508 return ret;
509 }
510
511 /**
512 * @brief Digital filtering Phase/bandwidth selection.[get]
513 *
514 * @param ctx Read / write interface definitions.(ptr)
515 * @param val Get the values of dsp in reg CTRL_REG4.(ptr)
516 * @retval Interface status (MANDATORY: return 0 -> no Error).
517 *
518 */
lis3dhh_filter_config_get(const stmdev_ctx_t * ctx,lis3dhh_dsp_t * val)519 int32_t lis3dhh_filter_config_get(const stmdev_ctx_t *ctx,
520 lis3dhh_dsp_t *val)
521 {
522 lis3dhh_ctrl_reg4_t ctrl_reg4;
523 int32_t ret;
524
525 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
526
527 switch (ctrl_reg4.dsp)
528 {
529 case LIS3DHH_LINEAR_PHASE_440Hz:
530 *val = LIS3DHH_LINEAR_PHASE_440Hz;
531 break;
532
533 case LIS3DHH_LINEAR_PHASE_235Hz:
534 *val = LIS3DHH_LINEAR_PHASE_235Hz;
535 break;
536
537 case LIS3DHH_NO_LINEAR_PHASE_440Hz:
538 *val = LIS3DHH_NO_LINEAR_PHASE_440Hz;
539 break;
540
541 case LIS3DHH_NO_LINEAR_PHASE_235Hz:
542 *val = LIS3DHH_NO_LINEAR_PHASE_235Hz;
543 break;
544
545 default:
546 *val = LIS3DHH_LINEAR_PHASE_440Hz;
547 break;
548 }
549
550 return ret;
551 }
552
553 /**
554 * @brief Statusregister.[get]
555 *
556 * @param ctx Read / write interface definitions.(ptr)
557 * @param val Get registers STATUS.(ptr)
558 * @retval Interface status (MANDATORY: return 0 -> no Error).
559 *
560 */
lis3dhh_status_get(const stmdev_ctx_t * ctx,lis3dhh_status_t * val)561 int32_t lis3dhh_status_get(const stmdev_ctx_t *ctx, lis3dhh_status_t *val)
562 {
563 int32_t ret;
564
565 ret = lis3dhh_read_reg(ctx, LIS3DHH_STATUS, (uint8_t *) val, 1);
566
567 return ret;
568 }
569
570 /**
571 * @}
572 *
573 */
574
575 /**
576 * @defgroup LIS3DHH_interrupts
577 * @brief This section group all the functions that manage interrupts
578 * @{
579 *
580 */
581
582 /**
583 * @brief DRDY latched / pulsed, pulse duration is 1/4 ODR.[set]
584 *
585 * @param ctx Read / write interface definitions.(ptr)
586 * @param val Change the values of drdy_pulse in reg CTRL_REG1
587 * @retval Interface status (MANDATORY: return 0 -> no Error).
588 *
589 */
lis3dhh_drdy_notification_mode_set(const stmdev_ctx_t * ctx,lis3dhh_drdy_pulse_t val)590 int32_t lis3dhh_drdy_notification_mode_set(const stmdev_ctx_t *ctx,
591 lis3dhh_drdy_pulse_t val)
592 {
593 lis3dhh_ctrl_reg1_t ctrl_reg1;
594 int32_t ret;
595
596 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
597
598 if (ret == 0)
599 {
600 ctrl_reg1.drdy_pulse = (uint8_t)val;
601 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
602 }
603
604 return ret;
605 }
606
607 /**
608 * @brief DRDY latched / pulsed, pulse duration is 1/4 ODR.[get]
609 *
610 * @param ctx Read / write interface definitions.(ptr)
611 * @param val Get the values of drdy_pulse in reg CTRL_REG1.(ptr)
612 * @retval Interface status (MANDATORY: return 0 -> no Error).
613 *
614 */
lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t * ctx,lis3dhh_drdy_pulse_t * val)615 int32_t lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t *ctx,
616 lis3dhh_drdy_pulse_t *val)
617 {
618 lis3dhh_ctrl_reg1_t ctrl_reg1;
619 int32_t ret;
620
621 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
622
623 switch (ctrl_reg1.drdy_pulse)
624 {
625 case LIS3DHH_LATCHED:
626 *val = LIS3DHH_LATCHED;
627 break;
628
629 case LIS3DHH_PULSED:
630 *val = LIS3DHH_PULSED;
631 break;
632
633 default:
634 *val = LIS3DHH_LATCHED;
635 break;
636 }
637
638 return ret;
639 }
640
641 /**
642 * @brief It configures the INT1 pad as output for FIFO flags or as
643 * external asynchronous input trigger to FIFO.[set]
644 *
645 * @param ctx Read / write interface definitions.(ptr)
646 * @param val Change the values of int1_ext in reg INT1_CTRL
647 * @retval Interface status (MANDATORY: return 0 -> no Error).
648 *
649 */
lis3dhh_int1_mode_set(const stmdev_ctx_t * ctx,lis3dhh_int1_ext_t val)650 int32_t lis3dhh_int1_mode_set(const stmdev_ctx_t *ctx,
651 lis3dhh_int1_ext_t val)
652 {
653 lis3dhh_int1_ctrl_t int1_ctrl;
654 int32_t ret;
655
656 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
657
658 if (ret == 0)
659 {
660 int1_ctrl.int1_ext = (uint8_t)val;
661 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
662 }
663
664 return ret;
665 }
666
667 /**
668 * @brief It configures the INT1 pad as output for FIFO flags or as
669 * external asynchronous input trigger to FIFO.[get]
670 *
671 * @param ctx Read / write interface definitions.(ptr)
672 * @param val Get the values of int1_ext in reg INT1_CTRL.(ptr)
673 * @retval Interface status (MANDATORY: return 0 -> no Error).
674 *
675 */
lis3dhh_int1_mode_get(const stmdev_ctx_t * ctx,lis3dhh_int1_ext_t * val)676 int32_t lis3dhh_int1_mode_get(const stmdev_ctx_t *ctx,
677 lis3dhh_int1_ext_t *val)
678 {
679 lis3dhh_int1_ctrl_t int1_ctrl;
680 int32_t ret;
681
682 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
683
684 switch (int1_ctrl.int1_ext)
685 {
686 case LIS3DHH_PIN_AS_INTERRUPT:
687 *val = LIS3DHH_PIN_AS_INTERRUPT;
688 break;
689
690 case LIS3DHH_PIN_AS_TRIGGER:
691 *val = LIS3DHH_PIN_AS_TRIGGER;
692 break;
693
694 default:
695 *val = LIS3DHH_PIN_AS_INTERRUPT;
696 break;
697 }
698
699 return ret;
700 }
701
702 /**
703 * @brief FIFO watermark status on INT1 pin.[set]
704 *
705 * @param ctx Read / write interface definitions.(ptr)
706 * @param val Change the values of int1_fth in reg INT1_CTRL
707 * @retval Interface status (MANDATORY: return 0 -> no Error).
708 *
709 */
lis3dhh_fifo_threshold_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)710 int32_t lis3dhh_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx,
711 uint8_t val)
712 {
713 lis3dhh_int1_ctrl_t int1_ctrl;
714 int32_t ret;
715
716 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
717
718 if (ret == 0)
719 {
720 int1_ctrl.int1_fth = val;
721 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
722 }
723
724 return ret;
725 }
726
727 /**
728 * @brief FIFO watermark status on INT1 pin.[get]
729 *
730 * @param ctx Read / write interface definitions.(ptr)
731 * @param val Get the values of int1_fth in reg INT1_CTRL.(ptr)
732 * @retval Interface status (MANDATORY: return 0 -> no Error).
733 *
734 */
lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)735 int32_t lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx,
736 uint8_t *val)
737 {
738 lis3dhh_int1_ctrl_t int1_ctrl;
739 int32_t ret;
740
741 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
742 *val = int1_ctrl.int1_fth;
743
744 return ret;
745 }
746
747 /**
748 * @brief FIFO full flag on INT1 pin.[set]
749 *
750 * @param ctx Read / write interface definitions.(ptr)
751 * @param val Change the values of int1_fss5 in reg INT1_CTRL
752 * @retval Interface status (MANDATORY: return 0 -> no Error).
753 *
754 */
lis3dhh_fifo_full_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)755 int32_t lis3dhh_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
756 {
757 lis3dhh_int1_ctrl_t int1_ctrl;
758 int32_t ret;
759
760 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
761
762 if (ret == 0)
763 {
764 int1_ctrl.int1_fss5 = val;
765 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
766 }
767
768 return ret;
769 }
770
771 /**
772 * @brief FIFO full flag on INT1 pin.[get]
773 *
774 * @param ctx Read / write interface definitions.(ptr)
775 * @param val Get the values of int1_fss5 in reg INT1_CTRL.(ptr)
776 * @retval Interface status (MANDATORY: return 0 -> no Error).
777 *
778 */
lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)779 int32_t lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
780 {
781 lis3dhh_int1_ctrl_t int1_ctrl;
782 int32_t ret;
783
784 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
785 *val = int1_ctrl.int1_fss5;
786
787 return ret;
788 }
789
790 /**
791 * @brief FIFO overrun interrupt on INT1 pin.[set]
792 *
793 * @param ctx Read / write interface definitions.(ptr)
794 * @param val Change the values of int1_ovr in reg INT1_CTRL
795 * @retval Interface status (MANDATORY: return 0 -> no Error).
796 *
797 */
lis3dhh_fifo_ovr_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)798 int32_t lis3dhh_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
799 {
800 lis3dhh_int1_ctrl_t int1_ctrl;
801 int32_t ret;
802
803 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
804
805 if (ret == 0)
806 {
807 int1_ctrl.int1_ovr = val;
808 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
809 }
810
811 return ret;
812 }
813
814 /**
815 * @brief FIFO overrun interrupt on INT1 pin.[get]
816 *
817 * @param ctx Read / write interface definitions.(ptr)
818 * @param val Get the values of int1_ovr in reg INT1_CTRL.(ptr)
819 * @retval Interface status (MANDATORY: return 0 -> no Error).
820 *
821 */
lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)822 int32_t lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
823 {
824 lis3dhh_int1_ctrl_t int1_ctrl;
825 int32_t ret;
826
827 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
828 *val = int1_ctrl.int1_ovr;
829
830 return ret;
831 }
832
833 /**
834 * @brief BOOT status on INT1 pin.[set]
835 *
836 * @param ctx Read / write interface definitions.(ptr)
837 * @param val Change the values of int1_boot in reg INT1_CTRL
838 * @retval Interface status (MANDATORY: return 0 -> no Error).
839 *
840 */
lis3dhh_boot_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)841 int32_t lis3dhh_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
842 {
843 lis3dhh_int1_ctrl_t int1_ctrl;
844 int32_t ret;
845
846 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
847
848 if (ret == 0)
849 {
850 int1_ctrl.int1_boot = val;
851 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
852 }
853
854 return ret;
855 }
856
857 /**
858 * @brief BOOT status on INT1 pin.[get]
859 *
860 * @param ctx Read / write interface definitions.(ptr)
861 * @param val Get the values of int1_boot in reg INT1_CTRL.(ptr)
862 * @retval Interface status (MANDATORY: return 0 -> no Error).
863 *
864 */
lis3dhh_boot_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)865 int32_t lis3dhh_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
866 {
867 lis3dhh_int1_ctrl_t int1_ctrl;
868 int32_t ret;
869
870 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
871 *val = int1_ctrl.int1_boot;
872
873 return ret;
874 }
875
876 /**
877 * @brief Data-ready signal on INT1 pin.[set]
878 *
879 * @param ctx Read / write interface definitions.(ptr)
880 * @param val Change the values of int1_drdy in reg INT1_CTRL
881 * @retval Interface status (MANDATORY: return 0 -> no Error).
882 *
883 */
lis3dhh_drdy_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)884 int32_t lis3dhh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
885 {
886 lis3dhh_int1_ctrl_t int1_ctrl;
887 int32_t ret;
888
889 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
890
891 if (ret == 0)
892 {
893 int1_ctrl.int1_drdy = val;
894 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
895 }
896
897 return ret;
898 }
899
900 /**
901 * @brief Data-ready signal on INT1 pin.[get]
902 *
903 * @param ctx Read / write interface definitions.(ptr)
904 * @param val Get the values of int1_drdy in reg INT1_CTRL.(ptr)
905 * @retval Interface status (MANDATORY: return 0 -> no Error).
906 *
907 */
lis3dhh_drdy_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)908 int32_t lis3dhh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
909 {
910 lis3dhh_int1_ctrl_t int1_ctrl;
911 int32_t ret;
912
913 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
914 *val = int1_ctrl.int1_drdy;
915
916 return ret;
917 }
918
919 /**
920 * @brief FIFO watermark status on INT2 pin.[set]
921 *
922 * @param ctx Read / write interface definitions.(ptr)
923 * @param val Change the values of int2_fth in reg INT2_CTRL
924 * @retval Interface status (MANDATORY: return 0 -> no Error).
925 *
926 */
lis3dhh_fifo_threshold_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)927 int32_t lis3dhh_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx,
928 uint8_t val)
929 {
930 lis3dhh_int2_ctrl_t int2_ctrl;
931 int32_t ret;
932
933 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
934
935 if (ret == 0)
936 {
937 int2_ctrl.int2_fth = val;
938 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
939 }
940
941 return ret;
942 }
943
944 /**
945 * @brief FIFO watermark status on INT2 pin.[get]
946 *
947 * @param ctx Read / write interface definitions.(ptr)
948 * @param val Get the values of int2_fth in reg INT2_CTRL.(ptr)
949 * @retval Interface status (MANDATORY: return 0 -> no Error).
950 *
951 */
lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)952 int32_t lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx,
953 uint8_t *val)
954 {
955 lis3dhh_int2_ctrl_t int2_ctrl;
956 int32_t ret;
957
958 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
959 *val = int2_ctrl.int2_fth;
960
961 return ret;
962 }
963
964 /**
965 * @brief FIFO full flag on INT2 pin.[set]
966 *
967 * @param ctx Read / write interface definitions.(ptr)
968 * @param val Change the values of int2_fss5 in reg INT2_CTRL
969 * @retval Interface status (MANDATORY: return 0 -> no Error).
970 *
971 */
lis3dhh_fifo_full_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)972 int32_t lis3dhh_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
973 {
974 lis3dhh_int2_ctrl_t int2_ctrl;
975 int32_t ret;
976
977 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
978
979 if (ret == 0)
980 {
981 int2_ctrl.int2_fss5 = val;
982 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
983 }
984
985 return ret;
986 }
987
988 /**
989 * @brief FIFO full flag on INT2 pin.[get]
990 *
991 * @param ctx Read / write interface definitions.(ptr)
992 * @param val Get the values of int2_fss5 in reg INT2_CTRL.(ptr)
993 * @retval Interface status (MANDATORY: return 0 -> no Error).
994 *
995 */
lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)996 int32_t lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
997 {
998 lis3dhh_int2_ctrl_t int2_ctrl;
999 int32_t ret;
1000
1001 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1002 *val = int2_ctrl.int2_fss5;
1003
1004 return ret;
1005 }
1006
1007 /**
1008 * @brief FIFO overrun interrupt on INT2 pin.[set]
1009 *
1010 * @param ctx Read / write interface definitions.(ptr)
1011 * @param val Change the values of int2_ovr in reg INT2_CTRL
1012 * @retval Interface status (MANDATORY: return 0 -> no Error).
1013 *
1014 */
lis3dhh_fifo_ovr_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1015 int32_t lis3dhh_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1016 {
1017 lis3dhh_int2_ctrl_t int2_ctrl;
1018 int32_t ret;
1019
1020 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1021
1022 if (ret == 0)
1023 {
1024 int2_ctrl.int2_ovr = val;
1025 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1026 }
1027
1028 return ret;
1029 }
1030
1031 /**
1032 * @brief FIFO overrun interrupt on INT2 pin.[get]
1033 *
1034 * @param ctx Read / write interface definitions.(ptr)
1035 * @param val Get the values of int2_ovr in reg INT2_CTRL.(ptr)
1036 * @retval Interface status (MANDATORY: return 0 -> no Error).
1037 *
1038 */
lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1039 int32_t lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1040 {
1041 lis3dhh_int2_ctrl_t int2_ctrl;
1042 int32_t ret;
1043
1044 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1045 *val = int2_ctrl.int2_ovr;
1046
1047 return ret;
1048 }
1049
1050 /**
1051 * @brief BOOT status on INT2 pin.[set]
1052 *
1053 * @param ctx Read / write interface definitions.(ptr)
1054 * @param val Change the values of int2_boot in reg INT2_CTRL
1055 * @retval Interface status (MANDATORY: return 0 -> no Error).
1056 *
1057 */
lis3dhh_boot_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1058 int32_t lis3dhh_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1059 {
1060 lis3dhh_int2_ctrl_t int2_ctrl;
1061 int32_t ret;
1062
1063 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1064
1065 if (ret == 0)
1066 {
1067 int2_ctrl.int2_boot = val;
1068 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1069 }
1070
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief BOOT status on INT2 pin.[get]
1076 *
1077 * @param ctx Read / write interface definitions.(ptr)
1078 * @param val Get the values of int2_boot in reg INT2_CTRL.(ptr)
1079 * @retval Interface status (MANDATORY: return 0 -> no Error).
1080 *
1081 */
lis3dhh_boot_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1082 int32_t lis3dhh_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1083 {
1084 lis3dhh_int2_ctrl_t int2_ctrl;
1085 int32_t ret;
1086
1087 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1088 *val = int2_ctrl.int2_boot;
1089
1090 return ret;
1091 }
1092
1093 /**
1094 * @brief Data-ready signal on INT2 pin.[set]
1095 *
1096 * @param ctx Read / write interface definitions.(ptr)
1097 * @param val Change the values of int2_drdy in reg INT2_CTRL
1098 * @retval Interface status (MANDATORY: return 0 -> no Error).
1099 *
1100 */
lis3dhh_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)1101 int32_t lis3dhh_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
1102 {
1103 lis3dhh_int2_ctrl_t int2_ctrl;
1104 int32_t ret;
1105
1106 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1107
1108 if (ret == 0)
1109 {
1110 int2_ctrl.int2_drdy = val;
1111 ret = lis3dhh_write_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1112 }
1113
1114 return ret;
1115 }
1116
1117 /**
1118 * @brief Data-ready signal on INT2 pin.[get]
1119 *
1120 * @param ctx Read / write interface definitions.(ptr)
1121 * @param val Get the values of int2_drdy in reg INT2_CTRL.(ptr)
1122 * @retval Interface status (MANDATORY: return 0 -> no Error).
1123 *
1124 */
lis3dhh_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)1125 int32_t lis3dhh_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
1126 {
1127 lis3dhh_int2_ctrl_t int2_ctrl;
1128 int32_t ret;
1129
1130 ret = lis3dhh_read_reg(ctx, LIS3DHH_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
1131 *val = int2_ctrl.int2_drdy;
1132
1133 return ret;
1134 }
1135
1136 /**
1137 * @brief Push-pull/open drain selection on interrupt pads.[set]
1138 *
1139 * @param ctx Read / write interface definitions.(ptr)
1140 * @param val Change the values of pp_od in reg CTRL_REG4
1141 * @retval Interface status (MANDATORY: return 0 -> no Error).
1142 *
1143 */
lis3dhh_pin_mode_set(const stmdev_ctx_t * ctx,lis3dhh_pp_od_t val)1144 int32_t lis3dhh_pin_mode_set(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t val)
1145 {
1146 lis3dhh_ctrl_reg4_t ctrl_reg4;
1147 int32_t ret;
1148
1149 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1150
1151 if (ret == 0)
1152 {
1153 ctrl_reg4.pp_od = (uint8_t)val;
1154 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1155 }
1156
1157 return ret;
1158 }
1159
1160 /**
1161 * @brief Push-pull/open drain selection on interrupt pads.[get]
1162 *
1163 * @param ctx Read / write interface definitions.(ptr)
1164 * @param val Get the values of pp_od in reg CTRL_REG4.(ptr)
1165 * @retval Interface status (MANDATORY: return 0 -> no Error).
1166 *
1167 */
lis3dhh_pin_mode_get(const stmdev_ctx_t * ctx,lis3dhh_pp_od_t * val)1168 int32_t lis3dhh_pin_mode_get(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val)
1169 {
1170 lis3dhh_ctrl_reg4_t ctrl_reg4;
1171 int32_t ret;
1172
1173 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1174
1175 switch (ctrl_reg4.pp_od)
1176 {
1177 case LIS3DHH_ALL_PUSH_PULL:
1178 *val = LIS3DHH_ALL_PUSH_PULL;
1179 break;
1180
1181 case LIS3DHH_INT1_OD_INT2_PP:
1182 *val = LIS3DHH_INT1_OD_INT2_PP;
1183 break;
1184
1185 case LIS3DHH_INT1_PP_INT2_OD:
1186 *val = LIS3DHH_INT1_PP_INT2_OD;
1187 break;
1188
1189 case LIS3DHH_ALL_OPEN_DRAIN:
1190 *val = LIS3DHH_ALL_OPEN_DRAIN;
1191 break;
1192
1193 default:
1194 *val = LIS3DHH_ALL_PUSH_PULL;
1195 break;
1196 }
1197
1198 return ret;
1199 }
1200
1201 /**
1202 * @}
1203 *
1204 */
1205
1206 /**
1207 * @defgroup LIS3DHH_fifo
1208 * @brief This section group all the functions concerning the
1209 * fifo usage
1210 * @{
1211 *
1212 */
1213
1214 /**
1215 * @brief FIFOenable.[set]
1216 *
1217 * @param ctx Read / write interface definitions.(ptr)
1218 * @param val Change the values of fifo_en in reg CTRL_REG4
1219 * @retval Interface status (MANDATORY: return 0 -> no Error).
1220 *
1221 */
lis3dhh_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)1222 int32_t lis3dhh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
1223 {
1224 lis3dhh_ctrl_reg4_t ctrl_reg4;
1225 int32_t ret;
1226
1227 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1228
1229 if (ret == 0)
1230 {
1231 ctrl_reg4.fifo_en = val;
1232 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1233 }
1234
1235 return ret;
1236 }
1237
1238 /**
1239 * @brief FIFOenable.[get]
1240 *
1241 * @param ctx Read / write interface definitions.(ptr)
1242 * @param val Get the values of fifo_en in reg CTRL_REG4.(ptr)
1243 * @retval Interface status (MANDATORY: return 0 -> no Error).
1244 *
1245 */
lis3dhh_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)1246 int32_t lis3dhh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
1247 {
1248 lis3dhh_ctrl_reg4_t ctrl_reg4;
1249 int32_t ret;
1250
1251 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1252 *val = ctrl_reg4.fifo_en;
1253
1254 return ret;
1255 }
1256
1257 /**
1258 * @brief Enables the SPI high speed configuration for the FIFO block that
1259 is used to guarantee a minimum duration of the window in which
1260 writing operation of RAM output is blocked. This bit is recommended
1261 for SPI clock frequencies higher than 6 MHz.[set]
1262 *
1263 * @param ctx Read / write interface definitions.(ptr)
1264 * @param val Change the values of fifo_spi_hs_on in reg CTRL_REG5
1265 * @retval Interface status (MANDATORY: return 0 -> no Error).
1266 *
1267 */
lis3dhh_fifo_block_spi_hs_set(const stmdev_ctx_t * ctx,uint8_t val)1268 int32_t lis3dhh_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val)
1269 {
1270 lis3dhh_ctrl_reg5_t ctrl_reg5;
1271 int32_t ret;
1272
1273 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1274
1275 if (ret == 0)
1276 {
1277 ctrl_reg5.fifo_spi_hs_on = val;
1278 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1279 }
1280
1281 return ret;
1282 }
1283
1284 /**
1285 * @brief Enables the SPI high speed configuration for the FIFO block that
1286 is used to guarantee a minimum duration of the window in which
1287 writing operation of RAM output is blocked. This bit is recommended
1288 for SPI clock frequencies higher than 6 MHz.[get]
1289 *
1290 * @param ctx Read / write interface definitions.(ptr)
1291 * @param val Get the values of fifo_spi_hs_on in reg CTRL_REG5.(ptr)
1292 * @retval Interface status (MANDATORY: return 0 -> no Error).
1293 *
1294 */
lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t * ctx,uint8_t * val)1295 int32_t lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val)
1296 {
1297 lis3dhh_ctrl_reg5_t ctrl_reg5;
1298 int32_t ret;
1299
1300 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1301 *val = ctrl_reg5.fifo_spi_hs_on;
1302
1303 return ret;
1304 }
1305
1306 /**
1307 * @brief FIFO watermark level selection.[set]
1308 *
1309 * @param ctx Read / write interface definitions.(ptr)
1310 * @param val Change the values of fth in reg FIFO_CTRL
1311 * @retval Interface status (MANDATORY: return 0 -> no Error).
1312 *
1313 */
lis3dhh_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1314 int32_t lis3dhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1315 {
1316 lis3dhh_fifo_ctrl_t fifo_ctrl;
1317 int32_t ret;
1318
1319 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1320
1321 if (ret == 0)
1322 {
1323 fifo_ctrl.fth = val;
1324 ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1325 }
1326
1327 return ret;
1328 }
1329
1330 /**
1331 * @brief FIFO watermark level selection.[get]
1332 *
1333 * @param ctx Read / write interface definitions.(ptr)
1334 * @param val Get the values of fth in reg FIFO_CTRL.(ptr)
1335 * @retval Interface status (MANDATORY: return 0 -> no Error).
1336 *
1337 */
lis3dhh_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1338 int32_t lis3dhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1339 {
1340 lis3dhh_fifo_ctrl_t fifo_ctrl;
1341 int32_t ret;
1342
1343 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1344 *val = fifo_ctrl.fth;
1345
1346 return ret;
1347 }
1348
1349 /**
1350 * @brief FIFO mode selection.[set]
1351 *
1352 * @param ctx Read / write interface definitions.(ptr)
1353 * @param val Change the values of fmode in reg FIFO_CTRL
1354 * @retval Interface status (MANDATORY: return 0 -> no Error).
1355 *
1356 */
lis3dhh_fifo_mode_set(const stmdev_ctx_t * ctx,lis3dhh_fmode_t val)1357 int32_t lis3dhh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dhh_fmode_t val)
1358 {
1359 lis3dhh_fifo_ctrl_t fifo_ctrl;
1360 int32_t ret;
1361
1362 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1363
1364 if (ret == 0)
1365 {
1366 fifo_ctrl.fmode = (uint8_t)val;
1367 ret = lis3dhh_write_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1368 }
1369
1370 return ret;
1371 }
1372
1373 /**
1374 * @brief FIFO mode selection.[get]
1375 *
1376 * @param ctx Read / write interface definitions.(ptr)
1377 * @param val Get the values of fmode in reg FIFO_CTRL.(ptr)
1378 * @retval Interface status (MANDATORY: return 0 -> no Error).
1379 *
1380 */
lis3dhh_fifo_mode_get(const stmdev_ctx_t * ctx,lis3dhh_fmode_t * val)1381 int32_t lis3dhh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dhh_fmode_t *val)
1382 {
1383 lis3dhh_fifo_ctrl_t fifo_ctrl;
1384 int32_t ret;
1385
1386 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1387
1388 switch (fifo_ctrl.fmode)
1389 {
1390 case LIS3DHH_BYPASS_MODE:
1391 *val = LIS3DHH_BYPASS_MODE;
1392 break;
1393
1394 case LIS3DHH_FIFO_MODE:
1395 *val = LIS3DHH_FIFO_MODE;
1396 break;
1397
1398 case LIS3DHH_STREAM_TO_FIFO_MODE:
1399 *val = LIS3DHH_STREAM_TO_FIFO_MODE;
1400 break;
1401
1402 case LIS3DHH_BYPASS_TO_STREAM_MODE:
1403 *val = LIS3DHH_BYPASS_TO_STREAM_MODE;
1404 break;
1405
1406 case LIS3DHH_DYNAMIC_STREAM_MODE:
1407 *val = LIS3DHH_DYNAMIC_STREAM_MODE;
1408 break;
1409
1410 default:
1411 *val = LIS3DHH_BYPASS_MODE;
1412 break;
1413 }
1414
1415 return ret;
1416 }
1417
1418 /**
1419 * @brief FIFO status register.[get]
1420 *
1421 * @param ctx Read / write interface definitions.(ptr)
1422 * @param val Get registers FIFO_SRC.(ptr)
1423 * @retval Interface status (MANDATORY: return 0 -> no Error).
1424 *
1425 */
lis3dhh_fifo_status_get(const stmdev_ctx_t * ctx,lis3dhh_fifo_src_t * val)1426 int32_t lis3dhh_fifo_status_get(const stmdev_ctx_t *ctx,
1427 lis3dhh_fifo_src_t *val)
1428 {
1429 int32_t ret;
1430
1431 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *) val, 1);
1432
1433 return ret;
1434 }
1435
1436 /**
1437 * @brief FIFO stored data level.[get]
1438 *
1439 * @param ctx Read / write interface definitions.(ptr)
1440 * @param val Get the values of fss in reg FIFO_SRC.(ptr)
1441 * @retval Interface status (MANDATORY: return 0 -> no Error).
1442 *
1443 */
lis3dhh_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1444 int32_t lis3dhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1445 {
1446 lis3dhh_fifo_src_t fifo_src;
1447 int32_t ret;
1448
1449 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1450 *val = fifo_src.fss;
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief FIFO overrun status flag.[get]
1457 *
1458 * @param ctx Read / write interface definitions.(ptr)
1459 * @param val Get the values of ovrn in reg FIFO_SRC.(ptr)
1460 * @retval Interface status (MANDATORY: return 0 -> no Error).
1461 *
1462 */
lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1463 int32_t lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1464 {
1465 lis3dhh_fifo_src_t fifo_src;
1466 int32_t ret;
1467
1468 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1469 *val = fifo_src.ovrn;
1470
1471 return ret;
1472 }
1473
1474 /**
1475 * @brief FIFO watermark status.[get]
1476 *
1477 * @param ctx Read / write interface definitions.(ptr)
1478 * @param val Get the values of fth in reg FIFO_SRC.(ptr)
1479 * @retval Interface status (MANDATORY: return 0 -> no Error).
1480 *
1481 */
lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1482 int32_t lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1483 {
1484 lis3dhh_fifo_src_t fifo_src;
1485 int32_t ret;
1486
1487 ret = lis3dhh_read_reg(ctx, LIS3DHH_FIFO_SRC, (uint8_t *)&fifo_src, 1);
1488 *val = fifo_src.fth;
1489
1490 return ret;
1491 }
1492
1493 /**
1494 * @}
1495 *
1496 */
1497
1498 /**
1499 * @defgroup LIS3DHH_serial_interface
1500 * @brief This section group all the functions concerning serial
1501 * interface management
1502 * @{
1503 *
1504 */
1505
1506 /**
1507 * @brief Register address automatically incremented during a multiple byte
1508 * access with a serial interface (I2C or SPI).[set]
1509 *
1510 * @param ctx Read / write interface definitions.(ptr)
1511 * @param val Change the values of if_add_inc in reg CTRL_REG1
1512 * @retval Interface status (MANDATORY: return 0 -> no Error).
1513 *
1514 */
lis3dhh_auto_add_inc_set(const stmdev_ctx_t * ctx,uint8_t val)1515 int32_t lis3dhh_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val)
1516 {
1517 lis3dhh_ctrl_reg1_t ctrl_reg1;
1518 int32_t ret;
1519
1520 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
1521
1522 if (ret == 0)
1523 {
1524 ctrl_reg1.if_add_inc = val;
1525 ret = lis3dhh_write_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
1526 }
1527
1528 return ret;
1529 }
1530
1531 /**
1532 * @brief Register address automatically incremented during a multiple byte
1533 * access with a serial interface (I2C or SPI).[get]
1534 *
1535 * @param ctx Read / write interface definitions.(ptr)
1536 * @param val Get the values of if_add_inc in reg CTRL_REG1.(ptr)
1537 * @retval Interface status (MANDATORY: return 0 -> no Error).
1538 *
1539 */
lis3dhh_auto_add_inc_get(const stmdev_ctx_t * ctx,uint8_t * val)1540 int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val)
1541 {
1542 lis3dhh_ctrl_reg1_t ctrl_reg1;
1543 int32_t ret;
1544
1545 ret = lis3dhh_read_reg(ctx, LIS3DHH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
1546 *val = ctrl_reg1.if_add_inc;
1547
1548 return ret;
1549 }
1550
1551 /**
1552 * @}
1553 *
1554 */
1555
1556 /**
1557 * @}
1558 *
1559 */
1560
1561 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1562
