1 /**
2 ******************************************************************************
3 * @file lis3dh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS3DH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis3dh_reg.h"
21
22 /**
23 * @defgroup LIS3DH
24 * @brief This file provides a set of functions needed to drive the
25 * lis3dh enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS3DH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis3dh_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis3dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
lis3dh_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak lis3dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
75 uint8_t *data,
76 uint16_t len)
77 {
78 int32_t ret;
79
80 if (ctx == NULL)
81 {
82 return -1;
83 }
84
85 ret = ctx->write_reg(ctx->handle, reg, data, len);
86
87 return ret;
88 }
89
90 /**
91 * @}
92 *
93 */
94
95 /**
96 * @defgroup LIS3DH_Sensitivity
97 * @brief These functions convert raw-data into engineering units.
98 * @{
99 *
100 */
101
lis3dh_from_fs2_hr_to_mg(int16_t lsb)102 float_t lis3dh_from_fs2_hr_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb / 16.0f) * 1.0f;
105 }
106
lis3dh_from_fs4_hr_to_mg(int16_t lsb)107 float_t lis3dh_from_fs4_hr_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb / 16.0f) * 2.0f;
110 }
111
lis3dh_from_fs8_hr_to_mg(int16_t lsb)112 float_t lis3dh_from_fs8_hr_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb / 16.0f) * 4.0f;
115 }
116
lis3dh_from_fs16_hr_to_mg(int16_t lsb)117 float_t lis3dh_from_fs16_hr_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb / 16.0f) * 12.0f;
120 }
121
lis3dh_from_lsb_hr_to_celsius(int16_t lsb)122 float_t lis3dh_from_lsb_hr_to_celsius(int16_t lsb)
123 {
124 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
125 }
126
lis3dh_from_fs2_nm_to_mg(int16_t lsb)127 float_t lis3dh_from_fs2_nm_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb / 64.0f) * 4.0f;
130 }
131
lis3dh_from_fs4_nm_to_mg(int16_t lsb)132 float_t lis3dh_from_fs4_nm_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb / 64.0f) * 8.0f;
135 }
136
lis3dh_from_fs8_nm_to_mg(int16_t lsb)137 float_t lis3dh_from_fs8_nm_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb / 64.0f) * 16.0f;
140 }
141
lis3dh_from_fs16_nm_to_mg(int16_t lsb)142 float_t lis3dh_from_fs16_nm_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb / 64.0f) * 48.0f;
145 }
146
lis3dh_from_lsb_nm_to_celsius(int16_t lsb)147 float_t lis3dh_from_lsb_nm_to_celsius(int16_t lsb)
148 {
149 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
150 }
151
lis3dh_from_fs2_lp_to_mg(int16_t lsb)152 float_t lis3dh_from_fs2_lp_to_mg(int16_t lsb)
153 {
154 return ((float_t)lsb / 256.0f) * 16.0f;
155 }
156
lis3dh_from_fs4_lp_to_mg(int16_t lsb)157 float_t lis3dh_from_fs4_lp_to_mg(int16_t lsb)
158 {
159 return ((float_t)lsb / 256.0f) * 32.0f;
160 }
161
lis3dh_from_fs8_lp_to_mg(int16_t lsb)162 float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb)
163 {
164 return ((float_t)lsb / 256.0f) * 64.0f;
165 }
166
lis3dh_from_fs16_lp_to_mg(int16_t lsb)167 float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb)
168 {
169 return ((float_t)lsb / 256.0f) * 192.0f;
170 }
171
lis3dh_from_lsb_lp_to_celsius(int16_t lsb)172 float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb)
173 {
174 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
175 }
176
177 /**
178 * @}
179 *
180 */
181
182 /**
183 * @defgroup LIS3DH_Data_generation
184 * @brief This section group all the functions concerning data generation.
185 * @{
186 *
187 */
188
189 /**
190 * @brief Temperature status register.[get]
191 *
192 * @param ctx read / write interface definitions
193 * @param buff buffer that stores data read
194 * @retval interface status (MANDATORY: return 0 -> no Error)
195 *
196 */
lis3dh_temp_status_reg_get(const stmdev_ctx_t * ctx,uint8_t * buff)197 int32_t lis3dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff)
198 {
199 int32_t ret;
200
201 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX, buff, 1);
202
203 return ret;
204 }
205 /**
206 * @brief Temperature data available.[get]
207 *
208 * @param ctx read / write interface definitions
209 * @param val change the values of tda in reg STATUS_REG_AUX
210 * @retval interface status (MANDATORY: return 0 -> no Error)
211 *
212 */
lis3dh_temp_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)213 int32_t lis3dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
214 {
215 lis3dh_status_reg_aux_t status_reg_aux;
216 int32_t ret;
217
218 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
219 (uint8_t *)&status_reg_aux, 1);
220 *val = status_reg_aux._3da;
221
222 return ret;
223 }
224 /**
225 * @brief Temperature data overrun.[get]
226 *
227 * @param ctx read / write interface definitions
228 * @param val change the values of tor in reg STATUS_REG_AUX
229 * @retval interface status (MANDATORY: return 0 -> no Error)
230 *
231 */
lis3dh_temp_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)232 int32_t lis3dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
233 {
234 lis3dh_status_reg_aux_t status_reg_aux;
235 int32_t ret;
236
237 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG_AUX,
238 (uint8_t *)&status_reg_aux, 1);
239 *val = status_reg_aux._3or;
240
241 return ret;
242 }
243 /**
244 * @brief Temperature output value.[get]
245 *
246 * @param ctx read / write interface definitions
247 * @param buff buffer that stores data read
248 * @retval interface status (MANDATORY: return 0 -> no Error)
249 *
250 */
lis3dh_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)251 int32_t lis3dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
252 {
253 uint8_t buff[2];
254 int32_t ret;
255
256 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC3_L, buff, 2);
257 *val = (int16_t)buff[1];
258 *val = (*val * 256) + (int16_t)buff[0];
259
260 return ret;
261 }
262
263 /**
264 * @brief ADC output value.[get]
265 * Sample frequency: the same as the ODR CTRL_REG1
266 * The resolution:
267 * 10bit if LPen bit in CTRL_REG1 (20h) is clear
268 * 8bit if LPen bit in CTRL_REG1 (20h) is set
269 * Data Format:
270 * Outputs are Left Justified in 2’ complements
271 * range 800mV
272 * code zero means an analogue value of about 1.2V
273 * Voltage values smaller than centre values are positive
274 * (Example: 800mV = 7Fh / 127 dec)
275 * Voltage values bigger than centre values are negative
276 * (Example: 1600mV = 80h / -128 dec)
277 *
278 * @param ctx read / write interface definitions
279 * @param buff buffer that stores data read
280 * @retval interface status (MANDATORY: return 0 -> no Error)
281 *
282 */
lis3dh_adc_raw_get(const stmdev_ctx_t * ctx,int16_t * val)283 int32_t lis3dh_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
284 {
285 uint8_t buff[6];
286 int32_t ret;
287
288 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_ADC1_L, buff, 6);
289 val[0] = (int16_t)buff[1];
290 val[0] = (val[0] * 256) + (int16_t)buff[0];
291 val[1] = (int16_t)buff[3];
292 val[1] = (val[1] * 256) + (int16_t)buff[2];
293 val[2] = (int16_t)buff[5];
294 val[2] = (val[2] * 256) + (int16_t)buff[4];
295
296 return ret;
297 }
298
299 /**
300 * @brief Auxiliary ADC.[set]
301 *
302 * @param ctx read / write interface definitions
303 * @param val configure the auxiliary ADC
304 * @retval interface status (MANDATORY: return 0 -> no Error)
305 *
306 */
lis3dh_aux_adc_set(const stmdev_ctx_t * ctx,lis3dh_temp_en_t val)307 int32_t lis3dh_aux_adc_set(const stmdev_ctx_t *ctx, lis3dh_temp_en_t val)
308 {
309 lis3dh_temp_cfg_reg_t temp_cfg_reg;
310 int32_t ret;
311
312 ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
313 (uint8_t *)&temp_cfg_reg, 1);
314
315 if (ret == 0)
316 {
317 if (val != LIS3DH_AUX_DISABLE)
318 {
319 /* Required in order to use auxiliary adc */
320 ret = lis3dh_block_data_update_set(ctx, PROPERTY_ENABLE);
321 }
322 }
323
324 if (ret == 0)
325 {
326 temp_cfg_reg.temp_en = ((uint8_t) val & 0x02U) >> 1;
327 temp_cfg_reg.adc_pd = (uint8_t) val & 0x01U;
328 ret = lis3dh_write_reg(ctx, LIS3DH_TEMP_CFG_REG,
329 (uint8_t *)&temp_cfg_reg, 1);
330 }
331
332 return ret;
333 }
334
335 /**
336 * @brief Auxiliary ADC.[get]
337 *
338 * @param ctx read / write interface definitions
339 * @param val configure the auxiliary ADC
340 * @retval interface status (MANDATORY: return 0 -> no Error)
341 *
342 */
lis3dh_aux_adc_get(const stmdev_ctx_t * ctx,lis3dh_temp_en_t * val)343 int32_t lis3dh_aux_adc_get(const stmdev_ctx_t *ctx, lis3dh_temp_en_t *val)
344 {
345 lis3dh_temp_cfg_reg_t temp_cfg_reg;
346 int32_t ret;
347
348 ret = lis3dh_read_reg(ctx, LIS3DH_TEMP_CFG_REG,
349 (uint8_t *)&temp_cfg_reg, 1);
350
351 if ((temp_cfg_reg.temp_en & temp_cfg_reg.adc_pd) ==
352 PROPERTY_ENABLE)
353 {
354 *val = LIS3DH_AUX_ON_TEMPERATURE;
355 }
356
357 if ((temp_cfg_reg.temp_en == PROPERTY_DISABLE) &&
358 (temp_cfg_reg.adc_pd == PROPERTY_ENABLE))
359 {
360 *val = LIS3DH_AUX_ON_PADS;
361 }
362
363 else
364 {
365 *val = LIS3DH_AUX_DISABLE;
366 }
367
368 return ret;
369 }
370
371 /**
372 * @brief Operating mode selection.[set]
373 *
374 * @param ctx read / write interface definitions
375 * @param val change the values of lpen in reg CTRL_REG1
376 * and HR in reg CTRL_REG4
377 * @retval interface status (MANDATORY: return 0 -> no Error)
378 *
379 */
lis3dh_operating_mode_set(const stmdev_ctx_t * ctx,lis3dh_op_md_t val)380 int32_t lis3dh_operating_mode_set(const stmdev_ctx_t *ctx,
381 lis3dh_op_md_t val)
382 {
383 lis3dh_ctrl_reg1_t ctrl_reg1;
384 lis3dh_ctrl_reg4_t ctrl_reg4;
385 int32_t ret;
386
387 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1,
388 (uint8_t *)&ctrl_reg1, 1);
389
390 if (ret == 0)
391 {
392 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4,
393 (uint8_t *)&ctrl_reg4, 1);
394 }
395
396 if (ret == 0)
397 {
398 if (val == LIS3DH_HR_12bit)
399 {
400 ctrl_reg1.lpen = 0;
401 ctrl_reg4.hr = 1;
402 }
403
404 if (val == LIS3DH_NM_10bit)
405 {
406 ctrl_reg1.lpen = 0;
407 ctrl_reg4.hr = 0;
408 }
409
410 if (val == LIS3DH_LP_8bit)
411 {
412 ctrl_reg1.lpen = 1;
413 ctrl_reg4.hr = 0;
414 }
415
416 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
417 }
418
419 if (ret == 0)
420 {
421 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
422 }
423
424 return ret;
425 }
426
427 /**
428 * @brief Operating mode selection.[get]
429 *
430 * @param ctx read / write interface definitions
431 * @param val change the values of lpen in reg CTRL_REG1
432 * @retval interface status (MANDATORY: return 0 -> no Error)
433 *
434 */
lis3dh_operating_mode_get(const stmdev_ctx_t * ctx,lis3dh_op_md_t * val)435 int32_t lis3dh_operating_mode_get(const stmdev_ctx_t *ctx,
436 lis3dh_op_md_t *val)
437 {
438 lis3dh_ctrl_reg1_t ctrl_reg1;
439 lis3dh_ctrl_reg4_t ctrl_reg4;
440 int32_t ret;
441
442 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
443
444 if (ret == 0)
445 {
446 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
447
448 if (ctrl_reg1.lpen == PROPERTY_ENABLE)
449 {
450 *val = LIS3DH_LP_8bit;
451 }
452
453 else if (ctrl_reg4.hr == PROPERTY_ENABLE)
454 {
455 *val = LIS3DH_HR_12bit;
456 }
457
458 else
459 {
460 *val = LIS3DH_NM_10bit;
461 }
462 }
463
464 return ret;
465 }
466
467 /**
468 * @brief Output data rate selection.[set]
469 *
470 * @param ctx read / write interface definitions
471 * @param val change the values of odr in reg CTRL_REG1
472 * @retval interface status (MANDATORY: return 0 -> no Error)
473 *
474 */
lis3dh_data_rate_set(const stmdev_ctx_t * ctx,lis3dh_odr_t val)475 int32_t lis3dh_data_rate_set(const stmdev_ctx_t *ctx, lis3dh_odr_t val)
476 {
477 lis3dh_ctrl_reg1_t ctrl_reg1;
478 int32_t ret;
479
480 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
481
482 if (ret == 0)
483 {
484 ctrl_reg1.odr = (uint8_t)val;
485 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
486 }
487
488 return ret;
489 }
490
491 /**
492 * @brief Output data rate selection.[get]
493 *
494 * @param ctx read / write interface definitions
495 * @param val get the values of odr in reg CTRL_REG1
496 * @retval interface status (MANDATORY: return 0 -> no Error)
497 *
498 */
lis3dh_data_rate_get(const stmdev_ctx_t * ctx,lis3dh_odr_t * val)499 int32_t lis3dh_data_rate_get(const stmdev_ctx_t *ctx, lis3dh_odr_t *val)
500 {
501 lis3dh_ctrl_reg1_t ctrl_reg1;
502 int32_t ret;
503
504 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
505
506 switch (ctrl_reg1.odr)
507 {
508 case LIS3DH_POWER_DOWN:
509 *val = LIS3DH_POWER_DOWN;
510 break;
511
512 case LIS3DH_ODR_1Hz:
513 *val = LIS3DH_ODR_1Hz;
514 break;
515
516 case LIS3DH_ODR_10Hz:
517 *val = LIS3DH_ODR_10Hz;
518 break;
519
520 case LIS3DH_ODR_25Hz:
521 *val = LIS3DH_ODR_25Hz;
522 break;
523
524 case LIS3DH_ODR_50Hz:
525 *val = LIS3DH_ODR_50Hz;
526 break;
527
528 case LIS3DH_ODR_100Hz:
529 *val = LIS3DH_ODR_100Hz;
530 break;
531
532 case LIS3DH_ODR_200Hz:
533 *val = LIS3DH_ODR_200Hz;
534 break;
535
536 case LIS3DH_ODR_400Hz:
537 *val = LIS3DH_ODR_400Hz;
538 break;
539
540 case LIS3DH_ODR_1kHz620_LP:
541 *val = LIS3DH_ODR_1kHz620_LP;
542 break;
543
544 case LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP:
545 *val = LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP;
546 break;
547
548 default:
549 *val = LIS3DH_POWER_DOWN;
550 break;
551 }
552
553 return ret;
554 }
555
556 /**
557 * @brief High pass data from internal filter sent to output register
558 * and FIFO.
559 *
560 * @param ctx read / write interface definitions
561 * @param val change the values of fds in reg CTRL_REG2
562 * @retval interface status (MANDATORY: return 0 -> no Error)
563 *
564 */
lis3dh_high_pass_on_outputs_set(const stmdev_ctx_t * ctx,uint8_t val)565 int32_t lis3dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx,
566 uint8_t val)
567 {
568 lis3dh_ctrl_reg2_t ctrl_reg2;
569 int32_t ret;
570
571 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
572
573 if (ret == 0)
574 {
575 ctrl_reg2.fds = val;
576 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
577 }
578
579 return ret;
580 }
581
582 /**
583 * @brief High pass data from internal filter sent to output register
584 * and FIFO.[get]
585 *
586 * @param ctx read / write interface definitions
587 * @param val change the values of fds in reg CTRL_REG2
588 * @retval interface status (MANDATORY: return 0 -> no Error)
589 *
590 */
lis3dh_high_pass_on_outputs_get(const stmdev_ctx_t * ctx,uint8_t * val)591 int32_t lis3dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx,
592 uint8_t *val)
593 {
594 lis3dh_ctrl_reg2_t ctrl_reg2;
595 int32_t ret;
596
597 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
598 *val = (uint8_t)ctrl_reg2.fds;
599
600 return ret;
601 }
602
603 /**
604 * @brief High-pass filter cutoff frequency selection.[set]
605 *
606 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
607 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
608 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
609 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
610 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
611 *
612 * @param ctx read / write interface definitions
613 * @param val change the values of hpcf in reg CTRL_REG2
614 * @retval interface status (MANDATORY: return 0 -> no Error)
615 *
616 */
lis3dh_high_pass_bandwidth_set(const stmdev_ctx_t * ctx,lis3dh_hpcf_t val)617 int32_t lis3dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx,
618 lis3dh_hpcf_t val)
619 {
620 lis3dh_ctrl_reg2_t ctrl_reg2;
621 int32_t ret;
622
623 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
624
625 if (ret == 0)
626 {
627 ctrl_reg2.hpcf = (uint8_t)val;
628 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
629 }
630
631 return ret;
632 }
633
634 /**
635 * @brief High-pass filter cutoff frequency selection.[get]
636 *
637 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
638 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
639 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
640 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
641 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
642 *
643 * @param ctx read / write interface definitions
644 * @param val get the values of hpcf in reg CTRL_REG2
645 * @retval interface status (MANDATORY: return 0 -> no Error)
646 *
647 */
lis3dh_high_pass_bandwidth_get(const stmdev_ctx_t * ctx,lis3dh_hpcf_t * val)648 int32_t lis3dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx,
649 lis3dh_hpcf_t *val)
650 {
651 lis3dh_ctrl_reg2_t ctrl_reg2;
652 int32_t ret;
653
654 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
655
656 switch (ctrl_reg2.hpcf)
657 {
658 case LIS3DH_AGGRESSIVE:
659 *val = LIS3DH_AGGRESSIVE;
660 break;
661
662 case LIS3DH_STRONG:
663 *val = LIS3DH_STRONG;
664 break;
665
666 case LIS3DH_MEDIUM:
667 *val = LIS3DH_MEDIUM;
668 break;
669
670 case LIS3DH_LIGHT:
671 *val = LIS3DH_LIGHT;
672 break;
673
674 default:
675 *val = LIS3DH_LIGHT;
676 break;
677 }
678
679 return ret;
680 }
681
682 /**
683 * @brief High-pass filter mode selection.[set]
684 *
685 * @param ctx read / write interface definitions
686 * @param val change the values of hpm in reg CTRL_REG2
687 * @retval interface status (MANDATORY: return 0 -> no Error)
688 *
689 */
lis3dh_high_pass_mode_set(const stmdev_ctx_t * ctx,lis3dh_hpm_t val)690 int32_t lis3dh_high_pass_mode_set(const stmdev_ctx_t *ctx, lis3dh_hpm_t val)
691 {
692 lis3dh_ctrl_reg2_t ctrl_reg2;
693 int32_t ret;
694
695 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
696
697 if (ret == 0)
698 {
699 ctrl_reg2.hpm = (uint8_t)val;
700 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
701 }
702
703 return ret;
704 }
705
706 /**
707 * @brief High-pass filter mode selection.[get]
708 *
709 * @param ctx read / write interface definitions
710 * @param val get the values of hpm in reg CTRL_REG2
711 * @retval interface status (MANDATORY: return 0 -> no Error)
712 *
713 */
lis3dh_high_pass_mode_get(const stmdev_ctx_t * ctx,lis3dh_hpm_t * val)714 int32_t lis3dh_high_pass_mode_get(const stmdev_ctx_t *ctx,
715 lis3dh_hpm_t *val)
716 {
717 lis3dh_ctrl_reg2_t ctrl_reg2;
718 int32_t ret;
719
720 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
721
722 switch (ctrl_reg2.hpm)
723 {
724 case LIS3DH_NORMAL_WITH_RST:
725 *val = LIS3DH_NORMAL_WITH_RST;
726 break;
727
728 case LIS3DH_REFERENCE_MODE:
729 *val = LIS3DH_REFERENCE_MODE;
730 break;
731
732 case LIS3DH_NORMAL:
733 *val = LIS3DH_NORMAL;
734 break;
735
736 case LIS3DH_AUTORST_ON_INT:
737 *val = LIS3DH_AUTORST_ON_INT;
738 break;
739
740 default:
741 *val = LIS3DH_NORMAL_WITH_RST;
742 break;
743 }
744
745 return ret;
746 }
747
748 /**
749 * @brief Full-scale configuration.[set]
750 *
751 * @param ctx read / write interface definitions
752 * @param val change the values of fs in reg CTRL_REG4
753 * @retval interface status (MANDATORY: return 0 -> no Error)
754 *
755 */
lis3dh_full_scale_set(const stmdev_ctx_t * ctx,lis3dh_fs_t val)756 int32_t lis3dh_full_scale_set(const stmdev_ctx_t *ctx, lis3dh_fs_t val)
757 {
758 lis3dh_ctrl_reg4_t ctrl_reg4;
759 int32_t ret;
760
761 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
762
763 if (ret == 0)
764 {
765 ctrl_reg4.fs = (uint8_t)val;
766 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
767 }
768
769 return ret;
770 }
771
772 /**
773 * @brief Full-scale configuration.[get]
774 *
775 * @param ctx read / write interface definitions
776 * @param val get the values of fs in reg CTRL_REG4
777 * @retval interface status (MANDATORY: return 0 -> no Error)
778 *
779 */
lis3dh_full_scale_get(const stmdev_ctx_t * ctx,lis3dh_fs_t * val)780 int32_t lis3dh_full_scale_get(const stmdev_ctx_t *ctx, lis3dh_fs_t *val)
781 {
782 lis3dh_ctrl_reg4_t ctrl_reg4;
783 int32_t ret;
784
785 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
786
787 switch (ctrl_reg4.fs)
788 {
789 case LIS3DH_2g:
790 *val = LIS3DH_2g;
791 break;
792
793 case LIS3DH_4g:
794 *val = LIS3DH_4g;
795 break;
796
797 case LIS3DH_8g:
798 *val = LIS3DH_8g;
799 break;
800
801 case LIS3DH_16g:
802 *val = LIS3DH_16g;
803 break;
804
805 default:
806 *val = LIS3DH_2g;
807 break;
808 }
809
810 return ret;
811 }
812
813 /**
814 * @brief Block Data Update.[set]
815 *
816 * @param ctx read / write interface definitions
817 * @param val change the values of bdu in reg CTRL_REG4
818 * @retval interface status (MANDATORY: return 0 -> no Error)
819 *
820 */
lis3dh_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)821 int32_t lis3dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
822 {
823 lis3dh_ctrl_reg4_t ctrl_reg4;
824 int32_t ret;
825
826 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
827
828 if (ret == 0)
829 {
830 ctrl_reg4.bdu = val;
831 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
832 }
833
834 return ret;
835 }
836
837 /**
838 * @brief Block Data Update.[get]
839 *
840 * @param ctx read / write interface definitions
841 * @param val change the values of bdu in reg CTRL_REG4
842 * @retval interface status (MANDATORY: return 0 -> no Error)
843 *
844 */
lis3dh_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)845 int32_t lis3dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
846 {
847 lis3dh_ctrl_reg4_t ctrl_reg4;
848 int32_t ret;
849
850 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
851 *val = (uint8_t)ctrl_reg4.bdu;
852
853 return ret;
854 }
855
856 /**
857 * @brief Reference value for interrupt generation.[set]
858 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
859 *
860 * @param ctx read / write interface definitions
861 * @param buff buffer that contains data to write
862 * @retval interface status (MANDATORY: return 0 -> no Error)
863 *
864 */
lis3dh_filter_reference_set(const stmdev_ctx_t * ctx,uint8_t * buff)865 int32_t lis3dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff)
866 {
867 int32_t ret;
868
869 ret = lis3dh_write_reg(ctx, LIS3DH_REFERENCE, buff, 1);
870
871 return ret;
872 }
873
874 /**
875 * @brief Reference value for interrupt generation.[get]
876 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
877 *
878 * @param ctx read / write interface definitions
879 * @param buff buffer that stores data read
880 * @retval interface status (MANDATORY: return 0 -> no Error)
881 *
882 */
lis3dh_filter_reference_get(const stmdev_ctx_t * ctx,uint8_t * buff)883 int32_t lis3dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff)
884 {
885 int32_t ret;
886
887 ret = lis3dh_read_reg(ctx, LIS3DH_REFERENCE, buff, 1);
888
889 return ret;
890 }
891 /**
892 * @brief Acceleration set of data available.[get]
893 *
894 * @param ctx read / write interface definitions
895 * @param val change the values of zyxda in reg STATUS_REG
896 * @retval interface status (MANDATORY: return 0 -> no Error)
897 *
898 */
lis3dh_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)899 int32_t lis3dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
900 {
901 lis3dh_status_reg_t status_reg;
902 int32_t ret;
903
904 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
905 *val = status_reg.zyxda;
906
907 return ret;
908 }
909 /**
910 * @brief Acceleration set of data overrun.[get]
911 *
912 * @param ctx read / write interface definitions
913 * @param val change the values of zyxor in reg STATUS_REG
914 * @retval interface status (MANDATORY: return 0 -> no Error)
915 *
916 */
lis3dh_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)917 int32_t lis3dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
918 {
919 lis3dh_status_reg_t status_reg;
920 int32_t ret;
921
922 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *)&status_reg, 1);
923 *val = status_reg.zyxor;
924
925 return ret;
926 }
927 /**
928 * @brief Acceleration output value.[get]
929 *
930 * @param ctx read / write interface definitions
931 * @param buff buffer that stores data read
932 * @retval interface status (MANDATORY: return 0 -> no Error)
933 *
934 */
lis3dh_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)935 int32_t lis3dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
936 {
937 uint8_t buff[6];
938 int32_t ret;
939
940 ret = lis3dh_read_reg(ctx, LIS3DH_OUT_X_L, buff, 6);
941 val[0] = (int16_t)buff[1];
942 val[0] = (val[0] * 256) + (int16_t)buff[0];
943 val[1] = (int16_t)buff[3];
944 val[1] = (val[1] * 256) + (int16_t)buff[2];
945 val[2] = (int16_t)buff[5];
946 val[2] = (val[2] * 256) + (int16_t)buff[4];
947
948 return ret;
949 }
950 /**
951 * @}
952 *
953 */
954
955 /**
956 * @defgroup LIS3DH_Common
957 * @brief This section group common useful functions
958 * @{
959 *
960 */
961
962 /**
963 * @brief DeviceWhoamI .[get]
964 *
965 * @param ctx read / write interface definitions
966 * @param buff buffer that stores data read
967 * @retval interface status (MANDATORY: return 0 -> no Error)
968 *
969 */
lis3dh_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)970 int32_t lis3dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
971 {
972 int32_t ret;
973
974 ret = lis3dh_read_reg(ctx, LIS3DH_WHO_AM_I, buff, 1);
975
976 return ret;
977 }
978 /**
979 * @brief Self Test.[set]
980 *
981 * @param ctx read / write interface definitions
982 * @param val change the values of st in reg CTRL_REG4
983 * @retval interface status (MANDATORY: return 0 -> no Error)
984 *
985 */
lis3dh_self_test_set(const stmdev_ctx_t * ctx,lis3dh_st_t val)986 int32_t lis3dh_self_test_set(const stmdev_ctx_t *ctx, lis3dh_st_t val)
987 {
988 lis3dh_ctrl_reg4_t ctrl_reg4;
989 int32_t ret;
990
991 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
992
993 if (ret == 0)
994 {
995 ctrl_reg4.st = (uint8_t)val;
996 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
997 }
998
999 return ret;
1000 }
1001
1002 /**
1003 * @brief Self Test.[get]
1004 *
1005 * @param ctx read / write interface definitions
1006 * @param val Get the values of st in reg CTRL_REG4
1007 * @retval interface status (MANDATORY: return 0 -> no Error)
1008 *
1009 */
lis3dh_self_test_get(const stmdev_ctx_t * ctx,lis3dh_st_t * val)1010 int32_t lis3dh_self_test_get(const stmdev_ctx_t *ctx, lis3dh_st_t *val)
1011 {
1012 lis3dh_ctrl_reg4_t ctrl_reg4;
1013 int32_t ret;
1014
1015 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1016
1017 switch (ctrl_reg4.st)
1018 {
1019 case LIS3DH_ST_DISABLE:
1020 *val = LIS3DH_ST_DISABLE;
1021 break;
1022
1023 case LIS3DH_ST_POSITIVE:
1024 *val = LIS3DH_ST_POSITIVE;
1025 break;
1026
1027 case LIS3DH_ST_NEGATIVE:
1028 *val = LIS3DH_ST_NEGATIVE;
1029 break;
1030
1031 default:
1032 *val = LIS3DH_ST_DISABLE;
1033 break;
1034 }
1035
1036 return ret;
1037 }
1038
1039 /**
1040 * @brief Big/Little Endian data selection.[set]
1041 *
1042 * @param ctx read / write interface definitions
1043 * @param val change the values of ble in reg CTRL_REG4
1044 * @retval interface status (MANDATORY: return 0 -> no Error)
1045 *
1046 */
lis3dh_data_format_set(const stmdev_ctx_t * ctx,lis3dh_ble_t val)1047 int32_t lis3dh_data_format_set(const stmdev_ctx_t *ctx, lis3dh_ble_t val)
1048 {
1049 lis3dh_ctrl_reg4_t ctrl_reg4;
1050 int32_t ret;
1051
1052 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1053
1054 if (ret == 0)
1055 {
1056 ctrl_reg4.ble = (uint8_t)val;
1057 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1058 }
1059
1060 return ret;
1061 }
1062
1063 /**
1064 * @brief Big/Little Endian data selection.[get]
1065 *
1066 * @param ctx read / write interface definitions
1067 * @param val get the values of ble in reg CTRL_REG4
1068 * @retval interface status (MANDATORY: return 0 -> no Error)
1069 *
1070 */
lis3dh_data_format_get(const stmdev_ctx_t * ctx,lis3dh_ble_t * val)1071 int32_t lis3dh_data_format_get(const stmdev_ctx_t *ctx, lis3dh_ble_t *val)
1072 {
1073 lis3dh_ctrl_reg4_t ctrl_reg4;
1074 int32_t ret;
1075
1076 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1077
1078 switch (ctrl_reg4.ble)
1079 {
1080 case LIS3DH_LSB_AT_LOW_ADD:
1081 *val = LIS3DH_LSB_AT_LOW_ADD;
1082 break;
1083
1084 case LIS3DH_MSB_AT_LOW_ADD:
1085 *val = LIS3DH_MSB_AT_LOW_ADD;
1086 break;
1087
1088 default:
1089 *val = LIS3DH_LSB_AT_LOW_ADD;
1090 break;
1091 }
1092
1093 return ret;
1094 }
1095
1096 /**
1097 * @brief Reboot memory content. Reload the calibration parameters.[set]
1098 *
1099 * @param ctx read / write interface definitions
1100 * @param val change the values of boot in reg CTRL_REG5
1101 * @retval interface status (MANDATORY: return 0 -> no Error)
1102 *
1103 */
lis3dh_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1104 int32_t lis3dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1105 {
1106 lis3dh_ctrl_reg5_t ctrl_reg5;
1107 int32_t ret;
1108
1109 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1110
1111 if (ret == 0)
1112 {
1113 ctrl_reg5.boot = val;
1114 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1115 }
1116
1117 return ret;
1118 }
1119
1120 /**
1121 * @brief Reboot memory content. Reload the calibration parameters.[get]
1122 *
1123 * @param ctx read / write interface definitions
1124 * @param val change the values of boot in reg CTRL_REG5
1125 * @retval interface status (MANDATORY: return 0 -> no Error)
1126 *
1127 */
lis3dh_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1128 int32_t lis3dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1129 {
1130 lis3dh_ctrl_reg5_t ctrl_reg5;
1131 int32_t ret;
1132
1133 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1134 *val = (uint8_t)ctrl_reg5.boot;
1135
1136 return ret;
1137 }
1138
1139 /**
1140 * @brief Info about device status.[get]
1141 *
1142 * @param ctx read / write interface definitions
1143 * @param val register STATUS_REG
1144 * @retval interface status (MANDATORY: return 0 -> no Error)
1145 *
1146 */
lis3dh_status_get(const stmdev_ctx_t * ctx,lis3dh_status_reg_t * val)1147 int32_t lis3dh_status_get(const stmdev_ctx_t *ctx, lis3dh_status_reg_t *val)
1148 {
1149 int32_t ret;
1150
1151 ret = lis3dh_read_reg(ctx, LIS3DH_STATUS_REG, (uint8_t *) val, 1);
1152
1153 return ret;
1154 }
1155 /**
1156 * @}
1157 *
1158 */
1159
1160 /**
1161 * @defgroup LIS3DH_Interrupts_generator_1
1162 * @brief This section group all the functions that manage the first
1163 * interrupts generator
1164 * @{
1165 *
1166 */
1167
1168 /**
1169 * @brief Interrupt generator 1 configuration register.[set]
1170 *
1171 * @param ctx read / write interface definitions
1172 * @param val register INT1_CFG
1173 * @retval interface status (MANDATORY: return 0 -> no Error)
1174 *
1175 */
lis3dh_int1_gen_conf_set(const stmdev_ctx_t * ctx,lis3dh_int1_cfg_t * val)1176 int32_t lis3dh_int1_gen_conf_set(const stmdev_ctx_t *ctx,
1177 lis3dh_int1_cfg_t *val)
1178 {
1179 int32_t ret;
1180
1181 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
1182
1183 return ret;
1184 }
1185
1186 /**
1187 * @brief Interrupt generator 1 configuration register.[get]
1188 *
1189 * @param ctx read / write interface definitions
1190 * @param val register INT1_CFG
1191 * @retval interface status (MANDATORY: return 0 -> no Error)
1192 *
1193 */
lis3dh_int1_gen_conf_get(const stmdev_ctx_t * ctx,lis3dh_int1_cfg_t * val)1194 int32_t lis3dh_int1_gen_conf_get(const stmdev_ctx_t *ctx,
1195 lis3dh_int1_cfg_t *val)
1196 {
1197 int32_t ret;
1198
1199 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_CFG, (uint8_t *) val, 1);
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Interrupt generator 1 source register.[get]
1206 *
1207 * @param ctx read / write interface definitions
1208 * @param val Registers INT1_SRC
1209 * @retval interface status (MANDATORY: return 0 -> no Error)
1210 *
1211 */
lis3dh_int1_gen_source_get(const stmdev_ctx_t * ctx,lis3dh_int1_src_t * val)1212 int32_t lis3dh_int1_gen_source_get(const stmdev_ctx_t *ctx,
1213 lis3dh_int1_src_t *val)
1214 {
1215 int32_t ret;
1216
1217 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_SRC, (uint8_t *) val, 1);
1218
1219 return ret;
1220 }
1221 /**
1222 * @brief User-defined threshold value for xl interrupt event on
1223 * generator 1.[set]
1224 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1225 *
1226 * @param ctx read / write interface definitions
1227 * @param val change the values of ths in reg INT1_THS
1228 * @retval interface status (MANDATORY: return 0 -> no Error)
1229 *
1230 */
lis3dh_int1_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1231 int32_t lis3dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1232 {
1233 lis3dh_int1_ths_t int1_ths;
1234 int32_t ret;
1235
1236 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1237
1238 if (ret == 0)
1239 {
1240 int1_ths.ths = val;
1241 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1242 }
1243
1244 return ret;
1245 }
1246
1247 /**
1248 * @brief User-defined threshold value for xl interrupt event on
1249 * generator 1.[get]
1250 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1251 *
1252 * @param ctx read / write interface definitions
1253 * @param val change the values of ths in reg INT1_THS
1254 * @retval interface status (MANDATORY: return 0 -> no Error)
1255 *
1256 */
lis3dh_int1_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1257 int32_t lis3dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1258 {
1259 lis3dh_int1_ths_t int1_ths;
1260 int32_t ret;
1261
1262 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1263 *val = (uint8_t)int1_ths.ths;
1264
1265 return ret;
1266 }
1267
1268 /**
1269 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1270 * recognized.[set]
1271 *
1272 * @param ctx read / write interface definitions
1273 * @param val change the values of d in reg INT1_DURATION
1274 * @retval interface status (MANDATORY: return 0 -> no Error)
1275 *
1276 */
lis3dh_int1_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1277 int32_t lis3dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1278 {
1279 lis3dh_int1_duration_t int1_duration;
1280 int32_t ret;
1281
1282 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
1283 (uint8_t *)&int1_duration, 1);
1284
1285 if (ret == 0)
1286 {
1287 int1_duration.d = val;
1288 ret = lis3dh_write_reg(ctx, LIS3DH_INT1_DURATION,
1289 (uint8_t *)&int1_duration, 1);
1290 }
1291
1292 return ret;
1293 }
1294
1295 /**
1296 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1297 * recognized.[get]
1298 *
1299 * @param ctx read / write interface definitions
1300 * @param val change the values of d in reg INT1_DURATION
1301 * @retval interface status (MANDATORY: return 0 -> no Error)
1302 *
1303 */
lis3dh_int1_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1304 int32_t lis3dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
1305 {
1306 lis3dh_int1_duration_t int1_duration;
1307 int32_t ret;
1308
1309 ret = lis3dh_read_reg(ctx, LIS3DH_INT1_DURATION,
1310 (uint8_t *)&int1_duration, 1);
1311 *val = (uint8_t)int1_duration.d;
1312
1313 return ret;
1314 }
1315
1316 /**
1317 * @}
1318 *
1319 */
1320
1321 /**
1322 * @defgroup LIS3DH_Interrupts_generator_2
1323 * @brief This section group all the functions that manage the second
1324 * interrupts generator
1325 * @{
1326 *
1327 */
1328
1329 /**
1330 * @brief Interrupt generator 2 configuration register.[set]
1331 *
1332 * @param ctx read / write interface definitions
1333 * @param val registers INT2_CFG
1334 * @retval interface status (MANDATORY: return 0 -> no Error)
1335 *
1336 */
lis3dh_int2_gen_conf_set(const stmdev_ctx_t * ctx,lis3dh_int2_cfg_t * val)1337 int32_t lis3dh_int2_gen_conf_set(const stmdev_ctx_t *ctx,
1338 lis3dh_int2_cfg_t *val)
1339 {
1340 int32_t ret;
1341
1342 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
1343
1344 return ret;
1345 }
1346
1347 /**
1348 * @brief Interrupt generator 2 configuration register.[get]
1349 *
1350 * @param ctx read / write interface definitions
1351 * @param val registers INT2_CFG
1352 * @retval interface status (MANDATORY: return 0 -> no Error)
1353 *
1354 */
lis3dh_int2_gen_conf_get(const stmdev_ctx_t * ctx,lis3dh_int2_cfg_t * val)1355 int32_t lis3dh_int2_gen_conf_get(const stmdev_ctx_t *ctx,
1356 lis3dh_int2_cfg_t *val)
1357 {
1358 int32_t ret;
1359
1360 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_CFG, (uint8_t *) val, 1);
1361
1362 return ret;
1363 }
1364 /**
1365 * @brief Interrupt generator 2 source register.[get]
1366 *
1367 * @param ctx read / write interface definitions
1368 * @param val registers INT2_SRC
1369 * @retval interface status (MANDATORY: return 0 -> no Error)
1370 *
1371 */
lis3dh_int2_gen_source_get(const stmdev_ctx_t * ctx,lis3dh_int2_src_t * val)1372 int32_t lis3dh_int2_gen_source_get(const stmdev_ctx_t *ctx,
1373 lis3dh_int2_src_t *val)
1374 {
1375 int32_t ret;
1376
1377 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_SRC, (uint8_t *) val, 1);
1378
1379 return ret;
1380 }
1381 /**
1382 * @brief User-defined threshold value for xl interrupt event on
1383 * generator 2.[set]
1384 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1385 *
1386 * @param ctx read / write interface definitions
1387 * @param val change the values of ths in reg INT2_THS
1388 * @retval interface status (MANDATORY: return 0 -> no Error)
1389 *
1390 */
lis3dh_int2_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1391 int32_t lis3dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1392 {
1393 lis3dh_int2_ths_t int2_ths;
1394 int32_t ret;
1395
1396 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1397
1398 if (ret == 0)
1399 {
1400 int2_ths.ths = val;
1401 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1402 }
1403
1404 return ret;
1405 }
1406
1407 /**
1408 * @brief User-defined threshold value for xl interrupt event on
1409 * generator 2.[get]
1410 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1411 *
1412 * @param ctx read / write interface definitions
1413 * @param val change the values of ths in reg INT2_THS
1414 * @retval interface status (MANDATORY: return 0 -> no Error)
1415 *
1416 */
lis3dh_int2_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1417 int32_t lis3dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1418 {
1419 lis3dh_int2_ths_t int2_ths;
1420 int32_t ret;
1421
1422 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1423 *val = (uint8_t)int2_ths.ths;
1424
1425 return ret;
1426 }
1427
1428 /**
1429 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1430 * recognized .[set]
1431 *
1432 * @param ctx read / write interface definitions
1433 * @param val change the values of d in reg INT2_DURATION
1434 * @retval interface status (MANDATORY: return 0 -> no Error)
1435 *
1436 */
lis3dh_int2_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)1437 int32_t lis3dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
1438 {
1439 lis3dh_int2_duration_t int2_duration;
1440 int32_t ret;
1441
1442 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
1443 (uint8_t *)&int2_duration, 1);
1444
1445 if (ret == 0)
1446 {
1447 int2_duration.d = val;
1448 ret = lis3dh_write_reg(ctx, LIS3DH_INT2_DURATION,
1449 (uint8_t *)&int2_duration, 1);
1450 }
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1457 * recognized.[get]
1458 *
1459 * @param ctx read / write interface definitions
1460 * @param val change the values of d in reg INT2_DURATION
1461 * @retval interface status (MANDATORY: return 0 -> no Error)
1462 *
1463 */
lis3dh_int2_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)1464 int32_t lis3dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
1465 {
1466 lis3dh_int2_duration_t int2_duration;
1467 int32_t ret;
1468
1469 ret = lis3dh_read_reg(ctx, LIS3DH_INT2_DURATION,
1470 (uint8_t *)&int2_duration, 1);
1471 *val = (uint8_t)int2_duration.d;
1472
1473 return ret;
1474 }
1475
1476 /**
1477 * @}
1478 *
1479 */
1480
1481 /**
1482 * @defgroup LIS3DH_Interrupt_pins
1483 * @brief This section group all the functions that manage interrupt pins
1484 * @{
1485 *
1486 */
1487
1488 /**
1489 * @brief High-pass filter on interrupts/tap generator.[set]
1490 *
1491 * @param ctx read / write interface definitions
1492 * @param val change the values of hp in reg CTRL_REG2
1493 * @retval interface status (MANDATORY: return 0 -> no Error)
1494 *
1495 */
lis3dh_high_pass_int_conf_set(const stmdev_ctx_t * ctx,lis3dh_hp_t val)1496 int32_t lis3dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx,
1497 lis3dh_hp_t val)
1498 {
1499 lis3dh_ctrl_reg2_t ctrl_reg2;
1500 int32_t ret;
1501
1502 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1503
1504 if (ret == 0)
1505 {
1506 ctrl_reg2.hp = (uint8_t)val;
1507 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1508 }
1509
1510 return ret;
1511 }
1512
1513 /**
1514 * @brief High-pass filter on interrupts/tap generator.[get]
1515 *
1516 * @param ctx read / write interface definitions
1517 * @param val Get the values of hp in reg CTRL_REG2
1518 * @retval interface status (MANDATORY: return 0 -> no Error)
1519 *
1520 */
lis3dh_high_pass_int_conf_get(const stmdev_ctx_t * ctx,lis3dh_hp_t * val)1521 int32_t lis3dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx,
1522 lis3dh_hp_t *val)
1523 {
1524 lis3dh_ctrl_reg2_t ctrl_reg2;
1525 int32_t ret;
1526
1527 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1528
1529 switch (ctrl_reg2.hp)
1530 {
1531 case LIS3DH_DISC_FROM_INT_GENERATOR:
1532 *val = LIS3DH_DISC_FROM_INT_GENERATOR;
1533 break;
1534
1535 case LIS3DH_ON_INT1_GEN:
1536 *val = LIS3DH_ON_INT1_GEN;
1537 break;
1538
1539 case LIS3DH_ON_INT2_GEN:
1540 *val = LIS3DH_ON_INT2_GEN;
1541 break;
1542
1543 case LIS3DH_ON_TAP_GEN:
1544 *val = LIS3DH_ON_TAP_GEN;
1545 break;
1546
1547 case LIS3DH_ON_INT1_INT2_GEN:
1548 *val = LIS3DH_ON_INT1_INT2_GEN;
1549 break;
1550
1551 case LIS3DH_ON_INT1_TAP_GEN:
1552 *val = LIS3DH_ON_INT1_TAP_GEN;
1553 break;
1554
1555 case LIS3DH_ON_INT2_TAP_GEN:
1556 *val = LIS3DH_ON_INT2_TAP_GEN;
1557 break;
1558
1559 case LIS3DH_ON_INT1_INT2_TAP_GEN:
1560 *val = LIS3DH_ON_INT1_INT2_TAP_GEN;
1561 break;
1562
1563 default:
1564 *val = LIS3DH_DISC_FROM_INT_GENERATOR;
1565 break;
1566 }
1567
1568 return ret;
1569 }
1570
1571 /**
1572 * @brief Int1 pin routing configuration register.[set]
1573 *
1574 * @param ctx read / write interface definitions
1575 * @param val registers CTRL_REG3
1576 * @retval interface status (MANDATORY: return 0 -> no Error)
1577 *
1578 */
lis3dh_pin_int1_config_set(const stmdev_ctx_t * ctx,lis3dh_ctrl_reg3_t * val)1579 int32_t lis3dh_pin_int1_config_set(const stmdev_ctx_t *ctx,
1580 lis3dh_ctrl_reg3_t *val)
1581 {
1582 int32_t ret;
1583
1584 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
1585
1586 return ret;
1587 }
1588
1589 /**
1590 * @brief Int1 pin routing configuration register.[get]
1591 *
1592 * @param ctx read / write interface definitions
1593 * @param val registers CTRL_REG3
1594 * @retval interface status (MANDATORY: return 0 -> no Error)
1595 *
1596 */
lis3dh_pin_int1_config_get(const stmdev_ctx_t * ctx,lis3dh_ctrl_reg3_t * val)1597 int32_t lis3dh_pin_int1_config_get(const stmdev_ctx_t *ctx,
1598 lis3dh_ctrl_reg3_t *val)
1599 {
1600 int32_t ret;
1601
1602 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG3, (uint8_t *) val, 1);
1603
1604 return ret;
1605 }
1606 /**
1607 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1608 * on INT2 pin when 6D bit on
1609 * INT2_CFG (34h) is set to 1.
1610 *
1611 * @param ctx read / write interface definitions
1612 * @param val change the values of d4d_int2 in reg CTRL_REG5
1613 * @retval interface status (MANDATORY: return 0 -> no Error)
1614 *
1615 */
lis3dh_int2_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1616 int32_t lis3dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val)
1617 {
1618 lis3dh_ctrl_reg5_t ctrl_reg5;
1619 int32_t ret;
1620
1621 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1622
1623 if (ret == 0)
1624 {
1625 ctrl_reg5.d4d_int2 = val;
1626 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1627 }
1628
1629 return ret;
1630 }
1631
1632 /**
1633 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1634 * INT2_CFG (34h) is set to 1.[get]
1635 *
1636 * @param ctx read / write interface definitions
1637 * @param val change the values of d4d_int2 in reg CTRL_REG5
1638 * @retval interface status (MANDATORY: return 0 -> no Error)
1639 *
1640 */
lis3dh_int2_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1641 int32_t lis3dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val)
1642 {
1643 lis3dh_ctrl_reg5_t ctrl_reg5;
1644 int32_t ret;
1645
1646 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1647 *val = (uint8_t)ctrl_reg5.d4d_int2;
1648
1649 return ret;
1650 }
1651
1652 /**
1653 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1654 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1655 * itself.[set]
1656 *
1657 * @param ctx read / write interface definitions
1658 * @param val change the values of lir_int2 in reg CTRL_REG5
1659 * @retval interface status (MANDATORY: return 0 -> no Error)
1660 *
1661 */
lis3dh_int2_pin_notification_mode_set(const stmdev_ctx_t * ctx,lis3dh_lir_int2_t val)1662 int32_t lis3dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1663 lis3dh_lir_int2_t val)
1664 {
1665 lis3dh_ctrl_reg5_t ctrl_reg5;
1666 int32_t ret;
1667
1668 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1669
1670 if (ret == 0)
1671 {
1672 ctrl_reg5.lir_int2 = (uint8_t)val;
1673 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1674 }
1675
1676 return ret;
1677 }
1678
1679 /**
1680 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1681 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1682 * itself.[get]
1683 *
1684 * @param ctx read / write interface definitions
1685 * @param val Get the values of lir_int2 in reg CTRL_REG5
1686 * @retval interface status (MANDATORY: return 0 -> no Error)
1687 *
1688 */
lis3dh_int2_pin_notification_mode_get(const stmdev_ctx_t * ctx,lis3dh_lir_int2_t * val)1689 int32_t lis3dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1690 lis3dh_lir_int2_t *val)
1691 {
1692 lis3dh_ctrl_reg5_t ctrl_reg5;
1693 int32_t ret;
1694
1695 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1696
1697 switch (ctrl_reg5.lir_int2)
1698 {
1699 case LIS3DH_INT2_PULSED:
1700 *val = LIS3DH_INT2_PULSED;
1701 break;
1702
1703 case LIS3DH_INT2_LATCHED:
1704 *val = LIS3DH_INT2_LATCHED;
1705 break;
1706
1707 default:
1708 *val = LIS3DH_INT2_PULSED;
1709 break;
1710 }
1711
1712 return ret;
1713 }
1714
1715 /**
1716 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1717 * on INT1_CFG(30h) is set to 1.[set]
1718 *
1719 * @param ctx read / write interface definitions
1720 * @param val change the values of d4d_int1 in reg CTRL_REG5
1721 * @retval interface status (MANDATORY: return 0 -> no Error)
1722 *
1723 */
lis3dh_int1_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)1724 int32_t lis3dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val)
1725 {
1726 lis3dh_ctrl_reg5_t ctrl_reg5;
1727 int32_t ret;
1728
1729 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1730
1731 if (ret == 0)
1732 {
1733 ctrl_reg5.d4d_int1 = val;
1734 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1735 }
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1742 * INT1_CFG(30h) is set to 1.[get]
1743 *
1744 * @param ctx read / write interface definitions
1745 * @param val change the values of d4d_int1 in reg CTRL_REG5
1746 * @retval interface status (MANDATORY: return 0 -> no Error)
1747 *
1748 */
lis3dh_int1_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)1749 int32_t lis3dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val)
1750 {
1751 lis3dh_ctrl_reg5_t ctrl_reg5;
1752 int32_t ret;
1753
1754 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1755 *val = (uint8_t)ctrl_reg5.d4d_int1;
1756
1757 return ret;
1758 }
1759
1760 /**
1761 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1762 * register cleared by reading INT1_SRC (31h) itself.[set]
1763 *
1764 * @param ctx read / write interface definitions
1765 * @param val change the values of lir_int1 in reg CTRL_REG5
1766 * @retval interface status (MANDATORY: return 0 -> no Error)
1767 *
1768 */
lis3dh_int1_pin_notification_mode_set(const stmdev_ctx_t * ctx,lis3dh_lir_int1_t val)1769 int32_t lis3dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx,
1770 lis3dh_lir_int1_t val)
1771 {
1772 lis3dh_ctrl_reg5_t ctrl_reg5;
1773 int32_t ret;
1774
1775 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1776
1777 if (ret == 0)
1778 {
1779 ctrl_reg5.lir_int1 = (uint8_t)val;
1780 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1781 }
1782
1783 return ret;
1784 }
1785
1786 /**
1787 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1788 * register cleared by reading INT1_SRC (31h) itself.[get]
1789 *
1790 * @param ctx read / write interface definitions
1791 * @param val Get the values of lir_int1 in reg CTRL_REG5
1792 * @retval interface status (MANDATORY: return 0 -> no Error)
1793 *
1794 */
lis3dh_int1_pin_notification_mode_get(const stmdev_ctx_t * ctx,lis3dh_lir_int1_t * val)1795 int32_t lis3dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx,
1796 lis3dh_lir_int1_t *val)
1797 {
1798 lis3dh_ctrl_reg5_t ctrl_reg5;
1799 int32_t ret;
1800
1801 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1802
1803 switch (ctrl_reg5.lir_int1)
1804 {
1805 case LIS3DH_INT1_PULSED:
1806 *val = LIS3DH_INT1_PULSED;
1807 break;
1808
1809 case LIS3DH_INT1_LATCHED:
1810 *val = LIS3DH_INT1_LATCHED;
1811 break;
1812
1813 default:
1814 *val = LIS3DH_INT1_PULSED;
1815 break;
1816 }
1817
1818 return ret;
1819 }
1820
1821 /**
1822 * @brief Int2 pin routing configuration register.[set]
1823 *
1824 * @param ctx read / write interface definitions
1825 * @param val registers CTRL_REG6
1826 * @retval interface status (MANDATORY: return 0 -> no Error)
1827 *
1828 */
lis3dh_pin_int2_config_set(const stmdev_ctx_t * ctx,lis3dh_ctrl_reg6_t * val)1829 int32_t lis3dh_pin_int2_config_set(const stmdev_ctx_t *ctx,
1830 lis3dh_ctrl_reg6_t *val)
1831 {
1832 int32_t ret;
1833
1834 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief Int2 pin routing configuration register.[get]
1841 *
1842 * @param ctx read / write interface definitions
1843 * @param val registers CTRL_REG6
1844 * @retval interface status (MANDATORY: return 0 -> no Error)
1845 *
1846 */
lis3dh_pin_int2_config_get(const stmdev_ctx_t * ctx,lis3dh_ctrl_reg6_t * val)1847 int32_t lis3dh_pin_int2_config_get(const stmdev_ctx_t *ctx,
1848 lis3dh_ctrl_reg6_t *val)
1849 {
1850 int32_t ret;
1851
1852 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG6, (uint8_t *) val, 1);
1853
1854 return ret;
1855 }
1856 /**
1857 * @}
1858 *
1859 */
1860
1861 /**
1862 * @defgroup LIS3DH_Fifo
1863 * @brief This section group all the functions concerning the fifo usage
1864 * @{
1865 *
1866 */
1867
1868 /**
1869 * @brief FIFO enable.[set]
1870 *
1871 * @param ctx read / write interface definitions
1872 * @param val change the values of fifo_en in reg CTRL_REG5
1873 * @retval interface status (MANDATORY: return 0 -> no Error)
1874 *
1875 */
lis3dh_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)1876 int32_t lis3dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
1877 {
1878 lis3dh_ctrl_reg5_t ctrl_reg5;
1879 int32_t ret;
1880
1881 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1882
1883 if (ret == 0)
1884 {
1885 ctrl_reg5.fifo_en = val;
1886 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1887 }
1888
1889 return ret;
1890 }
1891
1892 /**
1893 * @brief FIFO enable.[get]
1894 *
1895 * @param ctx read / write interface definitions
1896 * @param val change the values of fifo_en in reg CTRL_REG5
1897 * @retval interface status (MANDATORY: return 0 -> no Error)
1898 *
1899 */
lis3dh_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)1900 int32_t lis3dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
1901 {
1902 lis3dh_ctrl_reg5_t ctrl_reg5;
1903 int32_t ret;
1904
1905 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1906 *val = (uint8_t)ctrl_reg5.fifo_en;
1907
1908 return ret;
1909 }
1910
1911 /**
1912 * @brief FIFO watermark level selection.[set]
1913 *
1914 * @param ctx read / write interface definitions
1915 * @param val change the values of fth in reg FIFO_CTRL_REG
1916 * @retval interface status (MANDATORY: return 0 -> no Error)
1917 *
1918 */
lis3dh_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1919 int32_t lis3dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1920 {
1921 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1922 int32_t ret;
1923
1924 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1925 (uint8_t *)&fifo_ctrl_reg, 1);
1926
1927 if (ret == 0)
1928 {
1929 fifo_ctrl_reg.fth = val;
1930 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1931 (uint8_t *)&fifo_ctrl_reg, 1);
1932 }
1933
1934 return ret;
1935 }
1936
1937 /**
1938 * @brief FIFO watermark level selection.[get]
1939 *
1940 * @param ctx read / write interface definitions
1941 * @param val change the values of fth in reg FIFO_CTRL_REG
1942 * @retval interface status (MANDATORY: return 0 -> no Error)
1943 *
1944 */
lis3dh_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1945 int32_t lis3dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1946 {
1947 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1948 int32_t ret;
1949
1950 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1951 (uint8_t *)&fifo_ctrl_reg, 1);
1952 *val = (uint8_t)fifo_ctrl_reg.fth;
1953
1954 return ret;
1955 }
1956
1957 /**
1958 * @brief Trigger FIFO selection.[set]
1959 *
1960 * @param ctx read / write interface definitions
1961 * @param val change the values of tr in reg FIFO_CTRL_REG
1962 * @retval interface status (MANDATORY: return 0 -> no Error)
1963 *
1964 */
lis3dh_fifo_trigger_event_set(const stmdev_ctx_t * ctx,lis3dh_tr_t val)1965 int32_t lis3dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx,
1966 lis3dh_tr_t val)
1967 {
1968 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1969 int32_t ret;
1970
1971 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1972 (uint8_t *)&fifo_ctrl_reg, 1);
1973
1974 if (ret == 0)
1975 {
1976 fifo_ctrl_reg.tr = (uint8_t)val;
1977 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1978 (uint8_t *)&fifo_ctrl_reg, 1);
1979 }
1980
1981 return ret;
1982 }
1983
1984 /**
1985 * @brief Trigger FIFO selection.[get]
1986 *
1987 * @param ctx read / write interface definitions
1988 * @param val Get the values of tr in reg FIFO_CTRL_REG
1989 * @retval interface status (MANDATORY: return 0 -> no Error)
1990 *
1991 */
lis3dh_fifo_trigger_event_get(const stmdev_ctx_t * ctx,lis3dh_tr_t * val)1992 int32_t lis3dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx,
1993 lis3dh_tr_t *val)
1994 {
1995 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1996 int32_t ret;
1997
1998 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
1999 (uint8_t *)&fifo_ctrl_reg, 1);
2000
2001 switch (fifo_ctrl_reg.tr)
2002 {
2003 case LIS3DH_INT1_GEN:
2004 *val = LIS3DH_INT1_GEN;
2005 break;
2006
2007 case LIS3DH_INT2_GEN:
2008 *val = LIS3DH_INT2_GEN;
2009 break;
2010
2011 default:
2012 *val = LIS3DH_INT1_GEN;
2013 break;
2014 }
2015
2016 return ret;
2017 }
2018
2019 /**
2020 * @brief FIFO mode selection.[set]
2021 *
2022 * @param ctx read / write interface definitions
2023 * @param val change the values of fm in reg FIFO_CTRL_REG
2024 * @retval interface status (MANDATORY: return 0 -> no Error)
2025 *
2026 */
lis3dh_fifo_mode_set(const stmdev_ctx_t * ctx,lis3dh_fm_t val)2027 int32_t lis3dh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dh_fm_t val)
2028 {
2029 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2030 int32_t ret;
2031
2032 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2033 (uint8_t *)&fifo_ctrl_reg, 1);
2034
2035 if (ret == 0)
2036 {
2037 fifo_ctrl_reg.fm = (uint8_t)val;
2038 ret = lis3dh_write_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2039 (uint8_t *)&fifo_ctrl_reg, 1);
2040 }
2041
2042 return ret;
2043 }
2044
2045 /**
2046 * @brief FIFO mode selection.[get]
2047 *
2048 * @param ctx read / write interface definitions
2049 * @param val Get the values of fm in reg FIFO_CTRL_REG
2050 * @retval interface status (MANDATORY: return 0 -> no Error)
2051 *
2052 */
lis3dh_fifo_mode_get(const stmdev_ctx_t * ctx,lis3dh_fm_t * val)2053 int32_t lis3dh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dh_fm_t *val)
2054 {
2055 lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2056 int32_t ret;
2057
2058 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_CTRL_REG,
2059 (uint8_t *)&fifo_ctrl_reg, 1);
2060
2061 switch (fifo_ctrl_reg.fm)
2062 {
2063 case LIS3DH_BYPASS_MODE:
2064 *val = LIS3DH_BYPASS_MODE;
2065 break;
2066
2067 case LIS3DH_FIFO_MODE:
2068 *val = LIS3DH_FIFO_MODE;
2069 break;
2070
2071 case LIS3DH_DYNAMIC_STREAM_MODE:
2072 *val = LIS3DH_DYNAMIC_STREAM_MODE;
2073 break;
2074
2075 case LIS3DH_STREAM_TO_FIFO_MODE:
2076 *val = LIS3DH_STREAM_TO_FIFO_MODE;
2077 break;
2078
2079 default:
2080 *val = LIS3DH_BYPASS_MODE;
2081 break;
2082 }
2083
2084 return ret;
2085 }
2086
2087 /**
2088 * @brief FIFO status register.[get]
2089 *
2090 * @param ctx read / write interface definitions
2091 * @param val registers FIFO_SRC_REG
2092 * @retval interface status (MANDATORY: return 0 -> no Error)
2093 *
2094 */
lis3dh_fifo_status_get(const stmdev_ctx_t * ctx,lis3dh_fifo_src_reg_t * val)2095 int32_t lis3dh_fifo_status_get(const stmdev_ctx_t *ctx,
2096 lis3dh_fifo_src_reg_t *val)
2097 {
2098 int32_t ret;
2099
2100 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG, (uint8_t *) val, 1);
2101
2102 return ret;
2103 }
2104 /**
2105 * @brief FIFO stored data level.[get]
2106 *
2107 * @param ctx read / write interface definitions
2108 * @param val change the values of fss in reg FIFO_SRC_REG
2109 * @retval interface status (MANDATORY: return 0 -> no Error)
2110 *
2111 */
lis3dh_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)2112 int32_t lis3dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
2113 {
2114 lis3dh_fifo_src_reg_t fifo_src_reg;
2115 int32_t ret;
2116
2117 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2118 (uint8_t *)&fifo_src_reg, 1);
2119 *val = (uint8_t)fifo_src_reg.fss;
2120
2121 return ret;
2122 }
2123 /**
2124 * @brief Empty FIFO status flag.[get]
2125 *
2126 * @param ctx read / write interface definitions
2127 * @param val change the values of empty in reg FIFO_SRC_REG
2128 * @retval interface status (MANDATORY: return 0 -> no Error)
2129 *
2130 */
lis3dh_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2131 int32_t lis3dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2132 {
2133 lis3dh_fifo_src_reg_t fifo_src_reg;
2134 int32_t ret;
2135
2136 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2137 (uint8_t *)&fifo_src_reg, 1);
2138 *val = (uint8_t)fifo_src_reg.empty;
2139
2140 return ret;
2141 }
2142 /**
2143 * @brief FIFO overrun status flag.[get]
2144 *
2145 * @param ctx read / write interface definitions
2146 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
2147 * @retval interface status (MANDATORY: return 0 -> no Error)
2148 *
2149 */
lis3dh_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2150 int32_t lis3dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2151 {
2152 lis3dh_fifo_src_reg_t fifo_src_reg;
2153 int32_t ret;
2154
2155 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2156 (uint8_t *)&fifo_src_reg, 1);
2157 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
2158
2159 return ret;
2160 }
2161 /**
2162 * @brief FIFO watermark status.[get]
2163 *
2164 * @param ctx read / write interface definitions
2165 * @param val change the values of wtm in reg FIFO_SRC_REG
2166 * @retval interface status (MANDATORY: return 0 -> no Error)
2167 *
2168 */
lis3dh_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2169 int32_t lis3dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2170 {
2171 lis3dh_fifo_src_reg_t fifo_src_reg;
2172 int32_t ret;
2173
2174 ret = lis3dh_read_reg(ctx, LIS3DH_FIFO_SRC_REG,
2175 (uint8_t *)&fifo_src_reg, 1);
2176 *val = (uint8_t)fifo_src_reg.wtm;
2177
2178 return ret;
2179 }
2180 /**
2181 * @}
2182 *
2183 */
2184
2185 /**
2186 * @defgroup LIS3DH_Tap_generator
2187 * @brief This section group all the functions that manage the tap and
2188 * double tap event generation
2189 * @{
2190 *
2191 */
2192
2193 /**
2194 * @brief Tap/Double Tap generator configuration register.[set]
2195 *
2196 * @param ctx read / write interface definitions
2197 * @param val registers CLICK_CFG
2198 * @retval interface status (MANDATORY: return 0 -> no Error)
2199 *
2200 */
lis3dh_tap_conf_set(const stmdev_ctx_t * ctx,lis3dh_click_cfg_t * val)2201 int32_t lis3dh_tap_conf_set(const stmdev_ctx_t *ctx,
2202 lis3dh_click_cfg_t *val)
2203 {
2204 int32_t ret;
2205
2206 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
2207
2208 return ret;
2209 }
2210
2211 /**
2212 * @brief Tap/Double Tap generator configuration register.[get]
2213 *
2214 * @param ctx read / write interface definitions
2215 * @param val registers CLICK_CFG
2216 * @retval interface status (MANDATORY: return 0 -> no Error)
2217 *
2218 */
lis3dh_tap_conf_get(const stmdev_ctx_t * ctx,lis3dh_click_cfg_t * val)2219 int32_t lis3dh_tap_conf_get(const stmdev_ctx_t *ctx,
2220 lis3dh_click_cfg_t *val)
2221 {
2222 int32_t ret;
2223
2224 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_CFG, (uint8_t *) val, 1);
2225
2226 return ret;
2227 }
2228 /**
2229 * @brief Tap/Double Tap generator source register.[get]
2230 *
2231 * @param ctx read / write interface definitions
2232 * @param val registers CLICK_SRC
2233 * @retval interface status (MANDATORY: return 0 -> no Error)
2234 *
2235 */
lis3dh_tap_source_get(const stmdev_ctx_t * ctx,lis3dh_click_src_t * val)2236 int32_t lis3dh_tap_source_get(const stmdev_ctx_t *ctx,
2237 lis3dh_click_src_t *val)
2238 {
2239 int32_t ret;
2240
2241 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_SRC, (uint8_t *) val, 1);
2242
2243 return ret;
2244 }
2245 /**
2246 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2247 * 1 LSB = full scale/128
2248 *
2249 * @param ctx read / write interface definitions
2250 * @param val change the values of ths in reg CLICK_THS
2251 * @retval interface status (MANDATORY: return 0 -> no Error)
2252 *
2253 */
lis3dh_tap_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2254 int32_t lis3dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2255 {
2256 lis3dh_click_ths_t click_ths;
2257 int32_t ret;
2258
2259 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2260
2261 if (ret == 0)
2262 {
2263 click_ths.ths = val;
2264 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2265 }
2266
2267 return ret;
2268 }
2269
2270 /**
2271 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2272 * 1 LSB = full scale/128
2273 *
2274 * @param ctx read / write interface definitions
2275 * @param val change the values of ths in reg CLICK_THS
2276 * @retval interface status (MANDATORY: return 0 -> no Error)
2277 *
2278 */
lis3dh_tap_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2279 int32_t lis3dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2280 {
2281 lis3dh_click_ths_t click_ths;
2282 int32_t ret;
2283
2284 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2285 *val = (uint8_t)click_ths.ths;
2286
2287 return ret;
2288 }
2289
2290 /**
2291 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2292 * for the duration of the latency window.
2293 * If the LIR_Click bit is set, the interrupt is kept high until the
2294 * CLICK_SRC(39h) register is read.[set]
2295 *
2296 * @param ctx read / write interface definitions
2297 * @param val change the values of lir_click in reg CLICK_THS
2298 * @retval interface status (MANDATORY: return 0 -> no Error)
2299 *
2300 */
lis3dh_tap_notification_mode_set(const stmdev_ctx_t * ctx,lis3dh_lir_click_t val)2301 int32_t lis3dh_tap_notification_mode_set(const stmdev_ctx_t *ctx,
2302 lis3dh_lir_click_t val)
2303 {
2304 lis3dh_click_ths_t click_ths;
2305 int32_t ret;
2306
2307 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2308
2309 if (ret == 0)
2310 {
2311 click_ths.lir_click = (uint8_t)val;
2312 ret = lis3dh_write_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2313 }
2314
2315 return ret;
2316 }
2317
2318 /**
2319 * @brief If the LIR_Click bit is not set, the interrupt is kept high
2320 * for the duration of the latency window.
2321 * If the LIR_Click bit is set, the interrupt is kept high until the
2322 * CLICK_SRC(39h) register is read.[get]
2323 *
2324 * @param ctx read / write interface definitions
2325 * @param val Get the values of lir_click in reg CLICK_THS
2326 * @retval interface status (MANDATORY: return 0 -> no Error)
2327 *
2328 */
lis3dh_tap_notification_mode_get(const stmdev_ctx_t * ctx,lis3dh_lir_click_t * val)2329 int32_t lis3dh_tap_notification_mode_get(const stmdev_ctx_t *ctx,
2330 lis3dh_lir_click_t *val)
2331 {
2332 lis3dh_click_ths_t click_ths;
2333 int32_t ret;
2334
2335 ret = lis3dh_read_reg(ctx, LIS3DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2336
2337 switch (click_ths.lir_click)
2338 {
2339 case LIS3DH_TAP_PULSED:
2340 *val = LIS3DH_TAP_PULSED;
2341 break;
2342
2343 case LIS3DH_TAP_LATCHED:
2344 *val = LIS3DH_TAP_LATCHED;
2345 break;
2346
2347 default:
2348 *val = LIS3DH_TAP_PULSED;
2349 break;
2350 }
2351
2352 return ret;
2353 }
2354
2355 /**
2356 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2357 * between the start of the click-detection procedure and when the
2358 * acceleration falls back below the threshold.[set]
2359 *
2360 * @param ctx read / write interface definitions
2361 * @param val change the values of tli in reg TIME_LIMIT
2362 * @retval interface status (MANDATORY: return 0 -> no Error)
2363 *
2364 */
lis3dh_shock_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2365 int32_t lis3dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2366 {
2367 lis3dh_time_limit_t time_limit;
2368 int32_t ret;
2369
2370 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2371
2372 if (ret == 0)
2373 {
2374 time_limit.tli = val;
2375 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2376 }
2377
2378 return ret;
2379 }
2380
2381 /**
2382 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2383 * the start of the click-detection procedure and when the
2384 * acceleration falls back below the threshold.[get]
2385 *
2386 * @param ctx read / write interface definitions
2387 * @param val change the values of tli in reg TIME_LIMIT
2388 * @retval interface status (MANDATORY: return 0 -> no Error)
2389 *
2390 */
lis3dh_shock_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2391 int32_t lis3dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2392 {
2393 lis3dh_time_limit_t time_limit;
2394 int32_t ret;
2395
2396 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2397 *val = (uint8_t)time_limit.tli;
2398
2399 return ret;
2400 }
2401
2402 /**
2403 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2404 * click detection where the click-detection procedure is
2405 * disabled, in cases where the device is configured for
2406 * double-click detection.[set]
2407 *
2408 * @param ctx read / write interface definitions
2409 * @param val change the values of tla in reg TIME_LATENCY
2410 * @retval interface status (MANDATORY: return 0 -> no Error)
2411 *
2412 */
lis3dh_quiet_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2413 int32_t lis3dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2414 {
2415 lis3dh_time_latency_t time_latency;
2416 int32_t ret;
2417
2418 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
2419 (uint8_t *)&time_latency, 1);
2420
2421 if (ret == 0)
2422 {
2423 time_latency.tla = val;
2424 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_LATENCY,
2425 (uint8_t *)&time_latency, 1);
2426 }
2427
2428 return ret;
2429 }
2430
2431 /**
2432 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2433 * click detection where the click-detection procedure is
2434 * disabled, in cases where the device is configured for
2435 * double-click detection.[get]
2436 *
2437 * @param ctx read / write interface definitions
2438 * @param val change the values of tla in reg TIME_LATENCY
2439 * @retval interface status (MANDATORY: return 0 -> no Error)
2440 *
2441 */
lis3dh_quiet_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2442 int32_t lis3dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2443 {
2444 lis3dh_time_latency_t time_latency;
2445 int32_t ret;
2446
2447 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_LATENCY,
2448 (uint8_t *)&time_latency, 1);
2449 *val = (uint8_t)time_latency.tla;
2450
2451 return ret;
2452 }
2453
2454 /**
2455 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2456 * after the end of the latency interval in which the click-detection
2457 * procedure can start, in cases where the device is configured
2458 * for double-click detection.[set]
2459 *
2460 * @param ctx read / write interface definitions
2461 * @param val change the values of tw in reg TIME_WINDOW
2462 * @retval interface status (MANDATORY: return 0 -> no Error)
2463 *
2464 */
lis3dh_double_tap_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2465 int32_t lis3dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
2466 {
2467 lis3dh_time_window_t time_window;
2468 int32_t ret;
2469
2470 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
2471 (uint8_t *)&time_window, 1);
2472
2473 if (ret == 0)
2474 {
2475 time_window.tw = val;
2476 ret = lis3dh_write_reg(ctx, LIS3DH_TIME_WINDOW,
2477 (uint8_t *)&time_window, 1);
2478 }
2479
2480 return ret;
2481 }
2482
2483 /**
2484 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2485 * after the end of the latency interval in which the
2486 * click-detection procedure can start, in cases where the device
2487 * is configured for double-click detection.[get]
2488 *
2489 * @param ctx read / write interface definitions
2490 * @param val change the values of tw in reg TIME_WINDOW
2491 * @retval interface status (MANDATORY: return 0 -> no Error)
2492 *
2493 */
lis3dh_double_tap_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2494 int32_t lis3dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
2495 {
2496 lis3dh_time_window_t time_window;
2497 int32_t ret;
2498
2499 ret = lis3dh_read_reg(ctx, LIS3DH_TIME_WINDOW,
2500 (uint8_t *)&time_window, 1);
2501 *val = (uint8_t)time_window.tw;
2502
2503 return ret;
2504 }
2505
2506 /**
2507 * @}
2508 *
2509 */
2510
2511 /**
2512 * @defgroup LIS3DH_Activity_inactivity
2513 * @brief This section group all the functions concerning activity
2514 * inactivity functionality
2515 * @{
2516 *
2517 */
2518
2519 /**
2520 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2521 * low-power mode.[set]
2522 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2523 *
2524 * @param ctx read / write interface definitions
2525 * @param val change the values of acth in reg ACT_THS
2526 * @retval interface status (MANDATORY: return 0 -> no Error)
2527 *
2528 */
lis3dh_act_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2529 int32_t lis3dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2530 {
2531 lis3dh_act_ths_t act_ths;
2532 int32_t ret;
2533
2534 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2535
2536 if (ret == 0)
2537 {
2538 act_ths.acth = val;
2539 ret = lis3dh_write_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2540 }
2541
2542 return ret;
2543 }
2544
2545 /**
2546 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2547 * mode.[get]
2548 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2549 *
2550 * @param ctx read / write interface definitions
2551 * @param val change the values of acth in reg ACT_THS
2552 * @retval interface status (MANDATORY: return 0 -> no Error)
2553 *
2554 */
lis3dh_act_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2555 int32_t lis3dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2556 {
2557 lis3dh_act_ths_t act_ths;
2558 int32_t ret;
2559
2560 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_THS, (uint8_t *)&act_ths, 1);
2561 *val = (uint8_t)act_ths.acth;
2562
2563 return ret;
2564 }
2565
2566 /**
2567 * @brief Sleep-to-wake, return-to-sleep.[set]
2568 * duration = (8*1[LSb]+1)/ODR
2569 *
2570 * @param ctx read / write interface definitions
2571 * @param val change the values of actd in reg ACT_DUR
2572 * @retval interface status (MANDATORY: return 0 -> no Error)
2573 *
2574 */
lis3dh_act_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)2575 int32_t lis3dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
2576 {
2577 lis3dh_act_dur_t act_dur;
2578 int32_t ret;
2579
2580 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2581
2582 if (ret == 0)
2583 {
2584 act_dur.actd = val;
2585 ret = lis3dh_write_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2586 }
2587
2588 return ret;
2589 }
2590
2591 /**
2592 * @brief Sleep-to-wake, return-to-sleep.[get]
2593 * duration = (8*1[LSb]+1)/ODR
2594 *
2595 * @param ctx read / write interface definitions
2596 * @param val change the values of actd in reg ACT_DUR
2597 * @retval interface status (MANDATORY: return 0 -> no Error)
2598 *
2599 */
lis3dh_act_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)2600 int32_t lis3dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
2601 {
2602 lis3dh_act_dur_t act_dur;
2603 int32_t ret;
2604
2605 ret = lis3dh_read_reg(ctx, LIS3DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2606 *val = (uint8_t)act_dur.actd;
2607
2608 return ret;
2609 }
2610
2611 /**
2612 * @}
2613 *
2614 */
2615
2616 /**
2617 * @defgroup LIS3DH_Serial_interface
2618 * @brief This section group all the functions concerning serial
2619 * interface management
2620 * @{
2621 *
2622 */
2623
2624 /**
2625 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2626 *
2627 * @param ctx read / write interface definitions
2628 * @param val change the values of sdo_pu_disc in reg CTRL_REG0
2629 * @retval interface status (MANDATORY: return 0 -> no Error)
2630 *
2631 */
lis3dh_pin_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lis3dh_sdo_pu_disc_t val)2632 int32_t lis3dh_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2633 lis3dh_sdo_pu_disc_t val)
2634 {
2635 lis3dh_ctrl_reg0_t ctrl_reg0;
2636 int32_t ret;
2637
2638 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2639
2640 if (ret == 0)
2641 {
2642 ctrl_reg0.sdo_pu_disc = (uint8_t)val;
2643 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2644 }
2645
2646 return ret;
2647 }
2648
2649 /**
2650 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2651 *
2652 * @param ctx read / write interface definitions
2653 * @param val Get the values of sdo_pu_disc in reg CTRL_REG0
2654 * @retval interface status (MANDATORY: return 0 -> no Error)
2655 *
2656 */
lis3dh_pin_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lis3dh_sdo_pu_disc_t * val)2657 int32_t lis3dh_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2658 lis3dh_sdo_pu_disc_t *val)
2659 {
2660 lis3dh_ctrl_reg0_t ctrl_reg0;
2661 int32_t ret;
2662
2663 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG0, (uint8_t *)&ctrl_reg0, 1);
2664
2665 switch (ctrl_reg0.sdo_pu_disc)
2666 {
2667 case LIS3DH_PULL_UP_DISCONNECT:
2668 *val = LIS3DH_PULL_UP_DISCONNECT;
2669 break;
2670
2671 case LIS3DH_PULL_UP_CONNECT:
2672 *val = LIS3DH_PULL_UP_CONNECT;
2673 break;
2674
2675 default:
2676 *val = LIS3DH_PULL_UP_DISCONNECT;
2677 break;
2678 }
2679
2680 return ret;
2681 }
2682
2683 /**
2684 * @brief SPI Serial Interface Mode selection.[set]
2685 *
2686 * @param ctx read / write interface definitions
2687 * @param val change the values of sim in reg CTRL_REG4
2688 * @retval interface status (MANDATORY: return 0 -> no Error)
2689 *
2690 */
lis3dh_spi_mode_set(const stmdev_ctx_t * ctx,lis3dh_sim_t val)2691 int32_t lis3dh_spi_mode_set(const stmdev_ctx_t *ctx, lis3dh_sim_t val)
2692 {
2693 lis3dh_ctrl_reg4_t ctrl_reg4;
2694 int32_t ret;
2695
2696 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2697
2698 if (ret == 0)
2699 {
2700 ctrl_reg4.sim = (uint8_t)val;
2701 ret = lis3dh_write_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2702 }
2703
2704 return ret;
2705 }
2706
2707 /**
2708 * @brief SPI Serial Interface Mode selection.[get]
2709 *
2710 * @param ctx read / write interface definitions
2711 * @param val Get the values of sim in reg CTRL_REG4
2712 * @retval interface status (MANDATORY: return 0 -> no Error)
2713 *
2714 */
lis3dh_spi_mode_get(const stmdev_ctx_t * ctx,lis3dh_sim_t * val)2715 int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val)
2716 {
2717 lis3dh_ctrl_reg4_t ctrl_reg4;
2718 int32_t ret;
2719
2720 ret = lis3dh_read_reg(ctx, LIS3DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2721
2722 switch (ctrl_reg4.sim)
2723 {
2724 case LIS3DH_SPI_4_WIRE:
2725 *val = LIS3DH_SPI_4_WIRE;
2726 break;
2727
2728 case LIS3DH_SPI_3_WIRE:
2729 *val = LIS3DH_SPI_3_WIRE;
2730 break;
2731
2732 default:
2733 *val = LIS3DH_SPI_4_WIRE;
2734 break;
2735 }
2736
2737 return ret;
2738 }
2739
2740 /**
2741 * @}
2742 *
2743 */
2744
2745 /**
2746 * @}
2747 *
2748 */
2749
2750 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2751
