1 /** 2 ****************************************************************************** 3 * @file lis3de_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis3de_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS3DE_REGS_H 23 #define LIS3DE_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS3DE 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS3DE_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS3DE_I2C_ADD_L 0x31U 173 #define LIS3DE_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS3DE_ID 0x33U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS3DE_STATUS_REG_AUX 0x07U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t _1da : 1; 188 uint8_t _2da : 1; 189 uint8_t _3da : 1; 190 uint8_t _321da : 1; 191 uint8_t _1or : 1; 192 uint8_t _2or : 1; 193 uint8_t _3or : 1; 194 uint8_t _321or : 1; 195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 196 uint8_t _321or : 1; 197 uint8_t _3or : 1; 198 uint8_t _2or : 1; 199 uint8_t _1or : 1; 200 uint8_t _321da : 1; 201 uint8_t _3da : 1; 202 uint8_t _2da : 1; 203 uint8_t _1da : 1; 204 #endif /* DRV_BYTE_ORDER */ 205 } lis3de_status_reg_aux_t; 206 207 #define LIS3DE_OUT_ADC1_L 0x08U 208 #define LIS3DE_OUT_ADC1_H 0x09U 209 #define LIS3DE_OUT_ADC2_L 0x0AU 210 #define LIS3DE_OUT_ADC2_H 0x0BU 211 #define LIS3DE_OUT_ADC3_L 0x0CU 212 #define LIS3DE_OUT_ADC3_H 0x0DU 213 #define LIS3DE_INT_COUNTER_REG 0x0EU 214 #define LIS3DE_WHO_AM_I 0x0FU 215 216 #define LIS3DE_TEMP_CFG_REG 0x1FU 217 typedef struct 218 { 219 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 220 uint8_t not_used_01 : 6; 221 uint8_t adc_pd : 1; 222 uint8_t temp_en : 1; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t temp_en : 1; 225 uint8_t adc_pd : 1; 226 uint8_t not_used_01 : 6; 227 #endif /* DRV_BYTE_ORDER */ 228 } lis3de_temp_cfg_reg_t; 229 230 #define LIS3DE_CTRL_REG1 0x20U 231 typedef struct 232 { 233 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 234 uint8_t xen : 1; 235 uint8_t yen : 1; 236 uint8_t zen : 1; 237 uint8_t lpen : 1; 238 uint8_t odr : 4; 239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 240 uint8_t odr : 4; 241 uint8_t lpen : 1; 242 uint8_t zen : 1; 243 uint8_t yen : 1; 244 uint8_t xen : 1; 245 #endif /* DRV_BYTE_ORDER */ 246 } lis3de_ctrl_reg1_t; 247 248 #define LIS3DE_CTRL_REG2 0x21U 249 typedef struct 250 { 251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 252 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 253 uint8_t fds : 1; 254 uint8_t hpcf : 2; 255 uint8_t hpm : 2; 256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 257 uint8_t hpm : 2; 258 uint8_t hpcf : 2; 259 uint8_t fds : 1; 260 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 261 #endif /* DRV_BYTE_ORDER */ 262 } lis3de_ctrl_reg2_t; 263 264 #define LIS3DE_CTRL_REG3 0x22U 265 typedef struct 266 { 267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 268 uint8_t not_used_01 : 1; 269 uint8_t int1_overrun : 1; 270 uint8_t int1_wtm : 1; 271 uint8_t int1_drdy2 : 1; 272 uint8_t int1_drdy1 : 1; 273 uint8_t int1_ig2 : 1; 274 uint8_t int1_ig1 : 1; 275 uint8_t int1_click : 1; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t int1_click : 1; 278 uint8_t int1_ig1 : 1; 279 uint8_t int1_ig2 : 1; 280 uint8_t int1_drdy1 : 1; 281 uint8_t int1_drdy2 : 1; 282 uint8_t int1_wtm : 1; 283 uint8_t int1_overrun : 1; 284 uint8_t not_used_01 : 1; 285 #endif /* DRV_BYTE_ORDER */ 286 } lis3de_ctrl_reg3_t; 287 288 #define LIS3DE_CTRL_REG4 0x23U 289 typedef struct 290 { 291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 292 uint8_t sim : 1; 293 uint8_t st : 2; 294 uint8_t not_used_01 : 1; 295 uint8_t fs : 2; 296 uint8_t not_used_02 : 1; 297 uint8_t bdu : 1; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t bdu : 1; 300 uint8_t not_used_02 : 1; 301 uint8_t fs : 2; 302 uint8_t not_used_01 : 1; 303 uint8_t st : 2; 304 uint8_t sim : 1; 305 #endif /* DRV_BYTE_ORDER */ 306 } lis3de_ctrl_reg4_t; 307 308 #define LIS3DE_CTRL_REG5 0x24U 309 typedef struct 310 { 311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 312 uint8_t d4d_ig2 : 1; 313 uint8_t lir_ig2 : 1; 314 uint8_t d4d_ig1 : 1; 315 uint8_t lir_ig1 : 1; 316 uint8_t not_used_01 : 2; 317 uint8_t fifo_en : 1; 318 uint8_t boot : 1; 319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 320 uint8_t boot : 1; 321 uint8_t fifo_en : 1; 322 uint8_t not_used_01 : 2; 323 uint8_t lir_ig1 : 1; 324 uint8_t d4d_ig1 : 1; 325 uint8_t lir_ig2 : 1; 326 uint8_t d4d_ig2 : 1; 327 #endif /* DRV_BYTE_ORDER */ 328 } lis3de_ctrl_reg5_t; 329 330 #define LIS3DE_CTRL_REG6 0x25U 331 typedef struct 332 { 333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 334 uint8_t not_used_01 : 1; 335 uint8_t h_lactive : 1; 336 uint8_t not_used_02 : 1; 337 uint8_t int2_act : 1; 338 uint8_t int2_boot : 1; 339 uint8_t int2_ig2 : 1; 340 uint8_t int2_ig1 : 1; 341 uint8_t int2_click : 1; 342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 343 uint8_t int2_click : 1; 344 uint8_t int2_ig1 : 1; 345 uint8_t int2_ig2 : 1; 346 uint8_t int2_boot : 1; 347 uint8_t int2_act : 1; 348 uint8_t not_used_02 : 1; 349 uint8_t h_lactive : 1; 350 uint8_t not_used_01 : 1; 351 #endif /* DRV_BYTE_ORDER */ 352 } lis3de_ctrl_reg6_t; 353 354 #define LIS3DE_REFERENCE 0x26U 355 #define LIS3DE_STATUS_REG 0x27U 356 typedef struct 357 { 358 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 359 uint8_t xda : 1; 360 uint8_t yda : 1; 361 uint8_t zda : 1; 362 uint8_t zyxda : 1; 363 uint8_t _xor : 1; 364 uint8_t yor : 1; 365 uint8_t zor : 1; 366 uint8_t zyxor : 1; 367 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 368 uint8_t zyxor : 1; 369 uint8_t zor : 1; 370 uint8_t yor : 1; 371 uint8_t _xor : 1; 372 uint8_t zyxda : 1; 373 uint8_t zda : 1; 374 uint8_t yda : 1; 375 uint8_t xda : 1; 376 #endif /* DRV_BYTE_ORDER */ 377 } lis3de_status_reg_t; 378 379 #define LIS3DE_OUT_X 0x29U 380 #define LIS3DE_OUT_Y 0x2BU 381 #define LIS3DE_OUT_Z 0x2DU 382 #define LIS3DE_FIFO_CTRL_REG 0x2EU 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t fth : 5; 387 uint8_t tr : 1; 388 uint8_t fm : 2; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t fm : 2; 391 uint8_t tr : 1; 392 uint8_t fth : 5; 393 #endif /* DRV_BYTE_ORDER */ 394 } lis3de_fifo_ctrl_reg_t; 395 396 #define LIS3DE_FIFO_SRC_REG 0x2FU 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t fss : 5; 401 uint8_t empty : 1; 402 uint8_t ovrn_fifo : 1; 403 uint8_t wtm : 1; 404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 405 uint8_t wtm : 1; 406 uint8_t ovrn_fifo : 1; 407 uint8_t empty : 1; 408 uint8_t fss : 5; 409 #endif /* DRV_BYTE_ORDER */ 410 } lis3de_fifo_src_reg_t; 411 412 #define LIS3DE_IG1_CFG 0x30U 413 typedef struct 414 { 415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 416 uint8_t xlie : 1; 417 uint8_t xhie : 1; 418 uint8_t ylie : 1; 419 uint8_t yhie : 1; 420 uint8_t zlie : 1; 421 uint8_t zhie : 1; 422 uint8_t _6d : 1; 423 uint8_t aoi : 1; 424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 425 uint8_t aoi : 1; 426 uint8_t _6d : 1; 427 uint8_t zhie : 1; 428 uint8_t zlie : 1; 429 uint8_t yhie : 1; 430 uint8_t ylie : 1; 431 uint8_t xhie : 1; 432 uint8_t xlie : 1; 433 #endif /* DRV_BYTE_ORDER */ 434 } lis3de_ig1_cfg_t; 435 436 #define LIS3DE_IG1_SOURCE 0x31U 437 typedef struct 438 { 439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 440 uint8_t xl : 1; 441 uint8_t xh : 1; 442 uint8_t yl : 1; 443 uint8_t yh : 1; 444 uint8_t zl : 1; 445 uint8_t zh : 1; 446 uint8_t ia : 1; 447 uint8_t not_used_01 : 1; 448 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 449 uint8_t not_used_01 : 1; 450 uint8_t ia : 1; 451 uint8_t zh : 1; 452 uint8_t zl : 1; 453 uint8_t yh : 1; 454 uint8_t yl : 1; 455 uint8_t xh : 1; 456 uint8_t xl : 1; 457 #endif /* DRV_BYTE_ORDER */ 458 } lis3de_ig1_source_t; 459 460 #define LIS3DE_IG1_THS 0x32U 461 typedef struct 462 { 463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 464 uint8_t ths : 7; 465 uint8_t not_used_01 : 1; 466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 467 uint8_t not_used_01 : 1; 468 uint8_t ths : 7; 469 #endif /* DRV_BYTE_ORDER */ 470 } lis3de_ig1_ths_t; 471 472 #define LIS3DE_IG1_DURATION 0x33U 473 typedef struct 474 { 475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 476 uint8_t d : 7; 477 uint8_t not_used_01 : 1; 478 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 479 uint8_t not_used_01 : 1; 480 uint8_t d : 7; 481 #endif /* DRV_BYTE_ORDER */ 482 } lis3de_ig1_duration_t; 483 484 #define LIS3DE_IG2_CFG 0x34U 485 typedef struct 486 { 487 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 488 uint8_t xlie : 1; 489 uint8_t xhie : 1; 490 uint8_t ylie : 1; 491 uint8_t yhie : 1; 492 uint8_t zlie : 1; 493 uint8_t zhie : 1; 494 uint8_t _6d : 1; 495 uint8_t aoi : 1; 496 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 497 uint8_t aoi : 1; 498 uint8_t _6d : 1; 499 uint8_t zhie : 1; 500 uint8_t zlie : 1; 501 uint8_t yhie : 1; 502 uint8_t ylie : 1; 503 uint8_t xhie : 1; 504 uint8_t xlie : 1; 505 #endif /* DRV_BYTE_ORDER */ 506 } lis3de_ig2_cfg_t; 507 508 #define LIS3DE_IG2_SOURCE 0x35U 509 typedef struct 510 { 511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 512 uint8_t xl : 1; 513 uint8_t xh : 1; 514 uint8_t yl : 1; 515 uint8_t yh : 1; 516 uint8_t zl : 1; 517 uint8_t zh : 1; 518 uint8_t ia : 1; 519 uint8_t not_used_01 : 1; 520 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 521 uint8_t not_used_01 : 1; 522 uint8_t ia : 1; 523 uint8_t zh : 1; 524 uint8_t zl : 1; 525 uint8_t yh : 1; 526 uint8_t yl : 1; 527 uint8_t xh : 1; 528 uint8_t xl : 1; 529 #endif /* DRV_BYTE_ORDER */ 530 } lis3de_ig2_source_t; 531 532 #define LIS3DE_IG2_THS 0x36U 533 typedef struct 534 { 535 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 536 uint8_t ths : 7; 537 uint8_t not_used_01 : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t not_used_01 : 1; 540 uint8_t ths : 7; 541 #endif /* DRV_BYTE_ORDER */ 542 } lis3de_ig2_ths_t; 543 544 #define LIS3DE_IG2_DURATION 0x37U 545 typedef struct 546 { 547 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 548 uint8_t d : 7; 549 uint8_t not_used_01 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used_01 : 1; 552 uint8_t d : 7; 553 #endif /* DRV_BYTE_ORDER */ 554 } lis3de_ig2_duration_t; 555 556 #define LIS3DE_CLICK_CFG 0x38U 557 typedef struct 558 { 559 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 560 uint8_t xs : 1; 561 uint8_t xd : 1; 562 uint8_t ys : 1; 563 uint8_t yd : 1; 564 uint8_t zs : 1; 565 uint8_t zd : 1; 566 uint8_t not_used_01 : 2; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t not_used_01 : 2; 569 uint8_t zd : 1; 570 uint8_t zs : 1; 571 uint8_t yd : 1; 572 uint8_t ys : 1; 573 uint8_t xd : 1; 574 uint8_t xs : 1; 575 #endif /* DRV_BYTE_ORDER */ 576 } lis3de_click_cfg_t; 577 578 #define LIS3DE_CLICK_SRC 0x39U 579 typedef struct 580 { 581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 582 uint8_t x : 1; 583 uint8_t y : 1; 584 uint8_t z : 1; 585 uint8_t sign : 1; 586 uint8_t sclick : 1; 587 uint8_t dclick : 1; 588 uint8_t ia : 1; 589 uint8_t not_used_01 : 1; 590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 591 uint8_t not_used_01 : 1; 592 uint8_t ia : 1; 593 uint8_t dclick : 1; 594 uint8_t sclick : 1; 595 uint8_t sign : 1; 596 uint8_t z : 1; 597 uint8_t y : 1; 598 uint8_t x : 1; 599 #endif /* DRV_BYTE_ORDER */ 600 } lis3de_click_src_t; 601 602 #define LIS3DE_CLICK_THS 0x3AU 603 typedef struct 604 { 605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 606 uint8_t ths : 7; 607 uint8_t lir : 1; 608 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 609 uint8_t lir : 1; 610 uint8_t ths : 7; 611 #endif /* DRV_BYTE_ORDER */ 612 } lis3de_click_ths_t; 613 614 #define LIS3DE_TIME_LIMIT 0x3BU 615 typedef struct 616 { 617 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 618 uint8_t tli : 7; 619 uint8_t not_used_01 : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t not_used_01 : 1; 622 uint8_t tli : 7; 623 #endif /* DRV_BYTE_ORDER */ 624 } lis3de_time_limit_t; 625 626 #define LIS3DE_TIME_LATENCY 0x3CU 627 typedef struct 628 { 629 uint8_t tla : 8; 630 } lis3de_time_latency_t; 631 632 #define LIS3DE_TIME_WINDOW 0x3DU 633 typedef struct 634 { 635 uint8_t tw : 8; 636 } lis3de_time_window_t; 637 638 #define LIS3DE_ACT_THS 0x3EU 639 typedef struct 640 { 641 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 642 uint8_t acth : 7; 643 uint8_t not_used_01 : 1; 644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 645 uint8_t not_used_01 : 1; 646 uint8_t acth : 7; 647 #endif /* DRV_BYTE_ORDER */ 648 } lis3de_act_ths_t; 649 650 #define LIS3DE_ACT_DUR 0x3FU 651 typedef struct 652 { 653 uint8_t actd : 8; 654 } lis3de_act_dur_t; 655 656 /** 657 * @defgroup LIS3DE_Register_Union 658 * @brief This union group all the registers having a bit-field 659 * description. 660 * This union is useful but it's not needed by the driver. 661 * 662 * REMOVING this union you are compliant with: 663 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 664 * 665 * @{ 666 * 667 */ 668 typedef union 669 { 670 lis3de_status_reg_aux_t status_reg_aux; 671 lis3de_temp_cfg_reg_t temp_cfg_reg; 672 lis3de_ctrl_reg1_t ctrl_reg1; 673 lis3de_ctrl_reg2_t ctrl_reg2; 674 lis3de_ctrl_reg3_t ctrl_reg3; 675 lis3de_ctrl_reg4_t ctrl_reg4; 676 lis3de_ctrl_reg5_t ctrl_reg5; 677 lis3de_ctrl_reg6_t ctrl_reg6; 678 lis3de_status_reg_t status_reg; 679 lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; 680 lis3de_fifo_src_reg_t fifo_src_reg; 681 lis3de_ig1_cfg_t int1_cfg; 682 lis3de_ig1_source_t int1_src; 683 lis3de_ig1_ths_t int1_ths; 684 lis3de_ig1_duration_t int1_duration; 685 lis3de_ig2_cfg_t int2_cfg; 686 lis3de_ig2_source_t int2_src; 687 lis3de_ig2_ths_t int2_ths; 688 lis3de_ig2_duration_t int2_duration; 689 lis3de_click_cfg_t click_cfg; 690 lis3de_click_src_t click_src; 691 lis3de_click_ths_t click_ths; 692 lis3de_time_limit_t time_limit; 693 lis3de_time_latency_t time_latency; 694 lis3de_time_window_t time_window; 695 lis3de_act_ths_t act_ths; 696 lis3de_act_dur_t act_dur; 697 bitwise_t bitwise; 698 uint8_t byte; 699 } lis3de_reg_t; 700 701 /** 702 * @} 703 * 704 */ 705 706 #ifndef __weak 707 #define __weak __attribute__((weak)) 708 #endif /* __weak */ 709 710 /* 711 * These are the basic platform dependent I/O routines to read 712 * and write device registers connected on a standard bus. 713 * The driver keeps offering a default implementation based on function 714 * pointers to read/write routines for backward compatibility. 715 * The __weak directive allows the final application to overwrite 716 * them with a custom implementation. 717 */ 718 719 int32_t lis3de_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 720 uint16_t len); 721 int32_t lis3de_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 722 uint8_t *data, 723 uint16_t len); 724 725 float_t lis3de_from_fs2_to_mg(int16_t lsb); 726 float_t lis3de_from_fs4_to_mg(int16_t lsb); 727 float_t lis3de_from_fs8_to_mg(int16_t lsb); 728 float_t lis3de_from_fs16_to_mg(int16_t lsb); 729 730 float_t lis3de_from_lsb_to_celsius(int16_t lsb); 731 732 int32_t lis3de_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); 733 int32_t lis3de_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 734 735 int32_t lis3de_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 736 737 int32_t lis3de_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 738 int32_t lis3de_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 739 740 typedef enum 741 { 742 LIS3DE_AUX_DISABLE = 0, 743 LIS3DE_AUX_ON_TEMPERATURE = 3, 744 LIS3DE_AUX_ON_PADS = 1, 745 } lis3de_temp_en_t; 746 int32_t lis3de_aux_adc_set(const stmdev_ctx_t *ctx, lis3de_temp_en_t val); 747 int32_t lis3de_aux_adc_get(const stmdev_ctx_t *ctx, lis3de_temp_en_t *val); 748 749 typedef enum 750 { 751 LIS3DE_NM = 0, 752 LIS3DE_LP = 1, 753 } lis3de_op_md_t; 754 int32_t lis3de_operating_mode_set(const stmdev_ctx_t *ctx, 755 lis3de_op_md_t val); 756 int32_t lis3de_operating_mode_get(const stmdev_ctx_t *ctx, 757 lis3de_op_md_t *val); 758 759 typedef enum 760 { 761 LIS3DE_POWER_DOWN = 0x00, 762 LIS3DE_ODR_1Hz = 0x01, 763 LIS3DE_ODR_10Hz = 0x02, 764 LIS3DE_ODR_25Hz = 0x03, 765 LIS3DE_ODR_50Hz = 0x04, 766 LIS3DE_ODR_100Hz = 0x05, 767 LIS3DE_ODR_200Hz = 0x06, 768 LIS3DE_ODR_400Hz = 0x07, 769 LIS3DE_ODR_1kHz6 = 0x08, 770 LIS3DE_ODR_5kHz376_LP_1kHz344_NM = 0x09, 771 } lis3de_odr_t; 772 int32_t lis3de_data_rate_set(const stmdev_ctx_t *ctx, lis3de_odr_t val); 773 int32_t lis3de_data_rate_get(const stmdev_ctx_t *ctx, lis3de_odr_t *val); 774 775 int32_t lis3de_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, 776 uint8_t val); 777 int32_t lis3de_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, 778 uint8_t *val); 779 780 typedef enum 781 { 782 LIS3DE_AGGRESSIVE = 0, 783 LIS3DE_STRONG = 1, 784 LIS3DE_MEDIUM = 2, 785 LIS3DE_LIGHT = 3, 786 } lis3de_hpcf_t; 787 int32_t lis3de_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, 788 lis3de_hpcf_t val); 789 int32_t lis3de_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, 790 lis3de_hpcf_t *val); 791 792 typedef enum 793 { 794 LIS3DE_NORMAL_WITH_RST = 0, 795 LIS3DE_REFERENCE_MODE = 1, 796 LIS3DE_NORMAL = 2, 797 LIS3DE_AUTORST_ON_INT = 3, 798 } lis3de_hpm_t; 799 int32_t lis3de_high_pass_mode_set(const stmdev_ctx_t *ctx, 800 lis3de_hpm_t val); 801 int32_t lis3de_high_pass_mode_get(const stmdev_ctx_t *ctx, 802 lis3de_hpm_t *val); 803 804 typedef enum 805 { 806 LIS3DE_2g = 0, 807 LIS3DE_4g = 1, 808 LIS3DE_8g = 2, 809 LIS3DE_16g = 3, 810 } lis3de_fs_t; 811 int32_t lis3de_full_scale_set(const stmdev_ctx_t *ctx, lis3de_fs_t val); 812 int32_t lis3de_full_scale_get(const stmdev_ctx_t *ctx, lis3de_fs_t *val); 813 814 int32_t lis3de_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 815 int32_t lis3de_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 816 817 int32_t lis3de_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); 818 int32_t lis3de_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); 819 820 int32_t lis3de_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 821 822 int32_t lis3de_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 823 824 int32_t lis3de_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 825 826 int32_t lis3de_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 827 828 typedef enum 829 { 830 LIS3DE_ST_DISABLE = 0, 831 LIS3DE_ST_POSITIVE = 1, 832 LIS3DE_ST_NEGATIVE = 2, 833 } lis3de_st_t; 834 int32_t lis3de_self_test_set(const stmdev_ctx_t *ctx, lis3de_st_t val); 835 int32_t lis3de_self_test_get(const stmdev_ctx_t *ctx, lis3de_st_t *val); 836 837 int32_t lis3de_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 838 int32_t lis3de_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 839 840 int32_t lis3de_status_get(const stmdev_ctx_t *ctx, 841 lis3de_status_reg_t *val); 842 843 int32_t lis3de_int1_gen_conf_set(const stmdev_ctx_t *ctx, 844 lis3de_ig1_cfg_t *val); 845 int32_t lis3de_int1_gen_conf_get(const stmdev_ctx_t *ctx, 846 lis3de_ig1_cfg_t *val); 847 848 int32_t lis3de_int1_gen_source_get(const stmdev_ctx_t *ctx, 849 lis3de_ig1_source_t *val); 850 851 int32_t lis3de_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 852 int32_t lis3de_int1_gen_threshold_get(const stmdev_ctx_t *ctx, 853 uint8_t *val); 854 855 int32_t lis3de_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 856 int32_t lis3de_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 857 858 int32_t lis3de_int2_gen_conf_set(const stmdev_ctx_t *ctx, 859 lis3de_ig2_cfg_t *val); 860 int32_t lis3de_int2_gen_conf_get(const stmdev_ctx_t *ctx, 861 lis3de_ig2_cfg_t *val); 862 863 int32_t lis3de_int2_gen_source_get(const stmdev_ctx_t *ctx, 864 lis3de_ig2_source_t *val); 865 866 int32_t lis3de_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 867 int32_t lis3de_int2_gen_threshold_get(const stmdev_ctx_t *ctx, 868 uint8_t *val); 869 870 int32_t lis3de_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 871 int32_t lis3de_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 872 873 typedef enum 874 { 875 LIS3DE_DISC_FROM_INT_GENERATOR = 0, 876 LIS3DE_ON_INT1_GEN = 1, 877 LIS3DE_ON_INT2_GEN = 2, 878 LIS3DE_ON_TAP_GEN = 4, 879 LIS3DE_ON_INT1_INT2_GEN = 3, 880 LIS3DE_ON_INT1_TAP_GEN = 5, 881 LIS3DE_ON_INT2_TAP_GEN = 6, 882 LIS3DE_ON_INT1_INT2_TAP_GEN = 7, 883 } lis3de_hp_t; 884 int32_t lis3de_high_pass_int_conf_set(const stmdev_ctx_t *ctx, 885 lis3de_hp_t val); 886 int32_t lis3de_high_pass_int_conf_get(const stmdev_ctx_t *ctx, 887 lis3de_hp_t *val); 888 889 int32_t lis3de_pin_int1_config_set(const stmdev_ctx_t *ctx, 890 lis3de_ctrl_reg3_t *val); 891 int32_t lis3de_pin_int1_config_get(const stmdev_ctx_t *ctx, 892 lis3de_ctrl_reg3_t *val); 893 894 int32_t lis3de_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); 895 int32_t lis3de_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, 896 uint8_t *val); 897 898 typedef enum 899 { 900 LIS3DE_INT2_PULSED = 0, 901 LIS3DE_INT2_LATCHED = 1, 902 } lis3de_lir_int2_t; 903 int32_t lis3de_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, 904 lis3de_lir_int2_t val); 905 int32_t lis3de_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, 906 lis3de_lir_int2_t *val); 907 908 int32_t lis3de_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); 909 int32_t lis3de_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, 910 uint8_t *val); 911 912 typedef enum 913 { 914 LIS3DE_INT1_PULSED = 0, 915 LIS3DE_INT1_LATCHED = 1, 916 } lis3de_lir_int1_t; 917 int32_t lis3de_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, 918 lis3de_lir_int1_t val); 919 int32_t lis3de_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, 920 lis3de_lir_int1_t *val); 921 922 int32_t lis3de_pin_int2_config_set(const stmdev_ctx_t *ctx, 923 lis3de_ctrl_reg6_t *val); 924 int32_t lis3de_pin_int2_config_get(const stmdev_ctx_t *ctx, 925 lis3de_ctrl_reg6_t *val); 926 927 int32_t lis3de_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 928 int32_t lis3de_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 929 930 int32_t lis3de_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 931 int32_t lis3de_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 932 933 typedef enum 934 { 935 LIS3DE_INT1_GEN = 0, 936 LIS3DE_INT2_GEN = 1, 937 } lis3de_tr_t; 938 int32_t lis3de_fifo_trigger_event_set(const stmdev_ctx_t *ctx, 939 lis3de_tr_t val); 940 int32_t lis3de_fifo_trigger_event_get(const stmdev_ctx_t *ctx, 941 lis3de_tr_t *val); 942 943 typedef enum 944 { 945 LIS3DE_BYPASS_MODE = 0, 946 LIS3DE_FIFO_MODE = 1, 947 LIS3DE_DYNAMIC_STREAM_MODE = 2, 948 LIS3DE_STREAM_TO_FIFO_MODE = 3, 949 } lis3de_fm_t; 950 int32_t lis3de_fifo_mode_set(const stmdev_ctx_t *ctx, lis3de_fm_t val); 951 int32_t lis3de_fifo_mode_get(const stmdev_ctx_t *ctx, lis3de_fm_t *val); 952 953 int32_t lis3de_fifo_status_get(const stmdev_ctx_t *ctx, 954 lis3de_fifo_src_reg_t *val); 955 956 int32_t lis3de_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 957 958 int32_t lis3de_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 959 960 int32_t lis3de_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 961 962 int32_t lis3de_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 963 964 int32_t lis3de_tap_conf_set(const stmdev_ctx_t *ctx, 965 lis3de_click_cfg_t *val); 966 int32_t lis3de_tap_conf_get(const stmdev_ctx_t *ctx, 967 lis3de_click_cfg_t *val); 968 969 int32_t lis3de_tap_source_get(const stmdev_ctx_t *ctx, 970 lis3de_click_src_t *val); 971 972 int32_t lis3de_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 973 int32_t lis3de_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 974 975 typedef enum 976 { 977 LIS3DE_TAP_PULSED = 0, 978 LIS3DE_TAP_LATCHED = 1, 979 } lis3de_lir_t; 980 int32_t lis3de_tap_notification_mode_set(const stmdev_ctx_t *ctx, 981 lis3de_lir_t val); 982 int32_t lis3de_tap_notification_mode_get(const stmdev_ctx_t *ctx, 983 lis3de_lir_t *val); 984 985 int32_t lis3de_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 986 int32_t lis3de_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 987 988 int32_t lis3de_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 989 int32_t lis3de_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 990 991 int32_t lis3de_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 992 int32_t lis3de_double_tap_timeout_get(const stmdev_ctx_t *ctx, 993 uint8_t *val); 994 995 int32_t lis3de_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 996 int32_t lis3de_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 997 998 int32_t lis3de_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 999 int32_t lis3de_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 1000 1001 typedef enum 1002 { 1003 LIS3DE_SPI_4_WIRE = 0, 1004 LIS3DE_SPI_3_WIRE = 1, 1005 } lis3de_sim_t; 1006 int32_t lis3de_spi_mode_set(const stmdev_ctx_t *ctx, lis3de_sim_t val); 1007 int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val); 1008 1009 /** 1010 * @} 1011 * 1012 */ 1013 1014 #ifdef __cplusplus 1015 } 1016 #endif 1017 1018 #endif /* LIS3DE_REGS_H */ 1019 1020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1021
