1 /**
2 ******************************************************************************
3 * @file lis2mdl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2MDL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2mdl_reg.h"
21
22 /**
23 * @defgroup LIS2MDL
24 * @brief This file provides a set of functions needed to drive the
25 * lis2mdl enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2MDL_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2mdl_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis2mdl_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis2mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS2MDL_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
lis2mdl_from_lsb_to_mgauss(int16_t lsb)102 float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb)
103 {
104 return ((float_t)lsb * 1.5f);
105 }
106
lis2mdl_from_lsb_to_celsius(int16_t lsb)107 float_t lis2mdl_from_lsb_to_celsius(int16_t lsb)
108 {
109 return (((float_t)lsb / 8.0f) + 25.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup LIS2MDL_data_generation
119 * @brief This section group all the functions concerning
120 * data generation
121 * @{
122 *
123 */
124
125 /**
126 * @brief These registers comprise a 3 group of 16-bit number and represent
127 * hard-iron offset in order to compensate environmental effects.
128 * Data format is the same of output data raw: two’s complement
129 * with 1LSb = 1.5mG. These values act on the magnetic output data
130 * value in order to delete the environmental offset.[set]
131 *
132 * @param ctx read / write interface definitions.(ptr)
133 * @param buff buffer that contains data to write
134 * @retval interface status.(MANDATORY: return 0 -> no Error)
135 *
136 */
lis2mdl_mag_user_offset_set(const stmdev_ctx_t * ctx,int16_t * val)137 int32_t lis2mdl_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
138 {
139 uint8_t buff[6];
140 int32_t ret;
141
142 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
143 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
144 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
145 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
146 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
147 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
148 ret = lis2mdl_write_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
149
150 return ret;
151 }
152
153 /**
154 * @brief These registers comprise a 3 group of 16-bit number and represent
155 * hard-iron offset in order to compensate environmental effects.
156 * Data format is the same of output data raw: two’s complement
157 * with 1LSb = 1.5mG. These values act on the magnetic output data
158 * value in order to delete the environmental offset.[get]
159 *
160 * @param ctx read / write interface definitions.(ptr)
161 * @param buff that stores data read
162 * @retval interface status.(MANDATORY: return 0 -> no Error)
163 *
164 */
lis2mdl_mag_user_offset_get(const stmdev_ctx_t * ctx,int16_t * val)165 int32_t lis2mdl_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
166 {
167 uint8_t buff[6];
168 int32_t ret;
169
170 ret = lis2mdl_read_reg(ctx, LIS2MDL_OFFSET_X_REG_L, buff, 6);
171 val[0] = (int16_t)buff[1];
172 val[0] = (val[0] * 256) + (int16_t)buff[0];
173 val[1] = (int16_t)buff[3];
174 val[1] = (val[1] * 256) + (int16_t)buff[2];
175 val[2] = (int16_t)buff[5];
176 val[2] = (val[2] * 256) + (int16_t)buff[4];
177
178 return ret;
179 }
180
181 /**
182 * @brief Operating mode selection.[set]
183 *
184 * @param ctx read / write interface definitions.(ptr)
185 * @param val change the values of md in reg CFG_REG_A
186 * @retval interface status.(MANDATORY: return 0 -> no Error)
187 *
188 */
lis2mdl_operating_mode_set(const stmdev_ctx_t * ctx,lis2mdl_md_t val)189 int32_t lis2mdl_operating_mode_set(const stmdev_ctx_t *ctx,
190 lis2mdl_md_t val)
191 {
192 lis2mdl_cfg_reg_a_t reg;
193 int32_t ret;
194
195 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
196
197 if (ret == 0)
198 {
199 reg.md = (uint8_t)val;
200 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
201 }
202
203 return ret;
204 }
205
206 /**
207 * @brief Operating mode selection.[get]
208 *
209 * @param ctx read / write interface definitions.(ptr)
210 * @param val Get the values of md in reg CFG_REG_A.(ptr)
211 * @retval interface status.(MANDATORY: return 0 -> no Error)
212 *
213 */
lis2mdl_operating_mode_get(const stmdev_ctx_t * ctx,lis2mdl_md_t * val)214 int32_t lis2mdl_operating_mode_get(const stmdev_ctx_t *ctx,
215 lis2mdl_md_t *val)
216 {
217 lis2mdl_cfg_reg_a_t reg;
218 int32_t ret;
219
220 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
221
222 switch (reg.md)
223 {
224 case LIS2MDL_POWER_DOWN:
225 *val = LIS2MDL_POWER_DOWN;
226 break;
227
228 case LIS2MDL_CONTINUOUS_MODE:
229 *val = LIS2MDL_CONTINUOUS_MODE;
230 break;
231
232 case LIS2MDL_SINGLE_TRIGGER:
233 *val = LIS2MDL_SINGLE_TRIGGER;
234 break;
235
236 default:
237 *val = LIS2MDL_POWER_DOWN;
238 break;
239 }
240
241 return ret;
242 }
243
244 /**
245 * @brief Output data rate selection.[set]
246 *
247 * @param ctx read / write interface definitions.(ptr)
248 * @param val change the values of odr in reg CFG_REG_A
249 * @retval interface status.(MANDATORY: return 0 -> no Error)
250 *
251 */
lis2mdl_data_rate_set(const stmdev_ctx_t * ctx,lis2mdl_odr_t val)252 int32_t lis2mdl_data_rate_set(const stmdev_ctx_t *ctx, lis2mdl_odr_t val)
253 {
254 lis2mdl_cfg_reg_a_t reg;
255 int32_t ret;
256
257 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
258
259 if (ret == 0)
260 {
261 reg.odr = (uint8_t)val;
262 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
263 }
264
265 return ret;
266 }
267
268 /**
269 * @brief Output data rate selection.[get]
270 *
271 * @param ctx read / write interface definitions.(ptr)
272 * @param val Get the values of odr in reg CFG_REG_A.(ptr)
273 * @retval interface status.(MANDATORY: return 0 -> no Error)
274 *
275 */
lis2mdl_data_rate_get(const stmdev_ctx_t * ctx,lis2mdl_odr_t * val)276 int32_t lis2mdl_data_rate_get(const stmdev_ctx_t *ctx, lis2mdl_odr_t *val)
277 {
278 lis2mdl_cfg_reg_a_t reg;
279 int32_t ret;
280
281 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
282
283 switch (reg.odr)
284 {
285 case LIS2MDL_ODR_10Hz:
286 *val = LIS2MDL_ODR_10Hz;
287 break;
288
289 case LIS2MDL_ODR_20Hz:
290 *val = LIS2MDL_ODR_20Hz;
291 break;
292
293 case LIS2MDL_ODR_50Hz:
294 *val = LIS2MDL_ODR_50Hz;
295 break;
296
297 case LIS2MDL_ODR_100Hz:
298 *val = LIS2MDL_ODR_100Hz;
299 break;
300
301 default:
302 *val = LIS2MDL_ODR_10Hz;
303 break;
304 }
305
306 return ret;
307 }
308
309 /**
310 * @brief Enables high-resolution/low-power mode.[set]
311 *
312 * @param ctx read / write interface definitions.(ptr)
313 * @param val change the values of lp in reg CFG_REG_A
314 * @retval interface status.(MANDATORY: return 0 -> no Error)
315 *
316 */
lis2mdl_power_mode_set(const stmdev_ctx_t * ctx,lis2mdl_lp_t val)317 int32_t lis2mdl_power_mode_set(const stmdev_ctx_t *ctx, lis2mdl_lp_t val)
318 {
319 lis2mdl_cfg_reg_a_t reg;
320 int32_t ret;
321
322 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
323
324 if (ret == 0)
325 {
326 reg.lp = (uint8_t)val;
327 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Enables high-resolution/low-power mode.[get]
335 *
336 * @param ctx read / write interface definitions.(ptr)
337 * @param val Get the values of lp in reg CFG_REG_A.(ptr)
338 * @retval interface status.(MANDATORY: return 0 -> no Error)
339 *
340 */
lis2mdl_power_mode_get(const stmdev_ctx_t * ctx,lis2mdl_lp_t * val)341 int32_t lis2mdl_power_mode_get(const stmdev_ctx_t *ctx, lis2mdl_lp_t *val)
342 {
343 lis2mdl_cfg_reg_a_t reg;
344 int32_t ret;
345
346 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
347
348 switch (reg.lp)
349 {
350 case LIS2MDL_HIGH_RESOLUTION:
351 *val = LIS2MDL_HIGH_RESOLUTION;
352 break;
353
354 case LIS2MDL_LOW_POWER:
355 *val = LIS2MDL_LOW_POWER;
356 break;
357
358 default:
359 *val = LIS2MDL_HIGH_RESOLUTION;
360 break;
361 }
362
363 return ret;
364 }
365
366 /**
367 * @brief Enables the magnetometer temperature compensation.[set]
368 *
369 * @param ctx read / write interface definitions.(ptr)
370 * @param val change the values of comp_temp_en in reg CFG_REG_A
371 * @retval interface status.(MANDATORY: return 0 -> no Error)
372 *
373 */
lis2mdl_offset_temp_comp_set(const stmdev_ctx_t * ctx,uint8_t val)374 int32_t lis2mdl_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val)
375 {
376 lis2mdl_cfg_reg_a_t reg;
377 int32_t ret;
378
379 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
380
381 if (ret == 0)
382 {
383 reg.comp_temp_en = val;
384 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
385 }
386
387 return ret;
388 }
389
390 /**
391 * @brief Enables the magnetometer temperature compensation.[get]
392 *
393 * @param ctx read / write interface definitions.(ptr)
394 * @param val change the values of comp_temp_en in reg CFG_REG_A.(ptr)
395 * @retval interface status.(MANDATORY: return 0 -> no Error)
396 *
397 */
lis2mdl_offset_temp_comp_get(const stmdev_ctx_t * ctx,uint8_t * val)398 int32_t lis2mdl_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val)
399 {
400 lis2mdl_cfg_reg_a_t reg;
401 int32_t ret;
402
403 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
404 *val = reg.comp_temp_en;
405
406 return ret;
407 }
408
409 /**
410 * @brief Low-pass bandwidth selection.[set]
411 *
412 * @param ctx read / write interface definitions.(ptr)
413 * @param val change the values of lpf in reg CFG_REG_B
414 * @retval interface status.(MANDATORY: return 0 -> no Error)
415 *
416 */
lis2mdl_low_pass_bandwidth_set(const stmdev_ctx_t * ctx,lis2mdl_lpf_t val)417 int32_t lis2mdl_low_pass_bandwidth_set(const stmdev_ctx_t *ctx,
418 lis2mdl_lpf_t val)
419 {
420 lis2mdl_cfg_reg_b_t reg;
421 int32_t ret;
422
423 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
424
425 if (ret == 0)
426 {
427 reg.lpf = (uint8_t)val;
428 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
429 }
430
431 return ret;
432 }
433
434 /**
435 * @brief Low-pass bandwidth selection.[get]
436 *
437 * @param ctx read / write interface definitions.(ptr)
438 * @param val Get the values of lpf in reg CFG_REG_B.(ptr)
439 * @retval interface status.(MANDATORY: return 0 -> no Error)
440 *
441 */
lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t * ctx,lis2mdl_lpf_t * val)442 int32_t lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t *ctx,
443 lis2mdl_lpf_t *val)
444 {
445 lis2mdl_cfg_reg_b_t reg;
446 int32_t ret;
447
448 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
449
450 switch (reg.lpf)
451 {
452 case LIS2MDL_ODR_DIV_2:
453 *val = LIS2MDL_ODR_DIV_2;
454 break;
455
456 case LIS2MDL_ODR_DIV_4:
457 *val = LIS2MDL_ODR_DIV_4;
458 break;
459
460 default:
461 *val = LIS2MDL_ODR_DIV_2;
462 break;
463 }
464
465 return ret;
466 }
467
468 /**
469 * @brief Reset mode.[set]
470 *
471 * @param ctx read / write interface definitions.(ptr)
472 * @param val change the values of set_rst in reg CFG_REG_B
473 * @retval interface status.(MANDATORY: return 0 -> no Error)
474 *
475 */
lis2mdl_set_rst_mode_set(const stmdev_ctx_t * ctx,lis2mdl_set_rst_t val)476 int32_t lis2mdl_set_rst_mode_set(const stmdev_ctx_t *ctx,
477 lis2mdl_set_rst_t val)
478 {
479 lis2mdl_cfg_reg_b_t reg;
480 int32_t ret;
481
482 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
483
484 if (ret == 0)
485 {
486 reg.set_rst = (uint8_t)val;
487 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
488 }
489
490 return ret;
491 }
492
493 /**
494 * @brief Reset mode.[get]
495 *
496 * @param ctx read / write interface definitions.(ptr)
497 * @param val Get the values of set_rst in reg CFG_REG_B.(ptr)
498 * @retval interface status.(MANDATORY: return 0 -> no Error)
499 *
500 */
lis2mdl_set_rst_mode_get(const stmdev_ctx_t * ctx,lis2mdl_set_rst_t * val)501 int32_t lis2mdl_set_rst_mode_get(const stmdev_ctx_t *ctx,
502 lis2mdl_set_rst_t *val)
503 {
504 lis2mdl_cfg_reg_b_t reg;
505 int32_t ret;
506
507 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
508
509 switch (reg.set_rst)
510 {
511 case LIS2MDL_SET_SENS_ODR_DIV_63:
512 *val = LIS2MDL_SET_SENS_ODR_DIV_63;
513 break;
514
515 case LIS2MDL_SENS_OFF_CANC_EVERY_ODR:
516 *val = LIS2MDL_SENS_OFF_CANC_EVERY_ODR;
517 break;
518
519 case LIS2MDL_SET_SENS_ONLY_AT_POWER_ON:
520 *val = LIS2MDL_SET_SENS_ONLY_AT_POWER_ON;
521 break;
522
523 default:
524 *val = LIS2MDL_SET_SENS_ODR_DIV_63;
525 break;
526 }
527
528 return ret;
529 }
530
531 /**
532 * @brief Enables offset cancellation in single measurement mode.
533 * The OFF_CANC bit must be set to 1 when enabling offset
534 * cancellation in single measurement mode this means a
535 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR)
536 * is need.[set]
537 *
538 * @param ctx read / write interface definitions.(ptr)
539 * @param val change the values of off_canc_one_shot in reg CFG_REG_B
540 * @retval interface status.(MANDATORY: return 0 -> no Error)
541 *
542 */
lis2mdl_set_rst_sensor_single_set(const stmdev_ctx_t * ctx,uint8_t val)543 int32_t lis2mdl_set_rst_sensor_single_set(const stmdev_ctx_t *ctx,
544 uint8_t val)
545 {
546 lis2mdl_cfg_reg_b_t reg;
547 int32_t ret;
548
549 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
550
551 if (ret == 0)
552 {
553 reg.off_canc_one_shot = val;
554 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
555 }
556
557 return ret;
558 }
559
560 /**
561 * @brief Enables offset cancellation in single measurement mode.
562 * The OFF_CANC bit must be set to 1 when enabling offset
563 * cancellation in single measurement mode this means a
564 * call function: set_rst_mode(SENS_OFF_CANC_EVERY_ODR)
565 * is need.[get]
566 *
567 * @param ctx read / write interface definitions.(ptr)
568 * @param val change the values of off_canc_one_shot in reg CFG_REG_B.(ptr)
569 * @retval interface status.(MANDATORY: return 0 -> no Error)
570 *
571 */
lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t * ctx,uint8_t * val)572 int32_t lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t *ctx,
573 uint8_t *val)
574 {
575 lis2mdl_cfg_reg_b_t reg;
576 int32_t ret;
577
578 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
579 *val = reg.off_canc_one_shot;
580
581 return ret;
582 }
583
584 /**
585 * @brief Blockdataupdate.[set]
586 *
587 * @param ctx read / write interface definitions.(ptr)
588 * @param val change the values of bdu in reg CFG_REG_C
589 * @retval interface status.(MANDATORY: return 0 -> no Error)
590 *
591 */
lis2mdl_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)592 int32_t lis2mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
593 {
594 lis2mdl_cfg_reg_c_t reg;
595 int32_t ret;
596
597 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
598
599 if (ret == 0)
600 {
601 reg.bdu = val;
602 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
603 }
604
605 return ret;
606 }
607
608 /**
609 * @brief Blockdataupdate.[get]
610 *
611 * @param ctx read / write interface definitions.(ptr)
612 * @param val change the values of bdu in reg CFG_REG_C.(ptr)
613 * @retval interface status.(MANDATORY: return 0 -> no Error)
614 *
615 */
lis2mdl_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)616 int32_t lis2mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
617 {
618 lis2mdl_cfg_reg_c_t reg;
619 int32_t ret;
620
621 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
622 *val = reg.bdu;
623
624 return ret;
625 }
626
627 /**
628 * @brief Magnetic set of data available.[get]
629 *
630 * @param ctx read / write interface definitions.(ptr)
631 * @param val change the values of zyxda in reg STATUS_REG.(ptr)
632 * @retval interface status.(MANDATORY: return 0 -> no Error)
633 *
634 */
lis2mdl_mag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)635 int32_t lis2mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
636 {
637 lis2mdl_status_reg_t reg;
638 int32_t ret;
639
640 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
641 *val = reg.zyxda;
642
643 return ret;
644 }
645
646 /**
647 * @brief Magnetic set of data overrun.[get]
648 *
649 * @param ctx read / write interface definitions.(ptr)
650 * @param val change the values of zyxor in reg STATUS_REG.(ptr)
651 * @retval interface status.(MANDATORY: return 0 -> no Error)
652 *
653 */
lis2mdl_mag_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)654 int32_t lis2mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
655 {
656 lis2mdl_status_reg_t reg;
657 int32_t ret;
658
659 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *)®, 1);
660 *val = reg.zyxor;
661
662 return ret;
663 }
664
665 /**
666 * @brief Magnetic output value.[get]
667 *
668 * @param ctx read / write interface definitions.(ptr)
669 * @param buff that stores data read
670 * @retval interface status.(MANDATORY: return 0 -> no Error)
671 *
672 */
lis2mdl_magnetic_raw_get(const stmdev_ctx_t * ctx,int16_t * val)673 int32_t lis2mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
674 {
675 uint8_t buff[6];
676 int32_t ret;
677
678 ret = lis2mdl_read_reg(ctx, LIS2MDL_OUTX_L_REG, buff, 6);
679 val[0] = (int16_t)buff[1];
680 val[0] = (val[0] * 256) + (int16_t)buff[0];
681 val[1] = (int16_t)buff[3];
682 val[1] = (val[1] * 256) + (int16_t)buff[2];
683 val[2] = (int16_t)buff[5];
684 val[2] = (val[2] * 256) + (int16_t)buff[4];
685
686 return ret;
687 }
688
689 /**
690 * @brief Temperature output value.[get]
691 *
692 * @param ctx read / write interface definitions.(ptr)
693 * @param buff that stores data read
694 * @retval interface status.(MANDATORY: return 0 -> no Error)
695 *
696 */
lis2mdl_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)697 int32_t lis2mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
698 {
699 uint8_t buff[2];
700 int32_t ret;
701
702 ret = lis2mdl_read_reg(ctx, LIS2MDL_TEMP_OUT_L_REG, buff, 2);
703 *val = (int16_t)buff[1];
704 *val = (*val * 256) + (int16_t)buff[0];
705
706 return ret;
707 }
708
709 /**
710 * @}
711 *
712 */
713
714 /**
715 * @defgroup LIS2MDL_common
716 * @brief This section group common useful functions
717 * @{
718 *
719 */
720
721 /**
722 * @brief DeviceWhoamI.[get]
723 *
724 * @param ctx read / write interface definitions.(ptr)
725 * @param buff that stores data read
726 * @retval interface status.(MANDATORY: return 0 -> no Error)
727 *
728 */
lis2mdl_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)729 int32_t lis2mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
730 {
731 int32_t ret;
732
733 ret = lis2mdl_read_reg(ctx, LIS2MDL_WHO_AM_I, buff, 1);
734
735 return ret;
736 }
737
738 /**
739 * @brief Software reset. Restore the default values in user registers.[set]
740 *
741 * @param ctx read / write interface definitions.(ptr)
742 * @param val change the values of soft_rst in reg CFG_REG_A
743 * @retval interface status.(MANDATORY: return 0 -> no Error)
744 *
745 */
lis2mdl_reset_set(const stmdev_ctx_t * ctx,uint8_t val)746 int32_t lis2mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
747 {
748 lis2mdl_cfg_reg_a_t reg;
749 int32_t ret;
750
751 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
752
753 if (ret == 0)
754 {
755 reg.soft_rst = val;
756 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
757 }
758
759 return ret;
760 }
761
762 /**
763 * @brief Software reset. Restore the default values in user registers.[get]
764 *
765 * @param ctx read / write interface definitions.(ptr)
766 * @param val change the values of soft_rst in reg CFG_REG_A.(ptr)
767 * @retval interface status.(MANDATORY: return 0 -> no Error)
768 *
769 */
lis2mdl_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)770 int32_t lis2mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
771 {
772 lis2mdl_cfg_reg_a_t reg;
773 int32_t ret;
774
775 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
776 *val = reg.soft_rst;
777
778 return ret;
779 }
780
781 /**
782 * @brief Reboot memory content. Reload the calibration parameters.[set]
783 *
784 * @param ctx read / write interface definitions.(ptr)
785 * @param val change the values of reboot in reg CFG_REG_A
786 * @retval interface status.(MANDATORY: return 0 -> no Error)
787 *
788 */
lis2mdl_boot_set(const stmdev_ctx_t * ctx,uint8_t val)789 int32_t lis2mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
790 {
791 lis2mdl_cfg_reg_a_t reg;
792 int32_t ret;
793
794 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
795
796 if (ret == 0)
797 {
798 reg.reboot = val;
799 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
800 }
801
802 return ret;
803 }
804
805 /**
806 * @brief Reboot memory content. Reload the calibration parameters.[get]
807 *
808 * @param ctx read / write interface definitions.(ptr)
809 * @param val change the values of reboot in reg CFG_REG_A.(ptr)
810 * @retval interface status.(MANDATORY: return 0 -> no Error)
811 *
812 */
lis2mdl_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)813 int32_t lis2mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
814 {
815 lis2mdl_cfg_reg_a_t reg;
816 int32_t ret;
817
818 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_A, (uint8_t *)®, 1);
819 *val = reg.reboot;
820
821 return ret;
822 }
823
824 /**
825 * @brief Selftest.[set]
826 *
827 * @param ctx read / write interface definitions.(ptr)
828 * @param val change the values of self_test in reg CFG_REG_C
829 * @retval interface status.(MANDATORY: return 0 -> no Error)
830 *
831 */
lis2mdl_self_test_set(const stmdev_ctx_t * ctx,uint8_t val)832 int32_t lis2mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
833 {
834 lis2mdl_cfg_reg_c_t reg;
835 int32_t ret;
836
837 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
838
839 if (ret == 0)
840 {
841 reg.self_test = val;
842 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
843 }
844
845 return ret;
846 }
847
848 /**
849 * @brief Selftest.[get]
850 *
851 * @param ctx read / write interface definitions.(ptr)
852 * @param val change the values of self_test in reg CFG_REG_C.(ptr)
853 * @retval interface status.(MANDATORY: return 0 -> no Error)
854 *
855 */
lis2mdl_self_test_get(const stmdev_ctx_t * ctx,uint8_t * val)856 int32_t lis2mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
857 {
858 lis2mdl_cfg_reg_c_t reg;
859 int32_t ret;
860
861 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
862 *val = reg.self_test;
863
864 return ret;
865 }
866
867 /**
868 * @brief Big/Little Endian data selection.[set]
869 *
870 * @param ctx read / write interface definitions.(ptr)
871 * @param val change the values of ble in reg CFG_REG_C
872 * @retval interface status.(MANDATORY: return 0 -> no Error)
873 *
874 */
lis2mdl_data_format_set(const stmdev_ctx_t * ctx,lis2mdl_ble_t val)875 int32_t lis2mdl_data_format_set(const stmdev_ctx_t *ctx, lis2mdl_ble_t val)
876 {
877 lis2mdl_cfg_reg_c_t reg;
878 int32_t ret;
879
880 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
881
882 if (ret == 0)
883 {
884 reg.ble = (uint8_t)val;
885 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
886 }
887
888 return ret;
889 }
890
891 /**
892 * @brief Big/Little Endian data selection.[get]
893 *
894 * @param ctx read / write interface definitions.(ptr)
895 * @param val Get the values of ble in reg CFG_REG_C.(ptr)
896 * @retval interface status.(MANDATORY: return 0 -> no Error)
897 *
898 */
lis2mdl_data_format_get(const stmdev_ctx_t * ctx,lis2mdl_ble_t * val)899 int32_t lis2mdl_data_format_get(const stmdev_ctx_t *ctx, lis2mdl_ble_t *val)
900 {
901 lis2mdl_cfg_reg_c_t reg;
902 int32_t ret;
903
904 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
905
906 switch (reg.ble)
907 {
908 case LIS2MDL_LSB_AT_LOW_ADD:
909 *val = LIS2MDL_LSB_AT_LOW_ADD;
910 break;
911
912 case LIS2MDL_MSB_AT_LOW_ADD:
913 *val = LIS2MDL_MSB_AT_LOW_ADD;
914 break;
915
916 default:
917 *val = LIS2MDL_LSB_AT_LOW_ADD;
918 break;
919 }
920
921 return ret;
922 }
923
924 /**
925 * @brief Info about device status.[get]
926 *
927 * @param ctx read / write interface definitions.(ptr)
928 * @param val registers STATUS_REG.(ptr)
929 * @retval interface status.(MANDATORY: return 0 -> no Error)
930 *
931 */
lis2mdl_status_get(const stmdev_ctx_t * ctx,lis2mdl_status_reg_t * val)932 int32_t lis2mdl_status_get(const stmdev_ctx_t *ctx,
933 lis2mdl_status_reg_t *val)
934 {
935 int32_t ret;
936
937 ret = lis2mdl_read_reg(ctx, LIS2MDL_STATUS_REG, (uint8_t *) val, 1);
938
939 return ret;
940 }
941
942 /**
943 * @}
944 *
945 */
946
947 /**
948 * @defgroup LIS2MDL_interrupts
949 * @brief This section group all the functions that manage interrupts
950 * @{
951 *
952 */
953
954 /**
955 * @brief The interrupt block recognition checks data after/before the
956 * hard-iron correction to discover the interrupt.[set]
957 *
958 * @param ctx read / write interface definitions.(ptr)
959 * @param val change the values of int_on_dataoff in reg CFG_REG_B
960 * @retval interface status.(MANDATORY: return 0 -> no Error)
961 *
962 */
lis2mdl_offset_int_conf_set(const stmdev_ctx_t * ctx,lis2mdl_int_on_dataoff_t val)963 int32_t lis2mdl_offset_int_conf_set(const stmdev_ctx_t *ctx,
964 lis2mdl_int_on_dataoff_t val)
965 {
966 lis2mdl_cfg_reg_b_t reg;
967 int32_t ret;
968
969 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
970
971 if (ret == 0)
972 {
973 reg.int_on_dataoff = (uint8_t)val;
974 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief The interrupt block recognition checks data after/before the
982 * hard-iron correction to discover the interrupt.[get]
983 *
984 * @param ctx read / write interface definitions.(ptr)
985 * @param val Get the values of int_on_dataoff in reg CFG_REG_B.(ptr)
986 * @retval interface status.(MANDATORY: return 0 -> no Error)
987 *
988 */
lis2mdl_offset_int_conf_get(const stmdev_ctx_t * ctx,lis2mdl_int_on_dataoff_t * val)989 int32_t lis2mdl_offset_int_conf_get(const stmdev_ctx_t *ctx,
990 lis2mdl_int_on_dataoff_t *val)
991 {
992 lis2mdl_cfg_reg_b_t reg;
993 int32_t ret;
994
995 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_B, (uint8_t *)®, 1);
996
997 switch (reg.int_on_dataoff)
998 {
999 case LIS2MDL_CHECK_BEFORE:
1000 *val = LIS2MDL_CHECK_BEFORE;
1001 break;
1002
1003 case LIS2MDL_CHECK_AFTER:
1004 *val = LIS2MDL_CHECK_AFTER;
1005 break;
1006
1007 default:
1008 *val = LIS2MDL_CHECK_BEFORE;
1009 break;
1010 }
1011
1012 return ret;
1013 }
1014
1015 /**
1016 * @brief Data-ready signal on INT_DRDY pin.[set]
1017 *
1018 * @param ctx read / write interface definitions.(ptr)
1019 * @param val change the values of drdy_on_pin in reg CFG_REG_C
1020 * @retval interface status.(MANDATORY: return 0 -> no Error)
1021 *
1022 */
lis2mdl_drdy_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)1023 int32_t lis2mdl_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
1024 {
1025 lis2mdl_cfg_reg_c_t reg;
1026 int32_t ret;
1027
1028 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1029
1030 if (ret == 0)
1031 {
1032 reg.drdy_on_pin = val;
1033 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1034 }
1035
1036 return ret;
1037 }
1038
1039 /**
1040 * @brief Data-ready signal on INT_DRDY pin.[get]
1041 *
1042 * @param ctx read / write interface definitions.(ptr)
1043 * @param val change the values of drdy_on_pin in reg CFG_REG_C.(ptr)
1044 * @retval interface status.(MANDATORY: return 0 -> no Error)
1045 *
1046 */
lis2mdl_drdy_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)1047 int32_t lis2mdl_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
1048 {
1049 lis2mdl_cfg_reg_c_t reg;
1050 int32_t ret;
1051
1052 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1053 *val = reg.drdy_on_pin;
1054
1055 return ret;
1056 }
1057
1058 /**
1059 * @brief Interrupt signal on INT_DRDY pin.[set]
1060 *
1061 * @param ctx read / write interface definitions.(ptr)
1062 * @param val change the values of int_on_pin in reg CFG_REG_C
1063 * @retval interface status.(MANDATORY: return 0 -> no Error)
1064 *
1065 */
lis2mdl_int_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)1066 int32_t lis2mdl_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
1067 {
1068 lis2mdl_cfg_reg_c_t reg;
1069 int32_t ret;
1070
1071 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1072
1073 if (ret == 0)
1074 {
1075 reg.int_on_pin = val;
1076 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1077 }
1078
1079 return ret;
1080 }
1081
1082 /**
1083 * @brief Interrupt signal on INT_DRDY pin.[get]
1084 *
1085 * @param ctx read / write interface definitions.(ptr)
1086 * @param val change the values of int_on_pin in reg CFG_REG_C.(ptr)
1087 * @retval interface status.(MANDATORY: return 0 -> no Error)
1088 *
1089 */
lis2mdl_int_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)1090 int32_t lis2mdl_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
1091 {
1092 lis2mdl_cfg_reg_c_t reg;
1093 int32_t ret;
1094
1095 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1096 *val = reg.int_on_pin;
1097
1098 return ret;
1099 }
1100
1101 /**
1102 * @brief Interrupt generator configuration register.[set]
1103 *
1104 * @param ctx read / write interface definitions.(ptr)
1105 * @param val registers INT_CRTL_REG.(ptr)
1106 * @retval interface status.(MANDATORY: return 0 -> no Error)
1107 *
1108 */
lis2mdl_int_gen_conf_set(const stmdev_ctx_t * ctx,lis2mdl_int_crtl_reg_t * val)1109 int32_t lis2mdl_int_gen_conf_set(const stmdev_ctx_t *ctx,
1110 lis2mdl_int_crtl_reg_t *val)
1111 {
1112 int32_t ret;
1113
1114 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
1115
1116 return ret;
1117 }
1118
1119 /**
1120 * @brief Interrupt generator configuration register.[get]
1121 *
1122 * @param ctx read / write interface definitions.(ptr)
1123 * @param val registers INT_CRTL_REG.(ptr)
1124 * @retval interface status.(MANDATORY: return 0 -> no Error)
1125 *
1126 */
lis2mdl_int_gen_conf_get(const stmdev_ctx_t * ctx,lis2mdl_int_crtl_reg_t * val)1127 int32_t lis2mdl_int_gen_conf_get(const stmdev_ctx_t *ctx,
1128 lis2mdl_int_crtl_reg_t *val)
1129 {
1130 int32_t ret;
1131
1132 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_CRTL_REG, (uint8_t *) val, 1);
1133
1134 return ret;
1135 }
1136
1137 /**
1138 * @brief Interrupt generator source register.[get]
1139 *
1140 * @param ctx read / write interface definitions.(ptr)
1141 * @param val registers INT_SOURCE_REG.(ptr)
1142 * @retval interface status.(MANDATORY: return 0 -> no Error)
1143 *
1144 */
lis2mdl_int_gen_source_get(const stmdev_ctx_t * ctx,lis2mdl_int_source_reg_t * val)1145 int32_t lis2mdl_int_gen_source_get(const stmdev_ctx_t *ctx,
1146 lis2mdl_int_source_reg_t *val)
1147 {
1148 int32_t ret;
1149
1150 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_SOURCE_REG, (uint8_t *) val, 1);
1151
1152 return ret;
1153 }
1154
1155 /**
1156 * @brief User-defined threshold value for xl interrupt event on generator.
1157 * Data format is the same of output data raw: two’s complement with
1158 * 1LSb = 1.5mG.[set]
1159 *
1160 * @param ctx read / write interface definitions.(ptr)
1161 * @param buff that contains data to write
1162 * @retval interface status.(MANDATORY: return 0 -> no Error)
1163 *
1164 */
lis2mdl_int_gen_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1165 int32_t lis2mdl_int_gen_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1166 {
1167 uint8_t buff[2];
1168 int32_t ret;
1169
1170 buff[1] = (uint8_t)(val / 256U);
1171 buff[0] = (uint8_t)(val - (buff[1] * 256U));
1172 ret = lis2mdl_write_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
1173
1174 return ret;
1175 }
1176
1177 /**
1178 * @brief User-defined threshold value for xl interrupt event on generator.
1179 * Data format is the same of output data raw: two’s complement with
1180 * 1LSb = 1.5mG.[get]
1181 *
1182 * @param ctx read / write interface definitions.(ptr)
1183 * @param buff that stores data read
1184 * @retval interface status.(MANDATORY: return 0 -> no Error)
1185 *
1186 */
lis2mdl_int_gen_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1187 int32_t lis2mdl_int_gen_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1188 {
1189 uint8_t buff[2];
1190 int32_t ret;
1191
1192 ret = lis2mdl_read_reg(ctx, LIS2MDL_INT_THS_L_REG, buff, 2);
1193 *val = buff[1];
1194 *val = (*val * 256U) + buff[0];
1195
1196 return ret;
1197 }
1198
1199 /**
1200 * @}
1201 *
1202 */
1203
1204 /**
1205 * @defgroup LIS2MDL_serial_interface
1206 * @brief This section group all the functions concerning serial
1207 * interface management
1208 * @{
1209 *
1210 */
1211
1212 /**
1213 * @brief SPI Serial Interface Mode selection.[set]
1214 *
1215 * @param ctx read / write interface definitions
1216 * @param val change the values of 4wspi in reg CFG_REG_C
1217 * @retval interface status (MANDATORY: return 0 -> no Error)
1218 *
1219 */
lis2mdl_spi_mode_set(const stmdev_ctx_t * ctx,lis2mdl_sim_t val)1220 int32_t lis2mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis2mdl_sim_t val)
1221 {
1222 lis2mdl_cfg_reg_c_t reg;
1223 int32_t ret;
1224
1225 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1226
1227 if (ret == 0)
1228 {
1229 reg._4wspi = (uint8_t)val;
1230 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1231 }
1232
1233 return ret;
1234 }
1235
1236 /**
1237 * @brief SPI Serial Interface Mode selection.[get]
1238 *
1239 * @param ctx read / write interface definitions
1240 * @param val Get the values of 4wspi in reg CFG_REG_C
1241 * @retval interface status (MANDATORY: return 0 -> no Error)
1242 *
1243 */
lis2mdl_spi_mode_get(const stmdev_ctx_t * ctx,lis2mdl_sim_t * val)1244 int32_t lis2mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis2mdl_sim_t *val)
1245 {
1246 lis2mdl_cfg_reg_c_t reg;
1247 int32_t ret;
1248
1249 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1250
1251 switch (reg._4wspi)
1252 {
1253 case LIS2MDL_SPI_4_WIRE:
1254 *val = LIS2MDL_SPI_4_WIRE;
1255 break;
1256
1257 case LIS2MDL_SPI_3_WIRE:
1258 *val = LIS2MDL_SPI_3_WIRE;
1259 break;
1260
1261 default:
1262 *val = LIS2MDL_SPI_3_WIRE;
1263 break;
1264 }
1265
1266 return ret;
1267 }
1268
1269 /**
1270 * @brief Enable/Disable I2C interface.[set]
1271 *
1272 * @param ctx read / write interface definitions.(ptr)
1273 * @param val change the values of i2c_dis in reg CFG_REG_C
1274 * @retval interface status.(MANDATORY: return 0 -> no Error)
1275 *
1276 */
lis2mdl_i2c_interface_set(const stmdev_ctx_t * ctx,lis2mdl_i2c_dis_t val)1277 int32_t lis2mdl_i2c_interface_set(const stmdev_ctx_t *ctx,
1278 lis2mdl_i2c_dis_t val)
1279 {
1280 lis2mdl_cfg_reg_c_t reg;
1281 int32_t ret;
1282
1283 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1284
1285 if (ret == 0)
1286 {
1287 reg.i2c_dis = (uint8_t)val;
1288 ret = lis2mdl_write_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1289 }
1290
1291 return ret;
1292 }
1293
1294 /**
1295 * @brief Enable/Disable I2C interface.[get]
1296 *
1297 * @param ctx read / write interface definitions.(ptr)
1298 * @param val Get the values of i2c_dis in reg CFG_REG_C.(ptr)
1299 * @retval interface status.(MANDATORY: return 0 -> no Error)
1300 *
1301 */
lis2mdl_i2c_interface_get(const stmdev_ctx_t * ctx,lis2mdl_i2c_dis_t * val)1302 int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx,
1303 lis2mdl_i2c_dis_t *val)
1304 {
1305 lis2mdl_cfg_reg_c_t reg;
1306 int32_t ret;
1307
1308 ret = lis2mdl_read_reg(ctx, LIS2MDL_CFG_REG_C, (uint8_t *)®, 1);
1309
1310 switch (reg.i2c_dis)
1311 {
1312 case LIS2MDL_I2C_ENABLE:
1313 *val = LIS2MDL_I2C_ENABLE;
1314 break;
1315
1316 case LIS2MDL_I2C_DISABLE:
1317 *val = LIS2MDL_I2C_DISABLE;
1318 break;
1319
1320 default:
1321 *val = LIS2MDL_I2C_ENABLE;
1322 break;
1323 }
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * @}
1330 *
1331 */
1332
1333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1334
