1 /** 2 ****************************************************************************** 3 * @file lis2hh12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2hh12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2HH12_REGS_H 23 #define LIS2HH12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2HH12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2HH12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x3D if SA0=1 -> 0x3B **/ 172 #define LIS2HH12_I2C_ADD_L 0x3DU 173 #define LIS2HH12_I2C_ADD_H 0x3BU 174 /** Device Identification (Who am I) **/ 175 #define LIS2HH12_ID 0x41U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define LIS2HH12_TEMP_L 0x0BU 183 #define LIS2HH12_TEMP_H 0x0CU 184 #define LIS2HH12_WHO_AM_I 0x0FU 185 #define LIS2HH12_ACT_THS 0x1EU 186 typedef struct 187 { 188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 189 uint8_t ths : 7; 190 uint8_t not_used_01 : 1; 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t not_used_01 : 1; 193 uint8_t ths : 7; 194 #endif /* DRV_BYTE_ORDER */ 195 } lis2hh12_act_ths_t; 196 197 #define LIS2HH12_ACT_DUR 0x1FU 198 typedef struct 199 { 200 uint8_t dur : 8; 201 } lis2hh12_act_dur_t; 202 203 #define LIS2HH12_CTRL1 0x20U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t xen : 1; 208 uint8_t yen : 1; 209 uint8_t zen : 1; 210 uint8_t bdu : 1; 211 uint8_t odr : 3; 212 uint8_t hr : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t hr : 1; 215 uint8_t odr : 3; 216 uint8_t bdu : 1; 217 uint8_t zen : 1; 218 uint8_t yen : 1; 219 uint8_t xen : 1; 220 #endif /* DRV_BYTE_ORDER */ 221 } lis2hh12_ctrl1_t; 222 223 #define LIS2HH12_CTRL2 0x21U 224 typedef struct 225 { 226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 227 uint8_t hpis : 2; 228 uint8_t fds : 1; 229 uint8_t hpm : 2; 230 uint8_t dfc : 2; 231 uint8_t not_used_01 : 1; 232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 233 uint8_t not_used_01 : 1; 234 uint8_t dfc : 2; 235 uint8_t hpm : 2; 236 uint8_t fds : 1; 237 uint8_t hpis : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } lis2hh12_ctrl2_t; 240 241 #define LIS2HH12_CTRL3 0x22U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t int1_drdy : 1; 246 uint8_t int1_fth : 1; 247 uint8_t int1_ovr : 1; 248 uint8_t int1_ig1 : 1; 249 uint8_t int1_ig2 : 1; 250 uint8_t int1_inact : 1; 251 uint8_t stop_fth : 1; 252 uint8_t fifo_en : 1; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t fifo_en : 1; 255 uint8_t stop_fth : 1; 256 uint8_t int1_inact : 1; 257 uint8_t int1_ig2 : 1; 258 uint8_t int1_ig1 : 1; 259 uint8_t int1_ovr : 1; 260 uint8_t int1_fth : 1; 261 uint8_t int1_drdy : 1; 262 #endif /* DRV_BYTE_ORDER */ 263 } lis2hh12_ctrl3_t; 264 265 #define LIS2HH12_CTRL4 0x23U 266 typedef struct 267 { 268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 269 uint8_t sim : 1; 270 uint8_t i2c_disable : 1; 271 uint8_t if_add_inc : 1; 272 uint8_t bw_scale_odr : 1; 273 uint8_t fs : 2; 274 uint8_t bw : 2; 275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 276 uint8_t bw : 2; 277 uint8_t fs : 2; 278 uint8_t bw_scale_odr : 1; 279 uint8_t if_add_inc : 1; 280 uint8_t i2c_disable : 1; 281 uint8_t sim : 1; 282 #endif /* DRV_BYTE_ORDER */ 283 } lis2hh12_ctrl4_t; 284 285 #define LIS2HH12_CTRL5 0x24U 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t pp_od : 1; 290 uint8_t h_lactive : 1; 291 uint8_t st : 2; 292 uint8_t dec : 2; 293 uint8_t soft_reset : 1; 294 uint8_t debug : 1; 295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 296 uint8_t debug : 1; 297 uint8_t soft_reset : 1; 298 uint8_t dec : 2; 299 uint8_t st : 2; 300 uint8_t h_lactive : 1; 301 uint8_t pp_od : 1; 302 #endif /* DRV_BYTE_ORDER */ 303 } lis2hh12_ctrl5_t; 304 305 #define LIS2HH12_CTRL6 0x25U 306 typedef struct 307 { 308 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 309 uint8_t int2_drdy : 1; 310 uint8_t int2_fth : 1; 311 uint8_t int2_empty : 1; 312 uint8_t int2_ig1 : 1; 313 uint8_t int2_ig2 : 1; 314 uint8_t int2_boot : 1; 315 uint8_t not_used_01 : 1; 316 uint8_t boot : 1; 317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 318 uint8_t boot : 1; 319 uint8_t not_used_01 : 1; 320 uint8_t int2_boot : 1; 321 uint8_t int2_ig2 : 1; 322 uint8_t int2_ig1 : 1; 323 uint8_t int2_empty : 1; 324 uint8_t int2_fth : 1; 325 uint8_t int2_drdy : 1; 326 #endif /* DRV_BYTE_ORDER */ 327 } lis2hh12_ctrl6_t; 328 329 #define LIS2HH12_CTRL7 0x26U 330 typedef struct 331 { 332 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 333 uint8_t _4d_ig : 2; 334 uint8_t lir : 2; 335 uint8_t dcrm : 2; 336 uint8_t not_used_01 : 2; 337 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 338 uint8_t not_used_01 : 2; 339 uint8_t dcrm : 2; 340 uint8_t lir : 2; 341 uint8_t _4d_ig : 2; 342 #endif /* DRV_BYTE_ORDER */ 343 } lis2hh12_ctrl7_t; 344 345 #define LIS2HH12_STATUS 0x27U 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t xda : 1; 350 uint8_t yda : 1; 351 uint8_t zda : 1; 352 uint8_t zyxda : 1; 353 uint8_t _xor : 1; 354 uint8_t yor : 1; 355 uint8_t zor : 1; 356 uint8_t zyxor : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t zyxor : 1; 359 uint8_t zor : 1; 360 uint8_t yor : 1; 361 uint8_t _xor : 1; 362 uint8_t zyxda : 1; 363 uint8_t zda : 1; 364 uint8_t yda : 1; 365 uint8_t xda : 1; 366 #endif /* DRV_BYTE_ORDER */ 367 } lis2hh12_status_t; 368 369 #define LIS2HH12_OUT_X_L 0x28U 370 #define LIS2HH12_OUT_X_H 0x29U 371 #define LIS2HH12_OUT_Y_L 0x2AU 372 #define LIS2HH12_OUT_Y_H 0x2BU 373 #define LIS2HH12_OUT_Z_L 0x2CU 374 #define LIS2HH12_OUT_Z_H 0x2DU 375 #define LIS2HH12_FIFO_CTRL 0x2EU 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t fth : 5; 380 uint8_t fmode : 3; 381 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 382 uint8_t fmode : 3; 383 uint8_t fth : 5; 384 #endif /* DRV_BYTE_ORDER */ 385 } lis2hh12_fifo_ctrl_t; 386 387 #define LIS2HH12_FIFO_SRC 0x2FU 388 typedef struct 389 { 390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 391 uint8_t fss : 5; 392 uint8_t empty : 1; 393 uint8_t ovr : 1; 394 uint8_t fth : 1; 395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 396 uint8_t fth : 1; 397 uint8_t ovr : 1; 398 uint8_t empty : 1; 399 uint8_t fss : 5; 400 #endif /* DRV_BYTE_ORDER */ 401 } lis2hh12_fifo_src_t; 402 403 #define LIS2HH12_IG_CFG1 0x30U 404 typedef struct 405 { 406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 407 uint8_t xlie : 1; 408 uint8_t xhie : 1; 409 uint8_t ylie : 1; 410 uint8_t yhie : 1; 411 uint8_t zlie : 1; 412 uint8_t zhie : 1; 413 uint8_t _6d : 1; 414 uint8_t aoi : 1; 415 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 416 uint8_t aoi : 1; 417 uint8_t _6d : 1; 418 uint8_t zhie : 1; 419 uint8_t zlie : 1; 420 uint8_t yhie : 1; 421 uint8_t ylie : 1; 422 uint8_t xhie : 1; 423 uint8_t xlie : 1; 424 #endif /* DRV_BYTE_ORDER */ 425 } lis2hh12_ig_cfg1_t; 426 427 #define LIS2HH12_IG_SRC1 0x31U 428 typedef struct 429 { 430 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 431 uint8_t xl : 1; 432 uint8_t xh : 1; 433 uint8_t yl : 1; 434 uint8_t yh : 1; 435 uint8_t zl : 1; 436 uint8_t zh : 1; 437 uint8_t ia : 1; 438 uint8_t not_used_01 : 1; 439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 440 uint8_t not_used_01 : 1; 441 uint8_t ia : 1; 442 uint8_t zh : 1; 443 uint8_t zl : 1; 444 uint8_t yh : 1; 445 uint8_t yl : 1; 446 uint8_t xh : 1; 447 uint8_t xl : 1; 448 #endif /* DRV_BYTE_ORDER */ 449 } lis2hh12_ig_src1_t; 450 451 #define LIS2HH12_IG_THS_X1 0x32U 452 #define LIS2HH12_IG_THS_Y1 0x33U 453 #define LIS2HH12_IG_THS_Z1 0x34U 454 #define LIS2HH12_IG_DUR1 0x35U 455 typedef struct 456 { 457 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 458 uint8_t dur1 : 7; 459 uint8_t wait1 : 1; 460 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 461 uint8_t wait1 : 1; 462 uint8_t dur1 : 7; 463 #endif /* DRV_BYTE_ORDER */ 464 } lis2hh12_ig_dur1_t; 465 466 #define LIS2HH12_IG_CFG2 0x36U 467 typedef struct 468 { 469 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 470 uint8_t xlie : 1; 471 uint8_t xhie : 1; 472 uint8_t ylie : 1; 473 uint8_t yhie : 1; 474 uint8_t zlie : 1; 475 uint8_t zhie : 1; 476 uint8_t _6d : 1; 477 uint8_t aoi : 1; 478 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 479 uint8_t aoi : 1; 480 uint8_t _6d : 1; 481 uint8_t zhie : 1; 482 uint8_t zlie : 1; 483 uint8_t yhie : 1; 484 uint8_t ylie : 1; 485 uint8_t xhie : 1; 486 uint8_t xlie : 1; 487 #endif /* DRV_BYTE_ORDER */ 488 } lis2hh12_ig_cfg2_t; 489 490 #define LIS2HH12_IG_SRC2 0x37U 491 typedef struct 492 { 493 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 494 uint8_t xl : 1; 495 uint8_t xh : 1; 496 uint8_t yl : 1; 497 uint8_t yh : 1; 498 uint8_t zl : 1; 499 uint8_t zh : 1; 500 uint8_t ia : 1; 501 uint8_t not_used_01 : 1; 502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 503 uint8_t not_used_01 : 1; 504 uint8_t ia : 1; 505 uint8_t zh : 1; 506 uint8_t zl : 1; 507 uint8_t yh : 1; 508 uint8_t yl : 1; 509 uint8_t xh : 1; 510 uint8_t xl : 1; 511 #endif /* DRV_BYTE_ORDER */ 512 } lis2hh12_ig_src2_t; 513 514 #define LIS2HH12_IG_THS2 0x38U 515 #define LIS2HH12_IG_DUR2 0x39U 516 typedef struct 517 { 518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 519 uint8_t dur2 : 7; 520 uint8_t wait2 : 1; 521 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 522 uint8_t wait2 : 1; 523 uint8_t dur2 : 7; 524 #endif /* DRV_BYTE_ORDER */ 525 } lis2hh12_ig_dur2_t; 526 527 #define LIS2HH12_XL_REFERENCE 0x3AU 528 #define LIS2HH12_XH_REFERENCE 0x3BU 529 #define LIS2HH12_YL_REFERENCE 0x3CU 530 #define LIS2HH12_YH_REFERENCE 0x3DU 531 #define LIS2HH12_ZL_REFERENCE 0x3EU 532 #define LIS2HH12_ZH_REFERENCE 0x3FU 533 534 /** 535 * @defgroup LIS2HH12_Register_Union 536 * @brief This union group all the registers having a bit-field 537 * description. 538 * This union is useful but it's not needed by the driver. 539 * 540 * REMOVING this union you are compliant with: 541 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 542 * 543 * @{ 544 * 545 */ 546 typedef union 547 { 548 lis2hh12_act_ths_t act_ths; 549 lis2hh12_act_dur_t act_dur; 550 lis2hh12_ctrl1_t ctrl1; 551 lis2hh12_ctrl2_t ctrl2; 552 lis2hh12_ctrl3_t ctrl3; 553 lis2hh12_ctrl4_t ctrl4; 554 lis2hh12_ctrl5_t ctrl5; 555 lis2hh12_ctrl6_t ctrl6; 556 lis2hh12_ctrl7_t ctrl7; 557 lis2hh12_status_t status; 558 lis2hh12_fifo_ctrl_t fifo_ctrl; 559 lis2hh12_fifo_src_t fifo_src; 560 lis2hh12_ig_cfg1_t ig_cfg1; 561 lis2hh12_ig_src1_t ig_src1; 562 lis2hh12_ig_dur1_t ig_dur1; 563 lis2hh12_ig_cfg2_t ig_cfg2; 564 lis2hh12_ig_src2_t ig_src2; 565 lis2hh12_ig_dur2_t ig_dur2; 566 bitwise_t bitwise; 567 uint8_t byte; 568 } lis2hh12_reg_t; 569 570 /** 571 * @} 572 * 573 */ 574 575 #ifndef __weak 576 #define __weak __attribute__((weak)) 577 #endif /* __weak */ 578 579 /* 580 * These are the basic platform dependent I/O routines to read 581 * and write device registers connected on a standard bus. 582 * The driver keeps offering a default implementation based on function 583 * pointers to read/write routines for backward compatibility. 584 * The __weak directive allows the final application to overwrite 585 * them with a custom implementation. 586 */ 587 588 int32_t lis2hh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 589 uint8_t *data, 590 uint16_t len); 591 int32_t lis2hh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 592 uint8_t *data, 593 uint16_t len); 594 595 float_t lis2hh12_from_fs2g_to_mg(int16_t lsb); 596 float_t lis2hh12_from_fs4g_to_mg(int16_t lsb); 597 float_t lis2hh12_from_fs8g_to_mg(int16_t lsb); 598 599 float_t lis2hh12_from_lsb_to_celsius(int16_t lsb); 600 601 typedef struct 602 { 603 uint8_t xen : 1; 604 uint8_t yen : 1; 605 uint8_t zen : 1; 606 } lis2hh12_xl_axis_t; 607 int32_t lis2hh12_xl_axis_set(const stmdev_ctx_t *ctx, 608 lis2hh12_xl_axis_t val); 609 int32_t lis2hh12_xl_axis_get(const stmdev_ctx_t *ctx, 610 lis2hh12_xl_axis_t *val); 611 612 int32_t lis2hh12_block_data_update_set(const stmdev_ctx_t *ctx, 613 uint8_t val); 614 int32_t lis2hh12_block_data_update_get(const stmdev_ctx_t *ctx, 615 uint8_t *val); 616 617 typedef enum 618 { 619 LIS2HH12_XL_ODR_OFF = 0x00, 620 LIS2HH12_XL_ODR_10Hz = 0x01, 621 LIS2HH12_XL_ODR_50Hz = 0x02, 622 LIS2HH12_XL_ODR_100Hz = 0x03, 623 LIS2HH12_XL_ODR_200Hz = 0x04, 624 LIS2HH12_XL_ODR_400Hz = 0x05, 625 LIS2HH12_XL_ODR_800Hz = 0x06, 626 } lis2hh12_xl_data_rate_t; 627 int32_t lis2hh12_xl_data_rate_set(const stmdev_ctx_t *ctx, 628 lis2hh12_xl_data_rate_t val); 629 int32_t lis2hh12_xl_data_rate_get(const stmdev_ctx_t *ctx, 630 lis2hh12_xl_data_rate_t *val); 631 632 typedef enum 633 { 634 LIS2HH12_2g = 0x00, 635 LIS2HH12_16g = 0x01, 636 LIS2HH12_4g = 0x02, 637 LIS2HH12_8g = 0x03, 638 } lis2hh12_xl_fs_t; 639 int32_t lis2hh12_xl_full_scale_set(const stmdev_ctx_t *ctx, 640 lis2hh12_xl_fs_t val); 641 int32_t lis2hh12_xl_full_scale_get(const stmdev_ctx_t *ctx, 642 lis2hh12_xl_fs_t *val); 643 644 typedef enum 645 { 646 LIS2HH12_NO_DECIMATION = 0x00, 647 LIS2HH12_EVERY_2_SAMPLES = 0x01, 648 LIS2HH12_EVERY_4_SAMPLES = 0x02, 649 LIS2HH12_EVERY_8_SAMPLES = 0x03, 650 } lis2hh12_dec_t; 651 int32_t lis2hh12_xl_decimation_set(const stmdev_ctx_t *ctx, 652 lis2hh12_dec_t val); 653 int32_t lis2hh12_xl_decimation_get(const stmdev_ctx_t *ctx, 654 lis2hh12_dec_t *val); 655 656 int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 657 uint8_t *val); 658 659 int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 660 661 int32_t lis2hh12_acceleration_raw_get(const stmdev_ctx_t *ctx, 662 int16_t *val); 663 664 int32_t lis2hh12_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 665 666 int32_t lis2hh12_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 667 int32_t lis2hh12_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 668 669 int32_t lis2hh12_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 670 int32_t lis2hh12_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 671 672 typedef struct 673 { 674 uint8_t xda : 1; 675 uint8_t yda : 1; 676 uint8_t zda : 1; 677 uint8_t zyxda : 1; 678 uint8_t _xor : 1; 679 uint8_t yor : 1; 680 uint8_t zor : 1; 681 uint8_t zyxor : 1; 682 } lis2hh12_status_reg_t; 683 int32_t lis2hh12_dev_status_get(const stmdev_ctx_t *ctx, 684 lis2hh12_status_reg_t *val); 685 686 typedef enum 687 { 688 LIS2HH12_HP_DISABLE = 0x00, 689 LIS2HH12_HP_ON_INT_GEN_1 = 0x02, 690 LIS2HH12_HP_ON_INT_GEN_2 = 0x01, 691 LIS2HH12_HP_ON_BOTH_GEN = 0x03, 692 } lis2hh12_xl_hp_path_t; 693 int32_t lis2hh12_xl_filter_int_path_set(const stmdev_ctx_t *ctx, 694 lis2hh12_xl_hp_path_t val); 695 int32_t lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t *ctx, 696 lis2hh12_xl_hp_path_t *val); 697 698 typedef enum 699 { 700 LIS2HH12_BYPASSED = 0x00, 701 LIS2HH12_FILT_HP = 0x02, 702 LIS2HH12_FILT_LP = 0x01, 703 } lis2hh12_xl_out_path_t; 704 int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx, 705 lis2hh12_xl_out_path_t val); 706 int32_t lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t *ctx, 707 lis2hh12_xl_out_path_t *val); 708 709 typedef enum 710 { 711 LIS2HH12_HP_ODR_DIV_50 = 0x00, 712 LIS2HH12_HP_ODR_DIV_100 = 0x10, 713 LIS2HH12_HP_ODR_DIV_9 = 0x20, 714 LIS2HH12_HP_ODR_DIV_400 = 0x30, 715 LIS2HH12_HP_ODR_DIV_50_REF_MD = 0x01, 716 LIS2HH12_HP_ODR_DIV_100_REF_MD = 0x11, 717 LIS2HH12_HP_ODR_DIV_9_REF_MD = 0x21, 718 LIS2HH12_HP_ODR_DIV_400_REF_MD = 0x31, 719 } lis2hh12_xl_hp_bw_t; 720 int32_t lis2hh12_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, 721 lis2hh12_xl_hp_bw_t val); 722 int32_t lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, 723 lis2hh12_xl_hp_bw_t *val); 724 725 typedef enum 726 { 727 LIS2HH12_LP_ODR_DIV_50 = 0, 728 LIS2HH12_LP_ODR_DIV_100 = 1, 729 LIS2HH12_LP_ODR_DIV_9 = 2, 730 LIS2HH12_LP_ODR_DIV_400 = 3, 731 } lis2hh12_xl_lp_bw_t; 732 int32_t lis2hh12_xl_filter_low_bandwidth_set(const stmdev_ctx_t *ctx, 733 lis2hh12_xl_lp_bw_t val); 734 int32_t lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t *ctx, 735 lis2hh12_xl_lp_bw_t *val); 736 737 typedef enum 738 { 739 LIS2HH12_AUTO = 0x00, 740 LIS2HH12_408Hz = 0x10, 741 LIS2HH12_211Hz = 0x11, 742 LIS2HH12_105Hz = 0x12, 743 LIS2HH12_50Hz = 0x13, 744 } lis2hh12_xl_filt_aa_bw_t; 745 int32_t lis2hh12_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, 746 lis2hh12_xl_filt_aa_bw_t val); 747 int32_t lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, 748 lis2hh12_xl_filt_aa_bw_t *val); 749 750 int32_t lis2hh12_xl_filter_reference_set(const stmdev_ctx_t *ctx, 751 int16_t *val); 752 int32_t lis2hh12_xl_filter_reference_get(const stmdev_ctx_t *ctx, 753 int16_t *val); 754 755 typedef enum 756 { 757 LIS2HH12_SPI_4_WIRE = 0x00, 758 LIS2HH12_SPI_3_WIRE = 0x01, 759 } lis2hh12_sim_t; 760 int32_t lis2hh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2hh12_sim_t val); 761 int32_t lis2hh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2hh12_sim_t *val); 762 763 typedef enum 764 { 765 LIS2HH12_I2C_ENABLE = 0x00, 766 LIS2HH12_I2C_DISABLE = 0x01, 767 } lis2hh12_i2c_dis_t; 768 int32_t lis2hh12_i2c_interface_set(const stmdev_ctx_t *ctx, 769 lis2hh12_i2c_dis_t val); 770 int32_t lis2hh12_i2c_interface_get(const stmdev_ctx_t *ctx, 771 lis2hh12_i2c_dis_t *val); 772 773 typedef enum 774 { 775 LIS2HH12_DISABLE = 0x00, 776 LIS2HH12_ENABLE = 0x01, 777 } lis2hh12_auto_inc_t; 778 int32_t lis2hh12_auto_increment_set(const stmdev_ctx_t *ctx, 779 lis2hh12_auto_inc_t val); 780 int32_t lis2hh12_auto_increment_get(const stmdev_ctx_t *ctx, 781 lis2hh12_auto_inc_t *val); 782 783 typedef struct 784 { 785 uint8_t int1_drdy : 1; 786 uint8_t int1_fth : 1; 787 uint8_t int1_ovr : 1; 788 uint8_t int1_ig1 : 1; 789 uint8_t int1_ig2 : 1; 790 uint8_t int1_inact : 1; 791 } lis2hh12_pin_int1_route_t; 792 int32_t lis2hh12_pin_int1_route_set(const stmdev_ctx_t *ctx, 793 lis2hh12_pin_int1_route_t val); 794 int32_t lis2hh12_pin_int1_route_get(const stmdev_ctx_t *ctx, 795 lis2hh12_pin_int1_route_t *val); 796 797 typedef enum 798 { 799 LIS2HH12_PUSH_PULL = 0x00, 800 LIS2HH12_OPEN_DRAIN = 0x01, 801 } lis2hh12_pp_od_t; 802 int32_t lis2hh12_pin_mode_set(const stmdev_ctx_t *ctx, 803 lis2hh12_pp_od_t val); 804 int32_t lis2hh12_pin_mode_get(const stmdev_ctx_t *ctx, 805 lis2hh12_pp_od_t *val); 806 807 typedef enum 808 { 809 LIS2HH12_ACTIVE_HIGH = 0x00, 810 LIS2HH12_ACTIVE_LOW = 0x01, 811 } lis2hh12_pin_pol_t; 812 int32_t lis2hh12_pin_polarity_set(const stmdev_ctx_t *ctx, 813 lis2hh12_pin_pol_t val); 814 int32_t lis2hh12_pin_polarity_get(const stmdev_ctx_t *ctx, 815 lis2hh12_pin_pol_t *val); 816 817 typedef struct 818 { 819 uint8_t int2_drdy : 1; 820 uint8_t int2_fth : 1; 821 uint8_t int2_empty : 1; 822 uint8_t int2_ig1 : 1; 823 uint8_t int2_ig2 : 1; 824 uint8_t int2_boot : 1; 825 } lis2hh12_pin_int2_route_t; 826 int32_t lis2hh12_pin_int2_route_set(const stmdev_ctx_t *ctx, 827 lis2hh12_pin_int2_route_t val); 828 int32_t lis2hh12_pin_int2_route_get(const stmdev_ctx_t *ctx, 829 lis2hh12_pin_int2_route_t *val); 830 831 typedef enum 832 { 833 LIS2HH12_INT_PULSED = 0x00, 834 LIS2HH12_INT_LATCHED = 0x01, 835 } lis2hh12_lir_t; 836 int32_t lis2hh12_pin_notification_set(const stmdev_ctx_t *ctx, 837 lis2hh12_lir_t val); 838 int32_t lis2hh12_pin_notification_get(const stmdev_ctx_t *ctx, 839 lis2hh12_lir_t *val); 840 typedef enum 841 { 842 LIS2HH12_IG1_OR_IG2_OR = 0x00, 843 LIS2HH12_IG1_AND_IG2_OR = 0x01, 844 LIS2HH12_IG1_OR_IG2_AND = 0x10, 845 LIS2HH12_IG1_AND_IG2_AND = 0x11, 846 } lis2hh12_pin_logic_t; 847 int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx, 848 lis2hh12_pin_logic_t val); 849 int32_t lis2hh12_pin_logic_get(const stmdev_ctx_t *ctx, 850 lis2hh12_pin_logic_t *val); 851 852 typedef enum 853 { 854 LIS2HH12_RESET_MODE = 0x00, 855 LIS2HH12_DECREMENT_MODE = 0x01, 856 } lis2hh12_dcrm_t; 857 int32_t lis2hh12_xl_trshld_mode_set(const stmdev_ctx_t *ctx, 858 lis2hh12_dcrm_t val); 859 int32_t lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t *ctx, 860 lis2hh12_dcrm_t *val); 861 862 typedef struct 863 { 864 uint16_t ig1_xlie : 1; 865 uint16_t ig1_xhie : 1; 866 uint16_t ig1_ylie : 1; 867 uint16_t ig1_yhie : 1; 868 uint16_t ig1_zlie : 1; 869 uint16_t ig1_zhie : 1; 870 uint16_t ig2_xlie : 1; 871 uint16_t ig2_xhie : 1; 872 uint16_t ig2_ylie : 1; 873 uint16_t ig2_yhie : 1; 874 uint16_t ig2_zlie : 1; 875 uint16_t ig2_zhie : 1; 876 } lis2hh12_xl_trshld_en_t; 877 int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx, 878 lis2hh12_xl_trshld_en_t val); 879 int32_t lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t *ctx, 880 lis2hh12_xl_trshld_en_t *val); 881 882 typedef struct 883 { 884 uint16_t ig1_xl : 1; 885 uint16_t ig1_xh : 1; 886 uint16_t ig1_yl : 1; 887 uint16_t ig1_yh : 1; 888 uint16_t ig1_zl : 1; 889 uint16_t ig1_zh : 1; 890 uint16_t ig1_ia : 1; 891 uint16_t ig2_xl : 1; 892 uint16_t ig2_xh : 1; 893 uint16_t ig2_yl : 1; 894 uint16_t ig2_yh : 1; 895 uint16_t ig2_zl : 1; 896 uint16_t ig2_zh : 1; 897 uint16_t ig2_ia : 1; 898 } lis2hh12_xl_trshld_src_t; 899 int32_t lis2hh12_xl_trshld_src_get(const stmdev_ctx_t *ctx, 900 lis2hh12_xl_trshld_src_t *val); 901 902 int32_t lis2hh12_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t ig1_x, 903 uint8_t ig1_y, uint8_t ig1_z, 904 uint8_t ig2_xyz); 905 int32_t lis2hh12_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *ig1_x, 906 uint8_t *ig1_y, uint8_t *ig1_z, 907 uint8_t *ig2_xyz); 908 909 int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, 910 uint8_t ig1_sam, uint8_t ig2_sam); 911 int32_t lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, 912 uint8_t *ig1_sam, uint8_t *ig2_sam); 913 914 int32_t lis2hh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 915 int32_t lis2hh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 916 917 int32_t lis2hh12_act_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 918 int32_t lis2hh12_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 919 920 typedef enum 921 { 922 LIS2HH12_6D_4D_DISABLE = 0x00, 923 LIS2HH12_ENABLE_ON_IG1_6D = 0x01, 924 LIS2HH12_ENABLE_ON_IG2_6D = 0x02, 925 LIS2HH12_ENABLE_ON_IG1_4D = 0x11, 926 LIS2HH12_ENABLE_ON_IG2_4D = 0x12, 927 } lis2hh12_6d_mode_t; 928 int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx, 929 lis2hh12_6d_mode_t val); 930 int32_t lis2hh12_6d_mode_get(const stmdev_ctx_t *ctx, 931 lis2hh12_6d_mode_t *val); 932 933 int32_t lis2hh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 934 int32_t lis2hh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 935 936 typedef enum 937 { 938 LIS2HH12_FIFO_OFF = 0x00, 939 LIS2HH12_BYPASS_MODE = 0x10, 940 LIS2HH12_FIFO_MODE = 0x11, 941 LIS2HH12_STREAM_MODE = 0x12, 942 LIS2HH12_STREAM_TO_FIFO_MODE = 0x13, 943 LIS2HH12_BYPASS_TO_STREAM_MODE = 0x14, 944 LIS2HH12_BYPASS_TO_FIFO_MODE = 0x17, 945 } lis2hh12_fifo_md_t; 946 int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx, 947 lis2hh12_fifo_md_t val); 948 int32_t lis2hh12_fifo_mode_get(const stmdev_ctx_t *ctx, 949 lis2hh12_fifo_md_t *val); 950 951 typedef struct 952 { 953 uint8_t fss : 5; 954 uint8_t empty : 1; 955 uint8_t ovr : 1; 956 uint8_t fth : 1; 957 } lis2hh12_fifo_stat_t; 958 int32_t lis2hh12_fifo_status_get(const stmdev_ctx_t *ctx, 959 lis2hh12_fifo_stat_t *val); 960 961 typedef enum 962 { 963 LIS2HH12_ST_DISABLE = 0x00, 964 LIS2HH12_ST_POSITIVE = 0x01, 965 LIS2HH12_ST_NEGATIVE = 0x02, 966 } lis2hh12_xl_st_t; 967 int32_t lis2hh12_xl_self_test_set(const stmdev_ctx_t *ctx, 968 lis2hh12_xl_st_t val); 969 int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, 970 lis2hh12_xl_st_t *val); 971 972 /** 973 *@} 974 * 975 */ 976 977 #ifdef __cplusplus 978 } 979 #endif 980 981 #endif /* LIS2HH12_REGS_H */ 982 983 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 984
