1 /**
2 ******************************************************************************
3 * @file lis2hh12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2HH12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #include "lis2hh12_reg.h"
20
21 /**
22 * @defgroup LIS2HH12
23 * @brief This file provides a set of functions needed to drive the
24 * lis2hh12 enhanced inertial module.
25 * @{
26 *
27 */
28
29 /**
30 * @defgroup LIS2HH12_Interfaces_Functions
31 * @brief This section provide a set of functions used to read and
32 * write a generic register of the device.
33 * MANDATORY: return 0 -> no Error.
34 * @{
35 *
36 */
37
38 /**
39 * @brief Read generic device register
40 *
41 * @param ctx read / write interface definitions(ptr)
42 * @param reg register to read
43 * @param data pointer to buffer that store the data read(ptr)
44 * @param len number of consecutive register to read
45 * @retval interface status (MANDATORY: return 0 -> no Error)
46 *
47 */
lis2hh12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)48 int32_t __weak lis2hh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
49 uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
lis2hh12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak lis2hh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
75 uint8_t *data,
76 uint16_t len)
77 {
78 int32_t ret;
79
80 if (ctx == NULL)
81 {
82 return -1;
83 }
84
85 ret = ctx->write_reg(ctx->handle, reg, data, len);
86
87 return ret;
88 }
89
90 /**
91 * @}
92 *
93 */
94
95 /**
96 * @defgroup LIS2HH12_Sensitivity
97 * @brief These functions convert raw-data into engineering units.
98 * @{
99 *
100 */
101
lis2hh12_from_fs2g_to_mg(int16_t lsb)102 float_t lis2hh12_from_fs2g_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb * 0.061f);
105 }
106
lis2hh12_from_fs4g_to_mg(int16_t lsb)107 float_t lis2hh12_from_fs4g_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb * 0.122f);
110 }
111
lis2hh12_from_fs8g_to_mg(int16_t lsb)112 float_t lis2hh12_from_fs8g_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb * 0.244f);
115 }
116
lis2hh12_from_lsb_to_celsius(int16_t lsb)117 float_t lis2hh12_from_lsb_to_celsius(int16_t lsb)
118 {
119 /* 8 LSB/C - 11bit resolution */
120 return ((((float_t)lsb / 32.0f) / 8.0f) + 25.0f);
121 }
122
123 /**
124 * @}
125 *
126 */
127
128 /**
129 * @defgroup LIS2HH12_Data_generation
130 * @brief This section groups all the functions concerning
131 * data generation
132 * @{
133 *
134 */
135
136 /**
137 * @brief Enable accelerometer axis.[set]
138 *
139 * @param ctx Read / write interface definitions.(ptr)
140 * @param val Accelerometer’s X-axis output enable.
141 * @retval Interface status (MANDATORY: return 0 -> no Error).
142 *
143 */
lis2hh12_xl_axis_set(const stmdev_ctx_t * ctx,lis2hh12_xl_axis_t val)144 int32_t lis2hh12_xl_axis_set(const stmdev_ctx_t *ctx,
145 lis2hh12_xl_axis_t val)
146 {
147 lis2hh12_ctrl1_t ctrl1;
148 int32_t ret;
149
150 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
151
152 if (ret == 0)
153 {
154 ctrl1.xen = val.xen;
155 ctrl1.yen = val.yen;
156 ctrl1.zen = val.zen;
157 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
158 }
159
160 return ret;
161 }
162
163 /**
164 * @brief Enable accelerometer axis.[get]
165 *
166 * @param ctx Read / write interface definitions.(ptr)
167 * @param val Accelerometer’s X-axis output enable.(ptr)
168 * @retval Interface status (MANDATORY: return 0 -> no Error).
169 *
170 */
lis2hh12_xl_axis_get(const stmdev_ctx_t * ctx,lis2hh12_xl_axis_t * val)171 int32_t lis2hh12_xl_axis_get(const stmdev_ctx_t *ctx,
172 lis2hh12_xl_axis_t *val)
173 {
174 lis2hh12_ctrl1_t ctrl1;
175 int32_t ret;
176
177 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
178 val->xen = ctrl1.xen;
179 val->yen = ctrl1.yen;
180 val->zen = ctrl1.zen;
181
182 return ret;
183 }
184
185 /**
186 * @brief Blockdataupdate.[set]
187 *
188 * @param ctx Read / write interface definitions.(ptr)
189 * @param val Change the values of bdu in reg CTRL1.
190 * @retval Interface status (MANDATORY: return 0 -> no Error).
191 *
192 */
lis2hh12_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)193 int32_t lis2hh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
194 {
195 lis2hh12_ctrl1_t ctrl1;
196 int32_t ret;
197
198 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
199
200 if (ret == 0)
201 {
202 ctrl1.bdu = (uint8_t)val;
203 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
204 }
205
206 return ret;
207 }
208
209 /**
210 * @brief Blockdataupdate.[get]
211 *
212 * @param ctx Read / write interface definitions.(ptr)
213 * @param val Get the values of bdu in reg CTRL1.(ptr)
214 * @retval Interface status (MANDATORY: return 0 -> no Error).
215 *
216 */
lis2hh12_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)217 int32_t lis2hh12_block_data_update_get(const stmdev_ctx_t *ctx,
218 uint8_t *val)
219 {
220 lis2hh12_ctrl1_t ctrl1;
221 int32_t ret;
222
223 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
224 *val = (uint8_t)ctrl1.bdu;
225
226 return ret;
227 }
228
229 /**
230 * @brief Accelerometer data rate selection.[set]
231 *
232 * @param ctx Read / write interface definitions.(ptr)
233 * @param val Change the values of "odr" in reg LIS2HH12.
234 * @retval Interface status (MANDATORY: return 0 -> no Error).
235 *
236 */
lis2hh12_xl_data_rate_set(const stmdev_ctx_t * ctx,lis2hh12_xl_data_rate_t val)237 int32_t lis2hh12_xl_data_rate_set(const stmdev_ctx_t *ctx,
238 lis2hh12_xl_data_rate_t val)
239 {
240 lis2hh12_ctrl1_t ctrl1;
241 int32_t ret;
242
243 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
244
245 if (ret == 0)
246 {
247 ctrl1.odr = (uint8_t)val;
248 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
249 }
250
251 return ret;
252 }
253
254 /**
255 * @brief Accelerometer data rate selection.[get]
256 *
257 * @param ctx Read / write interface definitions.(ptr)
258 * @param val Get the values of odr in reg CTRL1.(ptr)
259 * @retval Interface status (MANDATORY: return 0 -> no Error).
260 *
261 */
lis2hh12_xl_data_rate_get(const stmdev_ctx_t * ctx,lis2hh12_xl_data_rate_t * val)262 int32_t lis2hh12_xl_data_rate_get(const stmdev_ctx_t *ctx,
263 lis2hh12_xl_data_rate_t *val)
264 {
265 lis2hh12_ctrl1_t ctrl1;
266 int32_t ret;
267
268 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
269
270 switch (ctrl1.odr)
271 {
272 case LIS2HH12_XL_ODR_OFF:
273 *val = LIS2HH12_XL_ODR_OFF;
274 break;
275
276 case LIS2HH12_XL_ODR_10Hz:
277 *val = LIS2HH12_XL_ODR_10Hz;
278 break;
279
280 case LIS2HH12_XL_ODR_50Hz:
281 *val = LIS2HH12_XL_ODR_50Hz;
282 break;
283
284 case LIS2HH12_XL_ODR_100Hz:
285 *val = LIS2HH12_XL_ODR_100Hz;
286 break;
287
288 case LIS2HH12_XL_ODR_200Hz:
289 *val = LIS2HH12_XL_ODR_200Hz;
290 break;
291
292 case LIS2HH12_XL_ODR_400Hz:
293 *val = LIS2HH12_XL_ODR_400Hz;
294 break;
295
296 case LIS2HH12_XL_ODR_800Hz:
297 *val = LIS2HH12_XL_ODR_800Hz;
298 break;
299
300 default:
301 *val = LIS2HH12_XL_ODR_OFF;
302 break;
303 }
304
305 return ret;
306 }
307
308 /**
309 * @brief Accelerometer full-scale selection.[set]
310 *
311 * @param ctx Read / write interface definitions.(ptr)
312 * @param val Change the values of "fs" in reg LIS2HH12.
313 * @retval Interface status (MANDATORY: return 0 -> no Error).
314 *
315 */
lis2hh12_xl_full_scale_set(const stmdev_ctx_t * ctx,lis2hh12_xl_fs_t val)316 int32_t lis2hh12_xl_full_scale_set(const stmdev_ctx_t *ctx,
317 lis2hh12_xl_fs_t val)
318 {
319 lis2hh12_ctrl4_t ctrl4;
320 int32_t ret;
321
322 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
323
324 if (ret == 0)
325 {
326 ctrl4.fs = (uint8_t)val;
327 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Accelerometer full-scale selection.[get]
335 *
336 * @param ctx Read / write interface definitions.(ptr)
337 * @param val Get the values of fs in reg CTRL4.(ptr)
338 * @retval Interface status (MANDATORY: return 0 -> no Error).
339 *
340 */
lis2hh12_xl_full_scale_get(const stmdev_ctx_t * ctx,lis2hh12_xl_fs_t * val)341 int32_t lis2hh12_xl_full_scale_get(const stmdev_ctx_t *ctx,
342 lis2hh12_xl_fs_t *val)
343 {
344 lis2hh12_ctrl4_t ctrl4;
345 int32_t ret;
346
347 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
348
349 switch (ctrl4.fs)
350 {
351 case LIS2HH12_2g:
352 *val = LIS2HH12_2g;
353 break;
354
355 case LIS2HH12_4g:
356 *val = LIS2HH12_4g;
357 break;
358
359 case LIS2HH12_8g:
360 *val = LIS2HH12_8g;
361 break;
362
363 default:
364 *val = LIS2HH12_2g;
365 break;
366 }
367
368 return ret;
369 }
370
371 /**
372 * @brief Decimation of acceleration data on OUT REG and FIFO.[set]
373 *
374 * @param ctx Read / write interface definitions.(ptr)
375 * @param val Change the values of "dec" in reg LIS2HH12.
376 * @retval Interface status (MANDATORY: return 0 -> no Error).
377 *
378 */
lis2hh12_xl_decimation_set(const stmdev_ctx_t * ctx,lis2hh12_dec_t val)379 int32_t lis2hh12_xl_decimation_set(const stmdev_ctx_t *ctx,
380 lis2hh12_dec_t val)
381 {
382 lis2hh12_ctrl5_t ctrl5;
383 int32_t ret;
384
385 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
386
387 if (ret == 0)
388 {
389 ctrl5.dec = (uint8_t)val;
390 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
391 }
392
393 return ret;
394 }
395
396 /**
397 * @brief Decimation of acceleration data on OUT REG and FIFO.[get]
398 *
399 * @param ctx Read / write interface definitions.(ptr)
400 * @param val Get the values of dec in reg CTRL5.(ptr)
401 * @retval Interface status (MANDATORY: return 0 -> no Error).
402 *
403 */
lis2hh12_xl_decimation_get(const stmdev_ctx_t * ctx,lis2hh12_dec_t * val)404 int32_t lis2hh12_xl_decimation_get(const stmdev_ctx_t *ctx,
405 lis2hh12_dec_t *val)
406 {
407 lis2hh12_ctrl5_t ctrl5;
408 int32_t ret;
409
410 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
411
412 switch (ctrl5.dec)
413 {
414 case LIS2HH12_NO_DECIMATION:
415 *val = LIS2HH12_NO_DECIMATION;
416 break;
417
418 case LIS2HH12_EVERY_2_SAMPLES:
419 *val = LIS2HH12_EVERY_2_SAMPLES;
420 break;
421
422 case LIS2HH12_EVERY_4_SAMPLES:
423 *val = LIS2HH12_EVERY_4_SAMPLES;
424 break;
425
426 case LIS2HH12_EVERY_8_SAMPLES:
427 *val = LIS2HH12_EVERY_8_SAMPLES;
428 break;
429
430 default:
431 *val = LIS2HH12_NO_DECIMATION;
432 break;
433 }
434
435 return ret;
436 }
437
438 /**
439 * @brief New data available.[get]
440 *
441 * @param ctx Read / write interface definitions.(ptr)
442 * @param val Iet the values of "zyxda" in reg STATUS.(ptr)
443 * @retval Interface status (MANDATORY: return 0 -> no Error).
444 *
445 */
lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)446 int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
447 uint8_t *val)
448 {
449 lis2hh12_status_t status;
450 int32_t ret;
451
452 ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1);
453 *val = status.zyxda;
454
455 return ret;
456 }
457
458 /**
459 * @}
460 *
461 */
462
463 /**
464 * @defgroup LIS2HH12_Dataoutput
465 * @brief This section groups all the data output functions.
466 * @{
467 *
468 */
469
470 /**
471 * @brief Temperature data output register (r). L and H registers together
472 * express a 16-bit word in two’s complement.[get]
473 *
474 * @param ctx Read / write interface definitions.(ptr)
475 * @param buff Buffer that stores the data read.(ptr)
476 * @retval Interface status (MANDATORY: return 0 -> no Error).
477 *
478 */
lis2hh12_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)479 int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
480 {
481 uint8_t buff[2];
482 int32_t ret;
483
484 ret = lis2hh12_read_reg(ctx, LIS2HH12_TEMP_L, buff, 2);
485 *val = (int16_t)buff[1];
486 *val = (*val * 256) + (int16_t)buff[0];
487
488 return ret;
489 }
490
491 /**
492 * @brief Linear acceleration output register. The value is expressed
493 * as a 16-bit word in two’s complement.[get]
494 *
495 * @param ctx Read / write interface definitions.(ptr)
496 * @param buff Buffer that stores the data read.(ptr)
497 * @retval Interface status (MANDATORY: return 0 -> no Error).
498 *
499 */
lis2hh12_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)500 int32_t lis2hh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
501 {
502 uint8_t buff[6];
503 int32_t ret;
504
505 ret = lis2hh12_read_reg(ctx, LIS2HH12_OUT_X_L, buff, 6);
506 val[0] = (int16_t)buff[1];
507 val[0] = (val[0] * 256) + (int16_t)buff[0];
508 val[1] = (int16_t)buff[3];
509 val[1] = (val[1] * 256) + (int16_t)buff[2];
510 val[2] = (int16_t)buff[5];
511 val[2] = (val[2] * 256) + (int16_t)buff[4];
512
513 return ret;
514 }
515
516 /**
517 * @}
518 *
519 */
520
521 /**
522 * @defgroup LIS2HH12_Common
523 * @brief This section groups common useful functions.
524 * @{
525 *
526 */
527
528 /**
529 * @brief DeviceWhoamI.[get]
530 *
531 * @param ctx Read / write interface definitions.(ptr)
532 * @param buff Buffer that stores the data read.(ptr)
533 * @retval Interface status (MANDATORY: return 0 -> no Error).
534 *
535 */
lis2hh12_dev_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)536 int32_t lis2hh12_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
537 {
538 int32_t ret;
539
540 ret = lis2hh12_read_reg(ctx, LIS2HH12_WHO_AM_I, buff, 1);
541
542 return ret;
543 }
544
545 /**
546 * @brief Software reset. Restore the default values
547 * in user registers.[set]
548 *
549 * @param ctx Read / write interface definitions.(ptr)
550 * @param val Change the values of soft_reset in reg CTRL5.
551 * @retval Interface status (MANDATORY: return 0 -> no Error).
552 *
553 */
lis2hh12_dev_reset_set(const stmdev_ctx_t * ctx,uint8_t val)554 int32_t lis2hh12_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
555 {
556 lis2hh12_ctrl5_t ctrl5;
557 int32_t ret;
558
559 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
560
561 if (ret == 0)
562 {
563 ctrl5.soft_reset = (uint8_t)val;
564 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
565 }
566
567 return ret;
568 }
569
570 /**
571 * @brief Software reset. Restore the default values in
572 * user registers.[get]
573 *
574 * @param ctx Read / write interface definitions.(ptr)
575 * @param val Get the values of soft_reset in reg CTRL5.(ptr)
576 * @retval Interface status (MANDATORY: return 0 -> no Error).
577 *
578 */
lis2hh12_dev_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)579 int32_t lis2hh12_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
580 {
581 lis2hh12_ctrl5_t ctrl5;
582 int32_t ret;
583
584 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
585 *val = (uint8_t)ctrl5.soft_reset;
586
587 return ret;
588 }
589
590 /**
591 * @brief Reboot memory content. Reload the calibration parameters.[set]
592 *
593 * @param ctx Read / write interface definitions.(ptr)
594 * @param val Change the values of boot in reg CTRL6.
595 * @retval Interface status (MANDATORY: return 0 -> no Error).
596 *
597 */
lis2hh12_dev_boot_set(const stmdev_ctx_t * ctx,uint8_t val)598 int32_t lis2hh12_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
599 {
600 lis2hh12_ctrl6_t ctrl6;
601 int32_t ret;
602
603 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
604
605 if (ret == 0)
606 {
607 ctrl6.boot = (uint8_t)val;
608 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
609 }
610
611 return ret;
612 }
613
614 /**
615 * @brief Reboot memory content. Reload the calibration parameters.[get]
616 *
617 * @param ctx Read / write interface definitions.(ptr)
618 * @param val Get the values of boot in reg CTRL6.(ptr)
619 * @retval Interface status (MANDATORY: return 0 -> no Error).
620 *
621 */
lis2hh12_dev_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)622 int32_t lis2hh12_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
623 {
624 lis2hh12_ctrl6_t ctrl6;
625 int32_t ret;
626
627 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
628 *val = (uint8_t)ctrl6.boot;
629
630 return ret;
631 }
632
633 /**
634 * @brief Device status register.[get]
635 *
636 * @param ctx Read / write interface definitions.(ptr)
637 * @param val X-axis new data available.(ptr)
638 * @retval Interface status (MANDATORY: return 0 -> no Error).
639 *
640 */
lis2hh12_dev_status_get(const stmdev_ctx_t * ctx,lis2hh12_status_reg_t * val)641 int32_t lis2hh12_dev_status_get(const stmdev_ctx_t *ctx,
642 lis2hh12_status_reg_t *val)
643 {
644 lis2hh12_status_t status;
645 int32_t ret;
646
647 ret = lis2hh12_read_reg(ctx, LIS2HH12_STATUS, (uint8_t *)&status, 1);
648 val->xda = status.xda;
649 val->yda = status.yda;
650 val->zda = status.zda;
651 val->zyxda = status.zyxda;
652 val->_xor = status._xor;
653 val->yor = status.yor;
654 val->zor = status.zor;
655 val->zyxor = status.zyxor;
656
657 return ret;
658 }
659
660 /**
661 * @}
662 *
663 */
664
665 /**
666 * @defgroup LIS2HH12_Filters
667 * @brief This section group all the functions concerning the
668 * filters configuration
669 * @{
670 *
671 */
672
673 /**
674 * @brief Accelerometer filter routing on interrupt generators.[set]
675 *
676 * @param ctx Read / write interface definitions.(ptr)
677 * @param val Change the values of "hpis" in reg LIS2HH12.
678 * @retval Interface status (MANDATORY: return 0 -> no Error).
679 *
680 */
lis2hh12_xl_filter_int_path_set(const stmdev_ctx_t * ctx,lis2hh12_xl_hp_path_t val)681 int32_t lis2hh12_xl_filter_int_path_set(const stmdev_ctx_t *ctx,
682 lis2hh12_xl_hp_path_t val)
683 {
684 lis2hh12_ctrl2_t ctrl2;
685 int32_t ret;
686
687 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
688
689 if (ret == 0)
690 {
691 ctrl2.hpis = (uint8_t)val;
692 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
693 }
694
695 return ret;
696 }
697
698 /**
699 * @brief Accelerometer filter routing on interrupt generators.[get]
700 *
701 * @param ctx Read / write interface definitions.(ptr)
702 * @param val Get the values of hpis in reg CTRL2.(ptr)
703 * @retval Interface status (MANDATORY: return 0 -> no Error).
704 *
705 */
lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t * ctx,lis2hh12_xl_hp_path_t * val)706 int32_t lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t *ctx,
707 lis2hh12_xl_hp_path_t *val)
708 {
709 lis2hh12_ctrl2_t ctrl2;
710 int32_t ret;
711
712 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
713
714 switch (ctrl2.hpis)
715 {
716 case LIS2HH12_HP_DISABLE:
717 *val = LIS2HH12_HP_DISABLE;
718 break;
719
720 case LIS2HH12_HP_ON_INT_GEN_1:
721 *val = LIS2HH12_HP_ON_INT_GEN_1;
722 break;
723
724 case LIS2HH12_HP_ON_INT_GEN_2:
725 *val = LIS2HH12_HP_ON_INT_GEN_2;
726 break;
727
728 default:
729 *val = LIS2HH12_HP_DISABLE;
730 break;
731 }
732
733 return ret;
734 }
735
736 /**
737 * @brief Accelerometer output filter path configuration.[set]
738 *
739 * @param ctx Read / write interface definitions.(ptr)
740 * @param val Change the values of "fds" in reg LIS2HH12.
741 * @retval Interface status (MANDATORY: return 0 -> no Error).
742 *
743 */
lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t * ctx,lis2hh12_xl_out_path_t val)744 int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx,
745 lis2hh12_xl_out_path_t val)
746 {
747 lis2hh12_ctrl1_t ctrl1;
748 lis2hh12_ctrl2_t ctrl2;
749 int32_t ret;
750
751 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
752
753 if (ret == 0)
754 {
755 ctrl1.hr = (uint8_t)val;
756 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
757 }
758
759 if (ret == 0)
760 {
761 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
762 }
763
764 if (ret == 0)
765 {
766 ctrl2.fds = ((uint8_t) val & 0x02U) >> 1;
767 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
768 }
769
770 return ret;
771 }
772
773 /**
774 * @brief Accelerometer output filter path configuration.[get]
775 *
776 * @param ctx Read / write interface definitions.(ptr)
777 * @param val Get the values of fds in reg CTRL2.(ptr)
778 * @retval Interface status (MANDATORY: return 0 -> no Error).
779 *
780 */
lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t * ctx,lis2hh12_xl_out_path_t * val)781 int32_t lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t *ctx,
782 lis2hh12_xl_out_path_t *val)
783 {
784 lis2hh12_ctrl1_t ctrl1;
785 lis2hh12_ctrl2_t ctrl2;
786 int32_t ret;
787
788 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL1, (uint8_t *)&ctrl1, 1);
789
790 if (ret == 0)
791 {
792 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
793
794 switch ((ctrl2.fds << 1) | ctrl1.hr)
795 {
796 case LIS2HH12_BYPASSED:
797 *val = LIS2HH12_BYPASSED;
798 break;
799
800 case LIS2HH12_FILT_HP:
801 *val = LIS2HH12_FILT_HP;
802 break;
803
804 case LIS2HH12_FILT_LP:
805 *val = LIS2HH12_FILT_LP;
806 break;
807
808 default:
809 *val = LIS2HH12_BYPASSED;
810 break;
811 }
812 }
813
814 return ret;
815 }
816
817 /**
818 * @brief Accelerometer digital filter high pass cutoff
819 * frequency selection.[set]
820 *
821 * @param ctx Read / write interface definitions.(ptr)
822 * @param val Change the values of "hpm" in reg LIS2HH12.
823 * @retval Interface status (MANDATORY: return 0 -> no Error).
824 *
825 */
lis2hh12_xl_filter_hp_bandwidth_set(const stmdev_ctx_t * ctx,lis2hh12_xl_hp_bw_t val)826 int32_t lis2hh12_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx,
827 lis2hh12_xl_hp_bw_t val)
828 {
829 lis2hh12_ctrl2_t ctrl2;
830 int32_t ret;
831
832 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
833
834 if (ret == 0)
835 {
836 ctrl2.hpm = (uint8_t) val & 0x01U;
837 ctrl2.dfc = (((uint8_t) val & 0x30U) >> 4);
838 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
839 }
840
841 return ret;
842 }
843
844 /**
845 * @brief Accelerometer digital filter high pass cutoff frequency
846 * selection.[get]
847 *
848 * @param ctx Read / write interface definitions.(ptr)
849 * @param val Get the values of hpm in reg CTRL2.(ptr)
850 * @retval Interface status (MANDATORY: return 0 -> no Error).
851 *
852 */
lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t * ctx,lis2hh12_xl_hp_bw_t * val)853 int32_t lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx,
854 lis2hh12_xl_hp_bw_t *val)
855 {
856 lis2hh12_ctrl2_t ctrl2;
857 int32_t ret;
858
859 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
860
861 switch ((ctrl2.dfc << 4) | ctrl2.hpm)
862 {
863 case LIS2HH12_HP_ODR_DIV_50:
864 *val = LIS2HH12_HP_ODR_DIV_50;
865 break;
866
867 case LIS2HH12_HP_ODR_DIV_100:
868 *val = LIS2HH12_HP_ODR_DIV_100;
869 break;
870
871 case LIS2HH12_HP_ODR_DIV_9:
872 *val = LIS2HH12_HP_ODR_DIV_9;
873 break;
874
875 case LIS2HH12_HP_ODR_DIV_400:
876 *val = LIS2HH12_HP_ODR_DIV_400;
877 break;
878
879 case LIS2HH12_HP_ODR_DIV_50_REF_MD:
880 *val = LIS2HH12_HP_ODR_DIV_50_REF_MD;
881 break;
882
883 case LIS2HH12_HP_ODR_DIV_100_REF_MD:
884 *val = LIS2HH12_HP_ODR_DIV_100_REF_MD;
885 break;
886
887 case LIS2HH12_HP_ODR_DIV_9_REF_MD:
888 *val = LIS2HH12_HP_ODR_DIV_9_REF_MD;
889 break;
890
891 case LIS2HH12_HP_ODR_DIV_400_REF_MD:
892 *val = LIS2HH12_HP_ODR_DIV_400_REF_MD;
893 break;
894
895 default:
896 *val = LIS2HH12_HP_ODR_DIV_50;
897 break;
898 }
899
900 return ret;
901 }
902
903 /**
904 * @brief Accelerometer digital filter low pass cutoff frequency
905 * selection.[set]
906 *
907 * @param ctx Read / write interface definitions.(ptr)
908 * @param val Change the values of "dfc" in reg LIS2HH12.
909 * @retval Interface status (MANDATORY: return 0 -> no Error).
910 *
911 */
lis2hh12_xl_filter_low_bandwidth_set(const stmdev_ctx_t * ctx,lis2hh12_xl_lp_bw_t val)912 int32_t lis2hh12_xl_filter_low_bandwidth_set(const stmdev_ctx_t *ctx,
913 lis2hh12_xl_lp_bw_t val)
914 {
915 lis2hh12_ctrl2_t ctrl2;
916 int32_t ret;
917
918 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
919
920 if (ret == 0)
921 {
922 ctrl2.dfc = (uint8_t)val;
923 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
924 }
925
926 return ret;
927 }
928
929 /**
930 * @brief Accelerometer digital filter low pass cutoff frequency
931 * selection.[get]
932 *
933 * @param ctx Read / write interface definitions.(ptr)
934 * @param val Get the values of dfc in reg CTRL2.(ptr)
935 * @retval Interface status (MANDATORY: return 0 -> no Error).
936 *
937 */
lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t * ctx,lis2hh12_xl_lp_bw_t * val)938 int32_t lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t *ctx,
939 lis2hh12_xl_lp_bw_t *val)
940 {
941 lis2hh12_ctrl2_t ctrl2;
942 int32_t ret;
943
944 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL2, (uint8_t *)&ctrl2, 1);
945
946 switch (ctrl2.dfc)
947 {
948 case LIS2HH12_LP_ODR_DIV_50:
949 *val = LIS2HH12_LP_ODR_DIV_50;
950 break;
951
952 case LIS2HH12_LP_ODR_DIV_100:
953 *val = LIS2HH12_LP_ODR_DIV_100;
954 break;
955
956 case LIS2HH12_LP_ODR_DIV_9:
957 *val = LIS2HH12_LP_ODR_DIV_9;
958 break;
959
960 case LIS2HH12_LP_ODR_DIV_400:
961 *val = LIS2HH12_LP_ODR_DIV_400;
962 break;
963
964 default:
965 *val = LIS2HH12_LP_ODR_DIV_50;
966 break;
967 }
968
969 return ret;
970 }
971
972 /**
973 * @brief Set anti-aliasing filter bandwidth.[set]
974 *
975 * @param ctx Read / write interface definitions.(ptr)
976 * @param val Change the values of "bw_scale_odr" in reg LIS2HH12.
977 * @retval Interface status (MANDATORY: return 0 -> no Error).
978 *
979 */
lis2hh12_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t * ctx,lis2hh12_xl_filt_aa_bw_t val)980 int32_t lis2hh12_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx,
981 lis2hh12_xl_filt_aa_bw_t val)
982 {
983 lis2hh12_ctrl4_t ctrl4;
984 int32_t ret;
985
986 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
987
988 if (ret == 0)
989 {
990 ctrl4.bw_scale_odr = (((uint8_t) val & 0x10U) >> 4);
991 ctrl4.bw = (uint8_t)val;
992 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
993 }
994
995 return ret;
996 }
997
998 /**
999 * @brief Set anti-aliasing filter bandwidth.[get]
1000 *
1001 * @param ctx Read / write interface definitions.(ptr)
1002 * @param val Get the values of bw_scale_odr in reg CTRL4.(ptr)
1003 * @retval Interface status (MANDATORY: return 0 -> no Error).
1004 *
1005 */
lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t * ctx,lis2hh12_xl_filt_aa_bw_t * val)1006 int32_t lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx,
1007 lis2hh12_xl_filt_aa_bw_t *val)
1008 {
1009 lis2hh12_ctrl4_t ctrl4;
1010 int32_t ret;
1011
1012 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1013
1014 switch ((ctrl4.bw_scale_odr << 4) | ctrl4.bw)
1015 {
1016 case LIS2HH12_AUTO:
1017 *val = LIS2HH12_AUTO;
1018 break;
1019
1020 case LIS2HH12_408Hz:
1021 *val = LIS2HH12_408Hz;
1022 break;
1023
1024 case LIS2HH12_211Hz:
1025 *val = LIS2HH12_211Hz;
1026 break;
1027
1028 case LIS2HH12_105Hz:
1029 *val = LIS2HH12_105Hz;
1030 break;
1031
1032 case LIS2HH12_50Hz:
1033 *val = LIS2HH12_50Hz;
1034 break;
1035
1036 default:
1037 *val = LIS2HH12_AUTO;
1038 break;
1039 }
1040
1041 return ret;
1042 }
1043
1044 /**
1045 * @brief Reference value for acelerometer digital high-pass filter.[set]
1046 *
1047 * @param ctx Read / write interface definitions.(ptr)
1048 * @param buff Buffer that stores data to be write.(ptr)
1049 * @retval Interface status (MANDATORY: return 0 -> no Error).
1050 *
1051 */
lis2hh12_xl_filter_reference_set(const stmdev_ctx_t * ctx,int16_t * val)1052 int32_t lis2hh12_xl_filter_reference_set(const stmdev_ctx_t *ctx,
1053 int16_t *val)
1054 {
1055 uint8_t buff[6];
1056 int32_t ret;
1057
1058 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
1059 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
1060 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
1061 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
1062 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
1063 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
1064 ret = lis2hh12_write_reg(ctx, LIS2HH12_XL_REFERENCE, buff, 6);
1065
1066 return ret;
1067 }
1068
1069 /**
1070 * @brief Reference value for acelerometer digital high-pass filter.[get]
1071 *
1072 * @param ctx Read / write interface definitions.(ptr)
1073 * @param buff Buffer that stores data read.(ptr)
1074 * @retval Interface status (MANDATORY: return 0 -> no Error).
1075 *
1076 */
lis2hh12_xl_filter_reference_get(const stmdev_ctx_t * ctx,int16_t * val)1077 int32_t lis2hh12_xl_filter_reference_get(const stmdev_ctx_t *ctx,
1078 int16_t *val)
1079 {
1080 uint8_t buff[6];
1081 int32_t ret;
1082
1083 ret = lis2hh12_read_reg(ctx, LIS2HH12_XL_REFERENCE, buff, 6);
1084 val[0] = (int16_t)buff[1];
1085 val[0] = (val[0] * 256) + (int16_t)buff[0];
1086 val[1] = (int16_t)buff[3];
1087 val[1] = (val[1] * 256) + (int16_t)buff[2];
1088 val[2] = (int16_t)buff[5];
1089 val[2] = (val[2] * 256) + (int16_t)buff[4];
1090
1091 return ret;
1092 }
1093
1094 /**
1095 * @}
1096 *
1097 */
1098
1099 /**
1100 * @defgroup LIS2HH12_Serial_interface
1101 * @brief This section groups all the functions concerning main
1102 * serial interface management (not auxiliary)
1103 * @{
1104 *
1105 */
1106
1107 /**
1108 * @brief SPI Serial Interface Mode selection.[set]
1109 *
1110 * @param ctx Read / write interface definitions.(ptr)
1111 * @param val Change the values of "sim" in reg LIS2HH12.
1112 * @retval Interface status (MANDATORY: return 0 -> no Error).
1113 *
1114 */
lis2hh12_spi_mode_set(const stmdev_ctx_t * ctx,lis2hh12_sim_t val)1115 int32_t lis2hh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2hh12_sim_t val)
1116 {
1117 lis2hh12_ctrl4_t ctrl4;
1118 int32_t ret;
1119
1120 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1121
1122 if (ret == 0)
1123 {
1124 ctrl4.sim = (uint8_t)val;
1125 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1126 }
1127
1128 return ret;
1129 }
1130
1131 /**
1132 * @brief SPI Serial Interface Mode selection.[get]
1133 *
1134 * @param ctx Read / write interface definitions.(ptr)
1135 * @param val Get the values of sim in reg CTRL4.(ptr)
1136 * @retval Interface status (MANDATORY: return 0 -> no Error).
1137 *
1138 */
lis2hh12_spi_mode_get(const stmdev_ctx_t * ctx,lis2hh12_sim_t * val)1139 int32_t lis2hh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2hh12_sim_t *val)
1140 {
1141 lis2hh12_ctrl4_t ctrl4;
1142 int32_t ret;
1143
1144 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1145
1146 switch (ctrl4.sim)
1147 {
1148 case LIS2HH12_SPI_4_WIRE:
1149 *val = LIS2HH12_SPI_4_WIRE;
1150 break;
1151
1152 case LIS2HH12_SPI_3_WIRE:
1153 *val = LIS2HH12_SPI_3_WIRE;
1154 break;
1155
1156 default:
1157 *val = LIS2HH12_SPI_4_WIRE;
1158 break;
1159 }
1160
1161 return ret;
1162 }
1163
1164 /**
1165 * @brief Disable I2C interface.[set]
1166 *
1167 * @param ctx Read / write interface definitions.(ptr)
1168 * @param val Change the values of "i2c_disable" in reg LIS2HH12.
1169 * @retval Interface status (MANDATORY: return 0 -> no Error).
1170 *
1171 */
lis2hh12_i2c_interface_set(const stmdev_ctx_t * ctx,lis2hh12_i2c_dis_t val)1172 int32_t lis2hh12_i2c_interface_set(const stmdev_ctx_t *ctx,
1173 lis2hh12_i2c_dis_t val)
1174 {
1175 lis2hh12_ctrl4_t ctrl4;
1176 int32_t ret;
1177
1178 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1179
1180 if (ret == 0)
1181 {
1182 ctrl4.i2c_disable = (uint8_t)val;
1183 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1184 }
1185
1186 return ret;
1187 }
1188
1189 /**
1190 * @brief Disable I2C interface.[get]
1191 *
1192 * @param ctx Read / write interface definitions.(ptr)
1193 * @param val Get the values of i2c_disable in reg CTRL4.(ptr)
1194 * @retval Interface status (MANDATORY: return 0 -> no Error).
1195 *
1196 */
lis2hh12_i2c_interface_get(const stmdev_ctx_t * ctx,lis2hh12_i2c_dis_t * val)1197 int32_t lis2hh12_i2c_interface_get(const stmdev_ctx_t *ctx,
1198 lis2hh12_i2c_dis_t *val)
1199 {
1200 lis2hh12_ctrl4_t ctrl4;
1201 int32_t ret;
1202
1203 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1204
1205 switch (ctrl4.i2c_disable)
1206 {
1207 case LIS2HH12_I2C_ENABLE:
1208 *val = LIS2HH12_I2C_ENABLE;
1209 break;
1210
1211 case LIS2HH12_I2C_DISABLE:
1212 *val = LIS2HH12_I2C_DISABLE;
1213 break;
1214
1215 default:
1216 *val = LIS2HH12_I2C_ENABLE;
1217 break;
1218 }
1219
1220 return ret;
1221 }
1222
1223 /**
1224 * @brief Register address automatically incremented during a
1225 * multiple byte access with a serial interface.[set]
1226 *
1227 * @param ctx Read / write interface definitions.(ptr)
1228 * @param val Change the values of "if_add_inc" in reg LIS2HH12.
1229 * @retval Interface status (MANDATORY: return 0 -> no Error).
1230 *
1231 */
lis2hh12_auto_increment_set(const stmdev_ctx_t * ctx,lis2hh12_auto_inc_t val)1232 int32_t lis2hh12_auto_increment_set(const stmdev_ctx_t *ctx,
1233 lis2hh12_auto_inc_t val)
1234 {
1235 lis2hh12_ctrl4_t ctrl4;
1236 int32_t ret;
1237
1238 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1239
1240 if (ret == 0)
1241 {
1242 ctrl4.if_add_inc = (uint8_t)val;
1243 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1244 }
1245
1246 return ret;
1247 }
1248
1249 /**
1250 * @brief Register address automatically incremented during a multiple
1251 * byte access with a serial interface.[get]
1252 *
1253 * @param ctx Read / write interface definitions.(ptr)
1254 * @param val Get the values of if_add_inc in reg CTRL4.(ptr)
1255 * @retval Interface status (MANDATORY: return 0 -> no Error).
1256 *
1257 */
lis2hh12_auto_increment_get(const stmdev_ctx_t * ctx,lis2hh12_auto_inc_t * val)1258 int32_t lis2hh12_auto_increment_get(const stmdev_ctx_t *ctx,
1259 lis2hh12_auto_inc_t *val)
1260 {
1261 lis2hh12_ctrl4_t ctrl4;
1262 int32_t ret;
1263
1264 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL4, (uint8_t *)&ctrl4, 1);
1265
1266 switch (ctrl4.if_add_inc)
1267 {
1268 case LIS2HH12_DISABLE:
1269 *val = LIS2HH12_DISABLE;
1270 break;
1271
1272 case LIS2HH12_ENABLE:
1273 *val = LIS2HH12_ENABLE;
1274 break;
1275
1276 default:
1277 *val = LIS2HH12_DISABLE;
1278 break;
1279 }
1280
1281 return ret;
1282 }
1283
1284 /**
1285 * @}
1286 *
1287 */
1288
1289 /**
1290 * @defgroup LIS2HH12_Interrupt_pins
1291 * @brief This section groups all the functions that manage
1292 * interrupt pins
1293 * @{
1294 *
1295 */
1296
1297 /**
1298 * @brief Route a signal on INT 1 pin.[set]
1299 *
1300 * @param ctx Read / write interface definitions.(ptr)
1301 * @param val Accelerometer data ready on INT 1 pin.
1302 * @retval Interface status (MANDATORY: return 0 -> no Error).
1303 *
1304 */
lis2hh12_pin_int1_route_set(const stmdev_ctx_t * ctx,lis2hh12_pin_int1_route_t val)1305 int32_t lis2hh12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1306 lis2hh12_pin_int1_route_t val)
1307 {
1308 lis2hh12_ctrl3_t ctrl3;
1309 int32_t ret;
1310
1311 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
1312
1313 if (ret == 0)
1314 {
1315 ctrl3.int1_drdy = val.int1_drdy;
1316 ctrl3.int1_fth = val.int1_fth;
1317 ctrl3.int1_ovr = val.int1_ovr;
1318 ctrl3.int1_ig1 = val.int1_ig1;
1319 ctrl3.int1_ig2 = val.int1_ig2;
1320 ctrl3.int1_inact = val.int1_inact;
1321 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
1322 }
1323
1324 return ret;
1325 }
1326
1327 /**
1328 * @brief Route a signal on INT 1 pin.[get]
1329 *
1330 * @param ctx Read / write interface definitions.(ptr)
1331 * @param val Accelerometer data ready on INT 1 pin.(ptr)
1332 * @retval Interface status (MANDATORY: return 0 -> no Error).
1333 *
1334 */
lis2hh12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2hh12_pin_int1_route_t * val)1335 int32_t lis2hh12_pin_int1_route_get(const stmdev_ctx_t *ctx,
1336 lis2hh12_pin_int1_route_t *val)
1337 {
1338 lis2hh12_ctrl3_t ctrl3;
1339 int32_t ret;
1340
1341 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
1342 val->int1_drdy = ctrl3.int1_drdy;
1343 val->int1_fth = ctrl3.int1_fth;
1344 val->int1_ovr = ctrl3.int1_ovr;
1345 val->int1_ig1 = ctrl3.int1_ig1;
1346 val->int1_ig2 = ctrl3.int1_ig2;
1347 val->int1_inact = ctrl3.int1_inact;
1348
1349 return ret;
1350 }
1351
1352 /**
1353 * @brief Push-pull/open drain selection on interrupt pads.[set]
1354 *
1355 * @param ctx Read / write interface definitions.(ptr)
1356 * @param val Change the values of "pp_od" in reg LIS2HH12.
1357 * @retval Interface status (MANDATORY: return 0 -> no Error).
1358 *
1359 */
lis2hh12_pin_mode_set(const stmdev_ctx_t * ctx,lis2hh12_pp_od_t val)1360 int32_t lis2hh12_pin_mode_set(const stmdev_ctx_t *ctx, lis2hh12_pp_od_t val)
1361 {
1362 lis2hh12_ctrl5_t ctrl5;
1363 int32_t ret;
1364
1365 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1366
1367 if (ret == 0)
1368 {
1369 ctrl5.pp_od = (uint8_t)val;
1370 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1371 }
1372
1373 return ret;
1374 }
1375
1376 /**
1377 * @brief Push-pull/open drain selection on interrupt pads.[get]
1378 *
1379 * @param ctx Read / write interface definitions.(ptr)
1380 * @param val Get the values of pp_od in reg CTRL5.(ptr)
1381 * @retval Interface status (MANDATORY: return 0 -> no Error).
1382 *
1383 */
lis2hh12_pin_mode_get(const stmdev_ctx_t * ctx,lis2hh12_pp_od_t * val)1384 int32_t lis2hh12_pin_mode_get(const stmdev_ctx_t *ctx,
1385 lis2hh12_pp_od_t *val)
1386 {
1387 lis2hh12_ctrl5_t ctrl5;
1388 int32_t ret;
1389
1390 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1391
1392 switch (ctrl5.pp_od)
1393 {
1394 case LIS2HH12_PUSH_PULL:
1395 *val = LIS2HH12_PUSH_PULL;
1396 break;
1397
1398 case LIS2HH12_OPEN_DRAIN:
1399 *val = LIS2HH12_OPEN_DRAIN;
1400 break;
1401
1402 default:
1403 *val = LIS2HH12_PUSH_PULL;
1404 break;
1405 }
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Interrupt active-high/low.Interrupt active-high/low.[set]
1412 *
1413 * @param ctx Read / write interface definitions.(ptr)
1414 * @param val Change the values of "h_lactive" in reg LIS2HH12.
1415 * @retval Interface status (MANDATORY: return 0 -> no Error).
1416 *
1417 */
lis2hh12_pin_polarity_set(const stmdev_ctx_t * ctx,lis2hh12_pin_pol_t val)1418 int32_t lis2hh12_pin_polarity_set(const stmdev_ctx_t *ctx,
1419 lis2hh12_pin_pol_t val)
1420 {
1421 lis2hh12_ctrl5_t ctrl5;
1422 int32_t ret;
1423
1424 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1425
1426 if (ret == 0)
1427 {
1428 ctrl5.h_lactive = (uint8_t)val;
1429 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1430 }
1431
1432 return ret;
1433 }
1434
1435 /**
1436 * @brief Interrupt active-high/low.Interrupt active-high/low.[get]
1437 *
1438 * @param ctx Read / write interface definitions.(ptr)
1439 * @param val Get the values of h_lactive in reg CTRL5.(ptr)
1440 * @retval Interface status (MANDATORY: return 0 -> no Error).
1441 *
1442 */
lis2hh12_pin_polarity_get(const stmdev_ctx_t * ctx,lis2hh12_pin_pol_t * val)1443 int32_t lis2hh12_pin_polarity_get(const stmdev_ctx_t *ctx,
1444 lis2hh12_pin_pol_t *val)
1445 {
1446 lis2hh12_ctrl5_t ctrl5;
1447 int32_t ret;
1448
1449 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
1450
1451 switch (ctrl5.h_lactive)
1452 {
1453 case LIS2HH12_ACTIVE_HIGH:
1454 *val = LIS2HH12_ACTIVE_HIGH;
1455 break;
1456
1457 case LIS2HH12_ACTIVE_LOW:
1458 *val = LIS2HH12_ACTIVE_LOW;
1459 break;
1460
1461 default:
1462 *val = LIS2HH12_ACTIVE_HIGH;
1463 break;
1464 }
1465
1466 return ret;
1467 }
1468
1469 /**
1470 * @brief Route a signal on INT 2 pin.[set]
1471 *
1472 * @param ctx Read / write interface definitions.(ptr)
1473 * @param val Accelerometer data ready on INT2 pin.
1474 * @retval Interface status (MANDATORY: return 0 -> no Error).
1475 *
1476 */
lis2hh12_pin_int2_route_set(const stmdev_ctx_t * ctx,lis2hh12_pin_int2_route_t val)1477 int32_t lis2hh12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1478 lis2hh12_pin_int2_route_t val)
1479 {
1480 lis2hh12_ctrl6_t ctrl6;
1481 int32_t ret;
1482
1483 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
1484
1485 if (ret == 0)
1486 {
1487 ctrl6.int2_drdy = val.int2_drdy;
1488 ctrl6.int2_fth = val.int2_fth;
1489 ctrl6.int2_empty = val.int2_empty;
1490 ctrl6.int2_ig1 = val.int2_ig1;
1491 ctrl6.int2_ig2 = val.int2_ig2;
1492 ctrl6.int2_boot = val.int2_boot;
1493 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
1494 }
1495
1496 return ret;
1497 }
1498
1499 /**
1500 * @brief Route a signal on INT 2 pin.[get]
1501 *
1502 * @param ctx Read / write interface definitions.(ptr)
1503 * @param val Accelerometer data ready on INT2 pin.(ptr)
1504 * @retval Interface status (MANDATORY: return 0 -> no Error).
1505 *
1506 */
lis2hh12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2hh12_pin_int2_route_t * val)1507 int32_t lis2hh12_pin_int2_route_get(const stmdev_ctx_t *ctx,
1508 lis2hh12_pin_int2_route_t *val)
1509 {
1510 lis2hh12_ctrl6_t ctrl6;
1511 int32_t ret;
1512
1513 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL6, (uint8_t *)&ctrl6, 1);
1514 val->int2_drdy = ctrl6.int2_drdy;
1515 val->int2_fth = ctrl6.int2_fth;
1516 val->int2_empty = ctrl6.int2_empty;
1517 val->int2_ig1 = ctrl6.int2_ig1;
1518 val->int2_ig2 = ctrl6.int2_ig2;
1519 val->int2_boot = ctrl6.int2_boot;
1520
1521 return ret;
1522 }
1523
1524 /**
1525 * @brief Latched/pulsed interrupt.[set]
1526 *
1527 * @param ctx Read / write interface definitions.(ptr)
1528 * @param val Change the values of "lir" in reg LIS2HH12.
1529 * @retval Interface status (MANDATORY: return 0 -> no Error).
1530 *
1531 */
lis2hh12_pin_notification_set(const stmdev_ctx_t * ctx,lis2hh12_lir_t val)1532 int32_t lis2hh12_pin_notification_set(const stmdev_ctx_t *ctx,
1533 lis2hh12_lir_t val)
1534 {
1535 lis2hh12_ctrl7_t ctrl7;
1536 int32_t ret;
1537
1538 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1539
1540 if (ret == 0)
1541 {
1542 ctrl7.lir = (uint8_t)val;
1543 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1544 }
1545
1546 return ret;
1547 }
1548
1549 /**
1550 * @brief Latched/pulsed interrupt.[get]
1551 *
1552 * @param ctx Read / write interface definitions.(ptr)
1553 * @param val Get the values of lir in reg CTRL7.(ptr)
1554 * @retval Interface status (MANDATORY: return 0 -> no Error).
1555 *
1556 */
lis2hh12_pin_notification_get(const stmdev_ctx_t * ctx,lis2hh12_lir_t * val)1557 int32_t lis2hh12_pin_notification_get(const stmdev_ctx_t *ctx,
1558 lis2hh12_lir_t *val)
1559 {
1560 lis2hh12_ctrl7_t ctrl7;
1561 int32_t ret;
1562
1563 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1564
1565 switch (ctrl7.lir)
1566 {
1567 case LIS2HH12_INT_PULSED:
1568 *val = LIS2HH12_INT_PULSED;
1569 break;
1570
1571 case LIS2HH12_INT_LATCHED:
1572 *val = LIS2HH12_INT_LATCHED;
1573 break;
1574
1575 default:
1576 *val = LIS2HH12_INT_PULSED;
1577 break;
1578 }
1579
1580 return ret;
1581 }
1582
1583 /**
1584 * @brief AND/OR combination of accelerometer’s interrupt events.[set]
1585 *
1586 * @param ctx Read / write interface definitions.(ptr)
1587 * @param val Change the values of "aoi" in reg LIS2HH12.
1588 * @retval Interface status (MANDATORY: return 0 -> no Error).
1589 *
1590 */
lis2hh12_pin_logic_set(const stmdev_ctx_t * ctx,lis2hh12_pin_logic_t val)1591 int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx,
1592 lis2hh12_pin_logic_t val)
1593 {
1594 lis2hh12_ig_cfg1_t ig_cfg1;
1595 lis2hh12_ig_cfg2_t ig_cfg2;
1596 int32_t ret;
1597
1598 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1599
1600 if (ret == 0)
1601 {
1602 ig_cfg1.aoi = (uint8_t)val;
1603 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1604 }
1605
1606 if (ret == 0)
1607 {
1608 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1609 }
1610
1611 if (ret == 0)
1612 {
1613 ig_cfg2.aoi = (((uint8_t) val & 0x02U) >> 1);
1614 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1615 }
1616
1617 return ret;
1618 }
1619
1620 /**
1621 * @brief AND/OR combination of accelerometer’s interrupt events.[get]
1622 *
1623 * @param ctx Read / write interface definitions.(ptr)
1624 * @param val Get the values of aoi in reg IG_CFG1.(ptr)
1625 * @retval Interface status (MANDATORY: return 0 -> no Error).
1626 *
1627 */
lis2hh12_pin_logic_get(const stmdev_ctx_t * ctx,lis2hh12_pin_logic_t * val)1628 int32_t lis2hh12_pin_logic_get(const stmdev_ctx_t *ctx,
1629 lis2hh12_pin_logic_t *val)
1630 {
1631 lis2hh12_ig_cfg1_t ig_cfg1;
1632 lis2hh12_ig_cfg2_t ig_cfg2;
1633 int32_t ret;
1634
1635 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1636
1637 if (ret == 0)
1638 {
1639 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1640 }
1641
1642 switch ((ig_cfg2.aoi << 1) | ig_cfg1.aoi)
1643 {
1644 case LIS2HH12_IG1_OR_IG2_OR:
1645 *val = LIS2HH12_IG1_OR_IG2_OR;
1646 break;
1647
1648 case LIS2HH12_IG1_AND_IG2_OR:
1649 *val = LIS2HH12_IG1_AND_IG2_OR;
1650 break;
1651
1652 case LIS2HH12_IG1_OR_IG2_AND:
1653 *val = LIS2HH12_IG1_OR_IG2_AND;
1654 break;
1655
1656 case LIS2HH12_IG1_AND_IG2_AND:
1657 *val = LIS2HH12_IG1_AND_IG2_AND;
1658 break;
1659
1660 default:
1661 *val = LIS2HH12_IG1_OR_IG2_OR;
1662 break;
1663 }
1664
1665 return ret;
1666 }
1667
1668 /**
1669 * @}
1670 *
1671 */
1672
1673 /**
1674 * @defgroup LIS2HH12_Interrupt_on_threshold
1675 * @brief This section group all the functions concerning the
1676 * interrupt on threshold configuration
1677 * @{
1678 *
1679 */
1680
1681 /**
1682 * @brief Decrement or reset counter mode selection.[set]
1683 *
1684 * @param ctx Read / write interface definitions.(ptr)
1685 * @param val Change the values of "dcrm" in reg LIS2HH12.
1686 * @retval Interface status (MANDATORY: return 0 -> no Error).
1687 *
1688 */
lis2hh12_xl_trshld_mode_set(const stmdev_ctx_t * ctx,lis2hh12_dcrm_t val)1689 int32_t lis2hh12_xl_trshld_mode_set(const stmdev_ctx_t *ctx,
1690 lis2hh12_dcrm_t val)
1691 {
1692 lis2hh12_ctrl7_t ctrl7;
1693 int32_t ret;
1694
1695 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1696
1697 if (ret == 0)
1698 {
1699 ctrl7.dcrm = (uint8_t)val;
1700 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1701 }
1702
1703 return ret;
1704 }
1705
1706 /**
1707 * @brief Decrement or reset counter mode selection.[get]
1708 *
1709 * @param ctx Read / write interface definitions.(ptr)
1710 * @param val Get the values of dcrm in reg CTRL7.(ptr)
1711 * @retval Interface status (MANDATORY: return 0 -> no Error).
1712 *
1713 */
lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t * ctx,lis2hh12_dcrm_t * val)1714 int32_t lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t *ctx,
1715 lis2hh12_dcrm_t *val)
1716 {
1717 lis2hh12_ctrl7_t ctrl7;
1718 int32_t ret;
1719
1720 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
1721
1722 switch (ctrl7.dcrm)
1723 {
1724 case LIS2HH12_RESET_MODE:
1725 *val = LIS2HH12_RESET_MODE;
1726 break;
1727
1728 case LIS2HH12_DECREMENT_MODE:
1729 *val = LIS2HH12_DECREMENT_MODE;
1730 break;
1731
1732 default:
1733 *val = LIS2HH12_RESET_MODE;
1734 break;
1735 }
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief Enable interrupt generation on threshold event.[set]
1742 *
1743 * @param ctx Read / write interface definitions.(ptr)
1744 * @param val Enable interrupt generation on accelerometer’s
1745 * X-axis low event.
1746 * @retval Interface status (MANDATORY: return 0 -> no Error).
1747 *
1748 */
lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t * ctx,lis2hh12_xl_trshld_en_t val)1749 int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx,
1750 lis2hh12_xl_trshld_en_t val)
1751 {
1752 lis2hh12_ig_cfg1_t ig_cfg1;
1753 lis2hh12_ig_cfg2_t ig_cfg2;
1754 int32_t ret;
1755
1756 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1757
1758 if (ret == 0)
1759 {
1760 ig_cfg1.xlie = (uint8_t)val.ig1_xlie;
1761 ig_cfg1.xhie = (uint8_t)val.ig1_xhie;
1762 ig_cfg1.ylie = (uint8_t)val.ig1_ylie;
1763 ig_cfg1.yhie = (uint8_t)val.ig1_yhie;
1764 ig_cfg1.zlie = (uint8_t)val.ig1_zlie;
1765 ig_cfg1.zhie = (uint8_t)val.ig1_zhie;
1766 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1767 }
1768
1769 if (ret == 0)
1770 {
1771 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1772 }
1773
1774 if (ret == 0)
1775 {
1776 ig_cfg2.xlie = (uint8_t)val.ig2_xlie;
1777 ig_cfg2.xhie = (uint8_t)val.ig2_xhie;
1778 ig_cfg2.ylie = (uint8_t)val.ig2_ylie;
1779 ig_cfg2.yhie = (uint8_t)val.ig2_yhie;
1780 ig_cfg2.zlie = (uint8_t)val.ig2_zlie;
1781 ig_cfg2.zhie = (uint8_t)val.ig2_zhie;
1782 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1783 }
1784
1785 return ret;
1786 }
1787
1788 /**
1789 * @brief Enable interrupt generation on threshold event.[get]
1790 *
1791 * @param ctx Read / write interface definitions.(ptr)
1792 * @param val Enable interrupt generation on accelerometer’s
1793 * X-axis low event.(ptr)
1794 * @retval Interface status (MANDATORY: return 0 -> no Error).
1795 *
1796 */
lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t * ctx,lis2hh12_xl_trshld_en_t * val)1797 int32_t lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t *ctx,
1798 lis2hh12_xl_trshld_en_t *val)
1799 {
1800 lis2hh12_ig_cfg1_t ig_cfg1;
1801 lis2hh12_ig_cfg2_t ig_cfg2;
1802 int32_t ret;
1803
1804 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
1805
1806 if (ret == 0)
1807 {
1808 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
1809 }
1810
1811 val->ig1_xlie = ig_cfg1.xlie;
1812 val->ig1_xhie = ig_cfg1.xhie;
1813 val->ig1_ylie = ig_cfg1.ylie;
1814 val->ig1_yhie = ig_cfg1.yhie;
1815 val->ig1_zlie = ig_cfg1.zlie;
1816 val->ig1_zhie = ig_cfg1.zhie;
1817 val->ig2_xlie = ig_cfg2.xlie;
1818 val->ig2_xhie = ig_cfg2.xhie;
1819 val->ig2_ylie = ig_cfg2.ylie;
1820 val->ig2_yhie = ig_cfg2.yhie;
1821 val->ig2_zlie = ig_cfg2.zlie;
1822 val->ig2_zhie = ig_cfg2.zhie;
1823
1824 return ret;
1825 }
1826
1827 /**
1828 * @brief Accelerometer interrupt on threshold source.[get]
1829 *
1830 * @param ctx Read / write interface definitions.(ptr)
1831 * @param val Accelerometer’s X low. event.(ptr)
1832 * @retval Interface status (MANDATORY: return 0 -> no Error).
1833 *
1834 */
lis2hh12_xl_trshld_src_get(const stmdev_ctx_t * ctx,lis2hh12_xl_trshld_src_t * val)1835 int32_t lis2hh12_xl_trshld_src_get(const stmdev_ctx_t *ctx,
1836 lis2hh12_xl_trshld_src_t *val)
1837 {
1838 lis2hh12_ig_src1_t ig_src1;
1839 lis2hh12_ig_src2_t ig_src2;
1840 int32_t ret;
1841
1842 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC1, (uint8_t *)&ig_src1, 1);
1843
1844 if (ret == 0)
1845 {
1846 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_SRC2, (uint8_t *)&ig_src2, 1);
1847 }
1848
1849 val->ig1_xl = ig_src1.xl;
1850 val->ig1_xh = ig_src1.xh;
1851 val->ig1_yl = ig_src1.yl;
1852 val->ig1_yh = ig_src1.yh;
1853 val->ig1_zl = ig_src1.zl;
1854 val->ig1_zh = ig_src1.zh;
1855 val->ig1_ia = ig_src1.ia;
1856 val->ig2_xl = ig_src2.xl;
1857 val->ig2_xh = ig_src2.xh;
1858 val->ig2_yl = ig_src2.yl;
1859 val->ig2_yh = ig_src2.yh;
1860 val->ig2_zl = ig_src2.zl;
1861 val->ig2_zh = ig_src2.zh;
1862 val->ig2_ia = ig_src2.ia;
1863
1864 return ret;
1865 }
1866
1867 /**
1868 * @brief Axis interrupt threshold.[set]
1869 *
1870 * @param ctx Read / write interface definitions.(ptr)
1871 * @param buff Buffer that stores data to be write.(ptr)
1872 * @retval Interface status (MANDATORY: return 0 -> no Error).
1873 *
1874 */
lis2hh12_xl_trshld_set(const stmdev_ctx_t * ctx,uint8_t ig1_x,uint8_t ig1_y,uint8_t ig1_z,uint8_t ig2_xyz)1875 int32_t lis2hh12_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t ig1_x,
1876 uint8_t ig1_y, uint8_t ig1_z,
1877 uint8_t ig2_xyz)
1878 {
1879 int32_t ret;
1880
1881 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_X1, &ig1_x, 1);
1882
1883 if (ret == 0)
1884 {
1885 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_Y1, &ig1_y, 1);
1886 }
1887
1888 if (ret == 0)
1889 {
1890 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS_Z1, &ig1_z, 1);
1891 }
1892
1893 if (ret == 0)
1894 {
1895 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_THS2, &ig2_xyz, 1);
1896 }
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @brief Axis interrupt threshold.[get]
1903 *
1904 * @param ctx Read / write interface definitions.(ptr)
1905 * @param buff Buffer that stores data read.(ptr)
1906 * @retval Interface status (MANDATORY: return 0 -> no Error).
1907 *
1908 */
lis2hh12_xl_trshld_get(const stmdev_ctx_t * ctx,uint8_t * ig1_x,uint8_t * ig1_y,uint8_t * ig1_z,uint8_t * ig2_xyz)1909 int32_t lis2hh12_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *ig1_x,
1910 uint8_t *ig1_y, uint8_t *ig1_z,
1911 uint8_t *ig2_xyz)
1912 {
1913 int32_t ret;
1914
1915 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_X1, ig1_x, 1);
1916
1917 if (ret == 0)
1918 {
1919 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_Y1, ig1_y, 1);
1920 }
1921
1922 if (ret == 0)
1923 {
1924 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS_Z1, ig1_z, 1);
1925 }
1926
1927 if (ret == 0)
1928 {
1929 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_THS2, ig2_xyz, 1);
1930 }
1931
1932 return ret;
1933 }
1934
1935 /**
1936 * @brief Enter/exit interrupt duration value.[set]
1937 *
1938 * @param ctx Read / write interface definitions.(ptr)
1939 * @param val Change the values of dur1 in reg IG_DUR1.
1940 * @retval Interface status (MANDATORY: return 0 -> no Error).
1941 *
1942 */
lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t * ctx,uint8_t ig1_sam,uint8_t ig2_sam)1943 int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx,
1944 uint8_t ig1_sam, uint8_t ig2_sam)
1945 {
1946 lis2hh12_ig_dur1_t ig_dur1;
1947 lis2hh12_ig_dur2_t ig_dur2;
1948 int32_t ret;
1949
1950 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
1951
1952 if (ret == 0)
1953 {
1954 if (ig1_sam == 0x00U)
1955 {
1956 ig_dur1.wait1 = PROPERTY_DISABLE;
1957 }
1958
1959 else
1960 {
1961 ig_dur1.wait1 = PROPERTY_ENABLE;
1962 }
1963
1964 ig_dur1.dur1 = ig1_sam;
1965 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
1966 }
1967
1968 if (ret == 0)
1969 {
1970 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
1971 }
1972
1973 if (ret == 0)
1974 {
1975 if (ig2_sam == 0x00U)
1976 {
1977 ig_dur2.wait2 = PROPERTY_DISABLE;
1978 }
1979
1980 else
1981 {
1982 ig_dur2.wait2 = PROPERTY_ENABLE;
1983 }
1984
1985 ig_dur2.dur2 = ig2_sam;
1986 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
1987 }
1988
1989 return ret;
1990 }
1991
1992 /**
1993 * @brief Enter/exit interrupt duration value.[get]
1994 *
1995 * @param ctx Read / write interface definitions.(ptr)
1996 * @param val Get the values of dur1 in reg IG_DUR1.(ptr)
1997 * @retval Interface status (MANDATORY: return 0 -> no Error).
1998 *
1999 */
lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t * ctx,uint8_t * ig1_sam,uint8_t * ig2_sam)2000 int32_t lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx,
2001 uint8_t *ig1_sam, uint8_t *ig2_sam)
2002 {
2003 lis2hh12_ig_dur1_t ig_dur1;
2004 lis2hh12_ig_dur2_t ig_dur2;
2005 int32_t ret;
2006
2007 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR1, (uint8_t *)&ig_dur1, 1);
2008 *ig1_sam = (uint8_t)ig_dur1.dur1;
2009
2010 if (ret == 0)
2011 {
2012 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_DUR2, (uint8_t *)&ig_dur2, 1);
2013 *ig2_sam = (uint8_t)ig_dur2.dur2;
2014 }
2015
2016 return ret;
2017 }
2018
2019 /**
2020 * @}
2021 *
2022 */
2023
2024 /**
2025 * @defgroup LIS2HH12_Activity/Inactivity_detection
2026 * @brief This section groups all the functions concerning
2027 * activity/inactivity detection.
2028 * @{
2029 *
2030 */
2031
2032 /**
2033 * @brief Inactivity threshold.[set]
2034 *
2035 * @param ctx Read / write interface definitions.(ptr)
2036 * @param val Change the values of ths in reg ACT_THS.
2037 * @retval Interface status (MANDATORY: return 0 -> no Error).
2038 *
2039 */
lis2hh12_act_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2040 int32_t lis2hh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2041 {
2042 lis2hh12_act_ths_t act_ths;
2043 int32_t ret;
2044
2045 ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
2046
2047 if (ret == 0)
2048 {
2049 act_ths.ths = (uint8_t)val;
2050 ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
2051 }
2052
2053 return ret;
2054 }
2055
2056 /**
2057 * @brief Inactivity threshold.[get]
2058 *
2059 * @param ctx Read / write interface definitions.(ptr)
2060 * @param val Get the values of ths in reg ACT_THS.(ptr)
2061 * @retval Interface status (MANDATORY: return 0 -> no Error).
2062 *
2063 */
lis2hh12_act_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2064 int32_t lis2hh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2065 {
2066 lis2hh12_act_ths_t act_ths;
2067 int32_t ret;
2068
2069 ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_THS, (uint8_t *)&act_ths, 1);
2070 *val = (uint8_t)act_ths.ths;
2071
2072 return ret;
2073 }
2074
2075 /**
2076 * @brief Inactivity duration in number of sample.[set]
2077 *
2078 * @param ctx Read / write interface definitions.(ptr)
2079 * @param val Change the values of dur in reg ACT_DUR.
2080 * @retval Interface status (MANDATORY: return 0 -> no Error).
2081 *
2082 */
lis2hh12_act_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2083 int32_t lis2hh12_act_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
2084 {
2085 lis2hh12_act_dur_t act_dur;
2086 int32_t ret;
2087
2088 ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
2089
2090 if (ret == 0)
2091 {
2092 act_dur.dur = (uint8_t)val;
2093 ret = lis2hh12_write_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
2094 }
2095
2096 return ret;
2097 }
2098
2099 /**
2100 * @brief Inactivity duration in number of sample.[get]
2101 *
2102 * @param ctx Read / write interface definitions.(ptr)
2103 * @param val Get the values of dur in reg ACT_DUR.(ptr)
2104 * @retval Interface status (MANDATORY: return 0 -> no Error).
2105 *
2106 */
lis2hh12_act_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2107 int32_t lis2hh12_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
2108 {
2109 lis2hh12_act_dur_t act_dur;
2110 int32_t ret;
2111
2112 ret = lis2hh12_read_reg(ctx, LIS2HH12_ACT_DUR, (uint8_t *)&act_dur, 1);
2113 *val = (uint8_t)act_dur.dur;
2114
2115 return ret;
2116 }
2117
2118 /**
2119 * @}
2120 *
2121 */
2122
2123 /**
2124 * @defgroup LIS2HH12_Six_position_detection(6D/4D).
2125 * @brief This section groups all the functions concerning six
2126 * position detection (6D).
2127 * @{
2128 *
2129 */
2130
2131 /**
2132 * @brief 6D feature working mode.[set]
2133 *
2134 * @param ctx Read / write interface definitions.(ptr)
2135 * @param val Configure 6D feature working mode.
2136 * @retval Interface status (MANDATORY: return 0 -> no Error).
2137 *
2138 */
lis2hh12_6d_mode_set(const stmdev_ctx_t * ctx,lis2hh12_6d_mode_t val)2139 int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx,
2140 lis2hh12_6d_mode_t val)
2141 {
2142 lis2hh12_ig_cfg1_t ig_cfg1;
2143 lis2hh12_ig_cfg2_t ig_cfg2;
2144 lis2hh12_ctrl7_t ctrl7;
2145 int32_t ret;
2146
2147 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
2148
2149 if (ret == 0)
2150 {
2151 ctrl7._4d_ig = ((uint8_t)val & 0x10U) >> 4;
2152 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
2153 }
2154
2155 if (ret == 0)
2156 {
2157 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
2158 }
2159
2160 if (ret == 0)
2161 {
2162 ig_cfg2._6d = ((uint8_t)val & 0x02U) >> 1;
2163 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
2164 }
2165
2166 if (ret == 0)
2167 {
2168 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
2169 }
2170
2171 if (ret == 0)
2172 {
2173 ig_cfg1._6d = (uint8_t)val & 0x01U;
2174 ret = lis2hh12_write_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
2175 }
2176
2177 return ret;
2178 }
2179
2180 /**
2181 * @brief 6D feature working mode.[get]
2182 *
2183 * @param ctx Read / write interface definitions.(ptr)
2184 * @param val Get the configuration of 6D feature.(ptr)
2185 * @retval Interface status (MANDATORY: return 0 -> no Error).
2186 *
2187 */
lis2hh12_6d_mode_get(const stmdev_ctx_t * ctx,lis2hh12_6d_mode_t * val)2188 int32_t lis2hh12_6d_mode_get(const stmdev_ctx_t *ctx,
2189 lis2hh12_6d_mode_t *val)
2190 {
2191 lis2hh12_ig_cfg1_t ig_cfg1;
2192 lis2hh12_ig_cfg2_t ig_cfg2;
2193 lis2hh12_ctrl7_t ctrl7;
2194 int32_t ret;
2195
2196 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL7, (uint8_t *)&ctrl7, 1);
2197
2198 if (ret == 0)
2199 {
2200 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG2, (uint8_t *)&ig_cfg2, 1);
2201 }
2202
2203 if (ret == 0)
2204 {
2205 ret = lis2hh12_read_reg(ctx, LIS2HH12_IG_CFG1, (uint8_t *)&ig_cfg1, 1);
2206 }
2207
2208 switch ((ctrl7._4d_ig << 4) | (ig_cfg2._6d << 1) | ig_cfg1._6d)
2209 {
2210 case LIS2HH12_6D_4D_DISABLE:
2211 *val = LIS2HH12_6D_4D_DISABLE;
2212 break;
2213
2214 case LIS2HH12_ENABLE_ON_IG1_6D:
2215 *val = LIS2HH12_ENABLE_ON_IG1_6D;
2216 break;
2217
2218 case LIS2HH12_ENABLE_ON_IG2_6D:
2219 *val = LIS2HH12_ENABLE_ON_IG2_6D;
2220 break;
2221
2222 case LIS2HH12_ENABLE_ON_IG1_4D:
2223 *val = LIS2HH12_ENABLE_ON_IG1_4D;
2224 break;
2225
2226 case LIS2HH12_ENABLE_ON_IG2_4D:
2227 *val = LIS2HH12_ENABLE_ON_IG2_4D;
2228 break;
2229
2230 default:
2231 *val = LIS2HH12_6D_4D_DISABLE;
2232 break;
2233 }
2234
2235 return ret;
2236 }
2237
2238 /**
2239 * @}
2240 *
2241 */
2242
2243 /**
2244 * @defgroup LIS2HH12_Fifo
2245 * @brief This section group all the functions concerning
2246 * the fifo usage
2247 * @{
2248 *
2249 */
2250
2251 /**
2252 * @brief FIFO watermark level selection.[set]
2253 *
2254 * @param ctx Read / write interface definitions.(ptr)
2255 * @param val Change the values of stop_fth in reg CTRL3.
2256 * @retval Interface status (MANDATORY: return 0 -> no Error).
2257 *
2258 */
lis2hh12_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)2259 int32_t lis2hh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
2260 {
2261 lis2hh12_fifo_ctrl_t fifo_ctrl;
2262 lis2hh12_ctrl3_t ctrl3;
2263 int32_t ret;
2264
2265 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
2266
2267 if (ret == 0)
2268 {
2269 ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
2270 (uint8_t *)&fifo_ctrl, 1);
2271 }
2272
2273 if (ret == 0)
2274 {
2275 if (val == 0x00U)
2276 {
2277 ctrl3.stop_fth = PROPERTY_DISABLE;
2278 }
2279
2280 else
2281 {
2282 ctrl3.stop_fth = PROPERTY_ENABLE;
2283 }
2284
2285 fifo_ctrl.fth = val;
2286 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
2287 }
2288
2289 if (ret == 0)
2290 {
2291 ret = lis2hh12_write_reg(ctx, LIS2HH12_FIFO_CTRL,
2292 (uint8_t *)&fifo_ctrl, 1);
2293 }
2294
2295 return ret;
2296 }
2297
2298 /**
2299 * @brief FIFO watermark level selection.[get]
2300 *
2301 * @param ctx Read / write interface definitions.(ptr)
2302 * @param val Get the values of stop_fth in reg CTRL3.(ptr)
2303 * @retval Interface status (MANDATORY: return 0 -> no Error).
2304 *
2305 */
lis2hh12_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)2306 int32_t lis2hh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
2307 {
2308 lis2hh12_fifo_ctrl_t fifo_ctrl;
2309 int32_t ret;
2310
2311 ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
2312 (uint8_t *)&fifo_ctrl, 1);
2313 *val = (uint8_t)fifo_ctrl.fth;
2314
2315 return ret;
2316 }
2317
2318 /**
2319 * @brief FIFO mode selection.[set]
2320 *
2321 * @param ctx Read / write interface definitions.(ptr)
2322 * @param val Change the values of "fifo_en" in reg LIS2HH12.
2323 * @retval Interface status (MANDATORY: return 0 -> no Error).
2324 *
2325 */
lis2hh12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2hh12_fifo_md_t val)2326 int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx,
2327 lis2hh12_fifo_md_t val)
2328 {
2329 lis2hh12_fifo_ctrl_t fifo_ctrl;
2330 lis2hh12_ctrl3_t ctrl3;
2331 int32_t ret;
2332
2333 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
2334
2335 if (ret == 0)
2336 {
2337 ctrl3.fifo_en = (((uint8_t) val & 0x10U) >> 4);
2338 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
2339 }
2340
2341 if (ret == 0)
2342 {
2343 ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
2344 (uint8_t *)&fifo_ctrl, 1);
2345 }
2346
2347 if (ret == 0)
2348 {
2349 fifo_ctrl.fmode = ((uint8_t)val & 0x0FU);
2350 ret = lis2hh12_write_reg(ctx, LIS2HH12_FIFO_CTRL,
2351 (uint8_t *)&fifo_ctrl, 1);
2352 }
2353
2354 return ret;
2355 }
2356
2357 /**
2358 * @brief FIFO mode selection.[get]
2359 *
2360 * @param ctx Read / write interface definitions.(ptr)
2361 * @param val Get the values of fifo_en in reg CTRL3.(ptr)
2362 * @retval Interface status (MANDATORY: return 0 -> no Error).
2363 *
2364 */
lis2hh12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2hh12_fifo_md_t * val)2365 int32_t lis2hh12_fifo_mode_get(const stmdev_ctx_t *ctx,
2366 lis2hh12_fifo_md_t *val)
2367 {
2368 lis2hh12_fifo_ctrl_t fifo_ctrl;
2369 lis2hh12_ctrl3_t ctrl3;
2370 int32_t ret;
2371
2372 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL3, (uint8_t *)&ctrl3, 1);
2373
2374 if (ret == 0)
2375 {
2376 ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_CTRL,
2377 (uint8_t *)&fifo_ctrl, 1);
2378 }
2379
2380 switch ((ctrl3.fifo_en << 4) | fifo_ctrl.fmode)
2381 {
2382 case LIS2HH12_FIFO_OFF:
2383 *val = LIS2HH12_FIFO_OFF;
2384 break;
2385
2386 case LIS2HH12_BYPASS_MODE:
2387 *val = LIS2HH12_BYPASS_MODE;
2388 break;
2389
2390 case LIS2HH12_FIFO_MODE:
2391 *val = LIS2HH12_FIFO_MODE;
2392 break;
2393
2394 case LIS2HH12_STREAM_MODE:
2395 *val = LIS2HH12_STREAM_MODE;
2396 break;
2397
2398 case LIS2HH12_STREAM_TO_FIFO_MODE:
2399 *val = LIS2HH12_STREAM_TO_FIFO_MODE;
2400 break;
2401
2402 case LIS2HH12_BYPASS_TO_STREAM_MODE:
2403 *val = LIS2HH12_BYPASS_TO_STREAM_MODE;
2404 break;
2405
2406 case LIS2HH12_BYPASS_TO_FIFO_MODE:
2407 *val = LIS2HH12_BYPASS_TO_FIFO_MODE;
2408 break;
2409
2410 default:
2411 *val = LIS2HH12_FIFO_OFF;
2412 break;
2413 }
2414
2415 return ret;
2416 }
2417
2418 /**
2419 * @brief FIFOstatus.[get]
2420 *
2421 * @param ctx Read / write interface definitions.(ptr)
2422 * @param val FIFOfullflag.(ptr)
2423 * @retval Interface status (MANDATORY: return 0 -> no Error).
2424 *
2425 */
lis2hh12_fifo_status_get(const stmdev_ctx_t * ctx,lis2hh12_fifo_stat_t * val)2426 int32_t lis2hh12_fifo_status_get(const stmdev_ctx_t *ctx,
2427 lis2hh12_fifo_stat_t *val)
2428 {
2429 lis2hh12_fifo_src_t fifo_src;
2430 int32_t ret;
2431
2432 ret = lis2hh12_read_reg(ctx, LIS2HH12_FIFO_SRC, (uint8_t *)&fifo_src, 1);
2433 val->fss = fifo_src.fss;
2434 val->empty = fifo_src.empty;
2435 val->ovr = fifo_src.ovr;
2436 val->fth = fifo_src.fth;
2437
2438 return ret;
2439 }
2440
2441 /**
2442 * @}
2443 *
2444 */
2445
2446 /**
2447 * @defgroup LIS2HH12_Self_test
2448 * @brief This section groups all the functions that manage
2449 * self test configuration
2450 * @{
2451 *
2452 */
2453
2454 /**
2455 * @brief Enable/disable self-test mode for accelerometer.[set]
2456 *
2457 * @param ctx Read / write interface definitions.(ptr)
2458 * @param val Change the values of "st" in reg LIS2HH12.
2459 * @retval Interface status (MANDATORY: return 0 -> no Error).
2460 *
2461 */
lis2hh12_xl_self_test_set(const stmdev_ctx_t * ctx,lis2hh12_xl_st_t val)2462 int32_t lis2hh12_xl_self_test_set(const stmdev_ctx_t *ctx,
2463 lis2hh12_xl_st_t val)
2464 {
2465 lis2hh12_ctrl5_t ctrl5;
2466 int32_t ret;
2467
2468 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
2469
2470 if (ret == 0)
2471 {
2472 ctrl5.st = (uint8_t)val;
2473 ret = lis2hh12_write_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
2474 }
2475
2476 return ret;
2477 }
2478
2479 /**
2480 * @brief Enable/disable self-test mode for accelerometer.[get]
2481 *
2482 * @param ctx Read / write interface definitions.(ptr)
2483 * @param val Get the values of st in reg CTRL5.(ptr)
2484 * @retval Interface status (MANDATORY: return 0 -> no Error).
2485 *
2486 */
lis2hh12_xl_self_test_get(const stmdev_ctx_t * ctx,lis2hh12_xl_st_t * val)2487 int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx,
2488 lis2hh12_xl_st_t *val)
2489 {
2490 lis2hh12_ctrl5_t ctrl5;
2491 int32_t ret;
2492
2493 ret = lis2hh12_read_reg(ctx, LIS2HH12_CTRL5, (uint8_t *)&ctrl5, 1);
2494
2495 switch (ctrl5.st)
2496 {
2497 case LIS2HH12_ST_DISABLE:
2498 *val = LIS2HH12_ST_DISABLE;
2499 break;
2500
2501 case LIS2HH12_ST_POSITIVE:
2502 *val = LIS2HH12_ST_POSITIVE;
2503 break;
2504
2505 case LIS2HH12_ST_NEGATIVE:
2506 *val = LIS2HH12_ST_NEGATIVE;
2507 break;
2508
2509 default:
2510 *val = LIS2HH12_ST_DISABLE;
2511 break;
2512 }
2513
2514 return ret;
2515 }
2516
2517 /**
2518 * @}
2519 *
2520 */
2521
2522 /**
2523 * @}
2524 *
2525 */
2526
2527 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2528
