1 /** 2 ****************************************************************************** 3 * @file lis2dw12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2dw12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DW12_REGS_H 23 #define LIS2DW12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DW12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DW12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define LIS2DW12_I2C_ADD_L 0x31U 173 #define LIS2DW12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DW12_ID 0x44U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DW12_OUT_T_L 0x0DU 184 #define LIS2DW12_OUT_T_H 0x0EU 185 #define LIS2DW12_WHO_AM_I 0x0FU 186 #define LIS2DW12_CTRL1 0x20U 187 typedef struct 188 { 189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 190 uint8_t lp_mode : 2; 191 uint8_t mode : 2; 192 uint8_t odr : 4; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t odr : 4; 195 uint8_t mode : 2; 196 uint8_t lp_mode : 2; 197 #endif /* DRV_BYTE_ORDER */ 198 199 } lis2dw12_ctrl1_t; 200 201 #define LIS2DW12_CTRL2 0x21U 202 typedef struct 203 { 204 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 205 uint8_t sim : 1; 206 uint8_t i2c_disable : 1; 207 uint8_t if_add_inc : 1; 208 uint8_t bdu : 1; 209 uint8_t cs_pu_disc : 1; 210 uint8_t not_used_01 : 1; 211 uint8_t soft_reset : 1; 212 uint8_t boot : 1; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t boot : 1; 215 uint8_t soft_reset : 1; 216 uint8_t not_used_01 : 1; 217 uint8_t cs_pu_disc : 1; 218 uint8_t bdu : 1; 219 uint8_t if_add_inc : 1; 220 uint8_t i2c_disable : 1; 221 uint8_t sim : 1; 222 #endif /* DRV_BYTE_ORDER */ 223 224 } lis2dw12_ctrl2_t; 225 226 #define LIS2DW12_CTRL3 0x22U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ 231 uint8_t not_used_01 : 1; 232 uint8_t h_lactive : 1; 233 uint8_t lir : 1; 234 uint8_t pp_od : 1; 235 uint8_t st : 2; 236 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 237 uint8_t st : 2; 238 uint8_t pp_od : 1; 239 uint8_t lir : 1; 240 uint8_t h_lactive : 1; 241 uint8_t not_used_01 : 1; 242 uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ 243 #endif /* DRV_BYTE_ORDER */ 244 245 } lis2dw12_ctrl3_t; 246 247 #define LIS2DW12_CTRL4_INT1_PAD_CTRL 0x23U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t int1_drdy : 1; 252 uint8_t int1_fth : 1; 253 uint8_t int1_diff5 : 1; 254 uint8_t int1_tap : 1; 255 uint8_t int1_ff : 1; 256 uint8_t int1_wu : 1; 257 uint8_t int1_single_tap : 1; 258 uint8_t int1_6d : 1; 259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 260 uint8_t int1_6d : 1; 261 uint8_t int1_single_tap : 1; 262 uint8_t int1_wu : 1; 263 uint8_t int1_ff : 1; 264 uint8_t int1_tap : 1; 265 uint8_t int1_diff5 : 1; 266 uint8_t int1_fth : 1; 267 uint8_t int1_drdy : 1; 268 #endif /* DRV_BYTE_ORDER */ 269 } lis2dw12_ctrl4_int1_pad_ctrl_t; 270 271 #define LIS2DW12_CTRL5_INT2_PAD_CTRL 0x24U 272 typedef struct 273 { 274 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 275 uint8_t int2_drdy : 1; 276 uint8_t int2_fth : 1; 277 uint8_t int2_diff5 : 1; 278 uint8_t int2_ovr : 1; 279 uint8_t int2_drdy_t : 1; 280 uint8_t int2_boot : 1; 281 uint8_t int2_sleep_chg : 1; 282 uint8_t int2_sleep_state : 1; 283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 284 uint8_t int2_sleep_state : 1; 285 uint8_t int2_sleep_chg : 1; 286 uint8_t int2_boot : 1; 287 uint8_t int2_drdy_t : 1; 288 uint8_t int2_ovr : 1; 289 uint8_t int2_diff5 : 1; 290 uint8_t int2_fth : 1; 291 uint8_t int2_drdy : 1; 292 #endif /* DRV_BYTE_ORDER */ 293 } lis2dw12_ctrl5_int2_pad_ctrl_t; 294 295 #define LIS2DW12_CTRL6 0x25U 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t not_used_01 : 2; 300 uint8_t low_noise : 1; 301 uint8_t fds : 1; 302 uint8_t fs : 2; 303 uint8_t bw_filt : 2; 304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 305 uint8_t bw_filt : 2; 306 uint8_t fs : 2; 307 uint8_t fds : 1; 308 uint8_t low_noise : 1; 309 uint8_t not_used_01 : 2; 310 #endif /* DRV_BYTE_ORDER */ 311 } lis2dw12_ctrl6_t; 312 313 #define LIS2DW12_OUT_T 0x26U 314 #define LIS2DW12_STATUS 0x27U 315 typedef struct 316 { 317 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 318 uint8_t drdy : 1; 319 uint8_t ff_ia : 1; 320 uint8_t _6d_ia : 1; 321 uint8_t single_tap : 1; 322 uint8_t double_tap : 1; 323 uint8_t sleep_state : 1; 324 uint8_t wu_ia : 1; 325 uint8_t fifo_ths : 1; 326 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 327 uint8_t fifo_ths : 1; 328 uint8_t wu_ia : 1; 329 uint8_t sleep_state : 1; 330 uint8_t double_tap : 1; 331 uint8_t single_tap : 1; 332 uint8_t _6d_ia : 1; 333 uint8_t ff_ia : 1; 334 uint8_t drdy : 1; 335 #endif /* DRV_BYTE_ORDER */ 336 } lis2dw12_status_t; 337 338 #define LIS2DW12_OUT_X_L 0x28U 339 #define LIS2DW12_OUT_X_H 0x29U 340 #define LIS2DW12_OUT_Y_L 0x2AU 341 #define LIS2DW12_OUT_Y_H 0x2BU 342 #define LIS2DW12_OUT_Z_L 0x2CU 343 #define LIS2DW12_OUT_Z_H 0x2DU 344 #define LIS2DW12_FIFO_CTRL 0x2EU 345 typedef struct 346 { 347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 348 uint8_t fth : 5; 349 uint8_t fmode : 3; 350 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 351 uint8_t fmode : 3; 352 uint8_t fth : 5; 353 #endif /* DRV_BYTE_ORDER */ 354 } lis2dw12_fifo_ctrl_t; 355 356 #define LIS2DW12_FIFO_SAMPLES 0x2FU 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t diff : 6; 361 uint8_t fifo_ovr : 1; 362 uint8_t fifo_fth : 1; 363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 364 uint8_t fifo_fth : 1; 365 uint8_t fifo_ovr : 1; 366 uint8_t diff : 6; 367 #endif /* DRV_BYTE_ORDER */ 368 } lis2dw12_fifo_samples_t; 369 370 #define LIS2DW12_TAP_THS_X 0x30U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t tap_thsx : 5; 375 uint8_t _6d_ths : 2; 376 uint8_t _4d_en : 1; 377 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 378 uint8_t _4d_en : 1; 379 uint8_t _6d_ths : 2; 380 uint8_t tap_thsx : 5; 381 #endif /* DRV_BYTE_ORDER */ 382 } lis2dw12_tap_ths_x_t; 383 384 #define LIS2DW12_TAP_THS_Y 0x31U 385 typedef struct 386 { 387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 388 uint8_t tap_thsy : 5; 389 uint8_t tap_prior : 3; 390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 uint8_t tap_prior : 3; 392 uint8_t tap_thsy : 5; 393 #endif /* DRV_BYTE_ORDER */ 394 } lis2dw12_tap_ths_y_t; 395 396 #define LIS2DW12_TAP_THS_Z 0x32U 397 typedef struct 398 { 399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 400 uint8_t tap_thsz : 5; 401 uint8_t tap_z_en : 1; 402 uint8_t tap_y_en : 1; 403 uint8_t tap_x_en : 1; 404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 405 uint8_t tap_x_en : 1; 406 uint8_t tap_y_en : 1; 407 uint8_t tap_z_en : 1; 408 uint8_t tap_thsz : 5; 409 #endif /* DRV_BYTE_ORDER */ 410 } lis2dw12_tap_ths_z_t; 411 412 #define LIS2DW12_INT_DUR 0x33U 413 typedef struct 414 { 415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 416 uint8_t shock : 2; 417 uint8_t quiet : 2; 418 uint8_t latency : 4; 419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 420 uint8_t latency : 4; 421 uint8_t quiet : 2; 422 uint8_t shock : 2; 423 #endif /* DRV_BYTE_ORDER */ 424 } lis2dw12_int_dur_t; 425 426 #define LIS2DW12_WAKE_UP_THS 0x34U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t wk_ths : 6; 431 uint8_t sleep_on : 1; 432 uint8_t single_double_tap : 1; 433 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 434 uint8_t single_double_tap : 1; 435 uint8_t sleep_on : 1; 436 uint8_t wk_ths : 6; 437 #endif /* DRV_BYTE_ORDER */ 438 } lis2dw12_wake_up_ths_t; 439 440 #define LIS2DW12_WAKE_UP_DUR 0x35U 441 typedef struct 442 { 443 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 444 uint8_t sleep_dur : 4; 445 uint8_t stationary : 1; 446 uint8_t wake_dur : 2; 447 uint8_t ff_dur : 1; 448 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 449 uint8_t ff_dur : 1; 450 uint8_t wake_dur : 2; 451 uint8_t stationary : 1; 452 uint8_t sleep_dur : 4; 453 #endif /* DRV_BYTE_ORDER */ 454 } lis2dw12_wake_up_dur_t; 455 456 #define LIS2DW12_FREE_FALL 0x36U 457 typedef struct 458 { 459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 460 uint8_t ff_ths : 3; 461 uint8_t ff_dur : 5; 462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 463 uint8_t ff_dur : 5; 464 uint8_t ff_ths : 3; 465 #endif /* DRV_BYTE_ORDER */ 466 } lis2dw12_free_fall_t; 467 468 #define LIS2DW12_STATUS_DUP 0x37U 469 typedef struct 470 { 471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 472 uint8_t drdy : 1; 473 uint8_t ff_ia : 1; 474 uint8_t _6d_ia : 1; 475 uint8_t single_tap : 1; 476 uint8_t double_tap : 1; 477 uint8_t sleep_state_ia : 1; 478 uint8_t drdy_t : 1; 479 uint8_t ovr : 1; 480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 481 uint8_t ovr : 1; 482 uint8_t drdy_t : 1; 483 uint8_t sleep_state_ia : 1; 484 uint8_t double_tap : 1; 485 uint8_t single_tap : 1; 486 uint8_t _6d_ia : 1; 487 uint8_t ff_ia : 1; 488 uint8_t drdy : 1; 489 #endif /* DRV_BYTE_ORDER */ 490 } lis2dw12_status_dup_t; 491 492 #define LIS2DW12_WAKE_UP_SRC 0x38U 493 typedef struct 494 { 495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 496 uint8_t z_wu : 1; 497 uint8_t y_wu : 1; 498 uint8_t x_wu : 1; 499 uint8_t wu_ia : 1; 500 uint8_t sleep_state_ia : 1; 501 uint8_t ff_ia : 1; 502 uint8_t not_used_01 : 2; 503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 504 uint8_t not_used_01 : 2; 505 uint8_t ff_ia : 1; 506 uint8_t sleep_state_ia : 1; 507 uint8_t wu_ia : 1; 508 uint8_t x_wu : 1; 509 uint8_t y_wu : 1; 510 uint8_t z_wu : 1; 511 #endif /* DRV_BYTE_ORDER */ 512 } lis2dw12_wake_up_src_t; 513 514 #define LIS2DW12_TAP_SRC 0x39U 515 typedef struct 516 { 517 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 518 uint8_t z_tap : 1; 519 uint8_t y_tap : 1; 520 uint8_t x_tap : 1; 521 uint8_t tap_sign : 1; 522 uint8_t double_tap : 1; 523 uint8_t single_tap : 1; 524 uint8_t tap_ia : 1; 525 uint8_t not_used_01 : 1; 526 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 527 uint8_t not_used_01 : 1; 528 uint8_t tap_ia : 1; 529 uint8_t single_tap : 1; 530 uint8_t double_tap : 1; 531 uint8_t tap_sign : 1; 532 uint8_t x_tap : 1; 533 uint8_t y_tap : 1; 534 uint8_t z_tap : 1; 535 #endif /* DRV_BYTE_ORDER */ 536 } lis2dw12_tap_src_t; 537 538 #define LIS2DW12_SIXD_SRC 0x3AU 539 typedef struct 540 { 541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 542 uint8_t xl : 1; 543 uint8_t xh : 1; 544 uint8_t yl : 1; 545 uint8_t yh : 1; 546 uint8_t zl : 1; 547 uint8_t zh : 1; 548 uint8_t _6d_ia : 1; 549 uint8_t not_used_01 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used_01 : 1; 552 uint8_t _6d_ia : 1; 553 uint8_t zh : 1; 554 uint8_t zl : 1; 555 uint8_t yh : 1; 556 uint8_t xh : 1; 557 uint8_t yl : 1; 558 uint8_t xh : 1; 559 uint8_t xl : 1; 560 #endif /* DRV_BYTE_ORDER */ 561 } lis2dw12_sixd_src_t; 562 563 #define LIS2DW12_ALL_INT_SRC 0x3BU 564 typedef struct 565 { 566 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 567 uint8_t ff_ia : 1; 568 uint8_t wu_ia : 1; 569 uint8_t single_tap : 1; 570 uint8_t double_tap : 1; 571 uint8_t _6d_ia : 1; 572 uint8_t sleep_change_ia : 1; 573 uint8_t not_used_01 : 2; 574 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 575 uint8_t not_used_01 : 2; 576 uint8_t sleep_change_ia : 1; 577 uint8_t _6d_ia : 1; 578 uint8_t double_tap : 1; 579 uint8_t single_tap : 1; 580 uint8_t wu_ia : 1; 581 uint8_t ff_ia : 1; 582 #endif /* DRV_BYTE_ORDER */ 583 } lis2dw12_all_int_src_t; 584 585 #define LIS2DW12_X_OFS_USR 0x3CU 586 #define LIS2DW12_Y_OFS_USR 0x3DU 587 #define LIS2DW12_Z_OFS_USR 0x3EU 588 #define LIS2DW12_CTRL_REG7 0x3FU 589 typedef struct 590 { 591 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 592 uint8_t lpass_on6d : 1; 593 uint8_t hp_ref_mode : 1; 594 uint8_t usr_off_w : 1; 595 uint8_t usr_off_on_wu : 1; 596 uint8_t usr_off_on_out : 1; 597 uint8_t interrupts_enable : 1; 598 uint8_t int2_on_int1 : 1; 599 uint8_t drdy_pulsed : 1; 600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 601 uint8_t drdy_pulsed : 1; 602 uint8_t int2_on_int1 : 1; 603 uint8_t interrupts_enable : 1; 604 uint8_t usr_off_on_out : 1; 605 uint8_t usr_off_on_wu : 1; 606 uint8_t usr_off_w : 1; 607 uint8_t hp_ref_mode : 1; 608 uint8_t lpass_on6d : 1; 609 #endif /* DRV_BYTE_ORDER */ 610 } lis2dw12_ctrl_reg7_t; 611 612 /** 613 * @defgroup LIS2DW12_Register_Union 614 * @brief This union group all the registers having a bit-field 615 * description. 616 * This union is useful but it's not needed by the driver. 617 * 618 * REMOVING this union you are compliant with: 619 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 620 * 621 * @{ 622 * 623 */ 624 typedef union 625 { 626 lis2dw12_ctrl1_t ctrl1; 627 lis2dw12_ctrl2_t ctrl2; 628 lis2dw12_ctrl3_t ctrl3; 629 lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl; 630 lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; 631 lis2dw12_ctrl6_t ctrl6; 632 lis2dw12_status_t status; 633 lis2dw12_fifo_ctrl_t fifo_ctrl; 634 lis2dw12_fifo_samples_t fifo_samples; 635 lis2dw12_tap_ths_x_t tap_ths_x; 636 lis2dw12_tap_ths_y_t tap_ths_y; 637 lis2dw12_tap_ths_z_t tap_ths_z; 638 lis2dw12_int_dur_t int_dur; 639 lis2dw12_wake_up_ths_t wake_up_ths; 640 lis2dw12_wake_up_dur_t wake_up_dur; 641 lis2dw12_free_fall_t free_fall; 642 lis2dw12_status_dup_t status_dup; 643 lis2dw12_wake_up_src_t wake_up_src; 644 lis2dw12_tap_src_t tap_src; 645 lis2dw12_sixd_src_t sixd_src; 646 lis2dw12_all_int_src_t all_int_src; 647 lis2dw12_ctrl_reg7_t ctrl_reg7; 648 bitwise_t bitwise; 649 uint8_t byte; 650 } lis2dw12_reg_t; 651 652 /** 653 * @} 654 * 655 */ 656 657 #ifndef __weak 658 #define __weak __attribute__((weak)) 659 #endif /* __weak */ 660 661 /* 662 * These are the basic platform dependent I/O routines to read 663 * and write device registers connected on a standard bus. 664 * The driver keeps offering a default implementation based on function 665 * pointers to read/write routines for backward compatibility. 666 * The __weak directive allows the final application to overwrite 667 * them with a custom implementation. 668 */ 669 670 int32_t lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 671 uint8_t *data, 672 uint16_t len); 673 int32_t lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 674 uint8_t *data, 675 uint16_t len); 676 677 float_t lis2dw12_from_fs2_to_mg(int16_t lsb); 678 float_t lis2dw12_from_fs4_to_mg(int16_t lsb); 679 float_t lis2dw12_from_fs8_to_mg(int16_t lsb); 680 float_t lis2dw12_from_fs16_to_mg(int16_t lsb); 681 682 float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb); 683 float_t lis2dw12_from_fs4_lp1_to_mg(int16_t lsb); 684 float_t lis2dw12_from_fs8_lp1_to_mg(int16_t lsb); 685 float_t lis2dw12_from_fs16_lp1_to_mg(int16_t lsb); 686 687 float_t lis2dw12_from_lsb_to_celsius(int16_t lsb); 688 689 typedef enum 690 { 691 LIS2DW12_HIGH_PERFORMANCE = 0x04, 692 LIS2DW12_CONT_LOW_PWR_4 = 0x03, 693 LIS2DW12_CONT_LOW_PWR_3 = 0x02, 694 LIS2DW12_CONT_LOW_PWR_2 = 0x01, 695 LIS2DW12_CONT_LOW_PWR_12bit = 0x00, 696 LIS2DW12_SINGLE_LOW_PWR_4 = 0x0B, 697 LIS2DW12_SINGLE_LOW_PWR_3 = 0x0A, 698 LIS2DW12_SINGLE_LOW_PWR_2 = 0x09, 699 LIS2DW12_SINGLE_LOW_PWR_12bit = 0x08, 700 LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE = 0x14, 701 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4 = 0x13, 702 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3 = 0x12, 703 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2 = 0x11, 704 LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit = 0x10, 705 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4 = 0x1B, 706 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3 = 0x1A, 707 LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, 708 LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, 709 } lis2dw12_mode_t; 710 int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx, 711 lis2dw12_mode_t val); 712 int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx, 713 lis2dw12_mode_t *val); 714 715 typedef enum 716 { 717 LIS2DW12_XL_ODR_OFF = 0x00, 718 LIS2DW12_XL_ODR_1Hz6_LP_ONLY = 0x01, 719 LIS2DW12_XL_ODR_12Hz5 = 0x02, 720 LIS2DW12_XL_ODR_25Hz = 0x03, 721 LIS2DW12_XL_ODR_50Hz = 0x04, 722 LIS2DW12_XL_ODR_100Hz = 0x05, 723 LIS2DW12_XL_ODR_200Hz = 0x06, 724 LIS2DW12_XL_ODR_400Hz = 0x07, 725 LIS2DW12_XL_ODR_800Hz = 0x08, 726 LIS2DW12_XL_ODR_1k6Hz = 0x09, 727 LIS2DW12_XL_SET_SW_TRIG = 0x32, /* Use this only in SINGLE mode */ 728 LIS2DW12_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */ 729 } lis2dw12_odr_t; 730 int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val); 731 int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, 732 lis2dw12_odr_t *val); 733 734 int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx, 735 uint8_t val); 736 int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx, 737 uint8_t *val); 738 739 typedef enum 740 { 741 LIS2DW12_2g = 0, 742 LIS2DW12_4g = 1, 743 LIS2DW12_8g = 2, 744 LIS2DW12_16g = 3, 745 } lis2dw12_fs_t; 746 int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val); 747 int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, 748 lis2dw12_fs_t *val); 749 750 int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx, 751 lis2dw12_status_t *val); 752 753 int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 754 755 typedef struct 756 { 757 lis2dw12_status_dup_t status_dup; 758 lis2dw12_wake_up_src_t wake_up_src; 759 lis2dw12_tap_src_t tap_src; 760 lis2dw12_sixd_src_t sixd_src; 761 lis2dw12_all_int_src_t all_int_src; 762 } lis2dw12_all_sources_t; 763 int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx, 764 lis2dw12_all_sources_t *val); 765 766 int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 767 int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 768 769 int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 770 int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 771 772 int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 773 int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 774 775 typedef enum 776 { 777 LIS2DW12_LSb_977ug = 0, 778 LIS2DW12_LSb_15mg6 = 1, 779 } lis2dw12_usr_off_w_t; 780 int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx, 781 lis2dw12_usr_off_w_t val); 782 int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx, 783 lis2dw12_usr_off_w_t *val); 784 785 int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 786 787 int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, 788 int16_t *val); 789 790 int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 791 792 int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 793 int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 794 795 int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 796 int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 797 798 int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 799 int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 800 801 typedef enum 802 { 803 LIS2DW12_XL_ST_DISABLE = 0, 804 LIS2DW12_XL_ST_POSITIVE = 1, 805 LIS2DW12_XL_ST_NEGATIVE = 2, 806 } lis2dw12_st_t; 807 int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val); 808 int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val); 809 810 typedef enum 811 { 812 LIS2DW12_DRDY_LATCHED = 0, 813 LIS2DW12_DRDY_PULSED = 1, 814 } lis2dw12_drdy_pulsed_t; 815 int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, 816 lis2dw12_drdy_pulsed_t val); 817 int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, 818 lis2dw12_drdy_pulsed_t *val); 819 820 typedef enum 821 { 822 LIS2DW12_LPF_ON_OUT = 0x00, 823 LIS2DW12_USER_OFFSET_ON_OUT = 0x01, 824 LIS2DW12_HIGH_PASS_ON_OUT = 0x10, 825 } lis2dw12_fds_t; 826 int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx, 827 lis2dw12_fds_t val); 828 int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx, 829 lis2dw12_fds_t *val); 830 831 typedef enum 832 { 833 LIS2DW12_ODR_DIV_2 = 0, 834 LIS2DW12_ODR_DIV_4 = 1, 835 LIS2DW12_ODR_DIV_10 = 2, 836 LIS2DW12_ODR_DIV_20 = 3, 837 } lis2dw12_bw_filt_t; 838 int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, 839 lis2dw12_bw_filt_t val); 840 int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, 841 lis2dw12_bw_filt_t *val); 842 843 int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 844 int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 845 846 typedef enum 847 { 848 LIS2DW12_SPI_4_WIRE = 0, 849 LIS2DW12_SPI_3_WIRE = 1, 850 } lis2dw12_sim_t; 851 int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val); 852 int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val); 853 854 typedef enum 855 { 856 LIS2DW12_I2C_ENABLE = 0, 857 LIS2DW12_I2C_DISABLE = 1, 858 } lis2dw12_i2c_disable_t; 859 int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, 860 lis2dw12_i2c_disable_t val); 861 int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, 862 lis2dw12_i2c_disable_t *val); 863 864 typedef enum 865 { 866 LIS2DW12_PULL_UP_CONNECT = 0, 867 LIS2DW12_PULL_UP_DISCONNECT = 1, 868 } lis2dw12_cs_pu_disc_t; 869 int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx, 870 lis2dw12_cs_pu_disc_t val); 871 int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx, 872 lis2dw12_cs_pu_disc_t *val); 873 874 typedef enum 875 { 876 LIS2DW12_ACTIVE_HIGH = 0, 877 LIS2DW12_ACTIVE_LOW = 1, 878 } lis2dw12_h_lactive_t; 879 int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, 880 lis2dw12_h_lactive_t val); 881 int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, 882 lis2dw12_h_lactive_t *val); 883 884 typedef enum 885 { 886 LIS2DW12_INT_PULSED = 0, 887 LIS2DW12_INT_LATCHED = 1, 888 } lis2dw12_lir_t; 889 int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx, 890 lis2dw12_lir_t val); 891 int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx, 892 lis2dw12_lir_t *val); 893 894 typedef enum 895 { 896 LIS2DW12_PUSH_PULL = 0, 897 LIS2DW12_OPEN_DRAIN = 1, 898 } lis2dw12_pp_od_t; 899 int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx, 900 lis2dw12_pp_od_t val); 901 int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx, 902 lis2dw12_pp_od_t *val); 903 904 int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, 905 lis2dw12_ctrl4_int1_pad_ctrl_t *val); 906 int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, 907 lis2dw12_ctrl4_int1_pad_ctrl_t *val); 908 909 int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, 910 lis2dw12_ctrl5_int2_pad_ctrl_t *val); 911 int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, 912 lis2dw12_ctrl5_int2_pad_ctrl_t *val); 913 914 int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 915 int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 916 917 int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 918 int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 919 920 int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 921 int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 922 923 typedef enum 924 { 925 LIS2DW12_HP_FEED = 0, 926 LIS2DW12_USER_OFFSET_FEED = 1, 927 } lis2dw12_usr_off_on_wu_t; 928 int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, 929 lis2dw12_usr_off_on_wu_t val); 930 int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, 931 lis2dw12_usr_off_on_wu_t *val); 932 933 typedef enum 934 { 935 LIS2DW12_NO_DETECTION = 0, 936 LIS2DW12_DETECT_ACT_INACT = 1, 937 LIS2DW12_DETECT_STAT_MOTION = 3, 938 } lis2dw12_sleep_on_t; 939 int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx, 940 lis2dw12_sleep_on_t val); 941 int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx, 942 lis2dw12_sleep_on_t *val); 943 944 int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 945 int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 946 947 int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); 948 int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 949 950 int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); 951 int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 952 953 typedef enum 954 { 955 LIS2DW12_XYZ = 0, 956 LIS2DW12_YXZ = 1, 957 LIS2DW12_XZY = 2, 958 LIS2DW12_ZYX = 3, 959 LIS2DW12_YZX = 5, 960 LIS2DW12_ZXY = 6, 961 } lis2dw12_tap_prior_t; 962 int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, 963 lis2dw12_tap_prior_t val); 964 int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, 965 lis2dw12_tap_prior_t *val); 966 967 int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); 968 int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 969 970 int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 971 uint8_t val); 972 int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 973 uint8_t *val); 974 975 int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 976 uint8_t val); 977 int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 978 uint8_t *val); 979 980 int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 981 uint8_t val); 982 int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 983 uint8_t *val); 984 985 int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 986 int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 987 988 int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 989 int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 990 991 int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 992 int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 993 994 typedef enum 995 { 996 LIS2DW12_ONLY_SINGLE = 0, 997 LIS2DW12_BOTH_SINGLE_DOUBLE = 1, 998 } lis2dw12_single_double_tap_t; 999 int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx, 1000 lis2dw12_single_double_tap_t val); 1001 int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx, 1002 lis2dw12_single_double_tap_t *val); 1003 1004 int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx, 1005 lis2dw12_tap_src_t *val); 1006 1007 int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1008 int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1009 1010 int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1011 int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1012 1013 int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx, 1014 lis2dw12_sixd_src_t *val); 1015 1016 typedef enum 1017 { 1018 LIS2DW12_ODR_DIV_2_FEED = 0, 1019 LIS2DW12_LPF2_FEED = 1, 1020 } lis2dw12_lpass_on6d_t; 1021 int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, 1022 lis2dw12_lpass_on6d_t val); 1023 int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, 1024 lis2dw12_lpass_on6d_t *val); 1025 1026 int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1027 int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1028 1029 typedef enum 1030 { 1031 LIS2DW12_FF_TSH_5LSb_FS2g = 0, 1032 LIS2DW12_FF_TSH_7LSb_FS2g = 1, 1033 LIS2DW12_FF_TSH_8LSb_FS2g = 2, 1034 LIS2DW12_FF_TSH_10LSb_FS2g = 3, 1035 LIS2DW12_FF_TSH_11LSb_FS2g = 4, 1036 LIS2DW12_FF_TSH_13LSb_FS2g = 5, 1037 LIS2DW12_FF_TSH_15LSb_FS2g = 6, 1038 LIS2DW12_FF_TSH_16LSb_FS2g = 7, 1039 } lis2dw12_ff_ths_t; 1040 int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, 1041 lis2dw12_ff_ths_t val); 1042 int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, 1043 lis2dw12_ff_ths_t *val); 1044 1045 int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 1046 int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 1047 1048 typedef enum 1049 { 1050 LIS2DW12_BYPASS_MODE = 0, 1051 LIS2DW12_FIFO_MODE = 1, 1052 LIS2DW12_STREAM_TO_FIFO_MODE = 3, 1053 LIS2DW12_BYPASS_TO_STREAM_MODE = 4, 1054 LIS2DW12_STREAM_MODE = 6, 1055 } lis2dw12_fmode_t; 1056 int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, 1057 lis2dw12_fmode_t val); 1058 int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, 1059 lis2dw12_fmode_t *val); 1060 1061 int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 1062 1063 int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1064 1065 int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1066 1067 /** 1068 * @} 1069 * 1070 */ 1071 1072 #ifdef __cplusplus 1073 } 1074 #endif 1075 1076 #endif /*LIS2DW12_REGS_H */ 1077 1078 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1079
