1 /**
2 ******************************************************************************
3 * @file lis2dw12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DW12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2dw12_reg.h"
21
22 /**
23 * @defgroup LIS2DW12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2dw12 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DW12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2dw12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lis2dw12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LIS2DW12_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lis2dw12_from_fs2_to_mg(int16_t lsb)103 float_t lis2dw12_from_fs2_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb) * 0.061f;
106 }
107
lis2dw12_from_fs4_to_mg(int16_t lsb)108 float_t lis2dw12_from_fs4_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb) * 0.122f;
111 }
112
lis2dw12_from_fs8_to_mg(int16_t lsb)113 float_t lis2dw12_from_fs8_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb) * 0.244f;
116 }
117
lis2dw12_from_fs16_to_mg(int16_t lsb)118 float_t lis2dw12_from_fs16_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb) * 0.488f;
121 }
122
lis2dw12_from_fs2_lp1_to_mg(int16_t lsb)123 float_t lis2dw12_from_fs2_lp1_to_mg(int16_t lsb)
124 {
125 return ((float_t)lsb) * 0.061f;
126 }
127
lis2dw12_from_fs4_lp1_to_mg(int16_t lsb)128 float_t lis2dw12_from_fs4_lp1_to_mg(int16_t lsb)
129 {
130 return ((float_t)lsb) * 0.122f;
131 }
132
lis2dw12_from_fs8_lp1_to_mg(int16_t lsb)133 float_t lis2dw12_from_fs8_lp1_to_mg(int16_t lsb)
134 {
135 return ((float_t)lsb) * 0.244f;
136 }
137
lis2dw12_from_fs16_lp1_to_mg(int16_t lsb)138 float_t lis2dw12_from_fs16_lp1_to_mg(int16_t lsb)
139 {
140 return ((float_t)lsb) * 0.488f;
141 }
142
lis2dw12_from_lsb_to_celsius(int16_t lsb)143 float_t lis2dw12_from_lsb_to_celsius(int16_t lsb)
144 {
145 return (((float_t)lsb / 256.0f) + 25.0f);
146 }
147
148 /**
149 * @}
150 *
151 */
152
153 /**
154 * @defgroup LIS2DW12_Data_Generation
155 * @brief This section groups all the functions concerning
156 * data generation
157 * @{
158 *
159 */
160
161 /**
162 * @brief Select accelerometer operating modes.[set]
163 *
164 * @param ctx read / write interface definitions
165 * @param val change the values of mode / lp_mode in reg CTRL1
166 * and low_noise in reg CTRL6
167 * @retval interface status (MANDATORY: return 0 -> no Error)
168 *
169 */
lis2dw12_power_mode_set(const stmdev_ctx_t * ctx,lis2dw12_mode_t val)170 int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx,
171 lis2dw12_mode_t val)
172 {
173 lis2dw12_ctrl1_t ctrl1;
174 lis2dw12_ctrl6_t ctrl6;
175 int32_t ret;
176
177 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
178
179 if (ret == 0)
180 {
181 ctrl1.mode = ((uint8_t) val & 0x0CU) >> 2;
182 ctrl1.lp_mode = (uint8_t) val & 0x03U ;
183 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
184 }
185
186 if (ret == 0)
187 {
188 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
189 }
190
191 if (ret == 0)
192 {
193 ctrl6.low_noise = ((uint8_t) val & 0x10U) >> 4;
194 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
195 }
196
197 return ret;
198 }
199
200 /**
201 * @brief Select accelerometer operating modes.[get]
202 *
203 * @param ctx read / write interface definitions
204 * @param val change the values of mode / lp_mode in reg CTRL1
205 * and low_noise in reg CTRL6
206 * @retval interface status (MANDATORY: return 0 -> no Error)
207 *
208 */
lis2dw12_power_mode_get(const stmdev_ctx_t * ctx,lis2dw12_mode_t * val)209 int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx,
210 lis2dw12_mode_t *val)
211 {
212 lis2dw12_ctrl1_t ctrl1;
213 lis2dw12_ctrl6_t ctrl6;
214 int32_t ret;
215
216 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
217
218 if (ret == 0)
219 {
220 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
221
222 switch (((ctrl6.low_noise << 4) + (ctrl1.mode << 2) +
223 ctrl1.lp_mode))
224 {
225 case LIS2DW12_HIGH_PERFORMANCE:
226 *val = LIS2DW12_HIGH_PERFORMANCE;
227 break;
228
229 case LIS2DW12_CONT_LOW_PWR_4:
230 *val = LIS2DW12_CONT_LOW_PWR_4;
231 break;
232
233 case LIS2DW12_CONT_LOW_PWR_3:
234 *val = LIS2DW12_CONT_LOW_PWR_3;
235 break;
236
237 case LIS2DW12_CONT_LOW_PWR_2:
238 *val = LIS2DW12_CONT_LOW_PWR_2;
239 break;
240
241 case LIS2DW12_CONT_LOW_PWR_12bit:
242 *val = LIS2DW12_CONT_LOW_PWR_12bit;
243 break;
244
245 case LIS2DW12_SINGLE_LOW_PWR_4:
246 *val = LIS2DW12_SINGLE_LOW_PWR_4;
247 break;
248
249 case LIS2DW12_SINGLE_LOW_PWR_3:
250 *val = LIS2DW12_SINGLE_LOW_PWR_3;
251 break;
252
253 case LIS2DW12_SINGLE_LOW_PWR_2:
254 *val = LIS2DW12_SINGLE_LOW_PWR_2;
255 break;
256
257 case LIS2DW12_SINGLE_LOW_PWR_12bit:
258 *val = LIS2DW12_SINGLE_LOW_PWR_12bit;
259 break;
260
261 case LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE:
262 *val = LIS2DW12_HIGH_PERFORMANCE_LOW_NOISE;
263 break;
264
265 case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4:
266 *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_4;
267 break;
268
269 case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3:
270 *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_3;
271 break;
272
273 case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2:
274 *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_2;
275 break;
276
277 case LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit:
278 *val = LIS2DW12_CONT_LOW_PWR_LOW_NOISE_12bit;
279 break;
280
281 case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4:
282 *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_4;
283 break;
284
285 case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3:
286 *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_3;
287 break;
288
289 case LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2:
290 *val = LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2;
291 break;
292
293 case LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit:
294 *val = LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit;
295 break;
296
297 default:
298 *val = LIS2DW12_HIGH_PERFORMANCE;
299 break;
300 }
301 }
302
303 return ret;
304 }
305
306 /**
307 * @brief Accelerometer data rate selection.[set]
308 *
309 * @param ctx read / write interface definitions
310 * @param val change the values of odr in reg CTRL1
311 * @retval interface status (MANDATORY: return 0 -> no Error)
312 *
313 */
lis2dw12_data_rate_set(const stmdev_ctx_t * ctx,lis2dw12_odr_t val)314 int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val)
315 {
316 lis2dw12_ctrl1_t ctrl1;
317 lis2dw12_ctrl3_t ctrl3;
318 int32_t ret;
319
320 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
321
322 if (ret == 0)
323 {
324 ctrl1.odr = (uint8_t) val;
325 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
326 }
327
328 if (ret == 0)
329 {
330 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
331 }
332
333 if (ret == 0)
334 {
335 ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
336 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
337 }
338
339 return ret;
340 }
341
342 /**
343 * @brief Accelerometer data rate selection.[get]
344 *
345 * @param ctx read / write interface definitions
346 * @param val Get the values of odr in reg CTRL1
347 * @retval interface status (MANDATORY: return 0 -> no Error)
348 *
349 */
lis2dw12_data_rate_get(const stmdev_ctx_t * ctx,lis2dw12_odr_t * val)350 int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dw12_odr_t *val)
351 {
352 lis2dw12_ctrl1_t ctrl1;
353 lis2dw12_ctrl3_t ctrl3;
354 int32_t ret;
355
356 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
357
358 if (ret == 0)
359 {
360 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
361
362 switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
363 {
364 case LIS2DW12_XL_ODR_OFF:
365 *val = LIS2DW12_XL_ODR_OFF;
366 break;
367
368 case LIS2DW12_XL_ODR_1Hz6_LP_ONLY:
369 *val = LIS2DW12_XL_ODR_1Hz6_LP_ONLY;
370 break;
371
372 case LIS2DW12_XL_ODR_12Hz5:
373 *val = LIS2DW12_XL_ODR_12Hz5;
374 break;
375
376 case LIS2DW12_XL_ODR_25Hz:
377 *val = LIS2DW12_XL_ODR_25Hz;
378 break;
379
380 case LIS2DW12_XL_ODR_50Hz:
381 *val = LIS2DW12_XL_ODR_50Hz;
382 break;
383
384 case LIS2DW12_XL_ODR_100Hz:
385 *val = LIS2DW12_XL_ODR_100Hz;
386 break;
387
388 case LIS2DW12_XL_ODR_200Hz:
389 *val = LIS2DW12_XL_ODR_200Hz;
390 break;
391
392 case LIS2DW12_XL_ODR_400Hz:
393 *val = LIS2DW12_XL_ODR_400Hz;
394 break;
395
396 case LIS2DW12_XL_ODR_800Hz:
397 *val = LIS2DW12_XL_ODR_800Hz;
398 break;
399
400 case LIS2DW12_XL_ODR_1k6Hz:
401 *val = LIS2DW12_XL_ODR_1k6Hz;
402 break;
403
404 case LIS2DW12_XL_SET_SW_TRIG:
405 *val = LIS2DW12_XL_SET_SW_TRIG;
406 break;
407
408 case LIS2DW12_XL_SET_PIN_TRIG:
409 *val = LIS2DW12_XL_SET_PIN_TRIG;
410 break;
411
412 default:
413 *val = LIS2DW12_XL_ODR_OFF;
414 break;
415 }
416 }
417
418 return ret;
419 }
420
421 /**
422 * @brief Block data update.[set]
423 *
424 * @param ctx read / write interface definitions
425 * @param val change the values of bdu in reg CTRL2
426 * @retval interface status (MANDATORY: return 0 -> no Error)
427 *
428 */
lis2dw12_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)429 int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
430 {
431 lis2dw12_ctrl2_t reg;
432 int32_t ret;
433
434 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
435
436 if (ret == 0)
437 {
438 reg.bdu = val;
439 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
440 }
441
442 return ret;
443 }
444
445 /**
446 * @brief Block data update.[get]
447 *
448 * @param ctx read / write interface definitions
449 * @param val change the values of bdu in reg CTRL2
450 * @retval interface status (MANDATORY: return 0 -> no Error)
451 *
452 */
lis2dw12_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)453 int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx,
454 uint8_t *val)
455 {
456 lis2dw12_ctrl2_t reg;
457 int32_t ret;
458
459 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
460 *val = reg.bdu;
461
462 return ret;
463 }
464
465 /**
466 * @brief Accelerometer full-scale selection.[set]
467 *
468 * @param ctx read / write interface definitions
469 * @param val change the values of fs in reg CTRL6
470 * @retval interface status (MANDATORY: return 0 -> no Error)
471 *
472 */
lis2dw12_full_scale_set(const stmdev_ctx_t * ctx,lis2dw12_fs_t val)473 int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val)
474 {
475 lis2dw12_ctrl6_t reg;
476 int32_t ret;
477
478 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
479
480 if (ret == 0)
481 {
482 reg.fs = (uint8_t) val;
483 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
484 }
485
486 return ret;
487 }
488
489 /**
490 * @brief Accelerometer full-scale selection.[get]
491 *
492 * @param ctx read / write interface definitions
493 * @param val Get the values of fs in reg CTRL6
494 * @retval interface status (MANDATORY: return 0 -> no Error)
495 *
496 */
lis2dw12_full_scale_get(const stmdev_ctx_t * ctx,lis2dw12_fs_t * val)497 int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dw12_fs_t *val)
498 {
499 lis2dw12_ctrl6_t reg;
500 int32_t ret;
501
502 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
503
504 switch (reg.fs)
505 {
506 case LIS2DW12_2g:
507 *val = LIS2DW12_2g;
508 break;
509
510 case LIS2DW12_4g:
511 *val = LIS2DW12_4g;
512 break;
513
514 case LIS2DW12_8g:
515 *val = LIS2DW12_8g;
516 break;
517
518 case LIS2DW12_16g:
519 *val = LIS2DW12_16g;
520 break;
521
522 default:
523 *val = LIS2DW12_2g;
524 break;
525 }
526
527 return ret;
528 }
529
530 /**
531 * @brief The STATUS_REG register of the device.[get]
532 *
533 * @param ctx read / write interface definitions
534 * @param val union of registers from STATUS to
535 * @retval interface status (MANDATORY: return 0 -> no Error)
536 *
537 */
lis2dw12_status_reg_get(const stmdev_ctx_t * ctx,lis2dw12_status_t * val)538 int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx,
539 lis2dw12_status_t *val)
540 {
541 int32_t ret;
542
543 ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) val, 1);
544
545 return ret;
546 }
547
548 /**
549 * @brief Accelerometer new data available.[get]
550 *
551 * @param ctx read / write interface definitions
552 * @param val change the values of drdy in reg STATUS
553 * @retval interface status (MANDATORY: return 0 -> no Error)
554 *
555 */
lis2dw12_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)556 int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
557 {
558 lis2dw12_status_t reg;
559 int32_t ret;
560
561 ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS, (uint8_t *) ®, 1);
562 *val = reg.drdy;
563
564 return ret;
565 }
566 /**
567 * @brief Read all the interrupt/status flag of the device.[get]
568 *
569 * @param ctx read / write interface definitions
570 * @param val registers STATUS_DUP, WAKE_UP_SRC,
571 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
572 * @retval interface status (MANDATORY: return 0 -> no Error)
573 *
574 */
lis2dw12_all_sources_get(const stmdev_ctx_t * ctx,lis2dw12_all_sources_t * val)575 int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx,
576 lis2dw12_all_sources_t *val)
577 {
578 int32_t ret;
579
580 ret = lis2dw12_read_reg(ctx, LIS2DW12_STATUS_DUP, (uint8_t *) val, 5);
581
582 return ret;
583 }
584
585 /**
586 * @brief Accelerometer X-axis user offset correction expressed in two’s
587 * complement, weight depends on bit USR_OFF_W. The value must be
588 * in the range [-127 127].[set]
589 *
590 * @param ctx read / write interface definitions
591 * @param buff buffer that contains data to write
592 * @retval interface status (MANDATORY: return 0 -> no Error)
593 *
594 */
lis2dw12_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)595 int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
596 {
597 int32_t ret;
598
599 ret = lis2dw12_write_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
600
601 return ret;
602 }
603
604 /**
605 * @brief Accelerometer X-axis user offset correction expressed in two’s
606 * complement, weight depends on bit USR_OFF_W. The value must be
607 * in the range [-127 127].[get]
608 *
609 * @param ctx read / write interface definitions
610 * @param buff buffer that stores data read
611 * @retval interface status (MANDATORY: return 0 -> no Error)
612 *
613 */
lis2dw12_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)614 int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
615 {
616 int32_t ret;
617
618 ret = lis2dw12_read_reg(ctx, LIS2DW12_X_OFS_USR, buff, 1);
619
620 return ret;
621 }
622
623 /**
624 * @brief Accelerometer Y-axis user offset correction expressed in two’s
625 * complement, weight depends on bit USR_OFF_W. The value must be
626 * in the range [-127 127].[set]
627 *
628 * @param ctx read / write interface definitions
629 * @param buff buffer that contains data to write
630 * @retval interface status (MANDATORY: return 0 -> no Error)
631 *
632 */
lis2dw12_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)633 int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
634 {
635 int32_t ret;
636
637 ret = lis2dw12_write_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
638
639 return ret;
640 }
641
642 /**
643 * @brief Accelerometer Y-axis user offset correction expressed in two’s
644 * complement, weight depends on bit USR_OFF_W. The value must be
645 * in the range [-127 127].[get]
646 *
647 * @param ctx read / write interface definitions
648 * @param buff buffer that stores data read
649 * @retval interface status (MANDATORY: return 0 -> no Error)
650 *
651 */
lis2dw12_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)652 int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
653 {
654 int32_t ret;
655
656 ret = lis2dw12_read_reg(ctx, LIS2DW12_Y_OFS_USR, buff, 1);
657
658 return ret;
659 }
660
661 /**
662 * @brief Accelerometer Z-axis user offset correction expressed in two’s
663 * complement, weight depends on bit USR_OFF_W. The value must be
664 * in the range [-127 127].[set]
665 *
666 * @param ctx read / write interface definitions
667 * @param buff buffer that contains data to write
668 * @retval interface status (MANDATORY: return 0 -> no Error)
669 *
670 */
lis2dw12_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)671 int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
672 {
673 int32_t ret;
674
675 ret = lis2dw12_write_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
676
677 return ret;
678 }
679
680 /**
681 * @brief Accelerometer Z-axis user offset correction expressed in two’s
682 * complement, weight depends on bit USR_OFF_W. The value must be
683 * in the range [-127 127].[get]
684 *
685 * @param ctx read / write interface definitions
686 * @param buff buffer that stores data read
687 * @retval interface status (MANDATORY: return 0 -> no Error)
688 *
689 */
lis2dw12_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)690 int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
691 {
692 int32_t ret;
693
694 ret = lis2dw12_read_reg(ctx, LIS2DW12_Z_OFS_USR, buff, 1);
695
696 return ret;
697 }
698
699 /**
700 * @brief Weight of XL user offset bits of registers X_OFS_USR,
701 * Y_OFS_USR, Z_OFS_USR.[set]
702 *
703 * @param ctx read / write interface definitions
704 * @param val change the values of usr_off_w in
705 * reg CTRL_REG7
706 * @retval interface status (MANDATORY: return 0 -> no Error)
707 *
708 */
lis2dw12_offset_weight_set(const stmdev_ctx_t * ctx,lis2dw12_usr_off_w_t val)709 int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx,
710 lis2dw12_usr_off_w_t val)
711 {
712 lis2dw12_ctrl_reg7_t reg;
713 int32_t ret;
714
715 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
716
717 if (ret == 0)
718 {
719 reg.usr_off_w = (uint8_t) val;
720 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
721 }
722
723 return ret;
724 }
725
726 /**
727 * @brief Weight of XL user offset bits of registers X_OFS_USR,
728 * Y_OFS_USR, Z_OFS_USR.[get]
729 *
730 * @param ctx read / write interface definitions
731 * @param val Get the values of usr_off_w in reg CTRL_REG7
732 * @retval interface status (MANDATORY: return 0 -> no Error)
733 *
734 */
lis2dw12_offset_weight_get(const stmdev_ctx_t * ctx,lis2dw12_usr_off_w_t * val)735 int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx,
736 lis2dw12_usr_off_w_t *val)
737 {
738 lis2dw12_ctrl_reg7_t reg;
739 int32_t ret;
740
741 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
742
743 switch (reg.usr_off_w)
744 {
745 case LIS2DW12_LSb_977ug:
746 *val = LIS2DW12_LSb_977ug;
747 break;
748
749 case LIS2DW12_LSb_15mg6:
750 *val = LIS2DW12_LSb_15mg6;
751 break;
752
753 default:
754 *val = LIS2DW12_LSb_977ug;
755 break;
756 }
757
758 return ret;
759 }
760
761 /**
762 * @}
763 *
764 */
765
766 /**
767 * @defgroup LIS2DW12_Data_Output
768 * @brief This section groups all the data output functions.
769 * @{
770 *
771 */
772
773 /**
774 * @brief Temperature data output register (r). L and H registers
775 * together express a 16-bit word in two’s complement.[get]
776 *
777 * @param ctx read / write interface definitions
778 * @param val buffer that stores data read
779 * @retval interface status (MANDATORY: return 0 -> no Error)
780 *
781 */
lis2dw12_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)782 int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
783 {
784 uint8_t buff[2];
785 int32_t ret;
786
787 ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_T_L, buff, 2);
788 *val = (int16_t)buff[1];
789 *val = (*val * 256) + (int16_t)buff[0];
790
791 return ret;
792 }
793
794 /**
795 * @brief Linear acceleration output register. The value is expressed as
796 * a 16-bit word in two’s complement.[get]
797 *
798 * @param ctx read / write interface definitions
799 * @param val buffer that stores data read
800 * @retval interface status (MANDATORY: return 0 -> no Error)
801 *
802 */
lis2dw12_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)803 int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
804 {
805 uint8_t buff[6];
806 int32_t ret;
807
808 ret = lis2dw12_read_reg(ctx, LIS2DW12_OUT_X_L, buff, 6);
809 val[0] = (int16_t)buff[1];
810 val[0] = (val[0] * 256) + (int16_t)buff[0];
811 val[1] = (int16_t)buff[3];
812 val[1] = (val[1] * 256) + (int16_t)buff[2];
813 val[2] = (int16_t)buff[5];
814 val[2] = (val[2] * 256) + (int16_t)buff[4];
815
816 return ret;
817 }
818
819 /**
820 * @}
821 *
822 */
823
824 /**
825 * @defgroup LIS2DW12_Common
826 * @brief This section groups common useful functions.
827 * @{
828 *
829 */
830
831 /**
832 * @brief Device Who am I.[get]
833 *
834 * @param ctx read / write interface definitions
835 * @param buff buffer that stores data read
836 * @retval interface status (MANDATORY: return 0 -> no Error)
837 *
838 */
lis2dw12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)839 int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
840 {
841 int32_t ret;
842
843 ret = lis2dw12_read_reg(ctx, LIS2DW12_WHO_AM_I, buff, 1);
844
845 return ret;
846 }
847
848 /**
849 * @brief Register address automatically incremented during multiple byte
850 * access with a serial interface.[set]
851 *
852 * @param ctx read / write interface definitions
853 * @param val change the values of if_add_inc in reg CTRL2
854 * @retval interface status (MANDATORY: return 0 -> no Error)
855 *
856 */
lis2dw12_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)857 int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
858 {
859 lis2dw12_ctrl2_t reg;
860 int32_t ret;
861
862 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
863
864 if (ret == 0)
865 {
866 reg.if_add_inc = val;
867 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
868 }
869
870 return ret;
871 }
872
873 /**
874 * @brief Register address automatically incremented during multiple
875 * byte access with a serial interface.[get]
876 *
877 * @param ctx read / write interface definitions
878 * @param val change the values of if_add_inc in reg CTRL2
879 * @retval interface status (MANDATORY: return 0 -> no Error)
880 *
881 */
lis2dw12_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)882 int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
883 {
884 lis2dw12_ctrl2_t reg;
885 int32_t ret;
886
887 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
888 *val = reg.if_add_inc;
889
890 return ret;
891 }
892
893 /**
894 * @brief Software reset. Restore the default values in user registers.[set]
895 *
896 * @param ctx read / write interface definitions
897 * @param val change the values of soft_reset in reg CTRL2
898 * @retval interface status (MANDATORY: return 0 -> no Error)
899 *
900 */
lis2dw12_reset_set(const stmdev_ctx_t * ctx,uint8_t val)901 int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
902 {
903 lis2dw12_ctrl2_t reg;
904 int32_t ret;
905
906 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
907
908 if (ret == 0)
909 {
910 reg.soft_reset = val;
911 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
912 }
913
914 return ret;
915 }
916
917 /**
918 * @brief Software reset. Restore the default values in user registers.[get]
919 *
920 * @param ctx read / write interface definitions
921 * @param val change the values of soft_reset in reg CTRL2
922 * @retval interface status (MANDATORY: return 0 -> no Error)
923 *
924 */
lis2dw12_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)925 int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
926 {
927 lis2dw12_ctrl2_t reg;
928 int32_t ret;
929
930 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
931 *val = reg.soft_reset;
932
933 return ret;
934 }
935
936 /**
937 * @brief Reboot memory content. Reload the calibration parameters.[set]
938 *
939 * @param ctx read / write interface definitions
940 * @param val change the values of boot in reg CTRL2
941 * @retval interface status (MANDATORY: return 0 -> no Error)
942 *
943 */
lis2dw12_boot_set(const stmdev_ctx_t * ctx,uint8_t val)944 int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
945 {
946 lis2dw12_ctrl2_t reg;
947 int32_t ret;
948
949 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
950
951 if (ret == 0)
952 {
953 reg.boot = val;
954 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
955 }
956
957 return ret;
958 }
959
960 /**
961 * @brief Reboot memory content. Reload the calibration parameters.[get]
962 *
963 * @param ctx read / write interface definitions
964 * @param val change the values of boot in reg CTRL2
965 * @retval interface status (MANDATORY: return 0 -> no Error)
966 *
967 */
lis2dw12_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)968 int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
969 {
970 lis2dw12_ctrl2_t reg;
971 int32_t ret;
972
973 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
974 *val = reg.boot;
975
976 return ret;
977 }
978
979 /**
980 * @brief Sensor self-test enable.[set]
981 *
982 * @param ctx read / write interface definitions
983 * @param val change the values of st in reg CTRL3
984 * @retval interface status (MANDATORY: return 0 -> no Error)
985 *
986 */
lis2dw12_self_test_set(const stmdev_ctx_t * ctx,lis2dw12_st_t val)987 int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val)
988 {
989 lis2dw12_ctrl3_t reg;
990 int32_t ret;
991
992 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
993
994 if (ret == 0)
995 {
996 reg.st = (uint8_t) val;
997 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
998 }
999
1000 return ret;
1001 }
1002
1003 /**
1004 * @brief Sensor self-test enable.[get]
1005 *
1006 * @param ctx read / write interface definitions
1007 * @param val Get the values of st in reg CTRL3
1008 * @retval interface status (MANDATORY: return 0 -> no Error)
1009 *
1010 */
lis2dw12_self_test_get(const stmdev_ctx_t * ctx,lis2dw12_st_t * val)1011 int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val)
1012 {
1013 lis2dw12_ctrl3_t reg;
1014 int32_t ret;
1015
1016 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1017
1018 switch (reg.st)
1019 {
1020 case LIS2DW12_XL_ST_DISABLE:
1021 *val = LIS2DW12_XL_ST_DISABLE;
1022 break;
1023
1024 case LIS2DW12_XL_ST_POSITIVE:
1025 *val = LIS2DW12_XL_ST_POSITIVE;
1026 break;
1027
1028 case LIS2DW12_XL_ST_NEGATIVE:
1029 *val = LIS2DW12_XL_ST_NEGATIVE;
1030 break;
1031
1032 default:
1033 *val = LIS2DW12_XL_ST_DISABLE;
1034 break;
1035 }
1036
1037 return ret;
1038 }
1039
1040 /**
1041 * @brief Data-ready pulsed / letched mode.[set]
1042 *
1043 * @param ctx read / write interface definitions
1044 * @param val change the values of drdy_pulsed in reg CTRL_REG7
1045 * @retval interface status (MANDATORY: return 0 -> no Error)
1046 *
1047 */
lis2dw12_data_ready_mode_set(const stmdev_ctx_t * ctx,lis2dw12_drdy_pulsed_t val)1048 int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx,
1049 lis2dw12_drdy_pulsed_t val)
1050 {
1051 lis2dw12_ctrl_reg7_t reg;
1052 int32_t ret;
1053
1054 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1055
1056 if (ret == 0)
1057 {
1058 reg.drdy_pulsed = (uint8_t) val;
1059 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1060 }
1061
1062 return ret;
1063 }
1064
1065 /**
1066 * @brief Data-ready pulsed / letched mode.[get]
1067 *
1068 * @param ctx read / write interface definitions
1069 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
1070 * @retval interface status (MANDATORY: return 0 -> no Error)
1071 *
1072 */
lis2dw12_data_ready_mode_get(const stmdev_ctx_t * ctx,lis2dw12_drdy_pulsed_t * val)1073 int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx,
1074 lis2dw12_drdy_pulsed_t *val)
1075 {
1076 lis2dw12_ctrl_reg7_t reg;
1077 int32_t ret;
1078
1079 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1080
1081 switch (reg.drdy_pulsed)
1082 {
1083 case LIS2DW12_DRDY_LATCHED:
1084 *val = LIS2DW12_DRDY_LATCHED;
1085 break;
1086
1087 case LIS2DW12_DRDY_PULSED:
1088 *val = LIS2DW12_DRDY_PULSED;
1089 break;
1090
1091 default:
1092 *val = LIS2DW12_DRDY_LATCHED;
1093 break;
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @}
1101 *
1102 */
1103
1104 /**
1105 * @defgroup LIS2DW12_Filters
1106 * @brief This section group all the functions concerning the filters
1107 * configuration.
1108 * @{
1109 *
1110 */
1111
1112 /**
1113 * @brief Accelerometer filtering path for outputs.[set]
1114 *
1115 * @param ctx read / write interface definitions
1116 * @param val change the values of fds in reg CTRL6
1117 * @retval interface status (MANDATORY: return 0 -> no Error)
1118 *
1119 */
lis2dw12_filter_path_set(const stmdev_ctx_t * ctx,lis2dw12_fds_t val)1120 int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx,
1121 lis2dw12_fds_t val)
1122 {
1123 lis2dw12_ctrl6_t ctrl6;
1124 lis2dw12_ctrl_reg7_t ctrl_reg7;
1125 int32_t ret;
1126
1127 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1128
1129 if (ret == 0)
1130 {
1131 ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
1132 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1133 }
1134
1135 if (ret == 0)
1136 {
1137 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
1138 (uint8_t *) &ctrl_reg7, 1);
1139 }
1140
1141 if (ret == 0)
1142 {
1143 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
1144 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7,
1145 (uint8_t *) &ctrl_reg7, 1);
1146 }
1147
1148 return ret;
1149 }
1150
1151 /**
1152 * @brief Accelerometer filtering path for outputs.[get]
1153 *
1154 * @param ctx read / write interface definitions
1155 * @param val Get the values of fds in reg CTRL6
1156 * @retval interface status (MANDATORY: return 0 -> no Error)
1157 *
1158 */
lis2dw12_filter_path_get(const stmdev_ctx_t * ctx,lis2dw12_fds_t * val)1159 int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx,
1160 lis2dw12_fds_t *val)
1161 {
1162 lis2dw12_ctrl6_t ctrl6;
1163 lis2dw12_ctrl_reg7_t ctrl_reg7;
1164 int32_t ret;
1165
1166 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1167
1168 if (ret == 0)
1169 {
1170 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7,
1171 (uint8_t *) &ctrl_reg7, 1);
1172
1173 switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
1174 {
1175 case LIS2DW12_LPF_ON_OUT:
1176 *val = LIS2DW12_LPF_ON_OUT;
1177 break;
1178
1179 case LIS2DW12_USER_OFFSET_ON_OUT:
1180 *val = LIS2DW12_USER_OFFSET_ON_OUT;
1181 break;
1182
1183 case LIS2DW12_HIGH_PASS_ON_OUT:
1184 *val = LIS2DW12_HIGH_PASS_ON_OUT;
1185 break;
1186
1187 default:
1188 *val = LIS2DW12_LPF_ON_OUT;
1189 break;
1190 }
1191 }
1192
1193 return ret;
1194 }
1195
1196 /**
1197 * @brief Accelerometer cutoff filter frequency. Valid for low and high
1198 * pass filter.[set]
1199 *
1200 * @param ctx read / write interface definitions
1201 * @param val change the values of bw_filt in reg CTRL6
1202 * @retval interface status (MANDATORY: return 0 -> no Error)
1203 *
1204 */
lis2dw12_filter_bandwidth_set(const stmdev_ctx_t * ctx,lis2dw12_bw_filt_t val)1205 int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx,
1206 lis2dw12_bw_filt_t val)
1207 {
1208 lis2dw12_ctrl6_t reg;
1209 int32_t ret;
1210
1211 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
1212
1213 if (ret == 0)
1214 {
1215 reg.bw_filt = (uint8_t) val;
1216 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
1217 }
1218
1219 return ret;
1220 }
1221
1222 /**
1223 * @brief Accelerometer cutoff filter frequency. Valid for low and
1224 * high pass filter.[get]
1225 *
1226 * @param ctx read / write interface definitions
1227 * @param val Get the values of bw_filt in reg CTRL6
1228 * @retval interface status (MANDATORY: return 0 -> no Error)
1229 *
1230 */
lis2dw12_filter_bandwidth_get(const stmdev_ctx_t * ctx,lis2dw12_bw_filt_t * val)1231 int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx,
1232 lis2dw12_bw_filt_t *val)
1233 {
1234 lis2dw12_ctrl6_t reg;
1235 int32_t ret;
1236
1237 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL6, (uint8_t *) ®, 1);
1238
1239 switch (reg.bw_filt)
1240 {
1241 case LIS2DW12_ODR_DIV_2:
1242 *val = LIS2DW12_ODR_DIV_2;
1243 break;
1244
1245 case LIS2DW12_ODR_DIV_4:
1246 *val = LIS2DW12_ODR_DIV_4;
1247 break;
1248
1249 case LIS2DW12_ODR_DIV_10:
1250 *val = LIS2DW12_ODR_DIV_10;
1251 break;
1252
1253 case LIS2DW12_ODR_DIV_20:
1254 *val = LIS2DW12_ODR_DIV_20;
1255 break;
1256
1257 default:
1258 *val = LIS2DW12_ODR_DIV_2;
1259 break;
1260 }
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief Enable HP filter reference mode.[set]
1267 *
1268 * @param ctx read / write interface definitions
1269 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1270 * @retval interface status (MANDATORY: return 0 -> no Error)
1271 *
1272 */
lis2dw12_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)1273 int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
1274 {
1275 lis2dw12_ctrl_reg7_t reg;
1276 int32_t ret;
1277
1278 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1279
1280 if (ret == 0)
1281 {
1282 reg.hp_ref_mode = val;
1283 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1284 }
1285
1286 return ret;
1287 }
1288
1289 /**
1290 * @brief Enable HP filter reference mode.[get]
1291 *
1292 * @param ctx read / write interface definitions
1293 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1294 * @retval interface status (MANDATORY: return 0 -> no Error)
1295 *
1296 */
lis2dw12_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)1297 int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
1298 {
1299 lis2dw12_ctrl_reg7_t reg;
1300 int32_t ret;
1301
1302 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1303 *val = reg.hp_ref_mode;
1304
1305 return ret;
1306 }
1307
1308 /**
1309 * @}
1310 *
1311 */
1312
1313 /**
1314 * @defgroup LIS2DW12_Serial_Interface
1315 * @brief This section groups all the functions concerning main serial
1316 * interface management (not auxiliary)
1317 * @{
1318 *
1319 */
1320
1321 /**
1322 * @brief SPI Serial Interface Mode selection.[set]
1323 *
1324 * @param ctx read / write interface definitions
1325 * @param val change the values of sim in reg CTRL2
1326 * @retval interface status (MANDATORY: return 0 -> no Error)
1327 *
1328 */
lis2dw12_spi_mode_set(const stmdev_ctx_t * ctx,lis2dw12_sim_t val)1329 int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val)
1330 {
1331 lis2dw12_ctrl2_t reg;
1332 int32_t ret;
1333
1334 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1335
1336 if (ret == 0)
1337 {
1338 reg.sim = (uint8_t) val;
1339 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1340 }
1341
1342 return ret;
1343 }
1344
1345 /**
1346 * @brief SPI Serial Interface Mode selection.[get]
1347 *
1348 * @param ctx read / write interface definitions
1349 * @param val Get the values of sim in reg CTRL2
1350 * @retval interface status (MANDATORY: return 0 -> no Error)
1351 *
1352 */
lis2dw12_spi_mode_get(const stmdev_ctx_t * ctx,lis2dw12_sim_t * val)1353 int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val)
1354 {
1355 lis2dw12_ctrl2_t reg;
1356 int32_t ret;
1357
1358 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1359
1360 switch (reg.sim)
1361 {
1362 case LIS2DW12_SPI_4_WIRE:
1363 *val = LIS2DW12_SPI_4_WIRE;
1364 break;
1365
1366 case LIS2DW12_SPI_3_WIRE:
1367 *val = LIS2DW12_SPI_3_WIRE;
1368 break;
1369
1370 default:
1371 *val = LIS2DW12_SPI_4_WIRE;
1372 break;
1373 }
1374
1375 return ret;
1376 }
1377
1378 /**
1379 * @brief Disable / Enable I2C interface.[set]
1380 *
1381 * @param ctx read / write interface definitions
1382 * @param val change the values of i2c_disable in
1383 * reg CTRL2
1384 * @retval interface status (MANDATORY: return 0 -> no Error)
1385 *
1386 */
lis2dw12_i2c_interface_set(const stmdev_ctx_t * ctx,lis2dw12_i2c_disable_t val)1387 int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx,
1388 lis2dw12_i2c_disable_t val)
1389 {
1390 lis2dw12_ctrl2_t reg;
1391 int32_t ret;
1392
1393 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1394
1395 if (ret == 0)
1396 {
1397 reg.i2c_disable = (uint8_t) val;
1398 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1399 }
1400
1401 return ret;
1402 }
1403
1404 /**
1405 * @brief Disable / Enable I2C interface.[get]
1406 *
1407 * @param ctx read / write interface definitions
1408 * @param val Get the values of i2c_disable in reg CTRL2
1409 * @retval interface status (MANDATORY: return 0 -> no Error)
1410 *
1411 */
lis2dw12_i2c_interface_get(const stmdev_ctx_t * ctx,lis2dw12_i2c_disable_t * val)1412 int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx,
1413 lis2dw12_i2c_disable_t *val)
1414 {
1415 lis2dw12_ctrl2_t reg;
1416 int32_t ret;
1417
1418 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1419
1420 switch (reg.i2c_disable)
1421 {
1422 case LIS2DW12_I2C_ENABLE:
1423 *val = LIS2DW12_I2C_ENABLE;
1424 break;
1425
1426 case LIS2DW12_I2C_DISABLE:
1427 *val = LIS2DW12_I2C_DISABLE;
1428 break;
1429
1430 default:
1431 *val = LIS2DW12_I2C_ENABLE;
1432 break;
1433 }
1434
1435 return ret;
1436 }
1437
1438 /**
1439 * @brief Disconnect CS pull-up.[set]
1440 *
1441 * @param ctx read / write interface definitions
1442 * @param val change the values of cs_pu_disc in reg CTRL2
1443 * @retval interface status (MANDATORY: return 0 -> no Error)
1444 *
1445 */
lis2dw12_cs_mode_set(const stmdev_ctx_t * ctx,lis2dw12_cs_pu_disc_t val)1446 int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx,
1447 lis2dw12_cs_pu_disc_t val)
1448 {
1449 lis2dw12_ctrl2_t reg;
1450 int32_t ret;
1451
1452 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1453
1454 if (ret == 0)
1455 {
1456 reg.cs_pu_disc = (uint8_t) val;
1457 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1458 }
1459
1460 return ret;
1461 }
1462
1463 /**
1464 * @brief Disconnect CS pull-up.[get]
1465 *
1466 * @param ctx read / write interface definitions
1467 * @param val Get the values of cs_pu_disc in reg CTRL2
1468 * @retval interface status (MANDATORY: return 0 -> no Error)
1469 *
1470 */
lis2dw12_cs_mode_get(const stmdev_ctx_t * ctx,lis2dw12_cs_pu_disc_t * val)1471 int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx,
1472 lis2dw12_cs_pu_disc_t *val)
1473 {
1474 lis2dw12_ctrl2_t reg;
1475 int32_t ret;
1476
1477 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL2, (uint8_t *) ®, 1);
1478
1479 switch (reg.cs_pu_disc)
1480 {
1481 case LIS2DW12_PULL_UP_CONNECT:
1482 *val = LIS2DW12_PULL_UP_CONNECT;
1483 break;
1484
1485 case LIS2DW12_PULL_UP_DISCONNECT:
1486 *val = LIS2DW12_PULL_UP_DISCONNECT;
1487 break;
1488
1489 default:
1490 *val = LIS2DW12_PULL_UP_CONNECT;
1491 break;
1492 }
1493
1494 return ret;
1495 }
1496
1497 /**
1498 * @}
1499 *
1500 */
1501
1502 /**
1503 * @defgroup LIS2DW12_Interrupt_Pins
1504 * @brief This section groups all the functions that manage interrupt pins
1505 * @{
1506 *
1507 */
1508
1509 /**
1510 * @brief Interrupt active-high/low.[set]
1511 *
1512 * @param ctx read / write interface definitions
1513 * @param val change the values of h_lactive in reg CTRL3
1514 * @retval interface status (MANDATORY: return 0 -> no Error)
1515 *
1516 */
lis2dw12_pin_polarity_set(const stmdev_ctx_t * ctx,lis2dw12_h_lactive_t val)1517 int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx,
1518 lis2dw12_h_lactive_t val)
1519 {
1520 lis2dw12_ctrl3_t reg;
1521 int32_t ret;
1522
1523 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1524
1525 if (ret == 0)
1526 {
1527 reg.h_lactive = (uint8_t) val;
1528 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1529 }
1530
1531 return ret;
1532 }
1533
1534 /**
1535 * @brief Interrupt active-high/low.[get]
1536 *
1537 * @param ctx read / write interface definitions
1538 * @param val Get the values of h_lactive in reg CTRL3
1539 * @retval interface status (MANDATORY: return 0 -> no Error)
1540 *
1541 */
lis2dw12_pin_polarity_get(const stmdev_ctx_t * ctx,lis2dw12_h_lactive_t * val)1542 int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx,
1543 lis2dw12_h_lactive_t *val)
1544 {
1545 lis2dw12_ctrl3_t reg;
1546 int32_t ret;
1547
1548 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1549
1550 switch (reg.h_lactive)
1551 {
1552 case LIS2DW12_ACTIVE_HIGH:
1553 *val = LIS2DW12_ACTIVE_HIGH;
1554 break;
1555
1556 case LIS2DW12_ACTIVE_LOW:
1557 *val = LIS2DW12_ACTIVE_LOW;
1558 break;
1559
1560 default:
1561 *val = LIS2DW12_ACTIVE_HIGH;
1562 break;
1563 }
1564
1565 return ret;
1566 }
1567
1568 /**
1569 * @brief Latched/pulsed interrupt.[set]
1570 *
1571 * @param ctx read / write interface definitions
1572 * @param val change the values of lir in reg CTRL3
1573 * @retval interface status (MANDATORY: return 0 -> no Error)
1574 *
1575 */
lis2dw12_int_notification_set(const stmdev_ctx_t * ctx,lis2dw12_lir_t val)1576 int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx,
1577 lis2dw12_lir_t val)
1578 {
1579 lis2dw12_ctrl3_t reg;
1580 int32_t ret;
1581
1582 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1583
1584 if (ret == 0)
1585 {
1586 reg.lir = (uint8_t) val;
1587 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1588 }
1589
1590 return ret;
1591 }
1592
1593 /**
1594 * @brief Latched/pulsed interrupt.[get]
1595 *
1596 * @param ctx read / write interface definitions
1597 * @param val Get the values of lir in reg CTRL3
1598 * @retval interface status (MANDATORY: return 0 -> no Error)
1599 *
1600 */
lis2dw12_int_notification_get(const stmdev_ctx_t * ctx,lis2dw12_lir_t * val)1601 int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx,
1602 lis2dw12_lir_t *val)
1603 {
1604 lis2dw12_ctrl3_t reg;
1605 int32_t ret;
1606
1607 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1608
1609 switch (reg.lir)
1610 {
1611 case LIS2DW12_INT_PULSED:
1612 *val = LIS2DW12_INT_PULSED;
1613 break;
1614
1615 case LIS2DW12_INT_LATCHED:
1616 *val = LIS2DW12_INT_LATCHED;
1617 break;
1618
1619 default:
1620 *val = LIS2DW12_INT_PULSED;
1621 break;
1622 }
1623
1624 return ret;
1625 }
1626
1627 /**
1628 * @brief Push-pull/open drain selection on interrupt pads.[set]
1629 *
1630 * @param ctx read / write interface definitions
1631 * @param val change the values of pp_od in reg CTRL3
1632 * @retval interface status (MANDATORY: return 0 -> no Error)
1633 *
1634 */
lis2dw12_pin_mode_set(const stmdev_ctx_t * ctx,lis2dw12_pp_od_t val)1635 int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t val)
1636 {
1637 lis2dw12_ctrl3_t reg;
1638 int32_t ret;
1639
1640 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1641
1642 if (ret == 0)
1643 {
1644 reg.pp_od = (uint8_t) val;
1645 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1646 }
1647
1648 return ret;
1649 }
1650
1651 /**
1652 * @brief Push-pull/open drain selection on interrupt pads.[get]
1653 *
1654 * @param ctx read / write interface definitions
1655 * @param val Get the values of pp_od in reg CTRL3
1656 * @retval interface status (MANDATORY: return 0 -> no Error)
1657 *
1658 */
lis2dw12_pin_mode_get(const stmdev_ctx_t * ctx,lis2dw12_pp_od_t * val)1659 int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx,
1660 lis2dw12_pp_od_t *val)
1661 {
1662 lis2dw12_ctrl3_t reg;
1663 int32_t ret;
1664
1665 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL3, (uint8_t *) ®, 1);
1666
1667 switch (reg.pp_od)
1668 {
1669 case LIS2DW12_PUSH_PULL:
1670 *val = LIS2DW12_PUSH_PULL;
1671 break;
1672
1673 case LIS2DW12_OPEN_DRAIN:
1674 *val = LIS2DW12_OPEN_DRAIN;
1675 break;
1676
1677 default:
1678 *val = LIS2DW12_PUSH_PULL;
1679 break;
1680 }
1681
1682 return ret;
1683 }
1684
1685 /**
1686 * @brief Select the signal that need to route on int1 pad.[set]
1687 *
1688 * @param ctx read / write interface definitions
1689 * @param val register CTRL4_INT1_PAD_CTRL.
1690 * @retval interface status (MANDATORY: return 0 -> no Error)
1691 *
1692 */
lis2dw12_pin_int1_route_set(const stmdev_ctx_t * ctx,lis2dw12_ctrl4_int1_pad_ctrl_t * val)1693 int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1694 lis2dw12_ctrl4_int1_pad_ctrl_t *val)
1695 {
1696 lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl;
1697 lis2dw12_ctrl_reg7_t reg;
1698 int32_t ret;
1699
1700 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
1701 (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
1702
1703 if (ret == 0)
1704 {
1705 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1706 }
1707
1708 if (ret == 0)
1709 {
1710 if ((val->int1_tap |
1711 val->int1_ff |
1712 val->int1_wu |
1713 val->int1_single_tap |
1714 val->int1_6d |
1715 ctrl5_int2_pad_ctrl.int2_sleep_state |
1716 ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
1717 {
1718 reg.interrupts_enable = PROPERTY_ENABLE;
1719 }
1720
1721 else
1722 {
1723 reg.interrupts_enable = PROPERTY_DISABLE;
1724 }
1725
1726 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
1727 (uint8_t *) val, 1);
1728 }
1729
1730 if (ret == 0)
1731 {
1732 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1733 }
1734
1735 return ret;
1736 }
1737
1738 /**
1739 * @brief Select the signal that need to route on int1 pad.[get]
1740 *
1741 * @param ctx read / write interface definitions
1742 * @param val register CTRL4_INT1_PAD_CTRL.
1743 * @retval interface status (MANDATORY: return 0 -> no Error)
1744 *
1745 */
lis2dw12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2dw12_ctrl4_int1_pad_ctrl_t * val)1746 int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx,
1747 lis2dw12_ctrl4_int1_pad_ctrl_t *val)
1748 {
1749 int32_t ret;
1750
1751 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
1752 (uint8_t *) val, 1);
1753
1754 return ret;
1755 }
1756
1757 /**
1758 * @brief Select the signal that need to route on int2 pad.[set]
1759 *
1760 * @param ctx read / write interface definitions
1761 * @param val register CTRL5_INT2_PAD_CTRL.
1762 * @retval interface status (MANDATORY: return 0 -> no Error)
1763 *
1764 */
lis2dw12_pin_int2_route_set(const stmdev_ctx_t * ctx,lis2dw12_ctrl5_int2_pad_ctrl_t * val)1765 int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1766 lis2dw12_ctrl5_int2_pad_ctrl_t *val)
1767 {
1768 lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl;
1769 lis2dw12_ctrl_reg7_t reg;
1770 int32_t ret;
1771
1772 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL4_INT1_PAD_CTRL,
1773 (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
1774
1775 if (ret == 0)
1776 {
1777 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1778 }
1779
1780 if (ret == 0)
1781 {
1782 if ((ctrl4_int1_pad_ctrl.int1_tap |
1783 ctrl4_int1_pad_ctrl.int1_ff |
1784 ctrl4_int1_pad_ctrl.int1_wu |
1785 ctrl4_int1_pad_ctrl.int1_single_tap |
1786 ctrl4_int1_pad_ctrl.int1_6d |
1787 val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
1788 {
1789 reg.interrupts_enable = PROPERTY_ENABLE;
1790 }
1791
1792 else
1793 {
1794 reg.interrupts_enable = PROPERTY_DISABLE;
1795 }
1796
1797 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
1798 (uint8_t *) val, 1);
1799 }
1800
1801 if (ret == 0)
1802 {
1803 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1804 }
1805
1806 return ret;
1807 }
1808
1809 /**
1810 * @brief Select the signal that need to route on int2 pad.[get]
1811 *
1812 * @param ctx read / write interface definitions
1813 * @param val register CTRL5_INT2_PAD_CTRL
1814 * @retval interface status (MANDATORY: return 0 -> no Error)
1815 *
1816 */
lis2dw12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2dw12_ctrl5_int2_pad_ctrl_t * val)1817 int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx,
1818 lis2dw12_ctrl5_int2_pad_ctrl_t *val)
1819 {
1820 int32_t ret;
1821
1822 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL5_INT2_PAD_CTRL,
1823 (uint8_t *) val, 1);
1824
1825 return ret;
1826 }
1827 /**
1828 * @brief All interrupt signals become available on INT1 pin.[set]
1829 *
1830 * @param ctx read / write interface definitions
1831 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1832 * @retval interface status (MANDATORY: return 0 -> no Error)
1833 *
1834 */
lis2dw12_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)1835 int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
1836 {
1837 lis2dw12_ctrl_reg7_t reg;
1838 int32_t ret;
1839
1840 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1841
1842 if (ret == 0)
1843 {
1844 reg.int2_on_int1 = val;
1845 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1846 }
1847
1848 return ret;
1849 }
1850
1851 /**
1852 * @brief All interrupt signals become available on INT1 pin.[get]
1853 *
1854 * @param ctx read / write interface definitions
1855 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1856 * @retval interface status (MANDATORY: return 0 -> no Error)
1857 *
1858 */
lis2dw12_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)1859 int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1860 {
1861 lis2dw12_ctrl_reg7_t reg;
1862 int32_t ret;
1863
1864 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1865 *val = reg.int2_on_int1;
1866
1867 return ret;
1868 }
1869
1870 /**
1871 * @}
1872 *
1873 */
1874
1875 /**
1876 * @defgroup LIS2DW12_Wake_Up_Event
1877 * @brief This section groups all the functions that manage the Wake
1878 * Up event generation.
1879 * @{
1880 *
1881 */
1882
1883 /**
1884 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
1885 *
1886 * @param ctx read / write interface definitions
1887 * @param val change the values of wk_ths in reg WAKE_UP_THS
1888 * @retval interface status (MANDATORY: return 0 -> no Error)
1889 *
1890 */
lis2dw12_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1891 int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1892 {
1893 lis2dw12_wake_up_ths_t reg;
1894 int32_t ret;
1895
1896 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1897
1898 if (ret == 0)
1899 {
1900 reg.wk_ths = val;
1901 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1902 }
1903
1904 return ret;
1905 }
1906
1907 /**
1908 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
1909 *
1910 * @param ctx read / write interface definitions
1911 * @param val change the values of wk_ths in reg WAKE_UP_THS
1912 * @retval interface status (MANDATORY: return 0 -> no Error)
1913 *
1914 */
lis2dw12_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1915 int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1916 {
1917 lis2dw12_wake_up_ths_t reg;
1918 int32_t ret;
1919
1920 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1921 *val = reg.wk_ths;
1922
1923 return ret;
1924 }
1925
1926 /**
1927 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
1928 *
1929 * @param ctx read / write interface definitions
1930 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1931 * @retval interface status (MANDATORY: return 0 -> no Error)
1932 *
1933 */
lis2dw12_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1934 int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1935 {
1936 lis2dw12_wake_up_dur_t reg;
1937 int32_t ret;
1938
1939 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1940
1941 if (ret == 0)
1942 {
1943 reg.wake_dur = val;
1944 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1945 }
1946
1947 return ret;
1948 }
1949
1950 /**
1951 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
1952 *
1953 * @param ctx read / write interface definitions
1954 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1955 * @retval interface status (MANDATORY: return 0 -> no Error)
1956 *
1957 */
lis2dw12_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1958 int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1959 {
1960 lis2dw12_wake_up_dur_t reg;
1961 int32_t ret;
1962
1963 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1964 *val = reg.wake_dur;
1965
1966 return ret;
1967 }
1968
1969 /**
1970 * @brief Data sent to wake-up interrupt function.[set]
1971 *
1972 * @param ctx read / write interface definitions
1973 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
1974 * @retval interface status (MANDATORY: return 0 -> no Error)
1975 *
1976 */
lis2dw12_wkup_feed_data_set(const stmdev_ctx_t * ctx,lis2dw12_usr_off_on_wu_t val)1977 int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx,
1978 lis2dw12_usr_off_on_wu_t val)
1979 {
1980 lis2dw12_ctrl_reg7_t reg;
1981 int32_t ret;
1982
1983 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1984
1985 if (ret == 0)
1986 {
1987 reg.usr_off_on_wu = (uint8_t) val;
1988 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
1989 }
1990
1991 return ret;
1992 }
1993
1994 /**
1995 * @brief Data sent to wake-up interrupt function.[get]
1996 *
1997 * @param ctx read / write interface definitions
1998 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
1999 * @retval interface status (MANDATORY: return 0 -> no Error)
2000 *
2001 */
lis2dw12_wkup_feed_data_get(const stmdev_ctx_t * ctx,lis2dw12_usr_off_on_wu_t * val)2002 int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx,
2003 lis2dw12_usr_off_on_wu_t *val)
2004 {
2005 lis2dw12_ctrl_reg7_t reg;
2006 int32_t ret;
2007
2008 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
2009
2010 switch (reg.usr_off_on_wu)
2011 {
2012 case LIS2DW12_HP_FEED:
2013 *val = LIS2DW12_HP_FEED;
2014 break;
2015
2016 case LIS2DW12_USER_OFFSET_FEED:
2017 *val = LIS2DW12_USER_OFFSET_FEED;
2018 break;
2019
2020 default:
2021 *val = LIS2DW12_HP_FEED;
2022 break;
2023 }
2024
2025 return ret;
2026 }
2027
2028 /**
2029 * @}
2030 *
2031 */
2032
2033 /**
2034 * @defgroup LIS2DW12_Activity/Inactivity_Detection
2035 * @brief This section groups all the functions concerning
2036 * activity/inactivity detection.
2037 * @{
2038 *
2039 */
2040
2041 /**
2042 * @brief Config activity / inactivity or
2043 * stationary / motion detection.[set]
2044 *
2045 * @param ctx read / write interface definitions
2046 * @param val change the values of sleep_on / stationary in
2047 * reg WAKE_UP_THS / WAKE_UP_DUR
2048 * @retval interface status (MANDATORY: return 0 -> no Error)
2049 *
2050 */
lis2dw12_act_mode_set(const stmdev_ctx_t * ctx,lis2dw12_sleep_on_t val)2051 int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx,
2052 lis2dw12_sleep_on_t val)
2053 {
2054 lis2dw12_wake_up_ths_t wake_up_ths;
2055 lis2dw12_wake_up_dur_t wake_up_dur;
2056 int32_t ret;
2057
2058 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
2059 (uint8_t *) &wake_up_ths, 1);
2060
2061 if (ret == 0)
2062 {
2063 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
2064 (uint8_t *) &wake_up_dur, 1);
2065 }
2066
2067 if (ret == 0)
2068 {
2069 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
2070 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS,
2071 (uint8_t *) &wake_up_ths, 1);
2072 }
2073
2074 if (ret == 0)
2075 {
2076 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
2077 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
2078 (uint8_t *) &wake_up_dur, 1);
2079 }
2080
2081 return ret;
2082 }
2083
2084 /**
2085 * @brief Config activity / inactivity or
2086 * stationary / motion detection. [get]
2087 *
2088 * @param ctx read / write interface definitions
2089 * @param val Get the values of sleep_on in reg WAKE_UP_THS
2090 * @retval interface status (MANDATORY: return 0 -> no Error)
2091 *
2092 */
lis2dw12_act_mode_get(const stmdev_ctx_t * ctx,lis2dw12_sleep_on_t * val)2093 int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx,
2094 lis2dw12_sleep_on_t *val)
2095 {
2096 lis2dw12_wake_up_ths_t wake_up_ths;
2097 lis2dw12_wake_up_dur_t wake_up_dur;;
2098 int32_t ret;
2099
2100 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS,
2101 (uint8_t *) &wake_up_ths, 1);
2102
2103 if (ret == 0)
2104 {
2105 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
2106 (uint8_t *) &wake_up_dur, 1);
2107
2108 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
2109 {
2110 case LIS2DW12_NO_DETECTION:
2111 *val = LIS2DW12_NO_DETECTION;
2112 break;
2113
2114 case LIS2DW12_DETECT_ACT_INACT:
2115 *val = LIS2DW12_DETECT_ACT_INACT;
2116 break;
2117
2118 case LIS2DW12_DETECT_STAT_MOTION:
2119 *val = LIS2DW12_DETECT_STAT_MOTION;
2120 break;
2121
2122 default:
2123 *val = LIS2DW12_NO_DETECTION;
2124 break;
2125 }
2126 }
2127
2128 return ret;
2129 }
2130
2131 /**
2132 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
2133 *
2134 * @param ctx read / write interface definitions
2135 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2136 * @retval interface status (MANDATORY: return 0 -> no Error)
2137 *
2138 */
lis2dw12_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2139 int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2140 {
2141 lis2dw12_wake_up_dur_t reg;
2142 int32_t ret;
2143
2144 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2145
2146 if (ret == 0)
2147 {
2148 reg.sleep_dur = val;
2149 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2150 }
2151
2152 return ret;
2153 }
2154
2155 /**
2156 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
2157 *
2158 * @param ctx read / write interface definitions
2159 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2160 * @retval interface status (MANDATORY: return 0 -> no Error)
2161 *
2162 */
lis2dw12_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2163 int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2164 {
2165 lis2dw12_wake_up_dur_t reg;
2166 int32_t ret;
2167
2168 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2169 *val = reg.sleep_dur;
2170
2171 return ret;
2172 }
2173
2174 /**
2175 * @}
2176 *
2177 */
2178
2179 /**
2180 * @defgroup LIS2DW12_Tap_Generator
2181 * @brief This section groups all the functions that manage the tap
2182 * and double tap event generation.
2183 * @{
2184 *
2185 */
2186
2187 /**
2188 * @brief Threshold for tap recognition.[set]
2189 *
2190 * @param ctx read / write interface definitions
2191 * @param val change the values of tap_thsx in reg TAP_THS_X
2192 * @retval interface status (MANDATORY: return 0 -> no Error)
2193 *
2194 */
lis2dw12_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)2195 int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
2196 {
2197 lis2dw12_tap_ths_x_t reg;
2198 int32_t ret;
2199
2200 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2201
2202 if (ret == 0)
2203 {
2204 reg.tap_thsx = val;
2205 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2206 }
2207
2208 return ret;
2209 }
2210
2211 /**
2212 * @brief Threshold for tap recognition.[get]
2213 *
2214 * @param ctx read / write interface definitions
2215 * @param val change the values of tap_thsx in reg TAP_THS_X
2216 * @retval interface status (MANDATORY: return 0 -> no Error)
2217 *
2218 */
lis2dw12_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2219 int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
2220 {
2221 lis2dw12_tap_ths_x_t reg;
2222 int32_t ret;
2223
2224 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2225 *val = reg.tap_thsx;
2226
2227 return ret;
2228 }
2229
2230 /**
2231 * @brief Threshold for tap recognition.[set]
2232 *
2233 * @param ctx read / write interface definitions
2234 * @param val change the values of tap_thsy in reg TAP_THS_Y
2235 * @retval interface status (MANDATORY: return 0 -> no Error)
2236 *
2237 */
lis2dw12_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)2238 int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
2239 {
2240 lis2dw12_tap_ths_y_t reg;
2241 int32_t ret;
2242
2243 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2244
2245 if (ret == 0)
2246 {
2247 reg.tap_thsy = val;
2248 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2249 }
2250
2251 return ret;
2252 }
2253
2254 /**
2255 * @brief Threshold for tap recognition.[get]
2256 *
2257 * @param ctx read / write interface definitions
2258 * @param val change the values of tap_thsy in reg TAP_THS_Y
2259 * @retval interface status (MANDATORY: return 0 -> no Error)
2260 *
2261 */
lis2dw12_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2262 int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
2263 {
2264 lis2dw12_tap_ths_y_t reg;
2265 int32_t ret;
2266
2267 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2268 *val = reg.tap_thsy;
2269
2270 return ret;
2271 }
2272
2273 /**
2274 * @brief Selection of axis priority for TAP detection.[set]
2275 *
2276 * @param ctx read / write interface definitions
2277 * @param val change the values of tap_prior in reg TAP_THS_Y
2278 * @retval interface status (MANDATORY: return 0 -> no Error)
2279 *
2280 */
lis2dw12_tap_axis_priority_set(const stmdev_ctx_t * ctx,lis2dw12_tap_prior_t val)2281 int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx,
2282 lis2dw12_tap_prior_t val)
2283 {
2284 lis2dw12_tap_ths_y_t reg;
2285 int32_t ret;
2286
2287 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2288
2289 if (ret == 0)
2290 {
2291 reg.tap_prior = (uint8_t) val;
2292 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2293 }
2294
2295 return ret;
2296 }
2297
2298 /**
2299 * @brief Selection of axis priority for TAP detection.[get]
2300 *
2301 * @param ctx read / write interface definitions
2302 * @param val Get the values of tap_prior in reg TAP_THS_Y
2303 * @retval interface status (MANDATORY: return 0 -> no Error)
2304 *
2305 */
lis2dw12_tap_axis_priority_get(const stmdev_ctx_t * ctx,lis2dw12_tap_prior_t * val)2306 int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx,
2307 lis2dw12_tap_prior_t *val)
2308 {
2309 lis2dw12_tap_ths_y_t reg;
2310 int32_t ret;
2311
2312 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Y, (uint8_t *) ®, 1);
2313
2314 switch (reg.tap_prior)
2315 {
2316 case LIS2DW12_XYZ:
2317 *val = LIS2DW12_XYZ;
2318 break;
2319
2320 case LIS2DW12_YXZ:
2321 *val = LIS2DW12_YXZ;
2322 break;
2323
2324 case LIS2DW12_XZY:
2325 *val = LIS2DW12_XZY;
2326 break;
2327
2328 case LIS2DW12_ZYX:
2329 *val = LIS2DW12_ZYX;
2330 break;
2331
2332 case LIS2DW12_YZX:
2333 *val = LIS2DW12_YZX;
2334 break;
2335
2336 case LIS2DW12_ZXY:
2337 *val = LIS2DW12_ZXY;
2338 break;
2339
2340 default:
2341 *val = LIS2DW12_XYZ;
2342 break;
2343 }
2344
2345 return ret;
2346 }
2347
2348 /**
2349 * @brief Threshold for tap recognition.[set]
2350 *
2351 * @param ctx read / write interface definitions
2352 * @param val change the values of tap_thsz in reg TAP_THS_Z
2353 * @retval interface status (MANDATORY: return 0 -> no Error)
2354 *
2355 */
lis2dw12_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)2356 int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
2357 {
2358 lis2dw12_tap_ths_z_t reg;
2359 int32_t ret;
2360
2361 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2362
2363 if (ret == 0)
2364 {
2365 reg.tap_thsz = val;
2366 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2367 }
2368
2369 return ret;
2370 }
2371
2372 /**
2373 * @brief Threshold for tap recognition.[get]
2374 *
2375 * @param ctx read / write interface definitions
2376 * @param val change the values of tap_thsz in reg TAP_THS_Z
2377 * @retval interface status (MANDATORY: return 0 -> no Error)
2378 *
2379 */
lis2dw12_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2380 int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
2381 {
2382 lis2dw12_tap_ths_z_t reg;
2383 int32_t ret;
2384
2385 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2386 *val = reg.tap_thsz;
2387
2388 return ret;
2389 }
2390
2391 /**
2392 * @brief Enable Z direction in tap recognition.[set]
2393 *
2394 * @param ctx read / write interface definitions
2395 * @param val change the values of tap_z_en in reg TAP_THS_Z
2396 * @retval interface status (MANDATORY: return 0 -> no Error)
2397 *
2398 */
lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)2399 int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
2400 uint8_t val)
2401 {
2402 lis2dw12_tap_ths_z_t reg;
2403 int32_t ret;
2404
2405 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2406
2407 if (ret == 0)
2408 {
2409 reg.tap_z_en = val;
2410 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2411 }
2412
2413 return ret;
2414 }
2415
2416 /**
2417 * @brief Enable Z direction in tap recognition.[get]
2418 *
2419 * @param ctx read / write interface definitions
2420 * @param val change the values of tap_z_en in reg TAP_THS_Z
2421 * @retval interface status (MANDATORY: return 0 -> no Error)
2422 *
2423 */
lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)2424 int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
2425 uint8_t *val)
2426 {
2427 lis2dw12_tap_ths_z_t reg;
2428 int32_t ret;
2429
2430 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2431 *val = reg.tap_z_en;
2432
2433 return ret;
2434 }
2435
2436 /**
2437 * @brief Enable Y direction in tap recognition.[set]
2438 *
2439 * @param ctx read / write interface definitions
2440 * @param val change the values of tap_y_en in reg TAP_THS_Z
2441 * @retval interface status (MANDATORY: return 0 -> no Error)
2442 *
2443 */
lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)2444 int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
2445 uint8_t val)
2446 {
2447 lis2dw12_tap_ths_z_t reg;
2448 int32_t ret;
2449
2450 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2451
2452 if (ret == 0)
2453 {
2454 reg.tap_y_en = val;
2455 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * @brief Enable Y direction in tap recognition.[get]
2463 *
2464 * @param ctx read / write interface definitions
2465 * @param val change the values of tap_y_en in reg TAP_THS_Z
2466 * @retval interface status (MANDATORY: return 0 -> no Error)
2467 *
2468 */
lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)2469 int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
2470 uint8_t *val)
2471 {
2472 lis2dw12_tap_ths_z_t reg;
2473 int32_t ret;
2474
2475 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2476 *val = reg.tap_y_en;
2477
2478 return ret;
2479 }
2480
2481 /**
2482 * @brief Enable X direction in tap recognition.[set]
2483 *
2484 * @param ctx read / write interface definitions
2485 * @param val change the values of tap_x_en in reg TAP_THS_Z
2486 * @retval interface status (MANDATORY: return 0 -> no Error)
2487 *
2488 */
lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)2489 int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
2490 uint8_t val)
2491 {
2492 lis2dw12_tap_ths_z_t reg;
2493 int32_t ret;
2494
2495 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2496
2497 if (ret == 0)
2498 {
2499 reg.tap_x_en = val;
2500 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2501 }
2502
2503 return ret;
2504 }
2505
2506 /**
2507 * @brief Enable X direction in tap recognition.[get]
2508 *
2509 * @param ctx read / write interface definitions
2510 * @param val change the values of tap_x_en in reg TAP_THS_Z
2511 * @retval interface status (MANDATORY: return 0 -> no Error)
2512 *
2513 */
lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)2514 int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
2515 uint8_t *val)
2516 {
2517 lis2dw12_tap_ths_z_t reg;
2518 int32_t ret;
2519
2520 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_Z, (uint8_t *) ®, 1);
2521 *val = reg.tap_x_en;
2522
2523 return ret;
2524 }
2525
2526 /**
2527 * @brief Maximum duration is the maximum time of an overthreshold signal
2528 * detection to be recognized as a tap event. The default value
2529 * of these bits is 00b which corresponds to 4*ODR_XL time.
2530 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2531 * corresponds to 8*ODR_XL time.[set]
2532 *
2533 * @param ctx read / write interface definitions
2534 * @param val change the values of shock in reg INT_DUR
2535 * @retval interface status (MANDATORY: return 0 -> no Error)
2536 *
2537 */
lis2dw12_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)2538 int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
2539 {
2540 lis2dw12_int_dur_t reg;
2541 int32_t ret;
2542
2543 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2544
2545 if (ret == 0)
2546 {
2547 reg.shock = val;
2548 ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2549 }
2550
2551 return ret;
2552 }
2553
2554 /**
2555 * @brief Maximum duration is the maximum time of an overthreshold signal
2556 * detection to be recognized as a tap event. The default value
2557 * of these bits is 00b which corresponds to 4*ODR_XL time.
2558 * If the SHOCK[1:0] bits are set to a different value, 1LSB
2559 * corresponds to 8*ODR_XL time.[get]
2560 *
2561 * @param ctx read / write interface definitions
2562 * @param val change the values of shock in reg INT_DUR
2563 * @retval interface status (MANDATORY: return 0 -> no Error)
2564 *
2565 */
lis2dw12_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)2566 int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
2567 {
2568 lis2dw12_int_dur_t reg;
2569 int32_t ret;
2570
2571 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2572 *val = reg.shock;
2573
2574 return ret;
2575 }
2576
2577 /**
2578 * @brief Quiet time is the time after the first detected tap in which
2579 * there must not be any overthreshold event.
2580 * The default value of these bits is 00b which corresponds
2581 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2582 * value, 1LSB corresponds to 4*ODR_XL time.[set]
2583 *
2584 * @param ctx read / write interface definitions
2585 * @param val change the values of quiet in reg INT_DUR
2586 * @retval interface status (MANDATORY: return 0 -> no Error)
2587 *
2588 */
lis2dw12_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)2589 int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
2590 {
2591 lis2dw12_int_dur_t reg;
2592 int32_t ret;
2593
2594 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2595
2596 if (ret == 0)
2597 {
2598 reg.quiet = val;
2599 ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2600 }
2601
2602 return ret;
2603 }
2604
2605 /**
2606 * @brief Quiet time is the time after the first detected tap in which
2607 * there must not be any overthreshold event.
2608 * The default value of these bits is 00b which corresponds
2609 * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
2610 * value, 1LSB corresponds to 4*ODR_XL time.[get]
2611 *
2612 * @param ctx read / write interface definitions
2613 * @param val change the values of quiet in reg INT_DUR
2614 * @retval interface status (MANDATORY: return 0 -> no Error)
2615 *
2616 */
lis2dw12_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)2617 int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
2618 {
2619 lis2dw12_int_dur_t reg;
2620 int32_t ret;
2621
2622 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2623 *val = reg.quiet;
2624
2625 return ret;
2626 }
2627
2628 /**
2629 * @brief When double tap recognition is enabled, this register expresses
2630 * the maximum time between two consecutive detected taps to
2631 * determine a double tap event.
2632 * The default value of these bits is 0000b which corresponds
2633 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2634 * value, 1LSB corresponds to 32*ODR_XL time.[set]
2635 *
2636 * @param ctx read / write interface definitions
2637 * @param val change the values of latency in reg INT_DUR
2638 * @retval interface status (MANDATORY: return 0 -> no Error)
2639 *
2640 */
lis2dw12_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2641 int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2642 {
2643 lis2dw12_int_dur_t reg;
2644 int32_t ret;
2645
2646 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2647
2648 if (ret == 0)
2649 {
2650 reg.latency = val;
2651 ret = lis2dw12_write_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2652 }
2653
2654 return ret;
2655 }
2656
2657 /**
2658 * @brief When double tap recognition is enabled, this register expresses
2659 * the maximum time between two consecutive detected taps to
2660 * determine a double tap event.
2661 * The default value of these bits is 0000b which corresponds
2662 * to 16*ODR_XL time. If the DUR[3:0] bits are set to a different
2663 * value, 1LSB corresponds to 32*ODR_XL time.[get]
2664 *
2665 * @param ctx read / write interface definitions
2666 * @param val change the values of latency in reg INT_DUR
2667 * @retval interface status (MANDATORY: return 0 -> no Error)
2668 *
2669 */
lis2dw12_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2670 int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2671 {
2672 lis2dw12_int_dur_t reg;
2673 int32_t ret;
2674
2675 ret = lis2dw12_read_reg(ctx, LIS2DW12_INT_DUR, (uint8_t *) ®, 1);
2676 *val = reg.latency;
2677
2678 return ret;
2679 }
2680
2681 /**
2682 * @brief Single/double-tap event enable.[set]
2683 *
2684 * @param ctx read / write interface definitions
2685 * @param val change the values of single_double_tap in reg WAKE_UP_THS
2686 * @retval interface status (MANDATORY: return 0 -> no Error)
2687 *
2688 */
lis2dw12_tap_mode_set(const stmdev_ctx_t * ctx,lis2dw12_single_double_tap_t val)2689 int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx,
2690 lis2dw12_single_double_tap_t val)
2691 {
2692 lis2dw12_wake_up_ths_t reg;
2693 int32_t ret;
2694
2695 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
2696
2697 if (ret == 0)
2698 {
2699 reg.single_double_tap = (uint8_t) val;
2700 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
2701 }
2702
2703 return ret;
2704 }
2705
2706 /**
2707 * @brief Single/double-tap event enable.[get]
2708 *
2709 * @param ctx read / write interface definitions
2710 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
2711 * @retval interface status (MANDATORY: return 0 -> no Error)
2712 *
2713 */
lis2dw12_tap_mode_get(const stmdev_ctx_t * ctx,lis2dw12_single_double_tap_t * val)2714 int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx,
2715 lis2dw12_single_double_tap_t *val)
2716 {
2717 lis2dw12_wake_up_ths_t reg;
2718 int32_t ret;
2719
2720 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
2721
2722 switch (reg.single_double_tap)
2723 {
2724 case LIS2DW12_ONLY_SINGLE:
2725 *val = LIS2DW12_ONLY_SINGLE;
2726 break;
2727
2728 case LIS2DW12_BOTH_SINGLE_DOUBLE:
2729 *val = LIS2DW12_BOTH_SINGLE_DOUBLE;
2730 break;
2731
2732 default:
2733 *val = LIS2DW12_ONLY_SINGLE;
2734 break;
2735 }
2736
2737 return ret;
2738 }
2739
2740 /**
2741 * @brief Read the tap / double tap source register.[get]
2742 *
2743 * @param ctx read / write interface definitions
2744 * @param lis2dw12_tap_src: union of registers from TAP_SRC to
2745 * @retval interface status (MANDATORY: return 0 -> no Error)
2746 *
2747 */
lis2dw12_tap_src_get(const stmdev_ctx_t * ctx,lis2dw12_tap_src_t * val)2748 int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx,
2749 lis2dw12_tap_src_t *val)
2750 {
2751 int32_t ret;
2752
2753 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_SRC, (uint8_t *) val, 1);
2754
2755 return ret;
2756 }
2757
2758 /**
2759 * @}
2760 *
2761 */
2762
2763 /**
2764 * @defgroup LIS2DW12_Six_Position_Detection(6D/4D)
2765 * @brief This section groups all the functions concerning six
2766 * position detection (6D).
2767 * @{
2768 *
2769 */
2770
2771 /**
2772 * @brief Threshold for 4D/6D function.[set]
2773 *
2774 * @param ctx read / write interface definitions
2775 * @param val change the values of 6d_ths in reg TAP_THS_X
2776 * @retval interface status (MANDATORY: return 0 -> no Error)
2777 *
2778 */
lis2dw12_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2779 int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2780 {
2781 lis2dw12_tap_ths_x_t reg;
2782 int32_t ret;
2783
2784 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2785
2786 if (ret == 0)
2787 {
2788 reg._6d_ths = val;
2789 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2790 }
2791
2792 return ret;
2793 }
2794
2795 /**
2796 * @brief Threshold for 4D/6D function.[get]
2797 *
2798 * @param ctx read / write interface definitions
2799 * @param val change the values of 6d_ths in reg TAP_THS_X
2800 * @retval interface status (MANDATORY: return 0 -> no Error)
2801 *
2802 */
lis2dw12_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2803 int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2804 {
2805 lis2dw12_tap_ths_x_t reg;
2806 int32_t ret;
2807
2808 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2809 *val = reg._6d_ths;
2810
2811 return ret;
2812 }
2813
2814 /**
2815 * @brief 4D orientation detection enable.[set]
2816 *
2817 * @param ctx read / write interface definitions
2818 * @param val change the values of 4d_en in reg TAP_THS_X
2819 * @retval interface status (MANDATORY: return 0 -> no Error)
2820 *
2821 */
lis2dw12_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2822 int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2823 {
2824 lis2dw12_tap_ths_x_t reg;
2825 int32_t ret;
2826
2827 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2828
2829 if (ret == 0)
2830 {
2831 reg._4d_en = val;
2832 ret = lis2dw12_write_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2833 }
2834
2835 return ret;
2836 }
2837
2838 /**
2839 * @brief 4D orientation detection enable.[get]
2840 *
2841 * @param ctx read / write interface definitions
2842 * @param val change the values of 4d_en in reg TAP_THS_X
2843 * @retval interface status (MANDATORY: return 0 -> no Error)
2844 *
2845 */
lis2dw12_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2846 int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2847 {
2848 lis2dw12_tap_ths_x_t reg;
2849 int32_t ret;
2850
2851 ret = lis2dw12_read_reg(ctx, LIS2DW12_TAP_THS_X, (uint8_t *) ®, 1);
2852 *val = reg._4d_en;
2853
2854 return ret;
2855 }
2856
2857 /**
2858 * @brief Read the 6D tap source register.[get]
2859 *
2860 * @param ctx read / write interface definitions
2861 * @param val union of registers from SIXD_SRC
2862 * @retval interface status (MANDATORY: return 0 -> no Error)
2863 *
2864 */
lis2dw12_6d_src_get(const stmdev_ctx_t * ctx,lis2dw12_sixd_src_t * val)2865 int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx,
2866 lis2dw12_sixd_src_t *val)
2867 {
2868 int32_t ret;
2869
2870 ret = lis2dw12_read_reg(ctx, LIS2DW12_SIXD_SRC, (uint8_t *) val, 1);
2871
2872 return ret;
2873 }
2874 /**
2875 * @brief Data sent to 6D interrupt function.[set]
2876 *
2877 * @param ctx read / write interface definitions
2878 * @param val change the values of lpass_on6d in reg CTRL_REG7
2879 * @retval interface status (MANDATORY: return 0 -> no Error)
2880 *
2881 */
lis2dw12_6d_feed_data_set(const stmdev_ctx_t * ctx,lis2dw12_lpass_on6d_t val)2882 int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx,
2883 lis2dw12_lpass_on6d_t val)
2884 {
2885 lis2dw12_ctrl_reg7_t reg;
2886 int32_t ret;
2887
2888 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
2889
2890 if (ret == 0)
2891 {
2892 reg.lpass_on6d = (uint8_t) val;
2893 ret = lis2dw12_write_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
2894 }
2895
2896 return ret;
2897 }
2898
2899 /**
2900 * @brief Data sent to 6D interrupt function.[get]
2901 *
2902 * @param ctx read / write interface definitions
2903 * @param val Get the values of lpass_on6d in reg CTRL_REG7
2904 * @retval interface status (MANDATORY: return 0 -> no Error)
2905 *
2906 */
lis2dw12_6d_feed_data_get(const stmdev_ctx_t * ctx,lis2dw12_lpass_on6d_t * val)2907 int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx,
2908 lis2dw12_lpass_on6d_t *val)
2909 {
2910 lis2dw12_ctrl_reg7_t reg;
2911 int32_t ret;
2912
2913 ret = lis2dw12_read_reg(ctx, LIS2DW12_CTRL_REG7, (uint8_t *) ®, 1);
2914
2915 switch (reg.lpass_on6d)
2916 {
2917 case LIS2DW12_ODR_DIV_2_FEED:
2918 *val = LIS2DW12_ODR_DIV_2_FEED;
2919 break;
2920
2921 case LIS2DW12_LPF2_FEED:
2922 *val = LIS2DW12_LPF2_FEED;
2923 break;
2924
2925 default:
2926 *val = LIS2DW12_ODR_DIV_2_FEED;
2927 break;
2928 }
2929
2930 return ret;
2931 }
2932
2933 /**
2934 * @}
2935 *
2936 */
2937
2938 /**
2939 * @defgroup LIS2DW12_Free_Fall
2940 * @brief This section group all the functions concerning
2941 * the free fall detection.
2942 * @{
2943 *
2944 */
2945
2946 /**
2947 * @brief Free fall duration event(1LSb = 1 / ODR).[set]
2948 *
2949 * @param ctx read / write interface definitions
2950 * @param val change the values of ff_dur in reg
2951 * WAKE_UP_DUR /F REE_FALL
2952 * @retval interface status (MANDATORY: return 0 -> no Error)
2953 *
2954 */
lis2dw12_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2955 int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2956 {
2957 lis2dw12_wake_up_dur_t wake_up_dur;
2958 lis2dw12_free_fall_t free_fall;
2959 int32_t ret;
2960
2961 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
2962 (uint8_t *) &wake_up_dur, 1);
2963
2964 if (ret == 0)
2965 {
2966 ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
2967 (uint8_t *) &free_fall, 1);
2968 }
2969
2970 if (ret == 0)
2971 {
2972 wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
2973 free_fall.ff_dur = (uint8_t) val & 0x1FU;
2974 ret = lis2dw12_write_reg(ctx, LIS2DW12_WAKE_UP_DUR,
2975 (uint8_t *) &wake_up_dur, 1);
2976 }
2977
2978 if (ret == 0)
2979 {
2980 ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL,
2981 (uint8_t *) &free_fall, 1);
2982 }
2983
2984 return ret;
2985 }
2986
2987 /**
2988 * @brief Free fall duration event(1LSb = 1 / ODR).[get]
2989 *
2990 * @param ctx read / write interface definitions
2991 * @param val change the values of ff_dur in
2992 * reg WAKE_UP_DUR /F REE_FALL
2993 * @retval interface status (MANDATORY: return 0 -> no Error)
2994 *
2995 */
lis2dw12_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2996 int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2997 {
2998 lis2dw12_wake_up_dur_t wake_up_dur;
2999 lis2dw12_free_fall_t free_fall;
3000 int32_t ret;
3001
3002 ret = lis2dw12_read_reg(ctx, LIS2DW12_WAKE_UP_DUR,
3003 (uint8_t *) &wake_up_dur, 1);
3004
3005 if (ret == 0)
3006 {
3007 ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL,
3008 (uint8_t *) &free_fall, 1);
3009 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
3010 }
3011
3012 return ret;
3013 }
3014
3015 /**
3016 * @brief Free fall threshold setting.[set]
3017 *
3018 * @param ctx read / write interface definitions
3019 * @param val change the values of ff_ths in reg FREE_FALL
3020 * @retval interface status (MANDATORY: return 0 -> no Error)
3021 *
3022 */
lis2dw12_ff_threshold_set(const stmdev_ctx_t * ctx,lis2dw12_ff_ths_t val)3023 int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx,
3024 lis2dw12_ff_ths_t val)
3025 {
3026 lis2dw12_free_fall_t reg;
3027 int32_t ret;
3028
3029 ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
3030
3031 if (ret == 0)
3032 {
3033 reg.ff_ths = (uint8_t) val;
3034 ret = lis2dw12_write_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
3035 }
3036
3037 return ret;
3038 }
3039
3040 /**
3041 * @brief Free fall threshold setting.[get]
3042 *
3043 * @param ctx read / write interface definitions
3044 * @param val Get the values of ff_ths in reg FREE_FALL
3045 * @retval interface status (MANDATORY: return 0 -> no Error)
3046 *
3047 */
lis2dw12_ff_threshold_get(const stmdev_ctx_t * ctx,lis2dw12_ff_ths_t * val)3048 int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx,
3049 lis2dw12_ff_ths_t *val)
3050 {
3051 lis2dw12_free_fall_t reg;
3052 int32_t ret;
3053
3054 ret = lis2dw12_read_reg(ctx, LIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
3055
3056 switch (reg.ff_ths)
3057 {
3058 case LIS2DW12_FF_TSH_5LSb_FS2g:
3059 *val = LIS2DW12_FF_TSH_5LSb_FS2g;
3060 break;
3061
3062 case LIS2DW12_FF_TSH_7LSb_FS2g:
3063 *val = LIS2DW12_FF_TSH_7LSb_FS2g;
3064 break;
3065
3066 case LIS2DW12_FF_TSH_8LSb_FS2g:
3067 *val = LIS2DW12_FF_TSH_8LSb_FS2g;
3068 break;
3069
3070 case LIS2DW12_FF_TSH_10LSb_FS2g:
3071 *val = LIS2DW12_FF_TSH_10LSb_FS2g;
3072 break;
3073
3074 case LIS2DW12_FF_TSH_11LSb_FS2g:
3075 *val = LIS2DW12_FF_TSH_11LSb_FS2g;
3076 break;
3077
3078 case LIS2DW12_FF_TSH_13LSb_FS2g:
3079 *val = LIS2DW12_FF_TSH_13LSb_FS2g;
3080 break;
3081
3082 case LIS2DW12_FF_TSH_15LSb_FS2g:
3083 *val = LIS2DW12_FF_TSH_15LSb_FS2g;
3084 break;
3085
3086 case LIS2DW12_FF_TSH_16LSb_FS2g:
3087 *val = LIS2DW12_FF_TSH_16LSb_FS2g;
3088 break;
3089
3090 default:
3091 *val = LIS2DW12_FF_TSH_5LSb_FS2g;
3092 break;
3093 }
3094
3095 return ret;
3096 }
3097
3098 /**
3099 * @}
3100 *
3101 */
3102
3103 /**
3104 * @defgroup LIS2DW12_Fifo
3105 * @brief This section group all the functions concerning the fifo usage
3106 * @{
3107 *
3108 */
3109
3110 /**
3111 * @brief FIFO watermark level selection.[set]
3112 *
3113 * @param ctx read / write interface definitions
3114 * @param val change the values of fth in reg FIFO_CTRL
3115 * @retval interface status (MANDATORY: return 0 -> no Error)
3116 *
3117 */
lis2dw12_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3118 int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3119 {
3120 lis2dw12_fifo_ctrl_t reg;
3121 int32_t ret;
3122
3123 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3124
3125 if (ret == 0)
3126 {
3127 reg.fth = val;
3128 ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3129 }
3130
3131 return ret;
3132 }
3133
3134 /**
3135 * @brief FIFO watermark level selection.[get]
3136 *
3137 * @param ctx read / write interface definitions
3138 * @param val change the values of fth in reg FIFO_CTRL
3139 * @retval interface status (MANDATORY: return 0 -> no Error)
3140 *
3141 */
lis2dw12_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3142 int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3143 {
3144 lis2dw12_fifo_ctrl_t reg;
3145 int32_t ret;
3146
3147 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3148 *val = reg.fth;
3149
3150 return ret;
3151 }
3152
3153 /**
3154 * @brief FIFO mode selection.[set]
3155 *
3156 * @param ctx read / write interface definitions
3157 * @param val change the values of fmode in reg FIFO_CTRL
3158 * @retval interface status (MANDATORY: return 0 -> no Error)
3159 *
3160 */
lis2dw12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2dw12_fmode_t val)3161 int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx,
3162 lis2dw12_fmode_t val)
3163 {
3164 lis2dw12_fifo_ctrl_t reg;
3165 int32_t ret;
3166
3167 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3168
3169 if (ret == 0)
3170 {
3171 reg.fmode = (uint8_t) val;
3172 ret = lis2dw12_write_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3173 }
3174
3175 return ret;
3176 }
3177
3178 /**
3179 * @brief FIFO mode selection.[get]
3180 *
3181 * @param ctx read / write interface definitions
3182 * @param val Get the values of fmode in reg FIFO_CTRL
3183 * @retval interface status (MANDATORY: return 0 -> no Error)
3184 *
3185 */
lis2dw12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2dw12_fmode_t * val)3186 int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx,
3187 lis2dw12_fmode_t *val)
3188 {
3189 lis2dw12_fifo_ctrl_t reg;
3190 int32_t ret;
3191
3192 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
3193
3194 switch (reg.fmode)
3195 {
3196 case LIS2DW12_BYPASS_MODE:
3197 *val = LIS2DW12_BYPASS_MODE;
3198 break;
3199
3200 case LIS2DW12_FIFO_MODE:
3201 *val = LIS2DW12_FIFO_MODE;
3202 break;
3203
3204 case LIS2DW12_STREAM_TO_FIFO_MODE:
3205 *val = LIS2DW12_STREAM_TO_FIFO_MODE;
3206 break;
3207
3208 case LIS2DW12_BYPASS_TO_STREAM_MODE:
3209 *val = LIS2DW12_BYPASS_TO_STREAM_MODE;
3210 break;
3211
3212 case LIS2DW12_STREAM_MODE:
3213 *val = LIS2DW12_STREAM_MODE;
3214 break;
3215
3216 default:
3217 *val = LIS2DW12_BYPASS_MODE;
3218 break;
3219 }
3220
3221 return ret;
3222 }
3223
3224 /**
3225 * @brief Number of unread samples stored in FIFO.[get]
3226 *
3227 * @param ctx read / write interface definitions
3228 * @param val change the values of diff in reg FIFO_SAMPLES
3229 * @retval interface status (MANDATORY: return 0 -> no Error)
3230 *
3231 */
lis2dw12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)3232 int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
3233 {
3234 lis2dw12_fifo_samples_t reg;
3235 int32_t ret;
3236
3237 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
3238 *val = reg.diff;
3239
3240 return ret;
3241 }
3242 /**
3243 * @brief FIFO overrun status.[get]
3244 *
3245 * @param ctx read / write interface definitions
3246 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
3247 * @retval interface status (MANDATORY: return 0 -> no Error)
3248 *
3249 */
lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3250 int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3251 {
3252 lis2dw12_fifo_samples_t reg;
3253 int32_t ret;
3254
3255 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
3256 *val = reg.fifo_ovr;
3257
3258 return ret;
3259 }
3260 /**
3261 * @brief FIFO threshold status flag.[get]
3262 *
3263 * @param ctx read / write interface definitions
3264 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
3265 * @retval interface status (MANDATORY: return 0 -> no Error)
3266 *
3267 */
lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3268 int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
3269 {
3270 lis2dw12_fifo_samples_t reg;
3271 int32_t ret;
3272
3273 ret = lis2dw12_read_reg(ctx, LIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
3274 *val = reg.fifo_fth;
3275
3276 return ret;
3277 }
3278
3279 /**
3280 * @}
3281 *
3282 */
3283
3284 /**
3285 * @}
3286 *
3287 */
3288
3289 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3290
