1 /*
2 ******************************************************************************
3 * @file lis2dux12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DUX12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2dux12_reg.h"
21
22 /**
23 * @defgroup LIS2DUX12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2dux12 sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DUX12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2dux12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2dux12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 if (ctx == NULL)
53 {
54 return -1;
55 }
56
57 return ctx->read_reg(ctx->handle, reg, data, len);
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lis2dux12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lis2dux12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
71 uint16_t len)
72 {
73 if (ctx == NULL)
74 {
75 return -1;
76 }
77
78 return ctx->write_reg(ctx->handle, reg, data, len);
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LIS2DUX12_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lis2dux12_from_fs2g_to_mg(int16_t lsb)93 float_t lis2dux12_from_fs2g_to_mg(int16_t lsb)
94 {
95 return (float_t)lsb * 0.061f;
96 }
97
lis2dux12_from_fs4g_to_mg(int16_t lsb)98 float_t lis2dux12_from_fs4g_to_mg(int16_t lsb)
99 {
100 return (float_t)lsb * 0.122f;
101 }
102
lis2dux12_from_fs8g_to_mg(int16_t lsb)103 float_t lis2dux12_from_fs8g_to_mg(int16_t lsb)
104 {
105 return (float_t)lsb * 0.244f;
106 }
107
lis2dux12_from_fs16g_to_mg(int16_t lsb)108 float_t lis2dux12_from_fs16g_to_mg(int16_t lsb)
109 {
110 return (float_t)lsb * 0.488f;
111 }
112
lis2dux12_from_lsb_to_celsius(int16_t lsb)113 float_t lis2dux12_from_lsb_to_celsius(int16_t lsb)
114 {
115 return ((float_t)lsb / 355.5f) + 25.0f;
116 }
117
118 /**
119 * @}
120 *
121 */
122
123 /**
124 * @defgroup Common
125 * @brief Common
126 * @{/
127 *
128 */
129 /**
130 * @brief Device ID.[get]
131 *
132 * @param ctx read / write interface definitions
133 * @param val Device ID.
134 * @retval interface status (MANDATORY: return 0 -> no Error)
135 *
136 */
lis2dux12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)137 int32_t lis2dux12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
138 {
139 int32_t ret;
140
141 ret = lis2dux12_read_reg(ctx, LIS2DUX12_WHO_AM_I, val, 1);
142
143 return ret;
144 }
145
146 /**
147 * @brief Configures the bus operating mode.[get]
148 *
149 * @param ctx communication interface handler.(ptr)
150 * @param val configures the bus operating mode.(ptr)
151 * @retval interface status (MANDATORY: return 0 -> no Error)
152 *
153 */
lis2dux12_init_set(const stmdev_ctx_t * ctx,lis2dux12_init_t val)154 int32_t lis2dux12_init_set(const stmdev_ctx_t *ctx, lis2dux12_init_t val)
155 {
156 lis2dux12_ctrl1_t ctrl1;
157 lis2dux12_ctrl4_t ctrl4;
158 lis2dux12_status_t status;
159 uint8_t cnt = 0;
160 int32_t ret = 0;
161
162 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
163 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
164 switch (val)
165 {
166 case LIS2DUX12_BOOT:
167 ctrl4.boot = PROPERTY_ENABLE;
168 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
169 if (ret != 0)
170 {
171 break;
172 }
173
174 do
175 {
176 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
177 if (ret != 0)
178 {
179 break;
180 }
181
182 /* boot procedure ended correctly */
183 if (ctrl4.boot == 0U)
184 {
185 break;
186 }
187
188 if (ctx->mdelay != NULL)
189 {
190 ctx->mdelay(25); /* 25 ms of boot time */
191 }
192 } while (cnt++ < 5U);
193
194 if (cnt >= 5U)
195 {
196 ret = -1; /* boot procedure failed */
197 }
198 break;
199 case LIS2DUX12_RESET:
200 ctrl1.sw_reset = PROPERTY_ENABLE;
201 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
202 if (ret != 0)
203 {
204 break;
205 }
206
207 do
208 {
209 ret = lis2dux12_status_get(ctx, &status);
210 if (ret != 0)
211 {
212 break;
213 }
214
215 /* sw-reset procedure ended correctly */
216 if (status.sw_reset == 0U)
217 {
218 break;
219 }
220
221 if (ctx->mdelay != NULL)
222 {
223 ctx->mdelay(1); /* should be 50 us */
224 }
225 } while (cnt++ < 5U);
226
227 if (cnt >= 5U)
228 {
229 ret = -1; /* sw-reset procedure failed */
230 }
231 break;
232 case LIS2DUX12_SENSOR_ONLY_ON:
233 /* no embedded funcs are used */
234 ctrl4.emb_func_en = PROPERTY_DISABLE;
235 ctrl4.bdu = PROPERTY_ENABLE;
236 ctrl1.if_add_inc = PROPERTY_ENABLE;
237 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
238 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
239 break;
240 case LIS2DUX12_SENSOR_EMB_FUNC_ON:
241 /* complete configuration is used */
242 ctrl4.emb_func_en = PROPERTY_ENABLE;
243 ctrl4.bdu = PROPERTY_ENABLE;
244 ctrl1.if_add_inc = PROPERTY_ENABLE;
245 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
246 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
247 break;
248 default:
249 ctrl1.sw_reset = PROPERTY_ENABLE;
250 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
251 break;
252 }
253 return ret;
254 }
255
256 /**
257 * @brief Get the status of the device.[get]
258 *
259 * @param ctx communication interface handler.(ptr)
260 * @param val the status of the device.(ptr)
261 * @retval interface status (MANDATORY: return 0 -> no Error)
262 *
263 */
lis2dux12_status_get(const stmdev_ctx_t * ctx,lis2dux12_status_t * val)264 int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val)
265 {
266 lis2dux12_status_register_t status_register;
267 lis2dux12_ctrl1_t ctrl1;
268 lis2dux12_ctrl4_t ctrl4;
269 int32_t ret;
270
271 ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS,
272 (uint8_t *)&status_register, 1);
273 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
274 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
275
276 val->sw_reset = ctrl1.sw_reset;
277 val->boot = ctrl4.boot;
278 val->drdy = status_register.drdy;
279
280 return ret;
281 }
282
283 /**
284 * @brief Get the status of the embedded funcs.[get]
285 *
286 * @param ctx communication interface handler.(ptr)
287 * @param val the status of the embedded funcs.(ptr)
288 * @retval interface status (MANDATORY: return 0 -> no Error)
289 *
290 */
lis2dux12_embedded_status_get(const stmdev_ctx_t * ctx,lis2dux12_embedded_status_t * val)291 int32_t lis2dux12_embedded_status_get(const stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val)
292 {
293 lis2dux12_emb_func_status_t status;
294 int32_t ret;
295
296 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
297 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, (uint8_t *)&status, 1);
298 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
299
300 val->is_step_det = status.is_step_det;
301 val->is_tilt = status.is_tilt;
302 val->is_sigmot = status.is_sigmot;
303
304 return ret;
305 }
306
307 /**
308 * @brief Enables pulsed data-ready mode (~75 us).[set]
309 *
310 * @param ctx read / write interface definitions
311 * @param val DRDY_LATCHED, DRDY_PULSED,
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
lis2dux12_data_ready_mode_set(const stmdev_ctx_t * ctx,lis2dux12_data_ready_mode_t val)315 int32_t lis2dux12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val)
316 {
317 lis2dux12_ctrl1_t ctrl1;
318 int32_t ret;
319
320 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
321
322 if (ret == 0)
323 {
324 ctrl1.drdy_pulsed = ((uint8_t)val & 0x1U);
325 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
326 }
327
328 return ret;
329 }
330
331 /**
332 * @brief Enables pulsed data-ready mode (~75 us).[get]
333 *
334 * @param ctx read / write interface definitions
335 * @param val DRDY_LATCHED, DRDY_PULSED,
336 * @retval interface status (MANDATORY: return 0 -> no Error)
337 *
338 */
lis2dux12_data_ready_mode_get(const stmdev_ctx_t * ctx,lis2dux12_data_ready_mode_t * val)339 int32_t lis2dux12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val)
340 {
341 lis2dux12_ctrl1_t ctrl1;
342 int32_t ret;
343
344 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
345
346 switch ((ctrl1.drdy_pulsed))
347 {
348 case 0x0:
349 *val = LIS2DUX12_DRDY_LATCHED;
350 break;
351
352 case 0x1:
353 *val = LIS2DUX12_DRDY_PULSED;
354 break;
355
356 default:
357 *val = LIS2DUX12_DRDY_LATCHED;
358 break;
359 }
360 return ret;
361 }
362
363 /**
364 * @brief Sensor mode.[set]
365 *
366 * @param ctx communication interface handler.(ptr)
367 * @param val set the sensor FS and ODR.(ptr)
368 * @retval interface status (MANDATORY: return 0 -> no Error)
369 *
370 */
lis2dux12_mode_set(const stmdev_ctx_t * ctx,const lis2dux12_md_t * val)371 int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val)
372 {
373 lis2dux12_ctrl3_t ctrl3;
374 lis2dux12_ctrl5_t ctrl5;
375 int32_t ret;
376
377 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1);
378
379 ctrl5.odr = (uint8_t)val->odr & 0xFU;
380 ctrl5.fs = (uint8_t)val->fs;
381
382 /* set the bandwidth */
383 switch (val->odr)
384 {
385 /* no anti-aliasing filter present */
386 case LIS2DUX12_OFF:
387 case LIS2DUX12_1Hz6_ULP:
388 case LIS2DUX12_3Hz_ULP:
389 case LIS2DUX12_25Hz_ULP:
390 ctrl5.bw = 0x0;
391 break;
392
393 /* low-power mode with ODR < 50 Hz */
394 case LIS2DUX12_6Hz_LP:
395 switch (val->bw)
396 {
397 default:
398 case LIS2DUX12_ODR_div_2:
399 case LIS2DUX12_ODR_div_4:
400 case LIS2DUX12_ODR_div_8:
401 /* value not allowed */
402 ret = -1;
403 break;
404 case LIS2DUX12_ODR_div_16:
405 ctrl5.bw = 0x3;
406 break;
407 }
408 break;
409 case LIS2DUX12_12Hz5_LP:
410 switch (val->bw)
411 {
412 default:
413 case LIS2DUX12_ODR_div_2:
414 case LIS2DUX12_ODR_div_4:
415 /* value not allowed */
416 ret = -1;
417 break;
418 case LIS2DUX12_ODR_div_8:
419 ctrl5.bw = 0x2;
420 break;
421 case LIS2DUX12_ODR_div_16:
422 ctrl5.bw = 0x3;
423 break;
424 }
425 break;
426 case LIS2DUX12_25Hz_LP:
427 switch (val->bw)
428 {
429 default:
430 case LIS2DUX12_ODR_div_2:
431 /* value not allowed */
432 ret = -1;
433 break;
434 case LIS2DUX12_ODR_div_4:
435 ctrl5.bw = 0x1;
436 break;
437 case LIS2DUX12_ODR_div_8:
438 ctrl5.bw = 0x2;
439 break;
440 case LIS2DUX12_ODR_div_16:
441 ctrl5.bw = 0x3;
442 break;
443 }
444 break;
445
446 /* standard cases */
447 case LIS2DUX12_50Hz_LP:
448 case LIS2DUX12_100Hz_LP:
449 case LIS2DUX12_200Hz_LP:
450 case LIS2DUX12_400Hz_LP:
451 case LIS2DUX12_800Hz_LP:
452 case LIS2DUX12_TRIG_PIN:
453 case LIS2DUX12_TRIG_SW:
454 case LIS2DUX12_6Hz_HP:
455 case LIS2DUX12_12Hz5_HP:
456 case LIS2DUX12_25Hz_HP:
457 case LIS2DUX12_50Hz_HP:
458 case LIS2DUX12_100Hz_HP:
459 case LIS2DUX12_200Hz_HP:
460 case LIS2DUX12_400Hz_HP:
461 case LIS2DUX12_800Hz_HP:
462 default:
463 ctrl5.bw = (uint8_t)val->bw;
464 break;
465 }
466
467 if (ret != 0)
468 {
469 return ret;
470 }
471
472 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
473
474 ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U;
475
476 if (ret == 0)
477 {
478 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1);
479 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
480 }
481
482 return ret;
483 }
484
485 /**
486 * @brief Sensor mode.[get]
487 *
488 * @param ctx communication interface handler.(ptr)
489 * @param val get the sensor FS and ODR.(ptr)
490 * @retval interface status (MANDATORY: return 0 -> no Error)
491 *
492 */
lis2dux12_mode_get(const stmdev_ctx_t * ctx,lis2dux12_md_t * val)493 int32_t lis2dux12_mode_get(const stmdev_ctx_t *ctx, lis2dux12_md_t *val)
494 {
495 lis2dux12_ctrl3_t ctrl3;
496 lis2dux12_ctrl5_t ctrl5;
497 int32_t ret;
498
499 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1);
500 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
501
502 switch (ctrl5.odr)
503 {
504 case 0x00:
505 val->odr = LIS2DUX12_OFF;
506 break;
507 case 0x01:
508 val->odr = LIS2DUX12_1Hz6_ULP;
509 break;
510 case 0x02:
511 val->odr = LIS2DUX12_3Hz_ULP;
512 break;
513 case 0x03:
514 val->odr = LIS2DUX12_25Hz_ULP;
515 break;
516 case 0x04:
517 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_6Hz_HP : LIS2DUX12_6Hz_LP;
518 break;
519 case 0x05:
520 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_12Hz5_HP : LIS2DUX12_12Hz5_LP;
521 break;
522 case 0x06:
523 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_25Hz_HP : LIS2DUX12_25Hz_LP;
524 break;
525 case 0x07:
526 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_50Hz_HP : LIS2DUX12_50Hz_LP;
527 break;
528 case 0x08:
529 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_100Hz_HP : LIS2DUX12_100Hz_LP;
530 break;
531 case 0x09:
532 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_200Hz_HP : LIS2DUX12_200Hz_LP;
533 break;
534 case 0x0A:
535 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_400Hz_HP : LIS2DUX12_400Hz_LP;
536 break;
537 case 0x0B:
538 val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_800Hz_HP : LIS2DUX12_800Hz_LP;
539 break;
540 case 0xe:
541 val->odr = LIS2DUX12_TRIG_PIN;
542 break;
543 case 0xf:
544 val->odr = LIS2DUX12_TRIG_SW;
545 break;
546 default:
547 val->odr = LIS2DUX12_OFF;
548 break;
549 }
550
551 switch (ctrl5.fs)
552 {
553 case 0:
554 val->fs = LIS2DUX12_2g;
555 break;
556 case 1:
557 val->fs = LIS2DUX12_4g;
558 break;
559 case 2:
560 val->fs = LIS2DUX12_8g;
561 break;
562 case 3:
563 val->fs = LIS2DUX12_16g;
564 break;
565 default:
566 val->fs = LIS2DUX12_2g;
567 break;
568 }
569
570 switch (ctrl5.bw)
571 {
572 case 0:
573 val->bw = LIS2DUX12_ODR_div_2;
574 break;
575 case 1:
576 val->bw = LIS2DUX12_ODR_div_4;
577 break;
578 case 2:
579 val->bw = LIS2DUX12_ODR_div_8;
580 break;
581 case 3:
582 val->bw = LIS2DUX12_ODR_div_16;
583 break;
584 default:
585 val->bw = LIS2DUX12_ODR_div_2;
586 break;
587 }
588
589 return ret;
590 }
591
592 /**
593 * @brief Disable/Enable temperature sensor acquisition[set]
594 *
595 * @param ctx read / write interface definitions
596 * @param val 1: disable temp acquisition - 0: enable temp acquisition
597 * @retval interface status (MANDATORY: return 0 -> no Error)
598 *
599 */
lis2dux12_temp_disable_set(const stmdev_ctx_t * ctx,uint8_t val)600 int32_t lis2dux12_temp_disable_set(const stmdev_ctx_t *ctx, uint8_t val)
601 {
602 lis2dux12_self_test_t temp;
603 int32_t ret;
604
605 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1);
606
607 if (ret == 0)
608 {
609 temp.t_dis = val;
610 ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1);
611 }
612
613 return ret;
614 }
615
616 /**
617 * @brief Disable/Enable temperature sensor acquisition[get]
618 *
619 * @param ctx read / write interface definitions
620 * @param val 1: disable temp acquisition - 0: enable temp acquisition
621 * @retval interface status (MANDATORY: return 0 -> no Error)
622 *
623 */
lis2dux12_temp_disable_get(const stmdev_ctx_t * ctx,uint8_t * val)624 int32_t lis2dux12_temp_disable_get(const stmdev_ctx_t *ctx, uint8_t *val)
625 {
626 lis2dux12_self_test_t temp;
627 int32_t ret;
628
629 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1);
630 *val = temp.t_dis;
631
632 return ret;
633 }
634
635 /**
636 * @brief Enter deep power down[set]
637 *
638 * @param ctx read / write interface definitions
639 * @param val Enter deep power down
640 * @retval interface status (MANDATORY: return 0 -> no Error)
641 *
642 */
lis2dux12_enter_deep_power_down(const stmdev_ctx_t * ctx,uint8_t val)643 int32_t lis2dux12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val)
644 {
645 lis2dux12_sleep_t sleep;
646 int32_t ret;
647
648 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SLEEP, (uint8_t *)&sleep, 1);
649
650 if (ret == 0)
651 {
652 sleep.deep_pd = val;
653 ret = lis2dux12_write_reg(ctx, LIS2DUX12_SLEEP, (uint8_t *)&sleep, 1);
654 }
655
656 return ret;
657 }
658
659 /**
660 * @brief Enter soft power down in SPI case[set]
661 *
662 * @param ctx read / write interface definitions
663 * @param val Enter soft power down in SPI case
664 * @retval interface status (MANDATORY: return 0 -> no Error)
665 *
666 */
lis2dux12_exit_deep_power_down(const stmdev_ctx_t * ctx)667 int32_t lis2dux12_exit_deep_power_down(const stmdev_ctx_t *ctx)
668 {
669 lis2dux12_en_device_config_t en_device_config = {0};
670 int32_t ret;
671
672 en_device_config.soft_pd = PROPERTY_ENABLE;
673 ret = lis2dux12_write_reg(ctx, LIS2DUX12_EN_DEVICE_CONFIG, (uint8_t *)&en_device_config, 1);
674
675 if (ctx->mdelay != NULL)
676 {
677 ctx->mdelay(25); /* See AN5909 - paragraphs 3.1.1.1 and 3.1.1.2 */
678 }
679
680 return ret;
681 }
682
683 /**
684 * @brief Software trigger for One-Shot.[get]
685 *
686 * @param ctx communication interface handler.(ptr)
687 * @param md the sensor conversion parameters.(ptr)
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lis2dux12_trigger_sw(const stmdev_ctx_t * ctx,const lis2dux12_md_t * md)691 int32_t lis2dux12_trigger_sw(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md)
692 {
693 lis2dux12_ctrl4_t ctrl4;
694 int32_t ret = 0;
695
696 if (md->odr == LIS2DUX12_TRIG_SW)
697 {
698 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
699 ctrl4.soc = PROPERTY_ENABLE;
700 if (ret == 0)
701 {
702 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
703 }
704 }
705 return ret;
706 }
707
lis2dux12_all_sources_get(const stmdev_ctx_t * ctx,lis2dux12_all_sources_t * val)708 int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val)
709 {
710 lis2dux12_status_register_t status;
711 int32_t ret;
712
713 ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, (uint8_t *)&status, 1);
714 val->drdy = status.drdy;
715
716 if (ret == 0 && status.int_global == 0x1U)
717 {
718 lis2dux12_wake_up_src_t wu_src;
719 lis2dux12_tap_src_t tap_src;
720 lis2dux12_sixd_src_t sixd_src;
721
722 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD_SRC, (uint8_t *)&sixd_src, 1);
723 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1);
724 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_SRC, (uint8_t *)&tap_src, 1);
725
726 val->six_d = sixd_src.d6d_ia;
727 val->six_d_xl = sixd_src.xl;
728 val->six_d_xh = sixd_src.xh;
729 val->six_d_yl = sixd_src.yl;
730 val->six_d_yh = sixd_src.yh;
731 val->six_d_zl = sixd_src.zl;
732 val->six_d_zh = sixd_src.zh;
733
734 val->wake_up = wu_src.wu_ia;
735 val->wake_up_z = wu_src.z_wu;
736 val->wake_up_y = wu_src.y_wu;
737 val->wake_up_x = wu_src.x_wu;
738 val->free_fall = wu_src.ff_ia;
739 val->sleep_change = wu_src.sleep_change_ia;
740 val->sleep_state = wu_src.sleep_state;
741
742 val->single_tap = tap_src.single_tap_ia;
743 val->double_tap = tap_src.double_tap_ia;
744 val->triple_tap = tap_src.triple_tap_ia;
745 }
746
747 return ret;
748 }
749
750 /**
751 * @brief Accelerometer data.[get]
752 *
753 * @param ctx communication interface handler.(ptr)
754 * @param md the sensor conversion parameters.(ptr)
755 * @param data data retrived from the sensor.(ptr)
756 * @retval interface status (MANDATORY: return 0 -> no Error)
757 *
758 */
lis2dux12_xl_data_get(const stmdev_ctx_t * ctx,const lis2dux12_md_t * md,lis2dux12_xl_data_t * data)759 int32_t lis2dux12_xl_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md,
760 lis2dux12_xl_data_t *data)
761 {
762 uint8_t buff[6];
763 int32_t ret;
764 uint8_t i;
765 uint8_t j;
766
767 ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_X_L, buff, 6);
768
769 /* acceleration conversion */
770 j = 0U;
771 for (i = 0U; i < 3U; i++)
772 {
773 data->raw[i] = (int16_t)buff[j + 1U];
774 data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j];
775 j += 2U;
776 switch (md->fs)
777 {
778 case LIS2DUX12_2g:
779 data->mg[i] = lis2dux12_from_fs2g_to_mg(data->raw[i]);
780 break;
781 case LIS2DUX12_4g:
782 data->mg[i] = lis2dux12_from_fs4g_to_mg(data->raw[i]);
783 break;
784 case LIS2DUX12_8g:
785 data->mg[i] = lis2dux12_from_fs8g_to_mg(data->raw[i]);
786 break;
787 case LIS2DUX12_16g:
788 data->mg[i] = lis2dux12_from_fs16g_to_mg(data->raw[i]);
789 break;
790 default:
791 data->mg[i] = 0.0f;
792 break;
793 }
794 }
795
796 return ret;
797 }
798
799 /**
800 * @brief OUTT data.[get]
801 *
802 * @param ctx communication interface handler.(ptr)
803 * @param md the sensor conversion parameters.(ptr)
804 * @param data data retrived from the sensor.(ptr)
805 * @retval interface status (MANDATORY: return 0 -> no Error)
806 *
807 */
lis2dux12_outt_data_get(const stmdev_ctx_t * ctx,lis2dux12_outt_data_t * data)808 int32_t lis2dux12_outt_data_get(const stmdev_ctx_t *ctx,
809 lis2dux12_outt_data_t *data)
810 {
811 uint8_t buff[2];
812 int32_t ret;
813
814 ret = lis2dux12_read_reg(ctx, LIS2DUX12_OUT_T_L, buff, 2);
815
816 data->heat.raw = (int16_t)buff[1U];
817 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[0];
818 /* temperature conversion */
819 data->heat.deg_c = lis2dux12_from_lsb_to_celsius(data->heat.raw);
820
821 return ret;
822 }
823
824 /**
825 * @brief Configures the self test.[set]
826 *
827 * @param ctx communication interface handler.(ptr)
828 * @param val self test mode.(ptr)
829 * @retval interface status (MANDATORY: return 0 -> no Error)
830 *
831 */
lis2dux12_self_test_sign_set(const stmdev_ctx_t * ctx,lis2dux12_xl_self_test_t val)832 int32_t lis2dux12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val)
833 {
834 lis2dux12_ctrl3_t ctrl3;
835 lis2dux12_wake_up_dur_t wkup_dur;
836 int32_t ret;
837
838 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
839 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
840
841 switch (val)
842 {
843 case LIS2DUX12_XL_ST_POSITIVE:
844 ctrl3.st_sign_x = 1;
845 ctrl3.st_sign_y = 1;
846 wkup_dur.st_sign_z = 0;
847 break;
848
849 case LIS2DUX12_XL_ST_NEGATIVE:
850 ctrl3.st_sign_x = 0;
851 ctrl3.st_sign_y = 0;
852 wkup_dur.st_sign_z = 1;
853 break;
854
855 case LIS2DUX12_XL_ST_DISABLE:
856 default:
857 ret = -1;
858 break;
859 }
860
861
862 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
863 ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1);
864
865 return ret;
866 }
867
868 /**
869 * @brief Configures the self test.[start]
870 *
871 * @param ctx communication interface handler.(ptr)
872 * @param val valid values 2 (1st step) or 1 (2nd step)
873 * @retval interface status (MANDATORY: return 0 -> no Error)
874 *
875 */
lis2dux12_self_test_start(const stmdev_ctx_t * ctx,uint8_t val)876 int32_t lis2dux12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val)
877 {
878 lis2dux12_self_test_t self_test;
879 int32_t ret;
880
881 if (val != 1U && val != 2U)
882 {
883 return -1;
884 }
885
886 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1);
887 if (ret == 0)
888 {
889 self_test.st = (uint8_t) val;
890 ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1);
891 }
892 return ret;
893 }
894
895 /**
896 * @brief Configures the self test.[stop]
897 *
898 * @param ctx communication interface handler.(ptr)
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
lis2dux12_self_test_stop(const stmdev_ctx_t * ctx)902 int32_t lis2dux12_self_test_stop(const stmdev_ctx_t *ctx)
903 {
904 lis2dux12_self_test_t self_test;
905 int32_t ret;
906
907 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1);
908 if (ret == 0)
909 {
910 self_test.st = 0;
911 ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1);
912 }
913 return ret;
914 }
915
916 /**
917 * @brief Configures I3C bus.[set]
918 *
919 * @param ctx communication interface handler.(ptr)
920 * @param val configuration params
921 * @retval interface status (MANDATORY: return 0 -> no Error)
922 *
923 */
lis2dux12_i3c_configure_set(const stmdev_ctx_t * ctx,const lis2dux12_i3c_cfg_t * val)924 int32_t lis2dux12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2dux12_i3c_cfg_t *val)
925 {
926 lis2dux12_i3c_if_ctrl_t i3c_cfg;
927 int32_t ret;
928
929 ret = lis2dux12_read_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
930
931 if (ret == 0)
932 {
933 i3c_cfg.bus_act_sel = (uint8_t)val->bus_act_sel;
934 i3c_cfg.dis_drstdaa = val->drstdaa_en;
935 i3c_cfg.asf_on = val->asf_on;
936 ret = lis2dux12_write_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
937 }
938
939 return ret;
940 }
941
942 /**
943 * @brief Configures I3C bus.[get]
944 *
945 * @param ctx communication interface handler.(ptr)
946 * @param val configuration params
947 * @retval interface status (MANDATORY: return 0 -> no Error)
948 *
lis2dux12_i3c_configure_get(const stmdev_ctx_t * ctx,lis2dux12_i3c_cfg_t * val)949 */int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val)
950 {
951 lis2dux12_i3c_if_ctrl_t i3c_cfg;
952 int32_t ret;
953
954 ret = lis2dux12_read_reg(ctx, LIS2DUX12_I3C_IF_CTRL, (uint8_t *)&i3c_cfg, 1);
955
956 val->drstdaa_en = i3c_cfg.dis_drstdaa;
957 val->asf_on = i3c_cfg.asf_on;
958
959 switch (val->bus_act_sel)
960 {
961 case LIS2DUX12_I3C_BUS_AVAIL_TIME_20US:
962 val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_20US;
963 break;
964
965 case LIS2DUX12_I3C_BUS_AVAIL_TIME_50US:
966 val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_50US;
967 break;
968
969 case LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS:
970 val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS;
971 break;
972
973 case LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS:
974 default:
975 val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS;
976 break;
977 }
978
979 return ret;
980 }
981
982 /**
983 * @brief Change memory bank.[set]
984 *
985 * @param ctx read / write interface definitions
986 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
987 * @retval interface status (MANDATORY: return 0 -> no Error)
988 *
989 */
lis2dux12_mem_bank_set(const stmdev_ctx_t * ctx,lis2dux12_mem_bank_t val)990 int32_t lis2dux12_mem_bank_set(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val)
991 {
992 lis2dux12_func_cfg_access_t func_cfg_access;
993 int32_t ret;
994
995 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
996
997 if (ret == 0)
998 {
999 func_cfg_access.emb_func_reg_access = ((uint8_t)val & 0x1U);
1000 ret = lis2dux12_write_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
1001 }
1002
1003 return ret;
1004 }
1005
1006 /**
1007 * @brief Change memory bank.[get]
1008 *
1009 * @param ctx read / write interface definitions
1010 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, SENSOR_HUB_MEM_BANK, STRED_MEM_BANK,
1011 * @retval interface status (MANDATORY: return 0 -> no Error)
1012 *
1013 */
lis2dux12_mem_bank_get(const stmdev_ctx_t * ctx,lis2dux12_mem_bank_t * val)1014 int32_t lis2dux12_mem_bank_get(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val)
1015 {
1016 lis2dux12_func_cfg_access_t func_cfg_access;
1017 int32_t ret;
1018
1019 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
1020
1021 switch ((func_cfg_access.emb_func_reg_access))
1022 {
1023 case 0x0:
1024 *val = LIS2DUX12_MAIN_MEM_BANK;
1025 break;
1026
1027 case 0x1:
1028 *val = LIS2DUX12_EMBED_FUNC_MEM_BANK;
1029 break;
1030
1031 default:
1032 *val = LIS2DUX12_MAIN_MEM_BANK;
1033 break;
1034 }
1035 return ret;
1036 }
1037
1038 /**
1039 * @brief Write buffer in a page.
1040 *
1041 * @param ctx read / write interface definitions
1042 * @param address Address of page register to be written (page number in 8-bit
1043 * msb, register address in 8-bit lsb).
1044 * @param buf Pointer to data buffer.
1045 * @param len Buffer len.
1046 * @retval interface status (MANDATORY: return 0 -> no Error)
1047 *
1048 */
lis2dux12_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1049 int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
1050 {
1051 lis2dux12_page_address_t page_address;
1052 lis2dux12_page_sel_t page_sel;
1053 lis2dux12_page_rw_t page_rw;
1054 uint8_t msb;
1055 uint8_t lsb;
1056 int32_t ret;
1057 uint8_t i ;
1058
1059 msb = ((uint8_t)(address >> 8) & 0x0FU);
1060 lsb = (uint8_t)address & 0xFFU;
1061
1062 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1063 if (ret != 0)
1064 {
1065 goto exit;
1066 }
1067
1068 /* page write */
1069 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1070 page_rw.page_read = PROPERTY_DISABLE;
1071 page_rw.page_write = PROPERTY_ENABLE;
1072 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1073
1074 /* set page num */
1075 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1076 page_sel.page_sel = msb;
1077 page_sel.not_used0 = 1; // Default value
1078 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1079
1080 /* set page addr */
1081 page_address.page_addr = lsb;
1082 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
1083
1084 for (i = 0; i < len; i++)
1085 {
1086 /* read value */
1087 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1);
1088 lsb++;
1089
1090 /* Check if page wrap */
1091 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1092 {
1093 msb++;
1094 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1095 page_sel.page_sel = msb;
1096 page_sel.not_used0 = 1; // Default value
1097 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1098 }
1099
1100 if (ret != 0)
1101 {
1102 break;
1103 }
1104 }
1105
1106 page_sel.page_sel = 0;
1107 page_sel.not_used0 = 1;// Default value
1108 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1109
1110 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1111 page_rw.page_read = PROPERTY_DISABLE;
1112 page_rw.page_write = PROPERTY_DISABLE;
1113 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1114
1115 exit:
1116 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief Read buffer in a page.
1123 *
1124 * @param ctx read / write interface definitions
1125 * @param address Address of page register to be read (page number in 8-bit
1126 * msb, register address in 8-bit lsb).
1127 * @param buf Pointer to data buffer.
1128 * @param len Buffer len.
1129 * @retval interface status (MANDATORY: return 0 -> no Error)
1130 *
1131 */
lis2dux12_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1132 int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len)
1133 {
1134 lis2dux12_page_address_t page_address;
1135 lis2dux12_page_sel_t page_sel;
1136 lis2dux12_page_rw_t page_rw;
1137 uint8_t msb;
1138 uint8_t lsb;
1139 int32_t ret;
1140 uint8_t i ;
1141
1142 msb = ((uint8_t)(address >> 8) & 0x0FU);
1143 lsb = (uint8_t)address & 0xFFU;
1144
1145 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1146 if (ret != 0)
1147 {
1148 goto exit;
1149 }
1150
1151 /* page read */
1152 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1153 page_rw.page_read = PROPERTY_ENABLE;
1154 page_rw.page_write = PROPERTY_DISABLE;
1155 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1156 if (ret != 0)
1157 {
1158 goto exit;
1159 }
1160
1161 /* set page num */
1162 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1163 page_sel.page_sel = msb;
1164 page_sel.not_used0 = 1; // Default value
1165 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1166 if (ret != 0)
1167 {
1168 goto exit;
1169 }
1170
1171 for (i = 0; i < len; i++)
1172 {
1173 /* Sequential readings are not allowed. Set page address every loop */
1174 page_address.page_addr = lsb++;
1175 ret = lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1);
1176
1177 /* read value */
1178 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1);
1179
1180 /* Check if page wrap */
1181 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1182 {
1183 msb++;
1184 lsb = 0;
1185
1186 /* set page */
1187 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1188 page_sel.page_sel = msb;
1189 page_sel.not_used0 = 1; // Default value
1190 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1191 }
1192
1193 if (ret != 0)
1194 {
1195 goto exit;
1196 }
1197 }
1198
1199 page_sel.page_sel = 0;
1200 page_sel.not_used0 = 1;// Default value
1201 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1);
1202
1203 ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1204 page_rw.page_read = PROPERTY_DISABLE;
1205 page_rw.page_write = PROPERTY_DISABLE;
1206 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1207
1208 exit:
1209 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1210
1211 return ret;
1212 }
1213
1214 /**
1215 * @}
1216 *
1217 */
1218
1219 /**
1220 * @defgroup Interrupt PINs
1221 * @brief Interrupt PINs
1222 * @{/
1223 *
1224 */
1225
1226 /**
1227 * @brief External Clock Enable/Disable on INT pin.[set]
1228 *
1229 * @param ctx read / write interface definitions
1230 * @param val 0: disable ext_clk - 1: enable ext_clk
1231 * @retval interface status (MANDATORY: return 0 -> no Error)
1232 *
1233 */
lis2dux12_ext_clk_en_set(const stmdev_ctx_t * ctx,uint8_t val)1234 int32_t lis2dux12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val)
1235 {
1236 lis2dux12_ext_clk_cfg_t clk;
1237 int32_t ret;
1238
1239 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1240 clk.ext_clk_en = val;
1241 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1242
1243 return ret;
1244 }
1245
1246 /**
1247 * @brief External Clock Enable/Disable on INT pin.[get]
1248 *
1249 * @param ctx read / write interface definitions
1250 * @param val 0: disable ext_clk - 1: enable ext_clk
1251 * @retval interface status (MANDATORY: return 0 -> no Error)
1252 *
1253 */
lis2dux12_ext_clk_en_get(const stmdev_ctx_t * ctx,uint8_t * val)1254 int32_t lis2dux12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
1255 {
1256 lis2dux12_ext_clk_cfg_t clk;
1257 int32_t ret;
1258
1259 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1);
1260 *val = clk.ext_clk_en;
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief Electrical pin configuration.[set]
1267 *
1268 * @param ctx read / write interface definitions
1269 * @param val the electrical settings for the configurable pins.(ptr)
1270 * @retval interface status (MANDATORY: return 0 -> no Error)
1271 *
1272 */
lis2dux12_pin_conf_set(const stmdev_ctx_t * ctx,const lis2dux12_pin_conf_t * val)1273 int32_t lis2dux12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_conf_t *val)
1274 {
1275 lis2dux12_pin_ctrl_t pin_ctrl;
1276 int32_t ret;
1277
1278 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1279
1280 if (ret == 0)
1281 {
1282 pin_ctrl.cs_pu_dis = ~val->cs_pull_up;
1283 pin_ctrl.pd_dis_int1 = ~val->int1_pull_down;
1284 pin_ctrl.pd_dis_int2 = ~val->int2_pull_down;
1285 pin_ctrl.sda_pu_en = val->sda_pull_up;
1286 pin_ctrl.sdo_pu_en = val->sdo_pull_up;
1287 pin_ctrl.pp_od = ~val->int1_int2_push_pull;
1288
1289 ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1290 }
1291
1292 return ret;
1293 }
1294
1295 /**
1296 * @brief Electrical pin configuration.[get]
1297 *
1298 * @param ctx read / write interface definitions
1299 * @param val the electrical settings for the configurable pins.(ptr)
1300 * @retval interface status (MANDATORY: return 0 -> no Error)
1301 *
1302 */
lis2dux12_pin_conf_get(const stmdev_ctx_t * ctx,lis2dux12_pin_conf_t * val)1303 int32_t lis2dux12_pin_conf_get(const stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val)
1304 {
1305 lis2dux12_pin_ctrl_t pin_ctrl;
1306 int32_t ret;
1307
1308 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1309
1310 val->cs_pull_up = ~pin_ctrl.cs_pu_dis;
1311 val->int1_pull_down = ~pin_ctrl.pd_dis_int1;
1312 val->int2_pull_down = ~pin_ctrl.pd_dis_int2;
1313 val->sda_pull_up = pin_ctrl.sda_pu_en;
1314 val->sdo_pull_up = pin_ctrl.sdo_pu_en;
1315 val->int1_int2_push_pull = ~pin_ctrl.pp_od;
1316
1317 return ret;
1318 }
1319
1320 /**
1321 * @brief Interrupt activation level.[set]
1322 *
1323 * @param ctx read / write interface definitions
1324 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1325 * @retval interface status (MANDATORY: return 0 -> no Error)
1326 *
1327 */
lis2dux12_int_pin_polarity_set(const stmdev_ctx_t * ctx,lis2dux12_int_pin_polarity_t val)1328 int32_t lis2dux12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val)
1329 {
1330 lis2dux12_pin_ctrl_t pin_ctrl;
1331 int32_t ret;
1332
1333 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1334
1335 if (ret == 0)
1336 {
1337 pin_ctrl.h_lactive = (uint8_t)val;
1338 ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1339 }
1340
1341 return ret;
1342 }
1343
1344 /**
1345 * @brief Interrupt activation level.[get]
1346 *
1347 * @param ctx read / write interface definitions
1348 * @param val ACTIVE_HIGH, ACTIVE_LOW,
1349 * @retval interface status (MANDATORY: return 0 -> no Error)
1350 *
1351 */
lis2dux12_int_pin_polarity_get(const stmdev_ctx_t * ctx,lis2dux12_int_pin_polarity_t * val)1352 int32_t lis2dux12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val)
1353 {
1354 lis2dux12_pin_ctrl_t pin_ctrl;
1355 int32_t ret;
1356
1357 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1358
1359 switch ((pin_ctrl.h_lactive))
1360 {
1361 case 0x0:
1362 *val = LIS2DUX12_ACTIVE_HIGH;
1363 break;
1364
1365 case 0x1:
1366 *val = LIS2DUX12_ACTIVE_LOW;
1367 break;
1368
1369 default:
1370 *val = LIS2DUX12_ACTIVE_HIGH;
1371 break;
1372 }
1373 return ret;
1374 }
1375
1376 /**
1377 * @brief SPI mode.[set]
1378 *
1379 * @param ctx read / write interface definitions
1380 * @param val SPI_4_WIRE, SPI_3_WIRE,
1381 * @retval interface status (MANDATORY: return 0 -> no Error)
1382 *
1383 */
lis2dux12_spi_mode_set(const stmdev_ctx_t * ctx,lis2dux12_spi_mode val)1384 int32_t lis2dux12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dux12_spi_mode val)
1385 {
1386 lis2dux12_pin_ctrl_t pin_ctrl;
1387 int32_t ret;
1388
1389 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1390
1391 if (ret == 0)
1392 {
1393 pin_ctrl.sim = (uint8_t)val;
1394 ret = lis2dux12_write_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1395 }
1396
1397 return ret;
1398 }
1399
1400 /**
1401 * @brief SPI mode.[get]
1402 *
1403 * @param ctx read / write interface definitions
1404 * @param val SPI_4_WIRE, SPI_3_WIRE,
1405 * @retval interface status (MANDATORY: return 0 -> no Error)
1406 *
1407 */
lis2dux12_spi_mode_get(const stmdev_ctx_t * ctx,lis2dux12_spi_mode * val)1408 int32_t lis2dux12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dux12_spi_mode *val)
1409 {
1410 lis2dux12_pin_ctrl_t pin_ctrl;
1411 int32_t ret;
1412
1413 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
1414
1415 switch ((pin_ctrl.sim))
1416 {
1417 case 0x0:
1418 *val = LIS2DUX12_SPI_4_WIRE;
1419 break;
1420
1421 case 0x1:
1422 *val = LIS2DUX12_SPI_3_WIRE;
1423 break;
1424
1425 default:
1426 *val = LIS2DUX12_SPI_4_WIRE;
1427 break;
1428 }
1429 return ret;
1430 }
1431
1432 /**
1433 * @brief routes interrupt signals on INT 1 pin.[set]
1434 *
1435 * @param ctx read / write interface definitions
1436 * @param val routes interrupt signals on INT 1 pin.
1437 * @retval interface status (MANDATORY: return 0 -> no Error)
1438 *
1439 */
lis2dux12_pin_int1_route_set(const stmdev_ctx_t * ctx,const lis2dux12_pin_int_route_t * val)1440 int32_t lis2dux12_pin_int1_route_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_int_route_t *val)
1441 {
1442 lis2dux12_ctrl1_t ctrl1;
1443 lis2dux12_ctrl2_t ctrl2;
1444 lis2dux12_md1_cfg_t md1_cfg;
1445 int32_t ret;
1446
1447 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
1448
1449 if (ret == 0)
1450 {
1451 ctrl1.int1_on_res = val->int_on_res;
1452
1453 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
1454 }
1455
1456 if (ret == 0)
1457 {
1458 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1);
1459
1460 if (ret == 0)
1461 {
1462 ctrl2.int1_drdy = val->drdy;
1463 ctrl2.int1_fifo_ovr = val->fifo_ovr;
1464 ctrl2.int1_fifo_th = val->fifo_th;
1465 ctrl2.int1_fifo_full = val->fifo_full;
1466 ctrl2.int1_boot = val->boot;
1467
1468 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1);
1469 }
1470 }
1471
1472 if (ret == 0)
1473 {
1474 ret = lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1475
1476 if (ret == 0)
1477 {
1478 md1_cfg.int1_ff = val->free_fall;
1479 md1_cfg.int1_6d = val->six_d;
1480 md1_cfg.int1_tap = val->tap;
1481 md1_cfg.int1_wu = val->wake_up;
1482 md1_cfg.int1_sleep_change = val->sleep_change;
1483 md1_cfg.int1_emb_func = val->emb_function;
1484 md1_cfg.int1_timestamp = val->timestamp;
1485
1486 ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1487 }
1488 }
1489
1490 return ret;
1491 }
1492
1493 /**
1494 * @brief routes interrupt signals on INT 1 pin.[get]
1495 *
1496 * @param ctx read / write interface definitions
1497 * @param val Get interrupt signals routing on INT 1 pin.
1498 * @retval interface status (MANDATORY: return 0 -> no Error)
1499 *
1500 */
lis2dux12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2dux12_pin_int_route_t * val)1501 int32_t lis2dux12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val)
1502 {
1503 lis2dux12_ctrl1_t ctrl1;
1504 lis2dux12_ctrl2_t ctrl2;
1505 lis2dux12_md1_cfg_t md1_cfg;
1506 int32_t ret;
1507
1508 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
1509 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl2, 1);
1510 ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1511
1512 if (ret == 0)
1513 {
1514 val->int_on_res = ctrl1.int1_on_res;
1515 val->drdy = ctrl2.int1_drdy;
1516 val->fifo_ovr = ctrl2.int1_fifo_ovr;
1517 val->fifo_th = ctrl2.int1_fifo_th;
1518 val->fifo_full = ctrl2.int1_fifo_full;
1519 val->boot = ctrl2.int1_boot;
1520 val->free_fall = md1_cfg.int1_ff;
1521 val->six_d = md1_cfg.int1_6d;
1522 val->tap = md1_cfg.int1_tap;
1523 val->wake_up = md1_cfg.int1_wu;
1524 val->sleep_change = md1_cfg.int1_sleep_change;
1525 val->emb_function = md1_cfg.int1_emb_func;
1526 val->timestamp = md1_cfg.int1_timestamp;
1527 }
1528
1529 return ret;
1530 }
1531
1532 /**
1533 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
1534 *
1535 * @param ctx read / write interface definitions
1536 * @param val routes embedded func interrupt signals on INT 1 pin.
1537 * @retval interface status (MANDATORY: return 0 -> no Error)
1538 *
1539 */
lis2dux12_emb_pin_int1_route_set(const stmdev_ctx_t * ctx,const lis2dux12_emb_pin_int_route_t * val)1540 int32_t lis2dux12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx,
1541 const lis2dux12_emb_pin_int_route_t *val)
1542 {
1543 lis2dux12_emb_func_int1_t emb_func_int1;
1544 lis2dux12_md1_cfg_t md1_cfg;
1545 int32_t ret;
1546
1547 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1548 if (ret == 0)
1549 {
1550 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1551 }
1552
1553 if (ret == 0)
1554 {
1555 emb_func_int1.int1_tilt = val->tilt;
1556 emb_func_int1.int1_sig_mot = val->sig_mot;
1557 emb_func_int1.int1_step_det = val->step_det;
1558 emb_func_int1.int1_fsm_lc = val->fsm_lc;
1559
1560 ret = lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1561 }
1562 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1563
1564 ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1565 if (ret == 0)
1566 {
1567 md1_cfg.int1_emb_func = 1;
1568 ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1569 }
1570
1571 return ret;
1572 }
1573
1574 /**
1575 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
1576 *
1577 * @param ctx read / write interface definitions
1578 * @param val routes embedded func interrupt signals on INT 1 pin.
1579 * @retval interface status (MANDATORY: return 0 -> no Error)
1580 *
1581 */
lis2dux12_emb_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2dux12_emb_pin_int_route_t * val)1582 int32_t lis2dux12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx,
1583 lis2dux12_emb_pin_int_route_t *val)
1584 {
1585 lis2dux12_emb_func_int1_t emb_func_int1;
1586 int32_t ret;
1587
1588 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1589 if (ret == 0)
1590 {
1591 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
1592 }
1593
1594 if (ret == 0)
1595 {
1596 val->tilt = emb_func_int1.int1_tilt;
1597 val->sig_mot = emb_func_int1.int1_sig_mot;
1598 val->step_det = emb_func_int1.int1_step_det;
1599 val->fsm_lc = emb_func_int1.int1_fsm_lc;
1600 }
1601 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1602
1603 return ret;
1604 }
1605
1606 /**
1607 * @brief routes interrupt signals on INT 2 pin.[set]
1608 *
1609 * @param ctx read / write interface definitions
1610 * @param val routes interrupt signals on INT 2 pin.
1611 * @retval interface status (MANDATORY: return 0 -> no Error)
1612 *
1613 */
lis2dux12_pin_int2_route_set(const stmdev_ctx_t * ctx,const lis2dux12_pin_int_route_t * val)1614 int32_t lis2dux12_pin_int2_route_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_int_route_t *val)
1615 {
1616 lis2dux12_ctrl3_t ctrl3;
1617 lis2dux12_md2_cfg_t md2_cfg;
1618 int32_t ret;
1619
1620 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
1621
1622 if (ret == 0)
1623 {
1624 ctrl3.int2_drdy = val->drdy;
1625 ctrl3.int2_fifo_ovr = val->fifo_ovr;
1626 ctrl3.int2_fifo_th = val->fifo_th;
1627 ctrl3.int2_fifo_full = val->fifo_full;
1628 ctrl3.int2_boot = val->boot;
1629
1630 ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1);
1631 }
1632
1633 if (ret == 0)
1634 {
1635 ret = lis2dux12_read_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1636
1637 if (ret == 0)
1638 {
1639 md2_cfg.int2_ff = val->free_fall;
1640 md2_cfg.int2_6d = val->six_d;
1641 md2_cfg.int2_tap = val->tap;
1642 md2_cfg.int2_wu = val->wake_up;
1643 md2_cfg.int2_sleep_change = val->sleep_change;
1644 md2_cfg.int2_emb_func = val->emb_function;
1645 md2_cfg.int2_timestamp = val->timestamp;
1646
1647 ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1648 }
1649 }
1650
1651 return ret;
1652 }
1653
1654 /**
1655 * @brief routes interrupt signals on INT 2 pin.[get]
1656 *
1657 * @param ctx read / write interface definitions
1658 * @param val Get interrupt signals routing on INT 2 pin.
1659 * @retval interface status (MANDATORY: return 0 -> no Error)
1660 *
1661 */
lis2dux12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2dux12_pin_int_route_t * val)1662 int32_t lis2dux12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val)
1663 {
1664 lis2dux12_ctrl3_t ctrl3;
1665 lis2dux12_md2_cfg_t md2_cfg;
1666 int32_t ret;
1667
1668 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL2, (uint8_t *)&ctrl3, 1);
1669 ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD1_CFG, (uint8_t *)&md2_cfg, 1);
1670
1671 if (ret == 0)
1672 {
1673 val->drdy = ctrl3.int2_drdy;
1674 val->fifo_ovr = ctrl3.int2_fifo_ovr;
1675 val->fifo_th = ctrl3.int2_fifo_th;
1676 val->fifo_full = ctrl3.int2_fifo_full;
1677 val->boot = ctrl3.int2_boot;
1678 val->free_fall = md2_cfg.int2_ff;
1679 val->six_d = md2_cfg.int2_6d;
1680 val->tap = md2_cfg.int2_tap;
1681 val->wake_up = md2_cfg.int2_wu;
1682 val->sleep_change = md2_cfg.int2_sleep_change;
1683 val->emb_function = md2_cfg.int2_emb_func;
1684 val->timestamp = md2_cfg.int2_timestamp;
1685 }
1686
1687 return ret;
1688 }
1689
1690 /**
1691 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
1692 *
1693 * @param ctx read / write interface definitions
1694 * @param val routes embedded func interrupt signals on INT 2 pin.
1695 * @retval interface status (MANDATORY: return 0 -> no Error)
1696 *
1697 */
lis2dux12_emb_pin_int2_route_set(const stmdev_ctx_t * ctx,const lis2dux12_emb_pin_int_route_t * val)1698 int32_t lis2dux12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx,
1699 const lis2dux12_emb_pin_int_route_t *val)
1700 {
1701 lis2dux12_emb_func_int2_t emb_func_int2;
1702 lis2dux12_md2_cfg_t md2_cfg;
1703 int32_t ret;
1704
1705 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1706 if (ret == 0)
1707 {
1708 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1709 }
1710
1711 if (ret == 0)
1712 {
1713 emb_func_int2.int2_tilt = val->tilt;
1714 emb_func_int2.int2_sig_mot = val->sig_mot;
1715 emb_func_int2.int2_step_det = val->step_det;
1716 emb_func_int2.int2_fsm_lc = val->fsm_lc;
1717
1718 ret = lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1719 }
1720 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1721
1722 ret += lis2dux12_read_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1723 if (ret == 0)
1724 {
1725 md2_cfg.int2_emb_func = 1;
1726 ret = lis2dux12_write_reg(ctx, LIS2DUX12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1727 }
1728
1729 return ret;
1730 }
1731
1732 /**
1733 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
1734 *
1735 * @param ctx read / write interface definitions
1736 * @param val routes embedded func interrupt signals on INT 2 pin.
1737 * @retval interface status (MANDATORY: return 0 -> no Error)
1738 *
1739 */
lis2dux12_emb_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2dux12_emb_pin_int_route_t * val)1740 int32_t lis2dux12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx,
1741 lis2dux12_emb_pin_int_route_t *val)
1742 {
1743 lis2dux12_emb_func_int2_t emb_func_int2;
1744 int32_t ret;
1745
1746 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1747 if (ret == 0)
1748 {
1749 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
1750 }
1751
1752 if (ret == 0)
1753 {
1754 val->tilt = emb_func_int2.int2_tilt;
1755 val->sig_mot = emb_func_int2.int2_sig_mot;
1756 val->step_det = emb_func_int2.int2_step_det;
1757 val->fsm_lc = emb_func_int2.int2_fsm_lc;
1758 }
1759 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1760
1761 return ret;
1762 }
1763
1764 /**
1765 * @brief Interrupt configuration mode.[set]
1766 *
1767 * @param ctx read / write interface definitions
1768 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1769 * @retval interface status (MANDATORY: return 0 -> no Error)
1770 *
1771 */
lis2dux12_int_config_set(const stmdev_ctx_t * ctx,const lis2dux12_int_config_t * val)1772 int32_t lis2dux12_int_config_set(const stmdev_ctx_t *ctx, const lis2dux12_int_config_t *val)
1773 {
1774 lis2dux12_interrupt_cfg_t interrupt_cfg;
1775 int32_t ret;
1776
1777 ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1778
1779 if (ret == 0)
1780 {
1781 switch (val->int_cfg)
1782 {
1783 case LIS2DUX12_INT_DISABLED:
1784 interrupt_cfg.interrupts_enable = 0;
1785 break;
1786
1787 case LIS2DUX12_INT_LEVEL:
1788 interrupt_cfg.interrupts_enable = 1;
1789 interrupt_cfg.lir = 0;
1790 break;
1791
1792 case LIS2DUX12_INT_LATCHED:
1793 default:
1794 interrupt_cfg.interrupts_enable = 1;
1795 interrupt_cfg.lir = 1;
1796 break;
1797 }
1798
1799 interrupt_cfg.dis_rst_lir_all_int = val->dis_rst_lir_all_int;
1800 interrupt_cfg.sleep_status_on_int = val->sleep_status_on_int;
1801
1802 ret = lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1803 }
1804
1805 return ret;
1806 }
1807
1808 /**
1809 * @brief Interrupt configuration mode.[get]
1810 *
1811 * @param ctx read / write interface definitions
1812 * @param val INT_DISABLED, INT_LEVEL, INT_LATCHED
1813 * @retval interface status (MANDATORY: return 0 -> no Error)
1814 *
1815 */
lis2dux12_int_config_get(const stmdev_ctx_t * ctx,lis2dux12_int_config_t * val)1816 int32_t lis2dux12_int_config_get(const stmdev_ctx_t *ctx, lis2dux12_int_config_t *val)
1817 {
1818 lis2dux12_interrupt_cfg_t interrupt_cfg;
1819 int32_t ret;
1820
1821 ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&interrupt_cfg, 1);
1822
1823 if (ret == 0)
1824 {
1825 val->dis_rst_lir_all_int = interrupt_cfg.dis_rst_lir_all_int;
1826 val->sleep_status_on_int = interrupt_cfg.sleep_status_on_int;
1827
1828 if (interrupt_cfg.interrupts_enable == 0U)
1829 {
1830 val->int_cfg = LIS2DUX12_INT_DISABLED;
1831 }
1832 else if (interrupt_cfg.lir == 0U)
1833 {
1834 val->int_cfg = LIS2DUX12_INT_LEVEL;
1835 }
1836 else
1837 {
1838 val->int_cfg = LIS2DUX12_INT_LATCHED;
1839 }
1840 }
1841
1842 return ret;
1843 }
1844
1845 /**
1846 * @brief Embedded Interrupt configuration mode.[set]
1847 *
1848 * @param ctx read / write interface definitions
1849 * @param val INT_PULSED, INT_LATCHED
1850 * @retval interface status (MANDATORY: return 0 -> no Error)
1851 *
1852 */
lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t * ctx,lis2dux12_embedded_int_config_t val)1853 int32_t lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val)
1854 {
1855 lis2dux12_page_rw_t page_rw;
1856 int32_t ret;
1857
1858 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1859 if (ret == 0)
1860 {
1861 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1862
1863 switch (val)
1864 {
1865 case LIS2DUX12_EMBEDDED_INT_LEVEL:
1866 page_rw.emb_func_lir = 0;
1867 break;
1868
1869 case LIS2DUX12_EMBEDDED_INT_LATCHED:
1870 default:
1871 page_rw.emb_func_lir = 1;
1872 break;
1873 }
1874
1875 ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1876 }
1877
1878 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1879
1880 return ret;
1881 }
1882
1883 /**
1884 * @brief Interrupt configuration mode.[get]
1885 *
1886 * @param ctx read / write interface definitions
1887 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
1888 * @retval interface status (MANDATORY: return 0 -> no Error)
1889 *
1890 */
lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t * ctx,lis2dux12_embedded_int_config_t * val)1891 int32_t lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
1892 lis2dux12_embedded_int_config_t *val)
1893 {
1894 lis2dux12_page_rw_t page_rw;
1895 int32_t ret;
1896
1897 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
1898 if (ret == 0)
1899 {
1900 ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1);
1901
1902 if (page_rw.emb_func_lir == 0U)
1903 {
1904 *val = LIS2DUX12_EMBEDDED_INT_LEVEL;
1905 }
1906 else
1907 {
1908 *val = LIS2DUX12_EMBEDDED_INT_LATCHED;
1909 }
1910 }
1911
1912 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
1913
1914 return ret;
1915 }
1916
1917 /**
1918 * @}
1919 *
1920 */
1921
1922 /**
1923 * @defgroup FIFO
1924 * @brief FIFO
1925 * @{/
1926 *
1927 */
1928
1929 /**
1930 * @brief FIFO mode selection.[set]
1931 *
1932 * @param ctx read / write interface definitions
1933 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1934 * @retval interface status (MANDATORY: return 0 -> no Error)
1935 *
1936 */
lis2dux12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2dux12_fifo_mode_t val)1937 int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val)
1938 {
1939 lis2dux12_ctrl4_t ctrl4;
1940 lis2dux12_fifo_ctrl_t fifo_ctrl;
1941 lis2dux12_fifo_wtm_t fifo_wtm;
1942 lis2dux12_fifo_batch_dec_t fifo_batch;
1943 int32_t ret;
1944
1945 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
1946 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1947 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1948 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1949
1950 if (ret == 0)
1951 {
1952 /* set FIFO mode */
1953 if (val.operation != LIS2DUX12_FIFO_OFF)
1954 {
1955 ctrl4.fifo_en = 1;
1956 fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U);
1957 }
1958 else
1959 {
1960 ctrl4.fifo_en = 0;
1961 }
1962
1963 /* set fifo depth (1X/2X) */
1964 fifo_ctrl.fifo_depth = (uint8_t)val.store;
1965
1966 /* Set xl_only_fifo */
1967 fifo_wtm.xl_only_fifo = val.xl_only;
1968
1969 /* set batching info */
1970 if (val.batch.dec_ts != LIS2DUX12_DEC_TS_OFF)
1971 {
1972 fifo_batch.dec_ts_batch = (uint8_t)val.batch.dec_ts;
1973 fifo_batch.bdr_xl = (uint8_t)val.batch.bdr_xl;
1974 }
1975
1976 fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo;
1977
1978 /* set watermark */
1979 if (val.watermark > 0U)
1980 {
1981 fifo_ctrl.stop_on_fth = 1;
1982 fifo_wtm.fth = val.watermark;
1983 }
1984
1985 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
1986 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
1987 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
1988 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
1989 }
1990
1991 return ret;
1992 }
1993
1994 /**
1995 * @brief FIFO mode selection.[get]
1996 *
1997 * @param ctx read / write interface definitions
1998 * @param val BYPASS_MODE, FIFO_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
1999 * @retval interface status (MANDATORY: return 0 -> no Error)
2000 *
2001 */
lis2dux12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2dux12_fifo_mode_t * val)2002 int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val)
2003 {
2004 lis2dux12_ctrl4_t ctrl4;
2005 lis2dux12_fifo_ctrl_t fifo_ctrl;
2006 lis2dux12_fifo_wtm_t fifo_wtm;
2007 lis2dux12_fifo_batch_dec_t fifo_batch;
2008 int32_t ret;
2009
2010 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
2011 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
2012 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_BATCH_DEC, (uint8_t *)&fifo_batch, 1);
2013 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_WTM, (uint8_t *)&fifo_wtm, 1);
2014
2015 if (ret == 0)
2016 {
2017 /* get FIFO mode */
2018 if (ctrl4.fifo_en == 0U)
2019 {
2020 val->operation = LIS2DUX12_FIFO_OFF;
2021 }
2022 else
2023 {
2024 val->operation = (lis2dux12_operation_t)fifo_ctrl.fifo_mode;
2025 }
2026 val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en;
2027
2028 /* get fifo depth (1X/2X) */
2029 val->store = (lis2dux12_store_t)fifo_ctrl.fifo_depth;
2030
2031 /* Get xl_only_fifo */
2032 val->xl_only = fifo_wtm.xl_only_fifo;
2033
2034 /* get batching info */
2035 val->batch.dec_ts = (lis2dux12_dec_ts_t)fifo_batch.dec_ts_batch;
2036 val->batch.bdr_xl = (lis2dux12_bdr_xl_t)fifo_batch.bdr_xl;
2037
2038 /* get watermark */
2039 val->watermark = fifo_wtm.fth;
2040 }
2041
2042 return ret;
2043 }
2044
2045 /**
2046 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
2047 *
2048 * @param ctx read / write interface definitions
2049 * @param val Number of unread sensor data (TAG + 6 bytes) stored in FIFO.
2050 * @retval interface status (MANDATORY: return 0 -> no Error)
2051 *
2052 */
lis2dux12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)2053 int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
2054 {
2055 uint8_t buff;
2056 int32_t ret;
2057
2058 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS2, &buff, 1);
2059
2060 *val = buff;
2061
2062 return ret;
2063 }
2064
lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2065 int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2066 {
2067 lis2dux12_fifo_status1_t fifo_status1;
2068 int32_t ret;
2069
2070 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1);
2071
2072 *val = fifo_status1.fifo_wtm_ia;
2073
2074 return ret;
2075 }
2076
lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lis2dux12_fifo_sensor_tag_t * val)2077 int32_t lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_sensor_tag_t *val)
2078 {
2079 lis2dux12_fifo_data_out_tag_t fifo_tag;
2080 int32_t ret;
2081
2082 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
2083
2084 *val = (lis2dux12_fifo_sensor_tag_t) fifo_tag.tag_sensor;
2085
2086 return ret;
2087 }
2088
lis2dux12_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)2089 int32_t lis2dux12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2090 {
2091 int32_t ret;
2092
2093 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_X_L, buff, 6);
2094
2095 return ret;
2096 }
2097
lis2dux12_fifo_data_get(const stmdev_ctx_t * ctx,const lis2dux12_md_t * md,const lis2dux12_fifo_mode_t * fmd,lis2dux12_fifo_data_t * data)2098 int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md,
2099 const lis2dux12_fifo_mode_t *fmd,
2100 lis2dux12_fifo_data_t *data)
2101 {
2102 lis2dux12_fifo_data_out_tag_t fifo_tag;
2103 uint8_t fifo_raw[6];
2104 int32_t ret, i;
2105
2106 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1);
2107 data->tag = fifo_tag.tag_sensor;
2108
2109 switch (fifo_tag.tag_sensor)
2110 {
2111 case 0x3:
2112 /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */
2113 ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw);
2114 for (i = 0; i < 3; i++)
2115 {
2116 data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256;
2117 data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256;
2118 }
2119 break;
2120 case 0x2:
2121 ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw);
2122 if (fmd->xl_only == 0x0U)
2123 {
2124 /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/
2125 data->xl[0].raw[0] = (int16_t)fifo_raw[0];
2126 data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16;
2127 data->xl[0].raw[1] = (int16_t)fifo_raw[1] / 16;
2128 data->xl[0].raw[1] = (data->xl[0].raw[1] + ((int16_t)fifo_raw[2] * 16)) * 16;
2129 data->xl[0].raw[2] = (int16_t)fifo_raw[3];
2130 data->xl[0].raw[2] = (data->xl[0].raw[2] + (int16_t)fifo_raw[4] * 256) * 16;
2131 data->heat.raw = (int16_t)fifo_raw[4] / 16;
2132 data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16;
2133 data->heat.deg_c = lis2dux12_from_lsb_to_celsius(data->heat.raw);
2134 }
2135 else
2136 {
2137 /* A FIFO sample consists of 16-bits 3-axis XL at ODR */
2138 data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256;
2139 data->xl[0].raw[1] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[3] * 256;
2140 data->xl[0].raw[2] = (int16_t)fifo_raw[4] + (int16_t)fifo_raw[5] * 256;
2141 }
2142 break;
2143 case 0x4:
2144 ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw);
2145
2146 data->cfg_chg.cfg_change = fifo_raw[0] >> 7;
2147 data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU;
2148 data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U;
2149 data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U;
2150 data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U;
2151 data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U;
2152 data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U;
2153
2154 data->cfg_chg.timestamp = fifo_raw[5];
2155 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4];
2156 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3];
2157 data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2];
2158 break;
2159
2160 case 0x12:
2161 ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw);
2162
2163 data->pedo.steps = fifo_raw[1];
2164 data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0];
2165
2166 data->pedo.timestamp = fifo_raw[5];
2167 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4];
2168 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3];
2169 data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2];
2170
2171 break;
2172
2173 case 0x0:
2174 default:
2175 /* do nothing */
2176 break;
2177 }
2178
2179 for (i = 0; i < 3; i++)
2180 {
2181 switch (md->fs)
2182 {
2183 case LIS2DUX12_2g:
2184 data->xl[0].mg[i] = lis2dux12_from_fs2g_to_mg(data->xl[0].raw[i]);
2185 data->xl[1].mg[i] = lis2dux12_from_fs2g_to_mg(data->xl[1].raw[i]);
2186 break;
2187 case LIS2DUX12_4g:
2188 data->xl[0].mg[i] = lis2dux12_from_fs4g_to_mg(data->xl[0].raw[i]);
2189 data->xl[1].mg[i] = lis2dux12_from_fs4g_to_mg(data->xl[1].raw[i]);
2190 break;
2191 case LIS2DUX12_8g:
2192 data->xl[0].mg[i] = lis2dux12_from_fs8g_to_mg(data->xl[0].raw[i]);
2193 data->xl[1].mg[i] = lis2dux12_from_fs8g_to_mg(data->xl[1].raw[i]);
2194 break;
2195 case LIS2DUX12_16g:
2196 data->xl[0].mg[i] = lis2dux12_from_fs16g_to_mg(data->xl[0].raw[i]);
2197 data->xl[1].mg[i] = lis2dux12_from_fs16g_to_mg(data->xl[1].raw[i]);
2198 break;
2199 default:
2200 data->xl[0].mg[i] = 0.0f;
2201 data->xl[1].mg[i] = 0.0f;
2202 break;
2203 }
2204 }
2205
2206 return ret;
2207 }
2208
2209 /**
2210 * @defgroup Step Counter (Pedometer)
2211 * @brief Step Counter (Pedometer)
2212 * @{/
2213 *
2214 */
2215 /**
2216 * @brief Step counter mode[set]
2217 *
2218 * @param ctx read / write interface definitions
2219 * @param val Step counter mode
2220 * @retval interface status (MANDATORY: return 0 -> no Error)
2221 *
2222 */
lis2dux12_stpcnt_mode_set(const stmdev_ctx_t * ctx,lis2dux12_stpcnt_mode_t val)2223 int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val)
2224 {
2225 lis2dux12_emb_func_en_a_t emb_func_en_a;
2226 lis2dux12_emb_func_en_b_t emb_func_en_b;
2227 lis2dux12_emb_func_fifo_en_t emb_func_fifo_en;
2228 lis2dux12_pedo_cmd_reg_t pedo_cmd_reg;
2229 int32_t ret;
2230
2231 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2232 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2233 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
2234 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2235
2236 if ((val.false_step_rej == PROPERTY_ENABLE)
2237 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE))
2238 {
2239 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
2240 }
2241
2242 emb_func_fifo_en.step_counter_fifo_en = val.step_counter_in_fifo;
2243 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1);
2244
2245 emb_func_en_a.pedo_en = val.step_counter_enable;
2246 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2247
2248 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2249 ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG,
2250 (uint8_t *)&pedo_cmd_reg, 1);
2251
2252 if (ret == 0)
2253 {
2254 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
2255 ret += lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG,
2256 (uint8_t *)&pedo_cmd_reg, 1);
2257 }
2258
2259 return ret;
2260 }
2261
2262 /**
2263 * @brief Step counter mode[get]
2264 *
2265 * @param ctx read / write interface definitions
2266 * @param val Step counter mode
2267 * @retval interface status (MANDATORY: return 0 -> no Error)
2268 *
2269 */
lis2dux12_stpcnt_mode_get(const stmdev_ctx_t * ctx,lis2dux12_stpcnt_mode_t * val)2270 int32_t lis2dux12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val)
2271 {
2272 lis2dux12_emb_func_en_a_t emb_func_en_a;
2273 lis2dux12_pedo_cmd_reg_t pedo_cmd_reg;
2274 int32_t ret;
2275
2276 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2277 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2278 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2279
2280 ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG,
2281 (uint8_t *)&pedo_cmd_reg, 1);
2282 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
2283 val->step_counter_enable = emb_func_en_a.pedo_en;
2284
2285 return ret;
2286 }
2287
2288 /**
2289 * @brief Step counter output, number of detected steps.[get]
2290 *
2291 * @param ctx read / write interface definitions
2292 * @param val Step counter output, number of detected steps.
2293 * @retval interface status (MANDATORY: return 0 -> no Error)
2294 *
2295 */
lis2dux12_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)2296 int32_t lis2dux12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
2297 {
2298 uint8_t buff[2];
2299 int32_t ret;
2300
2301 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2302 ret += lis2dux12_read_reg(ctx, LIS2DUX12_STEP_COUNTER_L, &buff[0], 2);
2303 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2304
2305 *val = buff[1];
2306 *val = (*val * 256U) + buff[0];
2307
2308 return ret;
2309 }
2310
2311 /**
2312 * @brief Reset step counter.[set]
2313 *
2314 * @param ctx read / write interface definitions
2315 * @param val Reset step counter.
2316 * @retval interface status (MANDATORY: return 0 -> no Error)
2317 *
2318 */
lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t * ctx)2319 int32_t lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx)
2320 {
2321 lis2dux12_emb_func_src_t emb_func_src;
2322 int32_t ret;
2323
2324 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2325 if (ret == 0)
2326 {
2327 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2328 emb_func_src.pedo_rst_step = 1;
2329 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2330 }
2331
2332 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2333
2334 return ret;
2335 }
2336
2337 /**
2338 * @brief Pedometer debounce configuration.[set]
2339 *
2340 * @param ctx read / write interface definitions
2341 * @param val Pedometer debounce configuration.
2342 * @retval interface status (MANDATORY: return 0 -> no Error)
2343 *
2344 */
lis2dux12_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)2345 int32_t lis2dux12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
2346 {
2347 lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2348 int32_t ret;
2349
2350 pedo_deb_steps_conf.deb_step = val;
2351 ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF,
2352 (uint8_t *)&pedo_deb_steps_conf, 1);
2353
2354 return ret;
2355 }
2356
2357 /**
2358 * @brief Pedometer debounce configuration.[get]
2359 *
2360 * @param ctx read / write interface definitions
2361 * @param val Pedometer debounce configuration.
2362 * @retval interface status (MANDATORY: return 0 -> no Error)
2363 *
2364 */
lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)2365 int32_t lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
2366 {
2367 lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf;
2368 int32_t ret;
2369
2370 ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF,
2371 (uint8_t *)&pedo_deb_steps_conf, 1);
2372 *val = pedo_deb_steps_conf.deb_step;
2373
2374 return ret;
2375 }
2376
2377 /**
2378 * @brief Time period register for step detection on delta time.[set]
2379 *
2380 * @param ctx read / write interface definitions
2381 * @param val Time period register for step detection on delta time.
2382 * @retval interface status (MANDATORY: return 0 -> no Error)
2383 *
2384 */
lis2dux12_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)2385 int32_t lis2dux12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
2386 {
2387 uint8_t buff[2];
2388 int32_t ret;
2389
2390 buff[1] = (uint8_t)(val / 256U);
2391 buff[0] = (uint8_t)(val - (buff[1] * 256U));
2392
2393 ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L,
2394 (uint8_t *)buff, 2);
2395
2396 return ret;
2397 }
2398
2399 /**
2400 * @brief Time period register for step detection on delta time.[get]
2401 *
2402 * @param ctx read / write interface definitions
2403 * @param val Time period register for step detection on delta time.
2404 * @retval interface status (MANDATORY: return 0 -> no Error)
2405 *
2406 */
lis2dux12_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)2407 int32_t lis2dux12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
2408 {
2409 uint8_t buff[2];
2410 int32_t ret;
2411
2412 ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L,
2413 (uint8_t *)buff, 2);
2414 *val = buff[1];
2415 *val = (*val * 256U) + buff[0];
2416
2417 return ret;
2418 }
2419
2420 /**
2421 * @brief smart_power functionality configuration.[set]
2422 *
2423 * @param ctx read / write interface definitions
2424 * @param val lis2dux12_smart_power_cfg_t structure.
2425 * @retval interface status (MANDATORY: return 0 -> no Error)
2426 */
lis2dux12_smart_power_set(const stmdev_ctx_t * ctx,lis2dux12_smart_power_cfg_t val)2427 int32_t lis2dux12_smart_power_set(const stmdev_ctx_t *ctx, lis2dux12_smart_power_cfg_t val)
2428 {
2429 lis2dux12_ctrl1_t ctrl1;
2430 lis2dux12_smart_power_ctrl_t smart_power_ctrl;
2431 int32_t ret;
2432
2433 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
2434 ctrl1.smart_power_en = val.enable;
2435 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
2436
2437 if (val.enable == 0)
2438 {
2439 /* if disabling smart_power no need to set win/dur fields */
2440 return ret;
2441 }
2442
2443 smart_power_ctrl.smart_power_ctrl_win = val.window;
2444 smart_power_ctrl.smart_power_ctrl_dur = val.duration;
2445 ret += lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_SMART_POWER_CTRL,
2446 (uint8_t *)&smart_power_ctrl, 1);
2447
2448 return ret;
2449 }
2450
2451 /**
2452 * @brief smart_power functionality configuration.[get]
2453 *
2454 * @param ctx read / write interface definitions
2455 * @param val lis2dux12_smart_power_cfg_t structure.
2456 * @retval interface status (MANDATORY: return 0 -> no Error)
2457 */
lis2dux12_smart_power_get(const stmdev_ctx_t * ctx,lis2dux12_smart_power_cfg_t * val)2458 int32_t lis2dux12_smart_power_get(const stmdev_ctx_t *ctx, lis2dux12_smart_power_cfg_t *val)
2459 {
2460 lis2dux12_ctrl1_t ctrl1;
2461 lis2dux12_smart_power_ctrl_t smart_power_ctrl;
2462 int32_t ret;
2463
2464 ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
2465 val->enable = ctrl1.smart_power_en;
2466
2467 ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_SMART_POWER_CTRL,
2468 (uint8_t *)&smart_power_ctrl, 1);
2469 val->window = smart_power_ctrl.smart_power_ctrl_win;
2470 val->duration = smart_power_ctrl.smart_power_ctrl_dur;
2471
2472 return ret;
2473 }
2474
2475 /**
2476 * @}
2477 *
2478 */
2479
2480 /**
2481 * @defgroup Tilt
2482 * @brief Tilt
2483 * @{/
2484 *
2485 */
2486 /**
2487 * @brief Tilt calculation.[set]
2488 *
2489 * @param ctx read / write interface definitions
2490 * @param val Tilt calculation.
2491 * @retval interface status (MANDATORY: return 0 -> no Error)
2492 *
2493 */
lis2dux12_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2494 int32_t lis2dux12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2495 {
2496 lis2dux12_emb_func_en_a_t emb_func_en_a;
2497 int32_t ret;
2498
2499 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2500 if (ret == 0)
2501 {
2502 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2503 emb_func_en_a.tilt_en = val;
2504 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2505 }
2506
2507 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2508
2509 return ret;
2510 }
2511
2512 /**
2513 * @brief Tilt calculation.[get]
2514 *
2515 * @param ctx read / write interface definitions
2516 * @param val Tilt calculation.
2517 * @retval interface status (MANDATORY: return 0 -> no Error)
2518 *
2519 */
lis2dux12_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2520 int32_t lis2dux12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2521 {
2522 lis2dux12_emb_func_en_a_t emb_func_en_a;
2523 int32_t ret;
2524
2525 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2526 if (ret == 0)
2527 {
2528 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2529 *val = emb_func_en_a.tilt_en;
2530 }
2531
2532 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2533
2534 return ret;
2535 }
2536
2537 /**
2538 * @}
2539 *
2540 */
2541
2542 /**
2543 * @defgroup Significant motion detection
2544 * @brief Significant motion detection
2545 * @{/
2546 *
2547 */
2548 /**
2549 * @brief Enables significant motion detection function.[set]
2550 *
2551 * @param ctx read / write interface definitions
2552 * @param val Enables significant motion detection function.
2553 * @retval interface status (MANDATORY: return 0 -> no Error)
2554 *
2555 */
lis2dux12_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2556 int32_t lis2dux12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2557 {
2558 lis2dux12_emb_func_en_a_t emb_func_en_a;
2559 int32_t ret;
2560
2561 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2562 if (ret == 0)
2563 {
2564 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2565 emb_func_en_a.sign_motion_en = val;
2566 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2567 }
2568
2569 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2570
2571 return ret;
2572 }
2573
2574 /**
2575 * @brief Enables significant motion detection function.[get]
2576 *
2577 * @param ctx read / write interface definitions
2578 * @param val Enables significant motion detection function.
2579 * @retval interface status (MANDATORY: return 0 -> no Error)
2580 *
2581 */
lis2dux12_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2582 int32_t lis2dux12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2583 {
2584 lis2dux12_emb_func_en_a_t emb_func_en_a;
2585 int32_t ret;
2586
2587 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
2588 if (ret == 0)
2589 {
2590 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
2591 *val = emb_func_en_a.sign_motion_en;
2592 }
2593
2594 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
2595
2596 return ret;
2597 }
2598
2599 /**
2600 * @}
2601 *
2602 */
2603
2604
2605 /**
2606 * @defgroup Free Fall
2607 * @brief Free Fall
2608 * @{/
2609 *
2610 */
2611 /**
2612 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
2613 *
2614 * @param ctx read / write interface definitions
2615 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2616 * @retval interface status (MANDATORY: return 0 -> no Error)
2617 *
2618 */
lis2dux12_ff_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2619 int32_t lis2dux12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val)
2620 {
2621 lis2dux12_wake_up_dur_t wake_up_dur;
2622 lis2dux12_free_fall_t free_fall;
2623 int32_t ret;
2624
2625 ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2626
2627 if (ret == 0)
2628 {
2629 wake_up_dur.ff_dur = (val >> 5) & 0x1U;
2630 ret = lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2631 }
2632
2633 if (ret == 0)
2634 {
2635 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2636 free_fall.ff_dur = val & 0x1FU;
2637 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2638 }
2639
2640 return ret;
2641 }
2642
2643 /**
2644 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
2645 *
2646 * @param ctx read / write interface definitions
2647 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
2648 * @retval interface status (MANDATORY: return 0 -> no Error)
2649 *
2650 */
lis2dux12_ff_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2651 int32_t lis2dux12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val)
2652 {
2653 lis2dux12_wake_up_dur_t wake_up_dur;
2654 lis2dux12_free_fall_t free_fall;
2655 int32_t ret;
2656
2657 ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
2658 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2659
2660 *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur;
2661
2662 return ret;
2663 }
2664
2665 /**
2666 * @brief Free fall threshold setting.[set]
2667 *
2668 * @param ctx read / write interface definitions
2669 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2670 * @retval interface status (MANDATORY: return 0 -> no Error)
2671 *
2672 */
lis2dux12_ff_thresholds_set(const stmdev_ctx_t * ctx,lis2dux12_ff_thresholds_t val)2673 int32_t lis2dux12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val)
2674 {
2675 lis2dux12_free_fall_t free_fall;
2676 int32_t ret;
2677
2678 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2679 free_fall.ff_ths = ((uint8_t)val & 0x7U);
2680 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2681
2682 return ret;
2683 }
2684
2685 /**
2686 * @brief Free fall threshold setting.[get]
2687 *
2688 * @param ctx read / write interface definitions
2689 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
2690 * @retval interface status (MANDATORY: return 0 -> no Error)
2691 *
2692 */
lis2dux12_ff_thresholds_get(const stmdev_ctx_t * ctx,lis2dux12_ff_thresholds_t * val)2693 int32_t lis2dux12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val)
2694 {
2695 lis2dux12_free_fall_t free_fall;
2696 int32_t ret;
2697
2698 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1);
2699
2700 switch (free_fall.ff_ths)
2701 {
2702 case 0x0:
2703 *val = LIS2DUX12_156_mg;
2704 break;
2705
2706 case 0x1:
2707 *val = LIS2DUX12_219_mg;
2708 break;
2709
2710 case 0x2:
2711 *val = LIS2DUX12_250_mg;
2712 break;
2713
2714 case 0x3:
2715 *val = LIS2DUX12_312_mg;
2716 break;
2717
2718 case 0x4:
2719 *val = LIS2DUX12_344_mg;
2720 break;
2721
2722 case 0x5:
2723 *val = LIS2DUX12_406_mg;
2724 break;
2725
2726 case 0x6:
2727 *val = LIS2DUX12_469_mg;
2728 break;
2729
2730 case 0x7:
2731 *val = LIS2DUX12_500_mg;
2732 break;
2733
2734 default:
2735 *val = LIS2DUX12_156_mg;
2736 break;
2737 }
2738 return ret;
2739 }
2740
2741 /**
2742 * @}
2743 *
2744 */
2745
2746
2747 /**
2748 * @defgroup Orientation 6D (and 4D)
2749 * @brief Orientation 6D (and 4D)
2750 * @{/
2751 *
2752 */
2753 /**
2754 * @brief configuration for 4D/6D function.[set]
2755 *
2756 * @param ctx read / write interface definitions
2757 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2758 * @retval interface status (MANDATORY: return 0 -> no Error)
2759 *
2760 */
lis2dux12_sixd_config_set(const stmdev_ctx_t * ctx,lis2dux12_sixd_config_t val)2761 int32_t lis2dux12_sixd_config_set(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val)
2762 {
2763 lis2dux12_sixd_t sixd;
2764 int32_t ret;
2765
2766 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1);
2767
2768 if (ret == 0)
2769 {
2770 sixd.d4d_en = ((uint8_t)val.mode);
2771 sixd.d6d_ths = ((uint8_t)val.threshold);
2772 ret = lis2dux12_write_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1);
2773 }
2774
2775 return ret;
2776 }
2777
2778 /**
2779 * @brief configuration for 4D/6D function.[get]
2780 *
2781 * @param ctx read / write interface definitions
2782 * @param val 4D/6D, DEG_80, DEG_70, DEG_60, DEG_50,
2783 * @retval interface status (MANDATORY: return 0 -> no Error)
2784 *
2785 */
lis2dux12_sixd_config_get(const stmdev_ctx_t * ctx,lis2dux12_sixd_config_t * val)2786 int32_t lis2dux12_sixd_config_get(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val)
2787 {
2788 lis2dux12_sixd_t sixd;
2789 int32_t ret;
2790
2791 ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1);
2792
2793 val->mode = (lis2dux12_mode_t)sixd.d4d_en;
2794
2795 switch ((sixd.d6d_ths))
2796 {
2797 case 0x0:
2798 val->threshold = LIS2DUX12_DEG_80;
2799 break;
2800
2801 case 0x1:
2802 val->threshold = LIS2DUX12_DEG_70;
2803 break;
2804
2805 case 0x2:
2806 val->threshold = LIS2DUX12_DEG_60;
2807 break;
2808
2809 case 0x3:
2810 val->threshold = LIS2DUX12_DEG_50;
2811 break;
2812
2813 default:
2814 val->threshold = LIS2DUX12_DEG_80;
2815 break;
2816 }
2817
2818 return ret;
2819 }
2820
2821 /**
2822 * @}
2823 *
2824 */
2825
2826 /**
2827 * @defgroup wakeup configuration
2828 * @brief wakeup configuration
2829 * @{/
2830 *
2831 */
2832
2833 /**
2834 * @brief configuration for wakeup function.[set]
2835 *
2836 * @param ctx read / write interface definitions
2837 * @param val threshold, duration, ...
2838 * @retval interface status (MANDATORY: return 0 -> no Error)
2839 *
2840 */
lis2dux12_wakeup_config_set(const stmdev_ctx_t * ctx,lis2dux12_wakeup_config_t val)2841 int32_t lis2dux12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val)
2842 {
2843 lis2dux12_wake_up_ths_t wup_ths;
2844 lis2dux12_wake_up_dur_t wup_dur;
2845 lis2dux12_wake_up_dur_ext_t wup_dur_ext;
2846 lis2dux12_interrupt_cfg_t int_cfg;
2847 lis2dux12_ctrl1_t ctrl1;
2848 lis2dux12_ctrl4_t ctrl4;
2849 int32_t ret;
2850
2851 ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2852 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2853 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2854 ret += lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2855 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
2856 ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
2857
2858 if (ret == 0)
2859 {
2860 wup_dur.wake_dur = (uint8_t)val.wake_dur & 0x3U;
2861 wup_dur_ext.wu_dur_extended = (uint8_t)val.wake_dur >> 2;
2862 wup_dur.sleep_dur = val.sleep_dur;
2863
2864 int_cfg.wake_ths_w = val.wake_ths_weight;
2865 wup_ths.wk_ths = val.wake_ths;
2866 wup_ths.sleep_on = (uint8_t)val.wake_enable;
2867 ctrl4.inact_odr = (uint8_t)val.inact_odr;
2868
2869 if (val.wake_enable == LIS2DUX12_SLEEP_ON)
2870 {
2871 ctrl1.wu_x_en = 1;
2872 ctrl1.wu_y_en = 1;
2873 ctrl1.wu_z_en = 1;
2874 }
2875 else
2876 {
2877 ctrl1.wu_x_en = 0;
2878 ctrl1.wu_y_en = 0;
2879 ctrl1.wu_z_en = 0;
2880 }
2881
2882 ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2883 ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2884 ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2885 ret += lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2886 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1);
2887 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
2888 }
2889
2890 return ret;
2891 }
2892
2893 /**
2894 * @brief configuration for wakeup function.[get]
2895 *
2896 * @param ctx read / write interface definitions
2897 * @param val threshold, duration, ...
2898 * @retval interface status (MANDATORY: return 0 -> no Error)
2899 *
2900 */
lis2dux12_wakeup_config_get(const stmdev_ctx_t * ctx,lis2dux12_wakeup_config_t * val)2901 int32_t lis2dux12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val)
2902 {
2903 lis2dux12_wake_up_ths_t wup_ths;
2904 lis2dux12_wake_up_dur_t wup_dur;
2905 lis2dux12_wake_up_dur_ext_t wup_dur_ext;
2906 lis2dux12_interrupt_cfg_t int_cfg;
2907 lis2dux12_ctrl4_t ctrl4;
2908 int32_t ret;
2909
2910 ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_THS, (uint8_t *)&wup_ths, 1);
2911 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wup_dur, 1);
2912 ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR_EXT, (uint8_t *)&wup_dur_ext, 1);
2913 ret += lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
2914 ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1);
2915
2916 if (ret == 0)
2917 {
2918 switch (wup_dur.wake_dur)
2919 {
2920 case 0x0:
2921 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2922 LIS2DUX12_3_ODR : LIS2DUX12_0_ODR;
2923 break;
2924
2925 case 0x1:
2926 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2927 LIS2DUX12_7_ODR : LIS2DUX12_1_ODR;
2928 break;
2929
2930 case 0x2:
2931 val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ?
2932 LIS2DUX12_11_ODR : LIS2DUX12_2_ODR;
2933 break;
2934
2935 case 0x3:
2936 default:
2937 val->wake_dur = LIS2DUX12_15_ODR;
2938 break;
2939 }
2940
2941 val->sleep_dur = wup_dur.sleep_dur;
2942
2943 val->wake_ths_weight = int_cfg.wake_ths_w;
2944 val->wake_ths = wup_ths.wk_ths;
2945 val->wake_enable = (lis2dux12_wake_enable_t)wup_ths.sleep_on;
2946 val->inact_odr = (lis2dux12_inact_odr_t)ctrl4.inact_odr;
2947 }
2948
2949 return ret;
2950 }
2951
2952 /**
2953 * @}
2954 *
2955 */
2956
lis2dux12_tap_config_set(const stmdev_ctx_t * ctx,lis2dux12_tap_config_t val)2957 int32_t lis2dux12_tap_config_set(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t val)
2958 {
2959 lis2dux12_tap_cfg0_t tap_cfg0;
2960 lis2dux12_tap_cfg1_t tap_cfg1;
2961 lis2dux12_tap_cfg2_t tap_cfg2;
2962 lis2dux12_tap_cfg3_t tap_cfg3;
2963 lis2dux12_tap_cfg4_t tap_cfg4;
2964 lis2dux12_tap_cfg5_t tap_cfg5;
2965 lis2dux12_tap_cfg6_t tap_cfg6;
2966 int32_t ret;
2967
2968 ret = lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2969 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
2970 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
2971 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
2972 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
2973 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
2974 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
2975
2976 if (ret == 0)
2977 {
2978 tap_cfg0.axis = (uint8_t)val.axis;
2979 tap_cfg0.invert_t = val.inverted_peak_time;
2980 tap_cfg1.pre_still_ths = val.pre_still_ths;
2981 tap_cfg3.post_still_ths = val.post_still_ths;
2982 tap_cfg1.post_still_t = val.post_still_time & 0xFU;
2983 tap_cfg2.post_still_t = val.post_still_time >> 4;
2984 tap_cfg2.wait_t = val.shock_wait_time;
2985 tap_cfg3.latency_t = val.latency;
2986 tap_cfg4.wait_end_latency = val.wait_end_latency;
2987 tap_cfg4.peak_ths = val.peak_ths;
2988 tap_cfg5.rebound_t = val.rebound;
2989 tap_cfg5.single_tap_en = val.single_tap_on;
2990 tap_cfg5.double_tap_en = val.double_tap_on;
2991 tap_cfg5.triple_tap_en = val.triple_tap_on;
2992 tap_cfg6.pre_still_st = val.pre_still_start;
2993 tap_cfg6.pre_still_n = val.pre_still_n;
2994
2995 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2996 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
2997 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
2998 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
2999 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3000 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3001 ret += lis2dux12_write_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3002 }
3003
3004 return ret;
3005 }
3006
lis2dux12_tap_config_get(const stmdev_ctx_t * ctx,lis2dux12_tap_config_t * val)3007 int32_t lis2dux12_tap_config_get(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val)
3008 {
3009 lis2dux12_tap_cfg0_t tap_cfg0;
3010 lis2dux12_tap_cfg1_t tap_cfg1;
3011 lis2dux12_tap_cfg2_t tap_cfg2;
3012 lis2dux12_tap_cfg3_t tap_cfg3;
3013 lis2dux12_tap_cfg4_t tap_cfg4;
3014 lis2dux12_tap_cfg5_t tap_cfg5;
3015 lis2dux12_tap_cfg6_t tap_cfg6;
3016 int32_t ret;
3017
3018 ret = lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3019 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3020 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3021 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG3, (uint8_t *)&tap_cfg3, 1);
3022 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG4, (uint8_t *)&tap_cfg4, 1);
3023 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG5, (uint8_t *)&tap_cfg5, 1);
3024 ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_CFG6, (uint8_t *)&tap_cfg6, 1);
3025
3026 if (ret == 0)
3027 {
3028 val->axis = (lis2dux12_axis_t)tap_cfg0.axis;
3029 val->inverted_peak_time = tap_cfg0.invert_t;
3030 val->pre_still_ths = tap_cfg1.pre_still_ths;
3031 val->post_still_ths = tap_cfg3.post_still_ths;
3032 val->post_still_time = (tap_cfg2.post_still_t << 4) | tap_cfg1.post_still_t;
3033 val->shock_wait_time = tap_cfg2.wait_t;
3034 val->latency = tap_cfg3.latency_t;
3035 val->wait_end_latency = tap_cfg4.wait_end_latency;
3036 val->peak_ths = tap_cfg4.peak_ths;
3037 val->rebound = tap_cfg5.rebound_t;
3038 val->single_tap_on = tap_cfg5.single_tap_en;
3039 val->double_tap_on = tap_cfg5.double_tap_en;
3040 val->triple_tap_on = tap_cfg5.triple_tap_en;
3041 val->pre_still_start = tap_cfg6.pre_still_st;
3042 val->pre_still_n = tap_cfg6.pre_still_n;
3043 }
3044
3045 return ret;
3046 }
3047
3048 /**
3049 * @}
3050 *
3051 */
3052
3053 /**
3054 * @defgroup lis2dux12_Timestamp
3055 * @brief This section groups all the functions that manage the
3056 * timestamp generation.
3057 * @{
3058 *
3059 */
3060
3061 /**
3062 * @brief Enables timestamp counter.[set]
3063 *
3064 * @param ctx Read / write interface definitions.(ptr)
3065 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3066 * @retval Interface status (MANDATORY: return 0 -> no Error).
3067 *
3068 */
lis2dux12_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)3069 int32_t lis2dux12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
3070 {
3071 lis2dux12_interrupt_cfg_t int_cfg;
3072 int32_t ret;
3073
3074 ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3075
3076 if (ret == 0)
3077 {
3078 int_cfg.timestamp_en = (uint8_t)val;
3079 ret = lis2dux12_write_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3080 }
3081
3082 return ret;
3083 }
3084
3085 /**
3086 * @brief Enables timestamp counter.[get]
3087 *
3088 * @param ctx Read / write interface definitions.(ptr)
3089 * @param val Change the values of timestamp_en in reg INTERRUPT_CFG
3090 * @retval Interface status (MANDATORY: return 0 -> no Error).
3091 *
3092 */
lis2dux12_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)3093 int32_t lis2dux12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
3094 {
3095 lis2dux12_interrupt_cfg_t int_cfg;
3096 int32_t ret;
3097
3098 ret = lis2dux12_read_reg(ctx, LIS2DUX12_INTERRUPT_CFG, (uint8_t *)&int_cfg, 1);
3099 *val = int_cfg.timestamp_en;
3100
3101 return ret;
3102 }
3103
3104 /**
3105 * @brief Timestamp first data output register (r).
3106 * The value is expressed as a 32-bit word and the bit resolution
3107 * is 10 us.[get]
3108 *
3109 * @param ctx Read / write interface definitions.(ptr)
3110 * @param buff Buffer that stores data read
3111 * @retval Interface status (MANDATORY: return 0 -> no Error).
3112 *
3113 */
lis2dux12_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)3114 int32_t lis2dux12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
3115 {
3116 uint8_t buff[4];
3117 int32_t ret;
3118
3119 ret = lis2dux12_read_reg(ctx, LIS2DUX12_TIMESTAMP0, buff, 4);
3120 *val = buff[3];
3121 *val = (*val * 256U) + buff[2];
3122 *val = (*val * 256U) + buff[1];
3123 *val = (*val * 256U) + buff[0];
3124
3125 return ret;
3126 }
3127
3128 /**
3129 * @}
3130 *
3131 */
3132
3133 /**
3134 * @defgroup LIS2DUX12_finite_state_machine
3135 * @brief This section groups all the functions that manage the
3136 * state_machine.
3137 * @{
3138 *
3139 */
3140
3141 /**
3142 * @brief Interrupt status bit for FSM long counter timeout interrupt
3143 * event.[get]
3144 *
3145 * @param ctx Read / write interface definitions.(ptr)
3146 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
3147 * @retval Interface status (MANDATORY: return 0 -> no Error).
3148 *
3149 */
lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3150 int32_t lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
3151 uint8_t *val)
3152 {
3153 lis2dux12_emb_func_status_t emb_func_status;
3154 int32_t ret;
3155
3156 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3157
3158 if (ret == 0)
3159 {
3160 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS,
3161 (uint8_t *)&emb_func_status, 1);
3162
3163 *val = emb_func_status.is_fsm_lc;
3164 }
3165
3166 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3167
3168 return ret;
3169 }
3170
3171 /**
3172 * @brief Embedded final state machine functions mode.[set]
3173 *
3174 * @param ctx Read / write interface definitions.(ptr)
3175 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
3176 * @retval Interface status (MANDATORY: return 0 -> no Error).
3177 *
3178 */
lis2dux12_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)3179 int32_t lis2dux12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3180 {
3181 int32_t ret;
3182
3183 lis2dux12_emb_func_en_b_t emb_func_en_b;
3184 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3185
3186 if (ret == 0)
3187 {
3188 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3189 (uint8_t *)&emb_func_en_b, 1);
3190
3191 emb_func_en_b.fsm_en = (uint8_t)val;
3192
3193 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3194 (uint8_t *)&emb_func_en_b, 1);
3195 }
3196
3197 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3198
3199 return ret;
3200 }
3201
3202 /**
3203 * @brief Embedded final state machine functions mode.[get]
3204 *
3205 * @param ctx Read / write interface definitions.(ptr)
3206 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
3207 * @retval Interface status (MANDATORY: return 0 -> no Error).
3208 *
3209 */
lis2dux12_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3210 int32_t lis2dux12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3211 {
3212 int32_t ret;
3213
3214 lis2dux12_emb_func_en_b_t emb_func_en_b;
3215 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3216
3217 if (ret == 0)
3218 {
3219 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3220 (uint8_t *)&emb_func_en_b, 1);
3221
3222 *val = emb_func_en_b.fsm_en;
3223
3224 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3225 (uint8_t *)&emb_func_en_b, 1);
3226 }
3227
3228 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3229
3230 return ret;
3231 }
3232
3233 /**
3234 * @brief Embedded final state machine functions mode.[set]
3235 *
3236 * @param ctx Read / write interface definitions.(ptr)
3237 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3238 * @retval Interface status (MANDATORY: return 0 -> no Error).
3239 *
3240 */
lis2dux12_fsm_enable_set(const stmdev_ctx_t * ctx,lis2dux12_emb_fsm_enable_t * val)3241 int32_t lis2dux12_fsm_enable_set(const stmdev_ctx_t *ctx,
3242 lis2dux12_emb_fsm_enable_t *val)
3243 {
3244 lis2dux12_emb_func_en_b_t emb_func_en_b;
3245 int32_t ret;
3246
3247 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3248
3249 if (ret == 0)
3250 {
3251 ret = lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ENABLE,
3252 (uint8_t *)&val->fsm_enable, 1);
3253 }
3254
3255 if (ret == 0)
3256 {
3257 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3258 (uint8_t *)&emb_func_en_b, 1);
3259
3260 if ((val->fsm_enable.fsm1_en |
3261 val->fsm_enable.fsm2_en |
3262 val->fsm_enable.fsm3_en |
3263 val->fsm_enable.fsm4_en |
3264 val->fsm_enable.fsm5_en |
3265 val->fsm_enable.fsm6_en |
3266 val->fsm_enable.fsm7_en |
3267 val->fsm_enable.fsm8_en) != PROPERTY_DISABLE)
3268 {
3269 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
3270 }
3271 else
3272 {
3273 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
3274 }
3275
3276 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B,
3277 (uint8_t *)&emb_func_en_b, 1);
3278 }
3279
3280 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3281
3282 return ret;
3283 }
3284
3285 /**
3286 * @brief Embedded final state machine functions mode.[get]
3287 *
3288 * @param ctx Read / write interface definitions.(ptr)
3289 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
3290 * @retval Interface status (MANDATORY: return 0 -> no Error).
3291 *
3292 */
lis2dux12_fsm_enable_get(const stmdev_ctx_t * ctx,lis2dux12_emb_fsm_enable_t * val)3293 int32_t lis2dux12_fsm_enable_get(const stmdev_ctx_t *ctx,
3294 lis2dux12_emb_fsm_enable_t *val)
3295 {
3296 int32_t ret;
3297
3298 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3299
3300 if (ret == 0)
3301 {
3302 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ENABLE,
3303 (uint8_t *)&val->fsm_enable, 1);
3304 }
3305
3306 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3307
3308 return ret;
3309 }
3310
3311 /**
3312 * @brief FSM long counter status register. Long counter value is an
3313 * unsigned integer value (16-bit format).[set]
3314 *
3315 * @param ctx Read / write interface definitions.(ptr)
3316 * @param buff Buffer that contains data to write
3317 * @retval Interface status (MANDATORY: return 0 -> no Error).
3318 *
3319 */
lis2dux12_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)3320 int32_t lis2dux12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
3321 {
3322 uint8_t buff[2];
3323 int32_t ret;
3324
3325 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3326
3327 if (ret == 0)
3328 {
3329 buff[1] = (uint8_t)(val / 256U);
3330 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3331 ret = lis2dux12_write_reg(ctx, LIS2DUX12_FSM_LONG_COUNTER_L, buff, 2);
3332 }
3333
3334 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3335
3336 return ret;
3337 }
3338
3339 /**
3340 * @brief FSM long counter status register. Long counter value is an
3341 * unsigned integer value (16-bit format).[get]
3342 *
3343 * @param ctx Read / write interface definitions.(ptr)
3344 * @param buff Buffer that stores data read
3345 * @retval Interface status (MANDATORY: return 0 -> no Error).
3346 *
3347 */
lis2dux12_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)3348 int32_t lis2dux12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
3349 {
3350 uint8_t buff[2];
3351 int32_t ret;
3352
3353 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3354
3355 if (ret == 0)
3356 {
3357 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_LONG_COUNTER_L, buff, 2);
3358 *val = buff[1];
3359 *val = (*val * 256U) + buff[0];
3360 }
3361
3362 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3363
3364 return ret;
3365 }
3366
3367 /**
3368 * @brief FSM status.[get]
3369 *
3370 * @param ctx read / write interface definitions
3371 * @param val register FSM_STATUS_MAINPAGE
3372 *
3373 */
lis2dux12_fsm_status_get(const stmdev_ctx_t * ctx,lis2dux12_fsm_status_mainpage_t * val)3374 int32_t lis2dux12_fsm_status_get(const stmdev_ctx_t *ctx,
3375 lis2dux12_fsm_status_mainpage_t *val)
3376 {
3377 return lis2dux12_read_reg(ctx, LIS2DUX12_FSM_STATUS_MAINPAGE,
3378 (uint8_t *) val, 1);
3379 }
3380
3381 /**
3382 * @brief FSM output registers.[get]
3383 *
3384 * @param ctx Read / write interface definitions.(ptr)
3385 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
3386 * @retval Interface status (MANDATORY: return 0 -> no Error).
3387 *
3388 */
lis2dux12_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * val)3389 int32_t lis2dux12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
3390 {
3391 int32_t ret;
3392
3393 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3394
3395 if (ret == 0)
3396 {
3397 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_OUTS1, val, 8);
3398 }
3399
3400 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3401
3402 return ret;
3403 }
3404
3405 /**
3406 * @brief Finite State Machine ODR configuration.[set]
3407 *
3408 * @param ctx Read / write interface definitions.(ptr)
3409 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3410 * @retval Interface status (MANDATORY: return 0 -> no Error).
3411 *
3412 */
lis2dux12_fsm_data_rate_set(const stmdev_ctx_t * ctx,lis2dux12_fsm_val_odr_t val)3413 int32_t lis2dux12_fsm_data_rate_set(const stmdev_ctx_t *ctx,
3414 lis2dux12_fsm_val_odr_t val)
3415 {
3416 lis2dux12_fsm_odr_t fsm_odr_reg;
3417 int32_t ret;
3418
3419 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3420
3421 if (ret == 0)
3422 {
3423 ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR,
3424 (uint8_t *)&fsm_odr_reg, 1);
3425
3426 fsm_odr_reg.fsm_odr = (uint8_t)val;
3427 ret += lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ODR,
3428 (uint8_t *)&fsm_odr_reg, 1);
3429 }
3430
3431 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3432
3433 return ret;
3434 }
3435
3436 /**
3437 * @brief Finite State Machine ODR configuration.[get]
3438 *
3439 * @param ctx Read / write interface definitions.(ptr)
3440 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
3441 * @retval Interface status (MANDATORY: return 0 -> no Error).
3442 *
3443 */
lis2dux12_fsm_data_rate_get(const stmdev_ctx_t * ctx,lis2dux12_fsm_val_odr_t * val)3444 int32_t lis2dux12_fsm_data_rate_get(const stmdev_ctx_t *ctx,
3445 lis2dux12_fsm_val_odr_t *val)
3446 {
3447 lis2dux12_fsm_odr_t fsm_odr_reg;
3448 int32_t ret;
3449
3450 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3451 ret += lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1);
3452 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3453
3454 switch (fsm_odr_reg.fsm_odr)
3455 {
3456 case 0:
3457 *val = LIS2DUX12_ODR_FSM_12Hz5;
3458 break;
3459
3460 case 1:
3461 *val = LIS2DUX12_ODR_FSM_25Hz;
3462 break;
3463
3464 case 2:
3465 *val = LIS2DUX12_ODR_FSM_50Hz;
3466 break;
3467
3468 case 3:
3469 *val = LIS2DUX12_ODR_FSM_100Hz;
3470 break;
3471
3472 case 4:
3473 *val = LIS2DUX12_ODR_FSM_200Hz;
3474 break;
3475
3476 case 5:
3477 *val = LIS2DUX12_ODR_FSM_400Hz;
3478 break;
3479
3480 case 6:
3481 *val = LIS2DUX12_ODR_FSM_800Hz;
3482 break;
3483
3484 default:
3485 *val = LIS2DUX12_ODR_FSM_12Hz5;
3486 break;
3487 }
3488
3489 return ret;
3490 }
3491
3492 /**
3493 * @brief FSM initialization request.[set]
3494 *
3495 * @param ctx Read / write interface definitions.(ptr)
3496 * @param val Change the values of fsm_init in reg FSM_INIT
3497 * @retval Interface status (MANDATORY: return 0 -> no Error).
3498 *
3499 */
lis2dux12_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)3500 int32_t lis2dux12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
3501 {
3502 lis2dux12_emb_func_init_b_t emb_func_init_b;
3503 int32_t ret;
3504
3505 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3506
3507 if (ret == 0)
3508 {
3509 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B,
3510 (uint8_t *)&emb_func_init_b, 1);
3511
3512 emb_func_init_b.fsm_init = (uint8_t)val;
3513
3514 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B,
3515 (uint8_t *)&emb_func_init_b, 1);
3516 }
3517
3518 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @brief FSM initialization request.[get]
3525 *
3526 * @param ctx Read / write interface definitions.(ptr)
3527 * @param val Change the values of fsm_init in reg FSM_INIT
3528 * @retval Interface status (MANDATORY: return 0 -> no Error).
3529 *
3530 */
lis2dux12_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)3531 int32_t lis2dux12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
3532 {
3533 lis2dux12_emb_func_init_b_t emb_func_init_b;
3534 int32_t ret;
3535
3536 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3537
3538 if (ret == 0)
3539 {
3540 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B,
3541 (uint8_t *)&emb_func_init_b, 1);
3542
3543 *val = emb_func_init_b.fsm_init;
3544 }
3545
3546 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3547
3548 return ret;
3549 }
3550
3551 /**
3552 * @brief FSM FIFO en bit.[set]
3553 *
3554 * @param ctx Read / write interface definitions.(ptr)
3555 * @param val Change the value of fsm_fifo_en in reg LIS2DUX12_EMB_FUNC_FIFO_EN
3556 * @retval Interface status (MANDATORY: return 0 -> no Error).
3557 *
3558 */
lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)3559 int32_t lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3560 {
3561 lis2dux12_emb_func_fifo_en_t fifo_reg;
3562 int32_t ret;
3563
3564 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3565
3566 if (ret == 0)
3567 {
3568 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3569 fifo_reg.fsm_fifo_en = val;
3570 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3571 }
3572
3573 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3574
3575 return ret;
3576 }
3577
3578 /**
3579 * @brief FSM FIFO en bit.[get]
3580 *
3581 * @param ctx Read / write interface definitions.(ptr)
3582 * @param val Get the value of fsm_fifo_en in reg LIS2DUX12_EMB_FUNC_FIFO_EN
3583 * @retval Interface status (MANDATORY: return 0 -> no Error).
3584 *
3585 */
lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3586 int32_t lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3587 {
3588 lis2dux12_emb_func_fifo_en_t fifo_reg;
3589 int32_t ret;
3590
3591 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3592
3593 if (ret == 0)
3594 {
3595 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3596 *val = fifo_reg.fsm_fifo_en;
3597 }
3598
3599 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3600
3601 return ret;
3602 }
3603
3604 /**
3605 * @brief FSM long counter timeout register (r/w). The long counter
3606 * timeout value is an unsigned integer value (16-bit format).
3607 * When the long counter value reached this value, the FSM
3608 * generates an interrupt.[set]
3609 *
3610 * @param ctx Read / write interface definitions.(ptr)
3611 * @param buff Buffer that contains data to write
3612 * @retval Interface status (MANDATORY: return 0 -> no Error).
3613 *
3614 */
lis2dux12_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)3615 int32_t lis2dux12_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
3616 uint16_t val)
3617 {
3618 uint8_t buff[2];
3619 int32_t ret;
3620
3621 buff[1] = (uint8_t)(val / 256U);
3622 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3623 ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_LC_TIMEOUT_L, buff, 2);
3624
3625 return ret;
3626 }
3627
3628 /**
3629 * @brief FSM long counter timeout register (r/w). The long counter
3630 * timeout value is an unsigned integer value (16-bit format).
3631 * When the long counter value reached this value, the FSM generates
3632 * an interrupt.[get]
3633 *
3634 * @param ctx Read / write interface definitions.(ptr)
3635 * @param buff Buffer that stores data read
3636 * @retval Interface status (MANDATORY: return 0 -> no Error).
3637 *
3638 */
lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)3639 int32_t lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
3640 uint16_t *val)
3641 {
3642 uint8_t buff[2];
3643 int32_t ret;
3644
3645 ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_LC_TIMEOUT_L, buff, 2);
3646 *val = buff[1];
3647 *val = (*val * 256U) + buff[0];
3648
3649 return ret;
3650 }
3651
3652 /**
3653 * @brief FSM number of programs register.[set]
3654 *
3655 * @param ctx Read / write interface definitions.(ptr)
3656 * @param val Buffer that contains data to write
3657 * @retval Interface status (MANDATORY: return 0 -> no Error).
3658 *
3659 */
lis2dux12_fsm_programs_num_set(const stmdev_ctx_t * ctx,uint8_t val)3660 int32_t lis2dux12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val)
3661 {
3662 int32_t ret;
3663
3664 ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_PROGRAMS, &val, 1);
3665
3666 return ret;
3667 }
3668
3669 /**
3670 * @brief FSM number of programs register.[get]
3671 *
3672 * @param ctx Read / write interface definitions.(ptr)
3673 * @param val Buffer that stores data read
3674 * @retval Interface status (MANDATORY: return 0 -> no Error).
3675 *
3676 */
lis2dux12_fsm_programs_num_get(const stmdev_ctx_t * ctx,uint8_t * val)3677 int32_t lis2dux12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val)
3678 {
3679 int32_t ret;
3680
3681 ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_PROGRAMS, val, 1);
3682
3683 return ret;
3684 }
3685
3686 /**
3687 * @brief FSM start address register (r/w). First available address is
3688 * 0x033C.[set]
3689 *
3690 * @param ctx Read / write interface definitions.(ptr)
3691 * @param buff Buffer that contains data to write
3692 * @retval Interface status (MANDATORY: return 0 -> no Error).
3693 *
3694 */
lis2dux12_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)3695 int32_t lis2dux12_fsm_start_address_set(const stmdev_ctx_t *ctx,
3696 uint16_t val)
3697 {
3698 uint8_t buff[2];
3699 int32_t ret;
3700
3701 buff[1] = (uint8_t)(val / 256U);
3702 buff[0] = (uint8_t)(val - (buff[1] * 256U));
3703 ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_START_ADD_L, buff, 2);
3704
3705 return ret;
3706 }
3707
3708 /**
3709 * @brief FSM start address register (r/w). First available address
3710 * is 0x033C.[get]
3711 *
3712 * @param ctx Read / write interface definitions.(ptr)
3713 * @param buff Buffer that stores data read
3714 * @retval Interface status (MANDATORY: return 0 -> no Error).
3715 *
3716 */
lis2dux12_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)3717 int32_t lis2dux12_fsm_start_address_get(const stmdev_ctx_t *ctx,
3718 uint16_t *val)
3719 {
3720 uint8_t buff[2];
3721 int32_t ret;
3722
3723 ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_START_ADD_L, buff, 2);
3724 *val = buff[1];
3725 *val = (*val * 256U) + buff[0];
3726
3727 return ret;
3728 }
3729
3730 /**
3731 * @}
3732 *
3733 */
3734
3735 /**
3736 * @addtogroup Machine Learning Core
3737 * @brief This section group all the functions concerning the
3738 * usage of Machine Learning Core
3739 * @{
3740 *
3741 */
3742
3743 /**
3744 * @brief Enable Machine Learning Core.[set]
3745 *
3746 * @param ctx read / write interface definitions
3747 * @param val change the values of mlc_en in
3748 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3749 * in EMB_FUNC_INIT_A
3750 *
3751 */
lis2dux12_mlc_set(const stmdev_ctx_t * ctx,lis2dux12_mlc_mode_t val)3752 int32_t lis2dux12_mlc_set(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val)
3753 {
3754 lis2dux12_emb_func_en_a_t emb_en_a;
3755 lis2dux12_emb_func_en_b_t emb_en_b;
3756 int32_t ret;
3757
3758 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3759
3760 if (ret == 0)
3761 {
3762 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3763 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3764
3765 switch (val)
3766 {
3767 case LIS2DUX12_MLC_OFF:
3768 emb_en_a.mlc_before_fsm_en = 0;
3769 emb_en_b.mlc_en = 0;
3770 break;
3771 case LIS2DUX12_MLC_ON:
3772 emb_en_a.mlc_before_fsm_en = 0;
3773 emb_en_b.mlc_en = 1;
3774 break;
3775 case LIS2DUX12_MLC_ON_BEFORE_FSM:
3776 emb_en_a.mlc_before_fsm_en = 1;
3777 emb_en_b.mlc_en = 0;
3778 break;
3779 default:
3780 /* do nothing */
3781 break;
3782 }
3783
3784 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3785 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3786 }
3787
3788 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3789
3790 return ret;
3791 }
3792
3793 /**
3794 * @brief Enable Machine Learning Core.[get]
3795 *
3796 * @param ctx read / write interface definitions
3797 * @param val get the values of mlc_en in
3798 * reg EMB_FUNC_EN_B and mlc_before_fsm_en
3799 * in EMB_FUNC_INIT_A
3800 *
3801 */
lis2dux12_mlc_get(const stmdev_ctx_t * ctx,lis2dux12_mlc_mode_t * val)3802 int32_t lis2dux12_mlc_get(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val)
3803 {
3804 lis2dux12_emb_func_en_a_t emb_en_a;
3805 lis2dux12_emb_func_en_b_t emb_en_b;
3806 int32_t ret;
3807
3808 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3809
3810 if (ret == 0)
3811 {
3812 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
3813 ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
3814
3815 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
3816 {
3817 *val = LIS2DUX12_MLC_OFF;
3818 }
3819 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
3820 {
3821 *val = LIS2DUX12_MLC_ON;
3822 }
3823 else if (emb_en_a.mlc_before_fsm_en == 1U)
3824 {
3825 *val = LIS2DUX12_MLC_ON_BEFORE_FSM;
3826 }
3827 else
3828 {
3829 /* Do nothing */
3830 }
3831 }
3832
3833 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3834
3835 return ret;
3836 }
3837
3838 /**
3839 * @brief Machine Learning Core status register[get]
3840 *
3841 * @param ctx read / write interface definitions
3842 * @param val register MLC_STATUS_MAINPAGE
3843 *
3844 */
lis2dux12_mlc_status_get(const stmdev_ctx_t * ctx,lis2dux12_mlc_status_mainpage_t * val)3845 int32_t lis2dux12_mlc_status_get(const stmdev_ctx_t *ctx,
3846 lis2dux12_mlc_status_mainpage_t *val)
3847 {
3848 return lis2dux12_read_reg(ctx, LIS2DUX12_MLC_STATUS_MAINPAGE,
3849 (uint8_t *) val, 1);
3850 }
3851
3852 /**
3853 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
3854 *
3855 * @param ctx_t *ctx: read / write interface definitions
3856 * @param uint8_t * : buffer that stores data read
3857 *
3858 */
lis2dux12_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)3859 int32_t lis2dux12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
3860 {
3861 int32_t ret;
3862
3863 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3864
3865 if (ret == 0)
3866 {
3867 ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC1_SRC, buff, 4);
3868 }
3869
3870 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3871
3872 return ret;
3873 }
3874
3875 /**
3876 * @brief Machine Learning Core data rate selection.[set]
3877 *
3878 * @param ctx read / write interface definitions
3879 * @param val get the values of mlc_odr in
3880 * reg EMB_FUNC_ODR_CFG_C
3881 *
3882 */
lis2dux12_mlc_data_rate_set(const stmdev_ctx_t * ctx,lis2dux12_mlc_odr_val_t val)3883 int32_t lis2dux12_mlc_data_rate_set(const stmdev_ctx_t *ctx,
3884 lis2dux12_mlc_odr_val_t val)
3885 {
3886 lis2dux12_mlc_odr_t reg;
3887 int32_t ret;
3888
3889 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3890
3891 if (ret == 0)
3892 {
3893 ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1);
3894 reg.mlc_odr = (uint8_t)val;
3895 ret += lis2dux12_write_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1);
3896 }
3897
3898 if (ret == 0)
3899 {
3900 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3901 }
3902
3903 return ret;
3904 }
3905
3906 /**
3907 * @brief Machine Learning Core data rate selection.[get]
3908 *
3909 * @param ctx read / write interface definitions
3910 * @param val change the values of mlc_odr in
3911 * reg EMB_FUNC_ODR_CFG_C
3912 *
3913 */
lis2dux12_mlc_data_rate_get(const stmdev_ctx_t * ctx,lis2dux12_mlc_odr_val_t * val)3914 int32_t lis2dux12_mlc_data_rate_get(const stmdev_ctx_t *ctx,
3915 lis2dux12_mlc_odr_val_t *val)
3916 {
3917 lis2dux12_mlc_odr_t reg;
3918 int32_t ret;
3919
3920 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3921
3922 if (ret == 0)
3923 {
3924 ret = lis2dux12_read_reg(ctx, LIS2DUX12_MLC_ODR, (uint8_t *)®, 1);
3925
3926 switch (reg.mlc_odr)
3927 {
3928 case 0:
3929 *val = LIS2DUX12_ODR_PRGS_12Hz5;
3930 break;
3931
3932 case 1:
3933 *val = LIS2DUX12_ODR_PRGS_25Hz;
3934 break;
3935
3936 case 2:
3937 *val = LIS2DUX12_ODR_PRGS_50Hz;
3938 break;
3939
3940 case 3:
3941 *val = LIS2DUX12_ODR_PRGS_100Hz;
3942 break;
3943
3944 case 4:
3945 *val = LIS2DUX12_ODR_PRGS_200Hz;
3946 break;
3947
3948 default:
3949 *val = LIS2DUX12_ODR_PRGS_12Hz5;
3950 break;
3951 }
3952 }
3953
3954 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3955
3956 return ret;
3957 }
3958
3959 /**
3960 * @brief MLC FIFO en bit.[set]
3961 *
3962 * @param ctx Read / write interface definitions.(ptr)
3963 * @param val Change the value of mlc_fifo_en in reg LIS2DUX12_EMB_FUNC_FIFO_EN
3964 * @retval Interface status (MANDATORY: return 0 -> no Error).
3965 *
3966 */
lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t * ctx,uint8_t val)3967 int32_t lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val)
3968 {
3969 lis2dux12_emb_func_fifo_en_t fifo_reg;
3970 int32_t ret;
3971
3972 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
3973
3974 if (ret == 0)
3975 {
3976 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3977 fifo_reg.mlc_fifo_en = val;
3978 ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
3979 }
3980
3981 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
3982
3983 return ret;
3984 }
3985
3986 /**
3987 * @brief MLC FIFO en bit.[get]
3988 *
3989 * @param ctx Read / write interface definitions.(ptr)
3990 * @param val Get the value of mlc_fifo_en in reg LIS2DUX12_EMB_FUNC_FIFO_EN
3991 * @retval Interface status (MANDATORY: return 0 -> no Error).
3992 *
3993 */
lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t * ctx,uint8_t * val)3994 int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
3995 {
3996 lis2dux12_emb_func_fifo_en_t fifo_reg;
3997 int32_t ret;
3998
3999 ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK);
4000
4001 if (ret == 0)
4002 {
4003 ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&fifo_reg, 1);
4004 *val = fifo_reg.mlc_fifo_en;
4005 }
4006
4007 ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK);
4008
4009 return ret;
4010 }
4011
4012 /**
4013 * @}
4014 *
4015 */
4016
4017 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4018
