1 /* 2 ****************************************************************************** 3 * @file lis2du12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2du12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DU12_REGS_H 23 #define LIS2DU12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DU12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LIS2DU12_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ 172 #define LIS2DU12_I2C_ADD_L 0x31U 173 #define LIS2DU12_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define LIS2DU12_ID 0x45U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LIS2DU12_IF_PU_CTRL 0x0CU 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 2; 188 uint8_t cs_pu_disc : 1; 189 uint8_t not_used_02 : 3; 190 uint8_t sda_pu_en : 1; 191 uint8_t sdo_pu_disc : 1; 192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 193 uint8_t sdo_pu_disc : 1; 194 uint8_t sda_pu_en : 1; 195 uint8_t not_used_02 : 3; 196 uint8_t cs_pu_disc : 1; 197 uint8_t not_used_01 : 2; 198 #endif /* DRV_BYTE_ORDER */ 199 } lis2du12_if_pu_ctrl_t; 200 201 #define LIS2DU12_IF_CTRL 0x0EU 202 typedef struct 203 { 204 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 205 uint8_t i2c_disable : 1; 206 uint8_t i3c_disable : 1; 207 uint8_t pd_dis_int1 : 1; 208 uint8_t not_used_01 : 5; 209 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 210 uint8_t not_used_01 : 5; 211 uint8_t pd_dis_int1 : 1; 212 uint8_t i3c_disable : 1; 213 uint8_t i2c_disable : 1; 214 #endif /* DRV_BYTE_ORDER */ 215 } lis2du12_if_ctrl_t; 216 217 #define LIS2DU12_CTRL1 0x10U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t wu_z_en : 1; 222 uint8_t wu_y_en : 1; 223 uint8_t wu_x_en : 1; 224 uint8_t drdy_pulsed : 1; 225 uint8_t if_add_inc : 1; 226 uint8_t sw_reset : 1; 227 uint8_t sim : 1; 228 uint8_t pp_od : 1; 229 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 230 uint8_t pp_od : 1; 231 uint8_t sim : 1; 232 uint8_t sw_reset : 1; 233 uint8_t if_add_inc : 1; 234 uint8_t drdy_pulsed : 1; 235 uint8_t wu_x_en : 1; 236 uint8_t wu_y_en : 1; 237 uint8_t wu_z_en : 1; 238 #endif /* DRV_BYTE_ORDER */ 239 } lis2du12_ctrl1_t; 240 241 #define LIS2DU12_CTRL2 0x11U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t not_used_01 : 3; 246 uint8_t int1_drdy : 1; 247 uint8_t int1_f_ovr : 1; 248 uint8_t int1_f_fth : 1; 249 uint8_t int1_f_full : 1; 250 uint8_t int1_boot : 1; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t int1_boot : 1; 253 uint8_t int1_f_full : 1; 254 uint8_t int1_f_fth : 1; 255 uint8_t int1_f_ovr : 1; 256 uint8_t int1_drdy : 1; 257 uint8_t not_used_01 : 3; 258 #endif /* DRV_BYTE_ORDER */ 259 } lis2du12_ctrl2_t; 260 261 #define LIS2DU12_CTRL3 0x12U 262 typedef struct 263 { 264 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 265 uint8_t st : 2; 266 uint8_t not_used_01 : 1; 267 uint8_t int2_drdy : 1; 268 uint8_t int2_f_ovr : 1; 269 uint8_t int2_f_fth : 1; 270 uint8_t int2_f_full : 1; 271 uint8_t int2_boot : 1; 272 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 273 uint8_t int2_boot : 1; 274 uint8_t int2_f_full : 1; 275 uint8_t int2_f_fth : 1; 276 uint8_t int2_f_ovr : 1; 277 uint8_t int2_drdy : 1; 278 uint8_t not_used_01 : 1; 279 uint8_t st : 2; 280 #endif /* DRV_BYTE_ORDER */ 281 } lis2du12_ctrl3_t; 282 283 #define LIS2DU12_CTRL4 0x13U 284 typedef struct 285 { 286 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 287 uint8_t boot : 1; 288 uint8_t soc : 1; 289 uint8_t not_used_01 : 3; 290 uint8_t bdu : 1; 291 uint8_t inact_odr : 2; 292 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 293 uint8_t inact_odr : 2; 294 uint8_t bdu : 1; 295 uint8_t not_used_01 : 3; 296 uint8_t soc : 1; 297 uint8_t boot : 1; 298 #endif /* DRV_BYTE_ORDER */ 299 } lis2du12_ctrl4_t; 300 301 #define LIS2DU12_CTRL5 0x14U 302 typedef struct 303 { 304 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 305 uint8_t fs : 2; 306 uint8_t bw : 2; 307 uint8_t odr : 4; 308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 309 uint8_t odr : 4; 310 uint8_t bw : 2; 311 uint8_t fs : 2; 312 #endif /* DRV_BYTE_ORDER */ 313 } lis2du12_ctrl5_t; 314 315 #define LIS2DU12_FIFO_CTRL 0x15U 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t f_mode : 3; 320 uint8_t stop_on_fth : 1; 321 uint8_t not_used_01 : 2; 322 uint8_t fifo_depth : 1; 323 uint8_t rounding_xyz : 1; 324 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 325 uint8_t rounding_xyz : 1; 326 uint8_t fifo_depth : 1; 327 uint8_t not_used_01 : 2; 328 uint8_t stop_on_fth : 1; 329 uint8_t f_mode : 3; 330 #endif /* DRV_BYTE_ORDER */ 331 } lis2du12_fifo_ctrl_t; 332 333 #define LIS2DU12_FIFO_WTM 0x16U 334 typedef struct 335 { 336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 337 uint8_t fth : 7; 338 uint8_t not_used_01 : 1; 339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 340 uint8_t not_used_01 : 1; 341 uint8_t fth : 7; 342 #endif /* DRV_BYTE_ORDER */ 343 } lis2du12_fifo_wtm_t; 344 345 #define LIS2DU12_INTERRUPT_CFG 0x17U 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t interrupts_enable : 1; 350 uint8_t lir : 1; 351 uint8_t h_lactive : 1; 352 uint8_t sleep_status_on_int : 1; 353 uint8_t not_used_01 : 1; 354 uint8_t wake_ths_w : 1; 355 uint8_t int_short_en : 1; 356 uint8_t not_used_02 : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used_02 : 1; 359 uint8_t int_short_en : 1; 360 uint8_t wake_ths_w : 1; 361 uint8_t not_used_01 : 1; 362 uint8_t sleep_status_on_int : 1; 363 uint8_t h_lactive : 1; 364 uint8_t lir : 1; 365 uint8_t interrupts_enable : 1; 366 #endif /* DRV_BYTE_ORDER */ 367 } lis2du12_interrupt_cfg_t; 368 369 #define LIS2DU12_TAP_THS_X 0x18U 370 typedef struct 371 { 372 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 373 uint8_t tap_ths_x : 5; 374 uint8_t d6d_ths : 2; 375 uint8_t d4d_en : 1; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t d4d_en : 1; 378 uint8_t d6d_ths : 2; 379 uint8_t tap_ths_x : 5; 380 #endif /* DRV_BYTE_ORDER */ 381 } lis2du12_tap_ths_x_t; 382 383 #define LIS2DU12_TAP_THS_Y 0x19U 384 typedef struct 385 { 386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 387 uint8_t tap_ths_y : 5; 388 uint8_t tap_priority : 3; 389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 390 uint8_t tap_priority : 3; 391 uint8_t tap_ths_y : 5; 392 #endif /* DRV_BYTE_ORDER */ 393 } lis2du12_tap_ths_y_t; 394 395 #define LIS2DU12_TAP_THS_Z 0x1AU 396 typedef struct 397 { 398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 399 uint8_t tap_ths_z : 5; 400 uint8_t tap_z_en : 1; 401 uint8_t tap_y_en : 1; 402 uint8_t tap_x_en : 1; 403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 404 uint8_t tap_x_en : 1; 405 uint8_t tap_y_en : 1; 406 uint8_t tap_z_en : 1; 407 uint8_t tap_ths_z : 5; 408 #endif /* DRV_BYTE_ORDER */ 409 } lis2du12_tap_ths_z_t; 410 411 #define LIS2DU12_INT_DUR 0x1BU 412 typedef struct 413 { 414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 415 uint8_t shock : 2; 416 uint8_t quiet : 2; 417 uint8_t latency : 4; 418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 419 uint8_t latency : 4; 420 uint8_t quiet : 2; 421 uint8_t shock : 2; 422 #endif /* DRV_BYTE_ORDER */ 423 } lis2du12_int_dur_t; 424 425 #define LIS2DU12_WAKE_UP_THS 0x1CU 426 typedef struct 427 { 428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 429 uint8_t wk_ths : 6; 430 uint8_t sleep_on : 1; 431 uint8_t single_double_tap : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t single_double_tap : 1; 434 uint8_t sleep_on : 1; 435 uint8_t wk_ths : 6; 436 #endif /* DRV_BYTE_ORDER */ 437 } lis2du12_wake_up_ths_t; 438 439 #define LIS2DU12_WAKE_UP_DUR 0x1DU 440 typedef struct 441 { 442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 443 uint8_t sleep_dur : 4; 444 uint8_t not_used_01 : 1; 445 uint8_t wake_dur : 2; 446 uint8_t ff_dur : 1; 447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 448 uint8_t ff_dur : 1; 449 uint8_t wake_dur : 2; 450 uint8_t not_used_01 : 1; 451 uint8_t sleep_dur : 4; 452 #endif /* DRV_BYTE_ORDER */ 453 } lis2du12_wake_up_dur_t; 454 455 #define LIS2DU12_FREE_FALL 0x1EU 456 typedef struct 457 { 458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 459 uint8_t ff_ths : 3; 460 uint8_t ff_dur : 5; 461 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 462 uint8_t ff_dur : 5; 463 uint8_t ff_ths : 3; 464 #endif /* DRV_BYTE_ORDER */ 465 } lis2du12_free_fall_t; 466 467 #define LIS2DU12_MD1_CFG 0x1FU 468 typedef struct 469 { 470 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 471 uint8_t not_used_01 : 1; 472 uint8_t wu_dur_x4 : 1; 473 uint8_t int1_6d : 1; 474 uint8_t int1_double_tap : 1; 475 uint8_t int1_ff : 1; 476 uint8_t int1_wu : 1; 477 uint8_t int1_single_tap : 1; 478 uint8_t int1_sleep_change : 1; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t int1_sleep_change : 1; 481 uint8_t int1_single_tap : 1; 482 uint8_t int1_wu : 1; 483 uint8_t int1_ff : 1; 484 uint8_t int1_double_tap : 1; 485 uint8_t int1_6d : 1; 486 uint8_t wu_dur_x4 : 1; 487 uint8_t not_used_01 : 1; 488 #endif /* DRV_BYTE_ORDER */ 489 } lis2du12_md1_cfg_t; 490 491 #define LIS2DU12_MD2_CFG 0x20U 492 typedef struct 493 { 494 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 495 uint8_t not_used_01 : 1; 496 uint8_t pd_dis_int2 : 1; 497 uint8_t int2_6d : 1; 498 uint8_t int2_double_tap : 1; 499 uint8_t int2_ff : 1; 500 uint8_t int2_wu : 1; 501 uint8_t int2_single_tap : 1; 502 uint8_t int2_sleep_change : 1; 503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 504 uint8_t int2_sleep_change : 1; 505 uint8_t int2_single_tap : 1; 506 uint8_t int2_wu : 1; 507 uint8_t int2_ff : 1; 508 uint8_t int2_double_tap : 1; 509 uint8_t int2_6d : 1; 510 uint8_t pd_dis_int2 : 1; 511 uint8_t not_used_01 : 1; 512 #endif /* DRV_BYTE_ORDER */ 513 } lis2du12_md2_cfg_t; 514 515 #define LIS2DU12_WAKE_UP_SRC 0x21U 516 typedef struct 517 { 518 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 519 uint8_t z_wu : 1; 520 uint8_t y_wu : 1; 521 uint8_t x_wu : 1; 522 uint8_t wu_ia : 1; 523 uint8_t sleep_state : 1; 524 uint8_t ff_ia : 1; 525 uint8_t sleep_change_ia : 1; 526 uint8_t not_used_01 : 1; 527 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 528 uint8_t not_used_01 : 1; 529 uint8_t sleep_change_ia : 1; 530 uint8_t ff_ia : 1; 531 uint8_t sleep_state : 1; 532 uint8_t wu_ia : 1; 533 uint8_t x_wu : 1; 534 uint8_t y_wu : 1; 535 uint8_t z_wu : 1; 536 #endif /* DRV_BYTE_ORDER */ 537 } lis2du12_wake_up_src_t; 538 539 #define LIS2DU12_TAP_SRC 0x22U 540 typedef struct 541 { 542 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 543 uint8_t z_tap : 1; 544 uint8_t y_tap : 1; 545 uint8_t x_tap : 1; 546 uint8_t tap_sign : 1; 547 uint8_t double_tap_ia : 1; 548 uint8_t single_tap_ia : 1; 549 uint8_t tap_ia : 1; 550 uint8_t not_used_01 : 1; 551 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 552 uint8_t not_used_01 : 1; 553 uint8_t tap_ia : 1; 554 uint8_t single_tap_ia : 1; 555 uint8_t double_tap_ia : 1; 556 uint8_t tap_sign : 1; 557 uint8_t x_tap : 1; 558 uint8_t y_tap : 1; 559 uint8_t z_tap : 1; 560 #endif /* DRV_BYTE_ORDER */ 561 } lis2du12_tap_src_t; 562 563 #define LIS2DU12_SIXD_SRC 0x23U 564 typedef struct 565 { 566 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 567 uint8_t xl : 1; 568 uint8_t xh : 1; 569 uint8_t yl : 1; 570 uint8_t yh : 1; 571 uint8_t zl : 1; 572 uint8_t zh : 1; 573 uint8_t d6d_ia : 1; 574 uint8_t not_used_01 : 1; 575 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 576 uint8_t not_used_01 : 1; 577 uint8_t d6d_ia : 1; 578 uint8_t zh : 1; 579 uint8_t zl : 1; 580 uint8_t yh : 1; 581 uint8_t yl : 1; 582 uint8_t xh : 1; 583 uint8_t xl : 1; 584 #endif /* DRV_BYTE_ORDER */ 585 } lis2du12_sixd_src_t; 586 587 #define LIS2DU12_ALL_INT_SRC 0x24U 588 typedef struct 589 { 590 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 591 uint8_t ff_ia_all : 1; 592 uint8_t wu_ia_all : 1; 593 uint8_t single_tap_all : 1; 594 uint8_t double_tap_all : 1; 595 uint8_t d6d_ia_all : 1; 596 uint8_t sleep_change_ia_all : 1; 597 uint8_t int_global : 1; 598 uint8_t not_used_01 : 1; 599 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 600 uint8_t not_used_01 : 1; 601 uint8_t int_global : 1; 602 uint8_t sleep_change_ia_all : 1; 603 uint8_t d6d_ia_all : 1; 604 uint8_t double_tap_all : 1; 605 uint8_t single_tap_all : 1; 606 uint8_t wu_ia_all : 1; 607 uint8_t ff_ia_all : 1; 608 #endif /* DRV_BYTE_ORDER */ 609 } lis2du12_all_int_src_t; 610 611 #define LIS2DU12_STATUS 0x25U 612 typedef struct 613 { 614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 615 uint8_t drdy : 1; 616 uint8_t pd_status : 1; 617 uint8_t not_used_01 : 6; 618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 619 uint8_t not_used_01 : 6; 620 uint8_t pd_status : 1; 621 uint8_t drdy : 1; 622 #endif /* DRV_BYTE_ORDER */ 623 } lis2du12_status_register_t; 624 625 #define LIS2DU12_FIFO_STATUS1 0x26U 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t not_used_01 : 6; 630 uint8_t fifo_ovr : 1; 631 uint8_t fth : 1; 632 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 633 uint8_t fth : 1; 634 uint8_t fifo_ovr : 1; 635 uint8_t not_used_01 : 6; 636 #endif /* DRV_BYTE_ORDER */ 637 } lis2du12_fifo_status1_t; 638 639 #define LIS2DU12_FIFO_STATUS2 0x27U 640 typedef struct 641 { 642 uint8_t fss : 8; 643 } lis2du12_fifo_status2_t; 644 645 #define LIS2DU12_OUTX_L 0x28U 646 #define LIS2DU12_OUTX_H 0x29U 647 #define LIS2DU12_OUTY_L 0x2AU 648 #define LIS2DU12_OUTY_H 0x2BU 649 #define LIS2DU12_OUTZ_L 0x2CU 650 #define LIS2DU12_OUTZ_H 0x2DU 651 #define LIS2DU12_OUTT_L 0x2EU 652 #define LIS2DU12_OUTT_H 0x2FU 653 #define LIS2DU12_TEMP_OUT_L 0x30U 654 #define LIS2DU12_TEMP_OUT_H 0x31U 655 #define LIS2DU12_WHO_AM_I 0x43U 656 657 #define LIS2DU12_ST_SIGN 0x58U 658 typedef struct 659 { 660 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 661 uint8_t not_used_01 : 5; 662 uint8_t stsign : 3; 663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 664 uint8_t stsign : 3; 665 uint8_t not_used_01 : 5; 666 #endif /* DRV_BYTE_ORDER */ 667 } lis2du12_st_sign_t; 668 669 /** 670 * @defgroup LIS2DU12_Register_Union 671 * @brief This union group all the registers that has a bitfield 672 * description. 673 * This union is useful but not need by the driver. 674 * 675 * REMOVING this union you are compliant with: 676 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 677 * 678 * @{ 679 * 680 */ 681 682 typedef union 683 { 684 lis2du12_if_pu_ctrl_t if_pu_ctrl; 685 lis2du12_if_ctrl_t if_ctrl; 686 lis2du12_ctrl1_t ctrl1; 687 lis2du12_ctrl2_t ctrl2; 688 lis2du12_ctrl3_t ctrl3; 689 lis2du12_ctrl4_t ctrl4; 690 lis2du12_ctrl5_t ctrl5; 691 lis2du12_fifo_ctrl_t fifo_ctrl; 692 lis2du12_fifo_wtm_t fifo_wtm; 693 lis2du12_interrupt_cfg_t interrupt_cfg; 694 lis2du12_tap_ths_x_t tap_ths_x; 695 lis2du12_tap_ths_y_t tap_ths_y; 696 lis2du12_tap_ths_z_t tap_ths_z; 697 lis2du12_int_dur_t int_dur; 698 lis2du12_wake_up_ths_t wake_up_ths; 699 lis2du12_wake_up_dur_t wake_up_dur; 700 lis2du12_free_fall_t free_fall; 701 lis2du12_md1_cfg_t md1_cfg; 702 lis2du12_md2_cfg_t md2_cfg; 703 lis2du12_wake_up_src_t wake_up_src; 704 lis2du12_tap_src_t tap_src; 705 lis2du12_sixd_src_t sixd_src; 706 lis2du12_all_int_src_t all_int_src; 707 lis2du12_status_register_t status_register; 708 lis2du12_fifo_status1_t fifo_status1; 709 lis2du12_fifo_status2_t fifo_status2; 710 bitwise_t bitwise; 711 uint8_t byte; 712 } lis2du12_reg_t; 713 714 /** 715 * @} 716 * 717 */ 718 719 #ifndef __weak 720 #define __weak __attribute__((weak)) 721 #endif /* __weak */ 722 723 /* 724 * These are the basic platform dependent I/O routines to read 725 * and write device registers connected on a standard bus. 726 * The driver keeps offering a default implementation based on function 727 * pointers to read/write routines for backward compatibility. 728 * The __weak directive allows the final application to overwrite 729 * them with a custom implementation. 730 */ 731 732 int32_t lis2du12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 733 uint16_t len); 734 int32_t lis2du12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 735 uint16_t len); 736 737 float_t lis2du12_from_fs2g_to_mg(int16_t lsb); 738 float_t lis2du12_from_fs4g_to_mg(int16_t lsb); 739 float_t lis2du12_from_fs8g_to_mg(int16_t lsb); 740 float_t lis2du12_from_fs16g_to_mg(int16_t lsb); 741 float_t lis2du12_from_lsb_to_celsius(int16_t lsb); 742 743 typedef struct 744 { 745 uint8_t whoami; 746 } lis2du12_id_t; 747 int32_t lis2du12_id_get(const stmdev_ctx_t *ctx, lis2du12_id_t *val); 748 749 typedef enum 750 { 751 LIS2DU12_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 752 LIS2DU12_SPI_4W = 0x03, /* Only SPI: SDO / SDI separated pins */ 753 LIS2DU12_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 754 LIS2DU12_I3C_DISABLE = 0x01, /* Select by HW (SPI 3W and I3C disable) */ 755 } lis2du12_bus_mode_t; 756 int32_t lis2du12_bus_mode_set(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t val); 757 int32_t lis2du12_bus_mode_get(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val); 758 759 typedef enum 760 { 761 LIS2DU12_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 762 LIS2DU12_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 763 LIS2DU12_RESET = 0x02, /* Reset configuration registers */ 764 } lis2du12_init_t; 765 int32_t lis2du12_init_set(const stmdev_ctx_t *ctx, lis2du12_init_t val); 766 767 typedef struct 768 { 769 uint8_t sw_reset : 1; /* Restoring configuration registers */ 770 uint8_t boot : 1; /* Restoring calibration parameters */ 771 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 772 uint8_t power_down : 1; /* Monitors power-down. */ 773 } lis2du12_status_t; 774 int32_t lis2du12_status_get(const stmdev_ctx_t *ctx, lis2du12_status_t *val); 775 776 typedef struct 777 { 778 uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ 779 uint8_t sda_pull_up : 1; /* 1 = pull up enable */ 780 uint8_t cs_pull_up : 1; /* 1 = pull up enable */ 781 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 782 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 783 uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 784 } lis2du12_pin_conf_t; 785 int32_t lis2du12_pin_conf_set(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); 786 int32_t lis2du12_pin_conf_get(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); 787 788 typedef struct 789 { 790 uint8_t free_fall : 1; /* free fall event */ 791 uint8_t wake_up : 1; /* wake up event */ 792 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 793 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 794 uint8_t wake_up_x : 1; /* wake up on X axis event */ 795 uint8_t single_tap : 1; /* single-tap event */ 796 uint8_t double_tap : 1; /* double-tap event */ 797 uint8_t tap_z : 1; /* single-tap on Z axis event */ 798 uint8_t tap_y : 1; /* single-tap on Y axis event */ 799 uint8_t tap_x : 1; /* single-tap on X axis event */ 800 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 801 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 802 uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ 803 uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ 804 uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ 805 uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ 806 uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ 807 uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ 808 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 809 uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 810 } lis2du12_all_sources_t; 811 int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, 812 lis2du12_all_sources_t *val); 813 814 typedef enum 815 { 816 LIS2DU12_OFF = 0x00, /* in power down */ 817 LIS2DU12_1Hz6_ULP = 0x01, /* @1Hz6(ultralow power) */ 818 LIS2DU12_3Hz_ULP = 0x02, /* @3Hz (ultralow power) */ 819 LIS2DU12_6Hz_ULP = 0x03, /* @6Hz (ultralow power) */ 820 LIS2DU12_6Hz = 0x04, /* @6Hz (normal) */ 821 LIS2DU12_12Hz5 = 0x05, /* @12Hz5 (normal) */ 822 LIS2DU12_25Hz = 0x06, /* @25Hz (normal) */ 823 LIS2DU12_50Hz = 0x07, /* @50Hz (normal) */ 824 LIS2DU12_100Hz = 0x08, /* @100Hz (normal) */ 825 LIS2DU12_200Hz = 0x09, /* @200Hz (normal) */ 826 LIS2DU12_400Hz = 0x0A, /* @400Hz (normal) */ 827 LIS2DU12_800Hz = 0x0B, /* @800Hz (normal) */ 828 LIS2DU12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ 829 LIS2DU12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ 830 } lis2du12_odr_t; 831 832 typedef enum 833 { 834 LIS2DU12_2g = 0, 835 LIS2DU12_4g = 1, 836 LIS2DU12_8g = 2, 837 LIS2DU12_16g = 3, 838 } lis2du12_fs_t; 839 840 typedef enum 841 { 842 LIS2DU12_ODR_div_2 = 0, 843 LIS2DU12_ODR_div_4 = 1, 844 LIS2DU12_ODR_div_8 = 2, 845 LIS2DU12_ODR_div_16 = 3, 846 } lis2du12_bw_t; 847 848 typedef struct 849 { 850 lis2du12_odr_t odr; 851 lis2du12_fs_t fs; 852 lis2du12_bw_t bw; 853 } lis2du12_md_t; 854 int32_t lis2du12_mode_set(const stmdev_ctx_t *ctx, lis2du12_md_t *val); 855 int32_t lis2du12_mode_get(const stmdev_ctx_t *ctx, lis2du12_md_t *val); 856 857 int32_t lis2du12_trigger_sw(const stmdev_ctx_t *ctx, lis2du12_md_t *val); 858 859 typedef struct 860 { 861 struct 862 { 863 float_t mg[3]; 864 int16_t raw[3]; 865 } xl; 866 struct 867 { 868 float_t deg_c; 869 int16_t raw; 870 } heat; 871 } lis2du12_data_t; 872 int32_t lis2du12_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, 873 lis2du12_data_t *data); 874 875 typedef enum 876 { 877 LIS2DU12_ST_DISABLE = 0, 878 LIS2DU12_ST_POSITIVE = 6, 879 LIS2DU12_ST_NEGATIVE = 1, 880 } lis2du12_st_t; 881 int32_t lis2du12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2du12_st_t val); 882 int32_t lis2du12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); /* valid values: 1 or 2 */ 883 int32_t lis2du12_self_test_stop(const stmdev_ctx_t *ctx); 884 885 typedef enum 886 { 887 LIS2DU12_BYPASS = 0, 888 LIS2DU12_FIFO = 1, 889 LIS2DU12_STREAM = 6, 890 LIS2DU12_STREAM_TO_FIFO = 3, /* Dynamic-Stream, FIFO on Trigger */ 891 LIS2DU12_BYPASS_TO_STREAM = 4, /* Bypass, Dynamic-Stream on Trigger */ 892 LIS2DU12_BYPASS_TO_FIFO = 7, /* Bypass, FIFO on Trigger */ 893 } lis2du12_fifo_operation_t; 894 895 typedef enum 896 { 897 LIS2DU12_8_BIT = 0, 898 LIS2DU12_16_BIT = 1, 899 } lis2du12_fifo_store_t; 900 901 typedef struct 902 { 903 lis2du12_fifo_operation_t operation; 904 lis2du12_fifo_store_t store; 905 uint8_t watermark; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ 906 } lis2du12_fifo_md_t; 907 int32_t lis2du12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); 908 int32_t lis2du12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); 909 910 typedef struct 911 { 912 uint8_t fifo_fth : 1; /* 1 = fifo threshold event */ 913 uint8_t fifo_ovr : 1; /* 1 = fifo overrun event */ 914 } lis2du12_fifo_status_t; 915 int32_t lis2du12_fifo_status_get(const stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val); 916 917 int32_t lis2du12_fifo_level_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, 918 uint8_t *val); 919 920 typedef struct 921 { 922 struct 923 { 924 float_t mg[3]; 925 int16_t raw[3]; 926 } xl[2]; 927 struct 928 { 929 float_t deg_c; 930 int16_t raw; 931 } heat; 932 } lis2du12_fifo_data_t; 933 int32_t lis2du12_fifo_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, 934 lis2du12_fifo_md_t *fmd, 935 lis2du12_fifo_data_t *data); 936 937 typedef enum 938 { 939 LIS2DU12_INT_LEVEL = 0, /* active till event condition persist */ 940 LIS2DU12_INT_LATCHED = 3, /* read ALL_INT_SRC for reset (API all_sources)*/ 941 } lis2du12_base_sig_t; /* base functions are: FF, WU(W2S), 4/6D, Tap */ 942 943 typedef struct 944 { 945 uint8_t enable : 1; /* 1 = enabled / 0 = disabled */ 946 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 947 uint8_t drdy_latched : 1; /* drdy returns to 0 after reading data */ 948 lis2du12_base_sig_t base_sig; 949 } lis2du12_int_mode_t; 950 int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx, 951 lis2du12_int_mode_t *val); 952 int32_t lis2du12_interrupt_mode_get(const stmdev_ctx_t *ctx, 953 lis2du12_int_mode_t *val); 954 955 typedef struct 956 { 957 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 958 uint8_t boot : 1; /* Restoring calibration parameters */ 959 uint8_t fifo_th : 1; /* FIFO threshold reached */ 960 uint8_t fifo_ovr : 1; /* FIFO overrun */ 961 uint8_t fifo_full : 1; /* FIFO full */ 962 uint8_t free_fall : 1; /* free fall event */ 963 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 964 uint8_t single_tap : 1; /* single-tap event */ 965 uint8_t double_tap : 1; /* double tap event */ 966 uint8_t wake_up : 1; /* wake up event */ 967 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 968 uint8_t sleep_state : 1; /* Act/Inact status flag */ 969 } lis2du12_pin_int_route_t; 970 int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx, 971 lis2du12_pin_int_route_t *val); 972 int32_t lis2du12_pin_int1_route_get(const stmdev_ctx_t *ctx, 973 lis2du12_pin_int_route_t *val); 974 975 int32_t lis2du12_pin_int2_route_set(const stmdev_ctx_t *ctx, 976 lis2du12_pin_int_route_t *val); 977 int32_t lis2du12_pin_int2_route_get(const stmdev_ctx_t *ctx, 978 lis2du12_pin_int_route_t *val); 979 980 typedef enum 981 { 982 LIS2DU12_DO_NOT_CHANGE = 0, 983 LIS2DU12_SLEEP_AT_6Hz = 1, 984 LIS2DU12_SLEEP_AT_3Hz = 2, 985 LIS2DU12_SLEEP_AT_1Hz6 = 3, 986 } lis2du12_sleep_odr_t; 987 988 typedef struct 989 { 990 uint8_t x_en : 1; /* Detection on X-axis */ 991 uint8_t y_en : 1; /* Detection on Y-axis */ 992 uint8_t z_en : 1; /* Detection on Z-axis */ 993 uint8_t threshold; /* full scale dependent */ 994 uint8_t duration; /* 1 LSb: 1 ODR_time */ 995 struct 996 { 997 uint8_t en : 1; /* Enable sleep detection */ 998 uint8_t duration; /* 0 is 16 ODR_time, 1 LSB: 512 ODR_time. */ 999 lis2du12_sleep_odr_t odr; 1000 } sleep; 1001 } lis2du12_wkup_md_t; 1002 int32_t lis2du12_wake_up_mode_set(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); 1003 int32_t lis2du12_wake_up_mode_get(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); 1004 1005 typedef enum 1006 { 1007 LIS2DU12_XYZ = 0, 1008 LIS2DU12_YXZ = 1, 1009 LIS2DU12_XZY = 2, 1010 LIS2DU12_ZYX = 3, 1011 LIS2DU12_YZX = 5, 1012 LIS2DU12_ZXY = 6, 1013 } lis2du12_priority_t; 1014 1015 typedef struct 1016 { 1017 uint8_t x_en : 1; /* Detection on X-axis */ 1018 uint8_t y_en : 1; /* Detection on Y-axis */ 1019 uint8_t z_en : 1; /* Detection on Z-axis */ 1020 struct 1021 { 1022 uint8_t x; 1023 uint8_t y; 1024 uint8_t z; 1025 } threshold; 1026 uint8_t shock; /* max shock time. 0 is 4 ODR_time, 1 LSb : 8 ODR_time. */ 1027 uint8_t quiet; /* Time after a tap. 0 is 2 ODR_time, 1 LSB : 4 ODR_time.*/ 1028 lis2du12_priority_t priority; 1029 struct 1030 { 1031 uint8_t en : 1; /* Double tap detection */ 1032 uint8_t latency; /* Max time gap. 0 is 16 ODR_time, 1 LSB : 32 ODR_time. */ 1033 } tap_double; 1034 } lis2du12_tap_md_t; 1035 int32_t lis2du12_tap_mode_set(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); 1036 int32_t lis2du12_tap_mode_get(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); 1037 1038 typedef enum 1039 { 1040 LIS2DU12_156mg = 0, 1041 LIS2DU12_219mg = 1, 1042 LIS2DU12_250mg = 2, 1043 LIS2DU12_312mg = 3, 1044 LIS2DU12_344mg = 4, 1045 LIS2DU12_406mg = 5, 1046 LIS2DU12_469mg = 6, 1047 LIS2DU12_500mg = 7, 1048 } lis2du12_threshold_t; 1049 1050 typedef struct 1051 { 1052 lis2du12_threshold_t threshold; 1053 uint8_t duration; /* 1 LSb: 1 ODR_time */ 1054 } lis2du12_ff_md_t; 1055 int32_t lis2du12_free_fall_mode_set(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); 1056 int32_t lis2du12_free_fall_mode_get(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); 1057 1058 typedef enum 1059 { 1060 LIS2DU12_DEG_80 = 0, 1061 LIS2DU12_DEG_70 = 1, 1062 LIS2DU12_DEG_60 = 2, 1063 LIS2DU12_DEG_50 = 3, 1064 } lis2du12_orient_trshld_t; 1065 1066 typedef enum 1067 { 1068 LIS2DU12_SIX = 0, 1069 LIS2DU12_FOUR = 1, 1070 } lis2du12_deg_of_freedom_t; 1071 1072 typedef struct 1073 { 1074 lis2du12_orient_trshld_t threshold; 1075 lis2du12_deg_of_freedom_t deg_of_freedom; 1076 } lis2du12_orient_md_t; 1077 int32_t lis2du12_orientation_mode_set(const stmdev_ctx_t *ctx, 1078 lis2du12_orient_md_t *val); 1079 int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, 1080 lis2du12_orient_md_t *val); 1081 1082 /** 1083 *@} 1084 * 1085 */ 1086 1087 #ifdef __cplusplus 1088 } 1089 #endif 1090 1091 #endif /* LIS2DU12_REGS_H */ 1092 1093 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1094
