1 /*
2 ******************************************************************************
3 * @file lis2du12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LIS2DU12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lis2du12_reg.h"
21
22 /**
23 * @defgroup LIS2DU12
24 * @brief This file provides a set of functions needed to drive the
25 * lis2du12 sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LIS2DU12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lis2du12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lis2du12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
lis2du12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak lis2du12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup LIS2DU12_Private_functions
96 * @brief Section collect all the utility functions needed by APIs.
97 * @{
98 *
99 */
100
bytecpy(uint8_t * target,uint8_t * source)101 static void bytecpy(uint8_t *target, uint8_t *source)
102 {
103 if ((target != NULL) && (source != NULL))
104 {
105 *target = *source;
106 }
107 }
108
109 /**
110 * @}
111 *
112 */
113
114 /**
115 * @defgroup LIS2DU12_Sensitivity
116 * @brief These functions convert raw-data into engineering units.
117 * @{
118 *
119 */
120
lis2du12_from_fs2g_to_mg(int16_t lsb)121 float_t lis2du12_from_fs2g_to_mg(int16_t lsb)
122 {
123 return (float_t)lsb * 0.061f;
124 }
125
lis2du12_from_fs4g_to_mg(int16_t lsb)126 float_t lis2du12_from_fs4g_to_mg(int16_t lsb)
127 {
128 return (float_t)lsb * 0.122f;
129 }
130
lis2du12_from_fs8g_to_mg(int16_t lsb)131 float_t lis2du12_from_fs8g_to_mg(int16_t lsb)
132 {
133 return (float_t)lsb * 0.244f;
134 }
135
lis2du12_from_fs16g_to_mg(int16_t lsb)136 float_t lis2du12_from_fs16g_to_mg(int16_t lsb)
137 {
138 return (float_t)lsb * 0.488f;
139 }
140
lis2du12_from_lsb_to_celsius(int16_t lsb)141 float_t lis2du12_from_lsb_to_celsius(int16_t lsb)
142 {
143 return ((float_t)lsb / 355.5f) + 25.0f;
144 }
145
146 /**
147 * @}
148 *
149 */
150
151 /**
152 * @defgroup Basic functions
153 * @brief This section groups all the functions concerning
154 * device basic configuration.
155 * @{
156 *
157 */
158
159 /**
160 * @brief Device "Who am I".[get]
161 *
162 * @param ctx communication interface handler.(ptr)
163 * @param val ID values.(ptr)
164 * @retval interface status (MANDATORY: return 0 -> no Error)
165 *
166 */
lis2du12_id_get(const stmdev_ctx_t * ctx,lis2du12_id_t * val)167 int32_t lis2du12_id_get(const stmdev_ctx_t *ctx, lis2du12_id_t *val)
168 {
169 uint8_t reg;
170 int32_t ret;
171
172 ret = lis2du12_read_reg(ctx, LIS2DU12_WHO_AM_I, ®, 1);
173 val->whoami = reg;
174
175 return ret;
176 }
177
178 /**
179 * @brief Configures the bus operating mode.[set]
180 *
181 * @param ctx communication interface handler.(ptr)
182 * @param val configures the bus operating mode.(ptr)
183 * @retval interface status (MANDATORY: return 0 -> no Error)
184 *
185 */
lis2du12_bus_mode_set(const stmdev_ctx_t * ctx,lis2du12_bus_mode_t val)186 int32_t lis2du12_bus_mode_set(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t val)
187 {
188 lis2du12_if_ctrl_t if_ctrl;
189 lis2du12_ctrl1_t ctrl1;
190 int32_t ret;
191
192 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
193 if (ret == 0)
194 {
195 if_ctrl.i3c_disable = (uint8_t)val & 0x01U;
196 if_ctrl.i2c_disable = ((uint8_t)val & 0x02U) >> 1;
197 ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
198 }
199 if (ret == 0)
200 {
201 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
202 }
203 if (ret == 0)
204 {
205 ctrl1.sim = ((uint8_t)val & 0x04U) >> 2;
206 ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
207 }
208
209 return ret;
210
211 }
212
213 /**
214 * @brief Configures the bus operating mode.[set]
215 *
216 * @param ctx communication interface handler.(ptr)
217 * @param val configures the bus operating mode.(ptr)
218 * @retval interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
lis2du12_bus_mode_get(const stmdev_ctx_t * ctx,lis2du12_bus_mode_t * val)221 int32_t lis2du12_bus_mode_get(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val)
222 {
223 lis2du12_if_ctrl_t if_ctrl;
224 lis2du12_ctrl1_t ctrl1;
225 int32_t ret;
226
227 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
228 if (ret == 0)
229 {
230 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
231 }
232 switch ((ctrl1.sim << 2) | (if_ctrl.i2c_disable) << 1 |
233 (if_ctrl.i3c_disable))
234 {
235 case LIS2DU12_SEL_BY_HW:
236 *val = LIS2DU12_SEL_BY_HW;
237 break;
238 case LIS2DU12_SPI_3W:
239 *val = LIS2DU12_SPI_3W;
240 break;
241 default:
242 *val = LIS2DU12_SEL_BY_HW;
243 break;
244 }
245
246 return ret;
247 }
248
249 /**
250 * @brief Configures the bus operating mode.[get]
251 *
252 * @param ctx communication interface handler.(ptr)
253 * @param val configures the bus operating mode.(ptr)
254 * @retval interface status (MANDATORY: return 0 -> no Error)
255 *
256 */
lis2du12_init_set(const stmdev_ctx_t * ctx,lis2du12_init_t val)257 int32_t lis2du12_init_set(const stmdev_ctx_t *ctx, lis2du12_init_t val)
258 {
259 lis2du12_ctrl1_t ctrl1;
260 lis2du12_ctrl4_t ctrl4;
261 int32_t ret;
262
263 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
264 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
265 switch (val)
266 {
267 case LIS2DU12_BOOT:
268 ctrl4.boot = PROPERTY_ENABLE;
269 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
270 break;
271 case LIS2DU12_RESET:
272
273 ctrl1.sw_reset = PROPERTY_ENABLE;
274 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
275 break;
276 case LIS2DU12_DRV_RDY:
277 ctrl4.bdu = PROPERTY_ENABLE;
278 ctrl1.if_add_inc = PROPERTY_ENABLE;
279 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
280 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
281 break;
282 default:
283 ctrl1.sw_reset = PROPERTY_ENABLE;
284 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
285 break;
286 }
287
288 return ret;
289 }
290
291 /**
292 * @brief Get the status of the device.[get]
293 *
294 * @param ctx communication interface handler.(ptr)
295 * @param val the status of the device.(ptr)
296 * @retval interface status (MANDATORY: return 0 -> no Error)
297 *
298 */
lis2du12_status_get(const stmdev_ctx_t * ctx,lis2du12_status_t * val)299 int32_t lis2du12_status_get(const stmdev_ctx_t *ctx, lis2du12_status_t *val)
300 {
301 lis2du12_status_register_t status_register;
302 lis2du12_ctrl1_t ctrl1;
303 lis2du12_ctrl4_t ctrl4;
304 int32_t ret;
305
306 ret = lis2du12_read_reg(ctx, LIS2DU12_STATUS,
307 (uint8_t *)&status_register, 1);
308 if (ret == 0)
309 {
310 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
311 }
312 if (ret == 0)
313 {
314 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
315 }
316
317 val->sw_reset = ctrl1.sw_reset;
318 val->boot = ctrl4.boot;
319 val->drdy_xl = status_register.drdy;
320 val->power_down = status_register.pd_status;
321
322 return ret;
323 }
324
325 /**
326 * @brief Electrical pin configuration.[set]
327 *
328 * @param ctx communication interface handler.(ptr)
329 * @param val the electrical settings for the configurable pins.(ptr)
330 * @retval interface status (MANDATORY: return 0 -> no Error)
331 *
332 */
lis2du12_pin_conf_set(const stmdev_ctx_t * ctx,lis2du12_pin_conf_t * val)333 int32_t lis2du12_pin_conf_set(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val)
334 {
335 lis2du12_if_pu_ctrl_t if_pu_ctrl;
336 lis2du12_md2_cfg_t md2_cfg;
337 lis2du12_if_ctrl_t if_ctrl;
338 lis2du12_ctrl1_t ctrl1;
339 int32_t ret;
340
341 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1);
342 if (ret == 0)
343 {
344 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
345 }
346 if (ret == 0)
347 {
348 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
349 }
350 if (ret == 0)
351 {
352 ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
353 }
354
355 if (ret == 0)
356 {
357 if_pu_ctrl.sdo_pu_disc = ~val->sdo_pull_up;
358 if_pu_ctrl.sda_pu_en = val->sda_pull_up;
359 if_pu_ctrl.cs_pu_disc = ~val->cs_pull_up;
360 ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1);
361 }
362 if (ret == 0)
363 {
364 if_ctrl.pd_dis_int1 = val->int1_pull_down;
365 ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
366 }
367 if (ret == 0)
368 {
369 ctrl1.pp_od = val->int1_int2_push_pull;
370 ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
371 }
372 if (ret == 0)
373 {
374 md2_cfg.pd_dis_int2 = val->int2_pull_down;
375 ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
376 }
377
378 return ret;
379 }
380
381 /**
382 * @brief Electrical pin configuration.[get]
383 *
384 * @param ctx communication interface handler.(ptr)
385 * @param val the electrical settings for the configurable pins.(ptr)
386 * @retval interface status (MANDATORY: return 0 -> no Error)
387 *
388 */
lis2du12_pin_conf_get(const stmdev_ctx_t * ctx,lis2du12_pin_conf_t * val)389 int32_t lis2du12_pin_conf_get(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val)
390 {
391 lis2du12_if_pu_ctrl_t if_pu_ctrl;
392 lis2du12_md2_cfg_t md2_cfg;
393 lis2du12_if_ctrl_t if_ctrl;
394 lis2du12_ctrl1_t ctrl1;
395 int32_t ret;
396
397 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1);
398 if (ret == 0)
399 {
400 ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1);
401 }
402 if (ret == 0)
403 {
404 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
405 }
406 if (ret == 0)
407 {
408 ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
409 }
410 val->sdo_pull_up = ~if_pu_ctrl.sdo_pu_disc;
411 val->sda_pull_up = if_pu_ctrl.sda_pu_en;
412 val->cs_pull_up = ~if_pu_ctrl.cs_pu_disc;
413 val->int1_int2_push_pull = ctrl1.pp_od;
414 val->int1_pull_down = if_ctrl.pd_dis_int1;
415 val->int2_pull_down = md2_cfg.pd_dis_int2;
416
417 return ret;
418 }
419
420 /**
421 * @brief Get the status of all the interrupt sources.[get]
422 *
423 * @param ctx communication interface handler.(ptr)
424 * @param val the status of all the interrupt sources.(ptr)
425 * @retval interface status (MANDATORY: return 0 -> no Error)
426 *
427 */
lis2du12_all_sources_get(const stmdev_ctx_t * ctx,lis2du12_all_sources_t * val)428 int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx,
429 lis2du12_all_sources_t *val)
430 {
431 lis2du12_all_int_src_t all_int_src;
432 int32_t ret;
433
434 ret = lis2du12_read_reg(ctx, LIS2DU12_ALL_INT_SRC, (uint8_t *)&all_int_src, 1);
435 if (ret == 0 && all_int_src.int_global == 1U)
436 {
437 val->free_fall = all_int_src.ff_ia_all;
438 val->six_d = all_int_src.d6d_ia_all;
439 val->wake_up = all_int_src.wu_ia_all;
440 val->sleep_change = all_int_src.sleep_change_ia_all;
441 val->single_tap = all_int_src.single_tap_all;
442 val->double_tap = all_int_src.double_tap_all;
443
444 if (all_int_src.d6d_ia_all == 1U)
445 {
446 lis2du12_sixd_src_t sixd_src;
447
448 ret = lis2du12_read_reg(ctx, LIS2DU12_SIXD_SRC, (uint8_t *)&sixd_src, 1);
449
450 val->six_d_xl = sixd_src.xl;
451 val->six_d_xh = sixd_src.xh;
452 val->six_d_yl = sixd_src.yl;
453 val->six_d_yh = sixd_src.yh;
454 val->six_d_zl = sixd_src.zl;
455 val->six_d_zh = sixd_src.zh;
456 }
457
458 if (all_int_src.wu_ia_all == 1U || all_int_src.sleep_change_ia_all == 1U)
459 {
460 lis2du12_wake_up_src_t wu_src;
461
462 ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1);
463
464 val->wake_up_z = wu_src.z_wu;
465 val->wake_up_y = wu_src.y_wu;
466 val->wake_up_x = wu_src.x_wu;
467 val->sleep_state = wu_src.sleep_state;
468 }
469
470 if (all_int_src.single_tap_all == 1U || all_int_src.double_tap_all == 1U)
471 {
472 lis2du12_tap_src_t tap_src;
473
474 ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_SRC, (uint8_t *)&tap_src, 1);
475
476 val->tap_z = tap_src.z_tap;
477 val->tap_y = tap_src.y_tap;
478 val->tap_x = tap_src.x_tap;
479 val->tap_sign = tap_src.tap_sign;
480 }
481 }
482
483 return ret;
484 }
485
486 /**
487 * @brief Sensor conversion parameters selection.[set]
488 *
489 * @param ctx communication interface handler.(ptr)
490 * @param val set the sensor conversion parameters.(ptr)
491 * @retval interface status (MANDATORY: return 0 -> no Error)
492 *
493 */
lis2du12_mode_set(const stmdev_ctx_t * ctx,lis2du12_md_t * val)494 int32_t lis2du12_mode_set(const stmdev_ctx_t *ctx, lis2du12_md_t *val)
495 {
496 lis2du12_ctrl5_t ctrl5;
497 int32_t ret;
498
499 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1);
500
501 ctrl5.odr = (uint8_t)val->odr;
502 ctrl5.fs = (uint8_t)val->fs;
503 ctrl5.bw = (uint8_t)val->bw;
504
505 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1);
506
507 return ret;
508 }
509
510 /**
511 * @brief Sensor conversion parameters selection.[get]
512 *
513 * @param ctx communication interface handler.(ptr)
514 * @param val get the sensor conversion parameters.(ptr)
515 * @retval interface status (MANDATORY: return 0 -> no Error)
516 *
517 */
lis2du12_mode_get(const stmdev_ctx_t * ctx,lis2du12_md_t * val)518 int32_t lis2du12_mode_get(const stmdev_ctx_t *ctx, lis2du12_md_t *val)
519 {
520 lis2du12_ctrl5_t ctrl5;
521 int32_t ret;
522
523 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1);
524
525 switch (ctrl5.odr)
526 {
527 case LIS2DU12_OFF:
528 val->odr = LIS2DU12_OFF;
529 break;
530 case LIS2DU12_1Hz6_ULP:
531 val->odr = LIS2DU12_1Hz6_ULP;
532 break;
533 case LIS2DU12_3Hz_ULP:
534 val->odr = LIS2DU12_3Hz_ULP;
535 break;
536 case LIS2DU12_6Hz_ULP:
537 val->odr = LIS2DU12_6Hz_ULP;
538 break;
539 case LIS2DU12_6Hz:
540 val->odr = LIS2DU12_6Hz;
541 break;
542 case LIS2DU12_12Hz5:
543 val->odr = LIS2DU12_12Hz5;
544 break;
545 case LIS2DU12_25Hz:
546 val->odr = LIS2DU12_25Hz;
547 break;
548 case LIS2DU12_50Hz:
549 val->odr = LIS2DU12_50Hz;
550 break;
551 case LIS2DU12_100Hz:
552 val->odr = LIS2DU12_100Hz;
553 break;
554 case LIS2DU12_200Hz:
555 val->odr = LIS2DU12_200Hz;
556 break;
557 case LIS2DU12_400Hz:
558 val->odr = LIS2DU12_400Hz;
559 break;
560 case LIS2DU12_800Hz:
561 val->odr = LIS2DU12_800Hz;
562 break;
563 case LIS2DU12_TRIG_PIN:
564 val->odr = LIS2DU12_TRIG_PIN;
565 break;
566 case LIS2DU12_TRIG_SW:
567 val->odr = LIS2DU12_TRIG_SW;
568 break;
569 default:
570 val->odr = LIS2DU12_OFF;
571 break;
572 }
573
574 switch (ctrl5.fs)
575 {
576 case LIS2DU12_2g:
577 val->fs = LIS2DU12_2g;
578 break;
579 case LIS2DU12_4g:
580 val->fs = LIS2DU12_4g;
581 break;
582 case LIS2DU12_8g:
583 val->fs = LIS2DU12_8g;
584 break;
585 case LIS2DU12_16g:
586 val->fs = LIS2DU12_16g;
587 break;
588 default:
589 val->fs = LIS2DU12_2g;
590 break;
591 }
592
593 switch (ctrl5.bw)
594 {
595 case LIS2DU12_ODR_div_2:
596 val->bw = LIS2DU12_ODR_div_2;
597 break;
598 case LIS2DU12_ODR_div_4:
599 val->bw = LIS2DU12_ODR_div_4;
600 break;
601 case LIS2DU12_ODR_div_8:
602 val->bw = LIS2DU12_ODR_div_8;
603 break;
604 case LIS2DU12_ODR_div_16:
605 val->bw = LIS2DU12_ODR_div_16;
606 break;
607 default:
608 val->bw = LIS2DU12_ODR_div_2;
609 break;
610 }
611
612 return ret;
613 }
614
615 /**
616 * @brief Software trigger for One-Shot.[get]
617 *
618 * @param ctx communication interface handler.(ptr)
619 * @param md the sensor conversion parameters.(ptr)
620 * @retval interface status (MANDATORY: return 0 -> no Error)
621 *
622 */
lis2du12_trigger_sw(const stmdev_ctx_t * ctx,lis2du12_md_t * md)623 int32_t lis2du12_trigger_sw(const stmdev_ctx_t *ctx, lis2du12_md_t *md)
624 {
625 lis2du12_ctrl4_t ctrl4;
626 int32_t ret = 0;
627
628 if (md->odr == LIS2DU12_TRIG_SW)
629 {
630 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
631 ctrl4.soc = PROPERTY_ENABLE;
632 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
633 }
634 return ret;
635 }
636
637 /**
638 * @brief Software trigger for One-Shot.[get]
639 *
640 * @param ctx communication interface handler.(ptr)
641 * @param md the sensor conversion parameters.(ptr)
642 * @param data data retrived from the sensor.(ptr)
643 * @retval interface status (MANDATORY: return 0 -> no Error)
644 *
645 */
lis2du12_data_get(const stmdev_ctx_t * ctx,lis2du12_md_t * md,lis2du12_data_t * data)646 int32_t lis2du12_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md,
647 lis2du12_data_t *data)
648 {
649 uint8_t buff[8];
650 int32_t ret;
651 uint8_t i;
652 uint8_t j;
653
654 ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, (uint8_t *)&buff, 8);
655
656 /* acceleration conversion */
657 j = 0U;
658 for (i = 0U; i < 3U; i++)
659 {
660 data->xl.raw[i] = (int16_t)buff[j + 1U];
661 data->xl.raw[i] = (data->xl.raw[i] * 256) + (int16_t) buff[j];
662 j += 2U;
663 switch (md->fs)
664 {
665 case LIS2DU12_2g:
666 data->xl.mg[i] = lis2du12_from_fs2g_to_mg(data->xl.raw[i]);
667 break;
668 case LIS2DU12_4g:
669 data->xl.mg[i] = lis2du12_from_fs4g_to_mg(data->xl.raw[i]);
670 break;
671 case LIS2DU12_8g:
672 data->xl.mg[i] = lis2du12_from_fs8g_to_mg(data->xl.raw[i]);
673 break;
674 case LIS2DU12_16g:
675 data->xl.mg[i] = lis2du12_from_fs16g_to_mg(data->xl.raw[i]);
676 break;
677 default:
678 data->xl.mg[i] = 0.0f;
679 break;
680 }
681 }
682
683 data->heat.raw = (int16_t)buff[j + 1U];
684 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[j];
685 /* temperature conversion */
686 data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw);
687
688 return ret;
689 }
690
691 /**
692 * @brief Configures the self test.[set]
693 *
694 * @param ctx communication interface handler.(ptr)
695 * @param val self test mode.(ptr)
696 * @retval interface status (MANDATORY: return 0 -> no Error)
697 *
698 */
lis2du12_self_test_sign_set(const stmdev_ctx_t * ctx,lis2du12_st_t val)699 int32_t lis2du12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2du12_st_t val)
700 {
701 lis2du12_st_sign_t st_sign;
702 int32_t ret;
703
704 ret = lis2du12_read_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t *)&st_sign, 1);
705 if (ret == 0)
706 {
707 st_sign.stsign = (uint8_t) val;
708 ret = lis2du12_write_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t *)&st_sign, 1);
709 }
710 return ret;
711 }
712
713 /**
714 * @brief Configures the self test.[start]
715 *
716 * @param ctx communication interface handler.(ptr)
717 * @param val valid values 2 (1st step) or 1 (2nd step)
718 * @retval interface status (MANDATORY: return 0 -> no Error)
719 *
720 */
lis2du12_self_test_start(const stmdev_ctx_t * ctx,uint8_t val)721 int32_t lis2du12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val)
722 {
723 lis2du12_ctrl3_t ctrl3;
724 int32_t ret;
725
726 if (val != 1U && val != 2U)
727 {
728 return -1;
729 }
730
731 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
732 ctrl3.st = (uint8_t) val;
733 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
734
735 return ret;
736 }
737
738 /**
739 * @brief Configures the self test.[stop]
740 *
741 * @param ctx communication interface handler.(ptr)
742 * @param val valid values 2 (1st step) or 1 (2nd step)
743 * @retval interface status (MANDATORY: return 0 -> no Error)
744 *
745 */
lis2du12_self_test_stop(const stmdev_ctx_t * ctx)746 int32_t lis2du12_self_test_stop(const stmdev_ctx_t *ctx)
747 {
748 lis2du12_ctrl3_t ctrl3;
749 int32_t ret;
750
751 ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
752 ctrl3.st = 0;
753 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
754
755 return ret;
756 }
757
758 /**
759 * @}
760 *
761 */
762
763 /**
764 * @defgroup FIFO functions
765 * @brief This section groups all the functions concerning the
766 * management of FIFO.
767 * @{
768 *
769 */
770
771 /**
772 * @brief FIFO operation mode selection.[set]
773 *
774 * @param ctx communication interface handler.(ptr)
775 * @param val set the FIFO operation mode.(ptr)
776 * @retval interface status (MANDATORY: return 0 -> no Error)
777 *
778 */
lis2du12_fifo_mode_set(const stmdev_ctx_t * ctx,lis2du12_fifo_md_t * val)779 int32_t lis2du12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val)
780 {
781 lis2du12_fifo_ctrl_t fifo_ctrl;
782 lis2du12_fifo_wtm_t fifo_wtm;
783 uint8_t reg[2];
784 int32_t ret;
785
786 ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2);
787
788 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
789 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
790
791 fifo_ctrl.f_mode = (uint8_t) val->operation;
792 fifo_ctrl.fifo_depth = (uint8_t) val->store;
793
794 if (val->watermark != 0x00U)
795 {
796 fifo_ctrl.stop_on_fth = PROPERTY_ENABLE;
797 }
798 else
799 {
800 fifo_ctrl.stop_on_fth = PROPERTY_DISABLE;
801 }
802
803 fifo_wtm.fth = val->watermark;
804
805 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
806 bytecpy(®[1], (uint8_t *)&fifo_wtm);
807
808 ret += lis2du12_write_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2);
809
810 return ret;
811 }
812
813 /**
814 * @brief FIFO operation mode selection.[get]
815 *
816 * @param ctx communication interface handler.(ptr)
817 * @param val get the FIFO operation mode.(ptr)
818 * @retval interface status (MANDATORY: return 0 -> no Error)
819 *
820 */
lis2du12_fifo_mode_get(const stmdev_ctx_t * ctx,lis2du12_fifo_md_t * val)821 int32_t lis2du12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val)
822 {
823 lis2du12_fifo_ctrl_t fifo_ctrl;
824 lis2du12_fifo_wtm_t fifo_wtm;
825 uint8_t reg[2];
826 int32_t ret;
827
828 ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2);
829
830 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
831 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
832
833 switch (fifo_ctrl.f_mode)
834 {
835 case LIS2DU12_BYPASS:
836 val->operation = LIS2DU12_BYPASS;
837 break;
838 case LIS2DU12_FIFO:
839 val->operation = LIS2DU12_FIFO;
840 break;
841 case LIS2DU12_STREAM:
842 val->operation = LIS2DU12_STREAM;
843 break;
844 case LIS2DU12_STREAM_TO_FIFO:
845 val->operation = LIS2DU12_STREAM_TO_FIFO;
846 break;
847 case LIS2DU12_BYPASS_TO_STREAM:
848 val->operation = LIS2DU12_BYPASS_TO_STREAM;
849 break;
850 case LIS2DU12_BYPASS_TO_FIFO:
851 val->operation = LIS2DU12_BYPASS_TO_FIFO;
852 break;
853 default:
854 val->operation = LIS2DU12_BYPASS;
855 break;
856 }
857
858 switch (fifo_ctrl.fifo_depth)
859 {
860 case LIS2DU12_16_BIT:
861 val->store = LIS2DU12_16_BIT;
862 break;
863 case LIS2DU12_8_BIT:
864 val->store = LIS2DU12_8_BIT;
865 break;
866 default:
867 val->store = LIS2DU12_16_BIT;
868 break;
869 }
870
871 val->watermark = fifo_wtm.fth;
872
873 return ret;
874 }
875
lis2du12_fifo_status_get(const stmdev_ctx_t * ctx,lis2du12_fifo_status_t * val)876 int32_t lis2du12_fifo_status_get(const stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val)
877 {
878 lis2du12_fifo_status1_t fifo_status1;
879 int32_t ret;
880
881 ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS1, (uint8_t *)&fifo_status1, 1);
882
883 val->fifo_fth = fifo_status1.fth;
884 val->fifo_ovr = fifo_status1.fifo_ovr;
885
886 return ret;
887 }
888
889 /**
890 * @brief Get the number of samples stored in FIFO.[get]
891 *
892 * @param ctx communication interface handler.(ptr)
893 * @param md the sensor conversion parameters.(ptr)
894 * @param val number of samples stored in FIFO.(ptr)
895 * @retval interface status (MANDATORY: return 0 -> no Error)
896 *
897 */
lis2du12_fifo_level_get(const stmdev_ctx_t * ctx,lis2du12_fifo_md_t * md,uint8_t * val)898 int32_t lis2du12_fifo_level_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md,
899 uint8_t *val)
900 {
901 lis2du12_fifo_status2_t fifo_status2;
902 int32_t ret;
903
904 ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS2,
905 (uint8_t *)&fifo_status2, 1);
906
907 *val = fifo_status2.fss;
908
909 return ret;
910 }
911
912 /**
913 * @brief Software trigger for One-Shot.[get]
914 *
915 * @param ctx communication interface handler.(ptr)
916 * @param md the sensor conversion parameters.(ptr)
917 * @param fmd get the FIFO operation mode.(ptr)
918 * @param data data retrived from FIFO.(ptr)
919 * @retval interface status (MANDATORY: return 0 -> no Error)
920 *
921 */
lis2du12_fifo_data_get(const stmdev_ctx_t * ctx,lis2du12_md_t * md,lis2du12_fifo_md_t * fmd,lis2du12_fifo_data_t * data)922 int32_t lis2du12_fifo_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md,
923 lis2du12_fifo_md_t *fmd,
924 lis2du12_fifo_data_t *data)
925 {
926 uint8_t fifo_data[8];
927 int8_t i;
928 int32_t ret;
929
930 ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, fifo_data, 8);
931
932 if (fmd->store == LIS2DU12_8_BIT)
933 {
934 for (i = 0; i < 3; i++)
935 {
936 data->xl[0].raw[i] = (int16_t)fifo_data[2 * i + 1];
937 data->xl[0].raw[i] = data->xl[0].raw[i] * 256 + (int16_t)fifo_data[2 * i];
938 }
939
940 data->heat.raw = (int16_t)fifo_data[7U];
941 data->heat.raw = (data->heat.raw * 256) + (int16_t) fifo_data[6U];
942 /* temperature conversion */
943 data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw);
944 }
945 else
946 {
947 for (i = 0; i < 3; i++)
948 {
949 data->xl[0].raw[i] = (int16_t)fifo_data[i] * 256;
950 data->xl[1].raw[i] = (int16_t)fifo_data[3 + i] * 256;
951 }
952 }
953
954 for (i = 0; i < 3; i++)
955 {
956 switch (md->fs)
957 {
958 case LIS2DU12_2g:
959 data->xl[0].mg[i] = lis2du12_from_fs2g_to_mg(data->xl[0].raw[i]);
960 data->xl[1].mg[i] = lis2du12_from_fs2g_to_mg(data->xl[1].raw[i]);
961 break;
962 case LIS2DU12_4g:
963 data->xl[0].mg[i] = lis2du12_from_fs4g_to_mg(data->xl[0].raw[i]);
964 data->xl[1].mg[i] = lis2du12_from_fs4g_to_mg(data->xl[1].raw[i]);
965 break;
966 case LIS2DU12_8g:
967 data->xl[0].mg[i] = lis2du12_from_fs8g_to_mg(data->xl[0].raw[i]);
968 data->xl[1].mg[i] = lis2du12_from_fs8g_to_mg(data->xl[1].raw[i]);
969 break;
970 case LIS2DU12_16g:
971 data->xl[0].mg[i] = lis2du12_from_fs16g_to_mg(data->xl[0].raw[i]);
972 data->xl[1].mg[i] = lis2du12_from_fs16g_to_mg(data->xl[1].raw[i]);
973 break;
974 default:
975 data->xl[0].mg[i] = 0.0f;
976 data->xl[1].mg[i] = 0.0f;
977 break;
978 }
979 }
980
981 return ret;
982 }
983
984 /**
985 * @}
986 *
987 */
988
989 /**
990 * @defgroup Interrupt signals
991 * @brief This section groups all the functions concerning
992 * the management of interrupt signals.
993 * @{
994 *
995 */
996
997 /**
998 * @brief Interrupt pins hardware signal configuration.[set]
999 *
1000 * @param ctx communication interface handler.(ptr)
1001 * @param val the pins hardware signal settings.(ptr)
1002 * @retval interface status (MANDATORY: return 0 -> no Error)
1003 *
1004 */
lis2du12_interrupt_mode_set(const stmdev_ctx_t * ctx,lis2du12_int_mode_t * val)1005 int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx,
1006 lis2du12_int_mode_t *val)
1007 {
1008 lis2du12_interrupt_cfg_t interrupt_cfg;
1009 lis2du12_ctrl1_t ctrl1;
1010 int32_t ret;
1011
1012 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1013 (uint8_t *)&interrupt_cfg, 1);
1014 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1015
1016 interrupt_cfg.int_short_en = (uint8_t)val->base_sig & 0x01U;
1017 interrupt_cfg.lir = ((uint8_t)val->base_sig & 0x02U) >> 1 ;
1018
1019 interrupt_cfg.h_lactive = val->active_low;
1020 ctrl1.drdy_pulsed = ~val->drdy_latched;
1021
1022 interrupt_cfg.interrupts_enable = val->enable;
1023
1024 ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1025 (uint8_t *)&interrupt_cfg, 1);
1026 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1027
1028 return ret;
1029 }
1030
1031 /**
1032 * @brief Interrupt pins hardware signal configuration.[get]
1033 *
1034 * @param ctx communication interface handler.(ptr)
1035 * @param val the pins hardware signal settings.(ptr)
1036 * @retval interface status (MANDATORY: return 0 -> no Error)
1037 *
1038 */
lis2du12_interrupt_mode_get(const stmdev_ctx_t * ctx,lis2du12_int_mode_t * val)1039 int32_t lis2du12_interrupt_mode_get(const stmdev_ctx_t *ctx,
1040 lis2du12_int_mode_t *val)
1041 {
1042 lis2du12_interrupt_cfg_t interrupt_cfg;
1043 lis2du12_ctrl1_t ctrl1;
1044 int32_t ret;
1045
1046 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1047 (uint8_t *)&interrupt_cfg, 1);
1048 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1049
1050 val->active_low = interrupt_cfg.h_lactive;
1051 val->drdy_latched = ~ctrl1.drdy_pulsed;
1052 val->enable = interrupt_cfg.interrupts_enable;
1053
1054 switch ((interrupt_cfg.lir << 1) | interrupt_cfg.int_short_en)
1055 {
1056 case LIS2DU12_INT_LEVEL:
1057 val->base_sig = LIS2DU12_INT_LEVEL;
1058 break;
1059 case LIS2DU12_INT_LATCHED:
1060 val->base_sig = LIS2DU12_INT_LATCHED;
1061 break;
1062 default:
1063 val->base_sig = LIS2DU12_INT_LEVEL;
1064 break;
1065 }
1066 return ret;
1067 }
1068
1069 /**
1070 * @brief Route interrupt signals on int1 pin.[set]
1071 *
1072 * @param ctx communication interface handler.(ptr)
1073 * @param val the signals to route on int1 pin.(ptr)
1074 * @retval interface status (MANDATORY: return 0 -> no Error)
1075 *
1076 */
lis2du12_pin_int1_route_set(const stmdev_ctx_t * ctx,lis2du12_pin_int_route_t * val)1077 int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1078 lis2du12_pin_int_route_t *val)
1079 {
1080 lis2du12_interrupt_cfg_t interrupt_cfg;
1081 lis2du12_md1_cfg_t md1_cfg;
1082 lis2du12_ctrl2_t ctrl2;
1083 int32_t ret;
1084
1085 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1086 (uint8_t *)&interrupt_cfg, 1);
1087 ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1088 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1);
1089
1090 ctrl2.int1_boot = val->boot;
1091 ctrl2.int1_drdy = val->drdy_xl;
1092 ctrl2.int1_f_fth = val->fifo_th;
1093 ctrl2.int1_f_ovr = val->fifo_ovr;
1094 ctrl2.int1_f_full = val->fifo_full;
1095
1096 md1_cfg.int1_double_tap = val->double_tap;
1097 md1_cfg.int1_6d = val->six_d;
1098 md1_cfg.int1_wu = val->wake_up;
1099 md1_cfg.int1_ff = val->free_fall;
1100 md1_cfg.int1_single_tap = val->single_tap;
1101
1102 if (val->sleep_state == 1U)
1103 {
1104 interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE;
1105 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
1106 }
1107 if (val->sleep_change == 1U)
1108 {
1109 interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE;
1110 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
1111 }
1112
1113 ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1114 (uint8_t *)&interrupt_cfg, 1);
1115 ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1116 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1);
1117
1118 return ret;
1119 }
1120
1121 /**
1122 * @brief Route interrupt signals on int1 pin.[get]
1123 *
1124 * @param ctx communication interface handler.(ptr)
1125 * @param val the signals that are routed on int1 pin.(ptr)
1126 * @retval interface status (MANDATORY: return 0 -> no Error)
1127 *
1128 */
lis2du12_pin_int1_route_get(const stmdev_ctx_t * ctx,lis2du12_pin_int_route_t * val)1129 int32_t lis2du12_pin_int1_route_get(const stmdev_ctx_t *ctx,
1130 lis2du12_pin_int_route_t *val)
1131 {
1132 lis2du12_interrupt_cfg_t interrupt_cfg;
1133 lis2du12_md1_cfg_t md1_cfg;
1134 lis2du12_ctrl2_t ctrl2;
1135 int32_t ret;
1136
1137 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1138 (uint8_t *)&interrupt_cfg, 1);
1139 ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1140 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1);
1141
1142 val->boot = ctrl2.int1_boot;
1143 val->drdy_xl = ctrl2.int1_drdy;
1144 val->fifo_th = ctrl2.int1_f_fth;
1145 val->fifo_ovr = ctrl2.int1_f_ovr;
1146 val->fifo_full = ctrl2.int1_f_full;
1147
1148 val->double_tap = md1_cfg.int1_double_tap;
1149 val->six_d = md1_cfg.int1_6d;
1150 val->wake_up = md1_cfg.int1_wu;
1151 val->free_fall = md1_cfg.int1_ff;
1152 val->single_tap = md1_cfg.int1_single_tap;
1153
1154 val->sleep_state = interrupt_cfg.sleep_status_on_int;
1155
1156 if (val->sleep_state == PROPERTY_DISABLE)
1157 {
1158 val->sleep_change = md1_cfg.int1_sleep_change;
1159 }
1160 else
1161 {
1162 val->sleep_change = PROPERTY_DISABLE;
1163 }
1164
1165 return ret;
1166 }
1167
1168 /**
1169 * @brief Route interrupt signals on int2 pin.[set]
1170 *
1171 * @param ctx communication interface handler.(ptr)
1172 * @param val the signals to route on int2 pin.(ptr)
1173 * @retval interface status (MANDATORY: return 0 -> no Error)
1174 *
1175 */
lis2du12_pin_int2_route_set(const stmdev_ctx_t * ctx,lis2du12_pin_int_route_t * val)1176 int32_t lis2du12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1177 lis2du12_pin_int_route_t *val)
1178 {
1179 lis2du12_interrupt_cfg_t interrupt_cfg;
1180 lis2du12_md2_cfg_t md2_cfg;
1181 lis2du12_ctrl3_t ctrl3;
1182 int32_t ret;
1183
1184 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1185 (uint8_t *)&interrupt_cfg, 1);
1186 ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1187 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
1188
1189 ctrl3.int2_boot = val->boot;
1190 ctrl3.int2_drdy = val->drdy_xl;
1191 ctrl3.int2_f_fth = val->fifo_th;
1192 ctrl3.int2_f_ovr = val->fifo_ovr;
1193 ctrl3.int2_f_full = val->fifo_full;
1194
1195 md2_cfg.int2_double_tap = val->double_tap;
1196 md2_cfg.int2_6d = val->six_d;
1197 md2_cfg.int2_wu = val->wake_up;
1198 md2_cfg.int2_ff = val->free_fall;
1199 md2_cfg.int2_single_tap = val->single_tap;
1200
1201 if (val->sleep_state == 1U)
1202 {
1203 interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE;
1204 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
1205 }
1206 if (val->sleep_change == 1U)
1207 {
1208 interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE;
1209 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
1210 }
1211
1212 ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1213 (uint8_t *)&interrupt_cfg, 1);
1214 ret += lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1215 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
1216
1217 return ret;
1218 }
1219
1220 /**
1221 * @brief Route interrupt signals on int2 pin.[get]
1222 *
1223 * @param ctx communication interface handler.(ptr)
1224 * @param val the signals that are routed on int2 pin.(ptr)
1225 * @retval interface status (MANDATORY: return 0 -> no Error)
1226 *
1227 */
lis2du12_pin_int2_route_get(const stmdev_ctx_t * ctx,lis2du12_pin_int_route_t * val)1228 int32_t lis2du12_pin_int2_route_get(const stmdev_ctx_t *ctx,
1229 lis2du12_pin_int_route_t *val)
1230 {
1231 lis2du12_interrupt_cfg_t interrupt_cfg;
1232 lis2du12_md2_cfg_t md2_cfg;
1233 lis2du12_ctrl3_t ctrl3;
1234 int32_t ret;
1235
1236 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1237 (uint8_t *)&interrupt_cfg, 1);
1238 ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1);
1239 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1);
1240
1241 val->boot = ctrl3.int2_boot;
1242 val->drdy_xl = ctrl3.int2_drdy;
1243 val->fifo_th = ctrl3.int2_f_fth;
1244 val->fifo_ovr = ctrl3.int2_f_ovr;
1245 val->fifo_full = ctrl3.int2_f_full;
1246
1247 val->double_tap = md2_cfg.int2_double_tap;
1248 val->six_d = md2_cfg.int2_6d;
1249 val->wake_up = md2_cfg.int2_wu;
1250 val->free_fall = md2_cfg.int2_ff;
1251 val->single_tap = md2_cfg.int2_single_tap;
1252
1253 val->sleep_state = interrupt_cfg.sleep_status_on_int;
1254
1255 if (val->sleep_state == PROPERTY_DISABLE)
1256 {
1257 val->sleep_change = md2_cfg.int2_sleep_change;
1258 }
1259 else
1260 {
1261 val->sleep_change = PROPERTY_DISABLE;
1262 }
1263
1264 return ret;
1265 }
1266
1267 /**
1268 * @}
1269 *
1270 */
1271
1272 /**
1273 * @defgroup Wakeup functions
1274 * @brief This section groups all the functions concerning
1275 * the wake up functionality.
1276 * @{
1277 *
1278 */
1279
1280 /**
1281 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1282 *
1283 * @param ctx communication interface handler.(ptr)
1284 * @param val parameters of configuration.(ptr)
1285 * @retval interface status (MANDATORY: return 0 -> no Error)
1286 *
1287 */
lis2du12_wake_up_mode_set(const stmdev_ctx_t * ctx,lis2du12_wkup_md_t * val)1288 int32_t lis2du12_wake_up_mode_set(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val)
1289 {
1290 lis2du12_interrupt_cfg_t interrupt_cfg;
1291 lis2du12_wake_up_ths_t wake_up_ths;
1292 lis2du12_wake_up_dur_t wake_up_dur;
1293 lis2du12_md1_cfg_t md1_cfg;
1294 lis2du12_ctrl1_t ctrl1;
1295 lis2du12_ctrl4_t ctrl4;
1296 int32_t ret;
1297
1298 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1299 (uint8_t *)&interrupt_cfg, 1);
1300 ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS,
1301 (uint8_t *)&wake_up_ths, 1);
1302 ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1303 (uint8_t *)&wake_up_dur, 1);
1304 ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1305 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1306 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
1307
1308 ctrl1.wu_z_en = val->z_en;
1309 ctrl1.wu_y_en = val->y_en;
1310 ctrl1.wu_x_en = val->x_en;
1311
1312 if (val->threshold > 63U)
1313 {
1314 interrupt_cfg.wake_ths_w = PROPERTY_ENABLE;
1315 wake_up_ths.wk_ths = val->threshold / 4U;
1316 }
1317 else
1318 {
1319 interrupt_cfg.wake_ths_w = PROPERTY_DISABLE;
1320 wake_up_ths.wk_ths = val->threshold;
1321 }
1322
1323 if (val->duration > 3U)
1324 {
1325 md1_cfg.wu_dur_x4 = PROPERTY_ENABLE;
1326 wake_up_dur.wake_dur = val->duration / 4U;
1327 }
1328 else
1329 {
1330 md1_cfg.wu_dur_x4 = PROPERTY_DISABLE;
1331 wake_up_dur.wake_dur = val->duration;
1332 }
1333
1334 wake_up_ths.sleep_on = val->sleep.en;
1335 ctrl4.inact_odr = (uint8_t)val->sleep.odr;
1336 wake_up_dur.sleep_dur = val->sleep.duration;
1337
1338 ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1339 (uint8_t *)&interrupt_cfg, 1);
1340 ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS,
1341 (uint8_t *)&wake_up_ths, 1);
1342 ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1343 (uint8_t *)&wake_up_dur, 1);
1344 ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1345 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1346 ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief Configuration of Wake-up and Wake-up to Sleep.[get]
1353 *
1354 * @param ctx communication interface handler.(ptr)
1355 * @param val retrieve the parameters of configuration.(ptr)
1356 * @retval interface status (MANDATORY: return 0 -> no Error)
1357 *
1358 */
lis2du12_wake_up_mode_get(const stmdev_ctx_t * ctx,lis2du12_wkup_md_t * val)1359 int32_t lis2du12_wake_up_mode_get(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val)
1360 {
1361 lis2du12_interrupt_cfg_t interrupt_cfg;
1362 lis2du12_wake_up_ths_t wake_up_ths;
1363 lis2du12_wake_up_dur_t wake_up_dur;
1364 lis2du12_md1_cfg_t md1_cfg;
1365 lis2du12_ctrl1_t ctrl1;
1366 lis2du12_ctrl4_t ctrl4;
1367 int32_t ret;
1368
1369 ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG,
1370 (uint8_t *)&interrupt_cfg, 1);
1371 ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS,
1372 (uint8_t *)&wake_up_ths, 1);
1373 ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1374 (uint8_t *)&wake_up_dur, 1);
1375 ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1376 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1);
1377 ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1);
1378
1379 val->z_en = ctrl1.wu_z_en;
1380 val->y_en = ctrl1.wu_y_en;
1381 val->x_en = ctrl1.wu_x_en;
1382
1383 if (interrupt_cfg.wake_ths_w == PROPERTY_ENABLE)
1384 {
1385 val->threshold = wake_up_ths.wk_ths * 4U;
1386 }
1387 else
1388 {
1389 val->threshold = wake_up_ths.wk_ths;
1390 }
1391
1392 if (md1_cfg.wu_dur_x4 == PROPERTY_ENABLE)
1393 {
1394 val->duration = wake_up_dur.wake_dur * 4U;
1395 }
1396 else
1397 {
1398 val->duration = wake_up_dur.wake_dur;
1399 }
1400
1401 val->sleep.en = wake_up_ths.sleep_on;
1402 val->sleep.duration = wake_up_dur.sleep_dur;
1403
1404 switch (ctrl4.inact_odr)
1405 {
1406 case LIS2DU12_DO_NOT_CHANGE:
1407 val->sleep.odr = LIS2DU12_DO_NOT_CHANGE;
1408 break;
1409 case LIS2DU12_SLEEP_AT_6Hz:
1410 val->sleep.odr = LIS2DU12_SLEEP_AT_6Hz;
1411 break;
1412 case LIS2DU12_SLEEP_AT_3Hz:
1413 val->sleep.odr = LIS2DU12_SLEEP_AT_3Hz;
1414 break;
1415 case LIS2DU12_SLEEP_AT_1Hz6:
1416 val->sleep.odr = LIS2DU12_SLEEP_AT_1Hz6;
1417 break;
1418 default:
1419 val->sleep.odr = LIS2DU12_DO_NOT_CHANGE;
1420 break;
1421 }
1422 return ret;
1423 }
1424
1425 /**
1426 * @}
1427 *
1428 */
1429
1430 /**
1431 * @defgroup Tap functions
1432 * @brief This section groups all the functions concerning
1433 * the single/double tap functionality.
1434 * @{
1435 *
1436 */
1437
1438 /**
1439 * @brief Configuration of Single and Double Tap.[set]
1440 *
1441 * @param ctx communication interface handler.(ptr)
1442 * @param val parameters of configuration.(ptr)
1443 * @retval interface status (MANDATORY: return 0 -> no Error)
1444 *
1445 */
lis2du12_tap_mode_set(const stmdev_ctx_t * ctx,lis2du12_tap_md_t * val)1446 int32_t lis2du12_tap_mode_set(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val)
1447 {
1448 lis2du12_wake_up_ths_t wake_up_ths;
1449 lis2du12_tap_ths_x_t tap_ths_x;
1450 lis2du12_tap_ths_y_t tap_ths_y;
1451 lis2du12_tap_ths_z_t tap_ths_z;
1452 lis2du12_int_dur_t int_dur;
1453 int32_t ret;
1454
1455 ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS,
1456 (uint8_t *)&wake_up_ths, 1);
1457 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X,
1458 (uint8_t *)&tap_ths_x, 1);
1459 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1);
1460 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1);
1461 ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1);
1462
1463 tap_ths_z.tap_z_en = val->z_en;
1464 tap_ths_z.tap_y_en = val->y_en;
1465 tap_ths_z.tap_x_en = val->x_en;
1466
1467 tap_ths_x.tap_ths_x = val->threshold.x;
1468 tap_ths_y.tap_ths_y = val->threshold.y;
1469 tap_ths_z.tap_ths_z = val->threshold.z;
1470
1471 int_dur.shock = val->shock;
1472 int_dur.quiet = val->quiet;
1473
1474 tap_ths_y.tap_priority = (uint8_t)val->priority;
1475
1476 wake_up_ths.single_double_tap = val->tap_double.en;
1477 int_dur.latency = val->tap_double.latency;
1478
1479 ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS,
1480 (uint8_t *)&wake_up_ths, 1);
1481 ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1);
1482 ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1);
1483 ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1);
1484 ret += lis2du12_write_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1);
1485
1486 return ret;
1487 }
1488
1489 /**
1490 * @brief Configuration of Single and Double Tap.[get]
1491 *
1492 * @param ctx communication interface handler.(ptr)
1493 * @param val retrieve the parameters of configuration.(ptr)
1494 * @retval interface status (MANDATORY: return 0 -> no Error)
1495 *
1496 */
lis2du12_tap_mode_get(const stmdev_ctx_t * ctx,lis2du12_tap_md_t * val)1497 int32_t lis2du12_tap_mode_get(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val)
1498 {
1499 lis2du12_wake_up_ths_t wake_up_ths;
1500 lis2du12_tap_ths_x_t tap_ths_x;
1501 lis2du12_tap_ths_y_t tap_ths_y;
1502 lis2du12_tap_ths_z_t tap_ths_z;
1503 lis2du12_int_dur_t int_dur;
1504 int32_t ret;
1505
1506 ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS,
1507 (uint8_t *)&wake_up_ths, 1);
1508 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1);
1509 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1);
1510 ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1);
1511 ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1);
1512
1513 val->z_en = tap_ths_z.tap_z_en;
1514 val->y_en = tap_ths_z.tap_y_en;
1515 val->x_en = tap_ths_z.tap_x_en;
1516
1517 val->threshold.x = tap_ths_x.tap_ths_x;
1518 val->threshold.y = tap_ths_y.tap_ths_y;
1519 val->threshold.z = tap_ths_z.tap_ths_z;
1520
1521 val->shock = int_dur.shock;
1522 val->quiet = int_dur.quiet;
1523
1524 switch (tap_ths_y.tap_priority)
1525 {
1526 case LIS2DU12_XYZ:
1527 val->priority = LIS2DU12_XYZ;
1528 break;
1529 case LIS2DU12_YXZ:
1530 val->priority = LIS2DU12_YXZ;
1531 break;
1532 case LIS2DU12_XZY:
1533 val->priority = LIS2DU12_XZY;
1534 break;
1535 case LIS2DU12_ZYX:
1536 val->priority = LIS2DU12_ZYX;
1537 break;
1538 case LIS2DU12_YZX:
1539 val->priority = LIS2DU12_YZX;
1540 break;
1541 case LIS2DU12_ZXY:
1542 val->priority = LIS2DU12_ZXY;
1543 break;
1544 default:
1545 val->priority = LIS2DU12_XYZ;
1546 break;
1547 }
1548
1549 val->tap_double.en = wake_up_ths.single_double_tap;
1550 val->tap_double.latency = int_dur.latency;
1551
1552 return ret;
1553 }
1554
1555 /**
1556 * @}
1557 *
1558 */
1559
1560 /**
1561 * @defgroup Free Fall Configuration
1562 * @brief This section groups all the functions concerning
1563 * the free fall functionality.
1564 * @{
1565 *
1566 */
1567
1568 /**
1569 * @brief Configuration Free Fall.[set]
1570 *
1571 * @param ctx communication interface handler.(ptr)
1572 * @param val parameters of configuration.(ptr)
1573 * @retval interface status (MANDATORY: return 0 -> no Error)
1574 *
1575 */
lis2du12_free_fall_mode_set(const stmdev_ctx_t * ctx,lis2du12_ff_md_t * val)1576 int32_t lis2du12_free_fall_mode_set(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val)
1577 {
1578 lis2du12_wake_up_dur_t wake_up_dur;
1579 lis2du12_free_fall_t free_fall;
1580 int32_t ret;
1581
1582 ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1583 (uint8_t *)&wake_up_dur, 1);
1584 ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1);
1585
1586 wake_up_dur.ff_dur = val->duration & 0x1FU;
1587 free_fall.ff_dur = (val->duration) & 0x20U >> 5;
1588
1589 free_fall.ff_ths = (uint8_t)val->threshold;
1590
1591 ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1592 (uint8_t *)&wake_up_dur, 1);
1593 ret += lis2du12_write_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1);
1594
1595 return ret;
1596 }
1597
1598 /**
1599 * @brief Configuration Free Fall.[get]
1600 *
1601 * @param ctx communication interface handler.(ptr)
1602 * @param val retrieve the parameters of configuration.(ptr)
1603 * @retval interface status (MANDATORY: return 0 -> no Error)
1604 *
1605 */
lis2du12_free_fall_mode_get(const stmdev_ctx_t * ctx,lis2du12_ff_md_t * val)1606 int32_t lis2du12_free_fall_mode_get(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val)
1607 {
1608 lis2du12_wake_up_dur_t wake_up_dur;
1609 lis2du12_free_fall_t free_fall;
1610 int32_t ret;
1611
1612 ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR,
1613 (uint8_t *)&wake_up_dur, 1);
1614 ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1);
1615
1616 val->duration = (free_fall.ff_dur * 32U) + wake_up_dur.ff_dur;
1617
1618 switch (free_fall.ff_ths)
1619 {
1620 case LIS2DU12_156mg:
1621 val->threshold = LIS2DU12_156mg;
1622 break;
1623 case LIS2DU12_219mg:
1624 val->threshold = LIS2DU12_219mg;
1625 break;
1626 case LIS2DU12_250mg:
1627 val->threshold = LIS2DU12_250mg;
1628 break;
1629 case LIS2DU12_312mg:
1630 val->threshold = LIS2DU12_312mg;
1631 break;
1632 case LIS2DU12_344mg:
1633 val->threshold = LIS2DU12_344mg;
1634 break;
1635 case LIS2DU12_406mg:
1636 val->threshold = LIS2DU12_406mg;
1637 break;
1638 case LIS2DU12_469mg:
1639 val->threshold = LIS2DU12_469mg;
1640 break;
1641 case LIS2DU12_500mg:
1642 val->threshold = LIS2DU12_500mg;
1643 break;
1644 default:
1645 val->threshold = LIS2DU12_156mg;
1646 break;
1647 }
1648
1649 return ret;
1650 }
1651
1652 /**
1653 * @}
1654 *
1655 */
1656
1657 /**
1658 * @defgroup Orientation 6D functions
1659 * @brief This section groups all the functions concerning
1660 * the 6/4D orientation functionality.
1661 * @{
1662 *
1663 */
1664
1665 /**
1666 * @brief Configuration of detection 6D or 4D orientation.[set]
1667 *
1668 * @param ctx communication interface handler.(ptr)
1669 * @param val parameters of configuration.(ptr)
1670 * @retval interface status (MANDATORY: return 0 -> no Error)
1671 *
1672 */
lis2du12_orientation_mode_set(const stmdev_ctx_t * ctx,lis2du12_orient_md_t * val)1673 int32_t lis2du12_orientation_mode_set(const stmdev_ctx_t *ctx,
1674 lis2du12_orient_md_t *val)
1675 {
1676 lis2du12_tap_ths_x_t tap_ths_x;
1677 int32_t ret;
1678
1679 ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1);
1680
1681 tap_ths_x.d6d_ths = (uint8_t)val->threshold;
1682 tap_ths_x.d4d_en = (uint8_t)val->deg_of_freedom;
1683
1684 ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1);
1685
1686 return ret;
1687 }
1688
1689 /**
1690 * @brief Configuration of detection 6D or 4D orientation.[get]
1691 *
1692 * @param ctx communication interface handler.(ptr)
1693 * @param val retrieve the parameters of configuration.(ptr)
1694 * @retval interface status (MANDATORY: return 0 -> no Error)
1695 *
1696 */
lis2du12_orientation_mode_get(const stmdev_ctx_t * ctx,lis2du12_orient_md_t * val)1697 int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx,
1698 lis2du12_orient_md_t *val)
1699 {
1700 lis2du12_tap_ths_x_t tap_ths_x;
1701 int32_t ret;
1702
1703 ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1);
1704
1705 switch (tap_ths_x.d6d_ths)
1706 {
1707 case LIS2DU12_DEG_80:
1708 val->threshold = LIS2DU12_DEG_80;
1709 break;
1710 case LIS2DU12_DEG_70:
1711 val->threshold = LIS2DU12_DEG_70;
1712 break;
1713 case LIS2DU12_DEG_60:
1714 val->threshold = LIS2DU12_DEG_60;
1715 break;
1716 case LIS2DU12_DEG_50:
1717 val->threshold = LIS2DU12_DEG_50;
1718 break;
1719 default:
1720 val->threshold = LIS2DU12_DEG_80;
1721 break;
1722 }
1723
1724 switch (tap_ths_x.d4d_en)
1725 {
1726 case LIS2DU12_SIX:
1727 val->deg_of_freedom = LIS2DU12_SIX;
1728 break;
1729 case LIS2DU12_FOUR:
1730 val->deg_of_freedom = LIS2DU12_FOUR;
1731 break;
1732 default:
1733 val->deg_of_freedom = LIS2DU12_SIX;
1734 break;
1735 }
1736 return ret;
1737
1738 }
1739
1740 /**
1741 * @}
1742 *
1743 */
1744
1745
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