1 /** 2 ****************************************************************************** 3 * @file lis2dh12_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lis2dh12_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LIS2DH12_REGS_H 23 #define LIS2DH12_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LIS2DH12 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 112 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 113 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 114 115 typedef struct 116 { 117 /** Component mandatory fields **/ 118 stmdev_write_ptr write_reg; 119 stmdev_read_ptr read_reg; 120 /** Component optional fields **/ 121 stmdev_mdelay_ptr mdelay; 122 /** Customizable optional pointer **/ 123 void *handle; 124 } stmdev_ctx_t; 125 126 /** 127 * @} 128 * 129 */ 130 131 #endif /* MEMS_SHARED_TYPES */ 132 133 #ifndef MEMS_UCF_SHARED_TYPES 134 #define MEMS_UCF_SHARED_TYPES 135 136 /** @defgroup Generic address-data structure definition 137 * @brief This structure is useful to load a predefined configuration 138 * of a sensor. 139 * You can create a sensor configuration by your own or using 140 * Unico / Unicleo tools available on STMicroelectronics 141 * web site. 142 * 143 * @{ 144 * 145 */ 146 147 typedef struct 148 { 149 uint8_t address; 150 uint8_t data; 151 } ucf_line_t; 152 153 /** 154 * @} 155 * 156 */ 157 158 #endif /* MEMS_UCF_SHARED_TYPES */ 159 160 /** 161 * @} 162 * 163 */ 164 165 /** @defgroup LIS2DH12_Infos 166 * @{ 167 * 168 */ 169 170 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 171 #define LIS2DH12_I2C_ADD_L 0x31U 172 #define LIS2DH12_I2C_ADD_H 0x33U 173 174 /** Device Identification (Who am I) **/ 175 #define LIS2DH12_ID 0x33U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define LIS2DH12_STATUS_REG_AUX 0x07U 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t not_used_01 : 2; 187 uint8_t tda : 1; 188 uint8_t not_used_02 : 3; 189 uint8_t tor : 1; 190 uint8_t not_used_03 : 1; 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t not_used_03 : 1; 193 uint8_t tor : 1; 194 uint8_t not_used_02 : 3; 195 uint8_t tda : 1; 196 uint8_t not_used_01 : 2; 197 #endif /* DRV_BYTE_ORDER */ 198 } lis2dh12_status_reg_aux_t; 199 200 #define LIS2DH12_OUT_TEMP_L 0x0CU 201 #define LIS2DH12_OUT_TEMP_H 0x0DU 202 #define LIS2DH12_WHO_AM_I 0x0FU 203 204 #define LIS2DH12_CTRL_REG0 0x1EU 205 typedef struct 206 { 207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 208 uint8_t not_used_01 : 7; 209 uint8_t sdo_pu_disc : 1; 210 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 211 uint8_t sdo_pu_disc : 1; 212 uint8_t not_used_01 : 7; 213 #endif /* DRV_BYTE_ORDER */ 214 } lis2dh12_ctrl_reg0_t; 215 216 #define LIS2DH12_TEMP_CFG_REG 0x1FU 217 typedef struct 218 { 219 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 220 uint8_t not_used_01 : 6; 221 uint8_t temp_en : 2; 222 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 223 uint8_t temp_en : 2; 224 uint8_t not_used_01 : 6; 225 #endif /* DRV_BYTE_ORDER */ 226 } lis2dh12_temp_cfg_reg_t; 227 228 #define LIS2DH12_CTRL_REG1 0x20U 229 typedef struct 230 { 231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 232 uint8_t xen : 1; 233 uint8_t yen : 1; 234 uint8_t zen : 1; 235 uint8_t lpen : 1; 236 uint8_t odr : 4; 237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 uint8_t odr : 4; 239 uint8_t lpen : 1; 240 uint8_t zen : 1; 241 uint8_t yen : 1; 242 uint8_t xen : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } lis2dh12_ctrl_reg1_t; 245 246 #define LIS2DH12_CTRL_REG2 0x21U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 251 uint8_t fds : 1; 252 uint8_t hpcf : 2; 253 uint8_t hpm : 2; 254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 uint8_t hpm : 2; 256 uint8_t hpcf : 2; 257 uint8_t fds : 1; 258 uint8_t hp : 3; /* HPCLICK + HP_IA2 + HP_IA1 -> HP */ 259 #endif /* DRV_BYTE_ORDER */ 260 } lis2dh12_ctrl_reg2_t; 261 262 #define LIS2DH12_CTRL_REG3 0x22U 263 typedef struct 264 { 265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 266 uint8_t not_used_01 : 1; 267 uint8_t i1_overrun : 1; 268 uint8_t i1_wtm : 1; 269 uint8_t not_used_02 : 1; 270 uint8_t i1_zyxda : 1; 271 uint8_t i1_ia2 : 1; 272 uint8_t i1_ia1 : 1; 273 uint8_t i1_click : 1; 274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 275 uint8_t i1_click : 1; 276 uint8_t i1_ia1 : 1; 277 uint8_t i1_ia2 : 1; 278 uint8_t i1_zyxda : 1; 279 uint8_t not_used_02 : 1; 280 uint8_t i1_wtm : 1; 281 uint8_t i1_overrun : 1; 282 uint8_t not_used_01 : 1; 283 #endif /* DRV_BYTE_ORDER */ 284 } lis2dh12_ctrl_reg3_t; 285 286 #define LIS2DH12_CTRL_REG4 0x23U 287 typedef struct 288 { 289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 290 uint8_t sim : 1; 291 uint8_t st : 2; 292 uint8_t hr : 1; 293 uint8_t fs : 2; 294 uint8_t ble : 1; 295 uint8_t bdu : 1; 296 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 297 uint8_t bdu : 1; 298 uint8_t ble : 1; 299 uint8_t fs : 2; 300 uint8_t hr : 1; 301 uint8_t st : 2; 302 uint8_t sim : 1; 303 #endif /* DRV_BYTE_ORDER */ 304 } lis2dh12_ctrl_reg4_t; 305 306 #define LIS2DH12_CTRL_REG5 0x24U 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t d4d_int2 : 1; 311 uint8_t lir_int2 : 1; 312 uint8_t d4d_int1 : 1; 313 uint8_t lir_int1 : 1; 314 uint8_t not_used_01 : 2; 315 uint8_t fifo_en : 1; 316 uint8_t boot : 1; 317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 318 uint8_t boot : 1; 319 uint8_t fifo_en : 1; 320 uint8_t not_used_01 : 2; 321 uint8_t lir_int1 : 1; 322 uint8_t d4d_int1 : 1; 323 uint8_t lir_int2 : 1; 324 uint8_t d4d_int2 : 1; 325 #endif /* DRV_BYTE_ORDER */ 326 } lis2dh12_ctrl_reg5_t; 327 328 #define LIS2DH12_CTRL_REG6 0x25U 329 typedef struct 330 { 331 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 332 uint8_t not_used_01 : 1; 333 uint8_t int_polarity : 1; 334 uint8_t not_used_02 : 1; 335 uint8_t i2_act : 1; 336 uint8_t i2_boot : 1; 337 uint8_t i2_ia2 : 1; 338 uint8_t i2_ia1 : 1; 339 uint8_t i2_click : 1; 340 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 341 uint8_t i2_click : 1; 342 uint8_t i2_ia1 : 1; 343 uint8_t i2_ia2 : 1; 344 uint8_t i2_boot : 1; 345 uint8_t i2_act : 1; 346 uint8_t not_used_02 : 1; 347 uint8_t int_polarity : 1; 348 uint8_t not_used_01 : 1; 349 #endif /* DRV_BYTE_ORDER */ 350 } lis2dh12_ctrl_reg6_t; 351 352 #define LIS2DH12_REFERENCE 0x26U 353 #define LIS2DH12_STATUS_REG 0x27U 354 typedef struct 355 { 356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 357 uint8_t xda : 1; 358 uint8_t yda : 1; 359 uint8_t zda : 1; 360 uint8_t zyxda : 1; 361 uint8_t _xor : 1; 362 uint8_t yor : 1; 363 uint8_t zor : 1; 364 uint8_t zyxor : 1; 365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 366 uint8_t zyxor : 1; 367 uint8_t zor : 1; 368 uint8_t yor : 1; 369 uint8_t _xor : 1; 370 uint8_t zyxda : 1; 371 uint8_t zda : 1; 372 uint8_t yda : 1; 373 uint8_t xda : 1; 374 #endif /* DRV_BYTE_ORDER */ 375 } lis2dh12_status_reg_t; 376 377 #define LIS2DH12_OUT_X_L 0x28U 378 #define LIS2DH12_OUT_X_H 0x29U 379 #define LIS2DH12_OUT_Y_L 0x2AU 380 #define LIS2DH12_OUT_Y_H 0x2BU 381 #define LIS2DH12_OUT_Z_L 0x2CU 382 #define LIS2DH12_OUT_Z_H 0x2DU 383 #define LIS2DH12_FIFO_CTRL_REG 0x2EU 384 typedef struct 385 { 386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 387 uint8_t fth : 5; 388 uint8_t tr : 1; 389 uint8_t fm : 2; 390 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 391 uint8_t fm : 2; 392 uint8_t tr : 1; 393 uint8_t fth : 5; 394 #endif /* DRV_BYTE_ORDER */ 395 } lis2dh12_fifo_ctrl_reg_t; 396 397 #define LIS2DH12_FIFO_SRC_REG 0x2FU 398 typedef struct 399 { 400 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 401 uint8_t fss : 5; 402 uint8_t empty : 1; 403 uint8_t ovrn_fifo : 1; 404 uint8_t wtm : 1; 405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 406 uint8_t wtm : 1; 407 uint8_t ovrn_fifo : 1; 408 uint8_t empty : 1; 409 uint8_t fss : 5; 410 #endif /* DRV_BYTE_ORDER */ 411 } lis2dh12_fifo_src_reg_t; 412 413 #define LIS2DH12_INT1_CFG 0x30U 414 typedef struct 415 { 416 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 417 uint8_t xlie : 1; 418 uint8_t xhie : 1; 419 uint8_t ylie : 1; 420 uint8_t yhie : 1; 421 uint8_t zlie : 1; 422 uint8_t zhie : 1; 423 uint8_t _6d : 1; 424 uint8_t aoi : 1; 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t aoi : 1; 427 uint8_t _6d : 1; 428 uint8_t zhie : 1; 429 uint8_t zlie : 1; 430 uint8_t yhie : 1; 431 uint8_t ylie : 1; 432 uint8_t xhie : 1; 433 uint8_t xlie : 1; 434 #endif /* DRV_BYTE_ORDER */ 435 } lis2dh12_int1_cfg_t; 436 437 #define LIS2DH12_INT1_SRC 0x31U 438 typedef struct 439 { 440 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 441 uint8_t xl : 1; 442 uint8_t xh : 1; 443 uint8_t yl : 1; 444 uint8_t yh : 1; 445 uint8_t zl : 1; 446 uint8_t zh : 1; 447 uint8_t ia : 1; 448 uint8_t not_used_01 : 1; 449 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 450 uint8_t not_used_01 : 1; 451 uint8_t ia : 1; 452 uint8_t zh : 1; 453 uint8_t zl : 1; 454 uint8_t yh : 1; 455 uint8_t yl : 1; 456 uint8_t xh : 1; 457 uint8_t xl : 1; 458 #endif /* DRV_BYTE_ORDER */ 459 } lis2dh12_int1_src_t; 460 461 #define LIS2DH12_INT1_THS 0x32U 462 typedef struct 463 { 464 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 465 uint8_t ths : 7; 466 uint8_t not_used_01 : 1; 467 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 468 uint8_t not_used_01 : 1; 469 uint8_t ths : 7; 470 #endif /* DRV_BYTE_ORDER */ 471 } lis2dh12_int1_ths_t; 472 473 #define LIS2DH12_INT1_DURATION 0x33U 474 typedef struct 475 { 476 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 477 uint8_t d : 7; 478 uint8_t not_used_01 : 1; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t not_used_01 : 1; 481 uint8_t d : 7; 482 #endif /* DRV_BYTE_ORDER */ 483 } lis2dh12_int1_duration_t; 484 485 #define LIS2DH12_INT2_CFG 0x34U 486 typedef struct 487 { 488 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 489 uint8_t xlie : 1; 490 uint8_t xhie : 1; 491 uint8_t ylie : 1; 492 uint8_t yhie : 1; 493 uint8_t zlie : 1; 494 uint8_t zhie : 1; 495 uint8_t _6d : 1; 496 uint8_t aoi : 1; 497 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 498 uint8_t aoi : 1; 499 uint8_t _6d : 1; 500 uint8_t zhie : 1; 501 uint8_t zlie : 1; 502 uint8_t yhie : 1; 503 uint8_t ylie : 1; 504 uint8_t xhie : 1; 505 uint8_t xlie : 1; 506 #endif /* DRV_BYTE_ORDER */ 507 } lis2dh12_int2_cfg_t; 508 509 #define LIS2DH12_INT2_SRC 0x35U 510 typedef struct 511 { 512 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 513 uint8_t xl : 1; 514 uint8_t xh : 1; 515 uint8_t yl : 1; 516 uint8_t yh : 1; 517 uint8_t zl : 1; 518 uint8_t zh : 1; 519 uint8_t ia : 1; 520 uint8_t not_used_01 : 1; 521 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 522 uint8_t not_used_01 : 1; 523 uint8_t ia : 1; 524 uint8_t zh : 1; 525 uint8_t zl : 1; 526 uint8_t yh : 1; 527 uint8_t yl : 1; 528 uint8_t xh : 1; 529 uint8_t xl : 1; 530 #endif /* DRV_BYTE_ORDER */ 531 } lis2dh12_int2_src_t; 532 533 #define LIS2DH12_INT2_THS 0x36U 534 typedef struct 535 { 536 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 537 uint8_t ths : 7; 538 uint8_t not_used_01 : 1; 539 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 540 uint8_t not_used_01 : 1; 541 uint8_t ths : 7; 542 #endif /* DRV_BYTE_ORDER */ 543 } lis2dh12_int2_ths_t; 544 545 #define LIS2DH12_INT2_DURATION 0x37U 546 typedef struct 547 { 548 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 549 uint8_t d : 7; 550 uint8_t not_used_01 : 1; 551 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 552 uint8_t not_used_01 : 1; 553 uint8_t d : 7; 554 #endif /* DRV_BYTE_ORDER */ 555 } lis2dh12_int2_duration_t; 556 557 #define LIS2DH12_CLICK_CFG 0x38U 558 typedef struct 559 { 560 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 561 uint8_t xs : 1; 562 uint8_t xd : 1; 563 uint8_t ys : 1; 564 uint8_t yd : 1; 565 uint8_t zs : 1; 566 uint8_t zd : 1; 567 uint8_t not_used_01 : 2; 568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 uint8_t not_used_01 : 2; 570 uint8_t zd : 1; 571 uint8_t zs : 1; 572 uint8_t yd : 1; 573 uint8_t ys : 1; 574 uint8_t xd : 1; 575 uint8_t xs : 1; 576 #endif /* DRV_BYTE_ORDER */ 577 } lis2dh12_click_cfg_t; 578 579 #define LIS2DH12_CLICK_SRC 0x39U 580 typedef struct 581 { 582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 583 uint8_t x : 1; 584 uint8_t y : 1; 585 uint8_t z : 1; 586 uint8_t sign : 1; 587 uint8_t sclick : 1; 588 uint8_t dclick : 1; 589 uint8_t ia : 1; 590 uint8_t not_used_01 : 1; 591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 uint8_t not_used_01 : 1; 593 uint8_t ia : 1; 594 uint8_t dclick : 1; 595 uint8_t sclick : 1; 596 uint8_t sign : 1; 597 uint8_t z : 1; 598 uint8_t y : 1; 599 uint8_t x : 1; 600 #endif /* DRV_BYTE_ORDER */ 601 } lis2dh12_click_src_t; 602 603 #define LIS2DH12_CLICK_THS 0x3AU 604 typedef struct 605 { 606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 607 uint8_t ths : 7; 608 uint8_t lir_click : 1; 609 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 610 uint8_t lir_click : 1; 611 uint8_t ths : 7; 612 #endif /* DRV_BYTE_ORDER */ 613 } lis2dh12_click_ths_t; 614 615 #define LIS2DH12_TIME_LIMIT 0x3BU 616 typedef struct 617 { 618 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 619 uint8_t tli : 7; 620 uint8_t not_used_01 : 1; 621 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 622 uint8_t not_used_01 : 1; 623 uint8_t tli : 7; 624 #endif /* DRV_BYTE_ORDER */ 625 } lis2dh12_time_limit_t; 626 627 #define LIS2DH12_TIME_LATENCY 0x3CU 628 typedef struct 629 { 630 uint8_t tla : 8; 631 } lis2dh12_time_latency_t; 632 633 #define LIS2DH12_TIME_WINDOW 0x3DU 634 typedef struct 635 { 636 uint8_t tw : 8; 637 } lis2dh12_time_window_t; 638 639 #define LIS2DH12_ACT_THS 0x3EU 640 typedef struct 641 { 642 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 643 uint8_t acth : 7; 644 uint8_t not_used_01 : 1; 645 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 646 uint8_t not_used_01 : 1; 647 uint8_t acth : 7; 648 #endif /* DRV_BYTE_ORDER */ 649 } lis2dh12_act_ths_t; 650 651 #define LIS2DH12_ACT_DUR 0x3FU 652 typedef struct 653 { 654 uint8_t actd : 8; 655 } lis2dh12_act_dur_t; 656 657 /** 658 * @defgroup LIS2DH12_Register_Union 659 * @brief This union group all the registers having a bit-field 660 * description. 661 * This union is useful but it's not needed by the driver. 662 * 663 * REMOVING this union you are compliant with: 664 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 665 * 666 * @{ 667 * 668 */ 669 typedef union 670 { 671 lis2dh12_status_reg_aux_t status_reg_aux; 672 lis2dh12_ctrl_reg0_t ctrl_reg0; 673 lis2dh12_temp_cfg_reg_t temp_cfg_reg; 674 lis2dh12_ctrl_reg1_t ctrl_reg1; 675 lis2dh12_ctrl_reg2_t ctrl_reg2; 676 lis2dh12_ctrl_reg3_t ctrl_reg3; 677 lis2dh12_ctrl_reg4_t ctrl_reg4; 678 lis2dh12_ctrl_reg5_t ctrl_reg5; 679 lis2dh12_ctrl_reg6_t ctrl_reg6; 680 lis2dh12_status_reg_t status_reg; 681 lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; 682 lis2dh12_fifo_src_reg_t fifo_src_reg; 683 lis2dh12_int1_cfg_t int1_cfg; 684 lis2dh12_int1_src_t int1_src; 685 lis2dh12_int1_ths_t int1_ths; 686 lis2dh12_int1_duration_t int1_duration; 687 lis2dh12_int2_cfg_t int2_cfg; 688 lis2dh12_int2_src_t int2_src; 689 lis2dh12_int2_ths_t int2_ths; 690 lis2dh12_int2_duration_t int2_duration; 691 lis2dh12_click_cfg_t click_cfg; 692 lis2dh12_click_src_t click_src; 693 lis2dh12_click_ths_t click_ths; 694 lis2dh12_time_limit_t time_limit; 695 lis2dh12_time_latency_t time_latency; 696 lis2dh12_time_window_t time_window; 697 lis2dh12_act_ths_t act_ths; 698 lis2dh12_act_dur_t act_dur; 699 bitwise_t bitwise; 700 uint8_t byte; 701 } lis2dh12_reg_t; 702 703 /** 704 * @} 705 * 706 */ 707 708 #ifndef __weak 709 #define __weak __attribute__((weak)) 710 #endif /* __weak */ 711 712 /* 713 * These are the basic platform dependent I/O routines to read 714 * and write device registers connected on a standard bus. 715 * The driver keeps offering a default implementation based on function 716 * pointers to read/write routines for backward compatibility. 717 * The __weak directive allows the final application to overwrite 718 * them with a custom implementation. 719 */ 720 721 int32_t lis2dh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 722 uint8_t *data, 723 uint16_t len); 724 int32_t lis2dh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 725 uint8_t *data, 726 uint16_t len); 727 728 float_t lis2dh12_from_fs2_hr_to_mg(int16_t lsb); 729 float_t lis2dh12_from_fs4_hr_to_mg(int16_t lsb); 730 float_t lis2dh12_from_fs8_hr_to_mg(int16_t lsb); 731 float_t lis2dh12_from_fs16_hr_to_mg(int16_t lsb); 732 float_t lis2dh12_from_lsb_hr_to_celsius(int16_t lsb); 733 734 float_t lis2dh12_from_fs2_nm_to_mg(int16_t lsb); 735 float_t lis2dh12_from_fs4_nm_to_mg(int16_t lsb); 736 float_t lis2dh12_from_fs8_nm_to_mg(int16_t lsb); 737 float_t lis2dh12_from_fs16_nm_to_mg(int16_t lsb); 738 float_t lis2dh12_from_lsb_nm_to_celsius(int16_t lsb); 739 740 float_t lis2dh12_from_fs2_lp_to_mg(int16_t lsb); 741 float_t lis2dh12_from_fs4_lp_to_mg(int16_t lsb); 742 float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb); 743 float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb); 744 float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb); 745 746 int32_t lis2dh12_temp_status_reg_get(const stmdev_ctx_t *ctx, 747 uint8_t *buff); 748 int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 749 750 int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 751 752 int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 753 754 typedef enum 755 { 756 LIS2DH12_TEMP_DISABLE = 0, 757 LIS2DH12_TEMP_ENABLE = 3, 758 } lis2dh12_temp_en_t; 759 int32_t lis2dh12_temperature_meas_set(const stmdev_ctx_t *ctx, 760 lis2dh12_temp_en_t val); 761 int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, 762 lis2dh12_temp_en_t *val); 763 764 typedef enum 765 { 766 LIS2DH12_HR_12bit = 0, 767 LIS2DH12_NM_10bit = 1, 768 LIS2DH12_LP_8bit = 2, 769 } lis2dh12_op_md_t; 770 int32_t lis2dh12_operating_mode_set(const stmdev_ctx_t *ctx, 771 lis2dh12_op_md_t val); 772 int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, 773 lis2dh12_op_md_t *val); 774 775 typedef enum 776 { 777 LIS2DH12_POWER_DOWN = 0x00, 778 LIS2DH12_ODR_1Hz = 0x01, 779 LIS2DH12_ODR_10Hz = 0x02, 780 LIS2DH12_ODR_25Hz = 0x03, 781 LIS2DH12_ODR_50Hz = 0x04, 782 LIS2DH12_ODR_100Hz = 0x05, 783 LIS2DH12_ODR_200Hz = 0x06, 784 LIS2DH12_ODR_400Hz = 0x07, 785 LIS2DH12_ODR_1kHz620_LP = 0x08, 786 LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 787 } lis2dh12_odr_t; 788 int32_t lis2dh12_data_rate_set(const stmdev_ctx_t *ctx, lis2dh12_odr_t val); 789 int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, 790 lis2dh12_odr_t *val); 791 792 int32_t lis2dh12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, 793 uint8_t val); 794 int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, 795 uint8_t *val); 796 797 typedef enum 798 { 799 LIS2DH12_AGGRESSIVE = 0, 800 LIS2DH12_STRONG = 1, 801 LIS2DH12_MEDIUM = 2, 802 LIS2DH12_LIGHT = 3, 803 } lis2dh12_hpcf_t; 804 int32_t lis2dh12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, 805 lis2dh12_hpcf_t val); 806 int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, 807 lis2dh12_hpcf_t *val); 808 809 typedef enum 810 { 811 LIS2DH12_NORMAL_WITH_RST = 0, 812 LIS2DH12_REFERENCE_MODE = 1, 813 LIS2DH12_NORMAL = 2, 814 LIS2DH12_AUTORST_ON_INT = 3, 815 } lis2dh12_hpm_t; 816 int32_t lis2dh12_high_pass_mode_set(const stmdev_ctx_t *ctx, 817 lis2dh12_hpm_t val); 818 int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, 819 lis2dh12_hpm_t *val); 820 821 typedef enum 822 { 823 LIS2DH12_2g = 0, 824 LIS2DH12_4g = 1, 825 LIS2DH12_8g = 2, 826 LIS2DH12_16g = 3, 827 } lis2dh12_fs_t; 828 int32_t lis2dh12_full_scale_set(const stmdev_ctx_t *ctx, lis2dh12_fs_t val); 829 int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, 830 lis2dh12_fs_t *val); 831 832 int32_t lis2dh12_block_data_update_set(const stmdev_ctx_t *ctx, 833 uint8_t val); 834 int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, 835 uint8_t *val); 836 837 int32_t lis2dh12_filter_reference_set(const stmdev_ctx_t *ctx, 838 uint8_t *buff); 839 int32_t lis2dh12_filter_reference_get(const stmdev_ctx_t *ctx, 840 uint8_t *buff); 841 842 int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 843 844 int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 845 846 int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, 847 int16_t *val); 848 849 int32_t lis2dh12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 850 851 typedef enum 852 { 853 LIS2DH12_ST_DISABLE = 0, 854 LIS2DH12_ST_POSITIVE = 1, 855 LIS2DH12_ST_NEGATIVE = 2, 856 } lis2dh12_st_t; 857 int32_t lis2dh12_self_test_set(const stmdev_ctx_t *ctx, lis2dh12_st_t val); 858 int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val); 859 860 typedef enum 861 { 862 LIS2DH12_LSB_AT_LOW_ADD = 0, 863 LIS2DH12_MSB_AT_LOW_ADD = 1, 864 } lis2dh12_ble_t; 865 int32_t lis2dh12_data_format_set(const stmdev_ctx_t *ctx, 866 lis2dh12_ble_t val); 867 int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, 868 lis2dh12_ble_t *val); 869 870 int32_t lis2dh12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 871 int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 872 873 int32_t lis2dh12_status_get(const stmdev_ctx_t *ctx, 874 lis2dh12_status_reg_t *val); 875 876 int32_t lis2dh12_int1_gen_conf_set(const stmdev_ctx_t *ctx, 877 lis2dh12_int1_cfg_t *val); 878 int32_t lis2dh12_int1_gen_conf_get(const stmdev_ctx_t *ctx, 879 lis2dh12_int1_cfg_t *val); 880 881 int32_t lis2dh12_int1_gen_source_get(const stmdev_ctx_t *ctx, 882 lis2dh12_int1_src_t *val); 883 884 int32_t lis2dh12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, 885 uint8_t val); 886 int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, 887 uint8_t *val); 888 889 int32_t lis2dh12_int1_gen_duration_set(const stmdev_ctx_t *ctx, 890 uint8_t val); 891 int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, 892 uint8_t *val); 893 894 int32_t lis2dh12_int2_gen_conf_set(const stmdev_ctx_t *ctx, 895 lis2dh12_int2_cfg_t *val); 896 int32_t lis2dh12_int2_gen_conf_get(const stmdev_ctx_t *ctx, 897 lis2dh12_int2_cfg_t *val); 898 899 int32_t lis2dh12_int2_gen_source_get(const stmdev_ctx_t *ctx, 900 lis2dh12_int2_src_t *val); 901 902 int32_t lis2dh12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, 903 uint8_t val); 904 int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, 905 uint8_t *val); 906 907 int32_t lis2dh12_int2_gen_duration_set(const stmdev_ctx_t *ctx, 908 uint8_t val); 909 int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, 910 uint8_t *val); 911 912 typedef enum 913 { 914 LIS2DH12_DISC_FROM_INT_GENERATOR = 0, 915 LIS2DH12_ON_INT1_GEN = 1, 916 LIS2DH12_ON_INT2_GEN = 2, 917 LIS2DH12_ON_TAP_GEN = 4, 918 LIS2DH12_ON_INT1_INT2_GEN = 3, 919 LIS2DH12_ON_INT1_TAP_GEN = 5, 920 LIS2DH12_ON_INT2_TAP_GEN = 6, 921 LIS2DH12_ON_INT1_INT2_TAP_GEN = 7, 922 } lis2dh12_hp_t; 923 int32_t lis2dh12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, 924 lis2dh12_hp_t val); 925 int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, 926 lis2dh12_hp_t *val); 927 928 int32_t lis2dh12_pin_int1_config_set(const stmdev_ctx_t *ctx, 929 lis2dh12_ctrl_reg3_t *val); 930 int32_t lis2dh12_pin_int1_config_get(const stmdev_ctx_t *ctx, 931 lis2dh12_ctrl_reg3_t *val); 932 933 int32_t lis2dh12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, 934 uint8_t val); 935 int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, 936 uint8_t *val); 937 938 typedef enum 939 { 940 LIS2DH12_INT2_PULSED = 0, 941 LIS2DH12_INT2_LATCHED = 1, 942 } lis2dh12_lir_int2_t; 943 int32_t lis2dh12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, 944 lis2dh12_lir_int2_t val); 945 int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, 946 lis2dh12_lir_int2_t *val); 947 948 int32_t lis2dh12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, 949 uint8_t val); 950 int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, 951 uint8_t *val); 952 953 typedef enum 954 { 955 LIS2DH12_INT1_PULSED = 0, 956 LIS2DH12_INT1_LATCHED = 1, 957 } lis2dh12_lir_int1_t; 958 int32_t lis2dh12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, 959 lis2dh12_lir_int1_t val); 960 int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, 961 lis2dh12_lir_int1_t *val); 962 963 int32_t lis2dh12_pin_int2_config_set(const stmdev_ctx_t *ctx, 964 lis2dh12_ctrl_reg6_t *val); 965 int32_t lis2dh12_pin_int2_config_get(const stmdev_ctx_t *ctx, 966 lis2dh12_ctrl_reg6_t *val); 967 968 int32_t lis2dh12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 969 int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 970 971 int32_t lis2dh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 972 int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 973 974 typedef enum 975 { 976 LIS2DH12_INT1_GEN = 0, 977 LIS2DH12_INT2_GEN = 1, 978 } lis2dh12_tr_t; 979 int32_t lis2dh12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, 980 lis2dh12_tr_t val); 981 int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, 982 lis2dh12_tr_t *val); 983 984 typedef enum 985 { 986 LIS2DH12_BYPASS_MODE = 0, 987 LIS2DH12_FIFO_MODE = 1, 988 LIS2DH12_DYNAMIC_STREAM_MODE = 2, 989 LIS2DH12_STREAM_TO_FIFO_MODE = 3, 990 } lis2dh12_fm_t; 991 int32_t lis2dh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dh12_fm_t val); 992 int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val); 993 994 int32_t lis2dh12_fifo_status_get(const stmdev_ctx_t *ctx, 995 lis2dh12_fifo_src_reg_t *val); 996 997 int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 998 999 int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1000 1001 int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1002 1003 int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1004 1005 int32_t lis2dh12_tap_conf_set(const stmdev_ctx_t *ctx, 1006 lis2dh12_click_cfg_t *val); 1007 int32_t lis2dh12_tap_conf_get(const stmdev_ctx_t *ctx, 1008 lis2dh12_click_cfg_t *val); 1009 1010 int32_t lis2dh12_tap_source_get(const stmdev_ctx_t *ctx, 1011 lis2dh12_click_src_t *val); 1012 1013 int32_t lis2dh12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1014 int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1015 1016 typedef enum 1017 { 1018 LIS2DH12_TAP_PULSED = 0, 1019 LIS2DH12_TAP_LATCHED = 1, 1020 } lis2dh12_lir_click_t; 1021 int32_t lis2dh12_tap_notification_mode_set(const stmdev_ctx_t *ctx, 1022 lis2dh12_lir_click_t val); 1023 int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, 1024 lis2dh12_lir_click_t *val); 1025 1026 int32_t lis2dh12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1027 int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1028 1029 int32_t lis2dh12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1030 int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1031 1032 int32_t lis2dh12_double_tap_timeout_set(const stmdev_ctx_t *ctx, 1033 uint8_t val); 1034 int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, 1035 uint8_t *val); 1036 1037 int32_t lis2dh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1038 int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1039 1040 int32_t lis2dh12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 1041 int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 1042 1043 typedef enum 1044 { 1045 LIS2DH12_PULL_UP_CONNECT = 0, 1046 LIS2DH12_PULL_UP_DISCONNECT = 1, 1047 } lis2dh12_sdo_pu_disc_t; 1048 int32_t lis2dh12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 1049 lis2dh12_sdo_pu_disc_t val); 1050 int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 1051 lis2dh12_sdo_pu_disc_t *val); 1052 1053 typedef enum 1054 { 1055 LIS2DH12_SPI_4_WIRE = 0, 1056 LIS2DH12_SPI_3_WIRE = 1, 1057 } lis2dh12_sim_t; 1058 int32_t lis2dh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sim_t val); 1059 int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val); 1060 1061 /** 1062 * @} 1063 * 1064 */ 1065 1066 #ifdef __cplusplus 1067 } 1068 #endif 1069 1070 #endif /* LIS2DH12_REGS_H */ 1071 1072 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1073
